From ff74a74a7c0535a51d677c36fd6a37c34d30ea38 Mon Sep 17 00:00:00 2001 From: David Srbecky Date: Thu, 6 Sep 2018 11:30:36 +0100 Subject: [PATCH 1/4] Rewrite the mterp code generator and the template snippets. This changes the code generation, but the generated assembly files are unchanged (except for some whitespace differences). This replaces the custom template meta-language with python. All the architecture-specific template files are concatenated to create one big python script. This generated python script is then executed to produced the final assembly file. The template syntax is: * Lines starting with % are python code. They will be copied as-is to the script (without the %) and thus executed during the generation. * Other lines are text, and they are essentially syntax sugar for out.write('''(line text)''') and thus they write the main output. * Within a text line, $ can be used insert variables from code. This makes the code generation simpler and it will make it possible to use full power of python within the snippets to simplify code. Test: test-art-host-gtest Change-Id: I8325ca406b328f82163241b3d698f94de5e38bff --- runtime/interpreter/mterp/Makefile_mterp | 49 - runtime/interpreter/mterp/README.txt | 144 +-- runtime/interpreter/mterp/arm/alt_stub.S | 1 + runtime/interpreter/mterp/arm/bincmp.S | 1 + runtime/interpreter/mterp/arm/binop.S | 2 +- runtime/interpreter/mterp/arm/binop2addr.S | 2 +- runtime/interpreter/mterp/arm/binopLit16.S | 2 +- runtime/interpreter/mterp/arm/binopLit8.S | 2 +- runtime/interpreter/mterp/arm/binopWide.S | 2 +- .../interpreter/mterp/arm/binopWide2addr.S | 2 +- runtime/interpreter/mterp/arm/const.S | 2 +- runtime/interpreter/mterp/arm/entry.S | 1 + runtime/interpreter/mterp/arm/fallback.S | 1 + runtime/interpreter/mterp/arm/fbinop.S | 1 + runtime/interpreter/mterp/arm/fbinop2addr.S | 1 + runtime/interpreter/mterp/arm/fbinopWide.S | 1 + .../interpreter/mterp/arm/fbinopWide2addr.S | 1 + runtime/interpreter/mterp/arm/field.S | 2 +- runtime/interpreter/mterp/arm/footer.S | 1 + runtime/interpreter/mterp/arm/funop.S | 1 + runtime/interpreter/mterp/arm/funopNarrower.S | 1 + runtime/interpreter/mterp/arm/funopWider.S | 1 + runtime/interpreter/mterp/arm/header.S | 1 + .../interpreter/mterp/arm/instruction_end.S | 1 + .../mterp/arm/instruction_end_alt.S | 1 + .../mterp/arm/instruction_end_sister.S | 1 + .../interpreter/mterp/arm/instruction_start.S | 1 + .../mterp/arm/instruction_start_alt.S | 1 + .../mterp/arm/instruction_start_sister.S | 1 + runtime/interpreter/mterp/arm/invoke.S | 2 +- .../mterp/arm/invoke_polymorphic.S | 2 +- runtime/interpreter/mterp/arm/op_add_double.S | 3 +- .../mterp/arm/op_add_double_2addr.S | 3 +- runtime/interpreter/mterp/arm/op_add_float.S | 3 +- .../mterp/arm/op_add_float_2addr.S | 3 +- runtime/interpreter/mterp/arm/op_add_int.S | 3 +- .../interpreter/mterp/arm/op_add_int_2addr.S | 3 +- .../interpreter/mterp/arm/op_add_int_lit16.S | 3 +- .../interpreter/mterp/arm/op_add_int_lit8.S | 3 +- runtime/interpreter/mterp/arm/op_add_long.S | 3 +- .../interpreter/mterp/arm/op_add_long_2addr.S | 3 +- runtime/interpreter/mterp/arm/op_aget.S | 2 +- .../interpreter/mterp/arm/op_aget_boolean.S | 3 +- runtime/interpreter/mterp/arm/op_aget_byte.S | 3 +- runtime/interpreter/mterp/arm/op_aget_char.S | 3 +- .../interpreter/mterp/arm/op_aget_object.S | 1 + runtime/interpreter/mterp/arm/op_aget_short.S | 3 +- runtime/interpreter/mterp/arm/op_aget_wide.S | 1 + runtime/interpreter/mterp/arm/op_and_int.S | 3 +- .../interpreter/mterp/arm/op_and_int_2addr.S | 3 +- .../interpreter/mterp/arm/op_and_int_lit16.S | 3 +- .../interpreter/mterp/arm/op_and_int_lit8.S | 3 +- runtime/interpreter/mterp/arm/op_and_long.S | 3 +- .../interpreter/mterp/arm/op_and_long_2addr.S | 3 +- runtime/interpreter/mterp/arm/op_aput.S | 2 +- .../interpreter/mterp/arm/op_aput_boolean.S | 3 +- runtime/interpreter/mterp/arm/op_aput_byte.S | 3 +- runtime/interpreter/mterp/arm/op_aput_char.S | 3 +- .../interpreter/mterp/arm/op_aput_object.S | 1 + runtime/interpreter/mterp/arm/op_aput_short.S | 3 +- runtime/interpreter/mterp/arm/op_aput_wide.S | 1 + .../interpreter/mterp/arm/op_array_length.S | 1 + runtime/interpreter/mterp/arm/op_check_cast.S | 1 + runtime/interpreter/mterp/arm/op_cmp_long.S | 1 + .../interpreter/mterp/arm/op_cmpg_double.S | 1 + runtime/interpreter/mterp/arm/op_cmpg_float.S | 1 + .../interpreter/mterp/arm/op_cmpl_double.S | 1 + runtime/interpreter/mterp/arm/op_cmpl_float.S | 1 + runtime/interpreter/mterp/arm/op_const.S | 1 + runtime/interpreter/mterp/arm/op_const_16.S | 1 + runtime/interpreter/mterp/arm/op_const_4.S | 1 + .../interpreter/mterp/arm/op_const_class.S | 3 +- .../interpreter/mterp/arm/op_const_high16.S | 1 + .../mterp/arm/op_const_method_handle.S | 3 +- .../mterp/arm/op_const_method_type.S | 3 +- .../interpreter/mterp/arm/op_const_string.S | 3 +- .../mterp/arm/op_const_string_jumbo.S | 1 + runtime/interpreter/mterp/arm/op_const_wide.S | 1 + .../interpreter/mterp/arm/op_const_wide_16.S | 1 + .../interpreter/mterp/arm/op_const_wide_32.S | 1 + .../mterp/arm/op_const_wide_high16.S | 1 + runtime/interpreter/mterp/arm/op_div_double.S | 3 +- .../mterp/arm/op_div_double_2addr.S | 3 +- runtime/interpreter/mterp/arm/op_div_float.S | 3 +- .../mterp/arm/op_div_float_2addr.S | 3 +- runtime/interpreter/mterp/arm/op_div_int.S | 2 +- .../interpreter/mterp/arm/op_div_int_2addr.S | 2 +- .../interpreter/mterp/arm/op_div_int_lit16.S | 2 +- .../interpreter/mterp/arm/op_div_int_lit8.S | 2 +- runtime/interpreter/mterp/arm/op_div_long.S | 3 +- .../interpreter/mterp/arm/op_div_long_2addr.S | 3 +- .../mterp/arm/op_double_to_float.S | 3 +- .../interpreter/mterp/arm/op_double_to_int.S | 3 +- .../interpreter/mterp/arm/op_double_to_long.S | 5 +- .../mterp/arm/op_fill_array_data.S | 1 + .../mterp/arm/op_filled_new_array.S | 2 +- .../mterp/arm/op_filled_new_array_range.S | 3 +- .../mterp/arm/op_float_to_double.S | 3 +- .../interpreter/mterp/arm/op_float_to_int.S | 3 +- .../interpreter/mterp/arm/op_float_to_long.S | 5 +- runtime/interpreter/mterp/arm/op_goto.S | 1 + runtime/interpreter/mterp/arm/op_goto_16.S | 1 + runtime/interpreter/mterp/arm/op_goto_32.S | 1 + runtime/interpreter/mterp/arm/op_if_eq.S | 3 +- runtime/interpreter/mterp/arm/op_if_eqz.S | 3 +- runtime/interpreter/mterp/arm/op_if_ge.S | 3 +- runtime/interpreter/mterp/arm/op_if_gez.S | 3 +- runtime/interpreter/mterp/arm/op_if_gt.S | 3 +- runtime/interpreter/mterp/arm/op_if_gtz.S | 3 +- runtime/interpreter/mterp/arm/op_if_le.S | 3 +- runtime/interpreter/mterp/arm/op_if_lez.S | 3 +- runtime/interpreter/mterp/arm/op_if_lt.S | 3 +- runtime/interpreter/mterp/arm/op_if_ltz.S | 3 +- runtime/interpreter/mterp/arm/op_if_ne.S | 3 +- runtime/interpreter/mterp/arm/op_if_nez.S | 3 +- runtime/interpreter/mterp/arm/op_iget.S | 4 +- .../interpreter/mterp/arm/op_iget_boolean.S | 3 +- .../mterp/arm/op_iget_boolean_quick.S | 3 +- runtime/interpreter/mterp/arm/op_iget_byte.S | 3 +- .../mterp/arm/op_iget_byte_quick.S | 3 +- runtime/interpreter/mterp/arm/op_iget_char.S | 3 +- .../mterp/arm/op_iget_char_quick.S | 3 +- .../interpreter/mterp/arm/op_iget_object.S | 3 +- .../mterp/arm/op_iget_object_quick.S | 1 + runtime/interpreter/mterp/arm/op_iget_quick.S | 2 +- runtime/interpreter/mterp/arm/op_iget_short.S | 3 +- .../mterp/arm/op_iget_short_quick.S | 3 +- runtime/interpreter/mterp/arm/op_iget_wide.S | 3 +- .../mterp/arm/op_iget_wide_quick.S | 1 + .../interpreter/mterp/arm/op_instance_of.S | 1 + .../interpreter/mterp/arm/op_int_to_byte.S | 3 +- .../interpreter/mterp/arm/op_int_to_char.S | 3 +- .../interpreter/mterp/arm/op_int_to_double.S | 3 +- .../interpreter/mterp/arm/op_int_to_float.S | 3 +- .../interpreter/mterp/arm/op_int_to_long.S | 3 +- .../interpreter/mterp/arm/op_int_to_short.S | 3 +- .../interpreter/mterp/arm/op_invoke_custom.S | 3 +- .../mterp/arm/op_invoke_custom_range.S | 3 +- .../interpreter/mterp/arm/op_invoke_direct.S | 3 +- .../mterp/arm/op_invoke_direct_range.S | 3 +- .../mterp/arm/op_invoke_interface.S | 3 +- .../mterp/arm/op_invoke_interface_range.S | 3 +- .../mterp/arm/op_invoke_polymorphic.S | 3 +- .../mterp/arm/op_invoke_polymorphic_range.S | 3 +- .../interpreter/mterp/arm/op_invoke_static.S | 3 +- .../mterp/arm/op_invoke_static_range.S | 3 +- .../interpreter/mterp/arm/op_invoke_super.S | 3 +- .../mterp/arm/op_invoke_super_range.S | 3 +- .../interpreter/mterp/arm/op_invoke_virtual.S | 3 +- .../mterp/arm/op_invoke_virtual_quick.S | 3 +- .../mterp/arm/op_invoke_virtual_range.S | 3 +- .../mterp/arm/op_invoke_virtual_range_quick.S | 3 +- runtime/interpreter/mterp/arm/op_iput.S | 4 +- .../interpreter/mterp/arm/op_iput_boolean.S | 3 +- .../mterp/arm/op_iput_boolean_quick.S | 3 +- runtime/interpreter/mterp/arm/op_iput_byte.S | 3 +- .../mterp/arm/op_iput_byte_quick.S | 3 +- runtime/interpreter/mterp/arm/op_iput_char.S | 3 +- .../mterp/arm/op_iput_char_quick.S | 3 +- .../interpreter/mterp/arm/op_iput_object.S | 3 +- .../mterp/arm/op_iput_object_quick.S | 1 + runtime/interpreter/mterp/arm/op_iput_quick.S | 2 +- runtime/interpreter/mterp/arm/op_iput_short.S | 3 +- .../mterp/arm/op_iput_short_quick.S | 3 +- runtime/interpreter/mterp/arm/op_iput_wide.S | 3 +- .../mterp/arm/op_iput_wide_quick.S | 1 + .../interpreter/mterp/arm/op_long_to_double.S | 2 +- .../interpreter/mterp/arm/op_long_to_float.S | 3 +- .../interpreter/mterp/arm/op_long_to_int.S | 3 +- .../interpreter/mterp/arm/op_monitor_enter.S | 1 + .../interpreter/mterp/arm/op_monitor_exit.S | 1 + runtime/interpreter/mterp/arm/op_move.S | 2 +- runtime/interpreter/mterp/arm/op_move_16.S | 2 +- .../interpreter/mterp/arm/op_move_exception.S | 1 + .../interpreter/mterp/arm/op_move_from16.S | 2 +- .../interpreter/mterp/arm/op_move_object.S | 3 +- .../interpreter/mterp/arm/op_move_object_16.S | 3 +- .../mterp/arm/op_move_object_from16.S | 3 +- .../interpreter/mterp/arm/op_move_result.S | 2 +- .../mterp/arm/op_move_result_object.S | 3 +- .../mterp/arm/op_move_result_wide.S | 1 + runtime/interpreter/mterp/arm/op_move_wide.S | 1 + .../interpreter/mterp/arm/op_move_wide_16.S | 1 + .../mterp/arm/op_move_wide_from16.S | 1 + runtime/interpreter/mterp/arm/op_mul_double.S | 3 +- .../mterp/arm/op_mul_double_2addr.S | 3 +- runtime/interpreter/mterp/arm/op_mul_float.S | 3 +- .../mterp/arm/op_mul_float_2addr.S | 3 +- runtime/interpreter/mterp/arm/op_mul_int.S | 3 +- .../interpreter/mterp/arm/op_mul_int_2addr.S | 3 +- .../interpreter/mterp/arm/op_mul_int_lit16.S | 3 +- .../interpreter/mterp/arm/op_mul_int_lit8.S | 3 +- runtime/interpreter/mterp/arm/op_mul_long.S | 1 + .../interpreter/mterp/arm/op_mul_long_2addr.S | 1 + runtime/interpreter/mterp/arm/op_neg_double.S | 3 +- runtime/interpreter/mterp/arm/op_neg_float.S | 3 +- runtime/interpreter/mterp/arm/op_neg_int.S | 3 +- runtime/interpreter/mterp/arm/op_neg_long.S | 3 +- runtime/interpreter/mterp/arm/op_new_array.S | 1 + .../interpreter/mterp/arm/op_new_instance.S | 1 + runtime/interpreter/mterp/arm/op_nop.S | 1 + runtime/interpreter/mterp/arm/op_not_int.S | 3 +- runtime/interpreter/mterp/arm/op_not_long.S | 3 +- runtime/interpreter/mterp/arm/op_or_int.S | 3 +- .../interpreter/mterp/arm/op_or_int_2addr.S | 3 +- .../interpreter/mterp/arm/op_or_int_lit16.S | 3 +- .../interpreter/mterp/arm/op_or_int_lit8.S | 3 +- runtime/interpreter/mterp/arm/op_or_long.S | 3 +- .../interpreter/mterp/arm/op_or_long_2addr.S | 3 +- .../interpreter/mterp/arm/op_packed_switch.S | 2 +- runtime/interpreter/mterp/arm/op_rem_double.S | 3 +- .../mterp/arm/op_rem_double_2addr.S | 3 +- runtime/interpreter/mterp/arm/op_rem_float.S | 3 +- .../mterp/arm/op_rem_float_2addr.S | 3 +- runtime/interpreter/mterp/arm/op_rem_int.S | 2 +- .../interpreter/mterp/arm/op_rem_int_2addr.S | 2 +- .../interpreter/mterp/arm/op_rem_int_lit16.S | 2 +- .../interpreter/mterp/arm/op_rem_int_lit8.S | 2 +- runtime/interpreter/mterp/arm/op_rem_long.S | 3 +- .../interpreter/mterp/arm/op_rem_long_2addr.S | 3 +- runtime/interpreter/mterp/arm/op_return.S | 1 + .../interpreter/mterp/arm/op_return_object.S | 3 +- .../interpreter/mterp/arm/op_return_void.S | 1 + .../mterp/arm/op_return_void_no_barrier.S | 1 + .../interpreter/mterp/arm/op_return_wide.S | 1 + runtime/interpreter/mterp/arm/op_rsub_int.S | 3 +- .../interpreter/mterp/arm/op_rsub_int_lit8.S | 3 +- runtime/interpreter/mterp/arm/op_sget.S | 4 +- .../interpreter/mterp/arm/op_sget_boolean.S | 3 +- runtime/interpreter/mterp/arm/op_sget_byte.S | 3 +- runtime/interpreter/mterp/arm/op_sget_char.S | 3 +- .../interpreter/mterp/arm/op_sget_object.S | 3 +- runtime/interpreter/mterp/arm/op_sget_short.S | 3 +- runtime/interpreter/mterp/arm/op_sget_wide.S | 3 +- runtime/interpreter/mterp/arm/op_shl_int.S | 3 +- .../interpreter/mterp/arm/op_shl_int_2addr.S | 3 +- .../interpreter/mterp/arm/op_shl_int_lit8.S | 3 +- runtime/interpreter/mterp/arm/op_shl_long.S | 1 + .../interpreter/mterp/arm/op_shl_long_2addr.S | 1 + runtime/interpreter/mterp/arm/op_shr_int.S | 3 +- .../interpreter/mterp/arm/op_shr_int_2addr.S | 3 +- .../interpreter/mterp/arm/op_shr_int_lit8.S | 3 +- runtime/interpreter/mterp/arm/op_shr_long.S | 1 + .../interpreter/mterp/arm/op_shr_long_2addr.S | 1 + .../interpreter/mterp/arm/op_sparse_switch.S | 3 +- runtime/interpreter/mterp/arm/op_sput.S | 4 +- .../interpreter/mterp/arm/op_sput_boolean.S | 3 +- runtime/interpreter/mterp/arm/op_sput_byte.S | 3 +- runtime/interpreter/mterp/arm/op_sput_char.S | 3 +- .../interpreter/mterp/arm/op_sput_object.S | 3 +- runtime/interpreter/mterp/arm/op_sput_short.S | 3 +- runtime/interpreter/mterp/arm/op_sput_wide.S | 3 +- runtime/interpreter/mterp/arm/op_sub_double.S | 3 +- .../mterp/arm/op_sub_double_2addr.S | 3 +- runtime/interpreter/mterp/arm/op_sub_float.S | 3 +- .../mterp/arm/op_sub_float_2addr.S | 3 +- runtime/interpreter/mterp/arm/op_sub_int.S | 3 +- .../interpreter/mterp/arm/op_sub_int_2addr.S | 3 +- runtime/interpreter/mterp/arm/op_sub_long.S | 3 +- .../interpreter/mterp/arm/op_sub_long_2addr.S | 3 +- runtime/interpreter/mterp/arm/op_throw.S | 1 + runtime/interpreter/mterp/arm/op_unused_3e.S | 3 +- runtime/interpreter/mterp/arm/op_unused_3f.S | 3 +- runtime/interpreter/mterp/arm/op_unused_40.S | 3 +- runtime/interpreter/mterp/arm/op_unused_41.S | 3 +- runtime/interpreter/mterp/arm/op_unused_42.S | 3 +- runtime/interpreter/mterp/arm/op_unused_43.S | 3 +- runtime/interpreter/mterp/arm/op_unused_73.S | 3 +- runtime/interpreter/mterp/arm/op_unused_79.S | 3 +- runtime/interpreter/mterp/arm/op_unused_7a.S | 3 +- runtime/interpreter/mterp/arm/op_unused_f3.S | 3 +- runtime/interpreter/mterp/arm/op_unused_f4.S | 3 +- runtime/interpreter/mterp/arm/op_unused_f5.S | 3 +- runtime/interpreter/mterp/arm/op_unused_f6.S | 3 +- runtime/interpreter/mterp/arm/op_unused_f7.S | 3 +- runtime/interpreter/mterp/arm/op_unused_f8.S | 3 +- runtime/interpreter/mterp/arm/op_unused_f9.S | 3 +- runtime/interpreter/mterp/arm/op_unused_fc.S | 3 +- runtime/interpreter/mterp/arm/op_unused_fd.S | 3 +- runtime/interpreter/mterp/arm/op_ushr_int.S | 3 +- .../interpreter/mterp/arm/op_ushr_int_2addr.S | 3 +- .../interpreter/mterp/arm/op_ushr_int_lit8.S | 3 +- runtime/interpreter/mterp/arm/op_ushr_long.S | 1 + .../mterp/arm/op_ushr_long_2addr.S | 1 + runtime/interpreter/mterp/arm/op_xor_int.S | 3 +- .../interpreter/mterp/arm/op_xor_int_2addr.S | 3 +- .../interpreter/mterp/arm/op_xor_int_lit16.S | 3 +- .../interpreter/mterp/arm/op_xor_int_lit8.S | 3 +- runtime/interpreter/mterp/arm/op_xor_long.S | 3 +- .../interpreter/mterp/arm/op_xor_long_2addr.S | 3 +- runtime/interpreter/mterp/arm/unop.S | 2 +- runtime/interpreter/mterp/arm/unopNarrower.S | 2 +- runtime/interpreter/mterp/arm/unopWide.S | 2 +- runtime/interpreter/mterp/arm/unopWider.S | 2 +- runtime/interpreter/mterp/arm/unused.S | 1 + runtime/interpreter/mterp/arm/zcmp.S | 1 + runtime/interpreter/mterp/arm64/alt_stub.S | 1 + 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+- .../mterp/x86_64/op_add_int_2addr.S | 3 +- .../mterp/x86_64/op_add_int_lit16.S | 3 +- .../mterp/x86_64/op_add_int_lit8.S | 3 +- .../interpreter/mterp/x86_64/op_add_long.S | 3 +- .../mterp/x86_64/op_add_long_2addr.S | 3 +- runtime/interpreter/mterp/x86_64/op_aget.S | 2 +- .../mterp/x86_64/op_aget_boolean.S | 3 +- .../interpreter/mterp/x86_64/op_aget_byte.S | 3 +- .../interpreter/mterp/x86_64/op_aget_char.S | 3 +- .../interpreter/mterp/x86_64/op_aget_object.S | 1 + .../interpreter/mterp/x86_64/op_aget_short.S | 3 +- .../interpreter/mterp/x86_64/op_aget_wide.S | 3 +- runtime/interpreter/mterp/x86_64/op_and_int.S | 3 +- .../mterp/x86_64/op_and_int_2addr.S | 3 +- .../mterp/x86_64/op_and_int_lit16.S | 3 +- .../mterp/x86_64/op_and_int_lit8.S | 3 +- .../interpreter/mterp/x86_64/op_and_long.S | 3 +- .../mterp/x86_64/op_and_long_2addr.S | 3 +- runtime/interpreter/mterp/x86_64/op_aput.S | 2 +- .../mterp/x86_64/op_aput_boolean.S | 3 +- .../interpreter/mterp/x86_64/op_aput_byte.S | 3 +- .../interpreter/mterp/x86_64/op_aput_char.S | 3 +- .../interpreter/mterp/x86_64/op_aput_object.S | 1 + .../interpreter/mterp/x86_64/op_aput_short.S | 3 +- .../interpreter/mterp/x86_64/op_aput_wide.S | 3 +- .../mterp/x86_64/op_array_length.S | 1 + .../interpreter/mterp/x86_64/op_check_cast.S | 1 + .../interpreter/mterp/x86_64/op_cmp_long.S | 1 + .../interpreter/mterp/x86_64/op_cmpg_double.S | 3 +- .../interpreter/mterp/x86_64/op_cmpg_float.S | 3 +- .../interpreter/mterp/x86_64/op_cmpl_double.S | 3 +- .../interpreter/mterp/x86_64/op_cmpl_float.S | 3 +- runtime/interpreter/mterp/x86_64/op_const.S | 1 + .../interpreter/mterp/x86_64/op_const_16.S | 1 + runtime/interpreter/mterp/x86_64/op_const_4.S | 1 + .../interpreter/mterp/x86_64/op_const_class.S | 3 +- .../mterp/x86_64/op_const_high16.S | 1 + .../mterp/x86_64/op_const_method_handle.S | 3 +- .../mterp/x86_64/op_const_method_type.S | 3 +- .../mterp/x86_64/op_const_string.S | 3 +- .../mterp/x86_64/op_const_string_jumbo.S | 1 + .../interpreter/mterp/x86_64/op_const_wide.S | 1 + .../mterp/x86_64/op_const_wide_16.S | 1 + .../mterp/x86_64/op_const_wide_32.S | 1 + .../mterp/x86_64/op_const_wide_high16.S | 1 + .../interpreter/mterp/x86_64/op_div_double.S | 3 +- .../mterp/x86_64/op_div_double_2addr.S | 3 +- .../interpreter/mterp/x86_64/op_div_float.S | 3 +- .../mterp/x86_64/op_div_float_2addr.S | 3 +- runtime/interpreter/mterp/x86_64/op_div_int.S | 3 +- .../mterp/x86_64/op_div_int_2addr.S | 3 +- .../mterp/x86_64/op_div_int_lit16.S | 3 +- .../mterp/x86_64/op_div_int_lit8.S | 3 +- .../interpreter/mterp/x86_64/op_div_long.S | 3 +- .../mterp/x86_64/op_div_long_2addr.S | 3 +- .../mterp/x86_64/op_double_to_float.S | 3 +- .../mterp/x86_64/op_double_to_int.S | 3 +- .../mterp/x86_64/op_double_to_long.S | 3 +- .../mterp/x86_64/op_fill_array_data.S | 1 + .../mterp/x86_64/op_filled_new_array.S | 2 +- .../mterp/x86_64/op_filled_new_array_range.S | 3 +- .../mterp/x86_64/op_float_to_double.S | 3 +- .../mterp/x86_64/op_float_to_int.S | 3 +- .../mterp/x86_64/op_float_to_long.S | 3 +- runtime/interpreter/mterp/x86_64/op_goto.S | 1 + runtime/interpreter/mterp/x86_64/op_goto_16.S | 1 + runtime/interpreter/mterp/x86_64/op_goto_32.S | 1 + runtime/interpreter/mterp/x86_64/op_if_eq.S | 3 +- runtime/interpreter/mterp/x86_64/op_if_eqz.S | 3 +- runtime/interpreter/mterp/x86_64/op_if_ge.S | 3 +- runtime/interpreter/mterp/x86_64/op_if_gez.S | 3 +- runtime/interpreter/mterp/x86_64/op_if_gt.S | 3 +- runtime/interpreter/mterp/x86_64/op_if_gtz.S | 3 +- runtime/interpreter/mterp/x86_64/op_if_le.S | 3 +- runtime/interpreter/mterp/x86_64/op_if_lez.S | 3 +- runtime/interpreter/mterp/x86_64/op_if_lt.S | 3 +- runtime/interpreter/mterp/x86_64/op_if_ltz.S | 3 +- runtime/interpreter/mterp/x86_64/op_if_ne.S | 3 +- runtime/interpreter/mterp/x86_64/op_if_nez.S | 3 +- runtime/interpreter/mterp/x86_64/op_iget.S | 4 +- .../mterp/x86_64/op_iget_boolean.S | 3 +- .../mterp/x86_64/op_iget_boolean_quick.S | 3 +- .../interpreter/mterp/x86_64/op_iget_byte.S | 3 +- .../mterp/x86_64/op_iget_byte_quick.S | 3 +- .../interpreter/mterp/x86_64/op_iget_char.S | 3 +- .../mterp/x86_64/op_iget_char_quick.S | 3 +- .../interpreter/mterp/x86_64/op_iget_object.S | 3 +- .../mterp/x86_64/op_iget_object_quick.S | 1 + .../interpreter/mterp/x86_64/op_iget_quick.S | 2 +- .../interpreter/mterp/x86_64/op_iget_short.S | 3 +- .../mterp/x86_64/op_iget_short_quick.S | 3 +- .../interpreter/mterp/x86_64/op_iget_wide.S | 3 +- .../mterp/x86_64/op_iget_wide_quick.S | 3 +- .../interpreter/mterp/x86_64/op_instance_of.S | 1 + .../interpreter/mterp/x86_64/op_int_to_byte.S | 3 +- .../interpreter/mterp/x86_64/op_int_to_char.S | 3 +- .../mterp/x86_64/op_int_to_double.S | 3 +- .../mterp/x86_64/op_int_to_float.S | 3 +- .../interpreter/mterp/x86_64/op_int_to_long.S | 1 + .../mterp/x86_64/op_int_to_short.S | 3 +- .../mterp/x86_64/op_invoke_custom.S | 3 +- .../mterp/x86_64/op_invoke_custom_range.S | 3 +- .../mterp/x86_64/op_invoke_direct.S | 3 +- .../mterp/x86_64/op_invoke_direct_range.S | 3 +- .../mterp/x86_64/op_invoke_interface.S | 3 +- .../mterp/x86_64/op_invoke_interface_range.S | 3 +- .../mterp/x86_64/op_invoke_polymorphic.S | 3 +- .../x86_64/op_invoke_polymorphic_range.S | 3 +- .../mterp/x86_64/op_invoke_static.S | 3 +- .../mterp/x86_64/op_invoke_static_range.S | 3 +- .../mterp/x86_64/op_invoke_super.S | 3 +- .../mterp/x86_64/op_invoke_super_range.S | 3 +- .../mterp/x86_64/op_invoke_virtual.S | 3 +- .../mterp/x86_64/op_invoke_virtual_quick.S | 3 +- .../mterp/x86_64/op_invoke_virtual_range.S | 3 +- .../x86_64/op_invoke_virtual_range_quick.S | 3 +- runtime/interpreter/mterp/x86_64/op_iput.S | 4 +- .../mterp/x86_64/op_iput_boolean.S | 3 +- .../mterp/x86_64/op_iput_boolean_quick.S | 3 +- .../interpreter/mterp/x86_64/op_iput_byte.S | 3 +- .../mterp/x86_64/op_iput_byte_quick.S | 3 +- .../interpreter/mterp/x86_64/op_iput_char.S | 3 +- .../mterp/x86_64/op_iput_char_quick.S | 3 +- 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.../mterp/x86_64/op_move_result_object.S | 3 +- .../mterp/x86_64/op_move_result_wide.S | 1 + .../interpreter/mterp/x86_64/op_move_wide.S | 1 + .../mterp/x86_64/op_move_wide_16.S | 1 + .../mterp/x86_64/op_move_wide_from16.S | 1 + .../interpreter/mterp/x86_64/op_mul_double.S | 3 +- .../mterp/x86_64/op_mul_double_2addr.S | 3 +- .../interpreter/mterp/x86_64/op_mul_float.S | 3 +- .../mterp/x86_64/op_mul_float_2addr.S | 3 +- runtime/interpreter/mterp/x86_64/op_mul_int.S | 3 +- .../mterp/x86_64/op_mul_int_2addr.S | 1 + .../mterp/x86_64/op_mul_int_lit16.S | 3 +- .../mterp/x86_64/op_mul_int_lit8.S | 3 +- .../interpreter/mterp/x86_64/op_mul_long.S | 3 +- .../mterp/x86_64/op_mul_long_2addr.S | 1 + .../interpreter/mterp/x86_64/op_neg_double.S | 3 +- .../interpreter/mterp/x86_64/op_neg_float.S | 3 +- runtime/interpreter/mterp/x86_64/op_neg_int.S | 3 +- .../interpreter/mterp/x86_64/op_neg_long.S | 3 +- .../interpreter/mterp/x86_64/op_new_array.S | 1 + .../mterp/x86_64/op_new_instance.S | 1 + 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.../mterp/x86_64/op_return_object.S | 3 +- .../interpreter/mterp/x86_64/op_return_void.S | 1 + .../mterp/x86_64/op_return_void_no_barrier.S | 1 + .../interpreter/mterp/x86_64/op_return_wide.S | 1 + .../interpreter/mterp/x86_64/op_rsub_int.S | 3 +- .../mterp/x86_64/op_rsub_int_lit8.S | 3 +- runtime/interpreter/mterp/x86_64/op_sget.S | 4 +- .../mterp/x86_64/op_sget_boolean.S | 3 +- .../interpreter/mterp/x86_64/op_sget_byte.S | 3 +- .../interpreter/mterp/x86_64/op_sget_char.S | 3 +- .../interpreter/mterp/x86_64/op_sget_object.S | 3 +- .../interpreter/mterp/x86_64/op_sget_short.S | 3 +- .../interpreter/mterp/x86_64/op_sget_wide.S | 3 +- runtime/interpreter/mterp/x86_64/op_shl_int.S | 3 +- .../mterp/x86_64/op_shl_int_2addr.S | 3 +- .../mterp/x86_64/op_shl_int_lit8.S | 3 +- .../interpreter/mterp/x86_64/op_shl_long.S | 3 +- .../mterp/x86_64/op_shl_long_2addr.S | 3 +- runtime/interpreter/mterp/x86_64/op_shr_int.S | 3 +- .../mterp/x86_64/op_shr_int_2addr.S | 3 +- .../mterp/x86_64/op_shr_int_lit8.S | 3 +- .../interpreter/mterp/x86_64/op_shr_long.S | 3 +- .../mterp/x86_64/op_shr_long_2addr.S | 3 +- .../mterp/x86_64/op_sparse_switch.S | 3 +- runtime/interpreter/mterp/x86_64/op_sput.S | 4 +- .../mterp/x86_64/op_sput_boolean.S | 3 +- .../interpreter/mterp/x86_64/op_sput_byte.S | 3 +- .../interpreter/mterp/x86_64/op_sput_char.S | 3 +- .../interpreter/mterp/x86_64/op_sput_object.S | 3 +- .../interpreter/mterp/x86_64/op_sput_short.S | 3 +- .../interpreter/mterp/x86_64/op_sput_wide.S | 3 +- .../interpreter/mterp/x86_64/op_sub_double.S | 3 +- .../mterp/x86_64/op_sub_double_2addr.S | 3 +- .../interpreter/mterp/x86_64/op_sub_float.S | 3 +- .../mterp/x86_64/op_sub_float_2addr.S | 3 +- runtime/interpreter/mterp/x86_64/op_sub_int.S | 3 +- .../mterp/x86_64/op_sub_int_2addr.S | 3 +- .../interpreter/mterp/x86_64/op_sub_long.S | 3 +- .../mterp/x86_64/op_sub_long_2addr.S | 3 +- runtime/interpreter/mterp/x86_64/op_throw.S | 1 + .../interpreter/mterp/x86_64/op_unused_3e.S | 3 +- .../interpreter/mterp/x86_64/op_unused_3f.S | 3 +- .../interpreter/mterp/x86_64/op_unused_40.S | 3 +- .../interpreter/mterp/x86_64/op_unused_41.S | 3 +- .../interpreter/mterp/x86_64/op_unused_42.S | 3 +- .../interpreter/mterp/x86_64/op_unused_43.S | 3 +- .../interpreter/mterp/x86_64/op_unused_79.S | 3 +- .../interpreter/mterp/x86_64/op_unused_7a.S | 3 +- .../interpreter/mterp/x86_64/op_unused_f3.S | 3 +- .../interpreter/mterp/x86_64/op_unused_f4.S | 3 +- .../interpreter/mterp/x86_64/op_unused_f5.S | 3 +- .../interpreter/mterp/x86_64/op_unused_f6.S | 3 +- .../interpreter/mterp/x86_64/op_unused_f7.S | 3 +- .../interpreter/mterp/x86_64/op_unused_f8.S | 3 +- .../interpreter/mterp/x86_64/op_unused_f9.S | 3 +- .../interpreter/mterp/x86_64/op_unused_fc.S | 3 +- .../interpreter/mterp/x86_64/op_unused_fd.S | 3 +- .../interpreter/mterp/x86_64/op_ushr_int.S | 3 +- .../mterp/x86_64/op_ushr_int_2addr.S | 3 +- .../mterp/x86_64/op_ushr_int_lit8.S | 3 +- .../interpreter/mterp/x86_64/op_ushr_long.S | 3 +- .../mterp/x86_64/op_ushr_long_2addr.S | 3 +- runtime/interpreter/mterp/x86_64/op_xor_int.S | 3 +- .../mterp/x86_64/op_xor_int_2addr.S | 3 +- .../mterp/x86_64/op_xor_int_lit16.S | 3 +- .../mterp/x86_64/op_xor_int_lit8.S | 3 +- .../interpreter/mterp/x86_64/op_xor_long.S | 3 +- .../mterp/x86_64/op_xor_long_2addr.S | 3 +- runtime/interpreter/mterp/x86_64/shop2addr.S | 2 +- runtime/interpreter/mterp/x86_64/sseBinop.S | 2 +- .../interpreter/mterp/x86_64/sseBinop2Addr.S | 2 +- runtime/interpreter/mterp/x86_64/unop.S | 2 +- runtime/interpreter/mterp/x86_64/unused.S | 1 + runtime/interpreter/mterp/x86_64/zcmp.S | 1 + 1779 files changed, 3179 insertions(+), 10009 deletions(-) delete mode 100644 runtime/interpreter/mterp/Makefile_mterp create mode 100644 runtime/interpreter/mterp/common/gen_setup.py delete mode 100644 runtime/interpreter/mterp/config_arm delete mode 100644 runtime/interpreter/mterp/config_arm64 delete mode 100644 runtime/interpreter/mterp/config_mips delete mode 100644 runtime/interpreter/mterp/config_mips64 delete mode 100644 runtime/interpreter/mterp/config_x86 delete mode 100644 runtime/interpreter/mterp/config_x86_64 delete mode 100755 runtime/interpreter/mterp/rebuild.sh diff --git a/runtime/interpreter/mterp/Makefile_mterp b/runtime/interpreter/mterp/Makefile_mterp deleted file mode 100644 index ac8da69742..0000000000 --- a/runtime/interpreter/mterp/Makefile_mterp +++ /dev/null @@ -1,49 +0,0 @@ -# Copyright (C) 2016 The Android Open Source Project -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -# -# Makefile for the Art fast interpreter. This is not currently -# integrated into the build system. -# - -SHELL := /bin/sh - -# Build system has TARGET_ARCH=arm, but we can support the exact architecture -# if it is worthwhile. -# -# To generate sources: -# for arch in arm arm64 x86 x86_64 mips mips64 -# do -# TARGET_ARCH_EXT=$arch make -f Makefile_mterp -# done -# - -OUTPUT_DIR := out - -# Accumulate all possible dependencies for the generated files in a very -# conservative fashion. If it's not one of the generated files in "out", -# assume it's a dependency. -SOURCE_DEPS := \ - $(shell find . -path ./$(OUTPUT_DIR) -prune -o -type f -print) \ - -# Source files generated by the script. There's always one C and one -# assembly file, though in practice one or the other could be empty. -GEN_SOURCES := \ - $(OUTPUT_DIR)/interp_asm_$(TARGET_ARCH_EXT).S - -target: $(GEN_SOURCES) - -$(GEN_SOURCES): $(SOURCE_DEPS) - @mkdir -p out - ./gen_mterp.py $(TARGET_ARCH_EXT) $(OUTPUT_DIR) diff --git a/runtime/interpreter/mterp/README.txt b/runtime/interpreter/mterp/README.txt index 19e02bec50..54bb634cb5 100644 --- a/runtime/interpreter/mterp/README.txt +++ b/runtime/interpreter/mterp/README.txt @@ -1,108 +1,29 @@ -rt "mterp" README - -NOTE: Find rebuilding instructions at the bottom of this file. - - ==== Overview ==== -Every configuration has a "config-*" file that controls how the sources -are generated. The sources are written into the "out" directory, where +The assembly source code is produced from custom python-based templates. +All the architecture-specific template files are concatenated to create +one big python script. This generated python script is then executed to +produced the final assembly file. The template syntax is: + * Lines starting with % are python code. They will be copied as-is to + the script (without the %) and thus executed during the generation. + * Other lines are text, and they are essentially syntax sugar for + out.write('''(line text)''') and thus they write the main output. + * Within a text line, $ can be used insert variables from code. + +The final assembly sources are written into the "out" directory, where they are picked up by the Android build system. The best way to become familiar with the interpreter is to look at the generated files in the "out" directory. -==== Config file format ==== - -The config files are parsed from top to bottom. Each line in the file -may be blank, hold a comment (line starts with '#'), or be a command. - -The commands are: - - handler-style - - Specify which style of interpreter to generate. In computed-goto, - each handler is allocated a fixed region, allowing transitions to - be done via table-start-address + (opcode * handler-size). With - jump-table style, handlers may be of any length, and the generated - table is an array of pointers to the handlers. This command is required, - and must be the first command in the config file. - - handler-size - - Specify the size of the fixed region, in bytes. On most platforms - this will need to be a power of 2. For jump-table implementations, - this command is ignored. - - import - - The specified file is included immediately, in its entirety. No - substitutions are performed. ".cpp" and ".h" files are copied to the - C output, ".S" files are copied to the asm output. - - asm-alt-stub - - When present, this command will cause the generation of an alternate - set of entry points (for computed-goto interpreters) or an alternate - jump table (for jump-table interpreters). - - fallback-stub - - Specifies a file to be used for the special FALLBACK tag on the "op" - command below. Intended to be used to transfer control to an alternate - interpreter to single-step a not-yet-implemented opcode. Note: should - note be used on RETURN-class instructions. - - op-start - - Indicates the start of the opcode list. Must precede any "op" - commands. The specified directory is the default location to pull - instruction files from. - - op |FALLBACK - - Can only appear after "op-start" and before "op-end". Overrides the - default source file location of the specified opcode. The opcode - definition will come from the specified file, e.g. "op OP_NOP arm" - will load from "arm/OP_NOP.S". A substitution dictionary will be - applied (see below). If the special "FALLBACK" token is used instead of - a directory name, the source file specified in fallback-stub will instead - be used for this opcode. - - alt - - Can only appear after "op-start" and before "op-end". Similar to the - "op" command above, but denotes a source file to override the entry - in the alternate handler table. The opcode definition will come from - the specified file, e.g. "alt OP_NOP arm" will load from - "arm/ALT_OP_NOP.S". A substitution dictionary will be applied - (see below). - - op-end - - Indicates the end of the opcode list. All kNumPackedOpcodes - opcodes are emitted when this is seen, followed by any code that - didn't fit inside the fixed-size instruction handler space. - -The order of "op" and "alt" directives are not significant; the generation -tool will extract ordering info from the VM sources. - -Typically the form in which most opcodes currently exist is used in -the "op-start" directive. - ==== Instruction file format ==== The assembly instruction files are simply fragments of assembly sources. The starting label will be provided by the generation tool, as will -declarations for the segment type and alignment. The expected target -assembler is GNU "as", but others will work (may require fiddling with -some of the pseudo-ops emitted by the generation tool). - -A substitution dictionary is applied to all opcode fragments as they are -appended to the output. Substitutions can look like "$value" or "${value}". +declarations for the segment type and alignment. -The dictionary always includes: +The following global variables are generally available: $opcode - opcode name, e.g. "OP_NOP" $opnum - opcode number, e.g. 0 for OP_NOP @@ -113,29 +34,6 @@ Both C and assembly sources will be passed through the C pre-processor, so you can take advantage of C-style comments and preprocessor directives like "#define". -Some generator operations are available. - - %include "filename" [subst-dict] - - Includes the file, which should look like "arm/OP_NOP.S". You can - specify values for the substitution dictionary, using standard Python - syntax. For example, this: - %include "arm/unop.S" {"result":"r1"} - would insert "arm/unop.S" at the current file position, replacing - occurrences of "$result" with "r1". - - %default - - Specify default substitution dictionary values, using standard Python - syntax. Useful if you want to have a "base" version and variants. - - %break - - Identifies the split between the main portion of the instruction - handler (which must fit in "handler-size" bytes) and the "sister" - code, which is appended to the end of the instruction handler block. - In jump table implementations, %break is ignored. - The generation tool does *not* print a warning if your instructions exceed "handler-size", but the VM will abort on startup if it detects an oversized handler. On architectures with fixed-width instructions this @@ -153,20 +51,6 @@ If a constant in the file becomes out of sync, the VM will log an error message and abort during startup. -==== Development tips ==== - -If you need to debug the initial piece of an opcode handler, and your -debug code expands it beyond the handler size limit, you can insert a -generic header at the top: - - b ${opcode}_start -%break -${opcode}_start: - -If you already have a %break, it's okay to leave it in place -- the second -%break is ignored. - - ==== Rebuilding ==== If you change any of the source file fragments, you need to rebuild the @@ -174,7 +58,7 @@ combined source files in the "out" directory. Make sure the files in "out" are editable, then: $ cd mterp - $ ./rebuild.sh + $ ./gen_mterp.py The ultimate goal is to have the build system generate the necessary output files without requiring this separate step, but we're not yet diff --git a/runtime/interpreter/mterp/arm/alt_stub.S b/runtime/interpreter/mterp/arm/alt_stub.S index 8799d9520c..9e6f91ecf7 100644 --- a/runtime/interpreter/mterp/arm/alt_stub.S +++ b/runtime/interpreter/mterp/arm/alt_stub.S @@ -1,3 +1,4 @@ +%def alt_stub(): /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction diff --git a/runtime/interpreter/mterp/arm/bincmp.S b/runtime/interpreter/mterp/arm/bincmp.S index 8fad42f0d2..368c2d6971 100644 --- a/runtime/interpreter/mterp/arm/bincmp.S +++ b/runtime/interpreter/mterp/arm/bincmp.S @@ -1,3 +1,4 @@ +%def bincmp(condition=""): /* * Generic two-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform. diff --git a/runtime/interpreter/mterp/arm/binop.S b/runtime/interpreter/mterp/arm/binop.S index eeb72ef65b..72ae9f4b38 100644 --- a/runtime/interpreter/mterp/arm/binop.S +++ b/runtime/interpreter/mterp/arm/binop.S @@ -1,4 +1,4 @@ -%default {"preinstr":"", "result":"r0", "chkzero":"0"} +%def binop(preinstr="", result="r0", chkzero="0", instr=""): /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = r0 op r1". diff --git a/runtime/interpreter/mterp/arm/binop2addr.S b/runtime/interpreter/mterp/arm/binop2addr.S index d09a43ae48..6f7f23c2aa 100644 --- a/runtime/interpreter/mterp/arm/binop2addr.S +++ b/runtime/interpreter/mterp/arm/binop2addr.S @@ -1,4 +1,4 @@ -%default {"preinstr":"", "result":"r0", "chkzero":"0"} +%def binop2addr(preinstr="", result="r0", chkzero="0", instr=""): /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0 op r1". diff --git a/runtime/interpreter/mterp/arm/binopLit16.S b/runtime/interpreter/mterp/arm/binopLit16.S index 065394e4ef..86291b5655 100644 --- a/runtime/interpreter/mterp/arm/binopLit16.S +++ b/runtime/interpreter/mterp/arm/binopLit16.S @@ -1,4 +1,4 @@ -%default {"result":"r0", "chkzero":"0"} +%def binopLit16(result="r0", chkzero="0", instr=""): /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0 op r1". diff --git a/runtime/interpreter/mterp/arm/binopLit8.S b/runtime/interpreter/mterp/arm/binopLit8.S index 7c9c6312cd..b850e496e7 100644 --- a/runtime/interpreter/mterp/arm/binopLit8.S +++ b/runtime/interpreter/mterp/arm/binopLit8.S @@ -1,4 +1,4 @@ -%default {"extract":"asr r1, r3, #8", "result":"r0", "chkzero":"0"} +%def binopLit8(extract="asr r1, r3, #8", result="r0", chkzero="0", instr=""): /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0 op r1". diff --git a/runtime/interpreter/mterp/arm/binopWide.S b/runtime/interpreter/mterp/arm/binopWide.S index 4d880015c8..b708627f97 100644 --- a/runtime/interpreter/mterp/arm/binopWide.S +++ b/runtime/interpreter/mterp/arm/binopWide.S @@ -1,4 +1,4 @@ -%default {"preinstr":"", "result0":"r0", "result1":"r1", "chkzero":"0"} +%def binopWide(preinstr="", result0="r0", result1="r1", chkzero="0", instr=""): /* * Generic 64-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = r0-r1 op r2-r3". diff --git a/runtime/interpreter/mterp/arm/binopWide2addr.S b/runtime/interpreter/mterp/arm/binopWide2addr.S index bb16335c34..2ce513088b 100644 --- a/runtime/interpreter/mterp/arm/binopWide2addr.S +++ b/runtime/interpreter/mterp/arm/binopWide2addr.S @@ -1,4 +1,4 @@ -%default {"preinstr":"", "result0":"r0", "result1":"r1", "chkzero":"0"} +%def binopWide2addr(preinstr="", result0="r0", result1="r1", chkzero="0", instr=""): /* * Generic 64-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0-r1 op r2-r3". diff --git a/runtime/interpreter/mterp/arm/const.S b/runtime/interpreter/mterp/arm/const.S index f6f8157a0b..a22f366c97 100644 --- a/runtime/interpreter/mterp/arm/const.S +++ b/runtime/interpreter/mterp/arm/const.S @@ -1,4 +1,4 @@ -%default { "helper":"UndefinedConstHandler" } +%def const(helper="UndefinedConstHandler"): /* const/class vAA, type@BBBB */ /* const/method-handle vAA, method_handle@BBBB */ /* const/method-type vAA, proto@BBBB */ diff --git a/runtime/interpreter/mterp/arm/entry.S b/runtime/interpreter/mterp/arm/entry.S index 7c7c527ef4..d17802b705 100644 --- a/runtime/interpreter/mterp/arm/entry.S +++ b/runtime/interpreter/mterp/arm/entry.S @@ -1,3 +1,4 @@ +%def entry(): /* * Copyright (C) 2016 The Android Open Source Project * diff --git a/runtime/interpreter/mterp/arm/fallback.S b/runtime/interpreter/mterp/arm/fallback.S index 44e7e1220d..3685700dec 100644 --- a/runtime/interpreter/mterp/arm/fallback.S +++ b/runtime/interpreter/mterp/arm/fallback.S @@ -1,3 +1,4 @@ +%def fallback(): /* Transfer stub to alternate interpreter */ b MterpFallback diff --git a/runtime/interpreter/mterp/arm/fbinop.S b/runtime/interpreter/mterp/arm/fbinop.S index 594ee032d1..0f75f89cbb 100644 --- a/runtime/interpreter/mterp/arm/fbinop.S +++ b/runtime/interpreter/mterp/arm/fbinop.S @@ -1,3 +1,4 @@ +%def fbinop(instr=""): /* * Generic 32-bit floating-point operation. Provide an "instr" line that * specifies an instruction that performs "s2 = s0 op s1". Because we diff --git a/runtime/interpreter/mterp/arm/fbinop2addr.S b/runtime/interpreter/mterp/arm/fbinop2addr.S index 53c87a08f3..a5162a13b2 100644 --- a/runtime/interpreter/mterp/arm/fbinop2addr.S +++ b/runtime/interpreter/mterp/arm/fbinop2addr.S @@ -1,3 +1,4 @@ +%def fbinop2addr(instr=""): /* * Generic 32-bit floating point "/2addr" binary operation. Provide * an "instr" line that specifies an instruction that performs diff --git a/runtime/interpreter/mterp/arm/fbinopWide.S b/runtime/interpreter/mterp/arm/fbinopWide.S index ca13bfbab6..e283feedd8 100644 --- a/runtime/interpreter/mterp/arm/fbinopWide.S +++ b/runtime/interpreter/mterp/arm/fbinopWide.S @@ -1,3 +1,4 @@ +%def fbinopWide(instr=""): /* * Generic 64-bit double-precision floating point binary operation. * Provide an "instr" line that specifies an instruction that performs diff --git a/runtime/interpreter/mterp/arm/fbinopWide2addr.S b/runtime/interpreter/mterp/arm/fbinopWide2addr.S index 9766e2c0c4..639a7834f9 100644 --- a/runtime/interpreter/mterp/arm/fbinopWide2addr.S +++ b/runtime/interpreter/mterp/arm/fbinopWide2addr.S @@ -1,3 +1,4 @@ +%def fbinopWide2addr(instr=""): /* * Generic 64-bit floating point "/2addr" binary operation. Provide * an "instr" line that specifies an instruction that performs diff --git a/runtime/interpreter/mterp/arm/field.S b/runtime/interpreter/mterp/arm/field.S index c46878829e..82e1638fcd 100644 --- a/runtime/interpreter/mterp/arm/field.S +++ b/runtime/interpreter/mterp/arm/field.S @@ -1,4 +1,4 @@ -%default { } +%def field(helper=""): /* * General field read / write (iget-* iput-* sget-* sput-*). */ diff --git a/runtime/interpreter/mterp/arm/footer.S b/runtime/interpreter/mterp/arm/footer.S index 8e9c3c22fe..275584e4ea 100644 --- a/runtime/interpreter/mterp/arm/footer.S +++ b/runtime/interpreter/mterp/arm/footer.S @@ -1,3 +1,4 @@ +%def footer(): /* * =========================================================================== * Common subroutines and data diff --git a/runtime/interpreter/mterp/arm/funop.S b/runtime/interpreter/mterp/arm/funop.S index 1b8bb8bac6..c4f2231938 100644 --- a/runtime/interpreter/mterp/arm/funop.S +++ b/runtime/interpreter/mterp/arm/funop.S @@ -1,3 +1,4 @@ +%def funop(instr=""): /* * Generic 32-bit unary floating-point operation. Provide an "instr" * line that specifies an instruction that performs "s1 = op s0". diff --git a/runtime/interpreter/mterp/arm/funopNarrower.S b/runtime/interpreter/mterp/arm/funopNarrower.S index b9f758ba86..ce5e82ca89 100644 --- a/runtime/interpreter/mterp/arm/funopNarrower.S +++ b/runtime/interpreter/mterp/arm/funopNarrower.S @@ -1,3 +1,4 @@ +%def funopNarrower(instr=""): /* * Generic 64bit-to-32bit unary floating point operation. Provide an * "instr" line that specifies an instruction that performs "s0 = op d0". diff --git a/runtime/interpreter/mterp/arm/funopWider.S b/runtime/interpreter/mterp/arm/funopWider.S index 854cdc9b66..8df362f250 100644 --- a/runtime/interpreter/mterp/arm/funopWider.S +++ b/runtime/interpreter/mterp/arm/funopWider.S @@ -1,3 +1,4 @@ +%def funopWider(instr=""): /* * Generic 32bit-to-64bit floating point unary operation. Provide an * "instr" line that specifies an instruction that performs "d0 = op s0". diff --git a/runtime/interpreter/mterp/arm/header.S b/runtime/interpreter/mterp/arm/header.S index 8d9cab5a2f..03f330a4e9 100644 --- a/runtime/interpreter/mterp/arm/header.S +++ b/runtime/interpreter/mterp/arm/header.S @@ -1,3 +1,4 @@ +%def header(): /* * Copyright (C) 2016 The Android Open Source Project * diff --git a/runtime/interpreter/mterp/arm/instruction_end.S b/runtime/interpreter/mterp/arm/instruction_end.S index f90ebd0221..cf30a9b0b0 100644 --- a/runtime/interpreter/mterp/arm/instruction_end.S +++ b/runtime/interpreter/mterp/arm/instruction_end.S @@ -1,3 +1,4 @@ +%def instruction_end(): .type artMterpAsmInstructionEnd, #object .hidden artMterpAsmInstructionEnd diff --git a/runtime/interpreter/mterp/arm/instruction_end_alt.S b/runtime/interpreter/mterp/arm/instruction_end_alt.S index 0b66dbb947..9509a63b6a 100644 --- a/runtime/interpreter/mterp/arm/instruction_end_alt.S +++ b/runtime/interpreter/mterp/arm/instruction_end_alt.S @@ -1,3 +1,4 @@ +%def instruction_end_alt(): .type artMterpAsmAltInstructionEnd, #object .hidden artMterpAsmAltInstructionEnd diff --git a/runtime/interpreter/mterp/arm/instruction_end_sister.S b/runtime/interpreter/mterp/arm/instruction_end_sister.S index 71c0300f6d..18f1dbb38d 100644 --- a/runtime/interpreter/mterp/arm/instruction_end_sister.S +++ b/runtime/interpreter/mterp/arm/instruction_end_sister.S @@ -1,3 +1,4 @@ +%def instruction_end_sister(): .type artMterpAsmSisterEnd, #object .hidden artMterpAsmSisterEnd diff --git a/runtime/interpreter/mterp/arm/instruction_start.S b/runtime/interpreter/mterp/arm/instruction_start.S index b7e9cf51e4..457dcf9617 100644 --- a/runtime/interpreter/mterp/arm/instruction_start.S +++ b/runtime/interpreter/mterp/arm/instruction_start.S @@ -1,3 +1,4 @@ +%def instruction_start(): .type artMterpAsmInstructionStart, #object .hidden artMterpAsmInstructionStart diff --git a/runtime/interpreter/mterp/arm/instruction_start_alt.S b/runtime/interpreter/mterp/arm/instruction_start_alt.S index 7a67ba064c..40d2bf5dbe 100644 --- a/runtime/interpreter/mterp/arm/instruction_start_alt.S +++ b/runtime/interpreter/mterp/arm/instruction_start_alt.S @@ -1,3 +1,4 @@ +%def instruction_start_alt(): .type artMterpAsmAltInstructionStart, #object .hidden artMterpAsmAltInstructionStart diff --git a/runtime/interpreter/mterp/arm/instruction_start_sister.S b/runtime/interpreter/mterp/arm/instruction_start_sister.S index 0036061605..2bf24636ea 100644 --- a/runtime/interpreter/mterp/arm/instruction_start_sister.S +++ b/runtime/interpreter/mterp/arm/instruction_start_sister.S @@ -1,3 +1,4 @@ +%def instruction_start_sister(): .type artMterpAsmSisterStart, #object .hidden artMterpAsmSisterStart diff --git a/runtime/interpreter/mterp/arm/invoke.S b/runtime/interpreter/mterp/arm/invoke.S index e47dd1b3ca..812852ef57 100644 --- a/runtime/interpreter/mterp/arm/invoke.S +++ b/runtime/interpreter/mterp/arm/invoke.S @@ -1,4 +1,4 @@ -%default { "helper":"UndefinedInvokeHandler" } +%def invoke(helper="UndefinedInvokeHandler"): /* * Generic invoke handler wrapper. */ diff --git a/runtime/interpreter/mterp/arm/invoke_polymorphic.S b/runtime/interpreter/mterp/arm/invoke_polymorphic.S index f569d61c0b..b473616ad2 100644 --- a/runtime/interpreter/mterp/arm/invoke_polymorphic.S +++ b/runtime/interpreter/mterp/arm/invoke_polymorphic.S @@ -1,4 +1,4 @@ -%default { "helper":"UndefinedInvokeHandler" } +%def invoke_polymorphic(helper="UndefinedInvokeHandler"): /* * invoke-polymorphic handler wrapper. */ diff --git a/runtime/interpreter/mterp/arm/op_add_double.S b/runtime/interpreter/mterp/arm/op_add_double.S index 9332bf2005..17aabcd817 100644 --- a/runtime/interpreter/mterp/arm/op_add_double.S +++ b/runtime/interpreter/mterp/arm/op_add_double.S @@ -1 +1,2 @@ -%include "arm/fbinopWide.S" {"instr":"faddd d2, d0, d1"} +%def op_add_double(): +% fbinopWide(instr="faddd d2, d0, d1") diff --git a/runtime/interpreter/mterp/arm/op_add_double_2addr.S b/runtime/interpreter/mterp/arm/op_add_double_2addr.S index 3242c53f65..97d1757468 100644 --- a/runtime/interpreter/mterp/arm/op_add_double_2addr.S +++ b/runtime/interpreter/mterp/arm/op_add_double_2addr.S @@ -1 +1,2 @@ -%include "arm/fbinopWide2addr.S" {"instr":"faddd d2, d0, d1"} +%def op_add_double_2addr(): +% fbinopWide2addr(instr="faddd d2, d0, d1") diff --git a/runtime/interpreter/mterp/arm/op_add_float.S b/runtime/interpreter/mterp/arm/op_add_float.S index afb7967eb7..9ca8cadc34 100644 --- a/runtime/interpreter/mterp/arm/op_add_float.S +++ b/runtime/interpreter/mterp/arm/op_add_float.S @@ -1 +1,2 @@ -%include "arm/fbinop.S" {"instr":"fadds s2, s0, s1"} +%def op_add_float(): +% fbinop(instr="fadds s2, s0, s1") diff --git a/runtime/interpreter/mterp/arm/op_add_float_2addr.S b/runtime/interpreter/mterp/arm/op_add_float_2addr.S index 0067b6a010..abe1989778 100644 --- a/runtime/interpreter/mterp/arm/op_add_float_2addr.S +++ b/runtime/interpreter/mterp/arm/op_add_float_2addr.S @@ -1 +1,2 @@ -%include "arm/fbinop2addr.S" {"instr":"fadds s2, s0, s1"} +%def op_add_float_2addr(): +% fbinop2addr(instr="fadds s2, s0, s1") diff --git a/runtime/interpreter/mterp/arm/op_add_int.S b/runtime/interpreter/mterp/arm/op_add_int.S index 1dcae7eab3..e18601c71b 100644 --- a/runtime/interpreter/mterp/arm/op_add_int.S +++ b/runtime/interpreter/mterp/arm/op_add_int.S @@ -1 +1,2 @@ -%include "arm/binop.S" {"instr":"add r0, r0, r1"} +%def op_add_int(): +% binop(instr="add r0, r0, r1") diff --git a/runtime/interpreter/mterp/arm/op_add_int_2addr.S b/runtime/interpreter/mterp/arm/op_add_int_2addr.S index 9ea98f1928..10ea943583 100644 --- a/runtime/interpreter/mterp/arm/op_add_int_2addr.S +++ b/runtime/interpreter/mterp/arm/op_add_int_2addr.S @@ -1 +1,2 @@ -%include "arm/binop2addr.S" {"instr":"add r0, r0, r1"} +%def op_add_int_2addr(): +% binop2addr(instr="add r0, r0, r1") diff --git a/runtime/interpreter/mterp/arm/op_add_int_lit16.S b/runtime/interpreter/mterp/arm/op_add_int_lit16.S index 5763ab849b..63febf20da 100644 --- a/runtime/interpreter/mterp/arm/op_add_int_lit16.S +++ b/runtime/interpreter/mterp/arm/op_add_int_lit16.S @@ -1 +1,2 @@ -%include "arm/binopLit16.S" {"instr":"add r0, r0, r1"} +%def op_add_int_lit16(): +% binopLit16(instr="add r0, r0, r1") diff --git a/runtime/interpreter/mterp/arm/op_add_int_lit8.S b/runtime/interpreter/mterp/arm/op_add_int_lit8.S index 035510d062..4393e66861 100644 --- a/runtime/interpreter/mterp/arm/op_add_int_lit8.S +++ b/runtime/interpreter/mterp/arm/op_add_int_lit8.S @@ -1 +1,2 @@ -%include "arm/binopLit8.S" {"extract":"", "instr":"add r0, r0, r3, asr #8"} +%def op_add_int_lit8(): +% binopLit8(extract="", instr="add r0, r0, r3, asr #8") diff --git a/runtime/interpreter/mterp/arm/op_add_long.S b/runtime/interpreter/mterp/arm/op_add_long.S index 093223e755..88994d40e5 100644 --- a/runtime/interpreter/mterp/arm/op_add_long.S +++ b/runtime/interpreter/mterp/arm/op_add_long.S @@ -1 +1,2 @@ -%include "arm/binopWide.S" {"preinstr":"adds r0, r0, r2", "instr":"adc r1, r1, r3"} +%def op_add_long(): +% binopWide(preinstr="adds r0, r0, r2", instr="adc r1, r1, r3") diff --git a/runtime/interpreter/mterp/arm/op_add_long_2addr.S b/runtime/interpreter/mterp/arm/op_add_long_2addr.S index c11e0aff44..bfe7447c92 100644 --- a/runtime/interpreter/mterp/arm/op_add_long_2addr.S +++ b/runtime/interpreter/mterp/arm/op_add_long_2addr.S @@ -1 +1,2 @@ -%include "arm/binopWide2addr.S" {"preinstr":"adds r0, r0, r2", "instr":"adc r1, r1, r3"} +%def op_add_long_2addr(): +% binopWide2addr(preinstr="adds r0, r0, r2", instr="adc r1, r1, r3") diff --git a/runtime/interpreter/mterp/arm/op_aget.S b/runtime/interpreter/mterp/arm/op_aget.S index 11f7079c3f..bf265b4819 100644 --- a/runtime/interpreter/mterp/arm/op_aget.S +++ b/runtime/interpreter/mterp/arm/op_aget.S @@ -1,4 +1,4 @@ -%default { "load":"ldr", "shift":"2", "data_offset":"MIRROR_INT_ARRAY_DATA_OFFSET" } +%def op_aget(load="ldr", shift="2", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"): /* * Array get, 32 bits or less. vAA <- vBB[vCC]. * diff --git a/runtime/interpreter/mterp/arm/op_aget_boolean.S b/runtime/interpreter/mterp/arm/op_aget_boolean.S index 8f678dc14f..d6e0a1bbd9 100644 --- a/runtime/interpreter/mterp/arm/op_aget_boolean.S +++ b/runtime/interpreter/mterp/arm/op_aget_boolean.S @@ -1 +1,2 @@ -%include "arm/op_aget.S" { "load":"ldrb", "shift":"0", "data_offset":"MIRROR_BOOLEAN_ARRAY_DATA_OFFSET" } +%def op_aget_boolean(): +% op_aget(load="ldrb", shift="0", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/arm/op_aget_byte.S b/runtime/interpreter/mterp/arm/op_aget_byte.S index a304650688..6c9f1b78fa 100644 --- a/runtime/interpreter/mterp/arm/op_aget_byte.S +++ b/runtime/interpreter/mterp/arm/op_aget_byte.S @@ -1 +1,2 @@ -%include "arm/op_aget.S" { "load":"ldrsb", "shift":"0", "data_offset":"MIRROR_BYTE_ARRAY_DATA_OFFSET" } +%def op_aget_byte(): +% op_aget(load="ldrsb", shift="0", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/arm/op_aget_char.S b/runtime/interpreter/mterp/arm/op_aget_char.S index 490830620e..c5812e3aff 100644 --- a/runtime/interpreter/mterp/arm/op_aget_char.S +++ b/runtime/interpreter/mterp/arm/op_aget_char.S @@ -1 +1,2 @@ -%include "arm/op_aget.S" { "load":"ldrh", "shift":"1", "data_offset":"MIRROR_CHAR_ARRAY_DATA_OFFSET" } +%def op_aget_char(): +% op_aget(load="ldrh", shift="1", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/arm/op_aget_object.S b/runtime/interpreter/mterp/arm/op_aget_object.S index 4e0aab5d13..3b25086dce 100644 --- a/runtime/interpreter/mterp/arm/op_aget_object.S +++ b/runtime/interpreter/mterp/arm/op_aget_object.S @@ -1,3 +1,4 @@ +%def op_aget_object(): /* * Array object get. vAA <- vBB[vCC]. * diff --git a/runtime/interpreter/mterp/arm/op_aget_short.S b/runtime/interpreter/mterp/arm/op_aget_short.S index b71e659a4a..9727560fe4 100644 --- a/runtime/interpreter/mterp/arm/op_aget_short.S +++ b/runtime/interpreter/mterp/arm/op_aget_short.S @@ -1 +1,2 @@ -%include "arm/op_aget.S" { "load":"ldrsh", "shift":"1", "data_offset":"MIRROR_SHORT_ARRAY_DATA_OFFSET" } +%def op_aget_short(): +% op_aget(load="ldrsh", shift="1", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/arm/op_aget_wide.S b/runtime/interpreter/mterp/arm/op_aget_wide.S index 66ec950531..28437e71f2 100644 --- a/runtime/interpreter/mterp/arm/op_aget_wide.S +++ b/runtime/interpreter/mterp/arm/op_aget_wide.S @@ -1,3 +1,4 @@ +%def op_aget_wide(): /* * Array get, 64 bits. vAA <- vBB[vCC]. * diff --git a/runtime/interpreter/mterp/arm/op_and_int.S b/runtime/interpreter/mterp/arm/op_and_int.S index 7c16d376be..ac0ae6670d 100644 --- a/runtime/interpreter/mterp/arm/op_and_int.S +++ b/runtime/interpreter/mterp/arm/op_and_int.S @@ -1 +1,2 @@ -%include "arm/binop.S" {"instr":"and r0, r0, r1"} +%def op_and_int(): +% binop(instr="and r0, r0, r1") diff --git a/runtime/interpreter/mterp/arm/op_and_int_2addr.S b/runtime/interpreter/mterp/arm/op_and_int_2addr.S index 0fbab02863..28a668a1a0 100644 --- a/runtime/interpreter/mterp/arm/op_and_int_2addr.S +++ b/runtime/interpreter/mterp/arm/op_and_int_2addr.S @@ -1 +1,2 @@ -%include "arm/binop2addr.S" {"instr":"and r0, r0, r1"} +%def op_and_int_2addr(): +% binop2addr(instr="and r0, r0, r1") diff --git a/runtime/interpreter/mterp/arm/op_and_int_lit16.S b/runtime/interpreter/mterp/arm/op_and_int_lit16.S index 541e9b7814..4b9a4c947a 100644 --- a/runtime/interpreter/mterp/arm/op_and_int_lit16.S +++ b/runtime/interpreter/mterp/arm/op_and_int_lit16.S @@ -1 +1,2 @@ -%include "arm/binopLit16.S" {"instr":"and r0, r0, r1"} +%def op_and_int_lit16(): +% binopLit16(instr="and r0, r0, r1") diff --git a/runtime/interpreter/mterp/arm/op_and_int_lit8.S b/runtime/interpreter/mterp/arm/op_and_int_lit8.S index af746b5447..b26bfe4227 100644 --- a/runtime/interpreter/mterp/arm/op_and_int_lit8.S +++ b/runtime/interpreter/mterp/arm/op_and_int_lit8.S @@ -1 +1,2 @@ -%include "arm/binopLit8.S" {"extract":"", "instr":"and r0, r0, r3, asr #8"} +%def op_and_int_lit8(): +% binopLit8(extract="", instr="and r0, r0, r3, asr #8") diff --git a/runtime/interpreter/mterp/arm/op_and_long.S b/runtime/interpreter/mterp/arm/op_and_long.S index 4ad5158da7..3af7897fb2 100644 --- a/runtime/interpreter/mterp/arm/op_and_long.S +++ b/runtime/interpreter/mterp/arm/op_and_long.S @@ -1 +1,2 @@ -%include "arm/binopWide.S" {"preinstr":"and r0, r0, r2", "instr":"and r1, r1, r3"} +%def op_and_long(): +% binopWide(preinstr="and r0, r0, r2", instr="and r1, r1, r3") diff --git a/runtime/interpreter/mterp/arm/op_and_long_2addr.S b/runtime/interpreter/mterp/arm/op_and_long_2addr.S index e23ea447ba..78e5d88162 100644 --- a/runtime/interpreter/mterp/arm/op_and_long_2addr.S +++ b/runtime/interpreter/mterp/arm/op_and_long_2addr.S @@ -1 +1,2 @@ -%include "arm/binopWide2addr.S" {"preinstr":"and r0, r0, r2", "instr":"and r1, r1, r3"} +%def op_and_long_2addr(): +% binopWide2addr(preinstr="and r0, r0, r2", instr="and r1, r1, r3") diff --git a/runtime/interpreter/mterp/arm/op_aput.S b/runtime/interpreter/mterp/arm/op_aput.S index a511fa59e0..7b5da541f6 100644 --- a/runtime/interpreter/mterp/arm/op_aput.S +++ b/runtime/interpreter/mterp/arm/op_aput.S @@ -1,4 +1,4 @@ -%default { "store":"str", "shift":"2", "data_offset":"MIRROR_INT_ARRAY_DATA_OFFSET" } +%def op_aput(store="str", shift="2", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"): /* * Array put, 32 bits or less. vBB[vCC] <- vAA. * diff --git a/runtime/interpreter/mterp/arm/op_aput_boolean.S b/runtime/interpreter/mterp/arm/op_aput_boolean.S index e86663f199..467cc4bf20 100644 --- a/runtime/interpreter/mterp/arm/op_aput_boolean.S +++ b/runtime/interpreter/mterp/arm/op_aput_boolean.S @@ -1 +1,2 @@ -%include "arm/op_aput.S" { "store":"strb", "shift":"0", "data_offset":"MIRROR_BOOLEAN_ARRAY_DATA_OFFSET" } +%def op_aput_boolean(): +% op_aput(store="strb", shift="0", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/arm/op_aput_byte.S b/runtime/interpreter/mterp/arm/op_aput_byte.S index 83694b788d..2b4c0ba389 100644 --- a/runtime/interpreter/mterp/arm/op_aput_byte.S +++ b/runtime/interpreter/mterp/arm/op_aput_byte.S @@ -1 +1,2 @@ -%include "arm/op_aput.S" { "store":"strb", "shift":"0", "data_offset":"MIRROR_BYTE_ARRAY_DATA_OFFSET" } +%def op_aput_byte(): +% op_aput(store="strb", shift="0", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/arm/op_aput_char.S b/runtime/interpreter/mterp/arm/op_aput_char.S index 3551cace33..cb7dcbad4d 100644 --- a/runtime/interpreter/mterp/arm/op_aput_char.S +++ b/runtime/interpreter/mterp/arm/op_aput_char.S @@ -1 +1,2 @@ -%include "arm/op_aput.S" { "store":"strh", "shift":"1", "data_offset":"MIRROR_CHAR_ARRAY_DATA_OFFSET" } +%def op_aput_char(): +% op_aput(store="strh", shift="1", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/arm/op_aput_object.S b/runtime/interpreter/mterp/arm/op_aput_object.S index c5399163e3..83b7e5a2fb 100644 --- a/runtime/interpreter/mterp/arm/op_aput_object.S +++ b/runtime/interpreter/mterp/arm/op_aput_object.S @@ -1,3 +1,4 @@ +%def op_aput_object(): /* * Store an object into an array. vBB[vCC] <- vAA. */ diff --git a/runtime/interpreter/mterp/arm/op_aput_short.S b/runtime/interpreter/mterp/arm/op_aput_short.S index 0a0590ec36..f624163087 100644 --- a/runtime/interpreter/mterp/arm/op_aput_short.S +++ b/runtime/interpreter/mterp/arm/op_aput_short.S @@ -1 +1,2 @@ -%include "arm/op_aput.S" { "store":"strh", "shift":"1", "data_offset":"MIRROR_SHORT_ARRAY_DATA_OFFSET" } +%def op_aput_short(): +% op_aput(store="strh", shift="1", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/arm/op_aput_wide.S b/runtime/interpreter/mterp/arm/op_aput_wide.S index 005750752f..769522a5ec 100644 --- a/runtime/interpreter/mterp/arm/op_aput_wide.S +++ b/runtime/interpreter/mterp/arm/op_aput_wide.S @@ -1,3 +1,4 @@ +%def op_aput_wide(): /* * Array put, 64 bits. vBB[vCC] <- vAA. * diff --git a/runtime/interpreter/mterp/arm/op_array_length.S b/runtime/interpreter/mterp/arm/op_array_length.S index 43b1682a9d..3ec24b8a3b 100644 --- a/runtime/interpreter/mterp/arm/op_array_length.S +++ b/runtime/interpreter/mterp/arm/op_array_length.S @@ -1,3 +1,4 @@ +%def op_array_length(): /* * Return the length of an array. */ diff --git a/runtime/interpreter/mterp/arm/op_check_cast.S b/runtime/interpreter/mterp/arm/op_check_cast.S index 24eba45a69..a56451b5df 100644 --- a/runtime/interpreter/mterp/arm/op_check_cast.S +++ b/runtime/interpreter/mterp/arm/op_check_cast.S @@ -1,3 +1,4 @@ +%def op_check_cast(): /* * Check to see if a cast from one class to another is allowed. */ diff --git a/runtime/interpreter/mterp/arm/op_cmp_long.S b/runtime/interpreter/mterp/arm/op_cmp_long.S index 6626ff0f49..2f87716df7 100644 --- a/runtime/interpreter/mterp/arm/op_cmp_long.S +++ b/runtime/interpreter/mterp/arm/op_cmp_long.S @@ -1,3 +1,4 @@ +%def op_cmp_long(): /* * Compare two 64-bit values. Puts 0, 1, or -1 into the destination * register based on the results of the comparison. diff --git a/runtime/interpreter/mterp/arm/op_cmpg_double.S b/runtime/interpreter/mterp/arm/op_cmpg_double.S index 602a4b1bfd..a166d16256 100644 --- a/runtime/interpreter/mterp/arm/op_cmpg_double.S +++ b/runtime/interpreter/mterp/arm/op_cmpg_double.S @@ -1,3 +1,4 @@ +%def op_cmpg_double(): /* * Compare two floating-point values. Puts 0, 1, or -1 into the * destination register based on the results of the comparison. diff --git a/runtime/interpreter/mterp/arm/op_cmpg_float.S b/runtime/interpreter/mterp/arm/op_cmpg_float.S index 965091f82d..e14f4ec1a2 100644 --- a/runtime/interpreter/mterp/arm/op_cmpg_float.S +++ b/runtime/interpreter/mterp/arm/op_cmpg_float.S @@ -1,3 +1,4 @@ +%def op_cmpg_float(): /* * Compare two floating-point values. Puts 0, 1, or -1 into the * destination register based on the results of the comparison. diff --git a/runtime/interpreter/mterp/arm/op_cmpl_double.S b/runtime/interpreter/mterp/arm/op_cmpl_double.S index 8a5e509ee8..44c827a9a3 100644 --- a/runtime/interpreter/mterp/arm/op_cmpl_double.S +++ b/runtime/interpreter/mterp/arm/op_cmpl_double.S @@ -1,3 +1,4 @@ +%def op_cmpl_double(): /* * Compare two floating-point values. Puts 0, 1, or -1 into the * destination register based on the results of the comparison. diff --git a/runtime/interpreter/mterp/arm/op_cmpl_float.S b/runtime/interpreter/mterp/arm/op_cmpl_float.S index 9df0c2c171..c2026634e2 100644 --- a/runtime/interpreter/mterp/arm/op_cmpl_float.S +++ b/runtime/interpreter/mterp/arm/op_cmpl_float.S @@ -1,3 +1,4 @@ +%def op_cmpl_float(): /* * Compare two floating-point values. Puts 0, 1, or -1 into the * destination register based on the results of the comparison. diff --git a/runtime/interpreter/mterp/arm/op_const.S b/runtime/interpreter/mterp/arm/op_const.S index 39890a085a..e5ef50e912 100644 --- a/runtime/interpreter/mterp/arm/op_const.S +++ b/runtime/interpreter/mterp/arm/op_const.S @@ -1,3 +1,4 @@ +%def op_const(): /* const vAA, #+BBBBbbbb */ mov r3, rINST, lsr #8 @ r3<- AA FETCH r0, 1 @ r0<- bbbb (low) diff --git a/runtime/interpreter/mterp/arm/op_const_16.S b/runtime/interpreter/mterp/arm/op_const_16.S index a30cf3a0db..3bb89d08ad 100644 --- a/runtime/interpreter/mterp/arm/op_const_16.S +++ b/runtime/interpreter/mterp/arm/op_const_16.S @@ -1,3 +1,4 @@ +%def op_const_16(): /* const/16 vAA, #+BBBB */ FETCH_S r0, 1 @ r0<- ssssBBBB (sign-extended) mov r3, rINST, lsr #8 @ r3<- AA diff --git a/runtime/interpreter/mterp/arm/op_const_4.S b/runtime/interpreter/mterp/arm/op_const_4.S index c97b0e91f5..bfb4246b0b 100644 --- a/runtime/interpreter/mterp/arm/op_const_4.S +++ b/runtime/interpreter/mterp/arm/op_const_4.S @@ -1,3 +1,4 @@ +%def op_const_4(): /* const/4 vA, #+B */ sbfx r1, rINST, #12, #4 @ r1<- sssssssB (sign-extended) ubfx r0, rINST, #8, #4 @ r0<- A diff --git a/runtime/interpreter/mterp/arm/op_const_class.S b/runtime/interpreter/mterp/arm/op_const_class.S index ff5c98c743..db12ec3141 100644 --- a/runtime/interpreter/mterp/arm/op_const_class.S +++ b/runtime/interpreter/mterp/arm/op_const_class.S @@ -1 +1,2 @@ -%include "arm/const.S" { "helper":"MterpConstClass" } +%def op_const_class(): +% const(helper="MterpConstClass") diff --git a/runtime/interpreter/mterp/arm/op_const_high16.S b/runtime/interpreter/mterp/arm/op_const_high16.S index 536276d52d..7f20e11f4c 100644 --- a/runtime/interpreter/mterp/arm/op_const_high16.S +++ b/runtime/interpreter/mterp/arm/op_const_high16.S @@ -1,3 +1,4 @@ +%def op_const_high16(): /* const/high16 vAA, #+BBBB0000 */ FETCH r0, 1 @ r0<- 0000BBBB (zero-extended) mov r3, rINST, lsr #8 @ r3<- AA diff --git a/runtime/interpreter/mterp/arm/op_const_method_handle.S b/runtime/interpreter/mterp/arm/op_const_method_handle.S index 71f05501e7..2680c17aad 100644 --- a/runtime/interpreter/mterp/arm/op_const_method_handle.S +++ b/runtime/interpreter/mterp/arm/op_const_method_handle.S @@ -1 +1,2 @@ -%include "arm/const.S" { "helper":"MterpConstMethodHandle" } +%def op_const_method_handle(): +% const(helper="MterpConstMethodHandle") diff --git a/runtime/interpreter/mterp/arm/op_const_method_type.S b/runtime/interpreter/mterp/arm/op_const_method_type.S index 2cccdafef4..ea814bf648 100644 --- a/runtime/interpreter/mterp/arm/op_const_method_type.S +++ b/runtime/interpreter/mterp/arm/op_const_method_type.S @@ -1 +1,2 @@ -%include "arm/const.S" { "helper":"MterpConstMethodType" } +%def op_const_method_type(): +% const(helper="MterpConstMethodType") diff --git a/runtime/interpreter/mterp/arm/op_const_string.S b/runtime/interpreter/mterp/arm/op_const_string.S index 75ec34ffb4..41376f8703 100644 --- a/runtime/interpreter/mterp/arm/op_const_string.S +++ b/runtime/interpreter/mterp/arm/op_const_string.S @@ -1 +1,2 @@ -%include "arm/const.S" { "helper":"MterpConstString" } +%def op_const_string(): +% const(helper="MterpConstString") diff --git a/runtime/interpreter/mterp/arm/op_const_string_jumbo.S b/runtime/interpreter/mterp/arm/op_const_string_jumbo.S index 1255c0768d..29c9854f44 100644 --- a/runtime/interpreter/mterp/arm/op_const_string_jumbo.S +++ b/runtime/interpreter/mterp/arm/op_const_string_jumbo.S @@ -1,3 +1,4 @@ +%def op_const_string_jumbo(): /* const/string vAA, String@BBBBBBBB */ EXPORT_PC FETCH r0, 1 @ r0<- bbbb (low) diff --git a/runtime/interpreter/mterp/arm/op_const_wide.S b/runtime/interpreter/mterp/arm/op_const_wide.S index 8310a4c129..40bac6d72b 100644 --- a/runtime/interpreter/mterp/arm/op_const_wide.S +++ b/runtime/interpreter/mterp/arm/op_const_wide.S @@ -1,3 +1,4 @@ +%def op_const_wide(): /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ FETCH r0, 1 @ r0<- bbbb (low) FETCH r1, 2 @ r1<- BBBB (low middle) diff --git a/runtime/interpreter/mterp/arm/op_const_wide_16.S b/runtime/interpreter/mterp/arm/op_const_wide_16.S index 28abb512f0..7d334c997f 100644 --- a/runtime/interpreter/mterp/arm/op_const_wide_16.S +++ b/runtime/interpreter/mterp/arm/op_const_wide_16.S @@ -1,3 +1,4 @@ +%def op_const_wide_16(): /* const-wide/16 vAA, #+BBBB */ FETCH_S r0, 1 @ r0<- ssssBBBB (sign-extended) mov r3, rINST, lsr #8 @ r3<- AA diff --git a/runtime/interpreter/mterp/arm/op_const_wide_32.S b/runtime/interpreter/mterp/arm/op_const_wide_32.S index c10bb0461a..eeb5fa510e 100644 --- a/runtime/interpreter/mterp/arm/op_const_wide_32.S +++ b/runtime/interpreter/mterp/arm/op_const_wide_32.S @@ -1,3 +1,4 @@ +%def op_const_wide_32(): /* const-wide/32 vAA, #+BBBBbbbb */ FETCH r0, 1 @ r0<- 0000bbbb (low) mov r3, rINST, lsr #8 @ r3<- AA diff --git a/runtime/interpreter/mterp/arm/op_const_wide_high16.S b/runtime/interpreter/mterp/arm/op_const_wide_high16.S index d7e38ecc20..57ce0242a1 100644 --- a/runtime/interpreter/mterp/arm/op_const_wide_high16.S +++ b/runtime/interpreter/mterp/arm/op_const_wide_high16.S @@ -1,3 +1,4 @@ +%def op_const_wide_high16(): /* const-wide/high16 vAA, #+BBBB000000000000 */ FETCH r1, 1 @ r1<- 0000BBBB (zero-extended) mov r3, rINST, lsr #8 @ r3<- AA diff --git a/runtime/interpreter/mterp/arm/op_div_double.S b/runtime/interpreter/mterp/arm/op_div_double.S index 5147550b97..d90969495d 100644 --- a/runtime/interpreter/mterp/arm/op_div_double.S +++ b/runtime/interpreter/mterp/arm/op_div_double.S @@ -1 +1,2 @@ -%include "arm/fbinopWide.S" {"instr":"fdivd d2, d0, d1"} +%def op_div_double(): +% fbinopWide(instr="fdivd d2, d0, d1") diff --git a/runtime/interpreter/mterp/arm/op_div_double_2addr.S b/runtime/interpreter/mterp/arm/op_div_double_2addr.S index b812f17ac9..499c87b1e6 100644 --- a/runtime/interpreter/mterp/arm/op_div_double_2addr.S +++ b/runtime/interpreter/mterp/arm/op_div_double_2addr.S @@ -1 +1,2 @@ -%include "arm/fbinopWide2addr.S" {"instr":"fdivd d2, d0, d1"} +%def op_div_double_2addr(): +% fbinopWide2addr(instr="fdivd d2, d0, d1") diff --git a/runtime/interpreter/mterp/arm/op_div_float.S b/runtime/interpreter/mterp/arm/op_div_float.S index 0f24d11e54..11369095be 100644 --- a/runtime/interpreter/mterp/arm/op_div_float.S +++ b/runtime/interpreter/mterp/arm/op_div_float.S @@ -1 +1,2 @@ -%include "arm/fbinop.S" {"instr":"fdivs s2, s0, s1"} +%def op_div_float(): +% fbinop(instr="fdivs s2, s0, s1") diff --git a/runtime/interpreter/mterp/arm/op_div_float_2addr.S b/runtime/interpreter/mterp/arm/op_div_float_2addr.S index a1dbf01713..5198bc778f 100644 --- a/runtime/interpreter/mterp/arm/op_div_float_2addr.S +++ b/runtime/interpreter/mterp/arm/op_div_float_2addr.S @@ -1 +1,2 @@ -%include "arm/fbinop2addr.S" {"instr":"fdivs s2, s0, s1"} +%def op_div_float_2addr(): +% fbinop2addr(instr="fdivs s2, s0, s1") diff --git a/runtime/interpreter/mterp/arm/op_div_int.S b/runtime/interpreter/mterp/arm/op_div_int.S index 251064be0d..211ac77296 100644 --- a/runtime/interpreter/mterp/arm/op_div_int.S +++ b/runtime/interpreter/mterp/arm/op_div_int.S @@ -1,4 +1,4 @@ -%default {} +%def op_div_int(): /* * Specialized 32-bit binary operation * diff --git a/runtime/interpreter/mterp/arm/op_div_int_2addr.S b/runtime/interpreter/mterp/arm/op_div_int_2addr.S index 9be4cd8b14..968a4991fa 100644 --- a/runtime/interpreter/mterp/arm/op_div_int_2addr.S +++ b/runtime/interpreter/mterp/arm/op_div_int_2addr.S @@ -1,4 +1,4 @@ -%default {} +%def op_div_int_2addr(): /* * Specialized 32-bit binary operation * diff --git a/runtime/interpreter/mterp/arm/op_div_int_lit16.S b/runtime/interpreter/mterp/arm/op_div_int_lit16.S index d9bc7d65ce..f1e21269c7 100644 --- a/runtime/interpreter/mterp/arm/op_div_int_lit16.S +++ b/runtime/interpreter/mterp/arm/op_div_int_lit16.S @@ -1,4 +1,4 @@ -%default {} +%def op_div_int_lit16(): /* * Specialized 32-bit binary operation * diff --git a/runtime/interpreter/mterp/arm/op_div_int_lit8.S b/runtime/interpreter/mterp/arm/op_div_int_lit8.S index 5d2dbd3ecb..e0d88f80df 100644 --- a/runtime/interpreter/mterp/arm/op_div_int_lit8.S +++ b/runtime/interpreter/mterp/arm/op_div_int_lit8.S @@ -1,4 +1,4 @@ -%default {} +%def op_div_int_lit8(): /* * Specialized 32-bit binary operation * diff --git a/runtime/interpreter/mterp/arm/op_div_long.S b/runtime/interpreter/mterp/arm/op_div_long.S index 0f21a845d4..7423f5bfa8 100644 --- a/runtime/interpreter/mterp/arm/op_div_long.S +++ b/runtime/interpreter/mterp/arm/op_div_long.S @@ -1 +1,2 @@ -%include "arm/binopWide.S" {"instr":"bl __aeabi_ldivmod", "chkzero":"1"} +%def op_div_long(): +% binopWide(instr="bl __aeabi_ldivmod", chkzero="1") diff --git a/runtime/interpreter/mterp/arm/op_div_long_2addr.S b/runtime/interpreter/mterp/arm/op_div_long_2addr.S index e172b29496..fed8b8f3d7 100644 --- a/runtime/interpreter/mterp/arm/op_div_long_2addr.S +++ b/runtime/interpreter/mterp/arm/op_div_long_2addr.S @@ -1 +1,2 @@ -%include "arm/binopWide2addr.S" {"instr":"bl __aeabi_ldivmod", "chkzero":"1"} +%def op_div_long_2addr(): +% binopWide2addr(instr="bl __aeabi_ldivmod", chkzero="1") diff --git a/runtime/interpreter/mterp/arm/op_double_to_float.S b/runtime/interpreter/mterp/arm/op_double_to_float.S index 98fdfbc64e..dcd575e3f1 100644 --- a/runtime/interpreter/mterp/arm/op_double_to_float.S +++ b/runtime/interpreter/mterp/arm/op_double_to_float.S @@ -1 +1,2 @@ -%include "arm/funopNarrower.S" {"instr":"vcvt.f32.f64 s0, d0"} +%def op_double_to_float(): +% funopNarrower(instr="vcvt.f32.f64 s0, d0") diff --git a/runtime/interpreter/mterp/arm/op_double_to_int.S b/runtime/interpreter/mterp/arm/op_double_to_int.S index aa035de63a..e11daad495 100644 --- a/runtime/interpreter/mterp/arm/op_double_to_int.S +++ b/runtime/interpreter/mterp/arm/op_double_to_int.S @@ -1 +1,2 @@ -%include "arm/funopNarrower.S" {"instr":"ftosizd s0, d0"} +%def op_double_to_int(): +% funopNarrower(instr="ftosizd s0, d0") diff --git a/runtime/interpreter/mterp/arm/op_double_to_long.S b/runtime/interpreter/mterp/arm/op_double_to_long.S index 19ff7235e0..c47570430e 100644 --- a/runtime/interpreter/mterp/arm/op_double_to_long.S +++ b/runtime/interpreter/mterp/arm/op_double_to_long.S @@ -1,6 +1,7 @@ -%include "arm/unopWide.S" {"instr":"bl d2l_doconv"} +%def op_double_to_long(): +% unopWide(instr="bl d2l_doconv") -%break +%def op_double_to_long_sister_code(): /* * Convert the double in r0/r1 to a long in r0/r1. * diff --git a/runtime/interpreter/mterp/arm/op_fill_array_data.S b/runtime/interpreter/mterp/arm/op_fill_array_data.S index e1ca85c866..ea0d39724d 100644 --- a/runtime/interpreter/mterp/arm/op_fill_array_data.S +++ b/runtime/interpreter/mterp/arm/op_fill_array_data.S @@ -1,3 +1,4 @@ +%def op_fill_array_data(): /* fill-array-data vAA, +BBBBBBBB */ EXPORT_PC FETCH r0, 1 @ r0<- bbbb (lo) diff --git a/runtime/interpreter/mterp/arm/op_filled_new_array.S b/runtime/interpreter/mterp/arm/op_filled_new_array.S index 1075f0c683..fb1c3c5dc3 100644 --- a/runtime/interpreter/mterp/arm/op_filled_new_array.S +++ b/runtime/interpreter/mterp/arm/op_filled_new_array.S @@ -1,4 +1,4 @@ -%default { "helper":"MterpFilledNewArray" } +%def op_filled_new_array(helper="MterpFilledNewArray"): /* * Create a new array with elements filled from registers. * diff --git a/runtime/interpreter/mterp/arm/op_filled_new_array_range.S b/runtime/interpreter/mterp/arm/op_filled_new_array_range.S index 16567af567..1667de149a 100644 --- a/runtime/interpreter/mterp/arm/op_filled_new_array_range.S +++ b/runtime/interpreter/mterp/arm/op_filled_new_array_range.S @@ -1 +1,2 @@ -%include "arm/op_filled_new_array.S" { "helper":"MterpFilledNewArrayRange" } +%def op_filled_new_array_range(): +% op_filled_new_array(helper="MterpFilledNewArrayRange") diff --git a/runtime/interpreter/mterp/arm/op_float_to_double.S b/runtime/interpreter/mterp/arm/op_float_to_double.S index b1e12bdc7a..760466eec9 100644 --- a/runtime/interpreter/mterp/arm/op_float_to_double.S +++ b/runtime/interpreter/mterp/arm/op_float_to_double.S @@ -1 +1,2 @@ -%include "arm/funopWider.S" {"instr":"vcvt.f64.f32 d0, s0"} +%def op_float_to_double(): +% funopWider(instr="vcvt.f64.f32 d0, s0") diff --git a/runtime/interpreter/mterp/arm/op_float_to_int.S b/runtime/interpreter/mterp/arm/op_float_to_int.S index aab87167bb..77837ba3d5 100644 --- a/runtime/interpreter/mterp/arm/op_float_to_int.S +++ b/runtime/interpreter/mterp/arm/op_float_to_int.S @@ -1 +1,2 @@ -%include "arm/funop.S" {"instr":"ftosizs s1, s0"} +%def op_float_to_int(): +% funop(instr="ftosizs s1, s0") diff --git a/runtime/interpreter/mterp/arm/op_float_to_long.S b/runtime/interpreter/mterp/arm/op_float_to_long.S index 42bd98dbc2..482b18e69f 100644 --- a/runtime/interpreter/mterp/arm/op_float_to_long.S +++ b/runtime/interpreter/mterp/arm/op_float_to_long.S @@ -1,6 +1,7 @@ -%include "arm/unopWider.S" {"instr":"bl f2l_doconv"} +%def op_float_to_long(): +% unopWider(instr="bl f2l_doconv") -%break +%def op_float_to_long_sister_code(): /* * Convert the float in r0 to a long in r0/r1. * diff --git a/runtime/interpreter/mterp/arm/op_goto.S b/runtime/interpreter/mterp/arm/op_goto.S index aa42dfd843..832a989339 100644 --- a/runtime/interpreter/mterp/arm/op_goto.S +++ b/runtime/interpreter/mterp/arm/op_goto.S @@ -1,3 +1,4 @@ +%def op_goto(): /* * Unconditional branch, 8-bit offset. * diff --git a/runtime/interpreter/mterp/arm/op_goto_16.S b/runtime/interpreter/mterp/arm/op_goto_16.S index 12a6bc07f8..4324a8d666 100644 --- a/runtime/interpreter/mterp/arm/op_goto_16.S +++ b/runtime/interpreter/mterp/arm/op_goto_16.S @@ -1,3 +1,4 @@ +%def op_goto_16(): /* * Unconditional branch, 16-bit offset. * diff --git a/runtime/interpreter/mterp/arm/op_goto_32.S b/runtime/interpreter/mterp/arm/op_goto_32.S index 7325a1c2d6..b01d2fa719 100644 --- a/runtime/interpreter/mterp/arm/op_goto_32.S +++ b/runtime/interpreter/mterp/arm/op_goto_32.S @@ -1,3 +1,4 @@ +%def op_goto_32(): /* * Unconditional branch, 32-bit offset. * diff --git a/runtime/interpreter/mterp/arm/op_if_eq.S b/runtime/interpreter/mterp/arm/op_if_eq.S index b8b6a6eec1..da58674fd4 100644 --- a/runtime/interpreter/mterp/arm/op_if_eq.S +++ b/runtime/interpreter/mterp/arm/op_if_eq.S @@ -1 +1,2 @@ -%include "arm/bincmp.S" { "condition":"eq" } +%def op_if_eq(): +% bincmp(condition="eq") diff --git a/runtime/interpreter/mterp/arm/op_if_eqz.S b/runtime/interpreter/mterp/arm/op_if_eqz.S index 7012f61c69..0639664d47 100644 --- a/runtime/interpreter/mterp/arm/op_if_eqz.S +++ b/runtime/interpreter/mterp/arm/op_if_eqz.S @@ -1 +1,2 @@ -%include "arm/zcmp.S" { "condition":"eq" } +%def op_if_eqz(): +% zcmp(condition="eq") diff --git a/runtime/interpreter/mterp/arm/op_if_ge.S b/runtime/interpreter/mterp/arm/op_if_ge.S index eb29e63f7c..5b6ed2f994 100644 --- a/runtime/interpreter/mterp/arm/op_if_ge.S +++ b/runtime/interpreter/mterp/arm/op_if_ge.S @@ -1 +1,2 @@ -%include "arm/bincmp.S" { "condition":"ge" } +%def op_if_ge(): +% bincmp(condition="ge") diff --git a/runtime/interpreter/mterp/arm/op_if_gez.S b/runtime/interpreter/mterp/arm/op_if_gez.S index d9da374199..ea6cda71fb 100644 --- a/runtime/interpreter/mterp/arm/op_if_gez.S +++ b/runtime/interpreter/mterp/arm/op_if_gez.S @@ -1 +1,2 @@ -%include "arm/zcmp.S" { "condition":"ge" } +%def op_if_gez(): +% zcmp(condition="ge") diff --git a/runtime/interpreter/mterp/arm/op_if_gt.S b/runtime/interpreter/mterp/arm/op_if_gt.S index a35eab8f47..201decff1a 100644 --- a/runtime/interpreter/mterp/arm/op_if_gt.S +++ b/runtime/interpreter/mterp/arm/op_if_gt.S @@ -1 +1,2 @@ -%include "arm/bincmp.S" { "condition":"gt" } +%def op_if_gt(): +% bincmp(condition="gt") diff --git a/runtime/interpreter/mterp/arm/op_if_gtz.S b/runtime/interpreter/mterp/arm/op_if_gtz.S index 4ef4d8ee19..1fdbb6e8d2 100644 --- a/runtime/interpreter/mterp/arm/op_if_gtz.S +++ b/runtime/interpreter/mterp/arm/op_if_gtz.S @@ -1 +1,2 @@ -%include "arm/zcmp.S" { "condition":"gt" } +%def op_if_gtz(): +% zcmp(condition="gt") diff --git a/runtime/interpreter/mterp/arm/op_if_le.S b/runtime/interpreter/mterp/arm/op_if_le.S index c7c31bc089..e6024f2b3e 100644 --- a/runtime/interpreter/mterp/arm/op_if_le.S +++ b/runtime/interpreter/mterp/arm/op_if_le.S @@ -1 +1,2 @@ -%include "arm/bincmp.S" { "condition":"le" } +%def op_if_le(): +% bincmp(condition="le") diff --git a/runtime/interpreter/mterp/arm/op_if_lez.S b/runtime/interpreter/mterp/arm/op_if_lez.S index 9fbf6c9f02..62c0d2cd39 100644 --- a/runtime/interpreter/mterp/arm/op_if_lez.S +++ b/runtime/interpreter/mterp/arm/op_if_lez.S @@ -1 +1,2 @@ -%include "arm/zcmp.S" { "condition":"le" } +%def op_if_lez(): +% zcmp(condition="le") diff --git a/runtime/interpreter/mterp/arm/op_if_lt.S b/runtime/interpreter/mterp/arm/op_if_lt.S index 9469fbb1ef..4ef22fd798 100644 --- a/runtime/interpreter/mterp/arm/op_if_lt.S +++ b/runtime/interpreter/mterp/arm/op_if_lt.S @@ -1 +1,2 @@ -%include "arm/bincmp.S" { "condition":"lt" } +%def op_if_lt(): +% bincmp(condition="lt") diff --git a/runtime/interpreter/mterp/arm/op_if_ltz.S b/runtime/interpreter/mterp/arm/op_if_ltz.S index a4fc1b8f0b..84b2d0b53a 100644 --- a/runtime/interpreter/mterp/arm/op_if_ltz.S +++ b/runtime/interpreter/mterp/arm/op_if_ltz.S @@ -1 +1,2 @@ -%include "arm/zcmp.S" { "condition":"lt" } +%def op_if_ltz(): +% zcmp(condition="lt") diff --git a/runtime/interpreter/mterp/arm/op_if_ne.S b/runtime/interpreter/mterp/arm/op_if_ne.S index c945331a31..ec3a688b29 100644 --- a/runtime/interpreter/mterp/arm/op_if_ne.S +++ b/runtime/interpreter/mterp/arm/op_if_ne.S @@ -1 +1,2 @@ -%include "arm/bincmp.S" { "condition":"ne" } +%def op_if_ne(): +% bincmp(condition="ne") diff --git a/runtime/interpreter/mterp/arm/op_if_nez.S b/runtime/interpreter/mterp/arm/op_if_nez.S index 2d81fda444..7009c3acaa 100644 --- a/runtime/interpreter/mterp/arm/op_if_nez.S +++ b/runtime/interpreter/mterp/arm/op_if_nez.S @@ -1 +1,2 @@ -%include "arm/zcmp.S" { "condition":"ne" } +%def op_if_nez(): +% zcmp(condition="ne") diff --git a/runtime/interpreter/mterp/arm/op_iget.S b/runtime/interpreter/mterp/arm/op_iget.S index 1fa32faa99..d09edc0a17 100644 --- a/runtime/interpreter/mterp/arm/op_iget.S +++ b/runtime/interpreter/mterp/arm/op_iget.S @@ -1,2 +1,2 @@ -%default { "is_object":"0", "helper":"MterpIGetU32"} -%include "arm/field.S" { } +%def op_iget(is_object="0", helper="MterpIGetU32"): +% field(helper=helper) diff --git a/runtime/interpreter/mterp/arm/op_iget_boolean.S b/runtime/interpreter/mterp/arm/op_iget_boolean.S index f23cb3aa97..cb8edeec77 100644 --- a/runtime/interpreter/mterp/arm/op_iget_boolean.S +++ b/runtime/interpreter/mterp/arm/op_iget_boolean.S @@ -1 +1,2 @@ -%include "arm/op_iget.S" { "helper":"MterpIGetU8" } +%def op_iget_boolean(): +% op_iget(helper="MterpIGetU8") diff --git a/runtime/interpreter/mterp/arm/op_iget_boolean_quick.S b/runtime/interpreter/mterp/arm/op_iget_boolean_quick.S index 0ae4843595..7ac9fce535 100644 --- a/runtime/interpreter/mterp/arm/op_iget_boolean_quick.S +++ b/runtime/interpreter/mterp/arm/op_iget_boolean_quick.S @@ -1 +1,2 @@ -%include "arm/op_iget_quick.S" { "load":"ldrb" } +%def op_iget_boolean_quick(): +% op_iget_quick(load="ldrb") diff --git a/runtime/interpreter/mterp/arm/op_iget_byte.S b/runtime/interpreter/mterp/arm/op_iget_byte.S index 9c4f37c8ac..2b87fb16b5 100644 --- a/runtime/interpreter/mterp/arm/op_iget_byte.S +++ b/runtime/interpreter/mterp/arm/op_iget_byte.S @@ -1 +1,2 @@ -%include "arm/op_iget.S" { "helper":"MterpIGetI8" } +%def op_iget_byte(): +% op_iget(helper="MterpIGetI8") diff --git a/runtime/interpreter/mterp/arm/op_iget_byte_quick.S b/runtime/interpreter/mterp/arm/op_iget_byte_quick.S index e1b3083404..bbccaffe94 100644 --- a/runtime/interpreter/mterp/arm/op_iget_byte_quick.S +++ b/runtime/interpreter/mterp/arm/op_iget_byte_quick.S @@ -1 +1,2 @@ -%include "arm/op_iget_quick.S" { "load":"ldrsb" } +%def op_iget_byte_quick(): +% op_iget_quick(load="ldrsb") diff --git a/runtime/interpreter/mterp/arm/op_iget_char.S b/runtime/interpreter/mterp/arm/op_iget_char.S index 80c4227ed2..001bd03e2b 100644 --- a/runtime/interpreter/mterp/arm/op_iget_char.S +++ b/runtime/interpreter/mterp/arm/op_iget_char.S @@ -1 +1,2 @@ -%include "arm/op_iget.S" { "helper":"MterpIGetU16" } +%def op_iget_char(): +% op_iget(helper="MterpIGetU16") diff --git a/runtime/interpreter/mterp/arm/op_iget_char_quick.S b/runtime/interpreter/mterp/arm/op_iget_char_quick.S index b44d8f14d8..71a9276a81 100644 --- a/runtime/interpreter/mterp/arm/op_iget_char_quick.S +++ b/runtime/interpreter/mterp/arm/op_iget_char_quick.S @@ -1 +1,2 @@ -%include "arm/op_iget_quick.S" { "load":"ldrh" } +%def op_iget_char_quick(): +% op_iget_quick(load="ldrh") diff --git a/runtime/interpreter/mterp/arm/op_iget_object.S b/runtime/interpreter/mterp/arm/op_iget_object.S index e30b129efe..4e5f769547 100644 --- a/runtime/interpreter/mterp/arm/op_iget_object.S +++ b/runtime/interpreter/mterp/arm/op_iget_object.S @@ -1 +1,2 @@ -%include "arm/op_iget.S" { "is_object":"1", "helper":"MterpIGetObj" } +%def op_iget_object(): +% op_iget(is_object="1", helper="MterpIGetObj") diff --git a/runtime/interpreter/mterp/arm/op_iget_object_quick.S b/runtime/interpreter/mterp/arm/op_iget_object_quick.S index 16cb1189ad..72b04b8bb0 100644 --- a/runtime/interpreter/mterp/arm/op_iget_object_quick.S +++ b/runtime/interpreter/mterp/arm/op_iget_object_quick.S @@ -1,3 +1,4 @@ +%def op_iget_object_quick(): /* For: iget-object-quick */ /* op vA, vB, offset@CCCC */ mov r2, rINST, lsr #12 @ r2<- B diff --git a/runtime/interpreter/mterp/arm/op_iget_quick.S b/runtime/interpreter/mterp/arm/op_iget_quick.S index 0eaf364f6b..989449867d 100644 --- a/runtime/interpreter/mterp/arm/op_iget_quick.S +++ b/runtime/interpreter/mterp/arm/op_iget_quick.S @@ -1,4 +1,4 @@ -%default { "load":"ldr" } +%def op_iget_quick(load="ldr"): /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ /* op vA, vB, offset@CCCC */ mov r2, rINST, lsr #12 @ r2<- B diff --git a/runtime/interpreter/mterp/arm/op_iget_short.S b/runtime/interpreter/mterp/arm/op_iget_short.S index dd6bc9991c..a62c4d998f 100644 --- a/runtime/interpreter/mterp/arm/op_iget_short.S +++ b/runtime/interpreter/mterp/arm/op_iget_short.S @@ -1 +1,2 @@ -%include "arm/op_iget.S" { "helper":"MterpIGetI16" } +%def op_iget_short(): +% op_iget(helper="MterpIGetI16") diff --git a/runtime/interpreter/mterp/arm/op_iget_short_quick.S b/runtime/interpreter/mterp/arm/op_iget_short_quick.S index 1831b99ac3..5dbdc4fa22 100644 --- a/runtime/interpreter/mterp/arm/op_iget_short_quick.S +++ b/runtime/interpreter/mterp/arm/op_iget_short_quick.S @@ -1 +1,2 @@ -%include "arm/op_iget_quick.S" { "load":"ldrsh" } +%def op_iget_short_quick(): +% op_iget_quick(load="ldrsh") diff --git a/runtime/interpreter/mterp/arm/op_iget_wide.S b/runtime/interpreter/mterp/arm/op_iget_wide.S index ede21ebd35..9643cc3403 100644 --- a/runtime/interpreter/mterp/arm/op_iget_wide.S +++ b/runtime/interpreter/mterp/arm/op_iget_wide.S @@ -1 +1,2 @@ -%include "arm/op_iget.S" { "helper":"MterpIGetU64" } +%def op_iget_wide(): +% op_iget(helper="MterpIGetU64") diff --git a/runtime/interpreter/mterp/arm/op_iget_wide_quick.S b/runtime/interpreter/mterp/arm/op_iget_wide_quick.S index 5a7177d8f5..e247fb2640 100644 --- a/runtime/interpreter/mterp/arm/op_iget_wide_quick.S +++ b/runtime/interpreter/mterp/arm/op_iget_wide_quick.S @@ -1,3 +1,4 @@ +%def op_iget_wide_quick(): /* iget-wide-quick vA, vB, offset@CCCC */ mov r2, rINST, lsr #12 @ r2<- B FETCH ip, 1 @ ip<- field byte offset diff --git a/runtime/interpreter/mterp/arm/op_instance_of.S b/runtime/interpreter/mterp/arm/op_instance_of.S index 019929edf9..020b4c5fea 100644 --- a/runtime/interpreter/mterp/arm/op_instance_of.S +++ b/runtime/interpreter/mterp/arm/op_instance_of.S @@ -1,3 +1,4 @@ +%def op_instance_of(): /* * Check to see if an object reference is an instance of a class. * diff --git a/runtime/interpreter/mterp/arm/op_int_to_byte.S b/runtime/interpreter/mterp/arm/op_int_to_byte.S index 059d5c2cf5..3229b5ecf7 100644 --- a/runtime/interpreter/mterp/arm/op_int_to_byte.S +++ b/runtime/interpreter/mterp/arm/op_int_to_byte.S @@ -1 +1,2 @@ -%include "arm/unop.S" {"instr":"sxtb r0, r0"} +%def op_int_to_byte(): +% unop(instr="sxtb r0, r0") diff --git a/runtime/interpreter/mterp/arm/op_int_to_char.S b/runtime/interpreter/mterp/arm/op_int_to_char.S index 83a0c196d6..9ce13b8b6e 100644 --- a/runtime/interpreter/mterp/arm/op_int_to_char.S +++ b/runtime/interpreter/mterp/arm/op_int_to_char.S @@ -1 +1,2 @@ -%include "arm/unop.S" {"instr":"uxth r0, r0"} +%def op_int_to_char(): +% unop(instr="uxth r0, r0") diff --git a/runtime/interpreter/mterp/arm/op_int_to_double.S b/runtime/interpreter/mterp/arm/op_int_to_double.S index 810c2e49bb..cc8065a9bc 100644 --- a/runtime/interpreter/mterp/arm/op_int_to_double.S +++ b/runtime/interpreter/mterp/arm/op_int_to_double.S @@ -1 +1,2 @@ -%include "arm/funopWider.S" {"instr":"fsitod d0, s0"} +%def op_int_to_double(): +% funopWider(instr="fsitod d0, s0") diff --git a/runtime/interpreter/mterp/arm/op_int_to_float.S b/runtime/interpreter/mterp/arm/op_int_to_float.S index f41654c678..b19f3f3164 100644 --- a/runtime/interpreter/mterp/arm/op_int_to_float.S +++ b/runtime/interpreter/mterp/arm/op_int_to_float.S @@ -1 +1,2 @@ -%include "arm/funop.S" {"instr":"fsitos s1, s0"} +%def op_int_to_float(): +% funop(instr="fsitos s1, s0") diff --git a/runtime/interpreter/mterp/arm/op_int_to_long.S b/runtime/interpreter/mterp/arm/op_int_to_long.S index b5aed8e056..8d678991a4 100644 --- a/runtime/interpreter/mterp/arm/op_int_to_long.S +++ b/runtime/interpreter/mterp/arm/op_int_to_long.S @@ -1 +1,2 @@ -%include "arm/unopWider.S" {"instr":"mov r1, r0, asr #31"} +%def op_int_to_long(): +% unopWider(instr="mov r1, r0, asr #31") diff --git a/runtime/interpreter/mterp/arm/op_int_to_short.S b/runtime/interpreter/mterp/arm/op_int_to_short.S index 717bd96bd1..2332460e07 100644 --- a/runtime/interpreter/mterp/arm/op_int_to_short.S +++ b/runtime/interpreter/mterp/arm/op_int_to_short.S @@ -1 +1,2 @@ -%include "arm/unop.S" {"instr":"sxth r0, r0"} +%def op_int_to_short(): +% unop(instr="sxth r0, r0") diff --git a/runtime/interpreter/mterp/arm/op_invoke_custom.S b/runtime/interpreter/mterp/arm/op_invoke_custom.S index 2af875c9df..0bd29b453a 100644 --- a/runtime/interpreter/mterp/arm/op_invoke_custom.S +++ b/runtime/interpreter/mterp/arm/op_invoke_custom.S @@ -1,4 +1,5 @@ -%include "arm/invoke.S" { "helper":"MterpInvokeCustom" } +%def op_invoke_custom(): +% invoke(helper="MterpInvokeCustom") /* * Handle an invoke-custom invocation. * diff --git a/runtime/interpreter/mterp/arm/op_invoke_custom_range.S b/runtime/interpreter/mterp/arm/op_invoke_custom_range.S index 32575c4d45..57e61af1fa 100644 --- a/runtime/interpreter/mterp/arm/op_invoke_custom_range.S +++ b/runtime/interpreter/mterp/arm/op_invoke_custom_range.S @@ -1 +1,2 @@ -%include "arm/invoke.S" { "helper":"MterpInvokeCustomRange" } +%def op_invoke_custom_range(): +% invoke(helper="MterpInvokeCustomRange") diff --git a/runtime/interpreter/mterp/arm/op_invoke_direct.S b/runtime/interpreter/mterp/arm/op_invoke_direct.S index 1edf221914..d3139cf39b 100644 --- a/runtime/interpreter/mterp/arm/op_invoke_direct.S +++ b/runtime/interpreter/mterp/arm/op_invoke_direct.S @@ -1 +1,2 @@ -%include "arm/invoke.S" { "helper":"MterpInvokeDirect" } +%def op_invoke_direct(): +% invoke(helper="MterpInvokeDirect") diff --git a/runtime/interpreter/mterp/arm/op_invoke_direct_range.S b/runtime/interpreter/mterp/arm/op_invoke_direct_range.S index 3097b8e2c7..b4a161f48b 100644 --- a/runtime/interpreter/mterp/arm/op_invoke_direct_range.S +++ b/runtime/interpreter/mterp/arm/op_invoke_direct_range.S @@ -1 +1,2 @@ -%include "arm/invoke.S" { "helper":"MterpInvokeDirectRange" } +%def op_invoke_direct_range(): +% invoke(helper="MterpInvokeDirectRange") diff --git a/runtime/interpreter/mterp/arm/op_invoke_interface.S b/runtime/interpreter/mterp/arm/op_invoke_interface.S index f6d565b168..b064126253 100644 --- a/runtime/interpreter/mterp/arm/op_invoke_interface.S +++ b/runtime/interpreter/mterp/arm/op_invoke_interface.S @@ -1,4 +1,5 @@ -%include "arm/invoke.S" { "helper":"MterpInvokeInterface" } +%def op_invoke_interface(): +% invoke(helper="MterpInvokeInterface") /* * Handle an interface method call. * diff --git a/runtime/interpreter/mterp/arm/op_invoke_interface_range.S b/runtime/interpreter/mterp/arm/op_invoke_interface_range.S index c8443b0cdc..2989115377 100644 --- a/runtime/interpreter/mterp/arm/op_invoke_interface_range.S +++ b/runtime/interpreter/mterp/arm/op_invoke_interface_range.S @@ -1 +1,2 @@ -%include "arm/invoke.S" { "helper":"MterpInvokeInterfaceRange" } +%def op_invoke_interface_range(): +% invoke(helper="MterpInvokeInterfaceRange") diff --git a/runtime/interpreter/mterp/arm/op_invoke_polymorphic.S b/runtime/interpreter/mterp/arm/op_invoke_polymorphic.S index 816a7ae217..ce61f5aa0e 100644 --- a/runtime/interpreter/mterp/arm/op_invoke_polymorphic.S +++ b/runtime/interpreter/mterp/arm/op_invoke_polymorphic.S @@ -1 +1,2 @@ -%include "arm/invoke_polymorphic.S" { "helper":"MterpInvokePolymorphic" } +%def op_invoke_polymorphic(): +% invoke_polymorphic(helper="MterpInvokePolymorphic") diff --git a/runtime/interpreter/mterp/arm/op_invoke_polymorphic_range.S b/runtime/interpreter/mterp/arm/op_invoke_polymorphic_range.S index 2541c270e2..16731bdb40 100644 --- a/runtime/interpreter/mterp/arm/op_invoke_polymorphic_range.S +++ b/runtime/interpreter/mterp/arm/op_invoke_polymorphic_range.S @@ -1 +1,2 @@ -%include "arm/invoke_polymorphic.S" { "helper":"MterpInvokePolymorphicRange" } +%def op_invoke_polymorphic_range(): +% invoke_polymorphic(helper="MterpInvokePolymorphicRange") diff --git a/runtime/interpreter/mterp/arm/op_invoke_static.S b/runtime/interpreter/mterp/arm/op_invoke_static.S index c3cefcff46..3e38d36a27 100644 --- a/runtime/interpreter/mterp/arm/op_invoke_static.S +++ b/runtime/interpreter/mterp/arm/op_invoke_static.S @@ -1,2 +1,3 @@ -%include "arm/invoke.S" { "helper":"MterpInvokeStatic" } +%def op_invoke_static(): +% invoke(helper="MterpInvokeStatic") diff --git a/runtime/interpreter/mterp/arm/op_invoke_static_range.S b/runtime/interpreter/mterp/arm/op_invoke_static_range.S index dd60d7bbfa..e0a546c92b 100644 --- a/runtime/interpreter/mterp/arm/op_invoke_static_range.S +++ b/runtime/interpreter/mterp/arm/op_invoke_static_range.S @@ -1 +1,2 @@ -%include "arm/invoke.S" { "helper":"MterpInvokeStaticRange" } +%def op_invoke_static_range(): +% invoke(helper="MterpInvokeStaticRange") diff --git a/runtime/interpreter/mterp/arm/op_invoke_super.S b/runtime/interpreter/mterp/arm/op_invoke_super.S index 92ef2a4e3e..3c34c9942e 100644 --- a/runtime/interpreter/mterp/arm/op_invoke_super.S +++ b/runtime/interpreter/mterp/arm/op_invoke_super.S @@ -1,4 +1,5 @@ -%include "arm/invoke.S" { "helper":"MterpInvokeSuper" } +%def op_invoke_super(): +% invoke(helper="MterpInvokeSuper") /* * Handle a "super" method call. * diff --git a/runtime/interpreter/mterp/arm/op_invoke_super_range.S b/runtime/interpreter/mterp/arm/op_invoke_super_range.S index 9e4fb1c9a1..caeafaa13c 100644 --- a/runtime/interpreter/mterp/arm/op_invoke_super_range.S +++ b/runtime/interpreter/mterp/arm/op_invoke_super_range.S @@ -1 +1,2 @@ -%include "arm/invoke.S" { "helper":"MterpInvokeSuperRange" } +%def op_invoke_super_range(): +% invoke(helper="MterpInvokeSuperRange") diff --git a/runtime/interpreter/mterp/arm/op_invoke_virtual.S b/runtime/interpreter/mterp/arm/op_invoke_virtual.S index 5b893ff866..249177b813 100644 --- a/runtime/interpreter/mterp/arm/op_invoke_virtual.S +++ b/runtime/interpreter/mterp/arm/op_invoke_virtual.S @@ -1,4 +1,5 @@ -%include "arm/invoke.S" { "helper":"MterpInvokeVirtual" } +%def op_invoke_virtual(): +% invoke(helper="MterpInvokeVirtual") /* * Handle a virtual method call. * diff --git a/runtime/interpreter/mterp/arm/op_invoke_virtual_quick.S b/runtime/interpreter/mterp/arm/op_invoke_virtual_quick.S index 020e8b8135..ea72c171ec 100644 --- a/runtime/interpreter/mterp/arm/op_invoke_virtual_quick.S +++ b/runtime/interpreter/mterp/arm/op_invoke_virtual_quick.S @@ -1 +1,2 @@ -%include "arm/invoke.S" { "helper":"MterpInvokeVirtualQuick" } +%def op_invoke_virtual_quick(): +% invoke(helper="MterpInvokeVirtualQuick") diff --git a/runtime/interpreter/mterp/arm/op_invoke_virtual_range.S b/runtime/interpreter/mterp/arm/op_invoke_virtual_range.S index 2b42a7863a..baa0779593 100644 --- a/runtime/interpreter/mterp/arm/op_invoke_virtual_range.S +++ b/runtime/interpreter/mterp/arm/op_invoke_virtual_range.S @@ -1 +1,2 @@ -%include "arm/invoke.S" { "helper":"MterpInvokeVirtualRange" } +%def op_invoke_virtual_range(): +% invoke(helper="MterpInvokeVirtualRange") diff --git a/runtime/interpreter/mterp/arm/op_invoke_virtual_range_quick.S b/runtime/interpreter/mterp/arm/op_invoke_virtual_range_quick.S index 42f2deda39..1d961a0781 100644 --- a/runtime/interpreter/mterp/arm/op_invoke_virtual_range_quick.S +++ b/runtime/interpreter/mterp/arm/op_invoke_virtual_range_quick.S @@ -1 +1,2 @@ -%include "arm/invoke.S" { "helper":"MterpInvokeVirtualQuickRange" } +%def op_invoke_virtual_range_quick(): +% invoke(helper="MterpInvokeVirtualQuickRange") diff --git a/runtime/interpreter/mterp/arm/op_iput.S b/runtime/interpreter/mterp/arm/op_iput.S index 6201d805f0..e5351baf55 100644 --- a/runtime/interpreter/mterp/arm/op_iput.S +++ b/runtime/interpreter/mterp/arm/op_iput.S @@ -1,2 +1,2 @@ -%default { "is_object":"0", "helper":"MterpIPutU32" } -%include "arm/field.S" { } +%def op_iput(is_object="0", helper="MterpIPutU32"): +% field(helper=helper) diff --git a/runtime/interpreter/mterp/arm/op_iput_boolean.S b/runtime/interpreter/mterp/arm/op_iput_boolean.S index 57edadddd7..9eb849877b 100644 --- a/runtime/interpreter/mterp/arm/op_iput_boolean.S +++ b/runtime/interpreter/mterp/arm/op_iput_boolean.S @@ -1 +1,2 @@ -%include "arm/op_iput.S" { "helper":"MterpIPutU8" } +%def op_iput_boolean(): +% op_iput(helper="MterpIPutU8") diff --git a/runtime/interpreter/mterp/arm/op_iput_boolean_quick.S b/runtime/interpreter/mterp/arm/op_iput_boolean_quick.S index f0a2777821..fd077a7792 100644 --- a/runtime/interpreter/mterp/arm/op_iput_boolean_quick.S +++ b/runtime/interpreter/mterp/arm/op_iput_boolean_quick.S @@ -1 +1,2 @@ -%include "arm/op_iput_quick.S" { "store":"strb" } +%def op_iput_boolean_quick(): +% op_iput_quick(store="strb") diff --git a/runtime/interpreter/mterp/arm/op_iput_byte.S b/runtime/interpreter/mterp/arm/op_iput_byte.S index ab283b90fb..4b74f9fb0e 100644 --- a/runtime/interpreter/mterp/arm/op_iput_byte.S +++ b/runtime/interpreter/mterp/arm/op_iput_byte.S @@ -1 +1,2 @@ -%include "arm/op_iput.S" { "helper":"MterpIPutI8" } +%def op_iput_byte(): +% op_iput(helper="MterpIPutI8") diff --git a/runtime/interpreter/mterp/arm/op_iput_byte_quick.S b/runtime/interpreter/mterp/arm/op_iput_byte_quick.S index f0a2777821..30238cf354 100644 --- a/runtime/interpreter/mterp/arm/op_iput_byte_quick.S +++ b/runtime/interpreter/mterp/arm/op_iput_byte_quick.S @@ -1 +1,2 @@ -%include "arm/op_iput_quick.S" { "store":"strb" } +%def op_iput_byte_quick(): +% op_iput_quick(store="strb") diff --git a/runtime/interpreter/mterp/arm/op_iput_char.S b/runtime/interpreter/mterp/arm/op_iput_char.S index 0fe5d964cc..64a249fc12 100644 --- a/runtime/interpreter/mterp/arm/op_iput_char.S +++ b/runtime/interpreter/mterp/arm/op_iput_char.S @@ -1 +1,2 @@ -%include "arm/op_iput.S" { "helper":"MterpIPutU16" } +%def op_iput_char(): +% op_iput(helper="MterpIPutU16") diff --git a/runtime/interpreter/mterp/arm/op_iput_char_quick.S b/runtime/interpreter/mterp/arm/op_iput_char_quick.S index 5212fc355b..0deff56503 100644 --- a/runtime/interpreter/mterp/arm/op_iput_char_quick.S +++ b/runtime/interpreter/mterp/arm/op_iput_char_quick.S @@ -1 +1,2 @@ -%include "arm/op_iput_quick.S" { "store":"strh" } +%def op_iput_char_quick(): +% op_iput_quick(store="strh") diff --git a/runtime/interpreter/mterp/arm/op_iput_object.S b/runtime/interpreter/mterp/arm/op_iput_object.S index 1003d10d4f..131edd5dbd 100644 --- a/runtime/interpreter/mterp/arm/op_iput_object.S +++ b/runtime/interpreter/mterp/arm/op_iput_object.S @@ -1 +1,2 @@ -%include "arm/op_iput.S" { "is_object":"1", "helper":"MterpIPutObj" } +%def op_iput_object(): +% op_iput(is_object="1", helper="MterpIPutObj") diff --git a/runtime/interpreter/mterp/arm/op_iput_object_quick.S b/runtime/interpreter/mterp/arm/op_iput_object_quick.S index 876b3daad8..be90b840e6 100644 --- a/runtime/interpreter/mterp/arm/op_iput_object_quick.S +++ b/runtime/interpreter/mterp/arm/op_iput_object_quick.S @@ -1,3 +1,4 @@ +%def op_iput_object_quick(): EXPORT_PC add r0, rFP, #OFF_FP_SHADOWFRAME mov r1, rPC diff --git a/runtime/interpreter/mterp/arm/op_iput_quick.S b/runtime/interpreter/mterp/arm/op_iput_quick.S index 98c8150cd6..f84c0982f3 100644 --- a/runtime/interpreter/mterp/arm/op_iput_quick.S +++ b/runtime/interpreter/mterp/arm/op_iput_quick.S @@ -1,4 +1,4 @@ -%default { "store":"str" } +%def op_iput_quick(store="str"): /* For: iput-quick, iput-object-quick */ /* op vA, vB, offset@CCCC */ mov r2, rINST, lsr #12 @ r2<- B diff --git a/runtime/interpreter/mterp/arm/op_iput_short.S b/runtime/interpreter/mterp/arm/op_iput_short.S index cc983630ff..e631a3b259 100644 --- a/runtime/interpreter/mterp/arm/op_iput_short.S +++ b/runtime/interpreter/mterp/arm/op_iput_short.S @@ -1 +1,2 @@ -%include "arm/op_iput.S" { "helper":"MterpIPutI16" } +%def op_iput_short(): +% op_iput(helper="MterpIPutI16") diff --git a/runtime/interpreter/mterp/arm/op_iput_short_quick.S b/runtime/interpreter/mterp/arm/op_iput_short_quick.S index 5212fc355b..6a1b65194e 100644 --- a/runtime/interpreter/mterp/arm/op_iput_short_quick.S +++ b/runtime/interpreter/mterp/arm/op_iput_short_quick.S @@ -1 +1,2 @@ -%include "arm/op_iput_quick.S" { "store":"strh" } +%def op_iput_short_quick(): +% op_iput_quick(store="strh") diff --git a/runtime/interpreter/mterp/arm/op_iput_wide.S b/runtime/interpreter/mterp/arm/op_iput_wide.S index f2845ad29c..2f34fd39f9 100644 --- a/runtime/interpreter/mterp/arm/op_iput_wide.S +++ b/runtime/interpreter/mterp/arm/op_iput_wide.S @@ -1 +1,2 @@ -%include "arm/op_iput.S" { "helper":"MterpIPutU64" } +%def op_iput_wide(): +% op_iput(helper="MterpIPutU64") diff --git a/runtime/interpreter/mterp/arm/op_iput_wide_quick.S b/runtime/interpreter/mterp/arm/op_iput_wide_quick.S index 88e6ea102c..8408f0a924 100644 --- a/runtime/interpreter/mterp/arm/op_iput_wide_quick.S +++ b/runtime/interpreter/mterp/arm/op_iput_wide_quick.S @@ -1,3 +1,4 @@ +%def op_iput_wide_quick(): /* iput-wide-quick vA, vB, offset@CCCC */ mov r2, rINST, lsr #12 @ r2<- B FETCH r3, 1 @ r3<- field byte offset diff --git a/runtime/interpreter/mterp/arm/op_long_to_double.S b/runtime/interpreter/mterp/arm/op_long_to_double.S index cac12d48d4..3228c70929 100644 --- a/runtime/interpreter/mterp/arm/op_long_to_double.S +++ b/runtime/interpreter/mterp/arm/op_long_to_double.S @@ -1,4 +1,4 @@ -%default {} +%def op_long_to_double(): /* * Specialised 64-bit floating point operation. * diff --git a/runtime/interpreter/mterp/arm/op_long_to_float.S b/runtime/interpreter/mterp/arm/op_long_to_float.S index efa5a66913..c021975445 100644 --- a/runtime/interpreter/mterp/arm/op_long_to_float.S +++ b/runtime/interpreter/mterp/arm/op_long_to_float.S @@ -1 +1,2 @@ -%include "arm/unopNarrower.S" {"instr":"bl __aeabi_l2f"} +%def op_long_to_float(): +% unopNarrower(instr="bl __aeabi_l2f") diff --git a/runtime/interpreter/mterp/arm/op_long_to_int.S b/runtime/interpreter/mterp/arm/op_long_to_int.S index 3e91f230b7..eacb8f59ec 100644 --- a/runtime/interpreter/mterp/arm/op_long_to_int.S +++ b/runtime/interpreter/mterp/arm/op_long_to_int.S @@ -1,2 +1,3 @@ +%def op_long_to_int(): /* we ignore the high word, making this equivalent to a 32-bit reg move */ -%include "arm/op_move.S" +% op_move() diff --git a/runtime/interpreter/mterp/arm/op_monitor_enter.S b/runtime/interpreter/mterp/arm/op_monitor_enter.S index 3c34f75d9d..afe293cb1b 100644 --- a/runtime/interpreter/mterp/arm/op_monitor_enter.S +++ b/runtime/interpreter/mterp/arm/op_monitor_enter.S @@ -1,3 +1,4 @@ +%def op_monitor_enter(): /* * Synchronize on an object. */ diff --git a/runtime/interpreter/mterp/arm/op_monitor_exit.S b/runtime/interpreter/mterp/arm/op_monitor_exit.S index fc7cef5395..ddfa7744ef 100644 --- a/runtime/interpreter/mterp/arm/op_monitor_exit.S +++ b/runtime/interpreter/mterp/arm/op_monitor_exit.S @@ -1,3 +1,4 @@ +%def op_monitor_exit(): /* * Unlock an object. * diff --git a/runtime/interpreter/mterp/arm/op_move.S b/runtime/interpreter/mterp/arm/op_move.S index dfecc2432d..7dd893fa66 100644 --- a/runtime/interpreter/mterp/arm/op_move.S +++ b/runtime/interpreter/mterp/arm/op_move.S @@ -1,4 +1,4 @@ -%default { "is_object":"0" } +%def op_move(is_object="0"): /* for move, move-object, long-to-int */ /* op vA, vB */ mov r1, rINST, lsr #12 @ r1<- B from 15:12 diff --git a/runtime/interpreter/mterp/arm/op_move_16.S b/runtime/interpreter/mterp/arm/op_move_16.S index 78138a238c..86601aa28b 100644 --- a/runtime/interpreter/mterp/arm/op_move_16.S +++ b/runtime/interpreter/mterp/arm/op_move_16.S @@ -1,4 +1,4 @@ -%default { "is_object":"0" } +%def op_move_16(is_object="0"): /* for: move/16, move-object/16 */ /* op vAAAA, vBBBB */ FETCH r1, 2 @ r1<- BBBB diff --git a/runtime/interpreter/mterp/arm/op_move_exception.S b/runtime/interpreter/mterp/arm/op_move_exception.S index 0242e26ee5..9136228521 100644 --- a/runtime/interpreter/mterp/arm/op_move_exception.S +++ b/runtime/interpreter/mterp/arm/op_move_exception.S @@ -1,3 +1,4 @@ +%def op_move_exception(): /* move-exception vAA */ mov r2, rINST, lsr #8 @ r2<- AA ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] diff --git a/runtime/interpreter/mterp/arm/op_move_from16.S b/runtime/interpreter/mterp/arm/op_move_from16.S index 3e79417307..113909c9f7 100644 --- a/runtime/interpreter/mterp/arm/op_move_from16.S +++ b/runtime/interpreter/mterp/arm/op_move_from16.S @@ -1,4 +1,4 @@ -%default { "is_object":"0" } +%def op_move_from16(is_object="0"): /* for: move/from16, move-object/from16 */ /* op vAA, vBBBB */ FETCH r1, 1 @ r1<- BBBB diff --git a/runtime/interpreter/mterp/arm/op_move_object.S b/runtime/interpreter/mterp/arm/op_move_object.S index 16de57bac0..dbb4d59710 100644 --- a/runtime/interpreter/mterp/arm/op_move_object.S +++ b/runtime/interpreter/mterp/arm/op_move_object.S @@ -1 +1,2 @@ -%include "arm/op_move.S" {"is_object":"1"} +%def op_move_object(): +% op_move(is_object="1") diff --git a/runtime/interpreter/mterp/arm/op_move_object_16.S b/runtime/interpreter/mterp/arm/op_move_object_16.S index 25343006a3..40120379d5 100644 --- a/runtime/interpreter/mterp/arm/op_move_object_16.S +++ b/runtime/interpreter/mterp/arm/op_move_object_16.S @@ -1 +1,2 @@ -%include "arm/op_move_16.S" {"is_object":"1"} +%def op_move_object_16(): +% op_move_16(is_object="1") diff --git a/runtime/interpreter/mterp/arm/op_move_object_from16.S b/runtime/interpreter/mterp/arm/op_move_object_from16.S index 9e0cf02d17..c82698e81e 100644 --- a/runtime/interpreter/mterp/arm/op_move_object_from16.S +++ b/runtime/interpreter/mterp/arm/op_move_object_from16.S @@ -1 +1,2 @@ -%include "arm/op_move_from16.S" {"is_object":"1"} +%def op_move_object_from16(): +% op_move_from16(is_object="1") diff --git a/runtime/interpreter/mterp/arm/op_move_result.S b/runtime/interpreter/mterp/arm/op_move_result.S index f2586a0769..eee23f6e25 100644 --- a/runtime/interpreter/mterp/arm/op_move_result.S +++ b/runtime/interpreter/mterp/arm/op_move_result.S @@ -1,4 +1,4 @@ -%default { "is_object":"0" } +%def op_move_result(is_object="0"): /* for: move-result, move-result-object */ /* op vAA */ mov r2, rINST, lsr #8 @ r2<- AA diff --git a/runtime/interpreter/mterp/arm/op_move_result_object.S b/runtime/interpreter/mterp/arm/op_move_result_object.S index 643296a5dc..87aea2646a 100644 --- a/runtime/interpreter/mterp/arm/op_move_result_object.S +++ b/runtime/interpreter/mterp/arm/op_move_result_object.S @@ -1 +1,2 @@ -%include "arm/op_move_result.S" {"is_object":"1"} +%def op_move_result_object(): +% op_move_result(is_object="1") diff --git a/runtime/interpreter/mterp/arm/op_move_result_wide.S b/runtime/interpreter/mterp/arm/op_move_result_wide.S index 87929eaeeb..8b4e98034a 100644 --- a/runtime/interpreter/mterp/arm/op_move_result_wide.S +++ b/runtime/interpreter/mterp/arm/op_move_result_wide.S @@ -1,3 +1,4 @@ +%def op_move_result_wide(): /* move-result-wide vAA */ mov rINST, rINST, lsr #8 @ rINST<- AA ldr r3, [rFP, #OFF_FP_RESULT_REGISTER] diff --git a/runtime/interpreter/mterp/arm/op_move_wide.S b/runtime/interpreter/mterp/arm/op_move_wide.S index ff353ea5d9..800f7f6faa 100644 --- a/runtime/interpreter/mterp/arm/op_move_wide.S +++ b/runtime/interpreter/mterp/arm/op_move_wide.S @@ -1,3 +1,4 @@ +%def op_move_wide(): /* move-wide vA, vB */ /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ mov r3, rINST, lsr #12 @ r3<- B diff --git a/runtime/interpreter/mterp/arm/op_move_wide_16.S b/runtime/interpreter/mterp/arm/op_move_wide_16.S index 9812b66e97..ef4f0a8f59 100644 --- a/runtime/interpreter/mterp/arm/op_move_wide_16.S +++ b/runtime/interpreter/mterp/arm/op_move_wide_16.S @@ -1,3 +1,4 @@ +%def op_move_wide_16(): /* move-wide/16 vAAAA, vBBBB */ /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ FETCH r3, 2 @ r3<- BBBB diff --git a/runtime/interpreter/mterp/arm/op_move_wide_from16.S b/runtime/interpreter/mterp/arm/op_move_wide_from16.S index d2cc60ca9d..aae5aa323c 100644 --- a/runtime/interpreter/mterp/arm/op_move_wide_from16.S +++ b/runtime/interpreter/mterp/arm/op_move_wide_from16.S @@ -1,3 +1,4 @@ +%def op_move_wide_from16(): /* move-wide/from16 vAA, vBBBB */ /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ FETCH r3, 1 @ r3<- BBBB diff --git a/runtime/interpreter/mterp/arm/op_mul_double.S b/runtime/interpreter/mterp/arm/op_mul_double.S index 530e85a39e..72948c22b8 100644 --- a/runtime/interpreter/mterp/arm/op_mul_double.S +++ b/runtime/interpreter/mterp/arm/op_mul_double.S @@ -1 +1,2 @@ -%include "arm/fbinopWide.S" {"instr":"fmuld d2, d0, d1"} +%def op_mul_double(): +% fbinopWide(instr="fmuld d2, d0, d1") diff --git a/runtime/interpreter/mterp/arm/op_mul_double_2addr.S b/runtime/interpreter/mterp/arm/op_mul_double_2addr.S index da1abc6e04..afa7fcf6cb 100644 --- a/runtime/interpreter/mterp/arm/op_mul_double_2addr.S +++ b/runtime/interpreter/mterp/arm/op_mul_double_2addr.S @@ -1 +1,2 @@ -%include "arm/fbinopWide2addr.S" {"instr":"fmuld d2, d0, d1"} +%def op_mul_double_2addr(): +% fbinopWide2addr(instr="fmuld d2, d0, d1") diff --git a/runtime/interpreter/mterp/arm/op_mul_float.S b/runtime/interpreter/mterp/arm/op_mul_float.S index 6a72e6f42c..ecb3717b0d 100644 --- a/runtime/interpreter/mterp/arm/op_mul_float.S +++ b/runtime/interpreter/mterp/arm/op_mul_float.S @@ -1 +1,2 @@ -%include "arm/fbinop.S" {"instr":"fmuls s2, s0, s1"} +%def op_mul_float(): +% fbinop(instr="fmuls s2, s0, s1") diff --git a/runtime/interpreter/mterp/arm/op_mul_float_2addr.S b/runtime/interpreter/mterp/arm/op_mul_float_2addr.S index edb5101666..d084b1171b 100644 --- a/runtime/interpreter/mterp/arm/op_mul_float_2addr.S +++ b/runtime/interpreter/mterp/arm/op_mul_float_2addr.S @@ -1 +1,2 @@ -%include "arm/fbinop2addr.S" {"instr":"fmuls s2, s0, s1"} +%def op_mul_float_2addr(): +% fbinop2addr(instr="fmuls s2, s0, s1") diff --git a/runtime/interpreter/mterp/arm/op_mul_int.S b/runtime/interpreter/mterp/arm/op_mul_int.S index d6151d4d45..8a7daf2c35 100644 --- a/runtime/interpreter/mterp/arm/op_mul_int.S +++ b/runtime/interpreter/mterp/arm/op_mul_int.S @@ -1,2 +1,3 @@ +%def op_mul_int(): /* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ -%include "arm/binop.S" {"instr":"mul r0, r1, r0"} +% binop(instr="mul r0, r1, r0") diff --git a/runtime/interpreter/mterp/arm/op_mul_int_2addr.S b/runtime/interpreter/mterp/arm/op_mul_int_2addr.S index 66a797d9fe..98bfb7a9d9 100644 --- a/runtime/interpreter/mterp/arm/op_mul_int_2addr.S +++ b/runtime/interpreter/mterp/arm/op_mul_int_2addr.S @@ -1,2 +1,3 @@ +%def op_mul_int_2addr(): /* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ -%include "arm/binop2addr.S" {"instr":"mul r0, r1, r0"} +% binop2addr(instr="mul r0, r1, r0") diff --git a/runtime/interpreter/mterp/arm/op_mul_int_lit16.S b/runtime/interpreter/mterp/arm/op_mul_int_lit16.S index 4e40c438f7..ab3f36122c 100644 --- a/runtime/interpreter/mterp/arm/op_mul_int_lit16.S +++ b/runtime/interpreter/mterp/arm/op_mul_int_lit16.S @@ -1,2 +1,3 @@ +%def op_mul_int_lit16(): /* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ -%include "arm/binopLit16.S" {"instr":"mul r0, r1, r0"} +% binopLit16(instr="mul r0, r1, r0") diff --git a/runtime/interpreter/mterp/arm/op_mul_int_lit8.S b/runtime/interpreter/mterp/arm/op_mul_int_lit8.S index dbafae9d24..6cc5b89652 100644 --- a/runtime/interpreter/mterp/arm/op_mul_int_lit8.S +++ b/runtime/interpreter/mterp/arm/op_mul_int_lit8.S @@ -1,2 +1,3 @@ +%def op_mul_int_lit8(): /* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ -%include "arm/binopLit8.S" {"instr":"mul r0, r1, r0"} +% binopLit8(instr="mul r0, r1, r0") diff --git a/runtime/interpreter/mterp/arm/op_mul_long.S b/runtime/interpreter/mterp/arm/op_mul_long.S index 4f55280871..c9f2e67323 100644 --- a/runtime/interpreter/mterp/arm/op_mul_long.S +++ b/runtime/interpreter/mterp/arm/op_mul_long.S @@ -1,3 +1,4 @@ +%def op_mul_long(): /* * Signed 64-bit integer multiply. * diff --git a/runtime/interpreter/mterp/arm/op_mul_long_2addr.S b/runtime/interpreter/mterp/arm/op_mul_long_2addr.S index 4c1f058260..2fd9f5c34b 100644 --- a/runtime/interpreter/mterp/arm/op_mul_long_2addr.S +++ b/runtime/interpreter/mterp/arm/op_mul_long_2addr.S @@ -1,3 +1,4 @@ +%def op_mul_long_2addr(): /* * Signed 64-bit integer multiply, "/2addr" version. * diff --git a/runtime/interpreter/mterp/arm/op_neg_double.S b/runtime/interpreter/mterp/arm/op_neg_double.S index 33e609cbfa..df73341b5c 100644 --- a/runtime/interpreter/mterp/arm/op_neg_double.S +++ b/runtime/interpreter/mterp/arm/op_neg_double.S @@ -1 +1,2 @@ -%include "arm/unopWide.S" {"instr":"add r1, r1, #0x80000000"} +%def op_neg_double(): +% unopWide(instr="add r1, r1, #0x80000000") diff --git a/runtime/interpreter/mterp/arm/op_neg_float.S b/runtime/interpreter/mterp/arm/op_neg_float.S index 993583fc86..4ed178fb29 100644 --- a/runtime/interpreter/mterp/arm/op_neg_float.S +++ b/runtime/interpreter/mterp/arm/op_neg_float.S @@ -1 +1,2 @@ -%include "arm/unop.S" {"instr":"add r0, r0, #0x80000000"} +%def op_neg_float(): +% unop(instr="add r0, r0, #0x80000000") diff --git a/runtime/interpreter/mterp/arm/op_neg_int.S b/runtime/interpreter/mterp/arm/op_neg_int.S index ec0b253745..08b72a168c 100644 --- a/runtime/interpreter/mterp/arm/op_neg_int.S +++ b/runtime/interpreter/mterp/arm/op_neg_int.S @@ -1 +1,2 @@ -%include "arm/unop.S" {"instr":"rsb r0, r0, #0"} +%def op_neg_int(): +% unop(instr="rsb r0, r0, #0") diff --git a/runtime/interpreter/mterp/arm/op_neg_long.S b/runtime/interpreter/mterp/arm/op_neg_long.S index dab2eb492e..716c6dc643 100644 --- a/runtime/interpreter/mterp/arm/op_neg_long.S +++ b/runtime/interpreter/mterp/arm/op_neg_long.S @@ -1 +1,2 @@ -%include "arm/unopWide.S" {"preinstr":"rsbs r0, r0, #0", "instr":"rsc r1, r1, #0"} +%def op_neg_long(): +% unopWide(preinstr="rsbs r0, r0, #0", instr="rsc r1, r1, #0") diff --git a/runtime/interpreter/mterp/arm/op_new_array.S b/runtime/interpreter/mterp/arm/op_new_array.S index 8bb792c217..04b5fa4b11 100644 --- a/runtime/interpreter/mterp/arm/op_new_array.S +++ b/runtime/interpreter/mterp/arm/op_new_array.S @@ -1,3 +1,4 @@ +%def op_new_array(): /* * Allocate an array of objects, specified with the array class * and a count. diff --git a/runtime/interpreter/mterp/arm/op_new_instance.S b/runtime/interpreter/mterp/arm/op_new_instance.S index 95d4be8762..447a6cfc0f 100644 --- a/runtime/interpreter/mterp/arm/op_new_instance.S +++ b/runtime/interpreter/mterp/arm/op_new_instance.S @@ -1,3 +1,4 @@ +%def op_new_instance(): /* * Create a new instance of a class. */ diff --git a/runtime/interpreter/mterp/arm/op_nop.S b/runtime/interpreter/mterp/arm/op_nop.S index af0f88f7e3..8bfd1a3557 100644 --- a/runtime/interpreter/mterp/arm/op_nop.S +++ b/runtime/interpreter/mterp/arm/op_nop.S @@ -1,3 +1,4 @@ +%def op_nop(): FETCH_ADVANCE_INST 1 @ advance to next instr, load rINST GET_INST_OPCODE ip @ ip<- opcode from rINST GOTO_OPCODE ip @ execute it diff --git a/runtime/interpreter/mterp/arm/op_not_int.S b/runtime/interpreter/mterp/arm/op_not_int.S index 816485ae6a..90c4eed34b 100644 --- a/runtime/interpreter/mterp/arm/op_not_int.S +++ b/runtime/interpreter/mterp/arm/op_not_int.S @@ -1 +1,2 @@ -%include "arm/unop.S" {"instr":"mvn r0, r0"} +%def op_not_int(): +% unop(instr="mvn r0, r0") diff --git a/runtime/interpreter/mterp/arm/op_not_long.S b/runtime/interpreter/mterp/arm/op_not_long.S index 49a59056d5..29104f2ff7 100644 --- a/runtime/interpreter/mterp/arm/op_not_long.S +++ b/runtime/interpreter/mterp/arm/op_not_long.S @@ -1 +1,2 @@ -%include "arm/unopWide.S" {"preinstr":"mvn r0, r0", "instr":"mvn r1, r1"} +%def op_not_long(): +% unopWide(preinstr="mvn r0, r0", instr="mvn r1, r1") diff --git a/runtime/interpreter/mterp/arm/op_or_int.S b/runtime/interpreter/mterp/arm/op_or_int.S index b046e8d8d8..6992d2ac3d 100644 --- a/runtime/interpreter/mterp/arm/op_or_int.S +++ b/runtime/interpreter/mterp/arm/op_or_int.S @@ -1 +1,2 @@ -%include "arm/binop.S" {"instr":"orr r0, r0, r1"} +%def op_or_int(): +% binop(instr="orr r0, r0, r1") diff --git a/runtime/interpreter/mterp/arm/op_or_int_2addr.S b/runtime/interpreter/mterp/arm/op_or_int_2addr.S index 493c59f285..805ca09169 100644 --- a/runtime/interpreter/mterp/arm/op_or_int_2addr.S +++ b/runtime/interpreter/mterp/arm/op_or_int_2addr.S @@ -1 +1,2 @@ -%include "arm/binop2addr.S" {"instr":"orr r0, r0, r1"} +%def op_or_int_2addr(): +% binop2addr(instr="orr r0, r0, r1") diff --git a/runtime/interpreter/mterp/arm/op_or_int_lit16.S b/runtime/interpreter/mterp/arm/op_or_int_lit16.S index 0a01db8052..03bf4edc54 100644 --- a/runtime/interpreter/mterp/arm/op_or_int_lit16.S +++ b/runtime/interpreter/mterp/arm/op_or_int_lit16.S @@ -1 +1,2 @@ -%include "arm/binopLit16.S" {"instr":"orr r0, r0, r1"} +%def op_or_int_lit16(): +% binopLit16(instr="orr r0, r0, r1") diff --git a/runtime/interpreter/mterp/arm/op_or_int_lit8.S b/runtime/interpreter/mterp/arm/op_or_int_lit8.S index 9882bfcf5e..a29d73f322 100644 --- a/runtime/interpreter/mterp/arm/op_or_int_lit8.S +++ b/runtime/interpreter/mterp/arm/op_or_int_lit8.S @@ -1 +1,2 @@ -%include "arm/binopLit8.S" {"extract":"", "instr":"orr r0, r0, r3, asr #8"} +%def op_or_int_lit8(): +% binopLit8(extract="", instr="orr r0, r0, r3, asr #8") diff --git a/runtime/interpreter/mterp/arm/op_or_long.S b/runtime/interpreter/mterp/arm/op_or_long.S index 048c45ccb5..3278700375 100644 --- a/runtime/interpreter/mterp/arm/op_or_long.S +++ b/runtime/interpreter/mterp/arm/op_or_long.S @@ -1 +1,2 @@ -%include "arm/binopWide.S" {"preinstr":"orr r0, r0, r2", "instr":"orr r1, r1, r3"} +%def op_or_long(): +% binopWide(preinstr="orr r0, r0, r2", instr="orr r1, r1, r3") diff --git a/runtime/interpreter/mterp/arm/op_or_long_2addr.S b/runtime/interpreter/mterp/arm/op_or_long_2addr.S index 93953461ba..56ce5e628e 100644 --- a/runtime/interpreter/mterp/arm/op_or_long_2addr.S +++ b/runtime/interpreter/mterp/arm/op_or_long_2addr.S @@ -1 +1,2 @@ -%include "arm/binopWide2addr.S" {"preinstr":"orr r0, r0, r2", "instr":"orr r1, r1, r3"} +%def op_or_long_2addr(): +% binopWide2addr(preinstr="orr r0, r0, r2", instr="orr r1, r1, r3") diff --git a/runtime/interpreter/mterp/arm/op_packed_switch.S b/runtime/interpreter/mterp/arm/op_packed_switch.S index 412c58f1bc..26af19db22 100644 --- a/runtime/interpreter/mterp/arm/op_packed_switch.S +++ b/runtime/interpreter/mterp/arm/op_packed_switch.S @@ -1,4 +1,4 @@ -%default { "func":"MterpDoPackedSwitch" } +%def op_packed_switch(func="MterpDoPackedSwitch"): /* * Handle a packed-switch or sparse-switch instruction. In both cases * we decode it and hand it off to a helper function. diff --git a/runtime/interpreter/mterp/arm/op_rem_double.S b/runtime/interpreter/mterp/arm/op_rem_double.S index b539221eac..1e1e680d5f 100644 --- a/runtime/interpreter/mterp/arm/op_rem_double.S +++ b/runtime/interpreter/mterp/arm/op_rem_double.S @@ -1,2 +1,3 @@ +%def op_rem_double(): /* EABI doesn't define a double remainder function, but libm does */ -%include "arm/binopWide.S" {"instr":"bl fmod"} +% binopWide(instr="bl fmod") diff --git a/runtime/interpreter/mterp/arm/op_rem_double_2addr.S b/runtime/interpreter/mterp/arm/op_rem_double_2addr.S index 372ef1dfe6..8db1cdecbd 100644 --- a/runtime/interpreter/mterp/arm/op_rem_double_2addr.S +++ b/runtime/interpreter/mterp/arm/op_rem_double_2addr.S @@ -1,2 +1,3 @@ +%def op_rem_double_2addr(): /* EABI doesn't define a double remainder function, but libm does */ -%include "arm/binopWide2addr.S" {"instr":"bl fmod"} +% binopWide2addr(instr="bl fmod") diff --git a/runtime/interpreter/mterp/arm/op_rem_float.S b/runtime/interpreter/mterp/arm/op_rem_float.S index 7bd10deafe..5362e0a5f2 100644 --- a/runtime/interpreter/mterp/arm/op_rem_float.S +++ b/runtime/interpreter/mterp/arm/op_rem_float.S @@ -1,2 +1,3 @@ +%def op_rem_float(): /* EABI doesn't define a float remainder function, but libm does */ -%include "arm/binop.S" {"instr":"bl fmodf"} +% binop(instr="bl fmodf") diff --git a/runtime/interpreter/mterp/arm/op_rem_float_2addr.S b/runtime/interpreter/mterp/arm/op_rem_float_2addr.S index 93c5faef68..90ff391990 100644 --- a/runtime/interpreter/mterp/arm/op_rem_float_2addr.S +++ b/runtime/interpreter/mterp/arm/op_rem_float_2addr.S @@ -1,2 +1,3 @@ +%def op_rem_float_2addr(): /* EABI doesn't define a float remainder function, but libm does */ -%include "arm/binop2addr.S" {"instr":"bl fmodf"} +% binop2addr(instr="bl fmodf") diff --git a/runtime/interpreter/mterp/arm/op_rem_int.S b/runtime/interpreter/mterp/arm/op_rem_int.S index ff6257340f..068870e02c 100644 --- a/runtime/interpreter/mterp/arm/op_rem_int.S +++ b/runtime/interpreter/mterp/arm/op_rem_int.S @@ -1,4 +1,4 @@ -%default {} +%def op_rem_int(): /* * Specialized 32-bit binary operation * diff --git a/runtime/interpreter/mterp/arm/op_rem_int_2addr.S b/runtime/interpreter/mterp/arm/op_rem_int_2addr.S index ba5751a2ae..22ade95135 100644 --- a/runtime/interpreter/mterp/arm/op_rem_int_2addr.S +++ b/runtime/interpreter/mterp/arm/op_rem_int_2addr.S @@ -1,4 +1,4 @@ -%default {} +%def op_rem_int_2addr(): /* * Specialized 32-bit binary operation * diff --git a/runtime/interpreter/mterp/arm/op_rem_int_lit16.S b/runtime/interpreter/mterp/arm/op_rem_int_lit16.S index 4edb187f50..0605663ce2 100644 --- a/runtime/interpreter/mterp/arm/op_rem_int_lit16.S +++ b/runtime/interpreter/mterp/arm/op_rem_int_lit16.S @@ -1,4 +1,4 @@ -%default {} +%def op_rem_int_lit16(): /* * Specialized 32-bit binary operation * diff --git a/runtime/interpreter/mterp/arm/op_rem_int_lit8.S b/runtime/interpreter/mterp/arm/op_rem_int_lit8.S index 3888361bc5..9b6867bac3 100644 --- a/runtime/interpreter/mterp/arm/op_rem_int_lit8.S +++ b/runtime/interpreter/mterp/arm/op_rem_int_lit8.S @@ -1,4 +1,4 @@ -%default {} +%def op_rem_int_lit8(): /* * Specialized 32-bit binary operation * diff --git a/runtime/interpreter/mterp/arm/op_rem_long.S b/runtime/interpreter/mterp/arm/op_rem_long.S index b2b1c24187..a44827f8a1 100644 --- a/runtime/interpreter/mterp/arm/op_rem_long.S +++ b/runtime/interpreter/mterp/arm/op_rem_long.S @@ -1,2 +1,3 @@ +%def op_rem_long(): /* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ -%include "arm/binopWide.S" {"instr":"bl __aeabi_ldivmod", "result0":"r2", "result1":"r3", "chkzero":"1"} +% binopWide(instr="bl __aeabi_ldivmod", result0="r2", result1="r3", chkzero="1") diff --git a/runtime/interpreter/mterp/arm/op_rem_long_2addr.S b/runtime/interpreter/mterp/arm/op_rem_long_2addr.S index f87d493a91..cf34964667 100644 --- a/runtime/interpreter/mterp/arm/op_rem_long_2addr.S +++ b/runtime/interpreter/mterp/arm/op_rem_long_2addr.S @@ -1,2 +1,3 @@ +%def op_rem_long_2addr(): /* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ -%include "arm/binopWide2addr.S" {"instr":"bl __aeabi_ldivmod", "result0":"r2", "result1":"r3", "chkzero":"1"} +% binopWide2addr(instr="bl __aeabi_ldivmod", result0="r2", result1="r3", chkzero="1") diff --git a/runtime/interpreter/mterp/arm/op_return.S b/runtime/interpreter/mterp/arm/op_return.S index f9c0f0fa19..fe35ec9035 100644 --- a/runtime/interpreter/mterp/arm/op_return.S +++ b/runtime/interpreter/mterp/arm/op_return.S @@ -1,3 +1,4 @@ +%def op_return(): /* * Return a 32-bit value. * diff --git a/runtime/interpreter/mterp/arm/op_return_object.S b/runtime/interpreter/mterp/arm/op_return_object.S index c4907302c9..2eeec0b948 100644 --- a/runtime/interpreter/mterp/arm/op_return_object.S +++ b/runtime/interpreter/mterp/arm/op_return_object.S @@ -1 +1,2 @@ -%include "arm/op_return.S" +%def op_return_object(): +% op_return() diff --git a/runtime/interpreter/mterp/arm/op_return_void.S b/runtime/interpreter/mterp/arm/op_return_void.S index a91ccb31f5..2418c6a1f7 100644 --- a/runtime/interpreter/mterp/arm/op_return_void.S +++ b/runtime/interpreter/mterp/arm/op_return_void.S @@ -1,3 +1,4 @@ +%def op_return_void(): .extern MterpThreadFenceForConstructor bl MterpThreadFenceForConstructor ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] diff --git a/runtime/interpreter/mterp/arm/op_return_void_no_barrier.S b/runtime/interpreter/mterp/arm/op_return_void_no_barrier.S index b953f4c7fd..fa4cc0abee 100644 --- a/runtime/interpreter/mterp/arm/op_return_void_no_barrier.S +++ b/runtime/interpreter/mterp/arm/op_return_void_no_barrier.S @@ -1,3 +1,4 @@ +%def op_return_void_no_barrier(): ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] mov r0, rSELF ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST diff --git a/runtime/interpreter/mterp/arm/op_return_wide.S b/runtime/interpreter/mterp/arm/op_return_wide.S index df582c0831..a2a3be41ef 100644 --- a/runtime/interpreter/mterp/arm/op_return_wide.S +++ b/runtime/interpreter/mterp/arm/op_return_wide.S @@ -1,3 +1,4 @@ +%def op_return_wide(): /* * Return a 64-bit value. */ diff --git a/runtime/interpreter/mterp/arm/op_rsub_int.S b/runtime/interpreter/mterp/arm/op_rsub_int.S index 1508dd4373..5d41f6d63b 100644 --- a/runtime/interpreter/mterp/arm/op_rsub_int.S +++ b/runtime/interpreter/mterp/arm/op_rsub_int.S @@ -1,2 +1,3 @@ +%def op_rsub_int(): /* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ -%include "arm/binopLit16.S" {"instr":"rsb r0, r0, r1"} +% binopLit16(instr="rsb r0, r0, r1") diff --git a/runtime/interpreter/mterp/arm/op_rsub_int_lit8.S b/runtime/interpreter/mterp/arm/op_rsub_int_lit8.S index dc953dcc4a..5ce759de4d 100644 --- a/runtime/interpreter/mterp/arm/op_rsub_int_lit8.S +++ b/runtime/interpreter/mterp/arm/op_rsub_int_lit8.S @@ -1 +1,2 @@ -%include "arm/binopLit8.S" {"extract":"", "instr":"rsb r0, r0, r3, asr #8"} +%def op_rsub_int_lit8(): +% binopLit8(extract="", instr="rsb r0, r0, r3, asr #8") diff --git a/runtime/interpreter/mterp/arm/op_sget.S b/runtime/interpreter/mterp/arm/op_sget.S index b382de4c8d..8a6a66ab60 100644 --- a/runtime/interpreter/mterp/arm/op_sget.S +++ b/runtime/interpreter/mterp/arm/op_sget.S @@ -1,2 +1,2 @@ -%default { "is_object":"0", "helper":"MterpSGetU32" } -%include "arm/field.S" { } +%def op_sget(is_object="0", helper="MterpSGetU32"): +% field(helper=helper) diff --git a/runtime/interpreter/mterp/arm/op_sget_boolean.S b/runtime/interpreter/mterp/arm/op_sget_boolean.S index df1a0246b5..d9c12c9b28 100644 --- a/runtime/interpreter/mterp/arm/op_sget_boolean.S +++ b/runtime/interpreter/mterp/arm/op_sget_boolean.S @@ -1 +1,2 @@ -%include "arm/op_sget.S" {"helper":"MterpSGetU8"} +%def op_sget_boolean(): +% op_sget(helper="MterpSGetU8") diff --git a/runtime/interpreter/mterp/arm/op_sget_byte.S b/runtime/interpreter/mterp/arm/op_sget_byte.S index 8ad3ff0e65..37c6879cd4 100644 --- a/runtime/interpreter/mterp/arm/op_sget_byte.S +++ b/runtime/interpreter/mterp/arm/op_sget_byte.S @@ -1 +1,2 @@ -%include "arm/op_sget.S" {"helper":"MterpSGetI8"} +%def op_sget_byte(): +% op_sget(helper="MterpSGetI8") diff --git a/runtime/interpreter/mterp/arm/op_sget_char.S b/runtime/interpreter/mterp/arm/op_sget_char.S index 523951490a..003bcd1683 100644 --- a/runtime/interpreter/mterp/arm/op_sget_char.S +++ b/runtime/interpreter/mterp/arm/op_sget_char.S @@ -1 +1,2 @@ -%include "arm/op_sget.S" {"helper":"MterpSGetU16"} +%def op_sget_char(): +% op_sget(helper="MterpSGetU16") diff --git a/runtime/interpreter/mterp/arm/op_sget_object.S b/runtime/interpreter/mterp/arm/op_sget_object.S index e61a5a7b21..7cf3597f44 100644 --- a/runtime/interpreter/mterp/arm/op_sget_object.S +++ b/runtime/interpreter/mterp/arm/op_sget_object.S @@ -1 +1,2 @@ -%include "arm/op_sget.S" {"is_object":"1", "helper":"MterpSGetObj"} +%def op_sget_object(): +% op_sget(is_object="1", helper="MterpSGetObj") diff --git a/runtime/interpreter/mterp/arm/op_sget_short.S b/runtime/interpreter/mterp/arm/op_sget_short.S index 49493ebc68..afacb578d9 100644 --- a/runtime/interpreter/mterp/arm/op_sget_short.S +++ b/runtime/interpreter/mterp/arm/op_sget_short.S @@ -1 +1,2 @@ -%include "arm/op_sget.S" {"helper":"MterpSGetI16"} +%def op_sget_short(): +% op_sget(helper="MterpSGetI16") diff --git a/runtime/interpreter/mterp/arm/op_sget_wide.S b/runtime/interpreter/mterp/arm/op_sget_wide.S index d6905df7d8..fff2be6945 100644 --- a/runtime/interpreter/mterp/arm/op_sget_wide.S +++ b/runtime/interpreter/mterp/arm/op_sget_wide.S @@ -1 +1,2 @@ -%include "arm/op_sget.S" {"helper":"MterpSGetU64"} +%def op_sget_wide(): +% op_sget(helper="MterpSGetU64") diff --git a/runtime/interpreter/mterp/arm/op_shl_int.S b/runtime/interpreter/mterp/arm/op_shl_int.S index 7e4c768888..948a520e8e 100644 --- a/runtime/interpreter/mterp/arm/op_shl_int.S +++ b/runtime/interpreter/mterp/arm/op_shl_int.S @@ -1 +1,2 @@ -%include "arm/binop.S" {"preinstr":"and r1, r1, #31", "instr":"mov r0, r0, asl r1"} +%def op_shl_int(): +% binop(preinstr="and r1, r1, #31", instr="mov r0, r0, asl r1") diff --git a/runtime/interpreter/mterp/arm/op_shl_int_2addr.S b/runtime/interpreter/mterp/arm/op_shl_int_2addr.S index 4286577e19..89b16da224 100644 --- a/runtime/interpreter/mterp/arm/op_shl_int_2addr.S +++ b/runtime/interpreter/mterp/arm/op_shl_int_2addr.S @@ -1 +1,2 @@ -%include "arm/binop2addr.S" {"preinstr":"and r1, r1, #31", "instr":"mov r0, r0, asl r1"} +%def op_shl_int_2addr(): +% binop2addr(preinstr="and r1, r1, #31", instr="mov r0, r0, asl r1") diff --git a/runtime/interpreter/mterp/arm/op_shl_int_lit8.S b/runtime/interpreter/mterp/arm/op_shl_int_lit8.S index 60a149880f..d6f81e779a 100644 --- a/runtime/interpreter/mterp/arm/op_shl_int_lit8.S +++ b/runtime/interpreter/mterp/arm/op_shl_int_lit8.S @@ -1 +1,2 @@ -%include "arm/binopLit8.S" {"extract":"ubfx r1, r3, #8, #5", "instr":"mov r0, r0, asl r1"} +%def op_shl_int_lit8(): +% binopLit8(extract="ubfx r1, r3, #8, #5", instr="mov r0, r0, asl r1") diff --git a/runtime/interpreter/mterp/arm/op_shl_long.S b/runtime/interpreter/mterp/arm/op_shl_long.S index 82ec6ed09f..d11fee24f4 100644 --- a/runtime/interpreter/mterp/arm/op_shl_long.S +++ b/runtime/interpreter/mterp/arm/op_shl_long.S @@ -1,3 +1,4 @@ +%def op_shl_long(): /* * Long integer shift. This is different from the generic 32/64-bit * binary operations because vAA/vBB are 64-bit but vCC (the shift diff --git a/runtime/interpreter/mterp/arm/op_shl_long_2addr.S b/runtime/interpreter/mterp/arm/op_shl_long_2addr.S index f361a7d29c..e636d2e330 100644 --- a/runtime/interpreter/mterp/arm/op_shl_long_2addr.S +++ b/runtime/interpreter/mterp/arm/op_shl_long_2addr.S @@ -1,3 +1,4 @@ +%def op_shl_long_2addr(): /* * Long integer shift, 2addr version. vA is 64-bit value/result, vB is * 32-bit shift distance. diff --git a/runtime/interpreter/mterp/arm/op_shr_int.S b/runtime/interpreter/mterp/arm/op_shr_int.S index 6317605c6d..4d94d1f550 100644 --- a/runtime/interpreter/mterp/arm/op_shr_int.S +++ b/runtime/interpreter/mterp/arm/op_shr_int.S @@ -1 +1,2 @@ -%include "arm/binop.S" {"preinstr":"and r1, r1, #31", "instr":"mov r0, r0, asr r1"} +%def op_shr_int(): +% binop(preinstr="and r1, r1, #31", instr="mov r0, r0, asr r1") diff --git a/runtime/interpreter/mterp/arm/op_shr_int_2addr.S b/runtime/interpreter/mterp/arm/op_shr_int_2addr.S index cc8632f4bd..786b409921 100644 --- a/runtime/interpreter/mterp/arm/op_shr_int_2addr.S +++ b/runtime/interpreter/mterp/arm/op_shr_int_2addr.S @@ -1 +1,2 @@ -%include "arm/binop2addr.S" {"preinstr":"and r1, r1, #31", "instr":"mov r0, r0, asr r1"} +%def op_shr_int_2addr(): +% binop2addr(preinstr="and r1, r1, #31", instr="mov r0, r0, asr r1") diff --git a/runtime/interpreter/mterp/arm/op_shr_int_lit8.S b/runtime/interpreter/mterp/arm/op_shr_int_lit8.S index c2f6cb0503..f5550b1d4b 100644 --- a/runtime/interpreter/mterp/arm/op_shr_int_lit8.S +++ b/runtime/interpreter/mterp/arm/op_shr_int_lit8.S @@ -1 +1,2 @@ -%include "arm/binopLit8.S" {"extract":"ubfx r1, r3, #8, #5", "instr":"mov r0, r0, asr r1"} +%def op_shr_int_lit8(): +% binopLit8(extract="ubfx r1, r3, #8, #5", instr="mov r0, r0, asr r1") diff --git a/runtime/interpreter/mterp/arm/op_shr_long.S b/runtime/interpreter/mterp/arm/op_shr_long.S index a0afe5b040..eec8d32c8c 100644 --- a/runtime/interpreter/mterp/arm/op_shr_long.S +++ b/runtime/interpreter/mterp/arm/op_shr_long.S @@ -1,3 +1,4 @@ +%def op_shr_long(): /* * Long integer shift. This is different from the generic 32/64-bit * binary operations because vAA/vBB are 64-bit but vCC (the shift diff --git a/runtime/interpreter/mterp/arm/op_shr_long_2addr.S b/runtime/interpreter/mterp/arm/op_shr_long_2addr.S index 976110efd4..ac40d36327 100644 --- a/runtime/interpreter/mterp/arm/op_shr_long_2addr.S +++ b/runtime/interpreter/mterp/arm/op_shr_long_2addr.S @@ -1,3 +1,4 @@ +%def op_shr_long_2addr(): /* * Long integer shift, 2addr version. vA is 64-bit value/result, vB is * 32-bit shift distance. diff --git a/runtime/interpreter/mterp/arm/op_sparse_switch.S b/runtime/interpreter/mterp/arm/op_sparse_switch.S index 9f7a42b96e..b74d7da816 100644 --- a/runtime/interpreter/mterp/arm/op_sparse_switch.S +++ b/runtime/interpreter/mterp/arm/op_sparse_switch.S @@ -1 +1,2 @@ -%include "arm/op_packed_switch.S" { "func":"MterpDoSparseSwitch" } +%def op_sparse_switch(): +% op_packed_switch(func="MterpDoSparseSwitch") diff --git a/runtime/interpreter/mterp/arm/op_sput.S b/runtime/interpreter/mterp/arm/op_sput.S index 171f02444b..cbd6ee96d3 100644 --- a/runtime/interpreter/mterp/arm/op_sput.S +++ b/runtime/interpreter/mterp/arm/op_sput.S @@ -1,2 +1,2 @@ -%default { "is_object":"0", "helper":"MterpSPutU32"} -%include "arm/field.S" { } +%def op_sput(is_object="0", helper="MterpSPutU32"): +% field(helper=helper) diff --git a/runtime/interpreter/mterp/arm/op_sput_boolean.S b/runtime/interpreter/mterp/arm/op_sput_boolean.S index 0c37623fb6..36fba8448b 100644 --- a/runtime/interpreter/mterp/arm/op_sput_boolean.S +++ b/runtime/interpreter/mterp/arm/op_sput_boolean.S @@ -1 +1,2 @@ -%include "arm/op_sput.S" {"helper":"MterpSPutU8"} +%def op_sput_boolean(): +% op_sput(helper="MterpSPutU8") diff --git a/runtime/interpreter/mterp/arm/op_sput_byte.S b/runtime/interpreter/mterp/arm/op_sput_byte.S index 8d4e754229..84ad4a0ff8 100644 --- a/runtime/interpreter/mterp/arm/op_sput_byte.S +++ b/runtime/interpreter/mterp/arm/op_sput_byte.S @@ -1 +1,2 @@ -%include "arm/op_sput.S" {"helper":"MterpSPutI8"} +%def op_sput_byte(): +% op_sput(helper="MterpSPutI8") diff --git a/runtime/interpreter/mterp/arm/op_sput_char.S b/runtime/interpreter/mterp/arm/op_sput_char.S index 442b56f7b1..9b8eeba578 100644 --- a/runtime/interpreter/mterp/arm/op_sput_char.S +++ b/runtime/interpreter/mterp/arm/op_sput_char.S @@ -1 +1,2 @@ -%include "arm/op_sput.S" {"helper":"MterpSPutU16"} +%def op_sput_char(): +% op_sput(helper="MterpSPutU16") diff --git a/runtime/interpreter/mterp/arm/op_sput_object.S b/runtime/interpreter/mterp/arm/op_sput_object.S index 8fcd52e2c4..081360c40f 100644 --- a/runtime/interpreter/mterp/arm/op_sput_object.S +++ b/runtime/interpreter/mterp/arm/op_sput_object.S @@ -1 +1,2 @@ -%include "arm/op_sput.S" {"is_object":"1", "helper":"MterpSPutObj"} +%def op_sput_object(): +% op_sput(is_object="1", helper="MterpSPutObj") diff --git a/runtime/interpreter/mterp/arm/op_sput_short.S b/runtime/interpreter/mterp/arm/op_sput_short.S index 0eb533fe3c..ee16513486 100644 --- a/runtime/interpreter/mterp/arm/op_sput_short.S +++ b/runtime/interpreter/mterp/arm/op_sput_short.S @@ -1 +1,2 @@ -%include "arm/op_sput.S" {"helper":"MterpSPutI16"} +%def op_sput_short(): +% op_sput(helper="MterpSPutI16") diff --git a/runtime/interpreter/mterp/arm/op_sput_wide.S b/runtime/interpreter/mterp/arm/op_sput_wide.S index c254f7834c..44c1a188ed 100644 --- a/runtime/interpreter/mterp/arm/op_sput_wide.S +++ b/runtime/interpreter/mterp/arm/op_sput_wide.S @@ -1 +1,2 @@ -%include "arm/op_sput.S" {"helper":"MterpSPutU64"} +%def op_sput_wide(): +% op_sput(helper="MterpSPutU64") diff --git a/runtime/interpreter/mterp/arm/op_sub_double.S b/runtime/interpreter/mterp/arm/op_sub_double.S index 69bcc6736c..418f93098a 100644 --- a/runtime/interpreter/mterp/arm/op_sub_double.S +++ b/runtime/interpreter/mterp/arm/op_sub_double.S @@ -1 +1,2 @@ -%include "arm/fbinopWide.S" {"instr":"fsubd d2, d0, d1"} +%def op_sub_double(): +% fbinopWide(instr="fsubd d2, d0, d1") diff --git a/runtime/interpreter/mterp/arm/op_sub_double_2addr.S b/runtime/interpreter/mterp/arm/op_sub_double_2addr.S index 2ea59fe854..2bd03703f5 100644 --- a/runtime/interpreter/mterp/arm/op_sub_double_2addr.S +++ b/runtime/interpreter/mterp/arm/op_sub_double_2addr.S @@ -1 +1,2 @@ -%include "arm/fbinopWide2addr.S" {"instr":"fsubd d2, d0, d1"} +%def op_sub_double_2addr(): +% fbinopWide2addr(instr="fsubd d2, d0, d1") diff --git a/runtime/interpreter/mterp/arm/op_sub_float.S b/runtime/interpreter/mterp/arm/op_sub_float.S index 3f17a0dfe3..c0b09ff093 100644 --- a/runtime/interpreter/mterp/arm/op_sub_float.S +++ b/runtime/interpreter/mterp/arm/op_sub_float.S @@ -1 +1,2 @@ -%include "arm/fbinop.S" {"instr":"fsubs s2, s0, s1"} +%def op_sub_float(): +% fbinop(instr="fsubs s2, s0, s1") diff --git a/runtime/interpreter/mterp/arm/op_sub_float_2addr.S b/runtime/interpreter/mterp/arm/op_sub_float_2addr.S index 2f4aac4ad8..c5ffec7be4 100644 --- a/runtime/interpreter/mterp/arm/op_sub_float_2addr.S +++ b/runtime/interpreter/mterp/arm/op_sub_float_2addr.S @@ -1 +1,2 @@ -%include "arm/fbinop2addr.S" {"instr":"fsubs s2, s0, s1"} +%def op_sub_float_2addr(): +% fbinop2addr(instr="fsubs s2, s0, s1") diff --git a/runtime/interpreter/mterp/arm/op_sub_int.S b/runtime/interpreter/mterp/arm/op_sub_int.S index efb9e10035..0932989efc 100644 --- a/runtime/interpreter/mterp/arm/op_sub_int.S +++ b/runtime/interpreter/mterp/arm/op_sub_int.S @@ -1 +1,2 @@ -%include "arm/binop.S" {"instr":"sub r0, r0, r1"} +%def op_sub_int(): +% binop(instr="sub r0, r0, r1") diff --git a/runtime/interpreter/mterp/arm/op_sub_int_2addr.S b/runtime/interpreter/mterp/arm/op_sub_int_2addr.S index 4d3036b82c..c6fa2e46b3 100644 --- a/runtime/interpreter/mterp/arm/op_sub_int_2addr.S +++ b/runtime/interpreter/mterp/arm/op_sub_int_2addr.S @@ -1 +1,2 @@ -%include "arm/binop2addr.S" {"instr":"sub r0, r0, r1"} +%def op_sub_int_2addr(): +% binop2addr(instr="sub r0, r0, r1") diff --git a/runtime/interpreter/mterp/arm/op_sub_long.S b/runtime/interpreter/mterp/arm/op_sub_long.S index 6f1eb6ed77..85d9a9f528 100644 --- a/runtime/interpreter/mterp/arm/op_sub_long.S +++ b/runtime/interpreter/mterp/arm/op_sub_long.S @@ -1 +1,2 @@ -%include "arm/binopWide.S" {"preinstr":"subs r0, r0, r2", "instr":"sbc r1, r1, r3"} +%def op_sub_long(): +% binopWide(preinstr="subs r0, r0, r2", instr="sbc r1, r1, r3") diff --git a/runtime/interpreter/mterp/arm/op_sub_long_2addr.S b/runtime/interpreter/mterp/arm/op_sub_long_2addr.S index 8e9da05525..8a782aa5bf 100644 --- a/runtime/interpreter/mterp/arm/op_sub_long_2addr.S +++ b/runtime/interpreter/mterp/arm/op_sub_long_2addr.S @@ -1 +1,2 @@ -%include "arm/binopWide2addr.S" {"preinstr":"subs r0, r0, r2", "instr":"sbc r1, r1, r3"} +%def op_sub_long_2addr(): +% binopWide2addr(preinstr="subs r0, r0, r2", instr="sbc r1, r1, r3") diff --git a/runtime/interpreter/mterp/arm/op_throw.S b/runtime/interpreter/mterp/arm/op_throw.S index be49ada424..0d3fe37934 100644 --- a/runtime/interpreter/mterp/arm/op_throw.S +++ b/runtime/interpreter/mterp/arm/op_throw.S @@ -1,3 +1,4 @@ +%def op_throw(): /* * Throw an exception object in the current thread. */ diff --git a/runtime/interpreter/mterp/arm/op_unused_3e.S b/runtime/interpreter/mterp/arm/op_unused_3e.S index 10948dc06c..d889f1a5fb 100644 --- a/runtime/interpreter/mterp/arm/op_unused_3e.S +++ b/runtime/interpreter/mterp/arm/op_unused_3e.S @@ -1 +1,2 @@ -%include "arm/unused.S" +%def op_unused_3e(): +% unused() diff --git a/runtime/interpreter/mterp/arm/op_unused_3f.S b/runtime/interpreter/mterp/arm/op_unused_3f.S index 10948dc06c..b3ebcfaeaa 100644 --- a/runtime/interpreter/mterp/arm/op_unused_3f.S +++ b/runtime/interpreter/mterp/arm/op_unused_3f.S @@ -1 +1,2 @@ -%include "arm/unused.S" +%def op_unused_3f(): +% unused() diff --git a/runtime/interpreter/mterp/arm/op_unused_40.S b/runtime/interpreter/mterp/arm/op_unused_40.S index 10948dc06c..7920fb350f 100644 --- a/runtime/interpreter/mterp/arm/op_unused_40.S +++ b/runtime/interpreter/mterp/arm/op_unused_40.S @@ -1 +1,2 @@ -%include "arm/unused.S" +%def op_unused_40(): +% unused() diff --git a/runtime/interpreter/mterp/arm/op_unused_41.S b/runtime/interpreter/mterp/arm/op_unused_41.S index 10948dc06c..5ed03b8506 100644 --- a/runtime/interpreter/mterp/arm/op_unused_41.S +++ b/runtime/interpreter/mterp/arm/op_unused_41.S @@ -1 +1,2 @@ -%include "arm/unused.S" +%def op_unused_41(): +% unused() diff --git a/runtime/interpreter/mterp/arm/op_unused_42.S b/runtime/interpreter/mterp/arm/op_unused_42.S index 10948dc06c..ac32521add 100644 --- a/runtime/interpreter/mterp/arm/op_unused_42.S +++ b/runtime/interpreter/mterp/arm/op_unused_42.S @@ -1 +1,2 @@ -%include "arm/unused.S" +%def op_unused_42(): +% unused() diff --git a/runtime/interpreter/mterp/arm/op_unused_43.S b/runtime/interpreter/mterp/arm/op_unused_43.S index 10948dc06c..33e2aa10f8 100644 --- a/runtime/interpreter/mterp/arm/op_unused_43.S +++ b/runtime/interpreter/mterp/arm/op_unused_43.S @@ -1 +1,2 @@ -%include "arm/unused.S" +%def op_unused_43(): +% unused() diff --git a/runtime/interpreter/mterp/arm/op_unused_73.S b/runtime/interpreter/mterp/arm/op_unused_73.S index 10948dc06c..e3267a30a1 100644 --- a/runtime/interpreter/mterp/arm/op_unused_73.S +++ b/runtime/interpreter/mterp/arm/op_unused_73.S @@ -1 +1,2 @@ -%include "arm/unused.S" +%def op_unused_73(): +% unused() diff --git a/runtime/interpreter/mterp/arm/op_unused_79.S b/runtime/interpreter/mterp/arm/op_unused_79.S index 10948dc06c..3c6dafc789 100644 --- a/runtime/interpreter/mterp/arm/op_unused_79.S +++ b/runtime/interpreter/mterp/arm/op_unused_79.S @@ -1 +1,2 @@ -%include "arm/unused.S" +%def op_unused_79(): +% unused() diff --git a/runtime/interpreter/mterp/arm/op_unused_7a.S b/runtime/interpreter/mterp/arm/op_unused_7a.S index 10948dc06c..9c03cd5535 100644 --- a/runtime/interpreter/mterp/arm/op_unused_7a.S +++ b/runtime/interpreter/mterp/arm/op_unused_7a.S @@ -1 +1,2 @@ -%include "arm/unused.S" +%def op_unused_7a(): +% unused() diff --git a/runtime/interpreter/mterp/arm/op_unused_f3.S b/runtime/interpreter/mterp/arm/op_unused_f3.S index 10948dc06c..ab10b78be2 100644 --- a/runtime/interpreter/mterp/arm/op_unused_f3.S +++ b/runtime/interpreter/mterp/arm/op_unused_f3.S @@ -1 +1,2 @@ -%include "arm/unused.S" +%def op_unused_f3(): +% unused() diff --git a/runtime/interpreter/mterp/arm/op_unused_f4.S b/runtime/interpreter/mterp/arm/op_unused_f4.S index 10948dc06c..09229d6d99 100644 --- a/runtime/interpreter/mterp/arm/op_unused_f4.S +++ b/runtime/interpreter/mterp/arm/op_unused_f4.S @@ -1 +1,2 @@ -%include "arm/unused.S" +%def op_unused_f4(): +% unused() diff --git a/runtime/interpreter/mterp/arm/op_unused_f5.S b/runtime/interpreter/mterp/arm/op_unused_f5.S index 10948dc06c..0d6149b5fd 100644 --- a/runtime/interpreter/mterp/arm/op_unused_f5.S +++ b/runtime/interpreter/mterp/arm/op_unused_f5.S @@ -1 +1,2 @@ -%include "arm/unused.S" +%def op_unused_f5(): +% unused() diff --git a/runtime/interpreter/mterp/arm/op_unused_f6.S b/runtime/interpreter/mterp/arm/op_unused_f6.S index 10948dc06c..117b03de6d 100644 --- a/runtime/interpreter/mterp/arm/op_unused_f6.S +++ b/runtime/interpreter/mterp/arm/op_unused_f6.S @@ -1 +1,2 @@ -%include "arm/unused.S" +%def op_unused_f6(): +% unused() diff --git a/runtime/interpreter/mterp/arm/op_unused_f7.S b/runtime/interpreter/mterp/arm/op_unused_f7.S index 10948dc06c..4e3a0f3c9a 100644 --- a/runtime/interpreter/mterp/arm/op_unused_f7.S +++ b/runtime/interpreter/mterp/arm/op_unused_f7.S @@ -1 +1,2 @@ -%include "arm/unused.S" +%def op_unused_f7(): +% unused() diff --git a/runtime/interpreter/mterp/arm/op_unused_f8.S b/runtime/interpreter/mterp/arm/op_unused_f8.S index 10948dc06c..d1220752d7 100644 --- a/runtime/interpreter/mterp/arm/op_unused_f8.S +++ b/runtime/interpreter/mterp/arm/op_unused_f8.S @@ -1 +1,2 @@ -%include "arm/unused.S" +%def op_unused_f8(): +% unused() diff --git a/runtime/interpreter/mterp/arm/op_unused_f9.S b/runtime/interpreter/mterp/arm/op_unused_f9.S index 10948dc06c..7d09a0ebcf 100644 --- a/runtime/interpreter/mterp/arm/op_unused_f9.S +++ b/runtime/interpreter/mterp/arm/op_unused_f9.S @@ -1 +1,2 @@ -%include "arm/unused.S" +%def op_unused_f9(): +% unused() diff --git a/runtime/interpreter/mterp/arm/op_unused_fc.S b/runtime/interpreter/mterp/arm/op_unused_fc.S index 10948dc06c..06978191eb 100644 --- a/runtime/interpreter/mterp/arm/op_unused_fc.S +++ b/runtime/interpreter/mterp/arm/op_unused_fc.S @@ -1 +1,2 @@ -%include "arm/unused.S" +%def op_unused_fc(): +% unused() diff --git a/runtime/interpreter/mterp/arm/op_unused_fd.S b/runtime/interpreter/mterp/arm/op_unused_fd.S index 10948dc06c..4bc2b4bdb6 100644 --- a/runtime/interpreter/mterp/arm/op_unused_fd.S +++ b/runtime/interpreter/mterp/arm/op_unused_fd.S @@ -1 +1,2 @@ -%include "arm/unused.S" +%def op_unused_fd(): +% unused() diff --git a/runtime/interpreter/mterp/arm/op_ushr_int.S b/runtime/interpreter/mterp/arm/op_ushr_int.S index a74361b64c..7716bebcbb 100644 --- a/runtime/interpreter/mterp/arm/op_ushr_int.S +++ b/runtime/interpreter/mterp/arm/op_ushr_int.S @@ -1 +1,2 @@ -%include "arm/binop.S" {"preinstr":"and r1, r1, #31", "instr":"mov r0, r0, lsr r1"} +%def op_ushr_int(): +% binop(preinstr="and r1, r1, #31", instr="mov r0, r0, lsr r1") diff --git a/runtime/interpreter/mterp/arm/op_ushr_int_2addr.S b/runtime/interpreter/mterp/arm/op_ushr_int_2addr.S index f2d1d13881..8e435a738c 100644 --- a/runtime/interpreter/mterp/arm/op_ushr_int_2addr.S +++ b/runtime/interpreter/mterp/arm/op_ushr_int_2addr.S @@ -1 +1,2 @@ -%include "arm/binop2addr.S" {"preinstr":"and r1, r1, #31", "instr":"mov r0, r0, lsr r1"} +%def op_ushr_int_2addr(): +% binop2addr(preinstr="and r1, r1, #31", instr="mov r0, r0, lsr r1") diff --git a/runtime/interpreter/mterp/arm/op_ushr_int_lit8.S b/runtime/interpreter/mterp/arm/op_ushr_int_lit8.S index 5554eb06f7..40783de326 100644 --- a/runtime/interpreter/mterp/arm/op_ushr_int_lit8.S +++ b/runtime/interpreter/mterp/arm/op_ushr_int_lit8.S @@ -1 +1,2 @@ -%include "arm/binopLit8.S" {"extract":"ubfx r1, r3, #8, #5", "instr":"mov r0, r0, lsr r1"} +%def op_ushr_int_lit8(): +% binopLit8(extract="ubfx r1, r3, #8, #5", instr="mov r0, r0, lsr r1") diff --git a/runtime/interpreter/mterp/arm/op_ushr_long.S b/runtime/interpreter/mterp/arm/op_ushr_long.S index c817bc9fb9..2ab31ff216 100644 --- a/runtime/interpreter/mterp/arm/op_ushr_long.S +++ b/runtime/interpreter/mterp/arm/op_ushr_long.S @@ -1,3 +1,4 @@ +%def op_ushr_long(): /* * Long integer shift. This is different from the generic 32/64-bit * binary operations because vAA/vBB are 64-bit but vCC (the shift diff --git a/runtime/interpreter/mterp/arm/op_ushr_long_2addr.S b/runtime/interpreter/mterp/arm/op_ushr_long_2addr.S index 2735f8733a..e86161b0f5 100644 --- a/runtime/interpreter/mterp/arm/op_ushr_long_2addr.S +++ b/runtime/interpreter/mterp/arm/op_ushr_long_2addr.S @@ -1,3 +1,4 @@ +%def op_ushr_long_2addr(): /* * Long integer shift, 2addr version. vA is 64-bit value/result, vB is * 32-bit shift distance. diff --git a/runtime/interpreter/mterp/arm/op_xor_int.S b/runtime/interpreter/mterp/arm/op_xor_int.S index fd7a4b7a02..89a6450b01 100644 --- a/runtime/interpreter/mterp/arm/op_xor_int.S +++ b/runtime/interpreter/mterp/arm/op_xor_int.S @@ -1 +1,2 @@ -%include "arm/binop.S" {"instr":"eor r0, r0, r1"} +%def op_xor_int(): +% binop(instr="eor r0, r0, r1") diff --git a/runtime/interpreter/mterp/arm/op_xor_int_2addr.S b/runtime/interpreter/mterp/arm/op_xor_int_2addr.S index 196a665724..af7e85ede6 100644 --- a/runtime/interpreter/mterp/arm/op_xor_int_2addr.S +++ b/runtime/interpreter/mterp/arm/op_xor_int_2addr.S @@ -1 +1,2 @@ -%include "arm/binop2addr.S" {"instr":"eor r0, r0, r1"} +%def op_xor_int_2addr(): +% binop2addr(instr="eor r0, r0, r1") diff --git a/runtime/interpreter/mterp/arm/op_xor_int_lit16.S b/runtime/interpreter/mterp/arm/op_xor_int_lit16.S index 39f2a47bfa..a970e01357 100644 --- a/runtime/interpreter/mterp/arm/op_xor_int_lit16.S +++ b/runtime/interpreter/mterp/arm/op_xor_int_lit16.S @@ -1 +1,2 @@ -%include "arm/binopLit16.S" {"instr":"eor r0, r0, r1"} +%def op_xor_int_lit16(): +% binopLit16(instr="eor r0, r0, r1") diff --git a/runtime/interpreter/mterp/arm/op_xor_int_lit8.S b/runtime/interpreter/mterp/arm/op_xor_int_lit8.S index 97d0b9ee14..2241f3176b 100644 --- a/runtime/interpreter/mterp/arm/op_xor_int_lit8.S +++ b/runtime/interpreter/mterp/arm/op_xor_int_lit8.S @@ -1 +1,2 @@ -%include "arm/binopLit8.S" {"extract":"", "instr":"eor r0, r0, r3, asr #8"} +%def op_xor_int_lit8(): +% binopLit8(extract="", instr="eor r0, r0, r3, asr #8") diff --git a/runtime/interpreter/mterp/arm/op_xor_long.S b/runtime/interpreter/mterp/arm/op_xor_long.S index 4f830d01be..3700a4a308 100644 --- a/runtime/interpreter/mterp/arm/op_xor_long.S +++ b/runtime/interpreter/mterp/arm/op_xor_long.S @@ -1 +1,2 @@ -%include "arm/binopWide.S" {"preinstr":"eor r0, r0, r2", "instr":"eor r1, r1, r3"} +%def op_xor_long(): +% binopWide(preinstr="eor r0, r0, r2", instr="eor r1, r1, r3") diff --git a/runtime/interpreter/mterp/arm/op_xor_long_2addr.S b/runtime/interpreter/mterp/arm/op_xor_long_2addr.S index 5b5ed88059..6558a4eb39 100644 --- a/runtime/interpreter/mterp/arm/op_xor_long_2addr.S +++ b/runtime/interpreter/mterp/arm/op_xor_long_2addr.S @@ -1 +1,2 @@ -%include "arm/binopWide2addr.S" {"preinstr":"eor r0, r0, r2", "instr":"eor r1, r1, r3"} +%def op_xor_long_2addr(): +% binopWide2addr(preinstr="eor r0, r0, r2", instr="eor r1, r1, r3") diff --git a/runtime/interpreter/mterp/arm/unop.S b/runtime/interpreter/mterp/arm/unop.S index 56518b5b2b..a0b095411e 100644 --- a/runtime/interpreter/mterp/arm/unop.S +++ b/runtime/interpreter/mterp/arm/unop.S @@ -1,4 +1,4 @@ -%default {"preinstr":""} +%def unop(preinstr="", instr=""): /* * Generic 32-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result = op r0". diff --git a/runtime/interpreter/mterp/arm/unopNarrower.S b/runtime/interpreter/mterp/arm/unopNarrower.S index 2d0453aeb1..4d1bdb90a6 100644 --- a/runtime/interpreter/mterp/arm/unopNarrower.S +++ b/runtime/interpreter/mterp/arm/unopNarrower.S @@ -1,4 +1,4 @@ -%default {"preinstr":""} +%def unopNarrower(preinstr="", instr=""): /* * Generic 64bit-to-32bit unary operation. Provide an "instr" line * that specifies an instruction that performs "result = op r0/r1", where diff --git a/runtime/interpreter/mterp/arm/unopWide.S b/runtime/interpreter/mterp/arm/unopWide.S index cd5defd616..658c2073d9 100644 --- a/runtime/interpreter/mterp/arm/unopWide.S +++ b/runtime/interpreter/mterp/arm/unopWide.S @@ -1,4 +1,4 @@ -%default {"preinstr":""} +%def unopWide(preinstr="", instr=""): /* * Generic 64-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result = op r0/r1". diff --git a/runtime/interpreter/mterp/arm/unopWider.S b/runtime/interpreter/mterp/arm/unopWider.S index 9d504899b8..8b3292719d 100644 --- a/runtime/interpreter/mterp/arm/unopWider.S +++ b/runtime/interpreter/mterp/arm/unopWider.S @@ -1,4 +1,4 @@ -%default {"preinstr":""} +%def unopWider(preinstr="", instr=""): /* * Generic 32bit-to-64bit unary operation. Provide an "instr" line * that specifies an instruction that performs "result = op r0", where diff --git a/runtime/interpreter/mterp/arm/unused.S b/runtime/interpreter/mterp/arm/unused.S index ffa00becfd..3f37e74bb4 100644 --- a/runtime/interpreter/mterp/arm/unused.S +++ b/runtime/interpreter/mterp/arm/unused.S @@ -1,3 +1,4 @@ +%def unused(): /* * Bail to reference interpreter to throw. */ diff --git a/runtime/interpreter/mterp/arm/zcmp.S b/runtime/interpreter/mterp/arm/zcmp.S index 5db8b6cdd7..6905a32499 100644 --- a/runtime/interpreter/mterp/arm/zcmp.S +++ b/runtime/interpreter/mterp/arm/zcmp.S @@ -1,3 +1,4 @@ +%def zcmp(condition=""): /* * Generic one-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform. diff --git a/runtime/interpreter/mterp/arm64/alt_stub.S b/runtime/interpreter/mterp/arm64/alt_stub.S index 3a463feb41..33434633cf 100644 --- a/runtime/interpreter/mterp/arm64/alt_stub.S +++ b/runtime/interpreter/mterp/arm64/alt_stub.S @@ -1,3 +1,4 @@ +%def alt_stub(): /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction diff --git a/runtime/interpreter/mterp/arm64/bincmp.S b/runtime/interpreter/mterp/arm64/bincmp.S index 8dd4fed7ca..80ffbc5f3b 100644 --- a/runtime/interpreter/mterp/arm64/bincmp.S +++ b/runtime/interpreter/mterp/arm64/bincmp.S @@ -1,3 +1,4 @@ +%def bincmp(condition=""): /* * Generic two-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform. diff --git a/runtime/interpreter/mterp/arm64/binop.S b/runtime/interpreter/mterp/arm64/binop.S index b629b0b37e..be4db17515 100644 --- a/runtime/interpreter/mterp/arm64/binop.S +++ b/runtime/interpreter/mterp/arm64/binop.S @@ -1,4 +1,4 @@ -%default {"preinstr":"", "result":"w0", "chkzero":"0"} +%def binop(preinstr="", result="w0", chkzero="0", instr=""): /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = w0 op w1". diff --git a/runtime/interpreter/mterp/arm64/binop2addr.S b/runtime/interpreter/mterp/arm64/binop2addr.S index a480a7d551..5b46b12157 100644 --- a/runtime/interpreter/mterp/arm64/binop2addr.S +++ b/runtime/interpreter/mterp/arm64/binop2addr.S @@ -1,4 +1,4 @@ -%default {"preinstr":"", "result":"w0", "chkzero":"0"} +%def binop2addr(preinstr="", result="w0", chkzero="0", instr=""): /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = w0 op w1". diff --git a/runtime/interpreter/mterp/arm64/binopLit16.S b/runtime/interpreter/mterp/arm64/binopLit16.S index 4f9d205b38..b8af7d18fc 100644 --- a/runtime/interpreter/mterp/arm64/binopLit16.S +++ b/runtime/interpreter/mterp/arm64/binopLit16.S @@ -1,4 +1,4 @@ -%default {"preinstr":"", "result":"w0", "chkzero":"0"} +%def binopLit16(preinstr="", result="w0", chkzero="0", instr=""): /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = w0 op w1". diff --git a/runtime/interpreter/mterp/arm64/binopLit8.S b/runtime/interpreter/mterp/arm64/binopLit8.S index dfa3169905..e7161a7d4b 100644 --- a/runtime/interpreter/mterp/arm64/binopLit8.S +++ b/runtime/interpreter/mterp/arm64/binopLit8.S @@ -1,4 +1,4 @@ -%default {"extract": "asr w1, w3, #8", "preinstr":"", "result":"w0", "chkzero":"0"} +%def binopLit8(extract="asr w1, w3, #8", preinstr="", result="w0", chkzero="0", instr=""): /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = w0 op w1". diff --git a/runtime/interpreter/mterp/arm64/binopWide.S b/runtime/interpreter/mterp/arm64/binopWide.S index 9de24f1c22..829b53067f 100644 --- a/runtime/interpreter/mterp/arm64/binopWide.S +++ b/runtime/interpreter/mterp/arm64/binopWide.S @@ -1,4 +1,4 @@ -%default {"preinstr":"", "instr":"add x0, x1, x2", "result":"x0", "r1":"x1", "r2":"x2", "chkzero":"0"} +%def binopWide(preinstr="", instr="add x0, x1, x2", result="x0", r1="x1", r2="x2", chkzero="0"): /* * Generic 64-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = x1 op x2". diff --git a/runtime/interpreter/mterp/arm64/binopWide2addr.S b/runtime/interpreter/mterp/arm64/binopWide2addr.S index d9927a2ca8..dbd6b3b853 100644 --- a/runtime/interpreter/mterp/arm64/binopWide2addr.S +++ b/runtime/interpreter/mterp/arm64/binopWide2addr.S @@ -1,4 +1,4 @@ -%default {"preinstr":"", "instr":"add x0, x0, x1", "r0":"x0", "r1":"x1", "chkzero":"0"} +%def binopWide2addr(preinstr="", instr="add x0, x0, x1", r0="x0", r1="x1", chkzero="0"): /* * Generic 64-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "x0 = x0 op x1". diff --git a/runtime/interpreter/mterp/arm64/close_cfi.S b/runtime/interpreter/mterp/arm64/close_cfi.S index 7ba0486079..8f651b18f0 100644 --- a/runtime/interpreter/mterp/arm64/close_cfi.S +++ b/runtime/interpreter/mterp/arm64/close_cfi.S @@ -1,3 +1,4 @@ +%def close_cfi(): // Close out the cfi info. We're treating mterp as a single function. END ExecuteMterpImpl diff --git a/runtime/interpreter/mterp/arm64/const.S b/runtime/interpreter/mterp/arm64/const.S index 6f82bbf0ba..f8477a8b12 100644 --- a/runtime/interpreter/mterp/arm64/const.S +++ b/runtime/interpreter/mterp/arm64/const.S @@ -1,4 +1,4 @@ -%default { "helper":"UndefinedConstHandler" } +%def const(helper="UndefinedConstHandler"): /* const/class vAA, type@BBBB */ /* const/method-handle vAA, method_handle@BBBB */ /* const/method-type vAA, proto@BBBB */ diff --git a/runtime/interpreter/mterp/arm64/entry.S b/runtime/interpreter/mterp/arm64/entry.S index cf38a2992d..baf8afce6e 100644 --- a/runtime/interpreter/mterp/arm64/entry.S +++ b/runtime/interpreter/mterp/arm64/entry.S @@ -1,3 +1,4 @@ +%def entry(): /* * Copyright (C) 2016 The Android Open Source Project * diff --git a/runtime/interpreter/mterp/arm64/fallback.S b/runtime/interpreter/mterp/arm64/fallback.S index 44e7e1220d..3685700dec 100644 --- a/runtime/interpreter/mterp/arm64/fallback.S +++ b/runtime/interpreter/mterp/arm64/fallback.S @@ -1,3 +1,4 @@ +%def fallback(): /* Transfer stub to alternate interpreter */ b MterpFallback diff --git a/runtime/interpreter/mterp/arm64/fbinop.S b/runtime/interpreter/mterp/arm64/fbinop.S index 926d0783da..e3fb25a8da 100644 --- a/runtime/interpreter/mterp/arm64/fbinop.S +++ b/runtime/interpreter/mterp/arm64/fbinop.S @@ -1,4 +1,4 @@ -%default {} +%def fbinop(instr=""): /*: * Generic 32-bit floating-point operation. * diff --git a/runtime/interpreter/mterp/arm64/fbinop2addr.S b/runtime/interpreter/mterp/arm64/fbinop2addr.S index 04236adb81..9f235d94b6 100644 --- a/runtime/interpreter/mterp/arm64/fbinop2addr.S +++ b/runtime/interpreter/mterp/arm64/fbinop2addr.S @@ -1,3 +1,4 @@ +%def fbinop2addr(instr=""): /* * Generic 32-bit floating point "/2addr" binary operation. Provide * an "instr" line that specifies an instruction that performs diff --git a/runtime/interpreter/mterp/arm64/fcmp.S b/runtime/interpreter/mterp/arm64/fcmp.S index cad63189af..c0cc33afcd 100644 --- a/runtime/interpreter/mterp/arm64/fcmp.S +++ b/runtime/interpreter/mterp/arm64/fcmp.S @@ -1,4 +1,4 @@ -%default {"wide":"", "r1":"s1", "r2":"s2", "cond":"lt"} +%def fcmp(wide="", r1="s1", r2="s2", cond="lt"): /* * Compare two floating-point values. Puts 0, 1, or -1 into the * destination register based on the results of the comparison. diff --git a/runtime/interpreter/mterp/arm64/field.S b/runtime/interpreter/mterp/arm64/field.S index 631c8d191b..8a66992724 100644 --- a/runtime/interpreter/mterp/arm64/field.S +++ b/runtime/interpreter/mterp/arm64/field.S @@ -1,4 +1,4 @@ -%default { } +%def field(helper=""): /* * General field read / write (iget-* iput-* sget-* sput-*). */ diff --git a/runtime/interpreter/mterp/arm64/footer.S b/runtime/interpreter/mterp/arm64/footer.S index 0ce3543911..ba17f5e897 100644 --- a/runtime/interpreter/mterp/arm64/footer.S +++ b/runtime/interpreter/mterp/arm64/footer.S @@ -1,10 +1,10 @@ +%def footer(): /* * =========================================================================== * Common subroutines and data * =========================================================================== */ - /* * We've detected a condition that will result in an exception, but the exception * has not yet been thrown. Just bail out to the reference interpreter to deal with it. @@ -207,7 +207,6 @@ MterpCommonTakenBranchNoFlags: GET_INST_OPCODE ip // extract opcode from wINST GOTO_OPCODE ip // jump to next instruction - /* * Check for suspend check request. Assumes wINST already loaded, xPC advanced and * still needs to get the opcode and branch to it, and flags are in lr. diff --git a/runtime/interpreter/mterp/arm64/funopNarrow.S b/runtime/interpreter/mterp/arm64/funopNarrow.S index aed830bc23..f08e87fb3c 100644 --- a/runtime/interpreter/mterp/arm64/funopNarrow.S +++ b/runtime/interpreter/mterp/arm64/funopNarrow.S @@ -1,4 +1,4 @@ -%default {"srcreg":"s0", "tgtreg":"d0"} +%def funopNarrow(srcreg="s0", tgtreg="d0", instr=""): /* * Generic 32bit-to-32bit floating point unary operation. Provide an * "instr" line that specifies an instruction that performs "$tgtreg = op $srcreg". diff --git a/runtime/interpreter/mterp/arm64/funopNarrower.S b/runtime/interpreter/mterp/arm64/funopNarrower.S index 6fddfea979..e1a1214f11 100644 --- a/runtime/interpreter/mterp/arm64/funopNarrower.S +++ b/runtime/interpreter/mterp/arm64/funopNarrower.S @@ -1,4 +1,4 @@ -%default {"srcreg":"s0", "tgtreg":"d0"} +%def funopNarrower(srcreg="s0", tgtreg="d0", instr=""): /* * Generic 64bit-to-32bit floating point unary operation. Provide an * "instr" line that specifies an instruction that performs "$tgtreg = op $srcreg". diff --git a/runtime/interpreter/mterp/arm64/funopWide.S b/runtime/interpreter/mterp/arm64/funopWide.S index 409e26b6ec..83e55be206 100644 --- a/runtime/interpreter/mterp/arm64/funopWide.S +++ b/runtime/interpreter/mterp/arm64/funopWide.S @@ -1,4 +1,4 @@ -%default {"srcreg":"s0", "tgtreg":"d0"} +%def funopWide(srcreg="s0", tgtreg="d0", instr=""): /* * Generic 64bit-to-64bit floating point unary operation. Provide an * "instr" line that specifies an instruction that performs "$tgtreg = op $srcreg". diff --git a/runtime/interpreter/mterp/arm64/funopWider.S b/runtime/interpreter/mterp/arm64/funopWider.S index 4c91ebcdc6..825698ebf7 100644 --- a/runtime/interpreter/mterp/arm64/funopWider.S +++ b/runtime/interpreter/mterp/arm64/funopWider.S @@ -1,4 +1,4 @@ -%default {"srcreg":"s0", "tgtreg":"d0"} +%def funopWider(srcreg="s0", tgtreg="d0", instr=""): /* * Generic 32bit-to-64bit floating point unary operation. Provide an * "instr" line that specifies an instruction that performs "$tgtreg = op $srcreg". diff --git a/runtime/interpreter/mterp/arm64/header.S b/runtime/interpreter/mterp/arm64/header.S index 0722804265..41029729ca 100644 --- a/runtime/interpreter/mterp/arm64/header.S +++ b/runtime/interpreter/mterp/arm64/header.S @@ -1,3 +1,4 @@ +%def header(): /* * Copyright (C) 2016 The Android Open Source Project * diff --git a/runtime/interpreter/mterp/arm64/instruction_end.S b/runtime/interpreter/mterp/arm64/instruction_end.S index f90ebd0221..cf30a9b0b0 100644 --- a/runtime/interpreter/mterp/arm64/instruction_end.S +++ b/runtime/interpreter/mterp/arm64/instruction_end.S @@ -1,3 +1,4 @@ +%def instruction_end(): .type artMterpAsmInstructionEnd, #object .hidden artMterpAsmInstructionEnd diff --git a/runtime/interpreter/mterp/arm64/instruction_end_alt.S b/runtime/interpreter/mterp/arm64/instruction_end_alt.S index 0b66dbb947..9509a63b6a 100644 --- a/runtime/interpreter/mterp/arm64/instruction_end_alt.S +++ b/runtime/interpreter/mterp/arm64/instruction_end_alt.S @@ -1,3 +1,4 @@ +%def instruction_end_alt(): .type artMterpAsmAltInstructionEnd, #object .hidden artMterpAsmAltInstructionEnd diff --git a/runtime/interpreter/mterp/arm64/instruction_end_sister.S b/runtime/interpreter/mterp/arm64/instruction_end_sister.S index 71c0300f6d..18f1dbb38d 100644 --- a/runtime/interpreter/mterp/arm64/instruction_end_sister.S +++ b/runtime/interpreter/mterp/arm64/instruction_end_sister.S @@ -1,3 +1,4 @@ +%def instruction_end_sister(): .type artMterpAsmSisterEnd, #object .hidden artMterpAsmSisterEnd diff --git a/runtime/interpreter/mterp/arm64/instruction_start.S b/runtime/interpreter/mterp/arm64/instruction_start.S index b7e9cf51e4..457dcf9617 100644 --- a/runtime/interpreter/mterp/arm64/instruction_start.S +++ b/runtime/interpreter/mterp/arm64/instruction_start.S @@ -1,3 +1,4 @@ +%def instruction_start(): .type artMterpAsmInstructionStart, #object .hidden artMterpAsmInstructionStart diff --git a/runtime/interpreter/mterp/arm64/instruction_start_alt.S b/runtime/interpreter/mterp/arm64/instruction_start_alt.S index 7a67ba064c..40d2bf5dbe 100644 --- a/runtime/interpreter/mterp/arm64/instruction_start_alt.S +++ b/runtime/interpreter/mterp/arm64/instruction_start_alt.S @@ -1,3 +1,4 @@ +%def instruction_start_alt(): .type artMterpAsmAltInstructionStart, #object .hidden artMterpAsmAltInstructionStart diff --git a/runtime/interpreter/mterp/arm64/instruction_start_sister.S b/runtime/interpreter/mterp/arm64/instruction_start_sister.S index 0036061605..2bf24636ea 100644 --- a/runtime/interpreter/mterp/arm64/instruction_start_sister.S +++ b/runtime/interpreter/mterp/arm64/instruction_start_sister.S @@ -1,3 +1,4 @@ +%def instruction_start_sister(): .type artMterpAsmSisterStart, #object .hidden artMterpAsmSisterStart diff --git a/runtime/interpreter/mterp/arm64/invoke.S b/runtime/interpreter/mterp/arm64/invoke.S index 7a32df7bca..9e5b5b725a 100644 --- a/runtime/interpreter/mterp/arm64/invoke.S +++ b/runtime/interpreter/mterp/arm64/invoke.S @@ -1,4 +1,4 @@ -%default { "helper":"UndefinedInvokeHandler" } +%def invoke(helper="UndefinedInvokeHandler"): /* * Generic invoke handler wrapper. */ diff --git a/runtime/interpreter/mterp/arm64/invoke_polymorphic.S b/runtime/interpreter/mterp/arm64/invoke_polymorphic.S index 7906f0ada0..08ffb9cae7 100644 --- a/runtime/interpreter/mterp/arm64/invoke_polymorphic.S +++ b/runtime/interpreter/mterp/arm64/invoke_polymorphic.S @@ -1,4 +1,4 @@ -%default { "helper":"UndefinedInvokeHandler" } +%def invoke_polymorphic(helper="UndefinedInvokeHandler"): /* * invoke-polymorphic handler wrapper. */ diff --git a/runtime/interpreter/mterp/arm64/op_add_double.S b/runtime/interpreter/mterp/arm64/op_add_double.S index 8509f70309..8d31342b38 100644 --- a/runtime/interpreter/mterp/arm64/op_add_double.S +++ b/runtime/interpreter/mterp/arm64/op_add_double.S @@ -1 +1,2 @@ -%include "arm64/binopWide.S" {"instr":"fadd d0, d1, d2", "result":"d0", "r1":"d1", "r2":"d2"} +%def op_add_double(): +% binopWide(instr="fadd d0, d1, d2", result="d0", r1="d1", r2="d2") diff --git a/runtime/interpreter/mterp/arm64/op_add_double_2addr.S b/runtime/interpreter/mterp/arm64/op_add_double_2addr.S index 61fd58f4b6..88c1d5e0bd 100644 --- a/runtime/interpreter/mterp/arm64/op_add_double_2addr.S +++ b/runtime/interpreter/mterp/arm64/op_add_double_2addr.S @@ -1 +1,2 @@ -%include "arm64/binopWide2addr.S" {"instr":"fadd d0, d0, d1", "r0":"d0", "r1":"d1"} +%def op_add_double_2addr(): +% binopWide2addr(instr="fadd d0, d0, d1", r0="d0", r1="d1") diff --git a/runtime/interpreter/mterp/arm64/op_add_float.S b/runtime/interpreter/mterp/arm64/op_add_float.S index 7d09fef10a..388732e34e 100644 --- a/runtime/interpreter/mterp/arm64/op_add_float.S +++ b/runtime/interpreter/mterp/arm64/op_add_float.S @@ -1 +1,2 @@ -%include "arm64/fbinop.S" {"instr":"fadd s0, s0, s1"} +%def op_add_float(): +% fbinop(instr="fadd s0, s0, s1") diff --git a/runtime/interpreter/mterp/arm64/op_add_float_2addr.S b/runtime/interpreter/mterp/arm64/op_add_float_2addr.S index 7b378e2889..061c9d52ae 100644 --- a/runtime/interpreter/mterp/arm64/op_add_float_2addr.S +++ b/runtime/interpreter/mterp/arm64/op_add_float_2addr.S @@ -1 +1,2 @@ -%include "arm64/fbinop2addr.S" {"instr":"fadd s2, s0, s1"} +%def op_add_float_2addr(): +% fbinop2addr(instr="fadd s2, s0, s1") diff --git a/runtime/interpreter/mterp/arm64/op_add_int.S b/runtime/interpreter/mterp/arm64/op_add_int.S index 6eadb5441d..99953ee837 100644 --- a/runtime/interpreter/mterp/arm64/op_add_int.S +++ b/runtime/interpreter/mterp/arm64/op_add_int.S @@ -1 +1,2 @@ -%include "arm64/binop.S" {"instr":"add w0, w0, w1"} +%def op_add_int(): +% binop(instr="add w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_add_int_2addr.S b/runtime/interpreter/mterp/arm64/op_add_int_2addr.S index d35bc8ecc9..d61fcce27d 100644 --- a/runtime/interpreter/mterp/arm64/op_add_int_2addr.S +++ b/runtime/interpreter/mterp/arm64/op_add_int_2addr.S @@ -1 +1,2 @@ -%include "arm64/binop2addr.S" {"instr":"add w0, w0, w1"} +%def op_add_int_2addr(): +% binop2addr(instr="add w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_add_int_lit16.S b/runtime/interpreter/mterp/arm64/op_add_int_lit16.S index 4930ad7716..37bf2e8621 100644 --- a/runtime/interpreter/mterp/arm64/op_add_int_lit16.S +++ b/runtime/interpreter/mterp/arm64/op_add_int_lit16.S @@ -1 +1,2 @@ -%include "arm64/binopLit16.S" {"instr":"add w0, w0, w1"} +%def op_add_int_lit16(): +% binopLit16(instr="add w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_add_int_lit8.S b/runtime/interpreter/mterp/arm64/op_add_int_lit8.S index 2dfb8b9b56..f4cab96fec 100644 --- a/runtime/interpreter/mterp/arm64/op_add_int_lit8.S +++ b/runtime/interpreter/mterp/arm64/op_add_int_lit8.S @@ -1 +1,2 @@ -%include "arm64/binopLit8.S" {"extract":"", "instr":"add w0, w0, w3, asr #8"} +%def op_add_int_lit8(): +% binopLit8(extract="", instr="add w0, w0, w3, asr #8") diff --git a/runtime/interpreter/mterp/arm64/op_add_long.S b/runtime/interpreter/mterp/arm64/op_add_long.S index bc334aa3b2..0ac32466bc 100644 --- a/runtime/interpreter/mterp/arm64/op_add_long.S +++ b/runtime/interpreter/mterp/arm64/op_add_long.S @@ -1 +1,2 @@ -%include "arm64/binopWide.S" {"instr":"add x0, x1, x2"} +%def op_add_long(): +% binopWide(instr="add x0, x1, x2") diff --git a/runtime/interpreter/mterp/arm64/op_add_long_2addr.S b/runtime/interpreter/mterp/arm64/op_add_long_2addr.S index 5e5dbce73b..03987eb5c6 100644 --- a/runtime/interpreter/mterp/arm64/op_add_long_2addr.S +++ b/runtime/interpreter/mterp/arm64/op_add_long_2addr.S @@ -1 +1,2 @@ -%include "arm64/binopWide2addr.S" {"instr":"add x0, x0, x1"} +%def op_add_long_2addr(): +% binopWide2addr(instr="add x0, x0, x1") diff --git a/runtime/interpreter/mterp/arm64/op_aget.S b/runtime/interpreter/mterp/arm64/op_aget.S index 662c9cc7cc..edc62f5cbb 100644 --- a/runtime/interpreter/mterp/arm64/op_aget.S +++ b/runtime/interpreter/mterp/arm64/op_aget.S @@ -1,4 +1,4 @@ -%default { "load":"ldr", "shift":"2", "data_offset":"MIRROR_INT_ARRAY_DATA_OFFSET" } +%def op_aget(load="ldr", shift="2", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"): /* * Array get, 32 bits or less. vAA <- vBB[vCC]. * diff --git a/runtime/interpreter/mterp/arm64/op_aget_boolean.S b/runtime/interpreter/mterp/arm64/op_aget_boolean.S index 6ab6cc1bff..d6e0a1bbd9 100644 --- a/runtime/interpreter/mterp/arm64/op_aget_boolean.S +++ b/runtime/interpreter/mterp/arm64/op_aget_boolean.S @@ -1 +1,2 @@ -%include "arm64/op_aget.S" { "load":"ldrb", "shift":"0", "data_offset":"MIRROR_BOOLEAN_ARRAY_DATA_OFFSET" } +%def op_aget_boolean(): +% op_aget(load="ldrb", shift="0", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/arm64/op_aget_byte.S b/runtime/interpreter/mterp/arm64/op_aget_byte.S index c7f5b23ebf..6c9f1b78fa 100644 --- a/runtime/interpreter/mterp/arm64/op_aget_byte.S +++ b/runtime/interpreter/mterp/arm64/op_aget_byte.S @@ -1 +1,2 @@ -%include "arm64/op_aget.S" { "load":"ldrsb", "shift":"0", "data_offset":"MIRROR_BYTE_ARRAY_DATA_OFFSET" } +%def op_aget_byte(): +% op_aget(load="ldrsb", shift="0", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/arm64/op_aget_char.S b/runtime/interpreter/mterp/arm64/op_aget_char.S index 9fddf1787a..c5812e3aff 100644 --- a/runtime/interpreter/mterp/arm64/op_aget_char.S +++ b/runtime/interpreter/mterp/arm64/op_aget_char.S @@ -1 +1,2 @@ -%include "arm64/op_aget.S" { "load":"ldrh", "shift":"1", "data_offset":"MIRROR_CHAR_ARRAY_DATA_OFFSET" } +%def op_aget_char(): +% op_aget(load="ldrh", shift="1", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/arm64/op_aget_object.S b/runtime/interpreter/mterp/arm64/op_aget_object.S index 1bbe3e8a3a..0c5d2c394d 100644 --- a/runtime/interpreter/mterp/arm64/op_aget_object.S +++ b/runtime/interpreter/mterp/arm64/op_aget_object.S @@ -1,3 +1,4 @@ +%def op_aget_object(): /* * Array object get. vAA <- vBB[vCC]. * diff --git a/runtime/interpreter/mterp/arm64/op_aget_short.S b/runtime/interpreter/mterp/arm64/op_aget_short.S index 39554de6e6..9727560fe4 100644 --- a/runtime/interpreter/mterp/arm64/op_aget_short.S +++ b/runtime/interpreter/mterp/arm64/op_aget_short.S @@ -1 +1,2 @@ -%include "arm64/op_aget.S" { "load":"ldrsh", "shift":"1", "data_offset":"MIRROR_SHORT_ARRAY_DATA_OFFSET" } +%def op_aget_short(): +% op_aget(load="ldrsh", shift="1", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/arm64/op_aget_wide.S b/runtime/interpreter/mterp/arm64/op_aget_wide.S index 6f990ba0cc..e9bccd6e4e 100644 --- a/runtime/interpreter/mterp/arm64/op_aget_wide.S +++ b/runtime/interpreter/mterp/arm64/op_aget_wide.S @@ -1,3 +1,4 @@ +%def op_aget_wide(): /* * Array get, 64 bits. vAA <- vBB[vCC]. * diff --git a/runtime/interpreter/mterp/arm64/op_and_int.S b/runtime/interpreter/mterp/arm64/op_and_int.S index 31f3f73e7a..364e615843 100644 --- a/runtime/interpreter/mterp/arm64/op_and_int.S +++ b/runtime/interpreter/mterp/arm64/op_and_int.S @@ -1 +1,2 @@ -%include "arm64/binop.S" {"instr":"and w0, w0, w1"} +%def op_and_int(): +% binop(instr="and w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_and_int_2addr.S b/runtime/interpreter/mterp/arm64/op_and_int_2addr.S index e59632cd06..98a5c5db3a 100644 --- a/runtime/interpreter/mterp/arm64/op_and_int_2addr.S +++ b/runtime/interpreter/mterp/arm64/op_and_int_2addr.S @@ -1 +1,2 @@ -%include "arm64/binop2addr.S" {"instr":"and w0, w0, w1"} +%def op_and_int_2addr(): +% binop2addr(instr="and w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_and_int_lit16.S b/runtime/interpreter/mterp/arm64/op_and_int_lit16.S index 6540f81554..add2ecc83b 100644 --- a/runtime/interpreter/mterp/arm64/op_and_int_lit16.S +++ b/runtime/interpreter/mterp/arm64/op_and_int_lit16.S @@ -1 +1,2 @@ -%include "arm64/binopLit16.S" {"instr":"and w0, w0, w1"} +%def op_and_int_lit16(): +% binopLit16(instr="and w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_and_int_lit8.S b/runtime/interpreter/mterp/arm64/op_and_int_lit8.S index 495b5cddd6..bf68c2a5cc 100644 --- a/runtime/interpreter/mterp/arm64/op_and_int_lit8.S +++ b/runtime/interpreter/mterp/arm64/op_and_int_lit8.S @@ -1 +1,2 @@ -%include "arm64/binopLit8.S" {"extract":"", "instr":"and w0, w0, w3, asr #8"} +%def op_and_int_lit8(): +% binopLit8(extract="", instr="and w0, w0, w3, asr #8") diff --git a/runtime/interpreter/mterp/arm64/op_and_long.S b/runtime/interpreter/mterp/arm64/op_and_long.S index ede047d088..aff5eadd05 100644 --- a/runtime/interpreter/mterp/arm64/op_and_long.S +++ b/runtime/interpreter/mterp/arm64/op_and_long.S @@ -1 +1,2 @@ -%include "arm64/binopWide.S" {"instr":"and x0, x1, x2"} +%def op_and_long(): +% binopWide(instr="and x0, x1, x2") diff --git a/runtime/interpreter/mterp/arm64/op_and_long_2addr.S b/runtime/interpreter/mterp/arm64/op_and_long_2addr.S index d62ccef891..ba71e5cec1 100644 --- a/runtime/interpreter/mterp/arm64/op_and_long_2addr.S +++ b/runtime/interpreter/mterp/arm64/op_and_long_2addr.S @@ -1 +1,2 @@ -%include "arm64/binopWide2addr.S" {"instr":"and x0, x0, x1"} +%def op_and_long_2addr(): +% binopWide2addr(instr="and x0, x0, x1") diff --git a/runtime/interpreter/mterp/arm64/op_aput.S b/runtime/interpreter/mterp/arm64/op_aput.S index 175b483d7d..85dd5564a9 100644 --- a/runtime/interpreter/mterp/arm64/op_aput.S +++ b/runtime/interpreter/mterp/arm64/op_aput.S @@ -1,4 +1,4 @@ -%default { "store":"str", "shift":"2", "data_offset":"MIRROR_INT_ARRAY_DATA_OFFSET" } +%def op_aput(store="str", shift="2", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"): /* * Array put, 32 bits or less. vBB[vCC] <- vAA. * diff --git a/runtime/interpreter/mterp/arm64/op_aput_boolean.S b/runtime/interpreter/mterp/arm64/op_aput_boolean.S index 5e7a86f15c..467cc4bf20 100644 --- a/runtime/interpreter/mterp/arm64/op_aput_boolean.S +++ b/runtime/interpreter/mterp/arm64/op_aput_boolean.S @@ -1 +1,2 @@ -%include "arm64/op_aput.S" { "store":"strb", "shift":"0", "data_offset":"MIRROR_BOOLEAN_ARRAY_DATA_OFFSET" } +%def op_aput_boolean(): +% op_aput(store="strb", shift="0", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/arm64/op_aput_byte.S b/runtime/interpreter/mterp/arm64/op_aput_byte.S index d659ebc3d0..2b4c0ba389 100644 --- a/runtime/interpreter/mterp/arm64/op_aput_byte.S +++ b/runtime/interpreter/mterp/arm64/op_aput_byte.S @@ -1 +1,2 @@ -%include "arm64/op_aput.S" { "store":"strb", "shift":"0", "data_offset":"MIRROR_BYTE_ARRAY_DATA_OFFSET" } +%def op_aput_byte(): +% op_aput(store="strb", shift="0", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/arm64/op_aput_char.S b/runtime/interpreter/mterp/arm64/op_aput_char.S index 7547c80870..cb7dcbad4d 100644 --- a/runtime/interpreter/mterp/arm64/op_aput_char.S +++ b/runtime/interpreter/mterp/arm64/op_aput_char.S @@ -1 +1,2 @@ -%include "arm64/op_aput.S" { "store":"strh", "shift":"1", "data_offset":"MIRROR_CHAR_ARRAY_DATA_OFFSET" } +%def op_aput_char(): +% op_aput(store="strh", shift="1", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/arm64/op_aput_object.S b/runtime/interpreter/mterp/arm64/op_aput_object.S index 0146fdc95c..4d1ee65f7f 100644 --- a/runtime/interpreter/mterp/arm64/op_aput_object.S +++ b/runtime/interpreter/mterp/arm64/op_aput_object.S @@ -1,3 +1,4 @@ +%def op_aput_object(): /* * Store an object into an array. vBB[vCC] <- vAA. */ diff --git a/runtime/interpreter/mterp/arm64/op_aput_short.S b/runtime/interpreter/mterp/arm64/op_aput_short.S index 8631e28070..f624163087 100644 --- a/runtime/interpreter/mterp/arm64/op_aput_short.S +++ b/runtime/interpreter/mterp/arm64/op_aput_short.S @@ -1 +1,2 @@ -%include "arm64/op_aput.S" { "store":"strh", "shift":"1", "data_offset":"MIRROR_SHORT_ARRAY_DATA_OFFSET" } +%def op_aput_short(): +% op_aput(store="strh", shift="1", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/arm64/op_aput_wide.S b/runtime/interpreter/mterp/arm64/op_aput_wide.S index e1cf9c1c2f..8498783f81 100644 --- a/runtime/interpreter/mterp/arm64/op_aput_wide.S +++ b/runtime/interpreter/mterp/arm64/op_aput_wide.S @@ -1,3 +1,4 @@ +%def op_aput_wide(): /* * Array put, 64 bits. vBB[vCC] <- vAA. * diff --git a/runtime/interpreter/mterp/arm64/op_array_length.S b/runtime/interpreter/mterp/arm64/op_array_length.S index 0cce917ff7..26979b837f 100644 --- a/runtime/interpreter/mterp/arm64/op_array_length.S +++ b/runtime/interpreter/mterp/arm64/op_array_length.S @@ -1,3 +1,4 @@ +%def op_array_length(): /* * Return the length of an array. */ diff --git a/runtime/interpreter/mterp/arm64/op_check_cast.S b/runtime/interpreter/mterp/arm64/op_check_cast.S index cb9f6068e0..359c860e48 100644 --- a/runtime/interpreter/mterp/arm64/op_check_cast.S +++ b/runtime/interpreter/mterp/arm64/op_check_cast.S @@ -1,3 +1,4 @@ +%def op_check_cast(): /* * Check to see if a cast from one class to another is allowed. */ diff --git a/runtime/interpreter/mterp/arm64/op_cmp_long.S b/runtime/interpreter/mterp/arm64/op_cmp_long.S index c4ad984084..636262c2f7 100644 --- a/runtime/interpreter/mterp/arm64/op_cmp_long.S +++ b/runtime/interpreter/mterp/arm64/op_cmp_long.S @@ -1,3 +1,4 @@ +%def op_cmp_long(): FETCH w0, 1 // w0<- CCBB lsr w4, wINST, #8 // w4<- AA and w2, w0, #255 // w2<- BB diff --git a/runtime/interpreter/mterp/arm64/op_cmpg_double.S b/runtime/interpreter/mterp/arm64/op_cmpg_double.S index 30cb7ebbe2..4527873eb1 100644 --- a/runtime/interpreter/mterp/arm64/op_cmpg_double.S +++ b/runtime/interpreter/mterp/arm64/op_cmpg_double.S @@ -1 +1,2 @@ -%include "arm64/fcmp.S" {"wide":"_WIDE", "r1":"d1", "r2":"d2", "cond":"cc"} +%def op_cmpg_double(): +% fcmp(wide="_WIDE", r1="d1", r2="d2", cond="cc") diff --git a/runtime/interpreter/mterp/arm64/op_cmpg_float.S b/runtime/interpreter/mterp/arm64/op_cmpg_float.S index ba23f43462..395d1862f7 100644 --- a/runtime/interpreter/mterp/arm64/op_cmpg_float.S +++ b/runtime/interpreter/mterp/arm64/op_cmpg_float.S @@ -1 +1,2 @@ -%include "arm64/fcmp.S" {"wide":"", "r1":"s1", "r2":"s2", "cond":"cc"} +%def op_cmpg_float(): +% fcmp(wide="", r1="s1", r2="s2", cond="cc") diff --git a/runtime/interpreter/mterp/arm64/op_cmpl_double.S b/runtime/interpreter/mterp/arm64/op_cmpl_double.S index c73968588e..67b69c8b65 100644 --- a/runtime/interpreter/mterp/arm64/op_cmpl_double.S +++ b/runtime/interpreter/mterp/arm64/op_cmpl_double.S @@ -1 +1,2 @@ -%include "arm64/fcmp.S" {"wide":"_WIDE", "r1":"d1", "r2":"d2", "cond":"lt"} +%def op_cmpl_double(): +% fcmp(wide="_WIDE", r1="d1", r2="d2", cond="lt") diff --git a/runtime/interpreter/mterp/arm64/op_cmpl_float.S b/runtime/interpreter/mterp/arm64/op_cmpl_float.S index 32a931935b..7574f4cec7 100644 --- a/runtime/interpreter/mterp/arm64/op_cmpl_float.S +++ b/runtime/interpreter/mterp/arm64/op_cmpl_float.S @@ -1 +1,2 @@ -%include "arm64/fcmp.S" {"wide":"", "r1":"s1", "r2":"s2", "cond":"lt"} +%def op_cmpl_float(): +% fcmp(wide="", r1="s1", r2="s2", cond="lt") diff --git a/runtime/interpreter/mterp/arm64/op_const.S b/runtime/interpreter/mterp/arm64/op_const.S index 031ede1fb2..493611e473 100644 --- a/runtime/interpreter/mterp/arm64/op_const.S +++ b/runtime/interpreter/mterp/arm64/op_const.S @@ -1,3 +1,4 @@ +%def op_const(): /* const vAA, #+BBBBbbbb */ lsr w3, wINST, #8 // w3<- AA FETCH w0, 1 // w0<- bbbb (low diff --git a/runtime/interpreter/mterp/arm64/op_const_16.S b/runtime/interpreter/mterp/arm64/op_const_16.S index f0e81923c5..75e69364a7 100644 --- a/runtime/interpreter/mterp/arm64/op_const_16.S +++ b/runtime/interpreter/mterp/arm64/op_const_16.S @@ -1,3 +1,4 @@ +%def op_const_16(): /* const/16 vAA, #+BBBB */ FETCH_S w0, 1 // w0<- ssssBBBB (sign-extended) lsr w3, wINST, #8 // w3<- AA diff --git a/runtime/interpreter/mterp/arm64/op_const_4.S b/runtime/interpreter/mterp/arm64/op_const_4.S index 9a36115288..e6281ed82c 100644 --- a/runtime/interpreter/mterp/arm64/op_const_4.S +++ b/runtime/interpreter/mterp/arm64/op_const_4.S @@ -1,3 +1,4 @@ +%def op_const_4(): /* const/4 vA, #+B */ sbfx w1, wINST, #12, #4 // w1<- sssssssB ubfx w0, wINST, #8, #4 // w0<- A diff --git a/runtime/interpreter/mterp/arm64/op_const_class.S b/runtime/interpreter/mterp/arm64/op_const_class.S index 7228245b8f..db12ec3141 100644 --- a/runtime/interpreter/mterp/arm64/op_const_class.S +++ b/runtime/interpreter/mterp/arm64/op_const_class.S @@ -1 +1,2 @@ -%include "arm64/const.S" { "helper":"MterpConstClass" } +%def op_const_class(): +% const(helper="MterpConstClass") diff --git a/runtime/interpreter/mterp/arm64/op_const_high16.S b/runtime/interpreter/mterp/arm64/op_const_high16.S index 3a9edfff91..8a8558f0fc 100644 --- a/runtime/interpreter/mterp/arm64/op_const_high16.S +++ b/runtime/interpreter/mterp/arm64/op_const_high16.S @@ -1,3 +1,4 @@ +%def op_const_high16(): /* const/high16 vAA, #+BBBB0000 */ FETCH w0, 1 // r0<- 0000BBBB (zero-extended) lsr w3, wINST, #8 // r3<- AA diff --git a/runtime/interpreter/mterp/arm64/op_const_method_handle.S b/runtime/interpreter/mterp/arm64/op_const_method_handle.S index 0df0fa6798..2680c17aad 100644 --- a/runtime/interpreter/mterp/arm64/op_const_method_handle.S +++ b/runtime/interpreter/mterp/arm64/op_const_method_handle.S @@ -1 +1,2 @@ -%include "arm64/const.S" { "helper":"MterpConstMethodHandle" } +%def op_const_method_handle(): +% const(helper="MterpConstMethodHandle") diff --git a/runtime/interpreter/mterp/arm64/op_const_method_type.S b/runtime/interpreter/mterp/arm64/op_const_method_type.S index 1adfe5ad65..ea814bf648 100644 --- a/runtime/interpreter/mterp/arm64/op_const_method_type.S +++ b/runtime/interpreter/mterp/arm64/op_const_method_type.S @@ -1 +1,2 @@ -%include "arm64/const.S" { "helper":"MterpConstMethodType" } +%def op_const_method_type(): +% const(helper="MterpConstMethodType") diff --git a/runtime/interpreter/mterp/arm64/op_const_string.S b/runtime/interpreter/mterp/arm64/op_const_string.S index 8cf0d6dc35..41376f8703 100644 --- a/runtime/interpreter/mterp/arm64/op_const_string.S +++ b/runtime/interpreter/mterp/arm64/op_const_string.S @@ -1 +1,2 @@ -%include "arm64/const.S" { "helper":"MterpConstString" } +%def op_const_string(): +% const(helper="MterpConstString") diff --git a/runtime/interpreter/mterp/arm64/op_const_string_jumbo.S b/runtime/interpreter/mterp/arm64/op_const_string_jumbo.S index e1a733987d..1a78bcb799 100644 --- a/runtime/interpreter/mterp/arm64/op_const_string_jumbo.S +++ b/runtime/interpreter/mterp/arm64/op_const_string_jumbo.S @@ -1,3 +1,4 @@ +%def op_const_string_jumbo(): /* const/string vAA, String//BBBBBBBB */ EXPORT_PC FETCH w0, 1 // w0<- bbbb (low diff --git a/runtime/interpreter/mterp/arm64/op_const_wide.S b/runtime/interpreter/mterp/arm64/op_const_wide.S index 8f57ddacfd..6d3be6b127 100644 --- a/runtime/interpreter/mterp/arm64/op_const_wide.S +++ b/runtime/interpreter/mterp/arm64/op_const_wide.S @@ -1,3 +1,4 @@ +%def op_const_wide(): /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ FETCH w0, 1 // w0<- bbbb (low) FETCH w1, 2 // w1<- BBBB (low middle) diff --git a/runtime/interpreter/mterp/arm64/op_const_wide_16.S b/runtime/interpreter/mterp/arm64/op_const_wide_16.S index 553d481541..04615e1d4e 100644 --- a/runtime/interpreter/mterp/arm64/op_const_wide_16.S +++ b/runtime/interpreter/mterp/arm64/op_const_wide_16.S @@ -1,3 +1,4 @@ +%def op_const_wide_16(): /* const-wide/16 vAA, #+BBBB */ FETCH_S x0, 1 // x0<- ssssssssssssBBBB (sign-extended) lsr w3, wINST, #8 // w3<- AA diff --git a/runtime/interpreter/mterp/arm64/op_const_wide_32.S b/runtime/interpreter/mterp/arm64/op_const_wide_32.S index 9dc4fc3867..627ddea3ea 100644 --- a/runtime/interpreter/mterp/arm64/op_const_wide_32.S +++ b/runtime/interpreter/mterp/arm64/op_const_wide_32.S @@ -1,3 +1,4 @@ +%def op_const_wide_32(): /* const-wide/32 vAA, #+BBBBbbbb */ FETCH w0, 1 // x0<- 000000000000bbbb (low) lsr w3, wINST, #8 // w3<- AA diff --git a/runtime/interpreter/mterp/arm64/op_const_wide_high16.S b/runtime/interpreter/mterp/arm64/op_const_wide_high16.S index 94ab9876c8..d51d25f3e1 100644 --- a/runtime/interpreter/mterp/arm64/op_const_wide_high16.S +++ b/runtime/interpreter/mterp/arm64/op_const_wide_high16.S @@ -1,3 +1,4 @@ +%def op_const_wide_high16(): /* const-wide/high16 vAA, #+BBBB000000000000 */ FETCH w0, 1 // w0<- 0000BBBB (zero-extended) lsr w1, wINST, #8 // w1<- AA diff --git a/runtime/interpreter/mterp/arm64/op_div_double.S b/runtime/interpreter/mterp/arm64/op_div_double.S index 1f7dad0917..ec5b1f5bbb 100644 --- a/runtime/interpreter/mterp/arm64/op_div_double.S +++ b/runtime/interpreter/mterp/arm64/op_div_double.S @@ -1 +1,2 @@ -%include "arm64/binopWide.S" {"instr":"fdiv d0, d1, d2", "result":"d0", "r1":"d1", "r2":"d2"} +%def op_div_double(): +% binopWide(instr="fdiv d0, d1, d2", result="d0", r1="d1", r2="d2") diff --git a/runtime/interpreter/mterp/arm64/op_div_double_2addr.S b/runtime/interpreter/mterp/arm64/op_div_double_2addr.S index 414a175658..e2781b884f 100644 --- a/runtime/interpreter/mterp/arm64/op_div_double_2addr.S +++ b/runtime/interpreter/mterp/arm64/op_div_double_2addr.S @@ -1 +1,2 @@ -%include "arm64/binopWide2addr.S" {"instr":"fdiv d0, d0, d1", "r0":"d0", "r1":"d1"} +%def op_div_double_2addr(): +% binopWide2addr(instr="fdiv d0, d0, d1", r0="d0", r1="d1") diff --git a/runtime/interpreter/mterp/arm64/op_div_float.S b/runtime/interpreter/mterp/arm64/op_div_float.S index f24a26c09b..f0e72c43f9 100644 --- a/runtime/interpreter/mterp/arm64/op_div_float.S +++ b/runtime/interpreter/mterp/arm64/op_div_float.S @@ -1 +1,2 @@ -%include "arm64/fbinop.S" {"instr":"fdiv s0, s0, s1"} +%def op_div_float(): +% fbinop(instr="fdiv s0, s0, s1") diff --git a/runtime/interpreter/mterp/arm64/op_div_float_2addr.S b/runtime/interpreter/mterp/arm64/op_div_float_2addr.S index 2888049c9e..aa73950ce5 100644 --- a/runtime/interpreter/mterp/arm64/op_div_float_2addr.S +++ b/runtime/interpreter/mterp/arm64/op_div_float_2addr.S @@ -1 +1,2 @@ -%include "arm64/fbinop2addr.S" {"instr":"fdiv s2, s0, s1"} +%def op_div_float_2addr(): +% fbinop2addr(instr="fdiv s2, s0, s1") diff --git a/runtime/interpreter/mterp/arm64/op_div_int.S b/runtime/interpreter/mterp/arm64/op_div_int.S index 88371c08d9..6f4cbf327f 100644 --- a/runtime/interpreter/mterp/arm64/op_div_int.S +++ b/runtime/interpreter/mterp/arm64/op_div_int.S @@ -1 +1,2 @@ -%include "arm64/binop.S" {"instr":"sdiv w0, w0, w1", "chkzero":"1"} +%def op_div_int(): +% binop(instr="sdiv w0, w0, w1", chkzero="1") diff --git a/runtime/interpreter/mterp/arm64/op_div_int_2addr.S b/runtime/interpreter/mterp/arm64/op_div_int_2addr.S index 5f5a80fe52..eb01066621 100644 --- a/runtime/interpreter/mterp/arm64/op_div_int_2addr.S +++ b/runtime/interpreter/mterp/arm64/op_div_int_2addr.S @@ -1 +1,2 @@ -%include "arm64/binop2addr.S" {"instr":"sdiv w0, w0, w1", "chkzero":"1"} +%def op_div_int_2addr(): +% binop2addr(instr="sdiv w0, w0, w1", chkzero="1") diff --git a/runtime/interpreter/mterp/arm64/op_div_int_lit16.S b/runtime/interpreter/mterp/arm64/op_div_int_lit16.S index dc7a484c6a..c5cdb96fcf 100644 --- a/runtime/interpreter/mterp/arm64/op_div_int_lit16.S +++ b/runtime/interpreter/mterp/arm64/op_div_int_lit16.S @@ -1 +1,2 @@ -%include "arm64/binopLit16.S" {"instr":"sdiv w0, w0, w1", "chkzero":"1"} +%def op_div_int_lit16(): +% binopLit16(instr="sdiv w0, w0, w1", chkzero="1") diff --git a/runtime/interpreter/mterp/arm64/op_div_int_lit8.S b/runtime/interpreter/mterp/arm64/op_div_int_lit8.S index c06521c4bc..3842cd92b1 100644 --- a/runtime/interpreter/mterp/arm64/op_div_int_lit8.S +++ b/runtime/interpreter/mterp/arm64/op_div_int_lit8.S @@ -1 +1,2 @@ -%include "arm64/binopLit8.S" {"instr":"sdiv w0, w0, w1", "chkzero":"1"} +%def op_div_int_lit8(): +% binopLit8(instr="sdiv w0, w0, w1", chkzero="1") diff --git a/runtime/interpreter/mterp/arm64/op_div_long.S b/runtime/interpreter/mterp/arm64/op_div_long.S index 820ae3db68..696a91f134 100644 --- a/runtime/interpreter/mterp/arm64/op_div_long.S +++ b/runtime/interpreter/mterp/arm64/op_div_long.S @@ -1 +1,2 @@ -%include "arm64/binopWide.S" {"instr":"sdiv x0, x1, x2", "chkzero":"1"} +%def op_div_long(): +% binopWide(instr="sdiv x0, x1, x2", chkzero="1") diff --git a/runtime/interpreter/mterp/arm64/op_div_long_2addr.S b/runtime/interpreter/mterp/arm64/op_div_long_2addr.S index da7eabdc9d..cac878c41c 100644 --- a/runtime/interpreter/mterp/arm64/op_div_long_2addr.S +++ b/runtime/interpreter/mterp/arm64/op_div_long_2addr.S @@ -1 +1,2 @@ -%include "arm64/binopWide2addr.S" {"instr":"sdiv x0, x0, x1", "chkzero":"1"} +%def op_div_long_2addr(): +% binopWide2addr(instr="sdiv x0, x0, x1", chkzero="1") diff --git a/runtime/interpreter/mterp/arm64/op_double_to_float.S b/runtime/interpreter/mterp/arm64/op_double_to_float.S index c1555fdaf9..292dcc78a6 100644 --- a/runtime/interpreter/mterp/arm64/op_double_to_float.S +++ b/runtime/interpreter/mterp/arm64/op_double_to_float.S @@ -1 +1,2 @@ -%include "arm64/funopNarrower.S" {"instr":"fcvt s0, d0", "srcreg":"d0", "tgtreg":"s0"} +%def op_double_to_float(): +% funopNarrower(instr="fcvt s0, d0", srcreg="d0", tgtreg="s0") diff --git a/runtime/interpreter/mterp/arm64/op_double_to_int.S b/runtime/interpreter/mterp/arm64/op_double_to_int.S index 7244bac2fc..640e6daa81 100644 --- a/runtime/interpreter/mterp/arm64/op_double_to_int.S +++ b/runtime/interpreter/mterp/arm64/op_double_to_int.S @@ -1 +1,2 @@ -%include "arm64/funopNarrower.S" {"instr":"fcvtzs w0, d0", "srcreg":"d0", "tgtreg":"w0"} +%def op_double_to_int(): +% funopNarrower(instr="fcvtzs w0, d0", srcreg="d0", tgtreg="w0") diff --git a/runtime/interpreter/mterp/arm64/op_double_to_long.S b/runtime/interpreter/mterp/arm64/op_double_to_long.S index 741160b564..99c15eb601 100644 --- a/runtime/interpreter/mterp/arm64/op_double_to_long.S +++ b/runtime/interpreter/mterp/arm64/op_double_to_long.S @@ -1 +1,2 @@ -%include "arm64/funopWide.S" {"instr":"fcvtzs x0, d0", "srcreg":"d0", "tgtreg":"x0"} +%def op_double_to_long(): +% funopWide(instr="fcvtzs x0, d0", srcreg="d0", tgtreg="x0") diff --git a/runtime/interpreter/mterp/arm64/op_fill_array_data.S b/runtime/interpreter/mterp/arm64/op_fill_array_data.S index 86fa6dbbd2..2ae444cc29 100644 --- a/runtime/interpreter/mterp/arm64/op_fill_array_data.S +++ b/runtime/interpreter/mterp/arm64/op_fill_array_data.S @@ -1,3 +1,4 @@ +%def op_fill_array_data(): /* fill-array-data vAA, +BBBBBBBB */ EXPORT_PC FETCH w0, 1 // x0<- 000000000000bbbb (lo) diff --git a/runtime/interpreter/mterp/arm64/op_filled_new_array.S b/runtime/interpreter/mterp/arm64/op_filled_new_array.S index 806a1b1201..2be627c3af 100644 --- a/runtime/interpreter/mterp/arm64/op_filled_new_array.S +++ b/runtime/interpreter/mterp/arm64/op_filled_new_array.S @@ -1,4 +1,4 @@ -%default { "helper":"MterpFilledNewArray" } +%def op_filled_new_array(helper="MterpFilledNewArray"): /* * Create a new array with elements filled from registers. * diff --git a/runtime/interpreter/mterp/arm64/op_filled_new_array_range.S b/runtime/interpreter/mterp/arm64/op_filled_new_array_range.S index 3c9a419628..1667de149a 100644 --- a/runtime/interpreter/mterp/arm64/op_filled_new_array_range.S +++ b/runtime/interpreter/mterp/arm64/op_filled_new_array_range.S @@ -1 +1,2 @@ -%include "arm64/op_filled_new_array.S" { "helper":"MterpFilledNewArrayRange" } +%def op_filled_new_array_range(): +% op_filled_new_array(helper="MterpFilledNewArrayRange") diff --git a/runtime/interpreter/mterp/arm64/op_float_to_double.S b/runtime/interpreter/mterp/arm64/op_float_to_double.S index 892feca21b..c3dff39283 100644 --- a/runtime/interpreter/mterp/arm64/op_float_to_double.S +++ b/runtime/interpreter/mterp/arm64/op_float_to_double.S @@ -1 +1,2 @@ -%include "arm64/funopWider.S" {"instr":"fcvt d0, s0", "srcreg":"s0", "tgtreg":"d0"} +%def op_float_to_double(): +% funopWider(instr="fcvt d0, s0", srcreg="s0", tgtreg="d0") diff --git a/runtime/interpreter/mterp/arm64/op_float_to_int.S b/runtime/interpreter/mterp/arm64/op_float_to_int.S index c849d8165d..ed784e2e14 100644 --- a/runtime/interpreter/mterp/arm64/op_float_to_int.S +++ b/runtime/interpreter/mterp/arm64/op_float_to_int.S @@ -1 +1,2 @@ -%include "arm64/funopNarrow.S" {"instr":"fcvtzs w0, s0", "srcreg":"s0", "tgtreg":"w0"} +%def op_float_to_int(): +% funopNarrow(instr="fcvtzs w0, s0", srcreg="s0", tgtreg="w0") diff --git a/runtime/interpreter/mterp/arm64/op_float_to_long.S b/runtime/interpreter/mterp/arm64/op_float_to_long.S index c3de16f9ff..14912493b5 100644 --- a/runtime/interpreter/mterp/arm64/op_float_to_long.S +++ b/runtime/interpreter/mterp/arm64/op_float_to_long.S @@ -1 +1,2 @@ -%include "arm64/funopWider.S" {"instr":"fcvtzs x0, s0", "srcreg":"s0", "tgtreg":"x0"} +%def op_float_to_long(): +% funopWider(instr="fcvtzs x0, s0", srcreg="s0", tgtreg="x0") diff --git a/runtime/interpreter/mterp/arm64/op_goto.S b/runtime/interpreter/mterp/arm64/op_goto.S index 6381e94fb5..722eec60a3 100644 --- a/runtime/interpreter/mterp/arm64/op_goto.S +++ b/runtime/interpreter/mterp/arm64/op_goto.S @@ -1,3 +1,4 @@ +%def op_goto(): /* * Unconditional branch, 8-bit offset. * diff --git a/runtime/interpreter/mterp/arm64/op_goto_16.S b/runtime/interpreter/mterp/arm64/op_goto_16.S index fb9a80a3c1..b5cfa71fce 100644 --- a/runtime/interpreter/mterp/arm64/op_goto_16.S +++ b/runtime/interpreter/mterp/arm64/op_goto_16.S @@ -1,3 +1,4 @@ +%def op_goto_16(): /* * Unconditional branch, 16-bit offset. * diff --git a/runtime/interpreter/mterp/arm64/op_goto_32.S b/runtime/interpreter/mterp/arm64/op_goto_32.S index b13cb41bc7..3843ba2af3 100644 --- a/runtime/interpreter/mterp/arm64/op_goto_32.S +++ b/runtime/interpreter/mterp/arm64/op_goto_32.S @@ -1,3 +1,4 @@ +%def op_goto_32(): /* * Unconditional branch, 32-bit offset. * diff --git a/runtime/interpreter/mterp/arm64/op_if_eq.S b/runtime/interpreter/mterp/arm64/op_if_eq.S index aa4a0f16a7..da58674fd4 100644 --- a/runtime/interpreter/mterp/arm64/op_if_eq.S +++ b/runtime/interpreter/mterp/arm64/op_if_eq.S @@ -1 +1,2 @@ -%include "arm64/bincmp.S" { "condition":"eq" } +%def op_if_eq(): +% bincmp(condition="eq") diff --git a/runtime/interpreter/mterp/arm64/op_if_eqz.S b/runtime/interpreter/mterp/arm64/op_if_eqz.S index 47c1dee8cf..8241db8287 100644 --- a/runtime/interpreter/mterp/arm64/op_if_eqz.S +++ b/runtime/interpreter/mterp/arm64/op_if_eqz.S @@ -1 +1,2 @@ -%include "arm64/zcmp.S" { "compare":"0", "branch":"cbz w2," } +%def op_if_eqz(): +% zcmp(compare="0", branch="cbz w2,") diff --git a/runtime/interpreter/mterp/arm64/op_if_ge.S b/runtime/interpreter/mterp/arm64/op_if_ge.S index d6ec761bfe..5b6ed2f994 100644 --- a/runtime/interpreter/mterp/arm64/op_if_ge.S +++ b/runtime/interpreter/mterp/arm64/op_if_ge.S @@ -1 +1,2 @@ -%include "arm64/bincmp.S" { "condition":"ge" } +%def op_if_ge(): +% bincmp(condition="ge") diff --git a/runtime/interpreter/mterp/arm64/op_if_gez.S b/runtime/interpreter/mterp/arm64/op_if_gez.S index 087e094a76..f7903b8b1d 100644 --- a/runtime/interpreter/mterp/arm64/op_if_gez.S +++ b/runtime/interpreter/mterp/arm64/op_if_gez.S @@ -1 +1,2 @@ -%include "arm64/zcmp.S" { "compare":"0", "branch":"tbz w2, #31," } +%def op_if_gez(): +% zcmp(compare="0", branch="tbz w2, #31,") diff --git a/runtime/interpreter/mterp/arm64/op_if_gt.S b/runtime/interpreter/mterp/arm64/op_if_gt.S index 7db8e9d911..201decff1a 100644 --- a/runtime/interpreter/mterp/arm64/op_if_gt.S +++ b/runtime/interpreter/mterp/arm64/op_if_gt.S @@ -1 +1,2 @@ -%include "arm64/bincmp.S" { "condition":"gt" } +%def op_if_gt(): +% bincmp(condition="gt") diff --git a/runtime/interpreter/mterp/arm64/op_if_gtz.S b/runtime/interpreter/mterp/arm64/op_if_gtz.S index 476b265431..e0663a0206 100644 --- a/runtime/interpreter/mterp/arm64/op_if_gtz.S +++ b/runtime/interpreter/mterp/arm64/op_if_gtz.S @@ -1 +1,2 @@ -%include "arm64/zcmp.S" { "branch":"b.gt" } +%def op_if_gtz(): +% zcmp(branch="b.gt") diff --git a/runtime/interpreter/mterp/arm64/op_if_le.S b/runtime/interpreter/mterp/arm64/op_if_le.S index ca3a83fff7..e6024f2b3e 100644 --- a/runtime/interpreter/mterp/arm64/op_if_le.S +++ b/runtime/interpreter/mterp/arm64/op_if_le.S @@ -1 +1,2 @@ -%include "arm64/bincmp.S" { "condition":"le" } +%def op_if_le(): +% bincmp(condition="le") diff --git a/runtime/interpreter/mterp/arm64/op_if_lez.S b/runtime/interpreter/mterp/arm64/op_if_lez.S index 2717a60ebf..7ec4a9ee26 100644 --- a/runtime/interpreter/mterp/arm64/op_if_lez.S +++ b/runtime/interpreter/mterp/arm64/op_if_lez.S @@ -1 +1,2 @@ -%include "arm64/zcmp.S" { "branch":"b.le" } +%def op_if_lez(): +% zcmp(branch="b.le") diff --git a/runtime/interpreter/mterp/arm64/op_if_lt.S b/runtime/interpreter/mterp/arm64/op_if_lt.S index 56450a15ca..4ef22fd798 100644 --- a/runtime/interpreter/mterp/arm64/op_if_lt.S +++ b/runtime/interpreter/mterp/arm64/op_if_lt.S @@ -1 +1,2 @@ -%include "arm64/bincmp.S" { "condition":"lt" } +%def op_if_lt(): +% bincmp(condition="lt") diff --git a/runtime/interpreter/mterp/arm64/op_if_ltz.S b/runtime/interpreter/mterp/arm64/op_if_ltz.S index 86089c10ba..a9f04ee478 100644 --- a/runtime/interpreter/mterp/arm64/op_if_ltz.S +++ b/runtime/interpreter/mterp/arm64/op_if_ltz.S @@ -1 +1,2 @@ -%include "arm64/zcmp.S" { "compare":"0", "branch":"tbnz w2, #31," } +%def op_if_ltz(): +% zcmp(compare="0", branch="tbnz w2, #31,") diff --git a/runtime/interpreter/mterp/arm64/op_if_ne.S b/runtime/interpreter/mterp/arm64/op_if_ne.S index 14d9e13dcf..ec3a688b29 100644 --- a/runtime/interpreter/mterp/arm64/op_if_ne.S +++ b/runtime/interpreter/mterp/arm64/op_if_ne.S @@ -1 +1,2 @@ -%include "arm64/bincmp.S" { "condition":"ne" } +%def op_if_ne(): +% bincmp(condition="ne") diff --git a/runtime/interpreter/mterp/arm64/op_if_nez.S b/runtime/interpreter/mterp/arm64/op_if_nez.S index efacc88806..c4bb3b3bdf 100644 --- a/runtime/interpreter/mterp/arm64/op_if_nez.S +++ b/runtime/interpreter/mterp/arm64/op_if_nez.S @@ -1 +1,2 @@ -%include "arm64/zcmp.S" { "compare":"0", "branch":"cbnz w2," } +%def op_if_nez(): +% zcmp(compare="0", branch="cbnz w2,") diff --git a/runtime/interpreter/mterp/arm64/op_iget.S b/runtime/interpreter/mterp/arm64/op_iget.S index 48b9cad44b..d09edc0a17 100644 --- a/runtime/interpreter/mterp/arm64/op_iget.S +++ b/runtime/interpreter/mterp/arm64/op_iget.S @@ -1,2 +1,2 @@ -%default { "is_object":"0", "helper":"MterpIGetU32"} -%include "arm64/field.S" { } +%def op_iget(is_object="0", helper="MterpIGetU32"): +% field(helper=helper) diff --git a/runtime/interpreter/mterp/arm64/op_iget_boolean.S b/runtime/interpreter/mterp/arm64/op_iget_boolean.S index 9a83b2a596..cb8edeec77 100644 --- a/runtime/interpreter/mterp/arm64/op_iget_boolean.S +++ b/runtime/interpreter/mterp/arm64/op_iget_boolean.S @@ -1 +1,2 @@ -%include "arm64/op_iget.S" { "helper":"MterpIGetU8" } +%def op_iget_boolean(): +% op_iget(helper="MterpIGetU8") diff --git a/runtime/interpreter/mterp/arm64/op_iget_boolean_quick.S b/runtime/interpreter/mterp/arm64/op_iget_boolean_quick.S index 2ceccb9ef0..7ac9fce535 100644 --- a/runtime/interpreter/mterp/arm64/op_iget_boolean_quick.S +++ b/runtime/interpreter/mterp/arm64/op_iget_boolean_quick.S @@ -1 +1,2 @@ -%include "arm64/op_iget_quick.S" { "load":"ldrb" } +%def op_iget_boolean_quick(): +% op_iget_quick(load="ldrb") diff --git a/runtime/interpreter/mterp/arm64/op_iget_byte.S b/runtime/interpreter/mterp/arm64/op_iget_byte.S index f73e634621..2b87fb16b5 100644 --- a/runtime/interpreter/mterp/arm64/op_iget_byte.S +++ b/runtime/interpreter/mterp/arm64/op_iget_byte.S @@ -1 +1,2 @@ -%include "arm64/op_iget.S" { "helper":"MterpIGetI8" } +%def op_iget_byte(): +% op_iget(helper="MterpIGetI8") diff --git a/runtime/interpreter/mterp/arm64/op_iget_byte_quick.S b/runtime/interpreter/mterp/arm64/op_iget_byte_quick.S index 6e97b72183..bbccaffe94 100644 --- a/runtime/interpreter/mterp/arm64/op_iget_byte_quick.S +++ b/runtime/interpreter/mterp/arm64/op_iget_byte_quick.S @@ -1 +1,2 @@ -%include "arm64/op_iget_quick.S" { "load":"ldrsb" } +%def op_iget_byte_quick(): +% op_iget_quick(load="ldrsb") diff --git a/runtime/interpreter/mterp/arm64/op_iget_char.S b/runtime/interpreter/mterp/arm64/op_iget_char.S index a5efd9e3ed..001bd03e2b 100644 --- a/runtime/interpreter/mterp/arm64/op_iget_char.S +++ b/runtime/interpreter/mterp/arm64/op_iget_char.S @@ -1 +1,2 @@ -%include "arm64/op_iget.S" { "helper":"MterpIGetU16" } +%def op_iget_char(): +% op_iget(helper="MterpIGetU16") diff --git a/runtime/interpreter/mterp/arm64/op_iget_char_quick.S b/runtime/interpreter/mterp/arm64/op_iget_char_quick.S index 325dd1cf9e..71a9276a81 100644 --- a/runtime/interpreter/mterp/arm64/op_iget_char_quick.S +++ b/runtime/interpreter/mterp/arm64/op_iget_char_quick.S @@ -1 +1,2 @@ -%include "arm64/op_iget_quick.S" { "load":"ldrh" } +%def op_iget_char_quick(): +% op_iget_quick(load="ldrh") diff --git a/runtime/interpreter/mterp/arm64/op_iget_object.S b/runtime/interpreter/mterp/arm64/op_iget_object.S index 40ddadd971..4e5f769547 100644 --- a/runtime/interpreter/mterp/arm64/op_iget_object.S +++ b/runtime/interpreter/mterp/arm64/op_iget_object.S @@ -1 +1,2 @@ -%include "arm64/op_iget.S" { "is_object":"1", "helper":"MterpIGetObj" } +%def op_iget_object(): +% op_iget(is_object="1", helper="MterpIGetObj") diff --git a/runtime/interpreter/mterp/arm64/op_iget_object_quick.S b/runtime/interpreter/mterp/arm64/op_iget_object_quick.S index e9a797dfe1..f55b08f909 100644 --- a/runtime/interpreter/mterp/arm64/op_iget_object_quick.S +++ b/runtime/interpreter/mterp/arm64/op_iget_object_quick.S @@ -1,3 +1,4 @@ +%def op_iget_object_quick(): /* For: iget-object-quick */ /* op vA, vB, offset//CCCC */ lsr w2, wINST, #12 // w2<- B diff --git a/runtime/interpreter/mterp/arm64/op_iget_quick.S b/runtime/interpreter/mterp/arm64/op_iget_quick.S index 699b2c4229..641bfab7df 100644 --- a/runtime/interpreter/mterp/arm64/op_iget_quick.S +++ b/runtime/interpreter/mterp/arm64/op_iget_quick.S @@ -1,4 +1,4 @@ -%default { "load":"ldr", "extend":"" } +%def op_iget_quick(load="ldr", extend=""): /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ /* op vA, vB, offset//CCCC */ lsr w2, wINST, #12 // w2<- B diff --git a/runtime/interpreter/mterp/arm64/op_iget_short.S b/runtime/interpreter/mterp/arm64/op_iget_short.S index bb81c1708e..a62c4d998f 100644 --- a/runtime/interpreter/mterp/arm64/op_iget_short.S +++ b/runtime/interpreter/mterp/arm64/op_iget_short.S @@ -1 +1,2 @@ -%include "arm64/op_iget.S" { "helper":"MterpIGetI16" } +%def op_iget_short(): +% op_iget(helper="MterpIGetI16") diff --git a/runtime/interpreter/mterp/arm64/op_iget_short_quick.S b/runtime/interpreter/mterp/arm64/op_iget_short_quick.S index 83670701c1..5dbdc4fa22 100644 --- a/runtime/interpreter/mterp/arm64/op_iget_short_quick.S +++ b/runtime/interpreter/mterp/arm64/op_iget_short_quick.S @@ -1 +1,2 @@ -%include "arm64/op_iget_quick.S" { "load":"ldrsh" } +%def op_iget_short_quick(): +% op_iget_quick(load="ldrsh") diff --git a/runtime/interpreter/mterp/arm64/op_iget_wide.S b/runtime/interpreter/mterp/arm64/op_iget_wide.S index 70061d6577..9643cc3403 100644 --- a/runtime/interpreter/mterp/arm64/op_iget_wide.S +++ b/runtime/interpreter/mterp/arm64/op_iget_wide.S @@ -1 +1,2 @@ -%include "arm64/op_iget.S" { "helper":"MterpIGetU64" } +%def op_iget_wide(): +% op_iget(helper="MterpIGetU64") diff --git a/runtime/interpreter/mterp/arm64/op_iget_wide_quick.S b/runtime/interpreter/mterp/arm64/op_iget_wide_quick.S index e9388e477d..9f7a61b4b2 100644 --- a/runtime/interpreter/mterp/arm64/op_iget_wide_quick.S +++ b/runtime/interpreter/mterp/arm64/op_iget_wide_quick.S @@ -1,3 +1,4 @@ +%def op_iget_wide_quick(): /* iget-wide-quick vA, vB, offset//CCCC */ lsr w2, wINST, #12 // w2<- B FETCH w4, 1 // w4<- field byte offset diff --git a/runtime/interpreter/mterp/arm64/op_instance_of.S b/runtime/interpreter/mterp/arm64/op_instance_of.S index a56705a68b..9c337d12fe 100644 --- a/runtime/interpreter/mterp/arm64/op_instance_of.S +++ b/runtime/interpreter/mterp/arm64/op_instance_of.S @@ -1,3 +1,4 @@ +%def op_instance_of(): /* * Check to see if an object reference is an instance of a class. * diff --git a/runtime/interpreter/mterp/arm64/op_int_to_byte.S b/runtime/interpreter/mterp/arm64/op_int_to_byte.S index 43f814820a..8174978f48 100644 --- a/runtime/interpreter/mterp/arm64/op_int_to_byte.S +++ b/runtime/interpreter/mterp/arm64/op_int_to_byte.S @@ -1 +1,2 @@ -%include "arm64/unop.S" {"instr":"sxtb w0, w0"} +%def op_int_to_byte(): +% unop(instr="sxtb w0, w0") diff --git a/runtime/interpreter/mterp/arm64/op_int_to_char.S b/runtime/interpreter/mterp/arm64/op_int_to_char.S index f092170681..bbf32394b7 100644 --- a/runtime/interpreter/mterp/arm64/op_int_to_char.S +++ b/runtime/interpreter/mterp/arm64/op_int_to_char.S @@ -1 +1,2 @@ -%include "arm64/unop.S" {"instr":"uxth w0, w0"} +%def op_int_to_char(): +% unop(instr="uxth w0, w0") diff --git a/runtime/interpreter/mterp/arm64/op_int_to_double.S b/runtime/interpreter/mterp/arm64/op_int_to_double.S index 3dee75a141..f2b9dc0c9f 100644 --- a/runtime/interpreter/mterp/arm64/op_int_to_double.S +++ b/runtime/interpreter/mterp/arm64/op_int_to_double.S @@ -1 +1,2 @@ -%include "arm64/funopWider.S" {"instr":"scvtf d0, w0", "srcreg":"w0", "tgtreg":"d0"} +%def op_int_to_double(): +% funopWider(instr="scvtf d0, w0", srcreg="w0", tgtreg="d0") diff --git a/runtime/interpreter/mterp/arm64/op_int_to_float.S b/runtime/interpreter/mterp/arm64/op_int_to_float.S index 3ebbdc7cb9..ffe873de81 100644 --- a/runtime/interpreter/mterp/arm64/op_int_to_float.S +++ b/runtime/interpreter/mterp/arm64/op_int_to_float.S @@ -1 +1,2 @@ -%include "arm64/funopNarrow.S" {"instr":"scvtf s0, w0", "srcreg":"w0", "tgtreg":"s0"} +%def op_int_to_float(): +% funopNarrow(instr="scvtf s0, w0", srcreg="w0", tgtreg="s0") diff --git a/runtime/interpreter/mterp/arm64/op_int_to_long.S b/runtime/interpreter/mterp/arm64/op_int_to_long.S index 45e31124ff..d7e5b463e6 100644 --- a/runtime/interpreter/mterp/arm64/op_int_to_long.S +++ b/runtime/interpreter/mterp/arm64/op_int_to_long.S @@ -1,3 +1,4 @@ +%def op_int_to_long(): /* int-to-long vA, vB */ lsr w3, wINST, #12 // w3<- B ubfx w4, wINST, #8, #4 // w4<- A diff --git a/runtime/interpreter/mterp/arm64/op_int_to_short.S b/runtime/interpreter/mterp/arm64/op_int_to_short.S index 87fb804668..0c51c76dc5 100644 --- a/runtime/interpreter/mterp/arm64/op_int_to_short.S +++ b/runtime/interpreter/mterp/arm64/op_int_to_short.S @@ -1 +1,2 @@ -%include "arm64/unop.S" {"instr":"sxth w0, w0"} +%def op_int_to_short(): +% unop(instr="sxth w0, w0") diff --git a/runtime/interpreter/mterp/arm64/op_invoke_custom.S b/runtime/interpreter/mterp/arm64/op_invoke_custom.S index 3686584950..4bba9ee524 100644 --- a/runtime/interpreter/mterp/arm64/op_invoke_custom.S +++ b/runtime/interpreter/mterp/arm64/op_invoke_custom.S @@ -1 +1,2 @@ -%include "arm64/invoke.S" { "helper":"MterpInvokeCustom" } +%def op_invoke_custom(): +% invoke(helper="MterpInvokeCustom") diff --git a/runtime/interpreter/mterp/arm64/op_invoke_custom_range.S b/runtime/interpreter/mterp/arm64/op_invoke_custom_range.S index 06de86a6a0..57e61af1fa 100644 --- a/runtime/interpreter/mterp/arm64/op_invoke_custom_range.S +++ b/runtime/interpreter/mterp/arm64/op_invoke_custom_range.S @@ -1 +1,2 @@ -%include "arm64/invoke.S" { "helper":"MterpInvokeCustomRange" } +%def op_invoke_custom_range(): +% invoke(helper="MterpInvokeCustomRange") diff --git a/runtime/interpreter/mterp/arm64/op_invoke_direct.S b/runtime/interpreter/mterp/arm64/op_invoke_direct.S index c117232d9c..d3139cf39b 100644 --- a/runtime/interpreter/mterp/arm64/op_invoke_direct.S +++ b/runtime/interpreter/mterp/arm64/op_invoke_direct.S @@ -1 +1,2 @@ -%include "arm64/invoke.S" { "helper":"MterpInvokeDirect" } +%def op_invoke_direct(): +% invoke(helper="MterpInvokeDirect") diff --git a/runtime/interpreter/mterp/arm64/op_invoke_direct_range.S b/runtime/interpreter/mterp/arm64/op_invoke_direct_range.S index efc54c71d9..b4a161f48b 100644 --- a/runtime/interpreter/mterp/arm64/op_invoke_direct_range.S +++ b/runtime/interpreter/mterp/arm64/op_invoke_direct_range.S @@ -1 +1,2 @@ -%include "arm64/invoke.S" { "helper":"MterpInvokeDirectRange" } +%def op_invoke_direct_range(): +% invoke(helper="MterpInvokeDirectRange") diff --git a/runtime/interpreter/mterp/arm64/op_invoke_interface.S b/runtime/interpreter/mterp/arm64/op_invoke_interface.S index 12dfa592d5..b064126253 100644 --- a/runtime/interpreter/mterp/arm64/op_invoke_interface.S +++ b/runtime/interpreter/mterp/arm64/op_invoke_interface.S @@ -1,4 +1,5 @@ -%include "arm64/invoke.S" { "helper":"MterpInvokeInterface" } +%def op_invoke_interface(): +% invoke(helper="MterpInvokeInterface") /* * Handle an interface method call. * diff --git a/runtime/interpreter/mterp/arm64/op_invoke_interface_range.S b/runtime/interpreter/mterp/arm64/op_invoke_interface_range.S index 61caaf47e3..2989115377 100644 --- a/runtime/interpreter/mterp/arm64/op_invoke_interface_range.S +++ b/runtime/interpreter/mterp/arm64/op_invoke_interface_range.S @@ -1 +1,2 @@ -%include "arm64/invoke.S" { "helper":"MterpInvokeInterfaceRange" } +%def op_invoke_interface_range(): +% invoke(helper="MterpInvokeInterfaceRange") diff --git a/runtime/interpreter/mterp/arm64/op_invoke_polymorphic.S b/runtime/interpreter/mterp/arm64/op_invoke_polymorphic.S index aace98f1a2..ce61f5aa0e 100644 --- a/runtime/interpreter/mterp/arm64/op_invoke_polymorphic.S +++ b/runtime/interpreter/mterp/arm64/op_invoke_polymorphic.S @@ -1 +1,2 @@ -%include "arm64/invoke_polymorphic.S" { "helper":"MterpInvokePolymorphic" } +%def op_invoke_polymorphic(): +% invoke_polymorphic(helper="MterpInvokePolymorphic") diff --git a/runtime/interpreter/mterp/arm64/op_invoke_polymorphic_range.S b/runtime/interpreter/mterp/arm64/op_invoke_polymorphic_range.S index 30c8c09cce..16731bdb40 100644 --- a/runtime/interpreter/mterp/arm64/op_invoke_polymorphic_range.S +++ b/runtime/interpreter/mterp/arm64/op_invoke_polymorphic_range.S @@ -1 +1,2 @@ -%include "arm64/invoke_polymorphic.S" { "helper":"MterpInvokePolymorphicRange" } +%def op_invoke_polymorphic_range(): +% invoke_polymorphic(helper="MterpInvokePolymorphicRange") diff --git a/runtime/interpreter/mterp/arm64/op_invoke_static.S b/runtime/interpreter/mterp/arm64/op_invoke_static.S index 634eda2736..3e38d36a27 100644 --- a/runtime/interpreter/mterp/arm64/op_invoke_static.S +++ b/runtime/interpreter/mterp/arm64/op_invoke_static.S @@ -1,2 +1,3 @@ -%include "arm64/invoke.S" { "helper":"MterpInvokeStatic" } +%def op_invoke_static(): +% invoke(helper="MterpInvokeStatic") diff --git a/runtime/interpreter/mterp/arm64/op_invoke_static_range.S b/runtime/interpreter/mterp/arm64/op_invoke_static_range.S index 32cdcddaa4..e0a546c92b 100644 --- a/runtime/interpreter/mterp/arm64/op_invoke_static_range.S +++ b/runtime/interpreter/mterp/arm64/op_invoke_static_range.S @@ -1 +1,2 @@ -%include "arm64/invoke.S" { "helper":"MterpInvokeStaticRange" } +%def op_invoke_static_range(): +% invoke(helper="MterpInvokeStaticRange") diff --git a/runtime/interpreter/mterp/arm64/op_invoke_super.S b/runtime/interpreter/mterp/arm64/op_invoke_super.S index def2c552fd..3c34c9942e 100644 --- a/runtime/interpreter/mterp/arm64/op_invoke_super.S +++ b/runtime/interpreter/mterp/arm64/op_invoke_super.S @@ -1,4 +1,5 @@ -%include "arm64/invoke.S" { "helper":"MterpInvokeSuper" } +%def op_invoke_super(): +% invoke(helper="MterpInvokeSuper") /* * Handle a "super" method call. * diff --git a/runtime/interpreter/mterp/arm64/op_invoke_super_range.S b/runtime/interpreter/mterp/arm64/op_invoke_super_range.S index 27fb8591a4..caeafaa13c 100644 --- a/runtime/interpreter/mterp/arm64/op_invoke_super_range.S +++ b/runtime/interpreter/mterp/arm64/op_invoke_super_range.S @@ -1 +1,2 @@ -%include "arm64/invoke.S" { "helper":"MterpInvokeSuperRange" } +%def op_invoke_super_range(): +% invoke(helper="MterpInvokeSuperRange") diff --git a/runtime/interpreter/mterp/arm64/op_invoke_virtual.S b/runtime/interpreter/mterp/arm64/op_invoke_virtual.S index 66d050217d..249177b813 100644 --- a/runtime/interpreter/mterp/arm64/op_invoke_virtual.S +++ b/runtime/interpreter/mterp/arm64/op_invoke_virtual.S @@ -1,4 +1,5 @@ -%include "arm64/invoke.S" { "helper":"MterpInvokeVirtual" } +%def op_invoke_virtual(): +% invoke(helper="MterpInvokeVirtual") /* * Handle a virtual method call. * diff --git a/runtime/interpreter/mterp/arm64/op_invoke_virtual_quick.S b/runtime/interpreter/mterp/arm64/op_invoke_virtual_quick.S index 4300c34646..ea72c171ec 100644 --- a/runtime/interpreter/mterp/arm64/op_invoke_virtual_quick.S +++ b/runtime/interpreter/mterp/arm64/op_invoke_virtual_quick.S @@ -1 +1,2 @@ -%include "arm64/invoke.S" { "helper":"MterpInvokeVirtualQuick" } +%def op_invoke_virtual_quick(): +% invoke(helper="MterpInvokeVirtualQuick") diff --git a/runtime/interpreter/mterp/arm64/op_invoke_virtual_range.S b/runtime/interpreter/mterp/arm64/op_invoke_virtual_range.S index b43955c6d8..baa0779593 100644 --- a/runtime/interpreter/mterp/arm64/op_invoke_virtual_range.S +++ b/runtime/interpreter/mterp/arm64/op_invoke_virtual_range.S @@ -1 +1,2 @@ -%include "arm64/invoke.S" { "helper":"MterpInvokeVirtualRange" } +%def op_invoke_virtual_range(): +% invoke(helper="MterpInvokeVirtualRange") diff --git a/runtime/interpreter/mterp/arm64/op_invoke_virtual_range_quick.S b/runtime/interpreter/mterp/arm64/op_invoke_virtual_range_quick.S index 90c7b65747..1d961a0781 100644 --- a/runtime/interpreter/mterp/arm64/op_invoke_virtual_range_quick.S +++ b/runtime/interpreter/mterp/arm64/op_invoke_virtual_range_quick.S @@ -1 +1,2 @@ -%include "arm64/invoke.S" { "helper":"MterpInvokeVirtualQuickRange" } +%def op_invoke_virtual_range_quick(): +% invoke(helper="MterpInvokeVirtualQuickRange") diff --git a/runtime/interpreter/mterp/arm64/op_iput.S b/runtime/interpreter/mterp/arm64/op_iput.S index 2bc3db9050..e5351baf55 100644 --- a/runtime/interpreter/mterp/arm64/op_iput.S +++ b/runtime/interpreter/mterp/arm64/op_iput.S @@ -1,2 +1,2 @@ -%default { "is_object":"0", "helper":"MterpIPutU32" } -%include "arm64/field.S" { } +%def op_iput(is_object="0", helper="MterpIPutU32"): +% field(helper=helper) diff --git a/runtime/interpreter/mterp/arm64/op_iput_boolean.S b/runtime/interpreter/mterp/arm64/op_iput_boolean.S index 12a278ccba..9eb849877b 100644 --- a/runtime/interpreter/mterp/arm64/op_iput_boolean.S +++ b/runtime/interpreter/mterp/arm64/op_iput_boolean.S @@ -1 +1,2 @@ -%include "arm64/op_iput.S" { "helper":"MterpIPutU8" } +%def op_iput_boolean(): +% op_iput(helper="MterpIPutU8") diff --git a/runtime/interpreter/mterp/arm64/op_iput_boolean_quick.S b/runtime/interpreter/mterp/arm64/op_iput_boolean_quick.S index 25c61d7c2e..fd077a7792 100644 --- a/runtime/interpreter/mterp/arm64/op_iput_boolean_quick.S +++ b/runtime/interpreter/mterp/arm64/op_iput_boolean_quick.S @@ -1 +1,2 @@ -%include "arm64/op_iput_quick.S" { "store":"strb" } +%def op_iput_boolean_quick(): +% op_iput_quick(store="strb") diff --git a/runtime/interpreter/mterp/arm64/op_iput_byte.S b/runtime/interpreter/mterp/arm64/op_iput_byte.S index 82b99e9765..4b74f9fb0e 100644 --- a/runtime/interpreter/mterp/arm64/op_iput_byte.S +++ b/runtime/interpreter/mterp/arm64/op_iput_byte.S @@ -1 +1,2 @@ -%include "arm64/op_iput.S" { "helper":"MterpIPutI8" } +%def op_iput_byte(): +% op_iput(helper="MterpIPutI8") diff --git a/runtime/interpreter/mterp/arm64/op_iput_byte_quick.S b/runtime/interpreter/mterp/arm64/op_iput_byte_quick.S index 25c61d7c2e..30238cf354 100644 --- a/runtime/interpreter/mterp/arm64/op_iput_byte_quick.S +++ b/runtime/interpreter/mterp/arm64/op_iput_byte_quick.S @@ -1 +1,2 @@ -%include "arm64/op_iput_quick.S" { "store":"strb" } +%def op_iput_byte_quick(): +% op_iput_quick(store="strb") diff --git a/runtime/interpreter/mterp/arm64/op_iput_char.S b/runtime/interpreter/mterp/arm64/op_iput_char.S index 427d92d9c0..64a249fc12 100644 --- a/runtime/interpreter/mterp/arm64/op_iput_char.S +++ b/runtime/interpreter/mterp/arm64/op_iput_char.S @@ -1 +1,2 @@ -%include "arm64/op_iput.S" { "helper":"MterpIPutU16" } +%def op_iput_char(): +% op_iput(helper="MterpIPutU16") diff --git a/runtime/interpreter/mterp/arm64/op_iput_char_quick.S b/runtime/interpreter/mterp/arm64/op_iput_char_quick.S index c6ef46ab87..0deff56503 100644 --- a/runtime/interpreter/mterp/arm64/op_iput_char_quick.S +++ b/runtime/interpreter/mterp/arm64/op_iput_char_quick.S @@ -1 +1,2 @@ -%include "arm64/op_iput_quick.S" { "store":"strh" } +%def op_iput_char_quick(): +% op_iput_quick(store="strh") diff --git a/runtime/interpreter/mterp/arm64/op_iput_object.S b/runtime/interpreter/mterp/arm64/op_iput_object.S index e9bb93f0a5..131edd5dbd 100644 --- a/runtime/interpreter/mterp/arm64/op_iput_object.S +++ b/runtime/interpreter/mterp/arm64/op_iput_object.S @@ -1 +1,2 @@ -%include "arm64/op_iput.S" { "is_object":"1", "helper":"MterpIPutObj" } +%def op_iput_object(): +% op_iput(is_object="1", helper="MterpIPutObj") diff --git a/runtime/interpreter/mterp/arm64/op_iput_object_quick.S b/runtime/interpreter/mterp/arm64/op_iput_object_quick.S index 6fbf2b1da3..58c1026658 100644 --- a/runtime/interpreter/mterp/arm64/op_iput_object_quick.S +++ b/runtime/interpreter/mterp/arm64/op_iput_object_quick.S @@ -1,3 +1,4 @@ +%def op_iput_object_quick(): EXPORT_PC add x0, xFP, #OFF_FP_SHADOWFRAME mov x1, xPC diff --git a/runtime/interpreter/mterp/arm64/op_iput_quick.S b/runtime/interpreter/mterp/arm64/op_iput_quick.S index e95da76283..1d9910826f 100644 --- a/runtime/interpreter/mterp/arm64/op_iput_quick.S +++ b/runtime/interpreter/mterp/arm64/op_iput_quick.S @@ -1,4 +1,4 @@ -%default { "store":"str" } +%def op_iput_quick(store="str"): /* For: iput-quick, iput-object-quick */ /* op vA, vB, offset//CCCC */ lsr w2, wINST, #12 // w2<- B diff --git a/runtime/interpreter/mterp/arm64/op_iput_short.S b/runtime/interpreter/mterp/arm64/op_iput_short.S index 67f1ace8bf..e631a3b259 100644 --- a/runtime/interpreter/mterp/arm64/op_iput_short.S +++ b/runtime/interpreter/mterp/arm64/op_iput_short.S @@ -1 +1,2 @@ -%include "arm64/op_iput.S" { "helper":"MterpIPutI16" } +%def op_iput_short(): +% op_iput(helper="MterpIPutI16") diff --git a/runtime/interpreter/mterp/arm64/op_iput_short_quick.S b/runtime/interpreter/mterp/arm64/op_iput_short_quick.S index c6ef46ab87..6a1b65194e 100644 --- a/runtime/interpreter/mterp/arm64/op_iput_short_quick.S +++ b/runtime/interpreter/mterp/arm64/op_iput_short_quick.S @@ -1 +1,2 @@ -%include "arm64/op_iput_quick.S" { "store":"strh" } +%def op_iput_short_quick(): +% op_iput_quick(store="strh") diff --git a/runtime/interpreter/mterp/arm64/op_iput_wide.S b/runtime/interpreter/mterp/arm64/op_iput_wide.S index e1fafad5a7..2f34fd39f9 100644 --- a/runtime/interpreter/mterp/arm64/op_iput_wide.S +++ b/runtime/interpreter/mterp/arm64/op_iput_wide.S @@ -1 +1,2 @@ -%include "arm64/op_iput.S" { "helper":"MterpIPutU64" } +%def op_iput_wide(): +% op_iput(helper="MterpIPutU64") diff --git a/runtime/interpreter/mterp/arm64/op_iput_wide_quick.S b/runtime/interpreter/mterp/arm64/op_iput_wide_quick.S index 28e831a5f8..a78918819b 100644 --- a/runtime/interpreter/mterp/arm64/op_iput_wide_quick.S +++ b/runtime/interpreter/mterp/arm64/op_iput_wide_quick.S @@ -1,3 +1,4 @@ +%def op_iput_wide_quick(): /* iput-wide-quick vA, vB, offset//CCCC */ lsr w2, wINST, #12 // w2<- B FETCH w3, 1 // w3<- field byte offset diff --git a/runtime/interpreter/mterp/arm64/op_long_to_double.S b/runtime/interpreter/mterp/arm64/op_long_to_double.S index a3f59c2048..b1b7b4e694 100644 --- a/runtime/interpreter/mterp/arm64/op_long_to_double.S +++ b/runtime/interpreter/mterp/arm64/op_long_to_double.S @@ -1 +1,2 @@ -%include "arm64/funopWide.S" {"instr":"scvtf d0, x0", "srcreg":"x0", "tgtreg":"d0"} +%def op_long_to_double(): +% funopWide(instr="scvtf d0, x0", srcreg="x0", tgtreg="d0") diff --git a/runtime/interpreter/mterp/arm64/op_long_to_float.S b/runtime/interpreter/mterp/arm64/op_long_to_float.S index e9c9145cee..424dea0964 100644 --- a/runtime/interpreter/mterp/arm64/op_long_to_float.S +++ b/runtime/interpreter/mterp/arm64/op_long_to_float.S @@ -1 +1,2 @@ -%include "arm64/funopNarrower.S" {"instr":"scvtf s0, x0", "srcreg":"x0", "tgtreg":"s0"} +%def op_long_to_float(): +% funopNarrower(instr="scvtf s0, x0", srcreg="x0", tgtreg="s0") diff --git a/runtime/interpreter/mterp/arm64/op_long_to_int.S b/runtime/interpreter/mterp/arm64/op_long_to_int.S index 73f58d8967..eacb8f59ec 100644 --- a/runtime/interpreter/mterp/arm64/op_long_to_int.S +++ b/runtime/interpreter/mterp/arm64/op_long_to_int.S @@ -1,2 +1,3 @@ +%def op_long_to_int(): /* we ignore the high word, making this equivalent to a 32-bit reg move */ -%include "arm64/op_move.S" +% op_move() diff --git a/runtime/interpreter/mterp/arm64/op_monitor_enter.S b/runtime/interpreter/mterp/arm64/op_monitor_enter.S index 6fbd9ae725..9d167a25da 100644 --- a/runtime/interpreter/mterp/arm64/op_monitor_enter.S +++ b/runtime/interpreter/mterp/arm64/op_monitor_enter.S @@ -1,3 +1,4 @@ +%def op_monitor_enter(): /* * Synchronize on an object. */ diff --git a/runtime/interpreter/mterp/arm64/op_monitor_exit.S b/runtime/interpreter/mterp/arm64/op_monitor_exit.S index 26e2d8d7b1..985769f15b 100644 --- a/runtime/interpreter/mterp/arm64/op_monitor_exit.S +++ b/runtime/interpreter/mterp/arm64/op_monitor_exit.S @@ -1,3 +1,4 @@ +%def op_monitor_exit(): /* * Unlock an object. * diff --git a/runtime/interpreter/mterp/arm64/op_move.S b/runtime/interpreter/mterp/arm64/op_move.S index 195b7eb62d..d3324f1158 100644 --- a/runtime/interpreter/mterp/arm64/op_move.S +++ b/runtime/interpreter/mterp/arm64/op_move.S @@ -1,4 +1,4 @@ -%default { "is_object":"0" } +%def op_move(is_object="0"): /* for move, move-object, long-to-int */ /* op vA, vB */ lsr w1, wINST, #12 // x1<- B from 15:12 diff --git a/runtime/interpreter/mterp/arm64/op_move_16.S b/runtime/interpreter/mterp/arm64/op_move_16.S index 5146e3d6e7..0dc862d5df 100644 --- a/runtime/interpreter/mterp/arm64/op_move_16.S +++ b/runtime/interpreter/mterp/arm64/op_move_16.S @@ -1,4 +1,4 @@ -%default { "is_object":"0" } +%def op_move_16(is_object="0"): /* for: move/16, move-object/16 */ /* op vAAAA, vBBBB */ FETCH w1, 2 // w1<- BBBB diff --git a/runtime/interpreter/mterp/arm64/op_move_exception.S b/runtime/interpreter/mterp/arm64/op_move_exception.S index b29298fd14..2ae5ca898c 100644 --- a/runtime/interpreter/mterp/arm64/op_move_exception.S +++ b/runtime/interpreter/mterp/arm64/op_move_exception.S @@ -1,3 +1,4 @@ +%def op_move_exception(): /* move-exception vAA */ lsr w2, wINST, #8 // w2<- AA ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] diff --git a/runtime/interpreter/mterp/arm64/op_move_from16.S b/runtime/interpreter/mterp/arm64/op_move_from16.S index 78f344db6b..5c7344504d 100644 --- a/runtime/interpreter/mterp/arm64/op_move_from16.S +++ b/runtime/interpreter/mterp/arm64/op_move_from16.S @@ -1,4 +1,4 @@ -%default { "is_object":"0" } +%def op_move_from16(is_object="0"): /* for: move/from16, move-object/from16 */ /* op vAA, vBBBB */ FETCH w1, 1 // r1<- BBBB diff --git a/runtime/interpreter/mterp/arm64/op_move_object.S b/runtime/interpreter/mterp/arm64/op_move_object.S index a5adc59e81..dbb4d59710 100644 --- a/runtime/interpreter/mterp/arm64/op_move_object.S +++ b/runtime/interpreter/mterp/arm64/op_move_object.S @@ -1 +1,2 @@ -%include "arm64/op_move.S" {"is_object":"1"} +%def op_move_object(): +% op_move(is_object="1") diff --git a/runtime/interpreter/mterp/arm64/op_move_object_16.S b/runtime/interpreter/mterp/arm64/op_move_object_16.S index ef86c4508b..40120379d5 100644 --- a/runtime/interpreter/mterp/arm64/op_move_object_16.S +++ b/runtime/interpreter/mterp/arm64/op_move_object_16.S @@ -1 +1,2 @@ -%include "arm64/op_move_16.S" {"is_object":"1"} +%def op_move_object_16(): +% op_move_16(is_object="1") diff --git a/runtime/interpreter/mterp/arm64/op_move_object_from16.S b/runtime/interpreter/mterp/arm64/op_move_object_from16.S index 0c73b3b045..c82698e81e 100644 --- a/runtime/interpreter/mterp/arm64/op_move_object_from16.S +++ b/runtime/interpreter/mterp/arm64/op_move_object_from16.S @@ -1 +1,2 @@ -%include "arm64/op_move_from16.S" {"is_object":"1"} +%def op_move_object_from16(): +% op_move_from16(is_object="1") diff --git a/runtime/interpreter/mterp/arm64/op_move_result.S b/runtime/interpreter/mterp/arm64/op_move_result.S index 06fe96269b..9c048f05a1 100644 --- a/runtime/interpreter/mterp/arm64/op_move_result.S +++ b/runtime/interpreter/mterp/arm64/op_move_result.S @@ -1,4 +1,4 @@ -%default { "is_object":"0" } +%def op_move_result(is_object="0"): /* for: move-result, move-result-object */ /* op vAA */ lsr w2, wINST, #8 // r2<- AA diff --git a/runtime/interpreter/mterp/arm64/op_move_result_object.S b/runtime/interpreter/mterp/arm64/op_move_result_object.S index da2bbee665..87aea2646a 100644 --- a/runtime/interpreter/mterp/arm64/op_move_result_object.S +++ b/runtime/interpreter/mterp/arm64/op_move_result_object.S @@ -1 +1,2 @@ -%include "arm64/op_move_result.S" {"is_object":"1"} +%def op_move_result_object(): +% op_move_result(is_object="1") diff --git a/runtime/interpreter/mterp/arm64/op_move_result_wide.S b/runtime/interpreter/mterp/arm64/op_move_result_wide.S index f90a33f01f..96347ea2d0 100644 --- a/runtime/interpreter/mterp/arm64/op_move_result_wide.S +++ b/runtime/interpreter/mterp/arm64/op_move_result_wide.S @@ -1,3 +1,4 @@ +%def op_move_result_wide(): /* for: move-result-wide */ /* op vAA */ lsr w2, wINST, #8 // r2<- AA diff --git a/runtime/interpreter/mterp/arm64/op_move_wide.S b/runtime/interpreter/mterp/arm64/op_move_wide.S index 538f079736..4576987b90 100644 --- a/runtime/interpreter/mterp/arm64/op_move_wide.S +++ b/runtime/interpreter/mterp/arm64/op_move_wide.S @@ -1,3 +1,4 @@ +%def op_move_wide(): /* move-wide vA, vB */ /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ lsr w3, wINST, #12 // w3<- B diff --git a/runtime/interpreter/mterp/arm64/op_move_wide_16.S b/runtime/interpreter/mterp/arm64/op_move_wide_16.S index c79cdc5007..09f7a61c55 100644 --- a/runtime/interpreter/mterp/arm64/op_move_wide_16.S +++ b/runtime/interpreter/mterp/arm64/op_move_wide_16.S @@ -1,3 +1,4 @@ +%def op_move_wide_16(): /* move-wide/16 vAAAA, vBBBB */ /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ FETCH w3, 2 // w3<- BBBB diff --git a/runtime/interpreter/mterp/arm64/op_move_wide_from16.S b/runtime/interpreter/mterp/arm64/op_move_wide_from16.S index 70dbe99039..6afc20a8c0 100644 --- a/runtime/interpreter/mterp/arm64/op_move_wide_from16.S +++ b/runtime/interpreter/mterp/arm64/op_move_wide_from16.S @@ -1,3 +1,4 @@ +%def op_move_wide_from16(): /* move-wide/from16 vAA, vBBBB */ /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ FETCH w3, 1 // w3<- BBBB diff --git a/runtime/interpreter/mterp/arm64/op_mul_double.S b/runtime/interpreter/mterp/arm64/op_mul_double.S index 8d35b81b12..30ca309997 100644 --- a/runtime/interpreter/mterp/arm64/op_mul_double.S +++ b/runtime/interpreter/mterp/arm64/op_mul_double.S @@ -1 +1,2 @@ -%include "arm64/binopWide.S" {"instr":"fmul d0, d1, d2", "result":"d0", "r1":"d1", "r2":"d2"} +%def op_mul_double(): +% binopWide(instr="fmul d0, d1, d2", result="d0", r1="d1", r2="d2") diff --git a/runtime/interpreter/mterp/arm64/op_mul_double_2addr.S b/runtime/interpreter/mterp/arm64/op_mul_double_2addr.S index 526cb3bccc..dedecb5be8 100644 --- a/runtime/interpreter/mterp/arm64/op_mul_double_2addr.S +++ b/runtime/interpreter/mterp/arm64/op_mul_double_2addr.S @@ -1 +1,2 @@ -%include "arm64/binopWide2addr.S" {"instr":"fmul d0, d0, d1", "r0":"d0", "r1":"d1"} +%def op_mul_double_2addr(): +% binopWide2addr(instr="fmul d0, d0, d1", r0="d0", r1="d1") diff --git a/runtime/interpreter/mterp/arm64/op_mul_float.S b/runtime/interpreter/mterp/arm64/op_mul_float.S index eea7733dbf..3bbbe7305b 100644 --- a/runtime/interpreter/mterp/arm64/op_mul_float.S +++ b/runtime/interpreter/mterp/arm64/op_mul_float.S @@ -1 +1,2 @@ -%include "arm64/fbinop.S" {"instr":"fmul s0, s0, s1"} +%def op_mul_float(): +% fbinop(instr="fmul s0, s0, s1") diff --git a/runtime/interpreter/mterp/arm64/op_mul_float_2addr.S b/runtime/interpreter/mterp/arm64/op_mul_float_2addr.S index c1f23765aa..035a1fb662 100644 --- a/runtime/interpreter/mterp/arm64/op_mul_float_2addr.S +++ b/runtime/interpreter/mterp/arm64/op_mul_float_2addr.S @@ -1 +1,2 @@ -%include "arm64/fbinop2addr.S" {"instr":"fmul s2, s0, s1"} +%def op_mul_float_2addr(): +% fbinop2addr(instr="fmul s2, s0, s1") diff --git a/runtime/interpreter/mterp/arm64/op_mul_int.S b/runtime/interpreter/mterp/arm64/op_mul_int.S index d14cae12e4..267623d1f5 100644 --- a/runtime/interpreter/mterp/arm64/op_mul_int.S +++ b/runtime/interpreter/mterp/arm64/op_mul_int.S @@ -1,2 +1,3 @@ +%def op_mul_int(): /* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */ -%include "arm64/binop.S" {"instr":"mul w0, w1, w0"} +% binop(instr="mul w0, w1, w0") diff --git a/runtime/interpreter/mterp/arm64/op_mul_int_2addr.S b/runtime/interpreter/mterp/arm64/op_mul_int_2addr.S index f079118172..c0f533a0c1 100644 --- a/runtime/interpreter/mterp/arm64/op_mul_int_2addr.S +++ b/runtime/interpreter/mterp/arm64/op_mul_int_2addr.S @@ -1,2 +1,3 @@ +%def op_mul_int_2addr(): /* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */ -%include "arm64/binop2addr.S" {"instr":"mul w0, w1, w0"} +% binop2addr(instr="mul w0, w1, w0") diff --git a/runtime/interpreter/mterp/arm64/op_mul_int_lit16.S b/runtime/interpreter/mterp/arm64/op_mul_int_lit16.S index a378559541..d309c86299 100644 --- a/runtime/interpreter/mterp/arm64/op_mul_int_lit16.S +++ b/runtime/interpreter/mterp/arm64/op_mul_int_lit16.S @@ -1,2 +1,3 @@ +%def op_mul_int_lit16(): /* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */ -%include "arm64/binopLit16.S" {"instr":"mul w0, w1, w0"} +% binopLit16(instr="mul w0, w1, w0") diff --git a/runtime/interpreter/mterp/arm64/op_mul_int_lit8.S b/runtime/interpreter/mterp/arm64/op_mul_int_lit8.S index b3d40141ae..b3368416d1 100644 --- a/runtime/interpreter/mterp/arm64/op_mul_int_lit8.S +++ b/runtime/interpreter/mterp/arm64/op_mul_int_lit8.S @@ -1,2 +1,3 @@ +%def op_mul_int_lit8(): /* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */ -%include "arm64/binopLit8.S" {"instr":"mul w0, w1, w0"} +% binopLit8(instr="mul w0, w1, w0") diff --git a/runtime/interpreter/mterp/arm64/op_mul_long.S b/runtime/interpreter/mterp/arm64/op_mul_long.S index bc0dcbd14b..5056c0e4c1 100644 --- a/runtime/interpreter/mterp/arm64/op_mul_long.S +++ b/runtime/interpreter/mterp/arm64/op_mul_long.S @@ -1 +1,2 @@ -%include "arm64/binopWide.S" {"instr":"mul x0, x1, x2"} +%def op_mul_long(): +% binopWide(instr="mul x0, x1, x2") diff --git a/runtime/interpreter/mterp/arm64/op_mul_long_2addr.S b/runtime/interpreter/mterp/arm64/op_mul_long_2addr.S index fa1cdf8a72..e69d40aadf 100644 --- a/runtime/interpreter/mterp/arm64/op_mul_long_2addr.S +++ b/runtime/interpreter/mterp/arm64/op_mul_long_2addr.S @@ -1 +1,2 @@ -%include "arm64/binopWide2addr.S" {"instr":"mul x0, x0, x1"} +%def op_mul_long_2addr(): +% binopWide2addr(instr="mul x0, x0, x1") diff --git a/runtime/interpreter/mterp/arm64/op_neg_double.S b/runtime/interpreter/mterp/arm64/op_neg_double.S index d77859d570..a56eff5493 100644 --- a/runtime/interpreter/mterp/arm64/op_neg_double.S +++ b/runtime/interpreter/mterp/arm64/op_neg_double.S @@ -1 +1,2 @@ -%include "arm64/unopWide.S" {"instr":"eor x0, x0, #0x8000000000000000"} +%def op_neg_double(): +% unopWide(instr="eor x0, x0, #0x8000000000000000") diff --git a/runtime/interpreter/mterp/arm64/op_neg_float.S b/runtime/interpreter/mterp/arm64/op_neg_float.S index 6652aec0ff..1366168def 100644 --- a/runtime/interpreter/mterp/arm64/op_neg_float.S +++ b/runtime/interpreter/mterp/arm64/op_neg_float.S @@ -1 +1,2 @@ -%include "arm64/unop.S" {"instr":"eor w0, w0, #0x80000000"} +%def op_neg_float(): +% unop(instr="eor w0, w0, #0x80000000") diff --git a/runtime/interpreter/mterp/arm64/op_neg_int.S b/runtime/interpreter/mterp/arm64/op_neg_int.S index 59c14a9087..be56dd2aca 100644 --- a/runtime/interpreter/mterp/arm64/op_neg_int.S +++ b/runtime/interpreter/mterp/arm64/op_neg_int.S @@ -1 +1,2 @@ -%include "arm64/unop.S" {"instr":"sub w0, wzr, w0"} +%def op_neg_int(): +% unop(instr="sub w0, wzr, w0") diff --git a/runtime/interpreter/mterp/arm64/op_neg_long.S b/runtime/interpreter/mterp/arm64/op_neg_long.S index 0c71ea7de6..eb2882c9a7 100644 --- a/runtime/interpreter/mterp/arm64/op_neg_long.S +++ b/runtime/interpreter/mterp/arm64/op_neg_long.S @@ -1 +1,2 @@ -%include "arm64/unopWide.S" {"instr":"sub x0, xzr, x0"} +%def op_neg_long(): +% unopWide(instr="sub x0, xzr, x0") diff --git a/runtime/interpreter/mterp/arm64/op_new_array.S b/runtime/interpreter/mterp/arm64/op_new_array.S index 886120a94e..34729a7aeb 100644 --- a/runtime/interpreter/mterp/arm64/op_new_array.S +++ b/runtime/interpreter/mterp/arm64/op_new_array.S @@ -1,3 +1,4 @@ +%def op_new_array(): /* * Allocate an array of objects, specified with the array class * and a count. diff --git a/runtime/interpreter/mterp/arm64/op_new_instance.S b/runtime/interpreter/mterp/arm64/op_new_instance.S index c171ac58f6..beb1f6e2e0 100644 --- a/runtime/interpreter/mterp/arm64/op_new_instance.S +++ b/runtime/interpreter/mterp/arm64/op_new_instance.S @@ -1,3 +1,4 @@ +%def op_new_instance(): /* * Create a new instance of a class. */ diff --git a/runtime/interpreter/mterp/arm64/op_nop.S b/runtime/interpreter/mterp/arm64/op_nop.S index 80c2d452f8..9702c5cd48 100644 --- a/runtime/interpreter/mterp/arm64/op_nop.S +++ b/runtime/interpreter/mterp/arm64/op_nop.S @@ -1,3 +1,4 @@ +%def op_nop(): FETCH_ADVANCE_INST 1 // advance to next instr, load rINST GET_INST_OPCODE ip // ip<- opcode from rINST GOTO_OPCODE ip // execute it diff --git a/runtime/interpreter/mterp/arm64/op_not_int.S b/runtime/interpreter/mterp/arm64/op_not_int.S index 55d77502aa..d2fc205318 100644 --- a/runtime/interpreter/mterp/arm64/op_not_int.S +++ b/runtime/interpreter/mterp/arm64/op_not_int.S @@ -1 +1,2 @@ -%include "arm64/unop.S" {"instr":"mvn w0, w0"} +%def op_not_int(): +% unop(instr="mvn w0, w0") diff --git a/runtime/interpreter/mterp/arm64/op_not_long.S b/runtime/interpreter/mterp/arm64/op_not_long.S index e5ebdd6e65..014a60dc40 100644 --- a/runtime/interpreter/mterp/arm64/op_not_long.S +++ b/runtime/interpreter/mterp/arm64/op_not_long.S @@ -1 +1,2 @@ -%include "arm64/unopWide.S" {"instr":"mvn x0, x0"} +%def op_not_long(): +% unopWide(instr="mvn x0, x0") diff --git a/runtime/interpreter/mterp/arm64/op_or_int.S b/runtime/interpreter/mterp/arm64/op_or_int.S index 648c1e6850..8041c6d805 100644 --- a/runtime/interpreter/mterp/arm64/op_or_int.S +++ b/runtime/interpreter/mterp/arm64/op_or_int.S @@ -1 +1,2 @@ -%include "arm64/binop.S" {"instr":"orr w0, w0, w1"} +%def op_or_int(): +% binop(instr="orr w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_or_int_2addr.S b/runtime/interpreter/mterp/arm64/op_or_int_2addr.S index abdf599fe9..918c5233ee 100644 --- a/runtime/interpreter/mterp/arm64/op_or_int_2addr.S +++ b/runtime/interpreter/mterp/arm64/op_or_int_2addr.S @@ -1 +1,2 @@ -%include "arm64/binop2addr.S" {"instr":"orr w0, w0, w1"} +%def op_or_int_2addr(): +% binop2addr(instr="orr w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_or_int_lit16.S b/runtime/interpreter/mterp/arm64/op_or_int_lit16.S index db7f4ffb0a..dda068bbbf 100644 --- a/runtime/interpreter/mterp/arm64/op_or_int_lit16.S +++ b/runtime/interpreter/mterp/arm64/op_or_int_lit16.S @@ -1 +1,2 @@ -%include "arm64/binopLit16.S" {"instr":"orr w0, w0, w1"} +%def op_or_int_lit16(): +% binopLit16(instr="orr w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_or_int_lit8.S b/runtime/interpreter/mterp/arm64/op_or_int_lit8.S index 7cb26b7796..0fe6122e79 100644 --- a/runtime/interpreter/mterp/arm64/op_or_int_lit8.S +++ b/runtime/interpreter/mterp/arm64/op_or_int_lit8.S @@ -1 +1,2 @@ -%include "arm64/binopLit8.S" {"extract":"", "instr":"orr w0, w0, w3, asr #8"} +%def op_or_int_lit8(): +% binopLit8(extract="", instr="orr w0, w0, w3, asr #8") diff --git a/runtime/interpreter/mterp/arm64/op_or_long.S b/runtime/interpreter/mterp/arm64/op_or_long.S index dd137ce85b..f434d3fae9 100644 --- a/runtime/interpreter/mterp/arm64/op_or_long.S +++ b/runtime/interpreter/mterp/arm64/op_or_long.S @@ -1 +1,2 @@ -%include "arm64/binopWide.S" {"instr":"orr x0, x1, x2"} +%def op_or_long(): +% binopWide(instr="orr x0, x1, x2") diff --git a/runtime/interpreter/mterp/arm64/op_or_long_2addr.S b/runtime/interpreter/mterp/arm64/op_or_long_2addr.S index f785230e1c..4186ce9ef9 100644 --- a/runtime/interpreter/mterp/arm64/op_or_long_2addr.S +++ b/runtime/interpreter/mterp/arm64/op_or_long_2addr.S @@ -1 +1,2 @@ -%include "arm64/binopWide2addr.S" {"instr":"orr x0, x0, x1"} +%def op_or_long_2addr(): +% binopWide2addr(instr="orr x0, x0, x1") diff --git a/runtime/interpreter/mterp/arm64/op_packed_switch.S b/runtime/interpreter/mterp/arm64/op_packed_switch.S index 408e03069b..9e4eb9bd37 100644 --- a/runtime/interpreter/mterp/arm64/op_packed_switch.S +++ b/runtime/interpreter/mterp/arm64/op_packed_switch.S @@ -1,4 +1,4 @@ -%default { "func":"MterpDoPackedSwitch" } +%def op_packed_switch(func="MterpDoPackedSwitch"): /* * Handle a packed-switch or sparse-switch instruction. In both cases * we decode it and hand it off to a helper function. diff --git a/runtime/interpreter/mterp/arm64/op_rem_double.S b/runtime/interpreter/mterp/arm64/op_rem_double.S index c631ddbfe5..3d43467e63 100644 --- a/runtime/interpreter/mterp/arm64/op_rem_double.S +++ b/runtime/interpreter/mterp/arm64/op_rem_double.S @@ -1,3 +1,4 @@ +%def op_rem_double(): /* rem vAA, vBB, vCC */ FETCH w0, 1 // w0<- CCBB lsr w2, w0, #8 // w2<- CC diff --git a/runtime/interpreter/mterp/arm64/op_rem_double_2addr.S b/runtime/interpreter/mterp/arm64/op_rem_double_2addr.S index 9868f4123a..179886d46b 100644 --- a/runtime/interpreter/mterp/arm64/op_rem_double_2addr.S +++ b/runtime/interpreter/mterp/arm64/op_rem_double_2addr.S @@ -1,3 +1,4 @@ +%def op_rem_double_2addr(): /* rem vA, vB */ lsr w1, wINST, #12 // w1<- B ubfx w2, wINST, #8, #4 // w2<- A diff --git a/runtime/interpreter/mterp/arm64/op_rem_float.S b/runtime/interpreter/mterp/arm64/op_rem_float.S index 73f7060cf5..29241e5722 100644 --- a/runtime/interpreter/mterp/arm64/op_rem_float.S +++ b/runtime/interpreter/mterp/arm64/op_rem_float.S @@ -1,2 +1,3 @@ +%def op_rem_float(): /* EABI doesn't define a float remainder function, but libm does */ -%include "arm64/fbinop.S" {"instr":"bl fmodf"} +% fbinop(instr="bl fmodf") diff --git a/runtime/interpreter/mterp/arm64/op_rem_float_2addr.S b/runtime/interpreter/mterp/arm64/op_rem_float_2addr.S index 95f81c5a23..49bf8ea320 100644 --- a/runtime/interpreter/mterp/arm64/op_rem_float_2addr.S +++ b/runtime/interpreter/mterp/arm64/op_rem_float_2addr.S @@ -1,3 +1,4 @@ +%def op_rem_float_2addr(): /* rem vA, vB */ lsr w3, wINST, #12 // w3<- B ubfx w9, wINST, #8, #4 // w9<- A diff --git a/runtime/interpreter/mterp/arm64/op_rem_int.S b/runtime/interpreter/mterp/arm64/op_rem_int.S index dd9dfda088..6f2f999f3f 100644 --- a/runtime/interpreter/mterp/arm64/op_rem_int.S +++ b/runtime/interpreter/mterp/arm64/op_rem_int.S @@ -1 +1,2 @@ -%include "arm64/binop.S" {"preinstr":"sdiv w2, w0, w1", "instr":"msub w0, w2, w1, w0", "chkzero":"1"} +%def op_rem_int(): +% binop(preinstr="sdiv w2, w0, w1", instr="msub w0, w2, w1, w0", chkzero="1") diff --git a/runtime/interpreter/mterp/arm64/op_rem_int_2addr.S b/runtime/interpreter/mterp/arm64/op_rem_int_2addr.S index 57fc4971b9..dc46b2feb4 100644 --- a/runtime/interpreter/mterp/arm64/op_rem_int_2addr.S +++ b/runtime/interpreter/mterp/arm64/op_rem_int_2addr.S @@ -1 +1,2 @@ -%include "arm64/binop2addr.S" {"preinstr":"sdiv w2, w0, w1", "instr":"msub w0, w2, w1, w0", "chkzero":"1"} +%def op_rem_int_2addr(): +% binop2addr(preinstr="sdiv w2, w0, w1", instr="msub w0, w2, w1, w0", chkzero="1") diff --git a/runtime/interpreter/mterp/arm64/op_rem_int_lit16.S b/runtime/interpreter/mterp/arm64/op_rem_int_lit16.S index b51a739d2e..75be3343ba 100644 --- a/runtime/interpreter/mterp/arm64/op_rem_int_lit16.S +++ b/runtime/interpreter/mterp/arm64/op_rem_int_lit16.S @@ -1 +1,2 @@ -%include "arm64/binopLit16.S" {"preinstr":"sdiv w3, w0, w1", "instr":"msub w0, w3, w1, w0", "chkzero":"1"} +%def op_rem_int_lit16(): +% binopLit16(preinstr="sdiv w3, w0, w1", instr="msub w0, w3, w1, w0", chkzero="1") diff --git a/runtime/interpreter/mterp/arm64/op_rem_int_lit8.S b/runtime/interpreter/mterp/arm64/op_rem_int_lit8.S index 03ea32420b..c5fef4be01 100644 --- a/runtime/interpreter/mterp/arm64/op_rem_int_lit8.S +++ b/runtime/interpreter/mterp/arm64/op_rem_int_lit8.S @@ -1 +1,2 @@ -%include "arm64/binopLit8.S" {"preinstr":"sdiv w3, w0, w1", "instr":"msub w0, w3, w1, w0", "chkzero":"1"} +%def op_rem_int_lit8(): +% binopLit8(preinstr="sdiv w3, w0, w1", instr="msub w0, w3, w1, w0", chkzero="1") diff --git a/runtime/interpreter/mterp/arm64/op_rem_long.S b/runtime/interpreter/mterp/arm64/op_rem_long.S index f133f86a6c..31dd6bec52 100644 --- a/runtime/interpreter/mterp/arm64/op_rem_long.S +++ b/runtime/interpreter/mterp/arm64/op_rem_long.S @@ -1 +1,2 @@ -%include "arm64/binopWide.S" {"preinstr":"sdiv x3, x1, x2","instr":"msub x0, x3, x2, x1", "chkzero":"1"} +%def op_rem_long(): +% binopWide(preinstr="sdiv x3, x1, x2", instr="msub x0, x3, x2, x1", chkzero="1") diff --git a/runtime/interpreter/mterp/arm64/op_rem_long_2addr.S b/runtime/interpreter/mterp/arm64/op_rem_long_2addr.S index b45e2a95c1..b30ef674b3 100644 --- a/runtime/interpreter/mterp/arm64/op_rem_long_2addr.S +++ b/runtime/interpreter/mterp/arm64/op_rem_long_2addr.S @@ -1 +1,2 @@ -%include "arm64/binopWide2addr.S" {"preinstr":"sdiv x3, x0, x1", "instr":"msub x0, x3, x1, x0", "chkzero":"1"} +%def op_rem_long_2addr(): +% binopWide2addr(preinstr="sdiv x3, x0, x1", instr="msub x0, x3, x1, x0", chkzero="1") diff --git a/runtime/interpreter/mterp/arm64/op_return.S b/runtime/interpreter/mterp/arm64/op_return.S index 9f125c7fef..eedae64d4e 100644 --- a/runtime/interpreter/mterp/arm64/op_return.S +++ b/runtime/interpreter/mterp/arm64/op_return.S @@ -1,3 +1,4 @@ +%def op_return(): /* * Return a 32-bit value. * diff --git a/runtime/interpreter/mterp/arm64/op_return_object.S b/runtime/interpreter/mterp/arm64/op_return_object.S index b6cb532b53..2eeec0b948 100644 --- a/runtime/interpreter/mterp/arm64/op_return_object.S +++ b/runtime/interpreter/mterp/arm64/op_return_object.S @@ -1 +1,2 @@ -%include "arm64/op_return.S" +%def op_return_object(): +% op_return() diff --git a/runtime/interpreter/mterp/arm64/op_return_void.S b/runtime/interpreter/mterp/arm64/op_return_void.S index b2530062e8..6962bb21d0 100644 --- a/runtime/interpreter/mterp/arm64/op_return_void.S +++ b/runtime/interpreter/mterp/arm64/op_return_void.S @@ -1,3 +1,4 @@ +%def op_return_void(): .extern MterpThreadFenceForConstructor bl MterpThreadFenceForConstructor ldr w7, [xSELF, #THREAD_FLAGS_OFFSET] diff --git a/runtime/interpreter/mterp/arm64/op_return_void_no_barrier.S b/runtime/interpreter/mterp/arm64/op_return_void_no_barrier.S index c817169070..8d872d1faa 100644 --- a/runtime/interpreter/mterp/arm64/op_return_void_no_barrier.S +++ b/runtime/interpreter/mterp/arm64/op_return_void_no_barrier.S @@ -1,3 +1,4 @@ +%def op_return_void_no_barrier(): ldr w7, [xSELF, #THREAD_FLAGS_OFFSET] mov x0, xSELF ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST diff --git a/runtime/interpreter/mterp/arm64/op_return_wide.S b/runtime/interpreter/mterp/arm64/op_return_wide.S index c47661cd54..5d31c6a5ab 100644 --- a/runtime/interpreter/mterp/arm64/op_return_wide.S +++ b/runtime/interpreter/mterp/arm64/op_return_wide.S @@ -1,3 +1,4 @@ +%def op_return_wide(): /* * Return a 64-bit value. */ diff --git a/runtime/interpreter/mterp/arm64/op_rsub_int.S b/runtime/interpreter/mterp/arm64/op_rsub_int.S index 3bf45fe654..dc2342d018 100644 --- a/runtime/interpreter/mterp/arm64/op_rsub_int.S +++ b/runtime/interpreter/mterp/arm64/op_rsub_int.S @@ -1,2 +1,3 @@ +%def op_rsub_int(): /* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ -%include "arm64/binopLit16.S" {"instr":"sub w0, w1, w0"} +% binopLit16(instr="sub w0, w1, w0") diff --git a/runtime/interpreter/mterp/arm64/op_rsub_int_lit8.S b/runtime/interpreter/mterp/arm64/op_rsub_int_lit8.S index 7a3572b364..51a48fb9bd 100644 --- a/runtime/interpreter/mterp/arm64/op_rsub_int_lit8.S +++ b/runtime/interpreter/mterp/arm64/op_rsub_int_lit8.S @@ -1 +1,2 @@ -%include "arm64/binopLit8.S" {"instr":"sub w0, w1, w0"} +%def op_rsub_int_lit8(): +% binopLit8(instr="sub w0, w1, w0") diff --git a/runtime/interpreter/mterp/arm64/op_sget.S b/runtime/interpreter/mterp/arm64/op_sget.S index 78e95b2e7c..8a6a66ab60 100644 --- a/runtime/interpreter/mterp/arm64/op_sget.S +++ b/runtime/interpreter/mterp/arm64/op_sget.S @@ -1,2 +1,2 @@ -%default { "is_object":"0", "helper":"MterpSGetU32" } -%include "arm64/field.S" { } +%def op_sget(is_object="0", helper="MterpSGetU32"): +% field(helper=helper) diff --git a/runtime/interpreter/mterp/arm64/op_sget_boolean.S b/runtime/interpreter/mterp/arm64/op_sget_boolean.S index 0cf9f09681..d9c12c9b28 100644 --- a/runtime/interpreter/mterp/arm64/op_sget_boolean.S +++ b/runtime/interpreter/mterp/arm64/op_sget_boolean.S @@ -1 +1,2 @@ -%include "arm64/op_sget.S" {"helper":"MterpSGetU8"} +%def op_sget_boolean(): +% op_sget(helper="MterpSGetU8") diff --git a/runtime/interpreter/mterp/arm64/op_sget_byte.S b/runtime/interpreter/mterp/arm64/op_sget_byte.S index 7c88a81faa..37c6879cd4 100644 --- a/runtime/interpreter/mterp/arm64/op_sget_byte.S +++ b/runtime/interpreter/mterp/arm64/op_sget_byte.S @@ -1 +1,2 @@ -%include "arm64/op_sget.S" {"helper":"MterpSGetI8"} +%def op_sget_byte(): +% op_sget(helper="MterpSGetI8") diff --git a/runtime/interpreter/mterp/arm64/op_sget_char.S b/runtime/interpreter/mterp/arm64/op_sget_char.S index 883e944ce5..003bcd1683 100644 --- a/runtime/interpreter/mterp/arm64/op_sget_char.S +++ b/runtime/interpreter/mterp/arm64/op_sget_char.S @@ -1 +1,2 @@ -%include "arm64/op_sget.S" {"helper":"MterpSGetU16"} +%def op_sget_char(): +% op_sget(helper="MterpSGetU16") diff --git a/runtime/interpreter/mterp/arm64/op_sget_object.S b/runtime/interpreter/mterp/arm64/op_sget_object.S index 69d6adb549..7cf3597f44 100644 --- a/runtime/interpreter/mterp/arm64/op_sget_object.S +++ b/runtime/interpreter/mterp/arm64/op_sget_object.S @@ -1 +1,2 @@ -%include "arm64/op_sget.S" {"is_object":"1", "helper":"MterpSGetObj"} +%def op_sget_object(): +% op_sget(is_object="1", helper="MterpSGetObj") diff --git a/runtime/interpreter/mterp/arm64/op_sget_short.S b/runtime/interpreter/mterp/arm64/op_sget_short.S index 6cb918433d..afacb578d9 100644 --- a/runtime/interpreter/mterp/arm64/op_sget_short.S +++ b/runtime/interpreter/mterp/arm64/op_sget_short.S @@ -1 +1,2 @@ -%include "arm64/op_sget.S" {"helper":"MterpSGetI16"} +%def op_sget_short(): +% op_sget(helper="MterpSGetI16") diff --git a/runtime/interpreter/mterp/arm64/op_sget_wide.S b/runtime/interpreter/mterp/arm64/op_sget_wide.S index f5d182e96d..fff2be6945 100644 --- a/runtime/interpreter/mterp/arm64/op_sget_wide.S +++ b/runtime/interpreter/mterp/arm64/op_sget_wide.S @@ -1 +1,2 @@ -%include "arm64/op_sget.S" {"helper":"MterpSGetU64"} +%def op_sget_wide(): +% op_sget(helper="MterpSGetU64") diff --git a/runtime/interpreter/mterp/arm64/op_shl_int.S b/runtime/interpreter/mterp/arm64/op_shl_int.S index 3062a3fad8..673d4a0a74 100644 --- a/runtime/interpreter/mterp/arm64/op_shl_int.S +++ b/runtime/interpreter/mterp/arm64/op_shl_int.S @@ -1 +1,2 @@ -%include "arm64/binop.S" {"instr":"lsl w0, w0, w1"} +%def op_shl_int(): +% binop(instr="lsl w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_shl_int_2addr.S b/runtime/interpreter/mterp/arm64/op_shl_int_2addr.S index 9a7e09f016..f4c2f8ceca 100644 --- a/runtime/interpreter/mterp/arm64/op_shl_int_2addr.S +++ b/runtime/interpreter/mterp/arm64/op_shl_int_2addr.S @@ -1 +1,2 @@ -%include "arm64/binop2addr.S" {"instr":"lsl w0, w0, w1"} +%def op_shl_int_2addr(): +% binop2addr(instr="lsl w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_shl_int_lit8.S b/runtime/interpreter/mterp/arm64/op_shl_int_lit8.S index 9c19b55550..38f3f8edcb 100644 --- a/runtime/interpreter/mterp/arm64/op_shl_int_lit8.S +++ b/runtime/interpreter/mterp/arm64/op_shl_int_lit8.S @@ -1 +1,2 @@ -%include "arm64/binopLit8.S" {"extract":"ubfx w1, w3, #8, #5", "instr":"lsl w0, w0, w1"} +%def op_shl_int_lit8(): +% binopLit8(extract="ubfx w1, w3, #8, #5", instr="lsl w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_shl_long.S b/runtime/interpreter/mterp/arm64/op_shl_long.S index bbf9600953..c56b59fb3c 100644 --- a/runtime/interpreter/mterp/arm64/op_shl_long.S +++ b/runtime/interpreter/mterp/arm64/op_shl_long.S @@ -1 +1,2 @@ -%include "arm64/shiftWide.S" {"opcode":"lsl"} +%def op_shl_long(): +% shiftWide(opcode="lsl") diff --git a/runtime/interpreter/mterp/arm64/op_shl_long_2addr.S b/runtime/interpreter/mterp/arm64/op_shl_long_2addr.S index a5c4013bf7..ed10db2fd8 100644 --- a/runtime/interpreter/mterp/arm64/op_shl_long_2addr.S +++ b/runtime/interpreter/mterp/arm64/op_shl_long_2addr.S @@ -1 +1,2 @@ -%include "arm64/shiftWide2addr.S" {"opcode":"lsl"} +%def op_shl_long_2addr(): +% shiftWide2addr(opcode="lsl") diff --git a/runtime/interpreter/mterp/arm64/op_shr_int.S b/runtime/interpreter/mterp/arm64/op_shr_int.S index 493b7407f7..9dab83d553 100644 --- a/runtime/interpreter/mterp/arm64/op_shr_int.S +++ b/runtime/interpreter/mterp/arm64/op_shr_int.S @@ -1 +1,2 @@ -%include "arm64/binop.S" {"instr":"asr w0, w0, w1"} +%def op_shr_int(): +% binop(instr="asr w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_shr_int_2addr.S b/runtime/interpreter/mterp/arm64/op_shr_int_2addr.S index 6efe8ee010..8bdcc11b70 100644 --- a/runtime/interpreter/mterp/arm64/op_shr_int_2addr.S +++ b/runtime/interpreter/mterp/arm64/op_shr_int_2addr.S @@ -1 +1,2 @@ -%include "arm64/binop2addr.S" {"instr":"asr w0, w0, w1"} +%def op_shr_int_2addr(): +% binop2addr(instr="asr w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_shr_int_lit8.S b/runtime/interpreter/mterp/arm64/op_shr_int_lit8.S index c7b61df13d..7f58bca4e9 100644 --- a/runtime/interpreter/mterp/arm64/op_shr_int_lit8.S +++ b/runtime/interpreter/mterp/arm64/op_shr_int_lit8.S @@ -1 +1,2 @@ -%include "arm64/binopLit8.S" {"extract":"ubfx w1, w3, #8, #5", "instr":"asr w0, w0, w1"} +%def op_shr_int_lit8(): +% binopLit8(extract="ubfx w1, w3, #8, #5", instr="asr w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_shr_long.S b/runtime/interpreter/mterp/arm64/op_shr_long.S index 4d332359ab..fcaf0ec45d 100644 --- a/runtime/interpreter/mterp/arm64/op_shr_long.S +++ b/runtime/interpreter/mterp/arm64/op_shr_long.S @@ -1 +1,2 @@ -%include "arm64/shiftWide.S" {"opcode":"asr"} +%def op_shr_long(): +% shiftWide(opcode="asr") diff --git a/runtime/interpreter/mterp/arm64/op_shr_long_2addr.S b/runtime/interpreter/mterp/arm64/op_shr_long_2addr.S index 0a4a386c95..359778ab53 100644 --- a/runtime/interpreter/mterp/arm64/op_shr_long_2addr.S +++ b/runtime/interpreter/mterp/arm64/op_shr_long_2addr.S @@ -1 +1,2 @@ -%include "arm64/shiftWide2addr.S" {"opcode":"asr"} +%def op_shr_long_2addr(): +% shiftWide2addr(opcode="asr") diff --git a/runtime/interpreter/mterp/arm64/op_sparse_switch.S b/runtime/interpreter/mterp/arm64/op_sparse_switch.S index 5a8d7489bc..b74d7da816 100644 --- a/runtime/interpreter/mterp/arm64/op_sparse_switch.S +++ b/runtime/interpreter/mterp/arm64/op_sparse_switch.S @@ -1 +1,2 @@ -%include "arm64/op_packed_switch.S" { "func":"MterpDoSparseSwitch" } +%def op_sparse_switch(): +% op_packed_switch(func="MterpDoSparseSwitch") diff --git a/runtime/interpreter/mterp/arm64/op_sput.S b/runtime/interpreter/mterp/arm64/op_sput.S index d229d0d899..cbd6ee96d3 100644 --- a/runtime/interpreter/mterp/arm64/op_sput.S +++ b/runtime/interpreter/mterp/arm64/op_sput.S @@ -1,2 +1,2 @@ -%default { "is_object":"0", "helper":"MterpSPutU32"} -%include "arm64/field.S" { } +%def op_sput(is_object="0", helper="MterpSPutU32"): +% field(helper=helper) diff --git a/runtime/interpreter/mterp/arm64/op_sput_boolean.S b/runtime/interpreter/mterp/arm64/op_sput_boolean.S index 3d0c7c0262..36fba8448b 100644 --- a/runtime/interpreter/mterp/arm64/op_sput_boolean.S +++ b/runtime/interpreter/mterp/arm64/op_sput_boolean.S @@ -1 +1,2 @@ -%include "arm64/op_sput.S" {"helper":"MterpSPutU8"} +%def op_sput_boolean(): +% op_sput(helper="MterpSPutU8") diff --git a/runtime/interpreter/mterp/arm64/op_sput_byte.S b/runtime/interpreter/mterp/arm64/op_sput_byte.S index 489cf92149..84ad4a0ff8 100644 --- a/runtime/interpreter/mterp/arm64/op_sput_byte.S +++ b/runtime/interpreter/mterp/arm64/op_sput_byte.S @@ -1 +1,2 @@ -%include "arm64/op_sput.S" {"helper":"MterpSPutI8"} +%def op_sput_byte(): +% op_sput(helper="MterpSPutI8") diff --git a/runtime/interpreter/mterp/arm64/op_sput_char.S b/runtime/interpreter/mterp/arm64/op_sput_char.S index f79d311c17..9b8eeba578 100644 --- a/runtime/interpreter/mterp/arm64/op_sput_char.S +++ b/runtime/interpreter/mterp/arm64/op_sput_char.S @@ -1 +1,2 @@ -%include "arm64/op_sput.S" {"helper":"MterpSPutU16"} +%def op_sput_char(): +% op_sput(helper="MterpSPutU16") diff --git a/runtime/interpreter/mterp/arm64/op_sput_object.S b/runtime/interpreter/mterp/arm64/op_sput_object.S index 536f1b16b8..081360c40f 100644 --- a/runtime/interpreter/mterp/arm64/op_sput_object.S +++ b/runtime/interpreter/mterp/arm64/op_sput_object.S @@ -1 +1,2 @@ -%include "arm64/op_sput.S" {"is_object":"1", "helper":"MterpSPutObj"} +%def op_sput_object(): +% op_sput(is_object="1", helper="MterpSPutObj") diff --git a/runtime/interpreter/mterp/arm64/op_sput_short.S b/runtime/interpreter/mterp/arm64/op_sput_short.S index 06482cd7a0..ee16513486 100644 --- a/runtime/interpreter/mterp/arm64/op_sput_short.S +++ b/runtime/interpreter/mterp/arm64/op_sput_short.S @@ -1 +1,2 @@ -%include "arm64/op_sput.S" {"helper":"MterpSPutI16"} +%def op_sput_short(): +% op_sput(helper="MterpSPutI16") diff --git a/runtime/interpreter/mterp/arm64/op_sput_wide.S b/runtime/interpreter/mterp/arm64/op_sput_wide.S index b4be6b2987..44c1a188ed 100644 --- a/runtime/interpreter/mterp/arm64/op_sput_wide.S +++ b/runtime/interpreter/mterp/arm64/op_sput_wide.S @@ -1 +1,2 @@ -%include "arm64/op_sput.S" {"helper":"MterpSPutU64"} +%def op_sput_wide(): +% op_sput(helper="MterpSPutU64") diff --git a/runtime/interpreter/mterp/arm64/op_sub_double.S b/runtime/interpreter/mterp/arm64/op_sub_double.S index e8e3401e17..cca75564da 100644 --- a/runtime/interpreter/mterp/arm64/op_sub_double.S +++ b/runtime/interpreter/mterp/arm64/op_sub_double.S @@ -1 +1,2 @@ -%include "arm64/binopWide.S" {"instr":"fsub d0, d1, d2", "result":"d0", "r1":"d1", "r2":"d2"} +%def op_sub_double(): +% binopWide(instr="fsub d0, d1, d2", result="d0", r1="d1", r2="d2") diff --git a/runtime/interpreter/mterp/arm64/op_sub_double_2addr.S b/runtime/interpreter/mterp/arm64/op_sub_double_2addr.S index ddab55e9fe..6d425fc29d 100644 --- a/runtime/interpreter/mterp/arm64/op_sub_double_2addr.S +++ b/runtime/interpreter/mterp/arm64/op_sub_double_2addr.S @@ -1 +1,2 @@ -%include "arm64/binopWide2addr.S" {"instr":"fsub d0, d0, d1", "r0":"d0", "r1":"d1"} +%def op_sub_double_2addr(): +% binopWide2addr(instr="fsub d0, d0, d1", r0="d0", r1="d1") diff --git a/runtime/interpreter/mterp/arm64/op_sub_float.S b/runtime/interpreter/mterp/arm64/op_sub_float.S index 227b15fdf3..e1c469b95c 100644 --- a/runtime/interpreter/mterp/arm64/op_sub_float.S +++ b/runtime/interpreter/mterp/arm64/op_sub_float.S @@ -1 +1,2 @@ -%include "arm64/fbinop.S" {"instr":"fsub s0, s0, s1"} +%def op_sub_float(): +% fbinop(instr="fsub s0, s0, s1") diff --git a/runtime/interpreter/mterp/arm64/op_sub_float_2addr.S b/runtime/interpreter/mterp/arm64/op_sub_float_2addr.S index 19ac8d5616..91b8346985 100644 --- a/runtime/interpreter/mterp/arm64/op_sub_float_2addr.S +++ b/runtime/interpreter/mterp/arm64/op_sub_float_2addr.S @@ -1 +1,2 @@ -%include "arm64/fbinop2addr.S" {"instr":"fsub s2, s0, s1"} +%def op_sub_float_2addr(): +% fbinop2addr(instr="fsub s2, s0, s1") diff --git a/runtime/interpreter/mterp/arm64/op_sub_int.S b/runtime/interpreter/mterp/arm64/op_sub_int.S index 0e7ce0e6e5..895146324b 100644 --- a/runtime/interpreter/mterp/arm64/op_sub_int.S +++ b/runtime/interpreter/mterp/arm64/op_sub_int.S @@ -1 +1,2 @@ -%include "arm64/binop.S" {"instr":"sub w0, w0, w1"} +%def op_sub_int(): +% binop(instr="sub w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_sub_int_2addr.S b/runtime/interpreter/mterp/arm64/op_sub_int_2addr.S index d2c1bd307a..a450ce499c 100644 --- a/runtime/interpreter/mterp/arm64/op_sub_int_2addr.S +++ b/runtime/interpreter/mterp/arm64/op_sub_int_2addr.S @@ -1 +1,2 @@ -%include "arm64/binop2addr.S" {"instr":"sub w0, w0, w1"} +%def op_sub_int_2addr(): +% binop2addr(instr="sub w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_sub_long.S b/runtime/interpreter/mterp/arm64/op_sub_long.S index 263c70d6e7..696e79a77f 100644 --- a/runtime/interpreter/mterp/arm64/op_sub_long.S +++ b/runtime/interpreter/mterp/arm64/op_sub_long.S @@ -1 +1,2 @@ -%include "arm64/binopWide.S" {"instr":"sub x0, x1, x2"} +%def op_sub_long(): +% binopWide(instr="sub x0, x1, x2") diff --git a/runtime/interpreter/mterp/arm64/op_sub_long_2addr.S b/runtime/interpreter/mterp/arm64/op_sub_long_2addr.S index 5be3772670..a622451669 100644 --- a/runtime/interpreter/mterp/arm64/op_sub_long_2addr.S +++ b/runtime/interpreter/mterp/arm64/op_sub_long_2addr.S @@ -1 +1,2 @@ -%include "arm64/binopWide2addr.S" {"instr":"sub x0, x0, x1"} +%def op_sub_long_2addr(): +% binopWide2addr(instr="sub x0, x0, x1") diff --git a/runtime/interpreter/mterp/arm64/op_throw.S b/runtime/interpreter/mterp/arm64/op_throw.S index 9a951af302..ed5a19effd 100644 --- a/runtime/interpreter/mterp/arm64/op_throw.S +++ b/runtime/interpreter/mterp/arm64/op_throw.S @@ -1,3 +1,4 @@ +%def op_throw(): /* * Throw an exception object in the current thread. */ diff --git a/runtime/interpreter/mterp/arm64/op_unused_3e.S b/runtime/interpreter/mterp/arm64/op_unused_3e.S index 204eceff7e..d889f1a5fb 100644 --- a/runtime/interpreter/mterp/arm64/op_unused_3e.S +++ b/runtime/interpreter/mterp/arm64/op_unused_3e.S @@ -1 +1,2 @@ -%include "arm64/unused.S" +%def op_unused_3e(): +% unused() diff --git a/runtime/interpreter/mterp/arm64/op_unused_3f.S b/runtime/interpreter/mterp/arm64/op_unused_3f.S index 204eceff7e..b3ebcfaeaa 100644 --- a/runtime/interpreter/mterp/arm64/op_unused_3f.S +++ b/runtime/interpreter/mterp/arm64/op_unused_3f.S @@ -1 +1,2 @@ -%include "arm64/unused.S" +%def op_unused_3f(): +% unused() diff --git a/runtime/interpreter/mterp/arm64/op_unused_40.S b/runtime/interpreter/mterp/arm64/op_unused_40.S index 204eceff7e..7920fb350f 100644 --- a/runtime/interpreter/mterp/arm64/op_unused_40.S +++ b/runtime/interpreter/mterp/arm64/op_unused_40.S @@ -1 +1,2 @@ -%include "arm64/unused.S" +%def op_unused_40(): +% unused() diff --git a/runtime/interpreter/mterp/arm64/op_unused_41.S b/runtime/interpreter/mterp/arm64/op_unused_41.S index 204eceff7e..5ed03b8506 100644 --- a/runtime/interpreter/mterp/arm64/op_unused_41.S +++ b/runtime/interpreter/mterp/arm64/op_unused_41.S @@ -1 +1,2 @@ -%include "arm64/unused.S" +%def op_unused_41(): +% unused() diff --git a/runtime/interpreter/mterp/arm64/op_unused_42.S b/runtime/interpreter/mterp/arm64/op_unused_42.S index 204eceff7e..ac32521add 100644 --- a/runtime/interpreter/mterp/arm64/op_unused_42.S +++ b/runtime/interpreter/mterp/arm64/op_unused_42.S @@ -1 +1,2 @@ -%include "arm64/unused.S" +%def op_unused_42(): +% unused() diff --git a/runtime/interpreter/mterp/arm64/op_unused_43.S b/runtime/interpreter/mterp/arm64/op_unused_43.S index 204eceff7e..33e2aa10f8 100644 --- a/runtime/interpreter/mterp/arm64/op_unused_43.S +++ b/runtime/interpreter/mterp/arm64/op_unused_43.S @@ -1 +1,2 @@ -%include "arm64/unused.S" +%def op_unused_43(): +% unused() diff --git a/runtime/interpreter/mterp/arm64/op_unused_73.S b/runtime/interpreter/mterp/arm64/op_unused_73.S index 204eceff7e..e3267a30a1 100644 --- a/runtime/interpreter/mterp/arm64/op_unused_73.S +++ b/runtime/interpreter/mterp/arm64/op_unused_73.S @@ -1 +1,2 @@ -%include "arm64/unused.S" +%def op_unused_73(): +% unused() diff --git a/runtime/interpreter/mterp/arm64/op_unused_79.S b/runtime/interpreter/mterp/arm64/op_unused_79.S index 204eceff7e..3c6dafc789 100644 --- a/runtime/interpreter/mterp/arm64/op_unused_79.S +++ b/runtime/interpreter/mterp/arm64/op_unused_79.S @@ -1 +1,2 @@ -%include "arm64/unused.S" +%def op_unused_79(): +% unused() diff --git a/runtime/interpreter/mterp/arm64/op_unused_7a.S b/runtime/interpreter/mterp/arm64/op_unused_7a.S index 204eceff7e..9c03cd5535 100644 --- a/runtime/interpreter/mterp/arm64/op_unused_7a.S +++ b/runtime/interpreter/mterp/arm64/op_unused_7a.S @@ -1 +1,2 @@ -%include "arm64/unused.S" +%def op_unused_7a(): +% unused() diff --git a/runtime/interpreter/mterp/arm64/op_unused_f3.S b/runtime/interpreter/mterp/arm64/op_unused_f3.S index 204eceff7e..ab10b78be2 100644 --- a/runtime/interpreter/mterp/arm64/op_unused_f3.S +++ b/runtime/interpreter/mterp/arm64/op_unused_f3.S @@ -1 +1,2 @@ -%include "arm64/unused.S" +%def op_unused_f3(): +% unused() diff --git a/runtime/interpreter/mterp/arm64/op_unused_f4.S b/runtime/interpreter/mterp/arm64/op_unused_f4.S index 204eceff7e..09229d6d99 100644 --- a/runtime/interpreter/mterp/arm64/op_unused_f4.S +++ b/runtime/interpreter/mterp/arm64/op_unused_f4.S @@ -1 +1,2 @@ -%include "arm64/unused.S" +%def op_unused_f4(): +% unused() diff --git a/runtime/interpreter/mterp/arm64/op_unused_f5.S b/runtime/interpreter/mterp/arm64/op_unused_f5.S index 204eceff7e..0d6149b5fd 100644 --- a/runtime/interpreter/mterp/arm64/op_unused_f5.S +++ b/runtime/interpreter/mterp/arm64/op_unused_f5.S @@ -1 +1,2 @@ -%include "arm64/unused.S" +%def op_unused_f5(): +% unused() diff --git a/runtime/interpreter/mterp/arm64/op_unused_f6.S b/runtime/interpreter/mterp/arm64/op_unused_f6.S index 204eceff7e..117b03de6d 100644 --- a/runtime/interpreter/mterp/arm64/op_unused_f6.S +++ b/runtime/interpreter/mterp/arm64/op_unused_f6.S @@ -1 +1,2 @@ -%include "arm64/unused.S" +%def op_unused_f6(): +% unused() diff --git a/runtime/interpreter/mterp/arm64/op_unused_f7.S b/runtime/interpreter/mterp/arm64/op_unused_f7.S index 204eceff7e..4e3a0f3c9a 100644 --- a/runtime/interpreter/mterp/arm64/op_unused_f7.S +++ b/runtime/interpreter/mterp/arm64/op_unused_f7.S @@ -1 +1,2 @@ -%include "arm64/unused.S" +%def op_unused_f7(): +% unused() diff --git a/runtime/interpreter/mterp/arm64/op_unused_f8.S b/runtime/interpreter/mterp/arm64/op_unused_f8.S index 204eceff7e..d1220752d7 100644 --- a/runtime/interpreter/mterp/arm64/op_unused_f8.S +++ b/runtime/interpreter/mterp/arm64/op_unused_f8.S @@ -1 +1,2 @@ -%include "arm64/unused.S" +%def op_unused_f8(): +% unused() diff --git a/runtime/interpreter/mterp/arm64/op_unused_f9.S b/runtime/interpreter/mterp/arm64/op_unused_f9.S index 204eceff7e..7d09a0ebcf 100644 --- a/runtime/interpreter/mterp/arm64/op_unused_f9.S +++ b/runtime/interpreter/mterp/arm64/op_unused_f9.S @@ -1 +1,2 @@ -%include "arm64/unused.S" +%def op_unused_f9(): +% unused() diff --git a/runtime/interpreter/mterp/arm64/op_unused_fc.S b/runtime/interpreter/mterp/arm64/op_unused_fc.S index 204eceff7e..06978191eb 100644 --- a/runtime/interpreter/mterp/arm64/op_unused_fc.S +++ b/runtime/interpreter/mterp/arm64/op_unused_fc.S @@ -1 +1,2 @@ -%include "arm64/unused.S" +%def op_unused_fc(): +% unused() diff --git a/runtime/interpreter/mterp/arm64/op_unused_fd.S b/runtime/interpreter/mterp/arm64/op_unused_fd.S index 204eceff7e..4bc2b4bdb6 100644 --- a/runtime/interpreter/mterp/arm64/op_unused_fd.S +++ b/runtime/interpreter/mterp/arm64/op_unused_fd.S @@ -1 +1,2 @@ -%include "arm64/unused.S" +%def op_unused_fd(): +% unused() diff --git a/runtime/interpreter/mterp/arm64/op_ushr_int.S b/runtime/interpreter/mterp/arm64/op_ushr_int.S index 005452b554..5f6ad2d8fd 100644 --- a/runtime/interpreter/mterp/arm64/op_ushr_int.S +++ b/runtime/interpreter/mterp/arm64/op_ushr_int.S @@ -1 +1,2 @@ -%include "arm64/binop.S" {"instr":"lsr w0, w0, w1"} +%def op_ushr_int(): +% binop(instr="lsr w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_ushr_int_2addr.S b/runtime/interpreter/mterp/arm64/op_ushr_int_2addr.S index 1cb8cb7442..47527b182f 100644 --- a/runtime/interpreter/mterp/arm64/op_ushr_int_2addr.S +++ b/runtime/interpreter/mterp/arm64/op_ushr_int_2addr.S @@ -1 +1,2 @@ -%include "arm64/binop2addr.S" {"instr":"lsr w0, w0, w1"} +%def op_ushr_int_2addr(): +% binop2addr(instr="lsr w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_ushr_int_lit8.S b/runtime/interpreter/mterp/arm64/op_ushr_int_lit8.S index 555ed4eb29..abc5898bcb 100644 --- a/runtime/interpreter/mterp/arm64/op_ushr_int_lit8.S +++ b/runtime/interpreter/mterp/arm64/op_ushr_int_lit8.S @@ -1 +1,2 @@ -%include "arm64/binopLit8.S" {"extract":"ubfx w1, w3, #8, #5", "instr":"lsr w0, w0, w1"} +%def op_ushr_int_lit8(): +% binopLit8(extract="ubfx w1, w3, #8, #5", instr="lsr w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_ushr_long.S b/runtime/interpreter/mterp/arm64/op_ushr_long.S index e13c86a48b..4f3e941872 100644 --- a/runtime/interpreter/mterp/arm64/op_ushr_long.S +++ b/runtime/interpreter/mterp/arm64/op_ushr_long.S @@ -1 +1,2 @@ -%include "arm64/shiftWide.S" {"opcode":"lsr"} +%def op_ushr_long(): +% shiftWide(opcode="lsr") diff --git a/runtime/interpreter/mterp/arm64/op_ushr_long_2addr.S b/runtime/interpreter/mterp/arm64/op_ushr_long_2addr.S index 67ec91e967..5606d12a21 100644 --- a/runtime/interpreter/mterp/arm64/op_ushr_long_2addr.S +++ b/runtime/interpreter/mterp/arm64/op_ushr_long_2addr.S @@ -1 +1,2 @@ -%include "arm64/shiftWide2addr.S" {"opcode":"lsr"} +%def op_ushr_long_2addr(): +% shiftWide2addr(opcode="lsr") diff --git a/runtime/interpreter/mterp/arm64/op_xor_int.S b/runtime/interpreter/mterp/arm64/op_xor_int.S index 74836635fe..369af7dc11 100644 --- a/runtime/interpreter/mterp/arm64/op_xor_int.S +++ b/runtime/interpreter/mterp/arm64/op_xor_int.S @@ -1 +1,2 @@ -%include "arm64/binop.S" {"instr":"eor w0, w0, w1"} +%def op_xor_int(): +% binop(instr="eor w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_xor_int_2addr.S b/runtime/interpreter/mterp/arm64/op_xor_int_2addr.S index 2f9a2c7359..f8e87b359f 100644 --- a/runtime/interpreter/mterp/arm64/op_xor_int_2addr.S +++ b/runtime/interpreter/mterp/arm64/op_xor_int_2addr.S @@ -1 +1,2 @@ -%include "arm64/binop2addr.S" {"instr":"eor w0, w0, w1"} +%def op_xor_int_2addr(): +% binop2addr(instr="eor w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_xor_int_lit16.S b/runtime/interpreter/mterp/arm64/op_xor_int_lit16.S index 6b72c560f9..bcfc6e20b3 100644 --- a/runtime/interpreter/mterp/arm64/op_xor_int_lit16.S +++ b/runtime/interpreter/mterp/arm64/op_xor_int_lit16.S @@ -1 +1,2 @@ -%include "arm64/binopLit16.S" {"instr":"eor w0, w0, w1"} +%def op_xor_int_lit16(): +% binopLit16(instr="eor w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_xor_int_lit8.S b/runtime/interpreter/mterp/arm64/op_xor_int_lit8.S index 1d3d93e3f7..bd59c4cdbd 100644 --- a/runtime/interpreter/mterp/arm64/op_xor_int_lit8.S +++ b/runtime/interpreter/mterp/arm64/op_xor_int_lit8.S @@ -1 +1,2 @@ -%include "arm64/binopLit8.S" {"extract":"", "instr":"eor w0, w0, w3, asr #8"} +%def op_xor_int_lit8(): +% binopLit8(extract="", instr="eor w0, w0, w3, asr #8") diff --git a/runtime/interpreter/mterp/arm64/op_xor_long.S b/runtime/interpreter/mterp/arm64/op_xor_long.S index 3880d5d19f..58b97bd247 100644 --- a/runtime/interpreter/mterp/arm64/op_xor_long.S +++ b/runtime/interpreter/mterp/arm64/op_xor_long.S @@ -1 +1,2 @@ -%include "arm64/binopWide.S" {"instr":"eor x0, x1, x2"} +%def op_xor_long(): +% binopWide(instr="eor x0, x1, x2") diff --git a/runtime/interpreter/mterp/arm64/op_xor_long_2addr.S b/runtime/interpreter/mterp/arm64/op_xor_long_2addr.S index 36905529d5..5877665de7 100644 --- a/runtime/interpreter/mterp/arm64/op_xor_long_2addr.S +++ b/runtime/interpreter/mterp/arm64/op_xor_long_2addr.S @@ -1 +1,2 @@ -%include "arm64/binopWide2addr.S" {"instr":"eor x0, x0, x1"} +%def op_xor_long_2addr(): +% binopWide2addr(instr="eor x0, x0, x1") diff --git a/runtime/interpreter/mterp/arm64/shiftWide.S b/runtime/interpreter/mterp/arm64/shiftWide.S index dcb2fb701a..46922c8626 100644 --- a/runtime/interpreter/mterp/arm64/shiftWide.S +++ b/runtime/interpreter/mterp/arm64/shiftWide.S @@ -1,4 +1,4 @@ -%default {"opcode":"shl"} +%def shiftWide(opcode="shl"): /* * 64-bit shift operation. * diff --git a/runtime/interpreter/mterp/arm64/shiftWide2addr.S b/runtime/interpreter/mterp/arm64/shiftWide2addr.S index b860dfddd3..2780d455e3 100644 --- a/runtime/interpreter/mterp/arm64/shiftWide2addr.S +++ b/runtime/interpreter/mterp/arm64/shiftWide2addr.S @@ -1,4 +1,4 @@ -%default {"opcode":"lsl"} +%def shiftWide2addr(opcode="lsl"): /* * Generic 64-bit shift operation. */ diff --git a/runtime/interpreter/mterp/arm64/unop.S b/runtime/interpreter/mterp/arm64/unop.S index e681968a9f..65faf665ab 100644 --- a/runtime/interpreter/mterp/arm64/unop.S +++ b/runtime/interpreter/mterp/arm64/unop.S @@ -1,3 +1,4 @@ +%def unop(instr=""): /* * Generic 32-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result = op w0". diff --git a/runtime/interpreter/mterp/arm64/unopWide.S b/runtime/interpreter/mterp/arm64/unopWide.S index 6ee4f922e1..6a16dfa9f0 100644 --- a/runtime/interpreter/mterp/arm64/unopWide.S +++ b/runtime/interpreter/mterp/arm64/unopWide.S @@ -1,4 +1,4 @@ -%default {"instr":"sub x0, xzr, x0"} +%def unopWide(instr="sub x0, xzr, x0"): /* * Generic 64-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result = op x0". diff --git a/runtime/interpreter/mterp/arm64/unused.S b/runtime/interpreter/mterp/arm64/unused.S index ffa00becfd..3f37e74bb4 100644 --- a/runtime/interpreter/mterp/arm64/unused.S +++ b/runtime/interpreter/mterp/arm64/unused.S @@ -1,3 +1,4 @@ +%def unused(): /* * Bail to reference interpreter to throw. */ diff --git a/runtime/interpreter/mterp/arm64/zcmp.S b/runtime/interpreter/mterp/arm64/zcmp.S index 510a3c10cd..4435854d14 100644 --- a/runtime/interpreter/mterp/arm64/zcmp.S +++ b/runtime/interpreter/mterp/arm64/zcmp.S @@ -1,4 +1,4 @@ -%default { "compare":"1" } +%def zcmp(compare="1", branch=""): /* * Generic one-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform. diff --git a/runtime/interpreter/mterp/common/gen_setup.py b/runtime/interpreter/mterp/common/gen_setup.py new file mode 100644 index 0000000000..b2e62f6ea0 --- /dev/null +++ b/runtime/interpreter/mterp/common/gen_setup.py @@ -0,0 +1,85 @@ +# +# Copyright (C) 2016 The Android Open Source Project +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +# Common global variables and helper methods for the in-memory python script. + +import sys, re +from cStringIO import StringIO + +out = StringIO() # File-like in-memory buffer. +handler_size_bytes = "128" +handler_size_bits = "7" +opcode = "" +opnum = "" + +def write_line(line): + out.write(line + "\n") + +def balign(): + write_line(" .balign {}".format(handler_size_bytes)) + +def write_opcode(num, name, write_method, is_alt): + global opnum, opcode + opnum, opcode = str(num), name + if is_alt: + name = "ALT_" + name + write_line("/* ------------------------------ */") + balign() + write_line(".L_{1}: /* {0:#04x} */".format(num, name)) + if is_alt: + alt_stub() + else: + write_method() + write_line("") + opnum, opcode = None, None + +def generate(): + out.seek(0) + out.truncate() + write_line("/* DO NOT EDIT: This file was generated by gen-mterp.py. */") + header() + entry() + + instruction_start() + opcodes(is_alt = False) + balign() + instruction_end() + + instruction_start_sister() + write_sister() + instruction_end_sister() + + # We need to footer sooner so that branch instruction can reach it. + # TODO: Clean up. + if arch == "arm64": + footer() + + instruction_start_alt() + opcodes(is_alt = True) + balign() + instruction_end_alt() + + if arch == "arm64": + close_cfi() + else: + footer() + + out.seek(0) + # Squash consequtive empty lines. + text = re.sub(r"(\n\n)(\n)+", r"\1", out.read()) + with open('out/mterp_' + arch + '.S', 'w') as output_file: + output_file.write(text) + diff --git a/runtime/interpreter/mterp/config_arm b/runtime/interpreter/mterp/config_arm deleted file mode 100644 index a45efd999b..0000000000 --- a/runtime/interpreter/mterp/config_arm +++ /dev/null @@ -1,298 +0,0 @@ -# Copyright (C) 2015 The Android Open Source Project -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -# -# Configuration for ARMv7-A targets. -# - -handler-style computed-goto -handler-size 128 - -# source for alternate entry stub -asm-alt-stub arm/alt_stub.S - -# file header and basic definitions -import arm/header.S - -# arch-specific entry point to interpreter -import arm/entry.S - -# Stub to switch to alternate interpreter -fallback-stub arm/fallback.S - -# opcode list; argument to op-start is default directory -op-start arm - # (override example:) op op_sub_float_2addr arm-vfp - # (fallback example:) op op_sub_float_2addr FALLBACK - - # op op_nop FALLBACK - # op op_move FALLBACK - # op op_move_from16 FALLBACK - # op op_move_16 FALLBACK - # op op_move_wide FALLBACK - # op op_move_wide_from16 FALLBACK - # op op_move_wide_16 FALLBACK - # op op_move_object FALLBACK - # op op_move_object_from16 FALLBACK - # op op_move_object_16 FALLBACK - # op op_move_result FALLBACK - # op op_move_result_wide FALLBACK - # op op_move_result_object FALLBACK - # op op_move_exception FALLBACK - # op op_return_void FALLBACK - # op op_return FALLBACK - # op op_return_wide FALLBACK - # op op_return_object FALLBACK - # op op_const_4 FALLBACK - # op op_const_16 FALLBACK - # op op_const FALLBACK - # op op_const_high16 FALLBACK - # op op_const_wide_16 FALLBACK - # op op_const_wide_32 FALLBACK - # op op_const_wide FALLBACK - # op op_const_wide_high16 FALLBACK - # op op_const_string FALLBACK - # op op_const_string_jumbo FALLBACK - # op op_const_class FALLBACK - # op op_monitor_enter FALLBACK - # op op_monitor_exit FALLBACK - # op op_check_cast FALLBACK - # op op_instance_of FALLBACK - # op op_array_length FALLBACK - # op op_new_instance FALLBACK - # op op_new_array FALLBACK - # op op_filled_new_array FALLBACK - # op op_filled_new_array_range FALLBACK - # op op_fill_array_data FALLBACK - # op op_throw FALLBACK - # op op_goto FALLBACK - # op op_goto_16 FALLBACK - # op op_goto_32 FALLBACK - # op op_packed_switch FALLBACK - # op op_sparse_switch FALLBACK - # op op_cmpl_float FALLBACK - # op op_cmpg_float FALLBACK - # op op_cmpl_double FALLBACK - # op op_cmpg_double FALLBACK - # op op_cmp_long FALLBACK - # op op_if_eq FALLBACK - # op op_if_ne FALLBACK - # op op_if_lt FALLBACK - # op op_if_ge FALLBACK - # op op_if_gt FALLBACK - # op op_if_le FALLBACK - # op op_if_eqz FALLBACK - # op op_if_nez FALLBACK - # op op_if_ltz FALLBACK - # op op_if_gez FALLBACK - # op op_if_gtz FALLBACK - # op op_if_lez FALLBACK - # op op_unused_3e FALLBACK - # op op_unused_3f FALLBACK - # op op_unused_40 FALLBACK - # op op_unused_41 FALLBACK - # op op_unused_42 FALLBACK - # op op_unused_43 FALLBACK - # op op_aget FALLBACK - # op op_aget_wide FALLBACK - # op op_aget_object FALLBACK - # op op_aget_boolean FALLBACK - # op op_aget_byte FALLBACK - # op op_aget_char FALLBACK - # op op_aget_short FALLBACK - # op op_aput FALLBACK - # op op_aput_wide FALLBACK - # op op_aput_object FALLBACK - # op op_aput_boolean FALLBACK - # op op_aput_byte FALLBACK - # op op_aput_char FALLBACK - # op op_aput_short FALLBACK - # op op_iget FALLBACK - # op op_iget_wide FALLBACK - # op op_iget_object FALLBACK - # op op_iget_boolean FALLBACK - # op op_iget_byte FALLBACK - # op op_iget_char FALLBACK - # op op_iget_short FALLBACK - # op op_iput FALLBACK - # op op_iput_wide FALLBACK - # op op_iput_object FALLBACK - # op op_iput_boolean FALLBACK - # op op_iput_byte FALLBACK - # op op_iput_char FALLBACK - # op op_iput_short FALLBACK - # op op_sget FALLBACK - # op op_sget_wide FALLBACK - # op op_sget_object FALLBACK - # op op_sget_boolean FALLBACK - # op op_sget_byte FALLBACK - # op op_sget_char FALLBACK - # op op_sget_short FALLBACK - # op op_sput FALLBACK - # op op_sput_wide FALLBACK - # op op_sput_object FALLBACK - # op op_sput_boolean FALLBACK - # op op_sput_byte FALLBACK - # op op_sput_char FALLBACK - # op op_sput_short FALLBACK - # op op_invoke_virtual FALLBACK - # op op_invoke_super FALLBACK - # op op_invoke_direct FALLBACK - # op op_invoke_static FALLBACK - # op op_invoke_interface FALLBACK - # op op_return_void_no_barrier FALLBACK - # op op_invoke_virtual_range FALLBACK - # op op_invoke_super_range FALLBACK - # op op_invoke_direct_range FALLBACK - # op op_invoke_static_range FALLBACK - # op op_invoke_interface_range FALLBACK - # op op_unused_79 FALLBACK - # op op_unused_7a FALLBACK - # op op_neg_int FALLBACK - # op op_not_int FALLBACK - # op op_neg_long FALLBACK - # op op_not_long FALLBACK - # op op_neg_float FALLBACK - # op op_neg_double FALLBACK - # op op_int_to_long FALLBACK - # op op_int_to_float FALLBACK - # op op_int_to_double FALLBACK - # op op_long_to_int FALLBACK - # op op_long_to_float FALLBACK - # op op_long_to_double FALLBACK - # op op_float_to_int FALLBACK - # op op_float_to_long FALLBACK - # op op_float_to_double FALLBACK - # op op_double_to_int FALLBACK - # op op_double_to_long FALLBACK - # op op_double_to_float FALLBACK - # op op_int_to_byte FALLBACK - # op op_int_to_char FALLBACK - # op op_int_to_short FALLBACK - # op op_add_int FALLBACK - # op op_sub_int FALLBACK - # op op_mul_int FALLBACK - # op op_div_int FALLBACK - # op op_rem_int FALLBACK - # op op_and_int FALLBACK - # op op_or_int FALLBACK - # op op_xor_int FALLBACK - # op op_shl_int FALLBACK - # op op_shr_int FALLBACK - # op op_ushr_int FALLBACK - # op op_add_long FALLBACK - # op op_sub_long FALLBACK - # op op_mul_long FALLBACK - # op op_div_long FALLBACK - # op op_rem_long FALLBACK - # op op_and_long FALLBACK - # op op_or_long FALLBACK - # op op_xor_long FALLBACK - # op op_shl_long FALLBACK - # op op_shr_long FALLBACK - # op op_ushr_long FALLBACK - # op op_add_float FALLBACK - # op op_sub_float FALLBACK - # op op_mul_float FALLBACK - # op op_div_float FALLBACK - # op op_rem_float FALLBACK - # op op_add_double FALLBACK - # op op_sub_double FALLBACK - # op op_mul_double FALLBACK - # op op_div_double FALLBACK - # op op_rem_double FALLBACK - # op op_add_int_2addr FALLBACK - # op op_sub_int_2addr FALLBACK - # op op_mul_int_2addr FALLBACK - # op op_div_int_2addr FALLBACK - # op op_rem_int_2addr FALLBACK - # op op_and_int_2addr FALLBACK - # op op_or_int_2addr FALLBACK - # op op_xor_int_2addr FALLBACK - # op op_shl_int_2addr FALLBACK - # op op_shr_int_2addr FALLBACK - # op op_ushr_int_2addr FALLBACK - # op op_add_long_2addr FALLBACK - # op op_sub_long_2addr FALLBACK - # op op_mul_long_2addr FALLBACK - # op op_div_long_2addr FALLBACK - # op op_rem_long_2addr FALLBACK - # op op_and_long_2addr FALLBACK - # op op_or_long_2addr FALLBACK - # op op_xor_long_2addr FALLBACK - # op op_shl_long_2addr FALLBACK - # op op_shr_long_2addr FALLBACK - # op op_ushr_long_2addr FALLBACK - # op op_add_float_2addr FALLBACK - # op op_sub_float_2addr FALLBACK - # op op_mul_float_2addr FALLBACK - # op op_div_float_2addr FALLBACK - # op op_rem_float_2addr FALLBACK - # op op_add_double_2addr FALLBACK - # op op_sub_double_2addr FALLBACK - # op op_mul_double_2addr FALLBACK - # op op_div_double_2addr FALLBACK - # op op_rem_double_2addr FALLBACK - # op op_add_int_lit16 FALLBACK - # op op_rsub_int FALLBACK - # op op_mul_int_lit16 FALLBACK - # op op_div_int_lit16 FALLBACK - # op op_rem_int_lit16 FALLBACK - # op op_and_int_lit16 FALLBACK - # op op_or_int_lit16 FALLBACK - # op op_xor_int_lit16 FALLBACK - # op op_add_int_lit8 FALLBACK - # op op_rsub_int_lit8 FALLBACK - # op op_mul_int_lit8 FALLBACK - # op op_div_int_lit8 FALLBACK - # op op_rem_int_lit8 FALLBACK - # op op_and_int_lit8 FALLBACK - # op op_or_int_lit8 FALLBACK - # op op_xor_int_lit8 FALLBACK - # op op_shl_int_lit8 FALLBACK - # op op_shr_int_lit8 FALLBACK - # op op_ushr_int_lit8 FALLBACK - # op op_iget_quick FALLBACK - # op op_iget_wide_quick FALLBACK - # op op_iget_object_quick FALLBACK - # op op_iput_quick FALLBACK - # op op_iput_wide_quick FALLBACK - # op op_iput_object_quick FALLBACK - # op op_invoke_virtual_quick FALLBACK - # op op_invoke_virtual_range_quick FALLBACK - # op op_iput_boolean_quick FALLBACK - # op op_iput_byte_quick FALLBACK - # op op_iput_char_quick FALLBACK - # op op_iput_short_quick FALLBACK - # op op_iget_boolean_quick FALLBACK - # op op_iget_byte_quick FALLBACK - # op op_iget_char_quick FALLBACK - # op op_iget_short_quick FALLBACK - # op op_unused_f3 FALLBACK - # op op_unused_f4 FALLBACK - # op op_unused_f5 FALLBACK - # op op_unused_f6 FALLBACK - # op op_unused_f7 FALLBACK - # op op_unused_f8 FALLBACK - # op op_unused_f9 FALLBACK - # op op_invoke_polymorphic FALLBACK - # op op_invoke_polymorphic_range FALLBACK - # op op_invoke_custom FALLBACK - # op op_invoke_custom_range FALLBACK - # op op_const_method_handle FALLBACK - # op op_const_method_type FALLBACK -op-end - -# common subroutines for asm -import arm/footer.S diff --git a/runtime/interpreter/mterp/config_arm64 b/runtime/interpreter/mterp/config_arm64 deleted file mode 100644 index 590363f6e4..0000000000 --- a/runtime/interpreter/mterp/config_arm64 +++ /dev/null @@ -1,306 +0,0 @@ - -# Copyright (C) 2015 The Android Open Source Project -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -# -# Configuration for ARM64 -# - -handler-style computed-goto -handler-size 128 - -# file header and basic definitions -import arm64/header.S - -# arch-specific entry point to interpreter -import arm64/entry.S - -# Stub to switch to alternate interpreter -fallback-stub arm64/fallback.S - -# opcode list; argument to op-start is default directory -op-start arm64 - # (override example:) op OP_SUB_FLOAT_2ADDR arm-vfp - # (fallback example:) op OP_SUB_FLOAT_2ADDR FALLBACK - - # op op_nop FALLBACK - # op op_move FALLBACK - # op op_move_from16 FALLBACK - # op op_move_16 FALLBACK - # op op_move_wide FALLBACK - # op op_move_wide_from16 FALLBACK - # op op_move_wide_16 FALLBACK - # op op_move_object FALLBACK - # op op_move_object_from16 FALLBACK - # op op_move_object_16 FALLBACK - # op op_move_result FALLBACK - # op op_move_result_wide FALLBACK - # op op_move_result_object FALLBACK - # op op_move_exception FALLBACK - # op op_return_void FALLBACK - # op op_return FALLBACK - # op op_return_wide FALLBACK - # op op_return_object FALLBACK - # op op_const_4 FALLBACK - # op op_const_16 FALLBACK - # op op_const FALLBACK - # op op_const_high16 FALLBACK - # op op_const_wide_16 FALLBACK - # op op_const_wide_32 FALLBACK - # op op_const_wide FALLBACK - # op op_const_wide_high16 FALLBACK - # op op_const_string FALLBACK - # op op_const_string_jumbo FALLBACK - # op op_const_class FALLBACK - # op op_monitor_enter FALLBACK - # op op_monitor_exit FALLBACK - # op op_check_cast FALLBACK - # op op_instance_of FALLBACK - # op op_array_length FALLBACK - # op op_new_instance FALLBACK - # op op_new_array FALLBACK - # op op_filled_new_array FALLBACK - # op op_filled_new_array_range FALLBACK - # op op_fill_array_data FALLBACK - # op op_throw FALLBACK - # op op_goto FALLBACK - # op op_goto_16 FALLBACK - # op op_goto_32 FALLBACK - # op op_packed_switch FALLBACK - # op op_sparse_switch FALLBACK - # op op_cmpl_float FALLBACK - # op op_cmpg_float FALLBACK - # op op_cmpl_double FALLBACK - # op op_cmpg_double FALLBACK - # op op_cmp_long FALLBACK - # op op_if_eq FALLBACK - # op op_if_ne FALLBACK - # op op_if_lt FALLBACK - # op op_if_ge FALLBACK - # op op_if_gt FALLBACK - # op op_if_le FALLBACK - # op op_if_eqz FALLBACK - # op op_if_nez FALLBACK - # op op_if_ltz FALLBACK - # op op_if_gez FALLBACK - # op op_if_gtz FALLBACK - # op op_if_lez FALLBACK - # op op_unused_3e FALLBACK - # op op_unused_3f FALLBACK - # op op_unused_40 FALLBACK - # op op_unused_41 FALLBACK - # op op_unused_42 FALLBACK - # op op_unused_43 FALLBACK - # op op_aget FALLBACK - # op op_aget_wide FALLBACK - # op op_aget_object FALLBACK - # op op_aget_boolean FALLBACK - # op op_aget_byte FALLBACK - # op op_aget_char FALLBACK - # op op_aget_short FALLBACK - # op op_aput FALLBACK - # op op_aput_wide FALLBACK - # op op_aput_object FALLBACK - # op op_aput_boolean FALLBACK - # op op_aput_byte FALLBACK - # op op_aput_char FALLBACK - # op op_aput_short FALLBACK - # op op_iget FALLBACK - # op op_iget_wide FALLBACK - # op op_iget_object FALLBACK - # op op_iget_boolean FALLBACK - # op op_iget_byte FALLBACK - # op op_iget_char FALLBACK - # op op_iget_short FALLBACK - # op op_iput FALLBACK - # op op_iput_wide FALLBACK - # op op_iput_object FALLBACK - # op op_iput_boolean FALLBACK - # op op_iput_byte FALLBACK - # op op_iput_char FALLBACK - # op op_iput_short FALLBACK - # op op_sget FALLBACK - # op op_sget_wide FALLBACK - # op op_sget_object FALLBACK - # op op_sget_boolean FALLBACK - # op op_sget_byte FALLBACK - # op op_sget_char FALLBACK - # op op_sget_short FALLBACK - # op op_sput FALLBACK - # op op_sput_wide FALLBACK - # op op_sput_object FALLBACK - # op op_sput_boolean FALLBACK - # op op_sput_byte FALLBACK - # op op_sput_char FALLBACK - # op op_sput_short FALLBACK - # op op_invoke_virtual FALLBACK - # op op_invoke_super FALLBACK - # op op_invoke_direct FALLBACK - # op op_invoke_static FALLBACK - # op op_invoke_interface FALLBACK - # op op_return_void_no_barrier FALLBACK - # op op_invoke_virtual_range FALLBACK - # op op_invoke_super_range FALLBACK - # op op_invoke_direct_range FALLBACK - # op op_invoke_static_range FALLBACK - # op op_invoke_interface_range FALLBACK - # op op_unused_79 FALLBACK - # op op_unused_7a FALLBACK - # op op_neg_int FALLBACK - # op op_not_int FALLBACK - # op op_neg_long FALLBACK - # op op_not_long FALLBACK - # op op_neg_float FALLBACK - # op op_neg_double FALLBACK - # op op_int_to_long FALLBACK - # op op_int_to_float FALLBACK - # op op_int_to_double FALLBACK - # op op_long_to_int FALLBACK - # op op_long_to_float FALLBACK - # op op_long_to_double FALLBACK - # op op_float_to_int FALLBACK - # op op_float_to_long FALLBACK - # op op_float_to_double FALLBACK - # op op_double_to_int FALLBACK - # op op_double_to_long FALLBACK - # op op_double_to_float FALLBACK - # op op_int_to_byte FALLBACK - # op op_int_to_char FALLBACK - # op op_int_to_short FALLBACK - # op op_add_int FALLBACK - # op op_sub_int FALLBACK - # op op_mul_int FALLBACK - # op op_div_int FALLBACK - # op op_rem_int FALLBACK - # op op_and_int FALLBACK - # op op_or_int FALLBACK - # op op_xor_int FALLBACK - # op op_shl_int FALLBACK - # op op_shr_int FALLBACK - # op op_ushr_int FALLBACK - # op op_add_long FALLBACK - # op op_sub_long FALLBACK - # op op_mul_long FALLBACK - # op op_div_long FALLBACK - # op op_rem_long FALLBACK - # op op_and_long FALLBACK - # op op_or_long FALLBACK - # op op_xor_long FALLBACK - # op op_shl_long FALLBACK - # op op_shr_long FALLBACK - # op op_ushr_long FALLBACK - # op op_add_float FALLBACK - # op op_sub_float FALLBACK - # op op_mul_float FALLBACK - # op op_div_float FALLBACK - # op op_rem_float FALLBACK - # op op_add_double FALLBACK - # op op_sub_double FALLBACK - # op op_mul_double FALLBACK - # op op_div_double FALLBACK - # op op_rem_double FALLBACK - # op op_add_int_2addr FALLBACK - # op op_sub_int_2addr FALLBACK - # op op_mul_int_2addr FALLBACK - # op op_div_int_2addr FALLBACK - # op op_rem_int_2addr FALLBACK - # op op_and_int_2addr FALLBACK - # op op_or_int_2addr FALLBACK - # op op_xor_int_2addr FALLBACK - # op op_shl_int_2addr FALLBACK - # op op_shr_int_2addr FALLBACK - # op op_ushr_int_2addr FALLBACK - # op op_add_long_2addr FALLBACK - # op op_sub_long_2addr FALLBACK - # op op_mul_long_2addr FALLBACK - # op op_div_long_2addr FALLBACK - # op op_rem_long_2addr FALLBACK - # op op_and_long_2addr FALLBACK - # op op_or_long_2addr FALLBACK - # op op_xor_long_2addr FALLBACK - # op op_shl_long_2addr FALLBACK - # op op_shr_long_2addr FALLBACK - # op op_ushr_long_2addr FALLBACK - # op op_add_float_2addr FALLBACK - # op op_sub_float_2addr FALLBACK - # op op_mul_float_2addr FALLBACK - # op op_div_float_2addr FALLBACK - # op op_rem_float_2addr FALLBACK - # op op_add_double_2addr FALLBACK - # op op_sub_double_2addr FALLBACK - # op op_mul_double_2addr FALLBACK - # op op_div_double_2addr FALLBACK - # op op_rem_double_2addr FALLBACK - # op op_add_int_lit16 FALLBACK - # op op_rsub_int FALLBACK - # op op_mul_int_lit16 FALLBACK - # op op_div_int_lit16 FALLBACK - # op op_rem_int_lit16 FALLBACK - # op op_and_int_lit16 FALLBACK - # op op_or_int_lit16 FALLBACK - # op op_xor_int_lit16 FALLBACK - # op op_add_int_lit8 FALLBACK - # op op_rsub_int_lit8 FALLBACK - # op op_mul_int_lit8 FALLBACK - # op op_div_int_lit8 FALLBACK - # op op_rem_int_lit8 FALLBACK - # op op_and_int_lit8 FALLBACK - # op op_or_int_lit8 FALLBACK - # op op_xor_int_lit8 FALLBACK - # op op_shl_int_lit8 FALLBACK - # op op_shr_int_lit8 FALLBACK - # op op_ushr_int_lit8 FALLBACK - # op op_iget_quick FALLBACK - # op op_iget_wide_quick FALLBACK - # op op_iget_object_quick FALLBACK - # op op_iput_quick FALLBACK - # op op_iput_wide_quick FALLBACK - # op op_iput_object_quick FALLBACK - # op op_invoke_virtual_quick FALLBACK - # op op_invoke_virtual_range_quick FALLBACK - # op op_iput_boolean_quick FALLBACK - # op op_iput_byte_quick FALLBACK - # op op_iput_char_quick FALLBACK - # op op_iput_short_quick FALLBACK - # op op_iget_boolean_quick FALLBACK - # op op_iget_byte_quick FALLBACK - # op op_iget_char_quick FALLBACK - # op op_iget_short_quick FALLBACK - # op op_unused_f3 FALLBACK - # op op_unused_f4 FALLBACK - # op op_unused_f5 FALLBACK - # op op_unused_f6 FALLBACK - # op op_unused_f7 FALLBACK - # op op_unused_f8 FALLBACK - # op op_unused_f9 FALLBACK - # op op_invoke_polymorphic FALLBACK - # op op_invoke_polymorphic_range FALLBACK - # op op_invoke_custom FALLBACK - # op op_invoke_custom_range FALLBACK - # op op_const_method_handle FALLBACK - # op op_const_method_type FALLBACK -op-end - -# common subroutines for asm; we emit the footer before alternate -# entry stubs, so that TBZ/TBNZ from ops can reach targets in footer -import arm64/footer.S - -# source for alternate entry stub -asm-alt-stub arm64/alt_stub.S - -# emit alternate entry stubs -alt-ops - -# finish by closing .cfi info -import arm64/close_cfi.S diff --git a/runtime/interpreter/mterp/config_mips b/runtime/interpreter/mterp/config_mips deleted file mode 100644 index d6173daf2c..0000000000 --- a/runtime/interpreter/mterp/config_mips +++ /dev/null @@ -1,298 +0,0 @@ -# Copyright (C) 2016 The Android Open Source Project -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -# -# Configuration for MIPS_32 targets. -# - -handler-style computed-goto -handler-size 128 - -# source for alternate entry stub -asm-alt-stub mips/alt_stub.S - -# file header and basic definitions -import mips/header.S - -# arch-specific entry point to interpreter -import mips/entry.S - -# Stub to switch to alternate interpreter -fallback-stub mips/fallback.S - -# opcode list; argument to op-start is default directory -op-start mips - # (override example:) op op_sub_float_2addr arm-vfp - # (fallback example:) op op_sub_float_2addr FALLBACK - - # op op_nop FALLBACK - # op op_move FALLBACK - # op op_move_from16 FALLBACK - # op op_move_16 FALLBACK - # op op_move_wide FALLBACK - # op op_move_wide_from16 FALLBACK - # op op_move_wide_16 FALLBACK - # op op_move_object FALLBACK - # op op_move_object_from16 FALLBACK - # op op_move_object_16 FALLBACK - # op op_move_result FALLBACK - # op op_move_result_wide FALLBACK - # op op_move_result_object FALLBACK - # op op_move_exception FALLBACK - # op op_return_void FALLBACK - # op op_return FALLBACK - # op op_return_wide FALLBACK - # op op_return_object FALLBACK - # op op_const_4 FALLBACK - # op op_const_16 FALLBACK - # op op_const FALLBACK - # op op_const_high16 FALLBACK - # op op_const_wide_16 FALLBACK - # op op_const_wide_32 FALLBACK - # op op_const_wide FALLBACK - # op op_const_wide_high16 FALLBACK - # op op_const_string FALLBACK - # op op_const_string_jumbo FALLBACK - # op op_const_class FALLBACK - # op op_monitor_enter FALLBACK - # op op_monitor_exit FALLBACK - # op op_check_cast FALLBACK - # op op_instance_of FALLBACK - # op op_array_length FALLBACK - # op op_new_instance FALLBACK - # op op_new_array FALLBACK - # op op_filled_new_array FALLBACK - # op op_filled_new_array_range FALLBACK - # op op_fill_array_data FALLBACK - # op op_throw FALLBACK - # op op_goto FALLBACK - # op op_goto_16 FALLBACK - # op op_goto_32 FALLBACK - # op op_packed_switch FALLBACK - # op op_sparse_switch FALLBACK - # op op_cmpl_float FALLBACK - # op op_cmpg_float FALLBACK - # op op_cmpl_double FALLBACK - # op op_cmpg_double FALLBACK - # op op_cmp_long FALLBACK - # op op_if_eq FALLBACK - # op op_if_ne FALLBACK - # op op_if_lt FALLBACK - # op op_if_ge FALLBACK - # op op_if_gt FALLBACK - # op op_if_le FALLBACK - # op op_if_eqz FALLBACK - # op op_if_nez FALLBACK - # op op_if_ltz FALLBACK - # op op_if_gez FALLBACK - # op op_if_gtz FALLBACK - # op op_if_lez FALLBACK - # op op_unused_3e FALLBACK - # op op_unused_3f FALLBACK - # op op_unused_40 FALLBACK - # op op_unused_41 FALLBACK - # op op_unused_42 FALLBACK - # op op_unused_43 FALLBACK - # op op_aget FALLBACK - # op op_aget_wide FALLBACK - # op op_aget_object FALLBACK - # op op_aget_boolean FALLBACK - # op op_aget_byte FALLBACK - # op op_aget_char FALLBACK - # op op_aget_short FALLBACK - # op op_aput FALLBACK - # op op_aput_wide FALLBACK - # op op_aput_object FALLBACK - # op op_aput_boolean FALLBACK - # op op_aput_byte FALLBACK - # op op_aput_char FALLBACK - # op op_aput_short FALLBACK - # op op_iget FALLBACK - # op op_iget_wide FALLBACK - # op op_iget_object FALLBACK - # op op_iget_boolean FALLBACK - # op op_iget_byte FALLBACK - # op op_iget_char FALLBACK - # op op_iget_short FALLBACK - # op op_iput FALLBACK - # op op_iput_wide FALLBACK - # op op_iput_object FALLBACK - # op op_iput_boolean FALLBACK - # op op_iput_byte FALLBACK - # op op_iput_char FALLBACK - # op op_iput_short FALLBACK - # op op_sget FALLBACK - # op op_sget_wide FALLBACK - # op op_sget_object FALLBACK - # op op_sget_boolean FALLBACK - # op op_sget_byte FALLBACK - # op op_sget_char FALLBACK - # op op_sget_short FALLBACK - # op op_sput FALLBACK - # op op_sput_wide FALLBACK - # op op_sput_object FALLBACK - # op op_sput_boolean FALLBACK - # op op_sput_byte FALLBACK - # op op_sput_char FALLBACK - # op op_sput_short FALLBACK - # op op_invoke_virtual FALLBACK - # op op_invoke_super FALLBACK - # op op_invoke_direct FALLBACK - # op op_invoke_static FALLBACK - # op op_invoke_interface FALLBACK - # op op_return_void_no_barrier FALLBACK - # op op_invoke_virtual_range FALLBACK - # op op_invoke_super_range FALLBACK - # op op_invoke_direct_range FALLBACK - # op op_invoke_static_range FALLBACK - # op op_invoke_interface_range FALLBACK - # op op_unused_79 FALLBACK - # op op_unused_7a FALLBACK - # op op_neg_int FALLBACK - # op op_not_int FALLBACK - # op op_neg_long FALLBACK - # op op_not_long FALLBACK - # op op_neg_float FALLBACK - # op op_neg_double FALLBACK - # op op_int_to_long FALLBACK - # op op_int_to_float FALLBACK - # op op_int_to_double FALLBACK - # op op_long_to_int FALLBACK - # op op_long_to_float FALLBACK - # op op_long_to_double FALLBACK - # op op_float_to_int FALLBACK - # op op_float_to_long FALLBACK - # op op_float_to_double FALLBACK - # op op_double_to_int FALLBACK - # op op_double_to_long FALLBACK - # op op_double_to_float FALLBACK - # op op_int_to_byte FALLBACK - # op op_int_to_char FALLBACK - # op op_int_to_short FALLBACK - # op op_add_int FALLBACK - # op op_sub_int FALLBACK - # op op_mul_int FALLBACK - # op op_div_int FALLBACK - # op op_rem_int FALLBACK - # op op_and_int FALLBACK - # op op_or_int FALLBACK - # op op_xor_int FALLBACK - # op op_shl_int FALLBACK - # op op_shr_int FALLBACK - # op op_ushr_int FALLBACK - # op op_add_long FALLBACK - # op op_sub_long FALLBACK - # op op_mul_long FALLBACK - # op op_div_long FALLBACK - # op op_rem_long FALLBACK - # op op_and_long FALLBACK - # op op_or_long FALLBACK - # op op_xor_long FALLBACK - # op op_shl_long FALLBACK - # op op_shr_long FALLBACK - # op op_ushr_long FALLBACK - # op op_add_float FALLBACK - # op op_sub_float FALLBACK - # op op_mul_float FALLBACK - # op op_div_float FALLBACK - # op op_rem_float FALLBACK - # op op_add_double FALLBACK - # op op_sub_double FALLBACK - # op op_mul_double FALLBACK - # op op_div_double FALLBACK - # op op_rem_double FALLBACK - # op op_add_int_2addr FALLBACK - # op op_sub_int_2addr FALLBACK - # op op_mul_int_2addr FALLBACK - # op op_div_int_2addr FALLBACK - # op op_rem_int_2addr FALLBACK - # op op_and_int_2addr FALLBACK - # op op_or_int_2addr FALLBACK - # op op_xor_int_2addr FALLBACK - # op op_shl_int_2addr FALLBACK - # op op_shr_int_2addr FALLBACK - # op op_ushr_int_2addr FALLBACK - # op op_add_long_2addr FALLBACK - # op op_sub_long_2addr FALLBACK - # op op_mul_long_2addr FALLBACK - # op op_div_long_2addr FALLBACK - # op op_rem_long_2addr FALLBACK - # op op_and_long_2addr FALLBACK - # op op_or_long_2addr FALLBACK - # op op_xor_long_2addr FALLBACK - # op op_shl_long_2addr FALLBACK - # op op_shr_long_2addr FALLBACK - # op op_ushr_long_2addr FALLBACK - # op op_add_float_2addr FALLBACK - # op op_sub_float_2addr FALLBACK - # op op_mul_float_2addr FALLBACK - # op op_div_float_2addr FALLBACK - # op op_rem_float_2addr FALLBACK - # op op_add_double_2addr FALLBACK - # op op_sub_double_2addr FALLBACK - # op op_mul_double_2addr FALLBACK - # op op_div_double_2addr FALLBACK - # op op_rem_double_2addr FALLBACK - # op op_add_int_lit16 FALLBACK - # op op_rsub_int FALLBACK - # op op_mul_int_lit16 FALLBACK - # op op_div_int_lit16 FALLBACK - # op op_rem_int_lit16 FALLBACK - # op op_and_int_lit16 FALLBACK - # op op_or_int_lit16 FALLBACK - # op op_xor_int_lit16 FALLBACK - # op op_add_int_lit8 FALLBACK - # op op_rsub_int_lit8 FALLBACK - # op op_mul_int_lit8 FALLBACK - # op op_div_int_lit8 FALLBACK - # op op_rem_int_lit8 FALLBACK - # op op_and_int_lit8 FALLBACK - # op op_or_int_lit8 FALLBACK - # op op_xor_int_lit8 FALLBACK - # op op_shl_int_lit8 FALLBACK - # op op_shr_int_lit8 FALLBACK - # op op_ushr_int_lit8 FALLBACK - # op op_iget_quick FALLBACK - # op op_iget_wide_quick FALLBACK - # op op_iget_object_quick FALLBACK - # op op_iput_quick FALLBACK - # op op_iput_wide_quick FALLBACK - # op op_iput_object_quick FALLBACK - # op op_invoke_virtual_quick FALLBACK - # op op_invoke_virtual_range_quick FALLBACK - # op op_iput_boolean_quick FALLBACK - # op op_iput_byte_quick FALLBACK - # op op_iput_char_quick FALLBACK - # op op_iput_short_quick FALLBACK - # op op_iget_boolean_quick FALLBACK - # op op_iget_byte_quick FALLBACK - # op op_iget_char_quick FALLBACK - # op op_iget_short_quick FALLBACK - # op op_unused_f3 FALLBACK - # op op_unused_f4 FALLBACK - # op op_unused_f5 FALLBACK - # op op_unused_f6 FALLBACK - # op op_unused_f7 FALLBACK - # op op_unused_f8 FALLBACK - # op op_unused_f9 FALLBACK - # op op_invoke_polymorphic FALLBACK - # op op_invoke_polymorphic_range FALLBACK - # op op_invoke_custom FALLBACK - # op op_invoke_custom_range FALLBACK - # op op_const_method_handle FALLBACK - # op op_const_method_type FALLBACK -op-end - -# common subroutines for asm -import mips/footer.S diff --git a/runtime/interpreter/mterp/config_mips64 b/runtime/interpreter/mterp/config_mips64 deleted file mode 100644 index a9bf362ec3..0000000000 --- a/runtime/interpreter/mterp/config_mips64 +++ /dev/null @@ -1,298 +0,0 @@ -# Copyright (C) 2015 The Android Open Source Project -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -# -# Configuration for MIPS_64 -# - -handler-style computed-goto -handler-size 128 - -# source for alternate entry stub -asm-alt-stub mips64/alt_stub.S - -# file header and basic definitions -import mips64/header.S - -# arch-specific entry point to interpreter -import mips64/entry.S - -# Stub to switch to alternate interpreter -fallback-stub mips64/fallback.S - -# opcode list; argument to op-start is default directory -op-start mips64 - # (override example:) op OP_SUB_FLOAT_2ADDR arm-vfp - # (fallback example:) op OP_SUB_FLOAT_2ADDR FALLBACK - - # op op_nop FALLBACK - # op op_move FALLBACK - # op op_move_from16 FALLBACK - # op op_move_16 FALLBACK - # op op_move_wide FALLBACK - # op op_move_wide_from16 FALLBACK - # op op_move_wide_16 FALLBACK - # op op_move_object FALLBACK - # op op_move_object_from16 FALLBACK - # op op_move_object_16 FALLBACK - # op op_move_result FALLBACK - # op op_move_result_wide FALLBACK - # op op_move_result_object FALLBACK - # op op_move_exception FALLBACK - # op op_return_void FALLBACK - # op op_return FALLBACK - # op op_return_wide FALLBACK - # op op_return_object FALLBACK - # op op_const_4 FALLBACK - # op op_const_16 FALLBACK - # op op_const FALLBACK - # op op_const_high16 FALLBACK - # op op_const_wide_16 FALLBACK - # op op_const_wide_32 FALLBACK - # op op_const_wide FALLBACK - # op op_const_wide_high16 FALLBACK - # op op_const_string FALLBACK - # op op_const_string_jumbo FALLBACK - # op op_const_class FALLBACK - # op op_monitor_enter FALLBACK - # op op_monitor_exit FALLBACK - # op op_check_cast FALLBACK - # op op_instance_of FALLBACK - # op op_array_length FALLBACK - # op op_new_instance FALLBACK - # op op_new_array FALLBACK - # op op_filled_new_array FALLBACK - # op op_filled_new_array_range FALLBACK - # op op_fill_array_data FALLBACK - # op op_throw FALLBACK - # op op_goto FALLBACK - # op op_goto_16 FALLBACK - # op op_goto_32 FALLBACK - # op op_packed_switch FALLBACK - # op op_sparse_switch FALLBACK - # op op_cmpl_float FALLBACK - # op op_cmpg_float FALLBACK - # op op_cmpl_double FALLBACK - # op op_cmpg_double FALLBACK - # op op_cmp_long FALLBACK - # op op_if_eq FALLBACK - # op op_if_ne FALLBACK - # op op_if_lt FALLBACK - # op op_if_ge FALLBACK - # op op_if_gt FALLBACK - # op op_if_le FALLBACK - # op op_if_eqz FALLBACK - # op op_if_nez FALLBACK - # op op_if_ltz FALLBACK - # op op_if_gez FALLBACK - # op op_if_gtz FALLBACK - # op op_if_lez FALLBACK - # op op_unused_3e FALLBACK - # op op_unused_3f FALLBACK - # op op_unused_40 FALLBACK - # op op_unused_41 FALLBACK - # op op_unused_42 FALLBACK - # op op_unused_43 FALLBACK - # op op_aget FALLBACK - # op op_aget_wide FALLBACK - # op op_aget_object FALLBACK - # op op_aget_boolean FALLBACK - # op op_aget_byte FALLBACK - # op op_aget_char FALLBACK - # op op_aget_short FALLBACK - # op op_aput FALLBACK - # op op_aput_wide FALLBACK - # op op_aput_object FALLBACK - # op op_aput_boolean FALLBACK - # op op_aput_byte FALLBACK - # op op_aput_char FALLBACK - # op op_aput_short FALLBACK - # op op_iget FALLBACK - # op op_iget_wide FALLBACK - # op op_iget_object FALLBACK - # op op_iget_boolean FALLBACK - # op op_iget_byte FALLBACK - # op op_iget_char FALLBACK - # op op_iget_short FALLBACK - # op op_iput FALLBACK - # op op_iput_wide FALLBACK - # op op_iput_object FALLBACK - # op op_iput_boolean FALLBACK - # op op_iput_byte FALLBACK - # op op_iput_char FALLBACK - # op op_iput_short FALLBACK - # op op_sget FALLBACK - # op op_sget_wide FALLBACK - # op op_sget_object FALLBACK - # op op_sget_boolean FALLBACK - # op op_sget_byte FALLBACK - # op op_sget_char FALLBACK - # op op_sget_short FALLBACK - # op op_sput FALLBACK - # op op_sput_wide FALLBACK - # op op_sput_object FALLBACK - # op op_sput_boolean FALLBACK - # op op_sput_byte FALLBACK - # op op_sput_char FALLBACK - # op op_sput_short FALLBACK - # op op_invoke_virtual FALLBACK - # op op_invoke_super FALLBACK - # op op_invoke_direct FALLBACK - # op op_invoke_static FALLBACK - # op op_invoke_interface FALLBACK - # op op_return_void_no_barrier FALLBACK - # op op_invoke_virtual_range FALLBACK - # op op_invoke_super_range FALLBACK - # op op_invoke_direct_range FALLBACK - # op op_invoke_static_range FALLBACK - # op op_invoke_interface_range FALLBACK - # op op_unused_79 FALLBACK - # op op_unused_7a FALLBACK - # op op_neg_int FALLBACK - # op op_not_int FALLBACK - # op op_neg_long FALLBACK - # op op_not_long FALLBACK - # op op_neg_float FALLBACK - # op op_neg_double FALLBACK - # op op_int_to_long FALLBACK - # op op_int_to_float FALLBACK - # op op_int_to_double FALLBACK - # op op_long_to_int FALLBACK - # op op_long_to_float FALLBACK - # op op_long_to_double FALLBACK - # op op_float_to_int FALLBACK - # op op_float_to_long FALLBACK - # op op_float_to_double FALLBACK - # op op_double_to_int FALLBACK - # op op_double_to_long FALLBACK - # op op_double_to_float FALLBACK - # op op_int_to_byte FALLBACK - # op op_int_to_char FALLBACK - # op op_int_to_short FALLBACK - # op op_add_int FALLBACK - # op op_sub_int FALLBACK - # op op_mul_int FALLBACK - # op op_div_int FALLBACK - # op op_rem_int FALLBACK - # op op_and_int FALLBACK - # op op_or_int FALLBACK - # op op_xor_int FALLBACK - # op op_shl_int FALLBACK - # op op_shr_int FALLBACK - # op op_ushr_int FALLBACK - # op op_add_long FALLBACK - # op op_sub_long FALLBACK - # op op_mul_long FALLBACK - # op op_div_long FALLBACK - # op op_rem_long FALLBACK - # op op_and_long FALLBACK - # op op_or_long FALLBACK - # op op_xor_long FALLBACK - # op op_shl_long FALLBACK - # op op_shr_long FALLBACK - # op op_ushr_long FALLBACK - # op op_add_float FALLBACK - # op op_sub_float FALLBACK - # op op_mul_float FALLBACK - # op op_div_float FALLBACK - # op op_rem_float FALLBACK - # op op_add_double FALLBACK - # op op_sub_double FALLBACK - # op op_mul_double FALLBACK - # op op_div_double FALLBACK - # op op_rem_double FALLBACK - # op op_add_int_2addr FALLBACK - # op op_sub_int_2addr FALLBACK - # op op_mul_int_2addr FALLBACK - # op op_div_int_2addr FALLBACK - # op op_rem_int_2addr FALLBACK - # op op_and_int_2addr FALLBACK - # op op_or_int_2addr FALLBACK - # op op_xor_int_2addr FALLBACK - # op op_shl_int_2addr FALLBACK - # op op_shr_int_2addr FALLBACK - # op op_ushr_int_2addr FALLBACK - # op op_add_long_2addr FALLBACK - # op op_sub_long_2addr FALLBACK - # op op_mul_long_2addr FALLBACK - # op op_div_long_2addr FALLBACK - # op op_rem_long_2addr FALLBACK - # op op_and_long_2addr FALLBACK - # op op_or_long_2addr FALLBACK - # op op_xor_long_2addr FALLBACK - # op op_shl_long_2addr FALLBACK - # op op_shr_long_2addr FALLBACK - # op op_ushr_long_2addr FALLBACK - # op op_add_float_2addr FALLBACK - # op op_sub_float_2addr FALLBACK - # op op_mul_float_2addr FALLBACK - # op op_div_float_2addr FALLBACK - # op op_rem_float_2addr FALLBACK - # op op_add_double_2addr FALLBACK - # op op_sub_double_2addr FALLBACK - # op op_mul_double_2addr FALLBACK - # op op_div_double_2addr FALLBACK - # op op_rem_double_2addr FALLBACK - # op op_add_int_lit16 FALLBACK - # op op_rsub_int FALLBACK - # op op_mul_int_lit16 FALLBACK - # op op_div_int_lit16 FALLBACK - # op op_rem_int_lit16 FALLBACK - # op op_and_int_lit16 FALLBACK - # op op_or_int_lit16 FALLBACK - # op op_xor_int_lit16 FALLBACK - # op op_add_int_lit8 FALLBACK - # op op_rsub_int_lit8 FALLBACK - # op op_mul_int_lit8 FALLBACK - # op op_div_int_lit8 FALLBACK - # op op_rem_int_lit8 FALLBACK - # op op_and_int_lit8 FALLBACK - # op op_or_int_lit8 FALLBACK - # op op_xor_int_lit8 FALLBACK - # op op_shl_int_lit8 FALLBACK - # op op_shr_int_lit8 FALLBACK - # op op_ushr_int_lit8 FALLBACK - # op op_iget_quick FALLBACK - # op op_iget_wide_quick FALLBACK - # op op_iget_object_quick FALLBACK - # op op_iput_quick FALLBACK - # op op_iput_wide_quick FALLBACK - # op op_iput_object_quick FALLBACK - # op op_invoke_virtual_quick FALLBACK - # op op_invoke_virtual_range_quick FALLBACK - # op op_iput_boolean_quick FALLBACK - # op op_iput_byte_quick FALLBACK - # op op_iput_char_quick FALLBACK - # op op_iput_short_quick FALLBACK - # op op_iget_boolean_quick FALLBACK - # op op_iget_byte_quick FALLBACK - # op op_iget_char_quick FALLBACK - # op op_iget_short_quick FALLBACK - # op op_unused_f3 FALLBACK - # op op_unused_f4 FALLBACK - # op op_unused_f5 FALLBACK - # op op_unused_f6 FALLBACK - # op op_unused_f7 FALLBACK - # op op_unused_f8 FALLBACK - # op op_unused_f9 FALLBACK - # op op_invoke_polymorphic FALLBACK - # op op_invoke_polymorphic_range FALLBACK - # op op_invoke_custom FALLBACK - # op op_invoke_custom_range FALLBACK - # op op_const_method_handle FALLBACK - # op op_const_method_type FALLBACK -op-end - -# common subroutines for asm -import mips64/footer.S diff --git a/runtime/interpreter/mterp/config_x86 b/runtime/interpreter/mterp/config_x86 deleted file mode 100644 index 2417851c11..0000000000 --- a/runtime/interpreter/mterp/config_x86 +++ /dev/null @@ -1,302 +0,0 @@ -# Copyright (C) 2015 The Android Open Source Project -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -# -# Configuration for X86 -# - -handler-style computed-goto -handler-size 128 - -function-type-format FUNCTION_TYPE(%s) -function-size-format SIZE(%s,%s) -global-name-format SYMBOL(%s) - -# source for alternate entry stub -asm-alt-stub x86/alt_stub.S - -# file header and basic definitions -import x86/header.S - -# arch-specific entry point to interpreter -import x86/entry.S - -# Stub to switch to alternate interpreter -fallback-stub x86/fallback.S - -# opcode list; argument to op-start is default directory -op-start x86 - # (override example:) op OP_SUB_FLOAT_2ADDR arm-vfp - # (fallback example:) op OP_SUB_FLOAT_2ADDR FALLBACK - - # op op_nop FALLBACK - # op op_move FALLBACK - # op op_move_from16 FALLBACK - # op op_move_16 FALLBACK - # op op_move_wide FALLBACK - # op op_move_wide_from16 FALLBACK - # op op_move_wide_16 FALLBACK - # op op_move_object FALLBACK - # op op_move_object_from16 FALLBACK - # op op_move_object_16 FALLBACK - # op op_move_result FALLBACK - # op op_move_result_wide FALLBACK - # op op_move_result_object FALLBACK - # op op_move_exception FALLBACK - # op op_return_void FALLBACK - # op op_return FALLBACK - # op op_return_wide FALLBACK - # op op_return_object FALLBACK - # op op_const_4 FALLBACK - # op op_const_16 FALLBACK - # op op_const FALLBACK - # op op_const_high16 FALLBACK - # op op_const_wide_16 FALLBACK - # op op_const_wide_32 FALLBACK - # op op_const_wide FALLBACK - # op op_const_wide_high16 FALLBACK - # op op_const_string FALLBACK - # op op_const_string_jumbo FALLBACK - # op op_const_class FALLBACK - # op op_monitor_enter FALLBACK - # op op_monitor_exit FALLBACK - # op op_check_cast FALLBACK - # op op_instance_of FALLBACK - # op op_array_length FALLBACK - # op op_new_instance FALLBACK - # op op_new_array FALLBACK - # op op_filled_new_array FALLBACK - # op op_filled_new_array_range FALLBACK - # op op_fill_array_data FALLBACK - # op op_throw FALLBACK - # op op_goto FALLBACK - # op op_goto_16 FALLBACK - # op op_goto_32 FALLBACK - # op op_packed_switch FALLBACK - # op op_sparse_switch FALLBACK - # op op_cmpl_float FALLBACK - # op op_cmpg_float FALLBACK - # op op_cmpl_double FALLBACK - # op op_cmpg_double FALLBACK - # op op_cmp_long FALLBACK - # op op_if_eq FALLBACK - # op op_if_ne FALLBACK - # op op_if_lt FALLBACK - # op op_if_ge FALLBACK - # op op_if_gt FALLBACK - # op op_if_le FALLBACK - # op op_if_eqz FALLBACK - # op op_if_nez FALLBACK - # op op_if_ltz FALLBACK - # op op_if_gez FALLBACK - # op op_if_gtz FALLBACK - # op op_if_lez FALLBACK - # op op_unused_3e FALLBACK - # op op_unused_3f FALLBACK - # op op_unused_40 FALLBACK - # op op_unused_41 FALLBACK - # op op_unused_42 FALLBACK - # op op_unused_43 FALLBACK - # op op_aget FALLBACK - # op op_aget_wide FALLBACK - # op op_aget_object FALLBACK - # op op_aget_boolean FALLBACK - # op op_aget_byte FALLBACK - # op op_aget_char FALLBACK - # op op_aget_short FALLBACK - # op op_aput FALLBACK - # op op_aput_wide FALLBACK - # op op_aput_object FALLBACK - # op op_aput_boolean FALLBACK - # op op_aput_byte FALLBACK - # op op_aput_char FALLBACK - # op op_aput_short FALLBACK - # op op_iget FALLBACK - # op op_iget_wide FALLBACK - # op op_iget_object FALLBACK - # op op_iget_boolean FALLBACK - # op op_iget_byte FALLBACK - # op op_iget_char FALLBACK - # op op_iget_short FALLBACK - # op op_iput FALLBACK - # op op_iput_wide FALLBACK - # op op_iput_object FALLBACK - # op op_iput_boolean FALLBACK - # op op_iput_byte FALLBACK - # op op_iput_char FALLBACK - # op op_iput_short FALLBACK - # op op_sget FALLBACK - # op op_sget_wide FALLBACK - # op op_sget_object FALLBACK - # op op_sget_boolean FALLBACK - # op op_sget_byte FALLBACK - # op op_sget_char FALLBACK - # op op_sget_short FALLBACK - # op op_sput FALLBACK - # op op_sput_wide FALLBACK - # op op_sput_object FALLBACK - # op op_sput_boolean FALLBACK - # op op_sput_byte FALLBACK - # op op_sput_char FALLBACK - # op op_sput_short FALLBACK - # op op_invoke_virtual FALLBACK - # op op_invoke_super FALLBACK - # op op_invoke_direct FALLBACK - # op op_invoke_static FALLBACK - # op op_invoke_interface FALLBACK - # op op_return_void_no_barrier FALLBACK - # op op_invoke_virtual_range FALLBACK - # op op_invoke_super_range FALLBACK - # op op_invoke_direct_range FALLBACK - # op op_invoke_static_range FALLBACK - # op op_invoke_interface_range FALLBACK - # op op_unused_79 FALLBACK - # op op_unused_7a FALLBACK - # op op_neg_int FALLBACK - # op op_not_int FALLBACK - # op op_neg_long FALLBACK - # op op_not_long FALLBACK - # op op_neg_float FALLBACK - # op op_neg_double FALLBACK - # op op_int_to_long FALLBACK - # op op_int_to_float FALLBACK - # op op_int_to_double FALLBACK - # op op_long_to_int FALLBACK - # op op_long_to_float FALLBACK - # op op_long_to_double FALLBACK - # op op_float_to_int FALLBACK - # op op_float_to_long FALLBACK - # op op_float_to_double FALLBACK - # op op_double_to_int FALLBACK - # op op_double_to_long FALLBACK - # op op_double_to_float FALLBACK - # op op_int_to_byte FALLBACK - # op op_int_to_char FALLBACK - # op op_int_to_short FALLBACK - # op op_add_int FALLBACK - # op op_sub_int FALLBACK - # op op_mul_int FALLBACK - # op op_div_int FALLBACK - # op op_rem_int FALLBACK - # op op_and_int FALLBACK - # op op_or_int FALLBACK - # op op_xor_int FALLBACK - # op op_shl_int FALLBACK - # op op_shr_int FALLBACK - # op op_ushr_int FALLBACK - # op op_add_long FALLBACK - # op op_sub_long FALLBACK - # op op_mul_long FALLBACK - # op op_div_long FALLBACK - # op op_rem_long FALLBACK - # op op_and_long FALLBACK - # op op_or_long FALLBACK - # op op_xor_long FALLBACK - # op op_shl_long FALLBACK - # op op_shr_long FALLBACK - # op op_ushr_long FALLBACK - # op op_add_float FALLBACK - # op op_sub_float FALLBACK - # op op_mul_float FALLBACK - # op op_div_float FALLBACK - # op op_rem_float FALLBACK - # op op_add_double FALLBACK - # op op_sub_double FALLBACK - # op op_mul_double FALLBACK - # op op_div_double FALLBACK - # op op_rem_double FALLBACK - # op op_add_int_2addr FALLBACK - # op op_sub_int_2addr FALLBACK - # op op_mul_int_2addr FALLBACK - # op op_div_int_2addr FALLBACK - # op op_rem_int_2addr FALLBACK - # op op_and_int_2addr FALLBACK - # op op_or_int_2addr FALLBACK - # op op_xor_int_2addr FALLBACK - # op op_shl_int_2addr FALLBACK - # op op_shr_int_2addr FALLBACK - # op op_ushr_int_2addr FALLBACK - # op op_add_long_2addr FALLBACK - # op op_sub_long_2addr FALLBACK - # op op_mul_long_2addr FALLBACK - # op op_div_long_2addr FALLBACK - # op op_rem_long_2addr FALLBACK - # op op_and_long_2addr FALLBACK - # op op_or_long_2addr FALLBACK - # op op_xor_long_2addr FALLBACK - # op op_shl_long_2addr FALLBACK - # op op_shr_long_2addr FALLBACK - # op op_ushr_long_2addr FALLBACK - # op op_add_float_2addr FALLBACK - # op op_sub_float_2addr FALLBACK - # op op_mul_float_2addr FALLBACK - # op op_div_float_2addr FALLBACK - # op op_rem_float_2addr FALLBACK - # op op_add_double_2addr FALLBACK - # op op_sub_double_2addr FALLBACK - # op op_mul_double_2addr FALLBACK - # op op_div_double_2addr FALLBACK - # op op_rem_double_2addr FALLBACK - # op op_add_int_lit16 FALLBACK - # op op_rsub_int FALLBACK - # op op_mul_int_lit16 FALLBACK - # op op_div_int_lit16 FALLBACK - # op op_rem_int_lit16 FALLBACK - # op op_and_int_lit16 FALLBACK - # op op_or_int_lit16 FALLBACK - # op op_xor_int_lit16 FALLBACK - # op op_add_int_lit8 FALLBACK - # op op_rsub_int_lit8 FALLBACK - # op op_mul_int_lit8 FALLBACK - # op op_div_int_lit8 FALLBACK - # op op_rem_int_lit8 FALLBACK - # op op_and_int_lit8 FALLBACK - # op op_or_int_lit8 FALLBACK - # op op_xor_int_lit8 FALLBACK - # op op_shl_int_lit8 FALLBACK - # op op_shr_int_lit8 FALLBACK - # op op_ushr_int_lit8 FALLBACK - # op op_iget_quick FALLBACK - # op op_iget_wide_quick FALLBACK - # op op_iget_object_quick FALLBACK - # op op_iput_quick FALLBACK - # op op_iput_wide_quick FALLBACK - # op op_iput_object_quick FALLBACK - # op op_invoke_virtual_quick FALLBACK - # op op_invoke_virtual_range_quick FALLBACK - # op op_iput_boolean_quick FALLBACK - # op op_iput_byte_quick FALLBACK - # op op_iput_char_quick FALLBACK - # op op_iput_short_quick FALLBACK - # op op_iget_boolean_quick FALLBACK - # op op_iget_byte_quick FALLBACK - # op op_iget_char_quick FALLBACK - # op op_iget_short_quick FALLBACK - # op op_unused_f3 FALLBACK - # op op_unused_f4 FALLBACK - # op op_unused_f5 FALLBACK - # op op_unused_f6 FALLBACK - # op op_unused_f7 FALLBACK - # op op_unused_f8 FALLBACK - # op op_unused_f9 FALLBACK - # op op_invoke_polymorphic FALLBACK - # op op_invoke_polymorphic_range FALLBACK - # op op_invoke_custom FALLBACK - # op op_invoke_custom_range FALLBACK - # op op_const_method_handle FALLBACK - # op op_const_method_type FALLBACK -op-end - -# common subroutines for asm -import x86/footer.S diff --git a/runtime/interpreter/mterp/config_x86_64 b/runtime/interpreter/mterp/config_x86_64 deleted file mode 100644 index 89fbf43444..0000000000 --- a/runtime/interpreter/mterp/config_x86_64 +++ /dev/null @@ -1,302 +0,0 @@ -# Copyright (C) 2015 The Android Open Source Project -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -# -# Configuration for X86_64 -# - -handler-style computed-goto -handler-size 128 - -function-type-format FUNCTION_TYPE(%s) -function-size-format SIZE(%s,%s) -global-name-format SYMBOL(%s) - -# source for alternate entry stub -asm-alt-stub x86_64/alt_stub.S - -# file header and basic definitions -import x86_64/header.S - -# arch-specific entry point to interpreter -import x86_64/entry.S - -# Stub to switch to alternate interpreter -fallback-stub x86_64/fallback.S - -# opcode list; argument to op-start is default directory -op-start x86_64 - # (override example:) op OP_SUB_FLOAT_2ADDR arm-vfp - # (fallback example:) op OP_SUB_FLOAT_2ADDR FALLBACK - - # op op_nop FALLBACK - # op op_move FALLBACK - # op op_move_from16 FALLBACK - # op op_move_16 FALLBACK - # op op_move_wide FALLBACK - # op op_move_wide_from16 FALLBACK - # op op_move_wide_16 FALLBACK - # op op_move_object FALLBACK - # op op_move_object_from16 FALLBACK - # op op_move_object_16 FALLBACK - # op op_move_result FALLBACK - # op op_move_result_wide FALLBACK - # op op_move_result_object FALLBACK - # op op_move_exception FALLBACK - # op op_return_void FALLBACK - # op op_return FALLBACK - # op op_return_wide FALLBACK - # op op_return_object FALLBACK - # op op_const_4 FALLBACK - # op op_const_16 FALLBACK - # op op_const FALLBACK - # op op_const_high16 FALLBACK - # op op_const_wide_16 FALLBACK - # op op_const_wide_32 FALLBACK - # op op_const_wide FALLBACK - # op op_const_wide_high16 FALLBACK - # op op_const_string FALLBACK - # op op_const_string_jumbo FALLBACK - # op op_const_class FALLBACK - # op op_monitor_enter FALLBACK - # op op_monitor_exit FALLBACK - # op op_check_cast FALLBACK - # op op_instance_of FALLBACK - # op op_array_length FALLBACK - # op op_new_instance FALLBACK - # op op_new_array FALLBACK - # op op_filled_new_array FALLBACK - # op op_filled_new_array_range FALLBACK - # op op_fill_array_data FALLBACK - # op op_throw FALLBACK - # op op_goto FALLBACK - # op op_goto_16 FALLBACK - # op op_goto_32 FALLBACK - # op op_packed_switch FALLBACK - # op op_sparse_switch FALLBACK - # op op_cmpl_float FALLBACK - # op op_cmpg_float FALLBACK - # op op_cmpl_double FALLBACK - # op op_cmpg_double FALLBACK - # op op_cmp_long FALLBACK - # op op_if_eq FALLBACK - # op op_if_ne FALLBACK - # op op_if_lt FALLBACK - # op op_if_ge FALLBACK - # op op_if_gt FALLBACK - # op op_if_le FALLBACK - # op op_if_eqz FALLBACK - # op op_if_nez FALLBACK - # op op_if_ltz FALLBACK - # op op_if_gez FALLBACK - # op op_if_gtz FALLBACK - # op op_if_lez FALLBACK - # op op_unused_3e FALLBACK - # op op_unused_3f FALLBACK - # op op_unused_40 FALLBACK - # op op_unused_41 FALLBACK - # op op_unused_42 FALLBACK - # op op_unused_43 FALLBACK - # op op_aget FALLBACK - # op op_aget_wide FALLBACK - # op op_aget_object FALLBACK - # op op_aget_boolean FALLBACK - # op op_aget_byte FALLBACK - # op op_aget_char FALLBACK - # op op_aget_short FALLBACK - # op op_aput FALLBACK - # op op_aput_wide FALLBACK - # op op_aput_object FALLBACK - # op op_aput_boolean FALLBACK - # op op_aput_byte FALLBACK - # op op_aput_char FALLBACK - # op op_aput_short FALLBACK - # op op_iget FALLBACK - # op op_iget_wide FALLBACK - # op op_iget_object FALLBACK - # op op_iget_boolean FALLBACK - # op op_iget_byte FALLBACK - # op op_iget_char FALLBACK - # op op_iget_short FALLBACK - # op op_iput FALLBACK - # op op_iput_wide FALLBACK - # op op_iput_object FALLBACK - # op op_iput_boolean FALLBACK - # op op_iput_byte FALLBACK - # op op_iput_char FALLBACK - # op op_iput_short FALLBACK - # op op_sget FALLBACK - # op op_sget_wide FALLBACK - # op op_sget_object FALLBACK - # op op_sget_boolean FALLBACK - # op op_sget_byte FALLBACK - # op op_sget_char FALLBACK - # op op_sget_short FALLBACK - # op op_sput FALLBACK - # op op_sput_wide FALLBACK - # op op_sput_object FALLBACK - # op op_sput_boolean FALLBACK - # op op_sput_byte FALLBACK - # op op_sput_char FALLBACK - # op op_sput_short FALLBACK - # op op_invoke_virtual FALLBACK - # op op_invoke_super FALLBACK - # op op_invoke_direct FALLBACK - # op op_invoke_static FALLBACK - # op op_invoke_interface FALLBACK - # op op_return_void_no_barrier FALLBACK - # op op_invoke_virtual_range FALLBACK - # op op_invoke_super_range FALLBACK - # op op_invoke_direct_range FALLBACK - # op op_invoke_static_range FALLBACK - # op op_invoke_interface_range FALLBACK - # op op_unused_79 FALLBACK - # op op_unused_7a FALLBACK - # op op_neg_int FALLBACK - # op op_not_int FALLBACK - # op op_neg_long FALLBACK - # op op_not_long FALLBACK - # op op_neg_float FALLBACK - # op op_neg_double FALLBACK - # op op_int_to_long FALLBACK - # op op_int_to_float FALLBACK - # op op_int_to_double FALLBACK - # op op_long_to_int FALLBACK - # op op_long_to_float FALLBACK - # op op_long_to_double FALLBACK - # op op_float_to_int FALLBACK - # op op_float_to_long FALLBACK - # op op_float_to_double FALLBACK - # op op_double_to_int FALLBACK - # op op_double_to_long FALLBACK - # op op_double_to_float FALLBACK - # op op_int_to_byte FALLBACK - # op op_int_to_char FALLBACK - # op op_int_to_short FALLBACK - # op op_add_int FALLBACK - # op op_sub_int FALLBACK - # op op_mul_int FALLBACK - # op op_div_int FALLBACK - # op op_rem_int FALLBACK - # op op_and_int FALLBACK - # op op_or_int FALLBACK - # op op_xor_int FALLBACK - # op op_shl_int FALLBACK - # op op_shr_int FALLBACK - # op op_ushr_int FALLBACK - # op op_add_long FALLBACK - # op op_sub_long FALLBACK - # op op_mul_long FALLBACK - # op op_div_long FALLBACK - # op op_rem_long FALLBACK - # op op_and_long FALLBACK - # op op_or_long FALLBACK - # op op_xor_long FALLBACK - # op op_shl_long FALLBACK - # op op_shr_long FALLBACK - # op op_ushr_long FALLBACK - # op op_add_float FALLBACK - # op op_sub_float FALLBACK - # op op_mul_float FALLBACK - # op op_div_float FALLBACK - # op op_rem_float FALLBACK - # op op_add_double FALLBACK - # op op_sub_double FALLBACK - # op op_mul_double FALLBACK - # op op_div_double FALLBACK - # op op_rem_double FALLBACK - # op op_add_int_2addr FALLBACK - # op op_sub_int_2addr FALLBACK - # op op_mul_int_2addr FALLBACK - # op op_div_int_2addr FALLBACK - # op op_rem_int_2addr FALLBACK - # op op_and_int_2addr FALLBACK - # op op_or_int_2addr FALLBACK - # op op_xor_int_2addr FALLBACK - # op op_shl_int_2addr FALLBACK - # op op_shr_int_2addr FALLBACK - # op op_ushr_int_2addr FALLBACK - # op op_add_long_2addr FALLBACK - # op op_sub_long_2addr FALLBACK - # op op_mul_long_2addr FALLBACK - # op op_div_long_2addr FALLBACK - # op op_rem_long_2addr FALLBACK - # op op_and_long_2addr FALLBACK - # op op_or_long_2addr FALLBACK - # op op_xor_long_2addr FALLBACK - # op op_shl_long_2addr FALLBACK - # op op_shr_long_2addr FALLBACK - # op op_ushr_long_2addr FALLBACK - # op op_add_float_2addr FALLBACK - # op op_sub_float_2addr FALLBACK - # op op_mul_float_2addr FALLBACK - # op op_div_float_2addr FALLBACK - # op op_rem_float_2addr FALLBACK - # op op_add_double_2addr FALLBACK - # op op_sub_double_2addr FALLBACK - # op op_mul_double_2addr FALLBACK - # op op_div_double_2addr FALLBACK - # op op_rem_double_2addr FALLBACK - # op op_add_int_lit16 FALLBACK - # op op_rsub_int FALLBACK - # op op_mul_int_lit16 FALLBACK - # op op_div_int_lit16 FALLBACK - # op op_rem_int_lit16 FALLBACK - # op op_and_int_lit16 FALLBACK - # op op_or_int_lit16 FALLBACK - # op op_xor_int_lit16 FALLBACK - # op op_add_int_lit8 FALLBACK - # op op_rsub_int_lit8 FALLBACK - # op op_mul_int_lit8 FALLBACK - # op op_div_int_lit8 FALLBACK - # op op_rem_int_lit8 FALLBACK - # op op_and_int_lit8 FALLBACK - # op op_or_int_lit8 FALLBACK - # op op_xor_int_lit8 FALLBACK - # op op_shl_int_lit8 FALLBACK - # op op_shr_int_lit8 FALLBACK - # op op_ushr_int_lit8 FALLBACK - # op op_iget_quick FALLBACK - # op op_iget_wide_quick FALLBACK - # op op_iget_object_quick FALLBACK - # op op_iput_quick FALLBACK - # op op_iput_wide_quick FALLBACK - # op op_iput_object_quick FALLBACK - # op op_invoke_virtual_quick FALLBACK - # op op_invoke_virtual_range_quick FALLBACK - # op op_iput_boolean_quick FALLBACK - # op op_iput_byte_quick FALLBACK - # op op_iput_char_quick FALLBACK - # op op_iput_short_quick FALLBACK - # op op_iget_boolean_quick FALLBACK - # op op_iget_byte_quick FALLBACK - # op op_iget_char_quick FALLBACK - # op op_iget_short_quick FALLBACK - # op op_unused_f3 FALLBACK - # op op_unused_f4 FALLBACK - # op op_unused_f5 FALLBACK - # op op_unused_f6 FALLBACK - # op op_unused_f7 FALLBACK - # op op_unused_f8 FALLBACK - # op op_unused_f9 FALLBACK - # op op_invoke_polymorphic FALLBACK - # op op_invoke_polymorphic_range FALLBACK - # op op_invoke_custom FALLBACK - # op op_invoke_custom_range FALLBACK - # op op_const_method_handle FALLBACK - # op op_const_method_type FALLBACK -op-end - -# common subroutines for asm -import x86_64/footer.S diff --git a/runtime/interpreter/mterp/gen_mterp.py b/runtime/interpreter/mterp/gen_mterp.py index 75c5174bcb..cf69bcecc3 100755 --- a/runtime/interpreter/mterp/gen_mterp.py +++ b/runtime/interpreter/mterp/gen_mterp.py @@ -14,605 +14,108 @@ # See the License for the specific language governing permissions and # limitations under the License. -# -# Using instructions from an architecture-specific config file, generate C -# and assembly source files for the Dalvik interpreter. -# - -import sys, string, re, time -from string import Template - -interp_defs_file = "../../../libdexfile/dex/dex_instruction_list.h" # need opcode list -kNumPackedOpcodes = 256 - -splitops = False -verbose = False -handler_size_bits = -1000 -handler_size_bytes = -1000 -in_op_start = 0 # 0=not started, 1=started, 2=ended -in_alt_op_start = 0 # 0=not started, 1=started, 2=ended -default_op_dir = None -default_alt_stub = None -opcode_locations = {} -alt_opcode_locations = {} -asm_stub_text = [] -fallback_stub_text = [] -label_prefix = ".L" # use ".L" to hide labels from gdb -alt_label_prefix = ".L_ALT" # use ".L" to hide labels from gdb -style = None # interpreter style -generate_alt_table = False -function_type_format = ".type %s, %%function" -function_size_format = ".size %s, .-%s" -global_name_format = "%s" - -# Exception class. -class DataParseError(SyntaxError): - "Failure when parsing data file" - -# -# Set any omnipresent substitution values. -# -def getGlobalSubDict(): - return { "handler_size_bits":handler_size_bits, - "handler_size_bytes":handler_size_bytes } - -# -# Parse arch config file -- -# Set interpreter style. -# -def setHandlerStyle(tokens): - global style - if len(tokens) != 2: - raise DataParseError("handler-style requires one argument") - style = tokens[1] - if style != "computed-goto": - raise DataParseError("handler-style (%s) invalid" % style) - -# -# Parse arch config file -- -# Set handler_size_bytes to the value of tokens[1], and handler_size_bits to -# log2(handler_size_bytes). Throws an exception if "bytes" is not 0 or -# a power of two. -# -def setHandlerSize(tokens): - global handler_size_bits, handler_size_bytes - if style != "computed-goto": - print "Warning: handler-size valid only for computed-goto interpreters" - if len(tokens) != 2: - raise DataParseError("handler-size requires one argument") - if handler_size_bits != -1000: - raise DataParseError("handler-size may only be set once") - - # compute log2(n), and make sure n is 0 or a power of 2 - handler_size_bytes = bytes = int(tokens[1]) - bits = -1 - while bytes > 0: - bytes //= 2 # halve with truncating division - bits += 1 - - if handler_size_bytes == 0 or handler_size_bytes != (1 << bits): - raise DataParseError("handler-size (%d) must be power of 2" \ - % orig_bytes) - handler_size_bits = bits - -# -# Parse arch config file -- -# Copy a file in to asm output file. -# -def importFile(tokens): - if len(tokens) != 2: - raise DataParseError("import requires one argument") - source = tokens[1] - if source.endswith(".S"): - appendSourceFile(tokens[1], getGlobalSubDict(), asm_fp, None) - else: - raise DataParseError("don't know how to import %s (expecting .cpp/.S)" - % source) - -# -# Parse arch config file -- -# Copy a file in to the C or asm output file. -# -def setAsmStub(tokens): - global asm_stub_text - if len(tokens) != 2: - raise DataParseError("import requires one argument") - try: - stub_fp = open(tokens[1]) - asm_stub_text = stub_fp.readlines() - except IOError, err: - stub_fp.close() - raise DataParseError("unable to load asm-stub: %s" % str(err)) - stub_fp.close() - -# -# Parse arch config file -- -# Copy a file in to the C or asm output file. -# -def setFallbackStub(tokens): - global fallback_stub_text - if len(tokens) != 2: - raise DataParseError("import requires one argument") - try: - stub_fp = open(tokens[1]) - fallback_stub_text = stub_fp.readlines() - except IOError, err: - stub_fp.close() - raise DataParseError("unable to load fallback-stub: %s" % str(err)) - stub_fp.close() -# -# Parse arch config file -- -# Record location of default alt stub -# -def setAsmAltStub(tokens): - global default_alt_stub, generate_alt_table - if len(tokens) != 2: - raise DataParseError("import requires one argument") - default_alt_stub = tokens[1] - generate_alt_table = True -# -# Change the default function type format -# -def setFunctionTypeFormat(tokens): - global function_type_format - function_type_format = tokens[1] -# -# Change the default function size format -# -def setFunctionSizeFormat(tokens): - global function_size_format - function_size_format = tokens[1] -# -# Change the global name format -# -def setGlobalNameFormat(tokens): - global global_name_format - global_name_format = tokens[1] -# -# Parse arch config file -- -# Start of opcode list. -# -def opStart(tokens): - global in_op_start - global default_op_dir - if len(tokens) != 2: - raise DataParseError("opStart takes a directory name argument") - if in_op_start != 0: - raise DataParseError("opStart can only be specified once") - default_op_dir = tokens[1] - in_op_start = 1 +import sys, re +from os import listdir +from cStringIO import StringIO -# -# Parse arch config file -- -# Set location of a single alt opcode's source file. -# -def altEntry(tokens): - global generate_alt_table - if len(tokens) != 3: - raise DataParseError("alt requires exactly two arguments") - if in_op_start != 1: - raise DataParseError("alt statements must be between opStart/opEnd") - try: - index = opcodes.index(tokens[1]) - except ValueError: - raise DataParseError("unknown opcode %s" % tokens[1]) - if alt_opcode_locations.has_key(tokens[1]): - print "Note: alt overrides earlier %s (%s -> %s)" \ - % (tokens[1], alt_opcode_locations[tokens[1]], tokens[2]) - alt_opcode_locations[tokens[1]] = tokens[2] - generate_alt_table = True +# This file is included verbatim at the start of the in-memory python script. +SCRIPT_SETUP_CODE = "common/gen_setup.py" -# -# Parse arch config file -- -# Set location of a single opcode's source file. -# -def opEntry(tokens): - #global opcode_locations - if len(tokens) != 3: - raise DataParseError("op requires exactly two arguments") - if in_op_start != 1: - raise DataParseError("op statements must be between opStart/opEnd") - try: - index = opcodes.index(tokens[1]) - except ValueError: - raise DataParseError("unknown opcode %s" % tokens[1]) - if opcode_locations.has_key(tokens[1]): - print "Note: op overrides earlier %s (%s -> %s)" \ - % (tokens[1], opcode_locations[tokens[1]], tokens[2]) - opcode_locations[tokens[1]] = tokens[2] +INTERP_DEFS_FILE = "../../../libdexfile/dex/dex_instruction_list.h" # need opcode list +NUM_PACKED_OPCODES = 256 -# -# Parse arch config file -- -# End of opcode list; emit instruction blocks. -# -def opEnd(tokens): - global in_op_start - if len(tokens) != 1: - raise DataParseError("opEnd takes no arguments") - if in_op_start != 1: - raise DataParseError("opEnd must follow opStart, and only appear once") - in_op_start = 2 - - loadAndEmitOpcodes() - if splitops == False: - if generate_alt_table: - loadAndEmitAltOpcodes() - -def genaltop(tokens): - if in_op_start != 2: - raise DataParseError("alt-op can be specified only after op-end") - if len(tokens) != 1: - raise DataParseError("opEnd takes no arguments") - if generate_alt_table: - loadAndEmitAltOpcodes() - -# # Extract an ordered list of instructions from the VM sources. We use the -# "goto table" definition macro, which has exactly kNumPackedOpcodes -# entries. -# +# "goto table" definition macro, which has exactly NUM_PACKED_OPCODES entries. def getOpcodeList(): - opcodes = [] - opcode_fp = open(interp_defs_file) - opcode_re = re.compile(r"^\s*V\((....), (\w+),.*", re.DOTALL) - for line in opcode_fp: - match = opcode_re.match(line) - if not match: - continue - opcodes.append("op_" + match.group(2).lower()) - opcode_fp.close() - - if len(opcodes) != kNumPackedOpcodes: - print "ERROR: found %d opcodes in Interp.h (expected %d)" \ - % (len(opcodes), kNumPackedOpcodes) - raise SyntaxError, "bad opcode count" - return opcodes - -def emitAlign(): - if style == "computed-goto": - asm_fp.write(" .balign %d\n" % handler_size_bytes) - -# -# Load and emit opcodes for all kNumPackedOpcodes instructions. -# -def loadAndEmitOpcodes(): - sister_list = [] - assert len(opcodes) == kNumPackedOpcodes - need_dummy_start = False - - loadAndEmitGenericAsm("instruction_start") - - for i in xrange(kNumPackedOpcodes): - op = opcodes[i] - - if opcode_locations.has_key(op): - location = opcode_locations[op] - else: - location = default_op_dir - - if location == "FALLBACK": - emitFallback(i) - else: - loadAndEmitAsm(location, i, sister_list) - - # For a 100% C implementation, there are no asm handlers or stubs. We - # need to have the MterpAsmInstructionStart label point at op_nop, and it's - # too annoying to try to slide it in after the alignment psuedo-op, so - # we take the low road and just emit a dummy op_nop here. - if need_dummy_start: - emitAlign() - asm_fp.write(label_prefix + "_op_nop: /* dummy */\n"); - - emitAlign() - - loadAndEmitGenericAsm("instruction_end") - - if style == "computed-goto": - emitSectionComment("Sister implementations", asm_fp) - loadAndEmitGenericAsm("instruction_start_sister") - asm_fp.writelines(sister_list) - loadAndEmitGenericAsm("instruction_end_sister") - -# -# Load an alternate entry stub -# -def loadAndEmitAltStub(source, opindex): - op = opcodes[opindex] - if verbose: - print " alt emit %s --> stub" % source - dict = getGlobalSubDict() - dict.update({ "opcode":op, "opnum":opindex }) - - emitAsmHeader(asm_fp, dict, alt_label_prefix) - appendSourceFile(source, dict, asm_fp, None) - -# -# Load and emit alternate opcodes for all kNumPackedOpcodes instructions. -# -def loadAndEmitAltOpcodes(): - assert len(opcodes) == kNumPackedOpcodes - start_label = global_name_format % "artMterpAsmAltInstructionStart" - end_label = global_name_format % "artMterpAsmAltInstructionEnd" - - loadAndEmitGenericAsm("instruction_start_alt") - - for i in xrange(kNumPackedOpcodes): - op = opcodes[i] - if alt_opcode_locations.has_key(op): - source = "%s/alt_%s.S" % (alt_opcode_locations[op], op) - else: - source = default_alt_stub - loadAndEmitAltStub(source, i) - - emitAlign() - - loadAndEmitGenericAsm("instruction_end_alt") - -# -# Load an assembly fragment and emit it. -# -def loadAndEmitAsm(location, opindex, sister_list): - op = opcodes[opindex] - source = "%s/%s.S" % (location, op) - dict = getGlobalSubDict() - dict.update({ "opcode":op, "opnum":opindex }) - if verbose: - print " emit %s --> asm" % source - - emitAsmHeader(asm_fp, dict, label_prefix) - appendSourceFile(source, dict, asm_fp, sister_list) - -# -# Load a non-handler assembly fragment and emit it. -# -def loadAndEmitGenericAsm(name): - source = "%s/%s.S" % (default_op_dir, name) - dict = getGlobalSubDict() - appendSourceFile(source, dict, asm_fp, None) - -# -# Emit fallback fragment -# -def emitFallback(opindex): - op = opcodes[opindex] - dict = getGlobalSubDict() - dict.update({ "opcode":op, "opnum":opindex }) - emitAsmHeader(asm_fp, dict, label_prefix) - for line in fallback_stub_text: - asm_fp.write(line) - asm_fp.write("\n") - -# -# Output the alignment directive and label for an assembly piece. -# -def emitAsmHeader(outfp, dict, prefix): - outfp.write("/* ------------------------------ */\n") - # The alignment directive ensures that the handler occupies - # at least the correct amount of space. We don't try to deal - # with overflow here. - emitAlign() - # Emit a label so that gdb will say the right thing. We prepend an - # underscore so the symbol name doesn't clash with the Opcode enum. - outfp.write(prefix + "_%(opcode)s: /* 0x%(opnum)02x */\n" % dict) - -# -# Output a generic instruction stub that updates the "glue" struct and -# calls the C implementation. -# -def emitAsmStub(outfp, dict): - emitAsmHeader(outfp, dict, label_prefix) - for line in asm_stub_text: - templ = Template(line) - outfp.write(templ.substitute(dict)) - -# -# Append the file specified by "source" to the open "outfp". Each line will -# be template-replaced using the substitution dictionary "dict". -# -# If the first line of the file starts with "%" it is taken as a directive. -# A "%include" line contains a filename and, optionally, a Python-style -# dictionary declaration with substitution strings. (This is implemented -# with recursion.) -# -# If "sister_list" is provided, and we find a line that contains only "&", -# all subsequent lines from the file will be appended to sister_list instead -# of copied to the output. -# -# This may modify "dict". -# -def appendSourceFile(source, dict, outfp, sister_list): - outfp.write("/* File: %s */\n" % source) - infp = open(source, "r") - in_sister = False - for line in infp: - if line.startswith("%include"): - # Parse the "include" line - tokens = line.strip().split(' ', 2) - if len(tokens) < 2: - raise DataParseError("malformed %%include in %s" % source) - - alt_source = tokens[1].strip("\"") - if alt_source == source: - raise DataParseError("self-referential %%include in %s" - % source) - - new_dict = dict.copy() - if len(tokens) == 3: - new_dict.update(eval(tokens[2])) - #print " including src=%s dict=%s" % (alt_source, new_dict) - appendSourceFile(alt_source, new_dict, outfp, sister_list) - continue - - elif line.startswith("%default"): - # copy keywords into dictionary - tokens = line.strip().split(' ', 1) - if len(tokens) < 2: - raise DataParseError("malformed %%default in %s" % source) - defaultValues = eval(tokens[1]) - for entry in defaultValues: - dict.setdefault(entry, defaultValues[entry]) - continue - - elif line.startswith("%break") and sister_list != None: - # allow more than one %break, ignoring all following the first - if style == "computed-goto" and not in_sister: - in_sister = True - sister_list.append("\n/* continuation for %(opcode)s */\n"%dict) - continue - - # perform keyword substitution if a dictionary was provided - if dict != None: - templ = Template(line) - try: - subline = templ.substitute(dict) - except KeyError, err: - raise DataParseError("keyword substitution failed in %s: %s" - % (source, str(err))) - except: - print "ERROR: substitution failed: " + line - raise - else: - subline = line - - # write output to appropriate file - if in_sister: - sister_list.append(subline) - else: - outfp.write(subline) - outfp.write("\n") - infp.close() - -# -# Emit a C-style section header comment. -# -def emitSectionComment(str, fp): - equals = "========================================" \ - "===================================" - - fp.write("\n/*\n * %s\n * %s\n * %s\n */\n" % - (equals, str, equals)) - - -# -# =========================================================================== -# "main" code -# - -# -# Check args. -# -if len(sys.argv) != 3: - print "Usage: %s target-arch output-dir" % sys.argv[0] - sys.exit(2) - -target_arch = sys.argv[1] -output_dir = sys.argv[2] - -# -# Extract opcode list. -# -opcodes = getOpcodeList() -#for op in opcodes: -# print " %s" % op - -# -# Open config file. -# -try: - config_fp = open("config_%s" % target_arch) -except: - print "Unable to open config file 'config_%s'" % target_arch - sys.exit(1) - -# -# Open and prepare output files. -# -try: - asm_fp = open("%s/mterp_%s.S" % (output_dir, target_arch), "w") -except: - print "Unable to open output files" - print "Make sure directory '%s' exists and existing files are writable" \ - % output_dir - # Ideally we'd remove the files to avoid confusing "make", but if they - # failed to open we probably won't be able to remove them either. - sys.exit(1) - -print "Generating %s" % (asm_fp.name) - -file_header = """/* - * This file was generated automatically by gen-mterp.py for '%s'. - * - * --> DO NOT EDIT <-- - */ - -""" % (target_arch) - -asm_fp.write(file_header) - -# -# Process the config file. -# -failed = False -try: - for line in config_fp: - line = line.strip() # remove CRLF, leading spaces - tokens = line.split(' ') # tokenize - #print "%d: %s" % (len(tokens), tokens) - if len(tokens[0]) == 0: - #print " blank" - pass - elif tokens[0][0] == '#': - #print " comment" - pass - else: - if tokens[0] == "handler-size": - setHandlerSize(tokens) - elif tokens[0] == "import": - importFile(tokens) - elif tokens[0] == "asm-stub": - setAsmStub(tokens) - elif tokens[0] == "asm-alt-stub": - setAsmAltStub(tokens) - elif tokens[0] == "op-start": - opStart(tokens) - elif tokens[0] == "op-end": - opEnd(tokens) - elif tokens[0] == "alt": - altEntry(tokens) - elif tokens[0] == "op": - opEntry(tokens) - elif tokens[0] == "handler-style": - setHandlerStyle(tokens) - elif tokens[0] == "alt-ops": - genaltop(tokens) - elif tokens[0] == "split-ops": - splitops = True - elif tokens[0] == "fallback-stub": - setFallbackStub(tokens) - elif tokens[0] == "function-type-format": - setFunctionTypeFormat(tokens) - elif tokens[0] == "function-size-format": - setFunctionSizeFormat(tokens) - elif tokens[0] == "global-name-format": - setGlobalNameFormat(tokens) - else: - raise DataParseError, "unrecognized command '%s'" % tokens[0] - if style == None: - print "tokens[0] = %s" % tokens[0] - raise DataParseError, "handler-style must be first command" -except DataParseError, err: - print "Failed: " + str(err) - # TODO: remove output files so "make" doesn't get confused - failed = True - asm_fp.close() - asm_fp = None - -config_fp.close() - -# -# Done! -# -if asm_fp: - asm_fp.close() - -sys.exit(failed) + opcodes = [] + opcode_fp = open(INTERP_DEFS_FILE) + opcode_re = re.compile(r"^\s*V\((....), (\w+),.*", re.DOTALL) + for line in opcode_fp: + match = opcode_re.match(line) + if not match: + continue + opcodes.append("op_" + match.group(2).lower()) + opcode_fp.close() + + if len(opcodes) != NUM_PACKED_OPCODES: + print "ERROR: found %d opcodes in Interp.h (expected %d)" \ + % (len(opcodes), NUM_PACKED_OPCODES) + raise SyntaxError, "bad opcode count" + return opcodes + +indent_re = re.compile(r"^%( *)") + +# Finds variable references in text: $foo or ${foo} +escape_re = re.compile(r''' + (?\w+) # Save the symbol in named group. + (?(1)\}) # Expect } if and only if { was present. +''', re.VERBOSE) + +def generate_script(arch, setup_code): + # Create new python script and write the initial setup code. + script = StringIO() # File-like in-memory buffer. + script.write("# DO NOT EDIT: This file was generated by gen-mterp.py.\n") + script.write('arch = "' + arch + '"\n') + script.write(setup_code) + opcodes = getOpcodeList() + script.write("def opcodes(is_alt):\n") + for i in xrange(NUM_PACKED_OPCODES): + script.write(' write_opcode({0}, "{1}", {1}, is_alt)\n'.format(i, opcodes[i])) + + # Find all template files and translate them into python code. + files = listdir(arch) + for file in sorted(files): + f = open(arch + "/" + file, "r") + indent = "" + for line in f.readlines(): + line = line.rstrip() + if line.startswith("%"): + script.write(line.lstrip("%") + "\n") + indent = indent_re.match(line).group(1) + if line.endswith(":"): + indent += " " + else: + line = escape_re.sub(r"''' + \g + '''", line) + line = line.replace("\\", "\\\\") + line = line.replace("$$", "$") + script.write(indent + "write_line('''" + line + "''')\n") + script.write("\n") + f.close() + + # TODO: Remove the concept of sister snippets. It is barely used. + script.write("def write_sister():\n") + if arch == "arm": + script.write(" op_float_to_long_sister_code()\n") + script.write(" op_double_to_long_sister_code()\n") + if arch == "mips": + script.write(" global opnum, opcode\n") + names = [ + "op_float_to_long", + "op_double_to_long", + "op_mul_long", + "op_shl_long", + "op_shr_long", + "op_ushr_long", + "op_shl_long_2addr", + "op_shr_long_2addr", + "op_ushr_long_2addr" + ] + for name in names: + script.write(' opcode = "' + name + '"\n') + script.write(" " + name + "_sister_code()\n") + script.write(" pass\n") + + script.write('generate()\n') + script.seek(0) + return script.read() + +# Generate the script for each architecture and execute it. +for arch in ["arm", "arm64", "mips", "mips64", "x86", "x86_64"]: + with open(SCRIPT_SETUP_CODE, "r") as setup_code_file: + script = generate_script(arch, setup_code_file.read()) + filename = "out/mterp_" + arch + ".py" # Name to report in error messages. + # open(filename, "w").write(script) # Write the script to disk for debugging. + exec(compile(script, filename, mode='exec')) diff --git a/runtime/interpreter/mterp/mips/alt_stub.S b/runtime/interpreter/mterp/mips/alt_stub.S index de133136e0..1ce75617a0 100644 --- a/runtime/interpreter/mterp/mips/alt_stub.S +++ b/runtime/interpreter/mterp/mips/alt_stub.S @@ -1,3 +1,4 @@ +%def alt_stub(): /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction diff --git a/runtime/interpreter/mterp/mips/bincmp.S b/runtime/interpreter/mterp/mips/bincmp.S index 68df5c3ff0..b4b671fd95 100644 --- a/runtime/interpreter/mterp/mips/bincmp.S +++ b/runtime/interpreter/mterp/mips/bincmp.S @@ -1,3 +1,4 @@ +%def bincmp(condition=""): /* * Generic two-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform. diff --git a/runtime/interpreter/mterp/mips/binop.S b/runtime/interpreter/mterp/mips/binop.S index 862d95a736..062b22da87 100644 --- a/runtime/interpreter/mterp/mips/binop.S +++ b/runtime/interpreter/mterp/mips/binop.S @@ -1,4 +1,4 @@ -%default {"preinstr":"", "result":"a0", "chkzero":"0"} +%def binop(preinstr="", result="a0", chkzero="0", instr=""): /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0 op a1". diff --git a/runtime/interpreter/mterp/mips/binop2addr.S b/runtime/interpreter/mterp/mips/binop2addr.S index 17aa8eba22..89af6e1eea 100644 --- a/runtime/interpreter/mterp/mips/binop2addr.S +++ b/runtime/interpreter/mterp/mips/binop2addr.S @@ -1,4 +1,4 @@ -%default {"preinstr":"", "result":"a0", "chkzero":"0"} +%def binop2addr(preinstr="", result="a0", chkzero="0", instr=""): /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". diff --git a/runtime/interpreter/mterp/mips/binopLit16.S b/runtime/interpreter/mterp/mips/binopLit16.S index 0696e7ab92..9ae0da79e9 100644 --- a/runtime/interpreter/mterp/mips/binopLit16.S +++ b/runtime/interpreter/mterp/mips/binopLit16.S @@ -1,4 +1,4 @@ -%default {"preinstr":"", "result":"a0", "chkzero":"0"} +%def binopLit16(preinstr="", result="a0", chkzero="0", instr=""): /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". diff --git a/runtime/interpreter/mterp/mips/binopLit8.S b/runtime/interpreter/mterp/mips/binopLit8.S index 382dd2b4cd..ecf08c2d0c 100644 --- a/runtime/interpreter/mterp/mips/binopLit8.S +++ b/runtime/interpreter/mterp/mips/binopLit8.S @@ -1,4 +1,4 @@ -%default {"preinstr":"", "result":"a0", "chkzero":"0"} +%def binopLit8(preinstr="", result="a0", chkzero="0", instr=""): /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". diff --git a/runtime/interpreter/mterp/mips/binopWide.S b/runtime/interpreter/mterp/mips/binopWide.S index 604134d252..5768e95c48 100644 --- a/runtime/interpreter/mterp/mips/binopWide.S +++ b/runtime/interpreter/mterp/mips/binopWide.S @@ -1,4 +1,4 @@ -%default {"preinstr":"", "result0":"a0", "result1":"a1", "chkzero":"0", "arg0":"a0", "arg1":"a1", "arg2":"a2", "arg3":"a3"} +%def binopWide(preinstr="", result0="a0", result1="a1", chkzero="0", arg0="a0", arg1="a1", arg2="a2", arg3="a3", instr=""): /* * Generic 64-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0-a1 op a2-a3". diff --git a/runtime/interpreter/mterp/mips/binopWide2addr.S b/runtime/interpreter/mterp/mips/binopWide2addr.S index f96fdb23f0..4e00c81961 100644 --- a/runtime/interpreter/mterp/mips/binopWide2addr.S +++ b/runtime/interpreter/mterp/mips/binopWide2addr.S @@ -1,4 +1,4 @@ -%default {"preinstr":"", "result0":"a0", "result1":"a1", "chkzero":"0", "arg0":"a0", "arg1":"a1", "arg2":"a2", "arg3":"a3"} +%def binopWide2addr(preinstr="", result0="a0", result1="a1", chkzero="0", arg0="a0", arg1="a1", arg2="a2", arg3="a3", instr=""): /* * Generic 64-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0-a1 op a2-a3". diff --git a/runtime/interpreter/mterp/mips/const.S b/runtime/interpreter/mterp/mips/const.S index 5d8379dfb7..403dfc7389 100644 --- a/runtime/interpreter/mterp/mips/const.S +++ b/runtime/interpreter/mterp/mips/const.S @@ -1,4 +1,4 @@ -%default { "helper":"UndefinedConstHandler" } +%def const(helper="UndefinedConstHandler"): /* const/class vAA, type@BBBB */ /* const/method-handle vAA, method_handle@BBBB */ /* const/method-type vAA, proto@BBBB */ diff --git a/runtime/interpreter/mterp/mips/entry.S b/runtime/interpreter/mterp/mips/entry.S index d342354969..e40fc0203f 100644 --- a/runtime/interpreter/mterp/mips/entry.S +++ b/runtime/interpreter/mterp/mips/entry.S @@ -1,3 +1,4 @@ +%def entry(): /* * Copyright (C) 2016 The Android Open Source Project * diff --git a/runtime/interpreter/mterp/mips/fallback.S b/runtime/interpreter/mterp/mips/fallback.S index 82cbc63480..6133d9f825 100644 --- a/runtime/interpreter/mterp/mips/fallback.S +++ b/runtime/interpreter/mterp/mips/fallback.S @@ -1,2 +1,3 @@ +%def fallback(): /* Transfer stub to alternate interpreter */ b MterpFallback diff --git a/runtime/interpreter/mterp/mips/fbinop.S b/runtime/interpreter/mterp/mips/fbinop.S index 6c1468ccfa..7cbf73fda8 100644 --- a/runtime/interpreter/mterp/mips/fbinop.S +++ b/runtime/interpreter/mterp/mips/fbinop.S @@ -1,3 +1,4 @@ +%def fbinop(instr=""): /* * Generic 32-bit binary float operation. * diff --git a/runtime/interpreter/mterp/mips/fbinop2addr.S b/runtime/interpreter/mterp/mips/fbinop2addr.S index 2caaf9cbbb..ea9970fb0b 100644 --- a/runtime/interpreter/mterp/mips/fbinop2addr.S +++ b/runtime/interpreter/mterp/mips/fbinop2addr.S @@ -1,3 +1,4 @@ +%def fbinop2addr(instr=""): /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" * that specifies an instruction that performs "fv0 = fa0 op fa1". diff --git a/runtime/interpreter/mterp/mips/fbinopWide.S b/runtime/interpreter/mterp/mips/fbinopWide.S index a1fe91e25c..1b5c0c1387 100644 --- a/runtime/interpreter/mterp/mips/fbinopWide.S +++ b/runtime/interpreter/mterp/mips/fbinopWide.S @@ -1,3 +1,4 @@ +%def fbinopWide(instr=""): /* * Generic 64-bit floating-point binary operation. Provide an "instr" * line that specifies an instruction that performs "fv0 = fa0 op fa1". diff --git a/runtime/interpreter/mterp/mips/fbinopWide2addr.S b/runtime/interpreter/mterp/mips/fbinopWide2addr.S index 73034411e1..e36f1f874d 100644 --- a/runtime/interpreter/mterp/mips/fbinopWide2addr.S +++ b/runtime/interpreter/mterp/mips/fbinopWide2addr.S @@ -1,3 +1,4 @@ +%def fbinopWide2addr(instr=""): /* * Generic 64-bit floating-point "/2addr" binary operation. * Provide an "instr" line that specifies an instruction that diff --git a/runtime/interpreter/mterp/mips/field.S b/runtime/interpreter/mterp/mips/field.S index 1333ed77b7..d61b06afd4 100644 --- a/runtime/interpreter/mterp/mips/field.S +++ b/runtime/interpreter/mterp/mips/field.S @@ -1 +1,2 @@ +%def field(helper=""): TODO diff --git a/runtime/interpreter/mterp/mips/footer.S b/runtime/interpreter/mterp/mips/footer.S index 1c784ef188..0f641d213b 100644 --- a/runtime/interpreter/mterp/mips/footer.S +++ b/runtime/interpreter/mterp/mips/footer.S @@ -1,3 +1,4 @@ +%def footer(): /* * =========================================================================== * Common subroutines and data diff --git a/runtime/interpreter/mterp/mips/funop.S b/runtime/interpreter/mterp/mips/funop.S index b2b22c9794..64f40ac23b 100644 --- a/runtime/interpreter/mterp/mips/funop.S +++ b/runtime/interpreter/mterp/mips/funop.S @@ -1,3 +1,4 @@ +%def funop(instr=""): /* * Generic 32-bit floating-point unary operation. Provide an "instr" * line that specifies an instruction that performs "fv0 = op fa0". diff --git a/runtime/interpreter/mterp/mips/funopWider.S b/runtime/interpreter/mterp/mips/funopWider.S index 6862e24530..afc45ee9f5 100644 --- a/runtime/interpreter/mterp/mips/funopWider.S +++ b/runtime/interpreter/mterp/mips/funopWider.S @@ -1,3 +1,4 @@ +%def funopWider(instr=""): /* * Generic 32bit-to-64bit floating-point unary operation. Provide an "instr" * line that specifies an instruction that performs "fv0 = op fa0". diff --git a/runtime/interpreter/mterp/mips/header.S b/runtime/interpreter/mterp/mips/header.S index bef9eeb7f2..57339d0f7f 100644 --- a/runtime/interpreter/mterp/mips/header.S +++ b/runtime/interpreter/mterp/mips/header.S @@ -1,3 +1,4 @@ +%def header(): /* * Copyright (C) 2016 The Android Open Source Project * @@ -663,7 +664,6 @@ #define STORE64_F(rlo, rhi, rbase) STORE64_off_F(rlo, rhi, rbase, 0) #define LOAD64_F(rlo, rhi, rbase) LOAD64_off_F(rlo, rhi, rbase, 0) - #define LOAD_base_offMirrorArray_length(rd, rbase) LOAD_RB_OFF(rd, rbase, MIRROR_ARRAY_LENGTH_OFFSET) #define STACK_STORE(rd, off) sw rd, off(sp) diff --git a/runtime/interpreter/mterp/mips/instruction_end.S b/runtime/interpreter/mterp/mips/instruction_end.S index 32c725c7d9..3d4429365a 100644 --- a/runtime/interpreter/mterp/mips/instruction_end.S +++ b/runtime/interpreter/mterp/mips/instruction_end.S @@ -1,3 +1,4 @@ +%def instruction_end(): .global artMterpAsmInstructionEnd artMterpAsmInstructionEnd: diff --git a/runtime/interpreter/mterp/mips/instruction_end_alt.S b/runtime/interpreter/mterp/mips/instruction_end_alt.S index f90916fc02..86a1068f10 100644 --- a/runtime/interpreter/mterp/mips/instruction_end_alt.S +++ b/runtime/interpreter/mterp/mips/instruction_end_alt.S @@ -1,3 +1,4 @@ +%def instruction_end_alt(): .global artMterpAsmAltInstructionEnd artMterpAsmAltInstructionEnd: diff --git a/runtime/interpreter/mterp/mips/instruction_end_sister.S b/runtime/interpreter/mterp/mips/instruction_end_sister.S index c5f4886697..8cc4513025 100644 --- a/runtime/interpreter/mterp/mips/instruction_end_sister.S +++ b/runtime/interpreter/mterp/mips/instruction_end_sister.S @@ -1,3 +1,4 @@ +%def instruction_end_sister(): .global artMterpAsmSisterEnd artMterpAsmSisterEnd: diff --git a/runtime/interpreter/mterp/mips/instruction_start.S b/runtime/interpreter/mterp/mips/instruction_start.S index 8874c20540..4b777f2fd5 100644 --- a/runtime/interpreter/mterp/mips/instruction_start.S +++ b/runtime/interpreter/mterp/mips/instruction_start.S @@ -1,3 +1,4 @@ +%def instruction_start(): .global artMterpAsmInstructionStart artMterpAsmInstructionStart = .L_op_nop diff --git a/runtime/interpreter/mterp/mips/instruction_start_alt.S b/runtime/interpreter/mterp/mips/instruction_start_alt.S index 0c9ffdb7d6..e7731b7505 100644 --- a/runtime/interpreter/mterp/mips/instruction_start_alt.S +++ b/runtime/interpreter/mterp/mips/instruction_start_alt.S @@ -1,3 +1,4 @@ +%def instruction_start_alt(): .global artMterpAsmAltInstructionStart artMterpAsmAltInstructionStart = .L_ALT_op_nop diff --git a/runtime/interpreter/mterp/mips/instruction_start_sister.S b/runtime/interpreter/mterp/mips/instruction_start_sister.S index 2ec51f7261..e09ea90b8e 100644 --- a/runtime/interpreter/mterp/mips/instruction_start_sister.S +++ b/runtime/interpreter/mterp/mips/instruction_start_sister.S @@ -1,3 +1,4 @@ +%def instruction_start_sister(): .global artMterpAsmSisterStart .text diff --git a/runtime/interpreter/mterp/mips/invoke.S b/runtime/interpreter/mterp/mips/invoke.S index db3b8af73a..fa744527de 100644 --- a/runtime/interpreter/mterp/mips/invoke.S +++ b/runtime/interpreter/mterp/mips/invoke.S @@ -1,4 +1,4 @@ -%default { "helper":"UndefinedInvokeHandler" } +%def invoke(helper="UndefinedInvokeHandler"): /* * Generic invoke handler wrapper. */ diff --git a/runtime/interpreter/mterp/mips/invoke_polymorphic.S b/runtime/interpreter/mterp/mips/invoke_polymorphic.S index 5c963f0314..f2532e7b2b 100644 --- a/runtime/interpreter/mterp/mips/invoke_polymorphic.S +++ b/runtime/interpreter/mterp/mips/invoke_polymorphic.S @@ -1,4 +1,4 @@ -%default { "helper":"UndefinedInvokeHandler" } +%def invoke_polymorphic(helper="UndefinedInvokeHandler"): /* * invoke-polymorphic handler wrapper. */ diff --git a/runtime/interpreter/mterp/mips/op_add_double.S b/runtime/interpreter/mterp/mips/op_add_double.S index 12ef0cf3cd..8308cdc4dd 100644 --- a/runtime/interpreter/mterp/mips/op_add_double.S +++ b/runtime/interpreter/mterp/mips/op_add_double.S @@ -1 +1,2 @@ -%include "mips/fbinopWide.S" {"instr":"add.d fv0, fa0, fa1"} +%def op_add_double(): +% fbinopWide(instr="add.d fv0, fa0, fa1") diff --git a/runtime/interpreter/mterp/mips/op_add_double_2addr.S b/runtime/interpreter/mterp/mips/op_add_double_2addr.S index c57add572c..41b099676c 100644 --- a/runtime/interpreter/mterp/mips/op_add_double_2addr.S +++ b/runtime/interpreter/mterp/mips/op_add_double_2addr.S @@ -1 +1,2 @@ -%include "mips/fbinopWide2addr.S" {"instr":"add.d fv0, fa0, fa1"} +%def op_add_double_2addr(): +% fbinopWide2addr(instr="add.d fv0, fa0, fa1") diff --git a/runtime/interpreter/mterp/mips/op_add_float.S b/runtime/interpreter/mterp/mips/op_add_float.S index 6a46cf0ab9..807ea97481 100644 --- a/runtime/interpreter/mterp/mips/op_add_float.S +++ b/runtime/interpreter/mterp/mips/op_add_float.S @@ -1 +1,2 @@ -%include "mips/fbinop.S" {"instr":"add.s fv0, fa0, fa1"} +%def op_add_float(): +% fbinop(instr="add.s fv0, fa0, fa1") diff --git a/runtime/interpreter/mterp/mips/op_add_float_2addr.S b/runtime/interpreter/mterp/mips/op_add_float_2addr.S index 6ab5cc1730..c5735ae2e0 100644 --- a/runtime/interpreter/mterp/mips/op_add_float_2addr.S +++ b/runtime/interpreter/mterp/mips/op_add_float_2addr.S @@ -1 +1,2 @@ -%include "mips/fbinop2addr.S" {"instr":"add.s fv0, fa0, fa1"} +%def op_add_float_2addr(): +% fbinop2addr(instr="add.s fv0, fa0, fa1") diff --git a/runtime/interpreter/mterp/mips/op_add_int.S b/runtime/interpreter/mterp/mips/op_add_int.S index 53a0cb128f..ed0fc012b8 100644 --- a/runtime/interpreter/mterp/mips/op_add_int.S +++ b/runtime/interpreter/mterp/mips/op_add_int.S @@ -1 +1,2 @@ -%include "mips/binop.S" {"instr":"addu a0, a0, a1"} +%def op_add_int(): +% binop(instr="addu a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_add_int_2addr.S b/runtime/interpreter/mterp/mips/op_add_int_2addr.S index ddd92145c3..ed0b1314ef 100644 --- a/runtime/interpreter/mterp/mips/op_add_int_2addr.S +++ b/runtime/interpreter/mterp/mips/op_add_int_2addr.S @@ -1 +1,2 @@ -%include "mips/binop2addr.S" {"instr":"addu a0, a0, a1"} +%def op_add_int_2addr(): +% binop2addr(instr="addu a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_add_int_lit16.S b/runtime/interpreter/mterp/mips/op_add_int_lit16.S index 05535c15dc..126807a303 100644 --- a/runtime/interpreter/mterp/mips/op_add_int_lit16.S +++ b/runtime/interpreter/mterp/mips/op_add_int_lit16.S @@ -1 +1,2 @@ -%include "mips/binopLit16.S" {"instr":"addu a0, a0, a1"} +%def op_add_int_lit16(): +% binopLit16(instr="addu a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_add_int_lit8.S b/runtime/interpreter/mterp/mips/op_add_int_lit8.S index fd021b31a9..30184c40f5 100644 --- a/runtime/interpreter/mterp/mips/op_add_int_lit8.S +++ b/runtime/interpreter/mterp/mips/op_add_int_lit8.S @@ -1 +1,2 @@ -%include "mips/binopLit8.S" {"instr":"addu a0, a0, a1"} +%def op_add_int_lit8(): +% binopLit8(instr="addu a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_add_long.S b/runtime/interpreter/mterp/mips/op_add_long.S index faacc6a3cc..32205068ba 100644 --- a/runtime/interpreter/mterp/mips/op_add_long.S +++ b/runtime/interpreter/mterp/mips/op_add_long.S @@ -1,3 +1,4 @@ +%def op_add_long(): /* * The compiler generates the following sequence for * [v1 v0] = [a1 a0] + [a3 a2]; @@ -6,4 +7,4 @@ * sltu v1,v0,a2 * addu v1,v1,a1 */ -%include "mips/binopWide.S" { "result0":"v0", "result1":"v1", "preinstr":"addu v0, a2, a0", "instr":"addu a1, a3, a1; sltu v1, v0, a2; addu v1, v1, a1" } +% binopWide(result0="v0", result1="v1", preinstr="addu v0, a2, a0", instr="addu a1, a3, a1; sltu v1, v0, a2; addu v1, v1, a1") diff --git a/runtime/interpreter/mterp/mips/op_add_long_2addr.S b/runtime/interpreter/mterp/mips/op_add_long_2addr.S index bf827c10d4..3bbc1f393d 100644 --- a/runtime/interpreter/mterp/mips/op_add_long_2addr.S +++ b/runtime/interpreter/mterp/mips/op_add_long_2addr.S @@ -1,4 +1,5 @@ +%def op_add_long_2addr(): /* * See op_add_long.S for details */ -%include "mips/binopWide2addr.S" { "result0":"v0", "result1":"v1", "preinstr":"addu v0, a2, a0", "instr":"addu a1, a3, a1; sltu v1, v0, a2; addu v1, v1, a1" } +% binopWide2addr(result0="v0", result1="v1", preinstr="addu v0, a2, a0", instr="addu a1, a3, a1; sltu v1, v0, a2; addu v1, v1, a1") diff --git a/runtime/interpreter/mterp/mips/op_aget.S b/runtime/interpreter/mterp/mips/op_aget.S index e88402c710..026095f7ac 100644 --- a/runtime/interpreter/mterp/mips/op_aget.S +++ b/runtime/interpreter/mterp/mips/op_aget.S @@ -1,4 +1,4 @@ -%default { "load":"lw", "shift":"2", "data_offset":"MIRROR_INT_ARRAY_DATA_OFFSET" } +%def op_aget(load="lw", shift="2", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"): /* * Array get, 32 bits or less. vAA <- vBB[vCC]. * diff --git a/runtime/interpreter/mterp/mips/op_aget_boolean.S b/runtime/interpreter/mterp/mips/op_aget_boolean.S index 59f7f82a84..7b28bc8e06 100644 --- a/runtime/interpreter/mterp/mips/op_aget_boolean.S +++ b/runtime/interpreter/mterp/mips/op_aget_boolean.S @@ -1 +1,2 @@ -%include "mips/op_aget.S" { "load":"lbu", "shift":"0", "data_offset":"MIRROR_BOOLEAN_ARRAY_DATA_OFFSET" } +%def op_aget_boolean(): +% op_aget(load="lbu", shift="0", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/mips/op_aget_byte.S b/runtime/interpreter/mterp/mips/op_aget_byte.S index 11038fa7e1..a4a0b7e9b7 100644 --- a/runtime/interpreter/mterp/mips/op_aget_byte.S +++ b/runtime/interpreter/mterp/mips/op_aget_byte.S @@ -1 +1,2 @@ -%include "mips/op_aget.S" { "load":"lb", "shift":"0", "data_offset":"MIRROR_BYTE_ARRAY_DATA_OFFSET" } +%def op_aget_byte(): +% op_aget(load="lb", shift="0", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/mips/op_aget_char.S b/runtime/interpreter/mterp/mips/op_aget_char.S index 96f2ab65dc..465de097cd 100644 --- a/runtime/interpreter/mterp/mips/op_aget_char.S +++ b/runtime/interpreter/mterp/mips/op_aget_char.S @@ -1 +1,2 @@ -%include "mips/op_aget.S" { "load":"lhu", "shift":"1", "data_offset":"MIRROR_CHAR_ARRAY_DATA_OFFSET" } +%def op_aget_char(): +% op_aget(load="lhu", shift="1", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/mips/op_aget_object.S b/runtime/interpreter/mterp/mips/op_aget_object.S index 9c49dfeed7..17a1e0ca8c 100644 --- a/runtime/interpreter/mterp/mips/op_aget_object.S +++ b/runtime/interpreter/mterp/mips/op_aget_object.S @@ -1,3 +1,4 @@ +%def op_aget_object(): /* * Array object get. vAA <- vBB[vCC]. * diff --git a/runtime/interpreter/mterp/mips/op_aget_short.S b/runtime/interpreter/mterp/mips/op_aget_short.S index cd7f7bf62f..4faa9ad358 100644 --- a/runtime/interpreter/mterp/mips/op_aget_short.S +++ b/runtime/interpreter/mterp/mips/op_aget_short.S @@ -1 +1,2 @@ -%include "mips/op_aget.S" { "load":"lh", "shift":"1", "data_offset":"MIRROR_SHORT_ARRAY_DATA_OFFSET" } +%def op_aget_short(): +% op_aget(load="lh", shift="1", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/mips/op_aget_wide.S b/runtime/interpreter/mterp/mips/op_aget_wide.S index 08822f56c3..4045c11dbe 100644 --- a/runtime/interpreter/mterp/mips/op_aget_wide.S +++ b/runtime/interpreter/mterp/mips/op_aget_wide.S @@ -1,3 +1,4 @@ +%def op_aget_wide(): /* * Array get, 64 bits. vAA <- vBB[vCC]. * diff --git a/runtime/interpreter/mterp/mips/op_and_int.S b/runtime/interpreter/mterp/mips/op_and_int.S index 98fe4af7d2..740411ddf7 100644 --- a/runtime/interpreter/mterp/mips/op_and_int.S +++ b/runtime/interpreter/mterp/mips/op_and_int.S @@ -1 +1,2 @@ -%include "mips/binop.S" {"instr":"and a0, a0, a1"} +%def op_and_int(): +% binop(instr="and a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_and_int_2addr.S b/runtime/interpreter/mterp/mips/op_and_int_2addr.S index 7f90ed4535..8224e5f18a 100644 --- a/runtime/interpreter/mterp/mips/op_and_int_2addr.S +++ b/runtime/interpreter/mterp/mips/op_and_int_2addr.S @@ -1 +1,2 @@ -%include "mips/binop2addr.S" {"instr":"and a0, a0, a1"} +%def op_and_int_2addr(): +% binop2addr(instr="and a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_and_int_lit16.S b/runtime/interpreter/mterp/mips/op_and_int_lit16.S index e46f23ba2e..5031f500ce 100644 --- a/runtime/interpreter/mterp/mips/op_and_int_lit16.S +++ b/runtime/interpreter/mterp/mips/op_and_int_lit16.S @@ -1 +1,2 @@ -%include "mips/binopLit16.S" {"instr":"and a0, a0, a1"} +%def op_and_int_lit16(): +% binopLit16(instr="and a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_and_int_lit8.S b/runtime/interpreter/mterp/mips/op_and_int_lit8.S index 3332883dc2..7a7b8b5d5a 100644 --- a/runtime/interpreter/mterp/mips/op_and_int_lit8.S +++ b/runtime/interpreter/mterp/mips/op_and_int_lit8.S @@ -1 +1,2 @@ -%include "mips/binopLit8.S" {"instr":"and a0, a0, a1"} +%def op_and_int_lit8(): +% binopLit8(instr="and a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_and_long.S b/runtime/interpreter/mterp/mips/op_and_long.S index a98a6dfbd8..210e6a1acc 100644 --- a/runtime/interpreter/mterp/mips/op_and_long.S +++ b/runtime/interpreter/mterp/mips/op_and_long.S @@ -1 +1,2 @@ -%include "mips/binopWide.S" {"preinstr":"and a0, a0, a2", "instr":"and a1, a1, a3"} +%def op_and_long(): +% binopWide(preinstr="and a0, a0, a2", instr="and a1, a1, a3") diff --git a/runtime/interpreter/mterp/mips/op_and_long_2addr.S b/runtime/interpreter/mterp/mips/op_and_long_2addr.S index 350c044f98..c76a5af695 100644 --- a/runtime/interpreter/mterp/mips/op_and_long_2addr.S +++ b/runtime/interpreter/mterp/mips/op_and_long_2addr.S @@ -1 +1,2 @@ -%include "mips/binopWide2addr.S" {"preinstr":"and a0, a0, a2", "instr":"and a1, a1, a3"} +%def op_and_long_2addr(): +% binopWide2addr(preinstr="and a0, a0, a2", instr="and a1, a1, a3") diff --git a/runtime/interpreter/mterp/mips/op_aput.S b/runtime/interpreter/mterp/mips/op_aput.S index 46dcaee3a9..6561f8f79f 100644 --- a/runtime/interpreter/mterp/mips/op_aput.S +++ b/runtime/interpreter/mterp/mips/op_aput.S @@ -1,4 +1,4 @@ -%default { "store":"sw", "shift":"2", "data_offset":"MIRROR_INT_ARRAY_DATA_OFFSET" } +%def op_aput(store="sw", shift="2", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"): /* * Array put, 32 bits or less. vBB[vCC] <- vAA. diff --git a/runtime/interpreter/mterp/mips/op_aput_boolean.S b/runtime/interpreter/mterp/mips/op_aput_boolean.S index 9cae5efbaf..098bbcd1c4 100644 --- a/runtime/interpreter/mterp/mips/op_aput_boolean.S +++ b/runtime/interpreter/mterp/mips/op_aput_boolean.S @@ -1 +1,2 @@ -%include "mips/op_aput.S" { "store":"sb", "shift":"0", "data_offset":"MIRROR_BOOLEAN_ARRAY_DATA_OFFSET" } +%def op_aput_boolean(): +% op_aput(store="sb", shift="0", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/mips/op_aput_byte.S b/runtime/interpreter/mterp/mips/op_aput_byte.S index 3bbd12cec1..f4b42ee6e8 100644 --- a/runtime/interpreter/mterp/mips/op_aput_byte.S +++ b/runtime/interpreter/mterp/mips/op_aput_byte.S @@ -1 +1,2 @@ -%include "mips/op_aput.S" { "store":"sb", "shift":"0", "data_offset":"MIRROR_BYTE_ARRAY_DATA_OFFSET" } +%def op_aput_byte(): +% op_aput(store="sb", shift="0", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/mips/op_aput_char.S b/runtime/interpreter/mterp/mips/op_aput_char.S index ae697173d7..18eedae68d 100644 --- a/runtime/interpreter/mterp/mips/op_aput_char.S +++ b/runtime/interpreter/mterp/mips/op_aput_char.S @@ -1 +1,2 @@ -%include "mips/op_aput.S" { "store":"sh", "shift":"1", "data_offset":"MIRROR_CHAR_ARRAY_DATA_OFFSET" } +%def op_aput_char(): +% op_aput(store="sh", shift="1", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/mips/op_aput_object.S b/runtime/interpreter/mterp/mips/op_aput_object.S index 55b13b1449..89c72bac4e 100644 --- a/runtime/interpreter/mterp/mips/op_aput_object.S +++ b/runtime/interpreter/mterp/mips/op_aput_object.S @@ -1,3 +1,4 @@ +%def op_aput_object(): /* * Store an object into an array. vBB[vCC] <- vAA. * diff --git a/runtime/interpreter/mterp/mips/op_aput_short.S b/runtime/interpreter/mterp/mips/op_aput_short.S index 9586259a24..61a3c0d6ea 100644 --- a/runtime/interpreter/mterp/mips/op_aput_short.S +++ b/runtime/interpreter/mterp/mips/op_aput_short.S @@ -1 +1,2 @@ -%include "mips/op_aput.S" { "store":"sh", "shift":"1", "data_offset":"MIRROR_SHORT_ARRAY_DATA_OFFSET" } +%def op_aput_short(): +% op_aput(store="sh", shift="1", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/mips/op_aput_wide.S b/runtime/interpreter/mterp/mips/op_aput_wide.S index c3cff56aaa..2fd0cbb932 100644 --- a/runtime/interpreter/mterp/mips/op_aput_wide.S +++ b/runtime/interpreter/mterp/mips/op_aput_wide.S @@ -1,3 +1,4 @@ +%def op_aput_wide(): /* * Array put, 64 bits. vBB[vCC] <- vAA. */ diff --git a/runtime/interpreter/mterp/mips/op_array_length.S b/runtime/interpreter/mterp/mips/op_array_length.S index ae2fe68322..12348bd3f2 100644 --- a/runtime/interpreter/mterp/mips/op_array_length.S +++ b/runtime/interpreter/mterp/mips/op_array_length.S @@ -1,3 +1,4 @@ +%def op_array_length(): /* * Return the length of an array. */ diff --git a/runtime/interpreter/mterp/mips/op_check_cast.S b/runtime/interpreter/mterp/mips/op_check_cast.S index 3875ce6fc7..4d0f28681c 100644 --- a/runtime/interpreter/mterp/mips/op_check_cast.S +++ b/runtime/interpreter/mterp/mips/op_check_cast.S @@ -1,3 +1,4 @@ +%def op_check_cast(): /* * Check to see if a cast from one class to another is allowed. */ diff --git a/runtime/interpreter/mterp/mips/op_cmp_long.S b/runtime/interpreter/mterp/mips/op_cmp_long.S index 44806c3d06..7d40b0e459 100644 --- a/runtime/interpreter/mterp/mips/op_cmp_long.S +++ b/runtime/interpreter/mterp/mips/op_cmp_long.S @@ -1,3 +1,4 @@ +%def op_cmp_long(): /* * Compare two 64-bit values * x = y return 0 diff --git a/runtime/interpreter/mterp/mips/op_cmpg_double.S b/runtime/interpreter/mterp/mips/op_cmpg_double.S index b2e753219c..8e3d181850 100644 --- a/runtime/interpreter/mterp/mips/op_cmpg_double.S +++ b/runtime/interpreter/mterp/mips/op_cmpg_double.S @@ -1 +1,2 @@ -%include "mips/op_cmpl_double.S" { "gt_bias":"1" } +%def op_cmpg_double(): +% op_cmpl_double(gt_bias="1") diff --git a/runtime/interpreter/mterp/mips/op_cmpg_float.S b/runtime/interpreter/mterp/mips/op_cmpg_float.S index 76550b56b0..d8afa2a1f4 100644 --- a/runtime/interpreter/mterp/mips/op_cmpg_float.S +++ b/runtime/interpreter/mterp/mips/op_cmpg_float.S @@ -1 +1,2 @@ -%include "mips/op_cmpl_float.S" { "gt_bias":"1" } +%def op_cmpg_float(): +% op_cmpl_float(gt_bias="1") diff --git a/runtime/interpreter/mterp/mips/op_cmpl_double.S b/runtime/interpreter/mterp/mips/op_cmpl_double.S index 369e5b30fd..ab6dd49a5d 100644 --- a/runtime/interpreter/mterp/mips/op_cmpl_double.S +++ b/runtime/interpreter/mterp/mips/op_cmpl_double.S @@ -1,4 +1,4 @@ -%default { "gt_bias":"0" } +%def op_cmpl_double(gt_bias="0"): /* * Compare two floating-point values. Puts 0(==), 1(>), or -1(<) * into the destination register based on the comparison results. diff --git a/runtime/interpreter/mterp/mips/op_cmpl_float.S b/runtime/interpreter/mterp/mips/op_cmpl_float.S index 1dd55067e9..6542844215 100644 --- a/runtime/interpreter/mterp/mips/op_cmpl_float.S +++ b/runtime/interpreter/mterp/mips/op_cmpl_float.S @@ -1,4 +1,4 @@ -%default { "gt_bias":"0" } +%def op_cmpl_float(gt_bias="0"): /* * Compare two floating-point values. Puts 0(==), 1(>), or -1(<) * into the destination register based on the comparison results. diff --git a/runtime/interpreter/mterp/mips/op_const.S b/runtime/interpreter/mterp/mips/op_const.S index bd9f873fb5..5b429d4b54 100644 --- a/runtime/interpreter/mterp/mips/op_const.S +++ b/runtime/interpreter/mterp/mips/op_const.S @@ -1,3 +1,4 @@ +%def op_const(): /* const vAA, +BBBBbbbb */ GET_OPA(a3) # a3 <- AA FETCH(a0, 1) # a0 <- bbbb (low) diff --git a/runtime/interpreter/mterp/mips/op_const_16.S b/runtime/interpreter/mterp/mips/op_const_16.S index 2ffb30f6f1..85669a91b3 100644 --- a/runtime/interpreter/mterp/mips/op_const_16.S +++ b/runtime/interpreter/mterp/mips/op_const_16.S @@ -1,3 +1,4 @@ +%def op_const_16(): /* const/16 vAA, +BBBB */ FETCH_S(a0, 1) # a0 <- ssssBBBB (sign-extended) GET_OPA(a3) # a3 <- AA diff --git a/runtime/interpreter/mterp/mips/op_const_4.S b/runtime/interpreter/mterp/mips/op_const_4.S index 6866c78417..158a24658a 100644 --- a/runtime/interpreter/mterp/mips/op_const_4.S +++ b/runtime/interpreter/mterp/mips/op_const_4.S @@ -1,3 +1,4 @@ +%def op_const_4(): /* const/4 vA, +B */ sll a1, rINST, 16 # a1 <- Bxxx0000 GET_OPA(a0) # a0 <- A+ diff --git a/runtime/interpreter/mterp/mips/op_const_class.S b/runtime/interpreter/mterp/mips/op_const_class.S index 5b3c96819a..db12ec3141 100644 --- a/runtime/interpreter/mterp/mips/op_const_class.S +++ b/runtime/interpreter/mterp/mips/op_const_class.S @@ -1 +1,2 @@ -%include "mips/const.S" { "helper":"MterpConstClass" } +%def op_const_class(): +% const(helper="MterpConstClass") diff --git a/runtime/interpreter/mterp/mips/op_const_high16.S b/runtime/interpreter/mterp/mips/op_const_high16.S index 5162402260..fee5296320 100644 --- a/runtime/interpreter/mterp/mips/op_const_high16.S +++ b/runtime/interpreter/mterp/mips/op_const_high16.S @@ -1,3 +1,4 @@ +%def op_const_high16(): /* const/high16 vAA, +BBBB0000 */ FETCH(a0, 1) # a0 <- 0000BBBB (zero-extended) GET_OPA(a3) # a3 <- AA diff --git a/runtime/interpreter/mterp/mips/op_const_method_handle.S b/runtime/interpreter/mterp/mips/op_const_method_handle.S index 4011e435c4..2680c17aad 100644 --- a/runtime/interpreter/mterp/mips/op_const_method_handle.S +++ b/runtime/interpreter/mterp/mips/op_const_method_handle.S @@ -1 +1,2 @@ -%include "mips/const.S" { "helper":"MterpConstMethodHandle" } +%def op_const_method_handle(): +% const(helper="MterpConstMethodHandle") diff --git a/runtime/interpreter/mterp/mips/op_const_method_type.S b/runtime/interpreter/mterp/mips/op_const_method_type.S index 18a5e0f688..ea814bf648 100644 --- a/runtime/interpreter/mterp/mips/op_const_method_type.S +++ b/runtime/interpreter/mterp/mips/op_const_method_type.S @@ -1 +1,2 @@ -%include "mips/const.S" { "helper":"MterpConstMethodType" } +%def op_const_method_type(): +% const(helper="MterpConstMethodType") diff --git a/runtime/interpreter/mterp/mips/op_const_string.S b/runtime/interpreter/mterp/mips/op_const_string.S index 0bab6b4068..41376f8703 100644 --- a/runtime/interpreter/mterp/mips/op_const_string.S +++ b/runtime/interpreter/mterp/mips/op_const_string.S @@ -1 +1,2 @@ -%include "mips/const.S" { "helper":"MterpConstString" } +%def op_const_string(): +% const(helper="MterpConstString") diff --git a/runtime/interpreter/mterp/mips/op_const_string_jumbo.S b/runtime/interpreter/mterp/mips/op_const_string_jumbo.S index 54cec977d3..0a031f3356 100644 --- a/runtime/interpreter/mterp/mips/op_const_string_jumbo.S +++ b/runtime/interpreter/mterp/mips/op_const_string_jumbo.S @@ -1,3 +1,4 @@ +%def op_const_string_jumbo(): /* const/string vAA, string@BBBBBBBB */ EXPORT_PC() FETCH(a0, 1) # a0 <- bbbb (low) diff --git a/runtime/interpreter/mterp/mips/op_const_wide.S b/runtime/interpreter/mterp/mips/op_const_wide.S index f8911e3a68..b424237135 100644 --- a/runtime/interpreter/mterp/mips/op_const_wide.S +++ b/runtime/interpreter/mterp/mips/op_const_wide.S @@ -1,3 +1,4 @@ +%def op_const_wide(): /* const-wide vAA, +HHHHhhhhBBBBbbbb */ FETCH(a0, 1) # a0 <- bbbb (low) FETCH(a1, 2) # a1 <- BBBB (low middle) diff --git a/runtime/interpreter/mterp/mips/op_const_wide_16.S b/runtime/interpreter/mterp/mips/op_const_wide_16.S index 2ca5ab927f..d89a2b629c 100644 --- a/runtime/interpreter/mterp/mips/op_const_wide_16.S +++ b/runtime/interpreter/mterp/mips/op_const_wide_16.S @@ -1,3 +1,4 @@ +%def op_const_wide_16(): /* const-wide/16 vAA, +BBBB */ FETCH_S(a0, 1) # a0 <- ssssBBBB (sign-extended) GET_OPA(a3) # a3 <- AA diff --git a/runtime/interpreter/mterp/mips/op_const_wide_32.S b/runtime/interpreter/mterp/mips/op_const_wide_32.S index bf802ca170..f9db95367a 100644 --- a/runtime/interpreter/mterp/mips/op_const_wide_32.S +++ b/runtime/interpreter/mterp/mips/op_const_wide_32.S @@ -1,3 +1,4 @@ +%def op_const_wide_32(): /* const-wide/32 vAA, +BBBBbbbb */ FETCH(a0, 1) # a0 <- 0000bbbb (low) GET_OPA(a3) # a3 <- AA diff --git a/runtime/interpreter/mterp/mips/op_const_wide_high16.S b/runtime/interpreter/mterp/mips/op_const_wide_high16.S index 04b90fa152..dd0cd947f2 100644 --- a/runtime/interpreter/mterp/mips/op_const_wide_high16.S +++ b/runtime/interpreter/mterp/mips/op_const_wide_high16.S @@ -1,3 +1,4 @@ +%def op_const_wide_high16(): /* const-wide/high16 vAA, +BBBB000000000000 */ FETCH(a1, 1) # a1 <- 0000BBBB (zero-extended) GET_OPA(a3) # a3 <- AA diff --git a/runtime/interpreter/mterp/mips/op_div_double.S b/runtime/interpreter/mterp/mips/op_div_double.S index 84e4c4e317..e1324d0dc7 100644 --- a/runtime/interpreter/mterp/mips/op_div_double.S +++ b/runtime/interpreter/mterp/mips/op_div_double.S @@ -1 +1,2 @@ -%include "mips/fbinopWide.S" {"instr":"div.d fv0, fa0, fa1"} +%def op_div_double(): +% fbinopWide(instr="div.d fv0, fa0, fa1") diff --git a/runtime/interpreter/mterp/mips/op_div_double_2addr.S b/runtime/interpreter/mterp/mips/op_div_double_2addr.S index 65b92e37db..aa6d16d4a9 100644 --- a/runtime/interpreter/mterp/mips/op_div_double_2addr.S +++ b/runtime/interpreter/mterp/mips/op_div_double_2addr.S @@ -1 +1,2 @@ -%include "mips/fbinopWide2addr.S" {"instr":"div.d fv0, fa0, fa1"} +%def op_div_double_2addr(): +% fbinopWide2addr(instr="div.d fv0, fa0, fa1") diff --git a/runtime/interpreter/mterp/mips/op_div_float.S b/runtime/interpreter/mterp/mips/op_div_float.S index 44b8d47e0b..b00c44c545 100644 --- a/runtime/interpreter/mterp/mips/op_div_float.S +++ b/runtime/interpreter/mterp/mips/op_div_float.S @@ -1 +1,2 @@ -%include "mips/fbinop.S" {"instr":"div.s fv0, fa0, fa1"} +%def op_div_float(): +% fbinop(instr="div.s fv0, fa0, fa1") diff --git a/runtime/interpreter/mterp/mips/op_div_float_2addr.S b/runtime/interpreter/mterp/mips/op_div_float_2addr.S index e5fff92c8c..5201603e42 100644 --- a/runtime/interpreter/mterp/mips/op_div_float_2addr.S +++ b/runtime/interpreter/mterp/mips/op_div_float_2addr.S @@ -1 +1,2 @@ -%include "mips/fbinop2addr.S" {"instr":"div.s fv0, fa0, fa1"} +%def op_div_float_2addr(): +% fbinop2addr(instr="div.s fv0, fa0, fa1") diff --git a/runtime/interpreter/mterp/mips/op_div_int.S b/runtime/interpreter/mterp/mips/op_div_int.S index 5d28c84d6b..2b49fd25e7 100644 --- a/runtime/interpreter/mterp/mips/op_div_int.S +++ b/runtime/interpreter/mterp/mips/op_div_int.S @@ -1,5 +1,6 @@ +%def op_div_int(): #ifdef MIPS32REVGE6 -%include "mips/binop.S" {"instr":"div a0, a0, a1", "chkzero":"1"} +% binop(instr="div a0, a0, a1", chkzero="1") #else -%include "mips/binop.S" {"preinstr":"div zero, a0, a1", "instr":"mflo a0", "chkzero":"1"} +% binop(preinstr="div zero, a0, a1", instr="mflo a0", chkzero="1") #endif diff --git a/runtime/interpreter/mterp/mips/op_div_int_2addr.S b/runtime/interpreter/mterp/mips/op_div_int_2addr.S index 6c079e04c4..325a5e6b0a 100644 --- a/runtime/interpreter/mterp/mips/op_div_int_2addr.S +++ b/runtime/interpreter/mterp/mips/op_div_int_2addr.S @@ -1,5 +1,6 @@ +%def op_div_int_2addr(): #ifdef MIPS32REVGE6 -%include "mips/binop2addr.S" {"instr":"div a0, a0, a1", "chkzero":"1"} +% binop2addr(instr="div a0, a0, a1", chkzero="1") #else -%include "mips/binop2addr.S" {"preinstr":"div zero, a0, a1", "instr":"mflo a0", "chkzero":"1"} +% binop2addr(preinstr="div zero, a0, a1", instr="mflo a0", chkzero="1") #endif diff --git a/runtime/interpreter/mterp/mips/op_div_int_lit16.S b/runtime/interpreter/mterp/mips/op_div_int_lit16.S index ee7452ce1a..7eaf340a4b 100644 --- a/runtime/interpreter/mterp/mips/op_div_int_lit16.S +++ b/runtime/interpreter/mterp/mips/op_div_int_lit16.S @@ -1,5 +1,6 @@ +%def op_div_int_lit16(): #ifdef MIPS32REVGE6 -%include "mips/binopLit16.S" {"instr":"div a0, a0, a1", "chkzero":"1"} +% binopLit16(instr="div a0, a0, a1", chkzero="1") #else -%include "mips/binopLit16.S" {"preinstr":"div zero, a0, a1", "instr":"mflo a0", "chkzero":"1"} +% binopLit16(preinstr="div zero, a0, a1", instr="mflo a0", chkzero="1") #endif diff --git a/runtime/interpreter/mterp/mips/op_div_int_lit8.S b/runtime/interpreter/mterp/mips/op_div_int_lit8.S index d2964b8065..b6aebb72be 100644 --- a/runtime/interpreter/mterp/mips/op_div_int_lit8.S +++ b/runtime/interpreter/mterp/mips/op_div_int_lit8.S @@ -1,5 +1,6 @@ +%def op_div_int_lit8(): #ifdef MIPS32REVGE6 -%include "mips/binopLit8.S" {"instr":"div a0, a0, a1", "chkzero":"1"} +% binopLit8(instr="div a0, a0, a1", chkzero="1") #else -%include "mips/binopLit8.S" {"preinstr":"div zero, a0, a1", "instr":"mflo a0", "chkzero":"1"} +% binopLit8(preinstr="div zero, a0, a1", instr="mflo a0", chkzero="1") #endif diff --git a/runtime/interpreter/mterp/mips/op_div_long.S b/runtime/interpreter/mterp/mips/op_div_long.S index 2097866886..631125927c 100644 --- a/runtime/interpreter/mterp/mips/op_div_long.S +++ b/runtime/interpreter/mterp/mips/op_div_long.S @@ -1 +1,2 @@ -%include "mips/binopWide.S" {"result0":"v0", "result1":"v1", "instr":"JAL(__divdi3)", "chkzero":"1"} +%def op_div_long(): +% binopWide(result0="v0", result1="v1", instr="JAL(__divdi3)", chkzero="1") diff --git a/runtime/interpreter/mterp/mips/op_div_long_2addr.S b/runtime/interpreter/mterp/mips/op_div_long_2addr.S index c279305142..b3f72932d6 100644 --- a/runtime/interpreter/mterp/mips/op_div_long_2addr.S +++ b/runtime/interpreter/mterp/mips/op_div_long_2addr.S @@ -1 +1,2 @@ -%include "mips/binopWide2addr.S" {"result0":"v0", "result1":"v1", "instr":"JAL(__divdi3)", "chkzero":"1"} +%def op_div_long_2addr(): +% binopWide2addr(result0="v0", result1="v1", instr="JAL(__divdi3)", chkzero="1") diff --git a/runtime/interpreter/mterp/mips/op_double_to_float.S b/runtime/interpreter/mterp/mips/op_double_to_float.S index 1d32c2e1e4..c3f2fedb03 100644 --- a/runtime/interpreter/mterp/mips/op_double_to_float.S +++ b/runtime/interpreter/mterp/mips/op_double_to_float.S @@ -1 +1,2 @@ -%include "mips/unopNarrower.S" {"instr":"cvt.s.d fv0, fa0"} +%def op_double_to_float(): +% unopNarrower(instr="cvt.s.d fv0, fa0") diff --git a/runtime/interpreter/mterp/mips/op_double_to_int.S b/runtime/interpreter/mterp/mips/op_double_to_int.S index 6d7c6cae61..a522c9c542 100644 --- a/runtime/interpreter/mterp/mips/op_double_to_int.S +++ b/runtime/interpreter/mterp/mips/op_double_to_int.S @@ -1,3 +1,4 @@ +%def op_double_to_int(): /* * double-to-int * diff --git a/runtime/interpreter/mterp/mips/op_double_to_long.S b/runtime/interpreter/mterp/mips/op_double_to_long.S index 459ab7eed0..bfc17f51ce 100644 --- a/runtime/interpreter/mterp/mips/op_double_to_long.S +++ b/runtime/interpreter/mterp/mips/op_double_to_long.S @@ -1,3 +1,4 @@ +%def op_double_to_long(): /* * double-to-long * @@ -40,7 +41,7 @@ GET_INST_OPCODE(t1) # extract opcode from rINST b .L${opcode}_set_vreg #endif -%break +%def op_double_to_long_sister_code(): #ifndef MIPS32REVGE6 .L${opcode}_get_opcode: diff --git a/runtime/interpreter/mterp/mips/op_fill_array_data.S b/runtime/interpreter/mterp/mips/op_fill_array_data.S index c3cd371636..558f68e5b8 100644 --- a/runtime/interpreter/mterp/mips/op_fill_array_data.S +++ b/runtime/interpreter/mterp/mips/op_fill_array_data.S @@ -1,3 +1,4 @@ +%def op_fill_array_data(): /* fill-array-data vAA, +BBBBBBBB */ EXPORT_PC() FETCH(a1, 1) # a1 <- bbbb (lo) diff --git a/runtime/interpreter/mterp/mips/op_filled_new_array.S b/runtime/interpreter/mterp/mips/op_filled_new_array.S index 9511578289..6ac6314bf8 100644 --- a/runtime/interpreter/mterp/mips/op_filled_new_array.S +++ b/runtime/interpreter/mterp/mips/op_filled_new_array.S @@ -1,4 +1,4 @@ -%default { "helper":"MterpFilledNewArray" } +%def op_filled_new_array(helper="MterpFilledNewArray"): /* * Create a new array with elements filled from registers. * diff --git a/runtime/interpreter/mterp/mips/op_filled_new_array_range.S b/runtime/interpreter/mterp/mips/op_filled_new_array_range.S index f8dcb0e037..1667de149a 100644 --- a/runtime/interpreter/mterp/mips/op_filled_new_array_range.S +++ b/runtime/interpreter/mterp/mips/op_filled_new_array_range.S @@ -1 +1,2 @@ -%include "mips/op_filled_new_array.S" { "helper":"MterpFilledNewArrayRange" } +%def op_filled_new_array_range(): +% op_filled_new_array(helper="MterpFilledNewArrayRange") diff --git a/runtime/interpreter/mterp/mips/op_float_to_double.S b/runtime/interpreter/mterp/mips/op_float_to_double.S index 1315255b5c..c0235a88e7 100644 --- a/runtime/interpreter/mterp/mips/op_float_to_double.S +++ b/runtime/interpreter/mterp/mips/op_float_to_double.S @@ -1 +1,2 @@ -%include "mips/funopWider.S" {"instr":"cvt.d.s fv0, fa0"} +%def op_float_to_double(): +% funopWider(instr="cvt.d.s fv0, fa0") diff --git a/runtime/interpreter/mterp/mips/op_float_to_int.S b/runtime/interpreter/mterp/mips/op_float_to_int.S index 26a0988082..2c0c418323 100644 --- a/runtime/interpreter/mterp/mips/op_float_to_int.S +++ b/runtime/interpreter/mterp/mips/op_float_to_int.S @@ -1,3 +1,4 @@ +%def op_float_to_int(): /* * float-to-int * diff --git a/runtime/interpreter/mterp/mips/op_float_to_long.S b/runtime/interpreter/mterp/mips/op_float_to_long.S index b8f8efbdcb..2134e630ae 100644 --- a/runtime/interpreter/mterp/mips/op_float_to_long.S +++ b/runtime/interpreter/mterp/mips/op_float_to_long.S @@ -1,3 +1,4 @@ +%def op_float_to_long(): /* * float-to-long * @@ -38,7 +39,7 @@ GET_INST_OPCODE(t1) # extract opcode from rINST b .L${opcode}_set_vreg #endif -%break +%def op_float_to_long_sister_code(): #ifndef MIPS32REVGE6 .L${opcode}_get_opcode: diff --git a/runtime/interpreter/mterp/mips/op_goto.S b/runtime/interpreter/mterp/mips/op_goto.S index 57182a5b59..8da1339257 100644 --- a/runtime/interpreter/mterp/mips/op_goto.S +++ b/runtime/interpreter/mterp/mips/op_goto.S @@ -1,3 +1,4 @@ +%def op_goto(): /* * Unconditional branch, 8-bit offset. * diff --git a/runtime/interpreter/mterp/mips/op_goto_16.S b/runtime/interpreter/mterp/mips/op_goto_16.S index 06c96cd545..55a055b329 100644 --- a/runtime/interpreter/mterp/mips/op_goto_16.S +++ b/runtime/interpreter/mterp/mips/op_goto_16.S @@ -1,3 +1,4 @@ +%def op_goto_16(): /* * Unconditional branch, 16-bit offset. * diff --git a/runtime/interpreter/mterp/mips/op_goto_32.S b/runtime/interpreter/mterp/mips/op_goto_32.S index ef5bf6bc82..e969bd2048 100644 --- a/runtime/interpreter/mterp/mips/op_goto_32.S +++ b/runtime/interpreter/mterp/mips/op_goto_32.S @@ -1,3 +1,4 @@ +%def op_goto_32(): /* * Unconditional branch, 32-bit offset. * diff --git a/runtime/interpreter/mterp/mips/op_if_eq.S b/runtime/interpreter/mterp/mips/op_if_eq.S index d6f9987186..da58674fd4 100644 --- a/runtime/interpreter/mterp/mips/op_if_eq.S +++ b/runtime/interpreter/mterp/mips/op_if_eq.S @@ -1 +1,2 @@ -%include "mips/bincmp.S" { "condition":"eq" } +%def op_if_eq(): +% bincmp(condition="eq") diff --git a/runtime/interpreter/mterp/mips/op_if_eqz.S b/runtime/interpreter/mterp/mips/op_if_eqz.S index c52b76a755..0639664d47 100644 --- a/runtime/interpreter/mterp/mips/op_if_eqz.S +++ b/runtime/interpreter/mterp/mips/op_if_eqz.S @@ -1 +1,2 @@ -%include "mips/zcmp.S" { "condition":"eq" } +%def op_if_eqz(): +% zcmp(condition="eq") diff --git a/runtime/interpreter/mterp/mips/op_if_ge.S b/runtime/interpreter/mterp/mips/op_if_ge.S index bd06ff5ad4..5b6ed2f994 100644 --- a/runtime/interpreter/mterp/mips/op_if_ge.S +++ b/runtime/interpreter/mterp/mips/op_if_ge.S @@ -1 +1,2 @@ -%include "mips/bincmp.S" { "condition":"ge" } +%def op_if_ge(): +% bincmp(condition="ge") diff --git a/runtime/interpreter/mterp/mips/op_if_gez.S b/runtime/interpreter/mterp/mips/op_if_gez.S index 549231a15f..ea6cda71fb 100644 --- a/runtime/interpreter/mterp/mips/op_if_gez.S +++ b/runtime/interpreter/mterp/mips/op_if_gez.S @@ -1 +1,2 @@ -%include "mips/zcmp.S" { "condition":"ge" } +%def op_if_gez(): +% zcmp(condition="ge") diff --git a/runtime/interpreter/mterp/mips/op_if_gt.S b/runtime/interpreter/mterp/mips/op_if_gt.S index 0be30912ed..201decff1a 100644 --- a/runtime/interpreter/mterp/mips/op_if_gt.S +++ b/runtime/interpreter/mterp/mips/op_if_gt.S @@ -1 +1,2 @@ -%include "mips/bincmp.S" { "condition":"gt" } +%def op_if_gt(): +% bincmp(condition="gt") diff --git a/runtime/interpreter/mterp/mips/op_if_gtz.S b/runtime/interpreter/mterp/mips/op_if_gtz.S index 5c7bcc48b5..1fdbb6e8d2 100644 --- a/runtime/interpreter/mterp/mips/op_if_gtz.S +++ b/runtime/interpreter/mterp/mips/op_if_gtz.S @@ -1 +1,2 @@ -%include "mips/zcmp.S" { "condition":"gt" } +%def op_if_gtz(): +% zcmp(condition="gt") diff --git a/runtime/interpreter/mterp/mips/op_if_le.S b/runtime/interpreter/mterp/mips/op_if_le.S index c35c1a24b7..e6024f2b3e 100644 --- a/runtime/interpreter/mterp/mips/op_if_le.S +++ b/runtime/interpreter/mterp/mips/op_if_le.S @@ -1 +1,2 @@ -%include "mips/bincmp.S" { "condition":"le" } +%def op_if_le(): +% bincmp(condition="le") diff --git a/runtime/interpreter/mterp/mips/op_if_lez.S b/runtime/interpreter/mterp/mips/op_if_lez.S index 3dc6543d90..62c0d2cd39 100644 --- a/runtime/interpreter/mterp/mips/op_if_lez.S +++ b/runtime/interpreter/mterp/mips/op_if_lez.S @@ -1 +1,2 @@ -%include "mips/zcmp.S" { "condition":"le" } +%def op_if_lez(): +% zcmp(condition="le") diff --git a/runtime/interpreter/mterp/mips/op_if_lt.S b/runtime/interpreter/mterp/mips/op_if_lt.S index 3f3386c9d2..4ef22fd798 100644 --- a/runtime/interpreter/mterp/mips/op_if_lt.S +++ b/runtime/interpreter/mterp/mips/op_if_lt.S @@ -1 +1,2 @@ -%include "mips/bincmp.S" { "condition":"lt" } +%def op_if_lt(): +% bincmp(condition="lt") diff --git a/runtime/interpreter/mterp/mips/op_if_ltz.S b/runtime/interpreter/mterp/mips/op_if_ltz.S index e6d6ed6aa6..84b2d0b53a 100644 --- a/runtime/interpreter/mterp/mips/op_if_ltz.S +++ b/runtime/interpreter/mterp/mips/op_if_ltz.S @@ -1 +1,2 @@ -%include "mips/zcmp.S" { "condition":"lt" } +%def op_if_ltz(): +% zcmp(condition="lt") diff --git a/runtime/interpreter/mterp/mips/op_if_ne.S b/runtime/interpreter/mterp/mips/op_if_ne.S index 3d7bf350f1..ec3a688b29 100644 --- a/runtime/interpreter/mterp/mips/op_if_ne.S +++ b/runtime/interpreter/mterp/mips/op_if_ne.S @@ -1 +1,2 @@ -%include "mips/bincmp.S" { "condition":"ne" } +%def op_if_ne(): +% bincmp(condition="ne") diff --git a/runtime/interpreter/mterp/mips/op_if_nez.S b/runtime/interpreter/mterp/mips/op_if_nez.S index d121eae930..7009c3acaa 100644 --- a/runtime/interpreter/mterp/mips/op_if_nez.S +++ b/runtime/interpreter/mterp/mips/op_if_nez.S @@ -1 +1,2 @@ -%include "mips/zcmp.S" { "condition":"ne" } +%def op_if_nez(): +% zcmp(condition="ne") diff --git a/runtime/interpreter/mterp/mips/op_iget.S b/runtime/interpreter/mterp/mips/op_iget.S index e218272196..d09edc0a17 100644 --- a/runtime/interpreter/mterp/mips/op_iget.S +++ b/runtime/interpreter/mterp/mips/op_iget.S @@ -1,2 +1,2 @@ -%default { "is_object":"0", "helper":"MterpIGetU32"} -%include "mips/field.S" { } +%def op_iget(is_object="0", helper="MterpIGetU32"): +% field(helper=helper) diff --git a/runtime/interpreter/mterp/mips/op_iget_boolean.S b/runtime/interpreter/mterp/mips/op_iget_boolean.S index f2ef68d8b2..cb8edeec77 100644 --- a/runtime/interpreter/mterp/mips/op_iget_boolean.S +++ b/runtime/interpreter/mterp/mips/op_iget_boolean.S @@ -1 +1,2 @@ -%include "mips/op_iget.S" { "helper":"MterpIGetU8" } +%def op_iget_boolean(): +% op_iget(helper="MterpIGetU8") diff --git a/runtime/interpreter/mterp/mips/op_iget_boolean_quick.S b/runtime/interpreter/mterp/mips/op_iget_boolean_quick.S index f3032b3d84..f3d2cb1e97 100644 --- a/runtime/interpreter/mterp/mips/op_iget_boolean_quick.S +++ b/runtime/interpreter/mterp/mips/op_iget_boolean_quick.S @@ -1 +1,2 @@ -%include "mips/op_iget_quick.S" { "load":"lbu" } +%def op_iget_boolean_quick(): +% op_iget_quick(load="lbu") diff --git a/runtime/interpreter/mterp/mips/op_iget_byte.S b/runtime/interpreter/mterp/mips/op_iget_byte.S index 0c8fb7cf2c..2b87fb16b5 100644 --- a/runtime/interpreter/mterp/mips/op_iget_byte.S +++ b/runtime/interpreter/mterp/mips/op_iget_byte.S @@ -1 +1,2 @@ -%include "mips/op_iget.S" { "helper":"MterpIGetI8" } +%def op_iget_byte(): +% op_iget(helper="MterpIGetI8") diff --git a/runtime/interpreter/mterp/mips/op_iget_byte_quick.S b/runtime/interpreter/mterp/mips/op_iget_byte_quick.S index d93f84486d..ddb469b3de 100644 --- a/runtime/interpreter/mterp/mips/op_iget_byte_quick.S +++ b/runtime/interpreter/mterp/mips/op_iget_byte_quick.S @@ -1 +1,2 @@ -%include "mips/op_iget_quick.S" { "load":"lb" } +%def op_iget_byte_quick(): +% op_iget_quick(load="lb") diff --git a/runtime/interpreter/mterp/mips/op_iget_char.S b/runtime/interpreter/mterp/mips/op_iget_char.S index 69d04c4fa8..001bd03e2b 100644 --- a/runtime/interpreter/mterp/mips/op_iget_char.S +++ b/runtime/interpreter/mterp/mips/op_iget_char.S @@ -1 +1,2 @@ -%include "mips/op_iget.S" { "helper":"MterpIGetU16" } +%def op_iget_char(): +% op_iget(helper="MterpIGetU16") diff --git a/runtime/interpreter/mterp/mips/op_iget_char_quick.S b/runtime/interpreter/mterp/mips/op_iget_char_quick.S index 6f6d6088e0..ef0b350d4e 100644 --- a/runtime/interpreter/mterp/mips/op_iget_char_quick.S +++ b/runtime/interpreter/mterp/mips/op_iget_char_quick.S @@ -1 +1,2 @@ -%include "mips/op_iget_quick.S" { "load":"lhu" } +%def op_iget_char_quick(): +% op_iget_quick(load="lhu") diff --git a/runtime/interpreter/mterp/mips/op_iget_object.S b/runtime/interpreter/mterp/mips/op_iget_object.S index bea330a14b..4e5f769547 100644 --- a/runtime/interpreter/mterp/mips/op_iget_object.S +++ b/runtime/interpreter/mterp/mips/op_iget_object.S @@ -1 +1,2 @@ -%include "mips/op_iget.S" { "is_object":"1", "helper":"MterpIGetObj" } +%def op_iget_object(): +% op_iget(is_object="1", helper="MterpIGetObj") diff --git a/runtime/interpreter/mterp/mips/op_iget_object_quick.S b/runtime/interpreter/mterp/mips/op_iget_object_quick.S index 95c34d7b3f..8bfd40b44c 100644 --- a/runtime/interpreter/mterp/mips/op_iget_object_quick.S +++ b/runtime/interpreter/mterp/mips/op_iget_object_quick.S @@ -1,3 +1,4 @@ +%def op_iget_object_quick(): /* For: iget-object-quick */ /* op vA, vB, offset@CCCC */ GET_OPB(a2) # a2 <- B diff --git a/runtime/interpreter/mterp/mips/op_iget_quick.S b/runtime/interpreter/mterp/mips/op_iget_quick.S index 46277d30cb..b8892fdb91 100644 --- a/runtime/interpreter/mterp/mips/op_iget_quick.S +++ b/runtime/interpreter/mterp/mips/op_iget_quick.S @@ -1,4 +1,4 @@ -%default { "load":"lw" } +%def op_iget_quick(load="lw"): /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ /* op vA, vB, offset@CCCC */ GET_OPB(a2) # a2 <- B diff --git a/runtime/interpreter/mterp/mips/op_iget_short.S b/runtime/interpreter/mterp/mips/op_iget_short.S index 357c7918e4..a62c4d998f 100644 --- a/runtime/interpreter/mterp/mips/op_iget_short.S +++ b/runtime/interpreter/mterp/mips/op_iget_short.S @@ -1 +1,2 @@ -%include "mips/op_iget.S" { "helper":"MterpIGetI16" } +%def op_iget_short(): +% op_iget(helper="MterpIGetI16") diff --git a/runtime/interpreter/mterp/mips/op_iget_short_quick.S b/runtime/interpreter/mterp/mips/op_iget_short_quick.S index 899a0feb65..5957cb4600 100644 --- a/runtime/interpreter/mterp/mips/op_iget_short_quick.S +++ b/runtime/interpreter/mterp/mips/op_iget_short_quick.S @@ -1 +1,2 @@ -%include "mips/op_iget_quick.S" { "load":"lh" } +%def op_iget_short_quick(): +% op_iget_quick(load="lh") diff --git a/runtime/interpreter/mterp/mips/op_iget_wide.S b/runtime/interpreter/mterp/mips/op_iget_wide.S index 885372a529..9643cc3403 100644 --- a/runtime/interpreter/mterp/mips/op_iget_wide.S +++ b/runtime/interpreter/mterp/mips/op_iget_wide.S @@ -1 +1,2 @@ -%include "mips/op_iget.S" { "helper":"MterpIGetU64" } +%def op_iget_wide(): +% op_iget(helper="MterpIGetU64") diff --git a/runtime/interpreter/mterp/mips/op_iget_wide_quick.S b/runtime/interpreter/mterp/mips/op_iget_wide_quick.S index 128be571f8..5bc90762dd 100644 --- a/runtime/interpreter/mterp/mips/op_iget_wide_quick.S +++ b/runtime/interpreter/mterp/mips/op_iget_wide_quick.S @@ -1,3 +1,4 @@ +%def op_iget_wide_quick(): /* iget-wide-quick vA, vB, offset@CCCC */ GET_OPB(a2) # a2 <- B GET_VREG(a3, a2) # a3 <- object we're operating on diff --git a/runtime/interpreter/mterp/mips/op_instance_of.S b/runtime/interpreter/mterp/mips/op_instance_of.S index 706dcf37a1..9312e72a10 100644 --- a/runtime/interpreter/mterp/mips/op_instance_of.S +++ b/runtime/interpreter/mterp/mips/op_instance_of.S @@ -1,3 +1,4 @@ +%def op_instance_of(): /* * Check to see if an object reference is an instance of a class. * diff --git a/runtime/interpreter/mterp/mips/op_int_to_byte.S b/runtime/interpreter/mterp/mips/op_int_to_byte.S index 9266aab020..584172583a 100644 --- a/runtime/interpreter/mterp/mips/op_int_to_byte.S +++ b/runtime/interpreter/mterp/mips/op_int_to_byte.S @@ -1 +1,2 @@ -%include "mips/unop.S" {"instr":"SEB(a0, a0)"} +%def op_int_to_byte(): +% unop(instr="SEB(a0, a0)") diff --git a/runtime/interpreter/mterp/mips/op_int_to_char.S b/runtime/interpreter/mterp/mips/op_int_to_char.S index 1b74a6e249..7fda63792c 100644 --- a/runtime/interpreter/mterp/mips/op_int_to_char.S +++ b/runtime/interpreter/mterp/mips/op_int_to_char.S @@ -1 +1,2 @@ -%include "mips/unop.S" {"preinstr":"", "instr":"and a0, 0xffff"} +%def op_int_to_char(): +% unop(preinstr="", instr="and a0, 0xffff") diff --git a/runtime/interpreter/mterp/mips/op_int_to_double.S b/runtime/interpreter/mterp/mips/op_int_to_double.S index 89484ce34f..736ebb3053 100644 --- a/runtime/interpreter/mterp/mips/op_int_to_double.S +++ b/runtime/interpreter/mterp/mips/op_int_to_double.S @@ -1 +1,2 @@ -%include "mips/funopWider.S" {"instr":"cvt.d.w fv0, fa0"} +%def op_int_to_double(): +% funopWider(instr="cvt.d.w fv0, fa0") diff --git a/runtime/interpreter/mterp/mips/op_int_to_float.S b/runtime/interpreter/mterp/mips/op_int_to_float.S index d6f4b3609f..45ab4c8f8b 100644 --- a/runtime/interpreter/mterp/mips/op_int_to_float.S +++ b/runtime/interpreter/mterp/mips/op_int_to_float.S @@ -1 +1,2 @@ -%include "mips/funop.S" {"instr":"cvt.s.w fv0, fa0"} +%def op_int_to_float(): +% funop(instr="cvt.s.w fv0, fa0") diff --git a/runtime/interpreter/mterp/mips/op_int_to_long.S b/runtime/interpreter/mterp/mips/op_int_to_long.S index 9907463950..093f181eda 100644 --- a/runtime/interpreter/mterp/mips/op_int_to_long.S +++ b/runtime/interpreter/mterp/mips/op_int_to_long.S @@ -1 +1,2 @@ -%include "mips/unopWider.S" {"instr":"sra a1, a0, 31"} +%def op_int_to_long(): +% unopWider(instr="sra a1, a0, 31") diff --git a/runtime/interpreter/mterp/mips/op_int_to_short.S b/runtime/interpreter/mterp/mips/op_int_to_short.S index 8749cd8717..38bc451886 100644 --- a/runtime/interpreter/mterp/mips/op_int_to_short.S +++ b/runtime/interpreter/mterp/mips/op_int_to_short.S @@ -1 +1,2 @@ -%include "mips/unop.S" {"instr":"SEH(a0, a0)"} +%def op_int_to_short(): +% unop(instr="SEH(a0, a0)") diff --git a/runtime/interpreter/mterp/mips/op_invoke_custom.S b/runtime/interpreter/mterp/mips/op_invoke_custom.S index f9241c43c6..4bba9ee524 100644 --- a/runtime/interpreter/mterp/mips/op_invoke_custom.S +++ b/runtime/interpreter/mterp/mips/op_invoke_custom.S @@ -1 +1,2 @@ -%include "mips/invoke.S" { "helper":"MterpInvokeCustom" } +%def op_invoke_custom(): +% invoke(helper="MterpInvokeCustom") diff --git a/runtime/interpreter/mterp/mips/op_invoke_custom_range.S b/runtime/interpreter/mterp/mips/op_invoke_custom_range.S index 862a614404..57e61af1fa 100644 --- a/runtime/interpreter/mterp/mips/op_invoke_custom_range.S +++ b/runtime/interpreter/mterp/mips/op_invoke_custom_range.S @@ -1 +1,2 @@ -%include "mips/invoke.S" { "helper":"MterpInvokeCustomRange" } +%def op_invoke_custom_range(): +% invoke(helper="MterpInvokeCustomRange") diff --git a/runtime/interpreter/mterp/mips/op_invoke_direct.S b/runtime/interpreter/mterp/mips/op_invoke_direct.S index 1ef198a434..d3139cf39b 100644 --- a/runtime/interpreter/mterp/mips/op_invoke_direct.S +++ b/runtime/interpreter/mterp/mips/op_invoke_direct.S @@ -1 +1,2 @@ -%include "mips/invoke.S" { "helper":"MterpInvokeDirect" } +%def op_invoke_direct(): +% invoke(helper="MterpInvokeDirect") diff --git a/runtime/interpreter/mterp/mips/op_invoke_direct_range.S b/runtime/interpreter/mterp/mips/op_invoke_direct_range.S index af7477f2cd..b4a161f48b 100644 --- a/runtime/interpreter/mterp/mips/op_invoke_direct_range.S +++ b/runtime/interpreter/mterp/mips/op_invoke_direct_range.S @@ -1 +1,2 @@ -%include "mips/invoke.S" { "helper":"MterpInvokeDirectRange" } +%def op_invoke_direct_range(): +% invoke(helper="MterpInvokeDirectRange") diff --git a/runtime/interpreter/mterp/mips/op_invoke_interface.S b/runtime/interpreter/mterp/mips/op_invoke_interface.S index 80a485a077..2e749aa263 100644 --- a/runtime/interpreter/mterp/mips/op_invoke_interface.S +++ b/runtime/interpreter/mterp/mips/op_invoke_interface.S @@ -1 +1,2 @@ -%include "mips/invoke.S" { "helper":"MterpInvokeInterface" } +%def op_invoke_interface(): +% invoke(helper="MterpInvokeInterface") diff --git a/runtime/interpreter/mterp/mips/op_invoke_interface_range.S b/runtime/interpreter/mterp/mips/op_invoke_interface_range.S index 8d725dc204..2989115377 100644 --- a/runtime/interpreter/mterp/mips/op_invoke_interface_range.S +++ b/runtime/interpreter/mterp/mips/op_invoke_interface_range.S @@ -1 +1,2 @@ -%include "mips/invoke.S" { "helper":"MterpInvokeInterfaceRange" } +%def op_invoke_interface_range(): +% invoke(helper="MterpInvokeInterfaceRange") diff --git a/runtime/interpreter/mterp/mips/op_invoke_polymorphic.S b/runtime/interpreter/mterp/mips/op_invoke_polymorphic.S index 85e01e7221..ce61f5aa0e 100644 --- a/runtime/interpreter/mterp/mips/op_invoke_polymorphic.S +++ b/runtime/interpreter/mterp/mips/op_invoke_polymorphic.S @@ -1 +1,2 @@ -%include "mips/invoke_polymorphic.S" { "helper":"MterpInvokePolymorphic" } +%def op_invoke_polymorphic(): +% invoke_polymorphic(helper="MterpInvokePolymorphic") diff --git a/runtime/interpreter/mterp/mips/op_invoke_polymorphic_range.S b/runtime/interpreter/mterp/mips/op_invoke_polymorphic_range.S index ce6397837b..16731bdb40 100644 --- a/runtime/interpreter/mterp/mips/op_invoke_polymorphic_range.S +++ b/runtime/interpreter/mterp/mips/op_invoke_polymorphic_range.S @@ -1 +1,2 @@ -%include "mips/invoke_polymorphic.S" { "helper":"MterpInvokePolymorphicRange" } +%def op_invoke_polymorphic_range(): +% invoke_polymorphic(helper="MterpInvokePolymorphicRange") diff --git a/runtime/interpreter/mterp/mips/op_invoke_static.S b/runtime/interpreter/mterp/mips/op_invoke_static.S index 46253cb3a7..8b104a66b0 100644 --- a/runtime/interpreter/mterp/mips/op_invoke_static.S +++ b/runtime/interpreter/mterp/mips/op_invoke_static.S @@ -1 +1,2 @@ -%include "mips/invoke.S" { "helper":"MterpInvokeStatic" } +%def op_invoke_static(): +% invoke(helper="MterpInvokeStatic") diff --git a/runtime/interpreter/mterp/mips/op_invoke_static_range.S b/runtime/interpreter/mterp/mips/op_invoke_static_range.S index 96abafe41d..e0a546c92b 100644 --- a/runtime/interpreter/mterp/mips/op_invoke_static_range.S +++ b/runtime/interpreter/mterp/mips/op_invoke_static_range.S @@ -1 +1,2 @@ -%include "mips/invoke.S" { "helper":"MterpInvokeStaticRange" } +%def op_invoke_static_range(): +% invoke(helper="MterpInvokeStaticRange") diff --git a/runtime/interpreter/mterp/mips/op_invoke_super.S b/runtime/interpreter/mterp/mips/op_invoke_super.S index 473951bcce..e5921f3d43 100644 --- a/runtime/interpreter/mterp/mips/op_invoke_super.S +++ b/runtime/interpreter/mterp/mips/op_invoke_super.S @@ -1 +1,2 @@ -%include "mips/invoke.S" { "helper":"MterpInvokeSuper" } +%def op_invoke_super(): +% invoke(helper="MterpInvokeSuper") diff --git a/runtime/interpreter/mterp/mips/op_invoke_super_range.S b/runtime/interpreter/mterp/mips/op_invoke_super_range.S index 963ff27ec5..caeafaa13c 100644 --- a/runtime/interpreter/mterp/mips/op_invoke_super_range.S +++ b/runtime/interpreter/mterp/mips/op_invoke_super_range.S @@ -1 +1,2 @@ -%include "mips/invoke.S" { "helper":"MterpInvokeSuperRange" } +%def op_invoke_super_range(): +% invoke(helper="MterpInvokeSuperRange") diff --git a/runtime/interpreter/mterp/mips/op_invoke_virtual.S b/runtime/interpreter/mterp/mips/op_invoke_virtual.S index ea51e98abc..8767741f28 100644 --- a/runtime/interpreter/mterp/mips/op_invoke_virtual.S +++ b/runtime/interpreter/mterp/mips/op_invoke_virtual.S @@ -1 +1,2 @@ -%include "mips/invoke.S" { "helper":"MterpInvokeVirtual" } +%def op_invoke_virtual(): +% invoke(helper="MterpInvokeVirtual") diff --git a/runtime/interpreter/mterp/mips/op_invoke_virtual_quick.S b/runtime/interpreter/mterp/mips/op_invoke_virtual_quick.S index 0c00091219..ea72c171ec 100644 --- a/runtime/interpreter/mterp/mips/op_invoke_virtual_quick.S +++ b/runtime/interpreter/mterp/mips/op_invoke_virtual_quick.S @@ -1 +1,2 @@ -%include "mips/invoke.S" { "helper":"MterpInvokeVirtualQuick" } +%def op_invoke_virtual_quick(): +% invoke(helper="MterpInvokeVirtualQuick") diff --git a/runtime/interpreter/mterp/mips/op_invoke_virtual_range.S b/runtime/interpreter/mterp/mips/op_invoke_virtual_range.S index 82201e726e..baa0779593 100644 --- a/runtime/interpreter/mterp/mips/op_invoke_virtual_range.S +++ b/runtime/interpreter/mterp/mips/op_invoke_virtual_range.S @@ -1 +1,2 @@ -%include "mips/invoke.S" { "helper":"MterpInvokeVirtualRange" } +%def op_invoke_virtual_range(): +% invoke(helper="MterpInvokeVirtualRange") diff --git a/runtime/interpreter/mterp/mips/op_invoke_virtual_range_quick.S b/runtime/interpreter/mterp/mips/op_invoke_virtual_range_quick.S index c783675dae..1d961a0781 100644 --- a/runtime/interpreter/mterp/mips/op_invoke_virtual_range_quick.S +++ b/runtime/interpreter/mterp/mips/op_invoke_virtual_range_quick.S @@ -1 +1,2 @@ -%include "mips/invoke.S" { "helper":"MterpInvokeVirtualQuickRange" } +%def op_invoke_virtual_range_quick(): +% invoke(helper="MterpInvokeVirtualQuickRange") diff --git a/runtime/interpreter/mterp/mips/op_iput.S b/runtime/interpreter/mterp/mips/op_iput.S index efbdfbad78..e5351baf55 100644 --- a/runtime/interpreter/mterp/mips/op_iput.S +++ b/runtime/interpreter/mterp/mips/op_iput.S @@ -1,2 +1,2 @@ -%default { "is_object":"0", "helper":"MterpIPutU32" } -%include "mips/field.S" { } +%def op_iput(is_object="0", helper="MterpIPutU32"): +% field(helper=helper) diff --git a/runtime/interpreter/mterp/mips/op_iput_boolean.S b/runtime/interpreter/mterp/mips/op_iput_boolean.S index 55ac4cedaa..9eb849877b 100644 --- a/runtime/interpreter/mterp/mips/op_iput_boolean.S +++ b/runtime/interpreter/mterp/mips/op_iput_boolean.S @@ -1 +1,2 @@ -%include "mips/op_iput.S" { "helper":"MterpIPutU8" } +%def op_iput_boolean(): +% op_iput(helper="MterpIPutU8") diff --git a/runtime/interpreter/mterp/mips/op_iput_boolean_quick.S b/runtime/interpreter/mterp/mips/op_iput_boolean_quick.S index 7d5caf6d6a..3d818a5a69 100644 --- a/runtime/interpreter/mterp/mips/op_iput_boolean_quick.S +++ b/runtime/interpreter/mterp/mips/op_iput_boolean_quick.S @@ -1 +1,2 @@ -%include "mips/op_iput_quick.S" { "store":"sb" } +%def op_iput_boolean_quick(): +% op_iput_quick(store="sb") diff --git a/runtime/interpreter/mterp/mips/op_iput_byte.S b/runtime/interpreter/mterp/mips/op_iput_byte.S index 61e489be11..4b74f9fb0e 100644 --- a/runtime/interpreter/mterp/mips/op_iput_byte.S +++ b/runtime/interpreter/mterp/mips/op_iput_byte.S @@ -1 +1,2 @@ -%include "mips/op_iput.S" { "helper":"MterpIPutI8" } +%def op_iput_byte(): +% op_iput(helper="MterpIPutI8") diff --git a/runtime/interpreter/mterp/mips/op_iput_byte_quick.S b/runtime/interpreter/mterp/mips/op_iput_byte_quick.S index 7d5caf6d6a..06dc24e095 100644 --- a/runtime/interpreter/mterp/mips/op_iput_byte_quick.S +++ b/runtime/interpreter/mterp/mips/op_iput_byte_quick.S @@ -1 +1,2 @@ -%include "mips/op_iput_quick.S" { "store":"sb" } +%def op_iput_byte_quick(): +% op_iput_quick(store="sb") diff --git a/runtime/interpreter/mterp/mips/op_iput_char.S b/runtime/interpreter/mterp/mips/op_iput_char.S index 2caad1e0a6..64a249fc12 100644 --- a/runtime/interpreter/mterp/mips/op_iput_char.S +++ b/runtime/interpreter/mterp/mips/op_iput_char.S @@ -1 +1,2 @@ -%include "mips/op_iput.S" { "helper":"MterpIPutU16" } +%def op_iput_char(): +% op_iput(helper="MterpIPutU16") diff --git a/runtime/interpreter/mterp/mips/op_iput_char_quick.S b/runtime/interpreter/mterp/mips/op_iput_char_quick.S index 4bc84eb581..3b6af5b9fe 100644 --- a/runtime/interpreter/mterp/mips/op_iput_char_quick.S +++ b/runtime/interpreter/mterp/mips/op_iput_char_quick.S @@ -1 +1,2 @@ -%include "mips/op_iput_quick.S" { "store":"sh" } +%def op_iput_char_quick(): +% op_iput_quick(store="sh") diff --git a/runtime/interpreter/mterp/mips/op_iput_object.S b/runtime/interpreter/mterp/mips/op_iput_object.S index 6f7e7b760f..131edd5dbd 100644 --- a/runtime/interpreter/mterp/mips/op_iput_object.S +++ b/runtime/interpreter/mterp/mips/op_iput_object.S @@ -1 +1,2 @@ -%include "mips/op_iput.S" { "is_object":"1", "helper":"MterpIPutObj" } +%def op_iput_object(): +% op_iput(is_object="1", helper="MterpIPutObj") diff --git a/runtime/interpreter/mterp/mips/op_iput_object_quick.S b/runtime/interpreter/mterp/mips/op_iput_object_quick.S index 82044f51c8..bb3cbe88ec 100644 --- a/runtime/interpreter/mterp/mips/op_iput_object_quick.S +++ b/runtime/interpreter/mterp/mips/op_iput_object_quick.S @@ -1,3 +1,4 @@ +%def op_iput_object_quick(): /* For: iput-object-quick */ /* op vA, vB, offset@CCCC */ EXPORT_PC() diff --git a/runtime/interpreter/mterp/mips/op_iput_quick.S b/runtime/interpreter/mterp/mips/op_iput_quick.S index d9753b1409..55067bea22 100644 --- a/runtime/interpreter/mterp/mips/op_iput_quick.S +++ b/runtime/interpreter/mterp/mips/op_iput_quick.S @@ -1,4 +1,4 @@ -%default { "store":"sw" } +%def op_iput_quick(store="sw"): /* For: iput-quick, iput-object-quick */ /* op vA, vB, offset@CCCC */ GET_OPB(a2) # a2 <- B diff --git a/runtime/interpreter/mterp/mips/op_iput_short.S b/runtime/interpreter/mterp/mips/op_iput_short.S index 414a15bd70..e631a3b259 100644 --- a/runtime/interpreter/mterp/mips/op_iput_short.S +++ b/runtime/interpreter/mterp/mips/op_iput_short.S @@ -1 +1,2 @@ -%include "mips/op_iput.S" { "helper":"MterpIPutI16" } +%def op_iput_short(): +% op_iput(helper="MterpIPutI16") diff --git a/runtime/interpreter/mterp/mips/op_iput_short_quick.S b/runtime/interpreter/mterp/mips/op_iput_short_quick.S index 4bc84eb581..fade093fc1 100644 --- a/runtime/interpreter/mterp/mips/op_iput_short_quick.S +++ b/runtime/interpreter/mterp/mips/op_iput_short_quick.S @@ -1 +1,2 @@ -%include "mips/op_iput_quick.S" { "store":"sh" } +%def op_iput_short_quick(): +% op_iput_quick(store="sh") diff --git a/runtime/interpreter/mterp/mips/op_iput_wide.S b/runtime/interpreter/mterp/mips/op_iput_wide.S index fc862e4fa7..2f34fd39f9 100644 --- a/runtime/interpreter/mterp/mips/op_iput_wide.S +++ b/runtime/interpreter/mterp/mips/op_iput_wide.S @@ -1 +1,2 @@ -%include "mips/op_iput.S" { "helper":"MterpIPutU64" } +%def op_iput_wide(): +% op_iput(helper="MterpIPutU64") diff --git a/runtime/interpreter/mterp/mips/op_iput_wide_quick.S b/runtime/interpreter/mterp/mips/op_iput_wide_quick.S index 0eb228d005..7b8e632be0 100644 --- a/runtime/interpreter/mterp/mips/op_iput_wide_quick.S +++ b/runtime/interpreter/mterp/mips/op_iput_wide_quick.S @@ -1,3 +1,4 @@ +%def op_iput_wide_quick(): /* iput-wide-quick vA, vB, offset@CCCC */ GET_OPA4(a0) # a0 <- A(+) GET_OPB(a1) # a1 <- B diff --git a/runtime/interpreter/mterp/mips/op_long_to_double.S b/runtime/interpreter/mterp/mips/op_long_to_double.S index 153f58210a..5dfc76b0cf 100644 --- a/runtime/interpreter/mterp/mips/op_long_to_double.S +++ b/runtime/interpreter/mterp/mips/op_long_to_double.S @@ -1,3 +1,4 @@ +%def op_long_to_double(): /* * long-to-double */ diff --git a/runtime/interpreter/mterp/mips/op_long_to_float.S b/runtime/interpreter/mterp/mips/op_long_to_float.S index dd1ab81f4d..fcf2a2e22a 100644 --- a/runtime/interpreter/mterp/mips/op_long_to_float.S +++ b/runtime/interpreter/mterp/mips/op_long_to_float.S @@ -1,3 +1,4 @@ +%def op_long_to_float(): /* * long-to-float */ diff --git a/runtime/interpreter/mterp/mips/op_long_to_int.S b/runtime/interpreter/mterp/mips/op_long_to_int.S index 949c180f31..eacb8f59ec 100644 --- a/runtime/interpreter/mterp/mips/op_long_to_int.S +++ b/runtime/interpreter/mterp/mips/op_long_to_int.S @@ -1,2 +1,3 @@ +%def op_long_to_int(): /* we ignore the high word, making this equivalent to a 32-bit reg move */ -%include "mips/op_move.S" +% op_move() diff --git a/runtime/interpreter/mterp/mips/op_monitor_enter.S b/runtime/interpreter/mterp/mips/op_monitor_enter.S index 20d90294ac..66e3af5847 100644 --- a/runtime/interpreter/mterp/mips/op_monitor_enter.S +++ b/runtime/interpreter/mterp/mips/op_monitor_enter.S @@ -1,3 +1,4 @@ +%def op_monitor_enter(): /* * Synchronize on an object. */ diff --git a/runtime/interpreter/mterp/mips/op_monitor_exit.S b/runtime/interpreter/mterp/mips/op_monitor_exit.S index 1eadff923b..d32d75ccc0 100644 --- a/runtime/interpreter/mterp/mips/op_monitor_exit.S +++ b/runtime/interpreter/mterp/mips/op_monitor_exit.S @@ -1,3 +1,4 @@ +%def op_monitor_exit(): /* * Unlock an object. * diff --git a/runtime/interpreter/mterp/mips/op_move.S b/runtime/interpreter/mterp/mips/op_move.S index 547ea3a185..a0c1c31016 100644 --- a/runtime/interpreter/mterp/mips/op_move.S +++ b/runtime/interpreter/mterp/mips/op_move.S @@ -1,4 +1,4 @@ -%default { "is_object":"0" } +%def op_move(is_object="0"): /* for move, move-object, long-to-int */ /* op vA, vB */ GET_OPB(a1) # a1 <- B from 15:12 diff --git a/runtime/interpreter/mterp/mips/op_move_16.S b/runtime/interpreter/mterp/mips/op_move_16.S index 91b73996b5..273858ec5a 100644 --- a/runtime/interpreter/mterp/mips/op_move_16.S +++ b/runtime/interpreter/mterp/mips/op_move_16.S @@ -1,4 +1,4 @@ -%default { "is_object":"0" } +%def op_move_16(is_object="0"): /* for: move/16, move-object/16 */ /* op vAAAA, vBBBB */ FETCH(a1, 2) # a1 <- BBBB diff --git a/runtime/interpreter/mterp/mips/op_move_exception.S b/runtime/interpreter/mterp/mips/op_move_exception.S index f1bece7be8..80c554b3c1 100644 --- a/runtime/interpreter/mterp/mips/op_move_exception.S +++ b/runtime/interpreter/mterp/mips/op_move_exception.S @@ -1,3 +1,4 @@ +%def op_move_exception(): /* move-exception vAA */ GET_OPA(a2) # a2 <- AA lw a3, THREAD_EXCEPTION_OFFSET(rSELF) # get exception obj diff --git a/runtime/interpreter/mterp/mips/op_move_from16.S b/runtime/interpreter/mterp/mips/op_move_from16.S index 90c25c9705..7306ed85ad 100644 --- a/runtime/interpreter/mterp/mips/op_move_from16.S +++ b/runtime/interpreter/mterp/mips/op_move_from16.S @@ -1,4 +1,4 @@ -%default { "is_object":"0" } +%def op_move_from16(is_object="0"): /* for: move/from16, move-object/from16 */ /* op vAA, vBBBB */ FETCH(a1, 1) # a1 <- BBBB diff --git a/runtime/interpreter/mterp/mips/op_move_object.S b/runtime/interpreter/mterp/mips/op_move_object.S index 9420ff359f..dbb4d59710 100644 --- a/runtime/interpreter/mterp/mips/op_move_object.S +++ b/runtime/interpreter/mterp/mips/op_move_object.S @@ -1 +1,2 @@ -%include "mips/op_move.S" {"is_object":"1"} +%def op_move_object(): +% op_move(is_object="1") diff --git a/runtime/interpreter/mterp/mips/op_move_object_16.S b/runtime/interpreter/mterp/mips/op_move_object_16.S index d6454c222d..40120379d5 100644 --- a/runtime/interpreter/mterp/mips/op_move_object_16.S +++ b/runtime/interpreter/mterp/mips/op_move_object_16.S @@ -1 +1,2 @@ -%include "mips/op_move_16.S" {"is_object":"1"} +%def op_move_object_16(): +% op_move_16(is_object="1") diff --git a/runtime/interpreter/mterp/mips/op_move_object_from16.S b/runtime/interpreter/mterp/mips/op_move_object_from16.S index db0aca1f83..c82698e81e 100644 --- a/runtime/interpreter/mterp/mips/op_move_object_from16.S +++ b/runtime/interpreter/mterp/mips/op_move_object_from16.S @@ -1 +1,2 @@ -%include "mips/op_move_from16.S" {"is_object":"1"} +%def op_move_object_from16(): +% op_move_from16(is_object="1") diff --git a/runtime/interpreter/mterp/mips/op_move_result.S b/runtime/interpreter/mterp/mips/op_move_result.S index a4d5bfef6a..20651d9185 100644 --- a/runtime/interpreter/mterp/mips/op_move_result.S +++ b/runtime/interpreter/mterp/mips/op_move_result.S @@ -1,4 +1,4 @@ -%default { "is_object":"0" } +%def op_move_result(is_object="0"): /* for: move-result, move-result-object */ /* op vAA */ GET_OPA(a2) # a2 <- AA diff --git a/runtime/interpreter/mterp/mips/op_move_result_object.S b/runtime/interpreter/mterp/mips/op_move_result_object.S index fcbffee281..87aea2646a 100644 --- a/runtime/interpreter/mterp/mips/op_move_result_object.S +++ b/runtime/interpreter/mterp/mips/op_move_result_object.S @@ -1 +1,2 @@ -%include "mips/op_move_result.S" {"is_object":"1"} +%def op_move_result_object(): +% op_move_result(is_object="1") diff --git a/runtime/interpreter/mterp/mips/op_move_result_wide.S b/runtime/interpreter/mterp/mips/op_move_result_wide.S index 1259218c34..205f174120 100644 --- a/runtime/interpreter/mterp/mips/op_move_result_wide.S +++ b/runtime/interpreter/mterp/mips/op_move_result_wide.S @@ -1,3 +1,4 @@ +%def op_move_result_wide(): /* move-result-wide vAA */ GET_OPA(a2) # a2 <- AA lw a3, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType diff --git a/runtime/interpreter/mterp/mips/op_move_wide.S b/runtime/interpreter/mterp/mips/op_move_wide.S index 01d094914b..ad71022108 100644 --- a/runtime/interpreter/mterp/mips/op_move_wide.S +++ b/runtime/interpreter/mterp/mips/op_move_wide.S @@ -1,3 +1,4 @@ +%def op_move_wide(): /* move-wide vA, vB */ /* NOTE: regs can overlap, e.g. "move v6, v7" or "move v7, v6" */ GET_OPA4(a2) # a2 <- A(+) diff --git a/runtime/interpreter/mterp/mips/op_move_wide_16.S b/runtime/interpreter/mterp/mips/op_move_wide_16.S index 587ba04b9d..60d41a5734 100644 --- a/runtime/interpreter/mterp/mips/op_move_wide_16.S +++ b/runtime/interpreter/mterp/mips/op_move_wide_16.S @@ -1,3 +1,4 @@ +%def op_move_wide_16(): /* move-wide/16 vAAAA, vBBBB */ /* NOTE: regs can overlap, e.g. "move v6, v7" or "move v7, v6" */ FETCH(a3, 2) # a3 <- BBBB diff --git a/runtime/interpreter/mterp/mips/op_move_wide_from16.S b/runtime/interpreter/mterp/mips/op_move_wide_from16.S index 5003fbdb24..0a970ef611 100644 --- a/runtime/interpreter/mterp/mips/op_move_wide_from16.S +++ b/runtime/interpreter/mterp/mips/op_move_wide_from16.S @@ -1,3 +1,4 @@ +%def op_move_wide_from16(): /* move-wide/from16 vAA, vBBBB */ /* NOTE: regs can overlap, e.g. "move v6, v7" or "move v7, v6" */ FETCH(a3, 1) # a3 <- BBBB diff --git a/runtime/interpreter/mterp/mips/op_mul_double.S b/runtime/interpreter/mterp/mips/op_mul_double.S index 44a473bac1..609a462a32 100644 --- a/runtime/interpreter/mterp/mips/op_mul_double.S +++ b/runtime/interpreter/mterp/mips/op_mul_double.S @@ -1 +1,2 @@ -%include "mips/fbinopWide.S" {"instr":"mul.d fv0, fa0, fa1"} +%def op_mul_double(): +% fbinopWide(instr="mul.d fv0, fa0, fa1") diff --git a/runtime/interpreter/mterp/mips/op_mul_double_2addr.S b/runtime/interpreter/mterp/mips/op_mul_double_2addr.S index 4e5c230bc5..ae0b13f1e9 100644 --- a/runtime/interpreter/mterp/mips/op_mul_double_2addr.S +++ b/runtime/interpreter/mterp/mips/op_mul_double_2addr.S @@ -1 +1,2 @@ -%include "mips/fbinopWide2addr.S" {"instr":"mul.d fv0, fa0, fa1"} +%def op_mul_double_2addr(): +% fbinopWide2addr(instr="mul.d fv0, fa0, fa1") diff --git a/runtime/interpreter/mterp/mips/op_mul_float.S b/runtime/interpreter/mterp/mips/op_mul_float.S index abc9390543..e4a578e7a9 100644 --- a/runtime/interpreter/mterp/mips/op_mul_float.S +++ b/runtime/interpreter/mterp/mips/op_mul_float.S @@ -1 +1,2 @@ -%include "mips/fbinop.S" {"instr":"mul.s fv0, fa0, fa1"} +%def op_mul_float(): +% fbinop(instr="mul.s fv0, fa0, fa1") diff --git a/runtime/interpreter/mterp/mips/op_mul_float_2addr.S b/runtime/interpreter/mterp/mips/op_mul_float_2addr.S index 2469109518..38b2a88ebd 100644 --- a/runtime/interpreter/mterp/mips/op_mul_float_2addr.S +++ b/runtime/interpreter/mterp/mips/op_mul_float_2addr.S @@ -1 +1,2 @@ -%include "mips/fbinop2addr.S" {"instr":"mul.s fv0, fa0, fa1"} +%def op_mul_float_2addr(): +% fbinop2addr(instr="mul.s fv0, fa0, fa1") diff --git a/runtime/interpreter/mterp/mips/op_mul_int.S b/runtime/interpreter/mterp/mips/op_mul_int.S index 266823c2c7..34e42f0783 100644 --- a/runtime/interpreter/mterp/mips/op_mul_int.S +++ b/runtime/interpreter/mterp/mips/op_mul_int.S @@ -1 +1,2 @@ -%include "mips/binop.S" {"instr":"mul a0, a0, a1"} +%def op_mul_int(): +% binop(instr="mul a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_mul_int_2addr.S b/runtime/interpreter/mterp/mips/op_mul_int_2addr.S index b7dc5d3fb1..0224a6e2c1 100644 --- a/runtime/interpreter/mterp/mips/op_mul_int_2addr.S +++ b/runtime/interpreter/mterp/mips/op_mul_int_2addr.S @@ -1 +1,2 @@ -%include "mips/binop2addr.S" {"instr":"mul a0, a0, a1"} +%def op_mul_int_2addr(): +% binop2addr(instr="mul a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_mul_int_lit16.S b/runtime/interpreter/mterp/mips/op_mul_int_lit16.S index fb4c8ec27d..935d632e11 100644 --- a/runtime/interpreter/mterp/mips/op_mul_int_lit16.S +++ b/runtime/interpreter/mterp/mips/op_mul_int_lit16.S @@ -1 +1,2 @@ -%include "mips/binopLit16.S" {"instr":"mul a0, a0, a1"} +%def op_mul_int_lit16(): +% binopLit16(instr="mul a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_mul_int_lit8.S b/runtime/interpreter/mterp/mips/op_mul_int_lit8.S index 6d2e7ded0c..4a2bfca5c1 100644 --- a/runtime/interpreter/mterp/mips/op_mul_int_lit8.S +++ b/runtime/interpreter/mterp/mips/op_mul_int_lit8.S @@ -1 +1,2 @@ -%include "mips/binopLit8.S" {"instr":"mul a0, a0, a1"} +%def op_mul_int_lit8(): +% binopLit8(instr="mul a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_mul_long.S b/runtime/interpreter/mterp/mips/op_mul_long.S index 74b049a028..ae31e1910f 100644 --- a/runtime/interpreter/mterp/mips/op_mul_long.S +++ b/runtime/interpreter/mterp/mips/op_mul_long.S @@ -1,3 +1,4 @@ +%def op_mul_long(): /* * Signed 64-bit integer multiply. * a1 a0 @@ -35,7 +36,7 @@ GET_OPA(a0) # a0 <- AA FETCH_ADVANCE_INST(2) # advance rPC, load rINST b .L${opcode}_finish -%break +%def op_mul_long_sister_code(): .L${opcode}_finish: GET_INST_OPCODE(t0) # extract opcode from rINST diff --git a/runtime/interpreter/mterp/mips/op_mul_long_2addr.S b/runtime/interpreter/mterp/mips/op_mul_long_2addr.S index 683b055e84..ef53254180 100644 --- a/runtime/interpreter/mterp/mips/op_mul_long_2addr.S +++ b/runtime/interpreter/mterp/mips/op_mul_long_2addr.S @@ -1,3 +1,4 @@ +%def op_mul_long_2addr(): /* * See op_mul_long.S for more details */ diff --git a/runtime/interpreter/mterp/mips/op_neg_double.S b/runtime/interpreter/mterp/mips/op_neg_double.S index 89cc918b80..b53ccbb63a 100644 --- a/runtime/interpreter/mterp/mips/op_neg_double.S +++ b/runtime/interpreter/mterp/mips/op_neg_double.S @@ -1 +1,2 @@ -%include "mips/unopWide.S" {"instr":"addu a1, a1, 0x80000000"} +%def op_neg_double(): +% unopWide(instr="addu a1, a1, 0x80000000") diff --git a/runtime/interpreter/mterp/mips/op_neg_float.S b/runtime/interpreter/mterp/mips/op_neg_float.S index e702755f11..655d827d22 100644 --- a/runtime/interpreter/mterp/mips/op_neg_float.S +++ b/runtime/interpreter/mterp/mips/op_neg_float.S @@ -1 +1,2 @@ -%include "mips/unop.S" {"instr":"addu a0, a0, 0x80000000"} +%def op_neg_float(): +% unop(instr="addu a0, a0, 0x80000000") diff --git a/runtime/interpreter/mterp/mips/op_neg_int.S b/runtime/interpreter/mterp/mips/op_neg_int.S index 4461731465..acc3440a33 100644 --- a/runtime/interpreter/mterp/mips/op_neg_int.S +++ b/runtime/interpreter/mterp/mips/op_neg_int.S @@ -1 +1,2 @@ -%include "mips/unop.S" {"instr":"negu a0, a0"} +%def op_neg_int(): +% unop(instr="negu a0, a0") diff --git a/runtime/interpreter/mterp/mips/op_neg_long.S b/runtime/interpreter/mterp/mips/op_neg_long.S index 71e60f59be..9108b2b0ed 100644 --- a/runtime/interpreter/mterp/mips/op_neg_long.S +++ b/runtime/interpreter/mterp/mips/op_neg_long.S @@ -1 +1,2 @@ -%include "mips/unopWide.S" {"result0":"v0", "result1":"v1", "preinstr":"negu v0, a0", "instr":"negu v1, a1; sltu a0, zero, v0; subu v1, v1, a0"} +%def op_neg_long(): +% unopWide(result0="v0", result1="v1", preinstr="negu v0, a0", instr="negu v1, a1; sltu a0, zero, v0; subu v1, v1, a0") diff --git a/runtime/interpreter/mterp/mips/op_new_array.S b/runtime/interpreter/mterp/mips/op_new_array.S index 4a6512d7c5..6ae04cc32b 100644 --- a/runtime/interpreter/mterp/mips/op_new_array.S +++ b/runtime/interpreter/mterp/mips/op_new_array.S @@ -1,3 +1,4 @@ +%def op_new_array(): /* * Allocate an array of objects, specified with the array class * and a count. diff --git a/runtime/interpreter/mterp/mips/op_new_instance.S b/runtime/interpreter/mterp/mips/op_new_instance.S index 3c9e83f9b8..0c98c93aaa 100644 --- a/runtime/interpreter/mterp/mips/op_new_instance.S +++ b/runtime/interpreter/mterp/mips/op_new_instance.S @@ -1,3 +1,4 @@ +%def op_new_instance(): /* * Create a new instance of a class. */ diff --git a/runtime/interpreter/mterp/mips/op_nop.S b/runtime/interpreter/mterp/mips/op_nop.S index 3565631e03..10f607478f 100644 --- a/runtime/interpreter/mterp/mips/op_nop.S +++ b/runtime/interpreter/mterp/mips/op_nop.S @@ -1,3 +1,4 @@ +%def op_nop(): FETCH_ADVANCE_INST(1) # advance rPC, load rINST GET_INST_OPCODE(t0) # extract opcode from rINST GOTO_OPCODE(t0) # jump to next instruction diff --git a/runtime/interpreter/mterp/mips/op_not_int.S b/runtime/interpreter/mterp/mips/op_not_int.S index 55d8cc11d1..7dc7aebc5c 100644 --- a/runtime/interpreter/mterp/mips/op_not_int.S +++ b/runtime/interpreter/mterp/mips/op_not_int.S @@ -1 +1,2 @@ -%include "mips/unop.S" {"instr":"not a0, a0"} +%def op_not_int(): +% unop(instr="not a0, a0") diff --git a/runtime/interpreter/mterp/mips/op_not_long.S b/runtime/interpreter/mterp/mips/op_not_long.S index 9e7c95bcea..0bca4bde59 100644 --- a/runtime/interpreter/mterp/mips/op_not_long.S +++ b/runtime/interpreter/mterp/mips/op_not_long.S @@ -1 +1,2 @@ -%include "mips/unopWide.S" {"preinstr":"not a0, a0", "instr":"not a1, a1"} +%def op_not_long(): +% unopWide(preinstr="not a0, a0", instr="not a1, a1") diff --git a/runtime/interpreter/mterp/mips/op_or_int.S b/runtime/interpreter/mterp/mips/op_or_int.S index c7ce760a73..df60be5896 100644 --- a/runtime/interpreter/mterp/mips/op_or_int.S +++ b/runtime/interpreter/mterp/mips/op_or_int.S @@ -1 +1,2 @@ -%include "mips/binop.S" {"instr":"or a0, a0, a1"} +%def op_or_int(): +% binop(instr="or a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_or_int_2addr.S b/runtime/interpreter/mterp/mips/op_or_int_2addr.S index 192d611e8d..c202e6799b 100644 --- a/runtime/interpreter/mterp/mips/op_or_int_2addr.S +++ b/runtime/interpreter/mterp/mips/op_or_int_2addr.S @@ -1 +1,2 @@ -%include "mips/binop2addr.S" {"instr":"or a0, a0, a1"} +%def op_or_int_2addr(): +% binop2addr(instr="or a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_or_int_lit16.S b/runtime/interpreter/mterp/mips/op_or_int_lit16.S index f4ef75fff8..09961e8845 100644 --- a/runtime/interpreter/mterp/mips/op_or_int_lit16.S +++ b/runtime/interpreter/mterp/mips/op_or_int_lit16.S @@ -1 +1,2 @@ -%include "mips/binopLit16.S" {"instr":"or a0, a0, a1"} +%def op_or_int_lit16(): +% binopLit16(instr="or a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_or_int_lit8.S b/runtime/interpreter/mterp/mips/op_or_int_lit8.S index f6212e217d..1bd6809d90 100644 --- a/runtime/interpreter/mterp/mips/op_or_int_lit8.S +++ b/runtime/interpreter/mterp/mips/op_or_int_lit8.S @@ -1 +1,2 @@ -%include "mips/binopLit8.S" {"instr":"or a0, a0, a1"} +%def op_or_int_lit8(): +% binopLit8(instr="or a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_or_long.S b/runtime/interpreter/mterp/mips/op_or_long.S index 0f94486e42..5f53085e0d 100644 --- a/runtime/interpreter/mterp/mips/op_or_long.S +++ b/runtime/interpreter/mterp/mips/op_or_long.S @@ -1 +1,2 @@ -%include "mips/binopWide.S" {"preinstr":"or a0, a0, a2", "instr":"or a1, a1, a3"} +%def op_or_long(): +% binopWide(preinstr="or a0, a0, a2", instr="or a1, a1, a3") diff --git a/runtime/interpreter/mterp/mips/op_or_long_2addr.S b/runtime/interpreter/mterp/mips/op_or_long_2addr.S index 43c3d05d41..f9b2f9c13e 100644 --- a/runtime/interpreter/mterp/mips/op_or_long_2addr.S +++ b/runtime/interpreter/mterp/mips/op_or_long_2addr.S @@ -1 +1,2 @@ -%include "mips/binopWide2addr.S" {"preinstr":"or a0, a0, a2", "instr":"or a1, a1, a3"} +%def op_or_long_2addr(): +% binopWide2addr(preinstr="or a0, a0, a2", instr="or a1, a1, a3") diff --git a/runtime/interpreter/mterp/mips/op_packed_switch.S b/runtime/interpreter/mterp/mips/op_packed_switch.S index 0a1ff989c1..e18a652f65 100644 --- a/runtime/interpreter/mterp/mips/op_packed_switch.S +++ b/runtime/interpreter/mterp/mips/op_packed_switch.S @@ -1,4 +1,4 @@ -%default { "func":"MterpDoPackedSwitch" } +%def op_packed_switch(func="MterpDoPackedSwitch"): /* * Handle a packed-switch or sparse-switch instruction. In both cases * we decode it and hand it off to a helper function. diff --git a/runtime/interpreter/mterp/mips/op_rem_double.S b/runtime/interpreter/mterp/mips/op_rem_double.S index a6890a8029..99857a383f 100644 --- a/runtime/interpreter/mterp/mips/op_rem_double.S +++ b/runtime/interpreter/mterp/mips/op_rem_double.S @@ -1 +1,2 @@ -%include "mips/fbinopWide.S" {"instr":"JAL(fmod)"} +%def op_rem_double(): +% fbinopWide(instr="JAL(fmod)") diff --git a/runtime/interpreter/mterp/mips/op_rem_double_2addr.S b/runtime/interpreter/mterp/mips/op_rem_double_2addr.S index a24e1604fa..cf2d3a7456 100644 --- a/runtime/interpreter/mterp/mips/op_rem_double_2addr.S +++ b/runtime/interpreter/mterp/mips/op_rem_double_2addr.S @@ -1 +1,2 @@ -%include "mips/fbinopWide2addr.S" {"instr":"JAL(fmod)"} +%def op_rem_double_2addr(): +% fbinopWide2addr(instr="JAL(fmod)") diff --git a/runtime/interpreter/mterp/mips/op_rem_float.S b/runtime/interpreter/mterp/mips/op_rem_float.S index ac3d50ce75..2295ae58ed 100644 --- a/runtime/interpreter/mterp/mips/op_rem_float.S +++ b/runtime/interpreter/mterp/mips/op_rem_float.S @@ -1 +1,2 @@ -%include "mips/fbinop.S" {"instr":"JAL(fmodf)"} +%def op_rem_float(): +% fbinop(instr="JAL(fmodf)") diff --git a/runtime/interpreter/mterp/mips/op_rem_float_2addr.S b/runtime/interpreter/mterp/mips/op_rem_float_2addr.S index 7f0a9320c8..9f6abee390 100644 --- a/runtime/interpreter/mterp/mips/op_rem_float_2addr.S +++ b/runtime/interpreter/mterp/mips/op_rem_float_2addr.S @@ -1 +1,2 @@ -%include "mips/fbinop2addr.S" {"instr":"JAL(fmodf)"} +%def op_rem_float_2addr(): +% fbinop2addr(instr="JAL(fmodf)") diff --git a/runtime/interpreter/mterp/mips/op_rem_int.S b/runtime/interpreter/mterp/mips/op_rem_int.S index c2a334a879..2f67adc1c7 100644 --- a/runtime/interpreter/mterp/mips/op_rem_int.S +++ b/runtime/interpreter/mterp/mips/op_rem_int.S @@ -1,5 +1,6 @@ +%def op_rem_int(): #ifdef MIPS32REVGE6 -%include "mips/binop.S" {"instr":"mod a0, a0, a1", "chkzero":"1"} +% binop(instr="mod a0, a0, a1", chkzero="1") #else -%include "mips/binop.S" {"preinstr":"div zero, a0, a1", "instr":"mfhi a0", "chkzero":"1"} +% binop(preinstr="div zero, a0, a1", instr="mfhi a0", chkzero="1") #endif diff --git a/runtime/interpreter/mterp/mips/op_rem_int_2addr.S b/runtime/interpreter/mterp/mips/op_rem_int_2addr.S index 46c353fa83..78766a7b55 100644 --- a/runtime/interpreter/mterp/mips/op_rem_int_2addr.S +++ b/runtime/interpreter/mterp/mips/op_rem_int_2addr.S @@ -1,5 +1,6 @@ +%def op_rem_int_2addr(): #ifdef MIPS32REVGE6 -%include "mips/binop2addr.S" {"instr":"mod a0, a0, a1", "chkzero":"1"} +% binop2addr(instr="mod a0, a0, a1", chkzero="1") #else -%include "mips/binop2addr.S" {"preinstr":"div zero, a0, a1", "instr":"mfhi a0", "chkzero":"1"} +% binop2addr(preinstr="div zero, a0, a1", instr="mfhi a0", chkzero="1") #endif diff --git a/runtime/interpreter/mterp/mips/op_rem_int_lit16.S b/runtime/interpreter/mterp/mips/op_rem_int_lit16.S index 2894ad37a2..ce136cbf37 100644 --- a/runtime/interpreter/mterp/mips/op_rem_int_lit16.S +++ b/runtime/interpreter/mterp/mips/op_rem_int_lit16.S @@ -1,5 +1,6 @@ +%def op_rem_int_lit16(): #ifdef MIPS32REVGE6 -%include "mips/binopLit16.S" {"instr":"mod a0, a0, a1", "chkzero":"1"} +% binopLit16(instr="mod a0, a0, a1", chkzero="1") #else -%include "mips/binopLit16.S" {"preinstr":"div zero, a0, a1", "instr":"mfhi a0", "chkzero":"1"} +% binopLit16(preinstr="div zero, a0, a1", instr="mfhi a0", chkzero="1") #endif diff --git a/runtime/interpreter/mterp/mips/op_rem_int_lit8.S b/runtime/interpreter/mterp/mips/op_rem_int_lit8.S index 582248ba8f..0a5084449d 100644 --- a/runtime/interpreter/mterp/mips/op_rem_int_lit8.S +++ b/runtime/interpreter/mterp/mips/op_rem_int_lit8.S @@ -1,5 +1,6 @@ +%def op_rem_int_lit8(): #ifdef MIPS32REVGE6 -%include "mips/binopLit8.S" {"instr":"mod a0, a0, a1", "chkzero":"1"} +% binopLit8(instr="mod a0, a0, a1", chkzero="1") #else -%include "mips/binopLit8.S" {"preinstr":"div zero, a0, a1", "instr":"mfhi a0", "chkzero":"1"} +% binopLit8(preinstr="div zero, a0, a1", instr="mfhi a0", chkzero="1") #endif diff --git a/runtime/interpreter/mterp/mips/op_rem_long.S b/runtime/interpreter/mterp/mips/op_rem_long.S index e3eb19bed4..2403deccc2 100644 --- a/runtime/interpreter/mterp/mips/op_rem_long.S +++ b/runtime/interpreter/mterp/mips/op_rem_long.S @@ -1 +1,2 @@ -%include "mips/binopWide.S" { "result0":"v0", "result1":"v1", "instr":"JAL(__moddi3)", "chkzero":"1"} +%def op_rem_long(): +% binopWide(result0="v0", result1="v1", instr="JAL(__moddi3)", chkzero="1") diff --git a/runtime/interpreter/mterp/mips/op_rem_long_2addr.S b/runtime/interpreter/mterp/mips/op_rem_long_2addr.S index 8fc9fdb15f..6cf3c09cea 100644 --- a/runtime/interpreter/mterp/mips/op_rem_long_2addr.S +++ b/runtime/interpreter/mterp/mips/op_rem_long_2addr.S @@ -1 +1,2 @@ -%include "mips/binopWide2addr.S" { "result0":"v0", "result1":"v1", "instr":"JAL(__moddi3)", "chkzero":"1"} +%def op_rem_long_2addr(): +% binopWide2addr(result0="v0", result1="v1", instr="JAL(__moddi3)", chkzero="1") diff --git a/runtime/interpreter/mterp/mips/op_return.S b/runtime/interpreter/mterp/mips/op_return.S index 44b93958d2..4e422d2999 100644 --- a/runtime/interpreter/mterp/mips/op_return.S +++ b/runtime/interpreter/mterp/mips/op_return.S @@ -1,3 +1,4 @@ +%def op_return(): /* * Return a 32-bit value. * diff --git a/runtime/interpreter/mterp/mips/op_return_object.S b/runtime/interpreter/mterp/mips/op_return_object.S index 7350e008c5..2eeec0b948 100644 --- a/runtime/interpreter/mterp/mips/op_return_object.S +++ b/runtime/interpreter/mterp/mips/op_return_object.S @@ -1 +1,2 @@ -%include "mips/op_return.S" +%def op_return_object(): +% op_return() diff --git a/runtime/interpreter/mterp/mips/op_return_void.S b/runtime/interpreter/mterp/mips/op_return_void.S index 1f616ea198..14e532b6f9 100644 --- a/runtime/interpreter/mterp/mips/op_return_void.S +++ b/runtime/interpreter/mterp/mips/op_return_void.S @@ -1,3 +1,4 @@ +%def op_return_void(): .extern MterpThreadFenceForConstructor JAL(MterpThreadFenceForConstructor) lw ra, THREAD_FLAGS_OFFSET(rSELF) diff --git a/runtime/interpreter/mterp/mips/op_return_void_no_barrier.S b/runtime/interpreter/mterp/mips/op_return_void_no_barrier.S index e670c2867f..a74f0855d1 100644 --- a/runtime/interpreter/mterp/mips/op_return_void_no_barrier.S +++ b/runtime/interpreter/mterp/mips/op_return_void_no_barrier.S @@ -1,3 +1,4 @@ +%def op_return_void_no_barrier(): lw ra, THREAD_FLAGS_OFFSET(rSELF) move a0, rSELF and ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST diff --git a/runtime/interpreter/mterp/mips/op_return_wide.S b/runtime/interpreter/mterp/mips/op_return_wide.S index f0f679dbde..fb065a56d6 100644 --- a/runtime/interpreter/mterp/mips/op_return_wide.S +++ b/runtime/interpreter/mterp/mips/op_return_wide.S @@ -1,3 +1,4 @@ +%def op_return_wide(): /* * Return a 64-bit value. */ diff --git a/runtime/interpreter/mterp/mips/op_rsub_int.S b/runtime/interpreter/mterp/mips/op_rsub_int.S index f7e61bb2e9..21ead06dbf 100644 --- a/runtime/interpreter/mterp/mips/op_rsub_int.S +++ b/runtime/interpreter/mterp/mips/op_rsub_int.S @@ -1,2 +1,3 @@ +%def op_rsub_int(): /* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ -%include "mips/binopLit16.S" {"instr":"subu a0, a1, a0"} +% binopLit16(instr="subu a0, a1, a0") diff --git a/runtime/interpreter/mterp/mips/op_rsub_int_lit8.S b/runtime/interpreter/mterp/mips/op_rsub_int_lit8.S index 3968a5ef8c..b9b214da94 100644 --- a/runtime/interpreter/mterp/mips/op_rsub_int_lit8.S +++ b/runtime/interpreter/mterp/mips/op_rsub_int_lit8.S @@ -1 +1,2 @@ -%include "mips/binopLit8.S" {"instr":"subu a0, a1, a0"} +%def op_rsub_int_lit8(): +% binopLit8(instr="subu a0, a1, a0") diff --git a/runtime/interpreter/mterp/mips/op_sget.S b/runtime/interpreter/mterp/mips/op_sget.S index 92d667335b..8a6a66ab60 100644 --- a/runtime/interpreter/mterp/mips/op_sget.S +++ b/runtime/interpreter/mterp/mips/op_sget.S @@ -1,2 +1,2 @@ -%default { "is_object":"0", "helper":"MterpSGetU32" } -%include "mips/field.S" { } +%def op_sget(is_object="0", helper="MterpSGetU32"): +% field(helper=helper) diff --git a/runtime/interpreter/mterp/mips/op_sget_boolean.S b/runtime/interpreter/mterp/mips/op_sget_boolean.S index 7a7012e81f..d9c12c9b28 100644 --- a/runtime/interpreter/mterp/mips/op_sget_boolean.S +++ b/runtime/interpreter/mterp/mips/op_sget_boolean.S @@ -1 +1,2 @@ -%include "mips/op_sget.S" {"helper":"MterpSGetU8"} +%def op_sget_boolean(): +% op_sget(helper="MterpSGetU8") diff --git a/runtime/interpreter/mterp/mips/op_sget_byte.S b/runtime/interpreter/mterp/mips/op_sget_byte.S index a2f1dbf606..37c6879cd4 100644 --- a/runtime/interpreter/mterp/mips/op_sget_byte.S +++ b/runtime/interpreter/mterp/mips/op_sget_byte.S @@ -1 +1,2 @@ -%include "mips/op_sget.S" {"helper":"MterpSGetI8"} +%def op_sget_byte(): +% op_sget(helper="MterpSGetI8") diff --git a/runtime/interpreter/mterp/mips/op_sget_char.S b/runtime/interpreter/mterp/mips/op_sget_char.S index 07d40416a3..003bcd1683 100644 --- a/runtime/interpreter/mterp/mips/op_sget_char.S +++ b/runtime/interpreter/mterp/mips/op_sget_char.S @@ -1 +1,2 @@ -%include "mips/op_sget.S" {"helper":"MterpSGetU16"} +%def op_sget_char(): +% op_sget(helper="MterpSGetU16") diff --git a/runtime/interpreter/mterp/mips/op_sget_object.S b/runtime/interpreter/mterp/mips/op_sget_object.S index 0a3c9eef88..7cf3597f44 100644 --- a/runtime/interpreter/mterp/mips/op_sget_object.S +++ b/runtime/interpreter/mterp/mips/op_sget_object.S @@ -1 +1,2 @@ -%include "mips/op_sget.S" {"is_object":"1", "helper":"MterpSGetObj"} +%def op_sget_object(): +% op_sget(is_object="1", helper="MterpSGetObj") diff --git a/runtime/interpreter/mterp/mips/op_sget_short.S b/runtime/interpreter/mterp/mips/op_sget_short.S index 29604430f2..afacb578d9 100644 --- a/runtime/interpreter/mterp/mips/op_sget_short.S +++ b/runtime/interpreter/mterp/mips/op_sget_short.S @@ -1 +1,2 @@ -%include "mips/op_sget.S" {"helper":"MterpSGetI16"} +%def op_sget_short(): +% op_sget(helper="MterpSGetI16") diff --git a/runtime/interpreter/mterp/mips/op_sget_wide.S b/runtime/interpreter/mterp/mips/op_sget_wide.S index be4ae027cb..fff2be6945 100644 --- a/runtime/interpreter/mterp/mips/op_sget_wide.S +++ b/runtime/interpreter/mterp/mips/op_sget_wide.S @@ -1 +1,2 @@ -%include "mips/op_sget.S" {"helper":"MterpSGetU64"} +%def op_sget_wide(): +% op_sget(helper="MterpSGetU64") diff --git a/runtime/interpreter/mterp/mips/op_shl_int.S b/runtime/interpreter/mterp/mips/op_shl_int.S index 15cbe94113..efd213c09a 100644 --- a/runtime/interpreter/mterp/mips/op_shl_int.S +++ b/runtime/interpreter/mterp/mips/op_shl_int.S @@ -1 +1,2 @@ -%include "mips/binop.S" {"instr":"sll a0, a0, a1"} +%def op_shl_int(): +% binop(instr="sll a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_shl_int_2addr.S b/runtime/interpreter/mterp/mips/op_shl_int_2addr.S index ef9bd655ab..0901e6b65a 100644 --- a/runtime/interpreter/mterp/mips/op_shl_int_2addr.S +++ b/runtime/interpreter/mterp/mips/op_shl_int_2addr.S @@ -1 +1,2 @@ -%include "mips/binop2addr.S" {"instr":"sll a0, a0, a1"} +%def op_shl_int_2addr(): +% binop2addr(instr="sll a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_shl_int_lit8.S b/runtime/interpreter/mterp/mips/op_shl_int_lit8.S index d2afb53e14..2263ec70c2 100644 --- a/runtime/interpreter/mterp/mips/op_shl_int_lit8.S +++ b/runtime/interpreter/mterp/mips/op_shl_int_lit8.S @@ -1 +1,2 @@ -%include "mips/binopLit8.S" {"instr":"sll a0, a0, a1"} +%def op_shl_int_lit8(): +% binopLit8(instr="sll a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_shl_long.S b/runtime/interpreter/mterp/mips/op_shl_long.S index cc0811295b..8bb4216425 100644 --- a/runtime/interpreter/mterp/mips/op_shl_long.S +++ b/runtime/interpreter/mterp/mips/op_shl_long.S @@ -1,3 +1,4 @@ +%def op_shl_long(): /* * Long integer shift. This is different from the generic 32/64-bit * binary operations because vAA/vBB are 64-bit but vCC (the shift @@ -25,7 +26,7 @@ sll v1, a1, a2 # rhi<- ahi << (shift&31) or v1, a0 # rhi<- rhi | alo SET_VREG64_GOTO(v0, v1, t2, t0) # vAA/vAA+1 <- v0/v1 -%break +%def op_shl_long_sister_code(): .L${opcode}_finish: SET_VREG64_GOTO(zero, v0, t2, t0) # vAA/vAA+1 <- rlo/rhi diff --git a/runtime/interpreter/mterp/mips/op_shl_long_2addr.S b/runtime/interpreter/mterp/mips/op_shl_long_2addr.S index 93c578353e..12015f5b15 100644 --- a/runtime/interpreter/mterp/mips/op_shl_long_2addr.S +++ b/runtime/interpreter/mterp/mips/op_shl_long_2addr.S @@ -1,3 +1,4 @@ +%def op_shl_long_2addr(): /* * Long integer shift, 2addr version. vA is 64-bit value/result, vB is * 32-bit shift distance. @@ -21,7 +22,7 @@ sll v1, a1, a2 # rhi<- ahi << (shift&31) or v1, a0 # rhi<- rhi | alo SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vA/vA+1 <- v0/v1 -%break +%def op_shl_long_2addr_sister_code(): .L${opcode}_finish: SET_VREG64_GOTO(zero, v0, rOBJ, t0) # vA/vA+1 <- rlo/rhi diff --git a/runtime/interpreter/mterp/mips/op_shr_int.S b/runtime/interpreter/mterp/mips/op_shr_int.S index 6110839999..8d55e7afa9 100644 --- a/runtime/interpreter/mterp/mips/op_shr_int.S +++ b/runtime/interpreter/mterp/mips/op_shr_int.S @@ -1 +1,2 @@ -%include "mips/binop.S" {"instr":"sra a0, a0, a1"} +%def op_shr_int(): +% binop(instr="sra a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_shr_int_2addr.S b/runtime/interpreter/mterp/mips/op_shr_int_2addr.S index e00ff5b2e6..e102baa99f 100644 --- a/runtime/interpreter/mterp/mips/op_shr_int_2addr.S +++ b/runtime/interpreter/mterp/mips/op_shr_int_2addr.S @@ -1 +1,2 @@ -%include "mips/binop2addr.S" {"instr":"sra a0, a0, a1"} +%def op_shr_int_2addr(): +% binop2addr(instr="sra a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_shr_int_lit8.S b/runtime/interpreter/mterp/mips/op_shr_int_lit8.S index d058f5862c..437c5c49a6 100644 --- a/runtime/interpreter/mterp/mips/op_shr_int_lit8.S +++ b/runtime/interpreter/mterp/mips/op_shr_int_lit8.S @@ -1 +1,2 @@ -%include "mips/binopLit8.S" {"instr":"sra a0, a0, a1"} +%def op_shr_int_lit8(): +% binopLit8(instr="sra a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_shr_long.S b/runtime/interpreter/mterp/mips/op_shr_long.S index ea032fe9a0..adffa615a1 100644 --- a/runtime/interpreter/mterp/mips/op_shr_long.S +++ b/runtime/interpreter/mterp/mips/op_shr_long.S @@ -1,3 +1,4 @@ +%def op_shr_long(): /* * Long integer shift. This is different from the generic 32/64-bit * binary operations because vAA/vBB are 64-bit but vCC (the shift @@ -24,7 +25,7 @@ sll a1, a0 # ahi<- ahi << (32-(shift&31)) or v0, a1 # rlo<- rlo | ahi SET_VREG64_GOTO(v0, v1, t3, t0) # vAA/VAA+1 <- v0/v1 -%break +%def op_shr_long_sister_code(): .L${opcode}_finish: sra a3, a1, 31 # a3<- sign(ah) diff --git a/runtime/interpreter/mterp/mips/op_shr_long_2addr.S b/runtime/interpreter/mterp/mips/op_shr_long_2addr.S index c805ea424f..d8acb790b6 100644 --- a/runtime/interpreter/mterp/mips/op_shr_long_2addr.S +++ b/runtime/interpreter/mterp/mips/op_shr_long_2addr.S @@ -1,3 +1,4 @@ +%def op_shr_long_2addr(): /* * Long integer shift, 2addr version. vA is 64-bit value/result, vB is * 32-bit shift distance. @@ -20,7 +21,7 @@ sll a1, a0 # ahi<- ahi << (32-(shift&31)) or v0, a1 # rlo<- rlo | ahi SET_VREG64_GOTO(v0, v1, t2, t0) # vA/vA+1 <- v0/v1 -%break +%def op_shr_long_2addr_sister_code(): .L${opcode}_finish: sra a3, a1, 31 # a3<- sign(ah) diff --git a/runtime/interpreter/mterp/mips/op_sparse_switch.S b/runtime/interpreter/mterp/mips/op_sparse_switch.S index 670f4648a8..b74d7da816 100644 --- a/runtime/interpreter/mterp/mips/op_sparse_switch.S +++ b/runtime/interpreter/mterp/mips/op_sparse_switch.S @@ -1 +1,2 @@ -%include "mips/op_packed_switch.S" { "func":"MterpDoSparseSwitch" } +%def op_sparse_switch(): +% op_packed_switch(func="MterpDoSparseSwitch") diff --git a/runtime/interpreter/mterp/mips/op_sput.S b/runtime/interpreter/mterp/mips/op_sput.S index c858679762..cbd6ee96d3 100644 --- a/runtime/interpreter/mterp/mips/op_sput.S +++ b/runtime/interpreter/mterp/mips/op_sput.S @@ -1,2 +1,2 @@ -%default { "is_object":"0", "helper":"MterpSPutU32"} -%include "mips/field.S" { } +%def op_sput(is_object="0", helper="MterpSPutU32"): +% field(helper=helper) diff --git a/runtime/interpreter/mterp/mips/op_sput_boolean.S b/runtime/interpreter/mterp/mips/op_sput_boolean.S index 0137430acc..36fba8448b 100644 --- a/runtime/interpreter/mterp/mips/op_sput_boolean.S +++ b/runtime/interpreter/mterp/mips/op_sput_boolean.S @@ -1 +1,2 @@ -%include "mips/op_sput.S" {"helper":"MterpSPutU8"} +%def op_sput_boolean(): +% op_sput(helper="MterpSPutU8") diff --git a/runtime/interpreter/mterp/mips/op_sput_byte.S b/runtime/interpreter/mterp/mips/op_sput_byte.S index 5ae4256a98..84ad4a0ff8 100644 --- a/runtime/interpreter/mterp/mips/op_sput_byte.S +++ b/runtime/interpreter/mterp/mips/op_sput_byte.S @@ -1 +1,2 @@ -%include "mips/op_sput.S" {"helper":"MterpSPutI8"} +%def op_sput_byte(): +% op_sput(helper="MterpSPutI8") diff --git a/runtime/interpreter/mterp/mips/op_sput_char.S b/runtime/interpreter/mterp/mips/op_sput_char.S index 83787a7753..9b8eeba578 100644 --- a/runtime/interpreter/mterp/mips/op_sput_char.S +++ b/runtime/interpreter/mterp/mips/op_sput_char.S @@ -1 +1,2 @@ -%include "mips/op_sput.S" {"helper":"MterpSPutU16"} +%def op_sput_char(): +% op_sput(helper="MterpSPutU16") diff --git a/runtime/interpreter/mterp/mips/op_sput_object.S b/runtime/interpreter/mterp/mips/op_sput_object.S index 683b76789d..081360c40f 100644 --- a/runtime/interpreter/mterp/mips/op_sput_object.S +++ b/runtime/interpreter/mterp/mips/op_sput_object.S @@ -1 +1,2 @@ -%include "mips/op_sput.S" {"is_object":"1", "helper":"MterpSPutObj"} +%def op_sput_object(): +% op_sput(is_object="1", helper="MterpSPutObj") diff --git a/runtime/interpreter/mterp/mips/op_sput_short.S b/runtime/interpreter/mterp/mips/op_sput_short.S index df99b4414d..ee16513486 100644 --- a/runtime/interpreter/mterp/mips/op_sput_short.S +++ b/runtime/interpreter/mterp/mips/op_sput_short.S @@ -1 +1,2 @@ -%include "mips/op_sput.S" {"helper":"MterpSPutI16"} +%def op_sput_short(): +% op_sput(helper="MterpSPutI16") diff --git a/runtime/interpreter/mterp/mips/op_sput_wide.S b/runtime/interpreter/mterp/mips/op_sput_wide.S index 1d2ed196f3..44c1a188ed 100644 --- a/runtime/interpreter/mterp/mips/op_sput_wide.S +++ b/runtime/interpreter/mterp/mips/op_sput_wide.S @@ -1 +1,2 @@ -%include "mips/op_sput.S" {"helper":"MterpSPutU64"} +%def op_sput_wide(): +% op_sput(helper="MterpSPutU64") diff --git a/runtime/interpreter/mterp/mips/op_sub_double.S b/runtime/interpreter/mterp/mips/op_sub_double.S index 9473218e89..ad8f12cfb3 100644 --- a/runtime/interpreter/mterp/mips/op_sub_double.S +++ b/runtime/interpreter/mterp/mips/op_sub_double.S @@ -1 +1,2 @@ -%include "mips/fbinopWide.S" {"instr":"sub.d fv0, fa0, fa1"} +%def op_sub_double(): +% fbinopWide(instr="sub.d fv0, fa0, fa1") diff --git a/runtime/interpreter/mterp/mips/op_sub_double_2addr.S b/runtime/interpreter/mterp/mips/op_sub_double_2addr.S index 7ce7c74330..ed5598d2a4 100644 --- a/runtime/interpreter/mterp/mips/op_sub_double_2addr.S +++ b/runtime/interpreter/mterp/mips/op_sub_double_2addr.S @@ -1 +1,2 @@ -%include "mips/fbinopWide2addr.S" {"instr":"sub.d fv0, fa0, fa1"} +%def op_sub_double_2addr(): +% fbinopWide2addr(instr="sub.d fv0, fa0, fa1") diff --git a/runtime/interpreter/mterp/mips/op_sub_float.S b/runtime/interpreter/mterp/mips/op_sub_float.S index 04650d9125..402fa2cfd7 100644 --- a/runtime/interpreter/mterp/mips/op_sub_float.S +++ b/runtime/interpreter/mterp/mips/op_sub_float.S @@ -1 +1,2 @@ -%include "mips/fbinop.S" {"instr":"sub.s fv0, fa0, fa1"} +%def op_sub_float(): +% fbinop(instr="sub.s fv0, fa0, fa1") diff --git a/runtime/interpreter/mterp/mips/op_sub_float_2addr.S b/runtime/interpreter/mterp/mips/op_sub_float_2addr.S index dfe935c8cf..1d38188048 100644 --- a/runtime/interpreter/mterp/mips/op_sub_float_2addr.S +++ b/runtime/interpreter/mterp/mips/op_sub_float_2addr.S @@ -1 +1,2 @@ -%include "mips/fbinop2addr.S" {"instr":"sub.s fv0, fa0, fa1"} +%def op_sub_float_2addr(): +% fbinop2addr(instr="sub.s fv0, fa0, fa1") diff --git a/runtime/interpreter/mterp/mips/op_sub_int.S b/runtime/interpreter/mterp/mips/op_sub_int.S index 43da1b617a..57f618d65a 100644 --- a/runtime/interpreter/mterp/mips/op_sub_int.S +++ b/runtime/interpreter/mterp/mips/op_sub_int.S @@ -1 +1,2 @@ -%include "mips/binop.S" {"instr":"subu a0, a0, a1"} +%def op_sub_int(): +% binop(instr="subu a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_sub_int_2addr.S b/runtime/interpreter/mterp/mips/op_sub_int_2addr.S index cf34aa69dc..445ffca50f 100644 --- a/runtime/interpreter/mterp/mips/op_sub_int_2addr.S +++ b/runtime/interpreter/mterp/mips/op_sub_int_2addr.S @@ -1 +1,2 @@ -%include "mips/binop2addr.S" {"instr":"subu a0, a0, a1"} +%def op_sub_int_2addr(): +% binop2addr(instr="subu a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_sub_long.S b/runtime/interpreter/mterp/mips/op_sub_long.S index 0f58e8e891..a54460b3b2 100644 --- a/runtime/interpreter/mterp/mips/op_sub_long.S +++ b/runtime/interpreter/mterp/mips/op_sub_long.S @@ -1,3 +1,4 @@ +%def op_sub_long(): /* * For little endian the code sequence looks as follows: * subu v0,a0,a2 @@ -5,4 +6,4 @@ * sltu a0,a0,v0 * subu v1,v1,a0 */ -%include "mips/binopWide.S" { "result0":"v0", "result1":"v1", "preinstr":"subu v0, a0, a2", "instr":"subu v1, a1, a3; sltu a0, a0, v0; subu v1, v1, a0" } +% binopWide(result0="v0", result1="v1", preinstr="subu v0, a0, a2", instr="subu v1, a1, a3; sltu a0, a0, v0; subu v1, v1, a0") diff --git a/runtime/interpreter/mterp/mips/op_sub_long_2addr.S b/runtime/interpreter/mterp/mips/op_sub_long_2addr.S index aa256c20f8..b3dd6b2cd2 100644 --- a/runtime/interpreter/mterp/mips/op_sub_long_2addr.S +++ b/runtime/interpreter/mterp/mips/op_sub_long_2addr.S @@ -1,4 +1,5 @@ +%def op_sub_long_2addr(): /* * See op_sub_long.S for more details */ -%include "mips/binopWide2addr.S" { "result0":"v0", "result1":"v1", "preinstr":"subu v0, a0, a2", "instr":"subu v1, a1, a3; sltu a0, a0, v0; subu v1, v1, a0" } +% binopWide2addr(result0="v0", result1="v1", preinstr="subu v0, a0, a2", instr="subu v1, a1, a3; sltu a0, a0, v0; subu v1, v1, a0") diff --git a/runtime/interpreter/mterp/mips/op_throw.S b/runtime/interpreter/mterp/mips/op_throw.S index adc8b047ca..84b9e5ecfc 100644 --- a/runtime/interpreter/mterp/mips/op_throw.S +++ b/runtime/interpreter/mterp/mips/op_throw.S @@ -1,3 +1,4 @@ +%def op_throw(): /* * Throw an exception object in the current thread. */ diff --git a/runtime/interpreter/mterp/mips/op_unused_3e.S b/runtime/interpreter/mterp/mips/op_unused_3e.S index 99ef3cf308..d889f1a5fb 100644 --- a/runtime/interpreter/mterp/mips/op_unused_3e.S +++ b/runtime/interpreter/mterp/mips/op_unused_3e.S @@ -1 +1,2 @@ -%include "mips/unused.S" +%def op_unused_3e(): +% unused() diff --git a/runtime/interpreter/mterp/mips/op_unused_3f.S b/runtime/interpreter/mterp/mips/op_unused_3f.S index 99ef3cf308..b3ebcfaeaa 100644 --- a/runtime/interpreter/mterp/mips/op_unused_3f.S +++ b/runtime/interpreter/mterp/mips/op_unused_3f.S @@ -1 +1,2 @@ -%include "mips/unused.S" +%def op_unused_3f(): +% unused() diff --git a/runtime/interpreter/mterp/mips/op_unused_40.S b/runtime/interpreter/mterp/mips/op_unused_40.S index 99ef3cf308..7920fb350f 100644 --- a/runtime/interpreter/mterp/mips/op_unused_40.S +++ b/runtime/interpreter/mterp/mips/op_unused_40.S @@ -1 +1,2 @@ -%include "mips/unused.S" +%def op_unused_40(): +% unused() diff --git a/runtime/interpreter/mterp/mips/op_unused_41.S b/runtime/interpreter/mterp/mips/op_unused_41.S index 99ef3cf308..5ed03b8506 100644 --- a/runtime/interpreter/mterp/mips/op_unused_41.S +++ b/runtime/interpreter/mterp/mips/op_unused_41.S @@ -1 +1,2 @@ -%include "mips/unused.S" +%def op_unused_41(): +% unused() diff --git a/runtime/interpreter/mterp/mips/op_unused_42.S b/runtime/interpreter/mterp/mips/op_unused_42.S index 99ef3cf308..ac32521add 100644 --- a/runtime/interpreter/mterp/mips/op_unused_42.S +++ b/runtime/interpreter/mterp/mips/op_unused_42.S @@ -1 +1,2 @@ -%include "mips/unused.S" +%def op_unused_42(): +% unused() diff --git a/runtime/interpreter/mterp/mips/op_unused_43.S b/runtime/interpreter/mterp/mips/op_unused_43.S index 99ef3cf308..33e2aa10f8 100644 --- a/runtime/interpreter/mterp/mips/op_unused_43.S +++ b/runtime/interpreter/mterp/mips/op_unused_43.S @@ -1 +1,2 @@ -%include "mips/unused.S" +%def op_unused_43(): +% unused() diff --git a/runtime/interpreter/mterp/mips/op_unused_73.S b/runtime/interpreter/mterp/mips/op_unused_73.S index 99ef3cf308..e3267a30a1 100644 --- a/runtime/interpreter/mterp/mips/op_unused_73.S +++ b/runtime/interpreter/mterp/mips/op_unused_73.S @@ -1 +1,2 @@ -%include "mips/unused.S" +%def op_unused_73(): +% unused() diff --git a/runtime/interpreter/mterp/mips/op_unused_79.S b/runtime/interpreter/mterp/mips/op_unused_79.S index 99ef3cf308..3c6dafc789 100644 --- a/runtime/interpreter/mterp/mips/op_unused_79.S +++ b/runtime/interpreter/mterp/mips/op_unused_79.S @@ -1 +1,2 @@ -%include "mips/unused.S" +%def op_unused_79(): +% unused() diff --git a/runtime/interpreter/mterp/mips/op_unused_7a.S b/runtime/interpreter/mterp/mips/op_unused_7a.S index 99ef3cf308..9c03cd5535 100644 --- a/runtime/interpreter/mterp/mips/op_unused_7a.S +++ b/runtime/interpreter/mterp/mips/op_unused_7a.S @@ -1 +1,2 @@ -%include "mips/unused.S" +%def op_unused_7a(): +% unused() diff --git a/runtime/interpreter/mterp/mips/op_unused_f3.S b/runtime/interpreter/mterp/mips/op_unused_f3.S index 99ef3cf308..ab10b78be2 100644 --- a/runtime/interpreter/mterp/mips/op_unused_f3.S +++ b/runtime/interpreter/mterp/mips/op_unused_f3.S @@ -1 +1,2 @@ -%include "mips/unused.S" +%def op_unused_f3(): +% unused() diff --git a/runtime/interpreter/mterp/mips/op_unused_f4.S b/runtime/interpreter/mterp/mips/op_unused_f4.S index 99ef3cf308..09229d6d99 100644 --- a/runtime/interpreter/mterp/mips/op_unused_f4.S +++ b/runtime/interpreter/mterp/mips/op_unused_f4.S @@ -1 +1,2 @@ -%include "mips/unused.S" +%def op_unused_f4(): +% unused() diff --git a/runtime/interpreter/mterp/mips/op_unused_f5.S b/runtime/interpreter/mterp/mips/op_unused_f5.S index 99ef3cf308..0d6149b5fd 100644 --- a/runtime/interpreter/mterp/mips/op_unused_f5.S +++ b/runtime/interpreter/mterp/mips/op_unused_f5.S @@ -1 +1,2 @@ -%include "mips/unused.S" +%def op_unused_f5(): +% unused() diff --git a/runtime/interpreter/mterp/mips/op_unused_f6.S b/runtime/interpreter/mterp/mips/op_unused_f6.S index 99ef3cf308..117b03de6d 100644 --- a/runtime/interpreter/mterp/mips/op_unused_f6.S +++ b/runtime/interpreter/mterp/mips/op_unused_f6.S @@ -1 +1,2 @@ -%include "mips/unused.S" +%def op_unused_f6(): +% unused() diff --git a/runtime/interpreter/mterp/mips/op_unused_f7.S b/runtime/interpreter/mterp/mips/op_unused_f7.S index 99ef3cf308..4e3a0f3c9a 100644 --- a/runtime/interpreter/mterp/mips/op_unused_f7.S +++ b/runtime/interpreter/mterp/mips/op_unused_f7.S @@ -1 +1,2 @@ -%include "mips/unused.S" +%def op_unused_f7(): +% unused() diff --git a/runtime/interpreter/mterp/mips/op_unused_f8.S b/runtime/interpreter/mterp/mips/op_unused_f8.S index 99ef3cf308..d1220752d7 100644 --- a/runtime/interpreter/mterp/mips/op_unused_f8.S +++ b/runtime/interpreter/mterp/mips/op_unused_f8.S @@ -1 +1,2 @@ -%include "mips/unused.S" +%def op_unused_f8(): +% unused() diff --git a/runtime/interpreter/mterp/mips/op_unused_f9.S b/runtime/interpreter/mterp/mips/op_unused_f9.S index 99ef3cf308..7d09a0ebcf 100644 --- a/runtime/interpreter/mterp/mips/op_unused_f9.S +++ b/runtime/interpreter/mterp/mips/op_unused_f9.S @@ -1 +1,2 @@ -%include "mips/unused.S" +%def op_unused_f9(): +% unused() diff --git a/runtime/interpreter/mterp/mips/op_unused_fc.S b/runtime/interpreter/mterp/mips/op_unused_fc.S index 99ef3cf308..06978191eb 100644 --- a/runtime/interpreter/mterp/mips/op_unused_fc.S +++ b/runtime/interpreter/mterp/mips/op_unused_fc.S @@ -1 +1,2 @@ -%include "mips/unused.S" +%def op_unused_fc(): +% unused() diff --git a/runtime/interpreter/mterp/mips/op_unused_fd.S b/runtime/interpreter/mterp/mips/op_unused_fd.S index 99ef3cf308..4bc2b4bdb6 100644 --- a/runtime/interpreter/mterp/mips/op_unused_fd.S +++ b/runtime/interpreter/mterp/mips/op_unused_fd.S @@ -1 +1,2 @@ -%include "mips/unused.S" +%def op_unused_fd(): +% unused() diff --git a/runtime/interpreter/mterp/mips/op_ushr_int.S b/runtime/interpreter/mterp/mips/op_ushr_int.S index b95472b30e..98d2dfbc9c 100644 --- a/runtime/interpreter/mterp/mips/op_ushr_int.S +++ b/runtime/interpreter/mterp/mips/op_ushr_int.S @@ -1 +1,2 @@ -%include "mips/binop.S" {"instr":"srl a0, a0, a1"} +%def op_ushr_int(): +% binop(instr="srl a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_ushr_int_2addr.S b/runtime/interpreter/mterp/mips/op_ushr_int_2addr.S index fc17778100..4b09cacabc 100644 --- a/runtime/interpreter/mterp/mips/op_ushr_int_2addr.S +++ b/runtime/interpreter/mterp/mips/op_ushr_int_2addr.S @@ -1 +1,2 @@ -%include "mips/binop2addr.S" {"instr":"srl a0, a0, a1 "} +%def op_ushr_int_2addr(): +% binop2addr(instr="srl a0, a0, a1 ") diff --git a/runtime/interpreter/mterp/mips/op_ushr_int_lit8.S b/runtime/interpreter/mterp/mips/op_ushr_int_lit8.S index c82cfba15c..531c30a000 100644 --- a/runtime/interpreter/mterp/mips/op_ushr_int_lit8.S +++ b/runtime/interpreter/mterp/mips/op_ushr_int_lit8.S @@ -1 +1,2 @@ -%include "mips/binopLit8.S" {"instr":"srl a0, a0, a1"} +%def op_ushr_int_lit8(): +% binopLit8(instr="srl a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_ushr_long.S b/runtime/interpreter/mterp/mips/op_ushr_long.S index 2e227a94af..b09e7b3c6a 100644 --- a/runtime/interpreter/mterp/mips/op_ushr_long.S +++ b/runtime/interpreter/mterp/mips/op_ushr_long.S @@ -1,3 +1,4 @@ +%def op_ushr_long(): /* * Long integer shift. This is different from the generic 32/64-bit * binary operations because vAA/vBB are 64-bit but vCC (the shift @@ -25,7 +26,7 @@ sll a1, a0 # ahi<- ahi << (32-(shift&31)) or v0, a1 # rlo<- rlo | ahi SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vAA/vAA+1 <- v0/v1 -%break +%def op_ushr_long_sister_code(): .L${opcode}_finish: SET_VREG64_GOTO(v1, zero, rOBJ, t0) # vAA/vAA+1 <- rlo/rhi diff --git a/runtime/interpreter/mterp/mips/op_ushr_long_2addr.S b/runtime/interpreter/mterp/mips/op_ushr_long_2addr.S index 9e93f34cdb..0da2011e6a 100644 --- a/runtime/interpreter/mterp/mips/op_ushr_long_2addr.S +++ b/runtime/interpreter/mterp/mips/op_ushr_long_2addr.S @@ -1,3 +1,4 @@ +%def op_ushr_long_2addr(): /* * Long integer shift, 2addr version. vA is 64-bit value/result, vB is * 32-bit shift distance. @@ -21,7 +22,7 @@ sll a1, a0 # ahi<- ahi << (32-(shift&31)) or v0, a1 # rlo<- rlo | ahi SET_VREG64_GOTO(v0, v1, t3, t0) # vA/vA+1 <- v0/v1 -%break +%def op_ushr_long_2addr_sister_code(): .L${opcode}_finish: SET_VREG64_GOTO(v1, zero, t3, t0) # vA/vA+1 <- rlo/rhi diff --git a/runtime/interpreter/mterp/mips/op_xor_int.S b/runtime/interpreter/mterp/mips/op_xor_int.S index 6c23f1f378..1379a344e0 100644 --- a/runtime/interpreter/mterp/mips/op_xor_int.S +++ b/runtime/interpreter/mterp/mips/op_xor_int.S @@ -1 +1,2 @@ -%include "mips/binop.S" {"instr":"xor a0, a0, a1"} +%def op_xor_int(): +% binop(instr="xor a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_xor_int_2addr.S b/runtime/interpreter/mterp/mips/op_xor_int_2addr.S index 5ee1667f8d..6dbe11c3a8 100644 --- a/runtime/interpreter/mterp/mips/op_xor_int_2addr.S +++ b/runtime/interpreter/mterp/mips/op_xor_int_2addr.S @@ -1 +1,2 @@ -%include "mips/binop2addr.S" {"instr":"xor a0, a0, a1"} +%def op_xor_int_2addr(): +% binop2addr(instr="xor a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_xor_int_lit16.S b/runtime/interpreter/mterp/mips/op_xor_int_lit16.S index 2af37a6116..f8cbce04f4 100644 --- a/runtime/interpreter/mterp/mips/op_xor_int_lit16.S +++ b/runtime/interpreter/mterp/mips/op_xor_int_lit16.S @@ -1 +1,2 @@ -%include "mips/binopLit16.S" {"instr":"xor a0, a0, a1"} +%def op_xor_int_lit16(): +% binopLit16(instr="xor a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_xor_int_lit8.S b/runtime/interpreter/mterp/mips/op_xor_int_lit8.S index 944ed69231..268a43aac8 100644 --- a/runtime/interpreter/mterp/mips/op_xor_int_lit8.S +++ b/runtime/interpreter/mterp/mips/op_xor_int_lit8.S @@ -1 +1,2 @@ -%include "mips/binopLit8.S" {"instr":"xor a0, a0, a1"} +%def op_xor_int_lit8(): +% binopLit8(instr="xor a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_xor_long.S b/runtime/interpreter/mterp/mips/op_xor_long.S index 93f8f70a21..5c0c641243 100644 --- a/runtime/interpreter/mterp/mips/op_xor_long.S +++ b/runtime/interpreter/mterp/mips/op_xor_long.S @@ -1 +1,2 @@ -%include "mips/binopWide.S" {"preinstr":"xor a0, a0, a2", "instr":"xor a1, a1, a3"} +%def op_xor_long(): +% binopWide(preinstr="xor a0, a0, a2", instr="xor a1, a1, a3") diff --git a/runtime/interpreter/mterp/mips/op_xor_long_2addr.S b/runtime/interpreter/mterp/mips/op_xor_long_2addr.S index 49f3fa42f4..a84e9f05e0 100644 --- a/runtime/interpreter/mterp/mips/op_xor_long_2addr.S +++ b/runtime/interpreter/mterp/mips/op_xor_long_2addr.S @@ -1 +1,2 @@ -%include "mips/binopWide2addr.S" {"preinstr":"xor a0, a0, a2", "instr":"xor a1, a1, a3"} +%def op_xor_long_2addr(): +% binopWide2addr(preinstr="xor a0, a0, a2", instr="xor a1, a1, a3") diff --git a/runtime/interpreter/mterp/mips/unop.S b/runtime/interpreter/mterp/mips/unop.S index bc99263adb..34eb118946 100644 --- a/runtime/interpreter/mterp/mips/unop.S +++ b/runtime/interpreter/mterp/mips/unop.S @@ -1,4 +1,4 @@ -%default {"preinstr":"", "result0":"a0"} +%def unop(preinstr="", result0="a0", instr=""): /* * Generic 32-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result0 = op a0". diff --git a/runtime/interpreter/mterp/mips/unopNarrower.S b/runtime/interpreter/mterp/mips/unopNarrower.S index 0196e27e36..4f0bb1dc1b 100644 --- a/runtime/interpreter/mterp/mips/unopNarrower.S +++ b/runtime/interpreter/mterp/mips/unopNarrower.S @@ -1,4 +1,4 @@ -%default {"load":"LOAD64_F(fa0, fa0f, a3)"} +%def unopNarrower(load="LOAD64_F(fa0, fa0f, a3)", instr=""): /* * Generic 64bit-to-32bit floating-point unary operation. Provide an "instr" * line that specifies an instruction that performs "fv0 = op fa0". diff --git a/runtime/interpreter/mterp/mips/unopWide.S b/runtime/interpreter/mterp/mips/unopWide.S index 135d9facdf..269a29651f 100644 --- a/runtime/interpreter/mterp/mips/unopWide.S +++ b/runtime/interpreter/mterp/mips/unopWide.S @@ -1,4 +1,4 @@ -%default {"preinstr":"", "result0":"a0", "result1":"a1"} +%def unopWide(preinstr="", result0="a0", result1="a1", instr=""): /* * Generic 64-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result0/result1 = op a0/a1". diff --git a/runtime/interpreter/mterp/mips/unopWider.S b/runtime/interpreter/mterp/mips/unopWider.S index ca888ad3fb..7767d6ee50 100644 --- a/runtime/interpreter/mterp/mips/unopWider.S +++ b/runtime/interpreter/mterp/mips/unopWider.S @@ -1,4 +1,4 @@ -%default {"preinstr":"", "result0":"a0", "result1":"a1"} +%def unopWider(preinstr="", result0="a0", result1="a1", instr=""): /* * Generic 32bit-to-64bit unary operation. Provide an "instr" line * that specifies an instruction that performs "result0/result1 = op a0". diff --git a/runtime/interpreter/mterp/mips/unused.S b/runtime/interpreter/mterp/mips/unused.S index ffa00becfd..3f37e74bb4 100644 --- a/runtime/interpreter/mterp/mips/unused.S +++ b/runtime/interpreter/mterp/mips/unused.S @@ -1,3 +1,4 @@ +%def unused(): /* * Bail to reference interpreter to throw. */ diff --git a/runtime/interpreter/mterp/mips/zcmp.S b/runtime/interpreter/mterp/mips/zcmp.S index 8d3a198891..eb23eea744 100644 --- a/runtime/interpreter/mterp/mips/zcmp.S +++ b/runtime/interpreter/mterp/mips/zcmp.S @@ -1,3 +1,4 @@ +%def zcmp(condition=""): /* * Generic one-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform. diff --git a/runtime/interpreter/mterp/mips64/alt_stub.S b/runtime/interpreter/mterp/mips64/alt_stub.S index 12fa84d7d2..17558bb4c2 100644 --- a/runtime/interpreter/mterp/mips64/alt_stub.S +++ b/runtime/interpreter/mterp/mips64/alt_stub.S @@ -1,3 +1,4 @@ +%def alt_stub(): /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction diff --git a/runtime/interpreter/mterp/mips64/bincmp.S b/runtime/interpreter/mterp/mips64/bincmp.S index c2bca91ebf..bdf01dc5e3 100644 --- a/runtime/interpreter/mterp/mips64/bincmp.S +++ b/runtime/interpreter/mterp/mips64/bincmp.S @@ -1,3 +1,4 @@ +%def bincmp(condition=""): /* * Generic two-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform, e.g. for diff --git a/runtime/interpreter/mterp/mips64/binop.S b/runtime/interpreter/mterp/mips64/binop.S index fab48b73b3..9332fadd5f 100644 --- a/runtime/interpreter/mterp/mips64/binop.S +++ b/runtime/interpreter/mterp/mips64/binop.S @@ -1,4 +1,4 @@ -%default {"preinstr":"", "result":"a0", "chkzero":"0"} +%def binop(preinstr="", result="a0", chkzero="0", instr=""): /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0 op a1". diff --git a/runtime/interpreter/mterp/mips64/binop2addr.S b/runtime/interpreter/mterp/mips64/binop2addr.S index 1ae73f51d4..19f18151eb 100644 --- a/runtime/interpreter/mterp/mips64/binop2addr.S +++ b/runtime/interpreter/mterp/mips64/binop2addr.S @@ -1,4 +1,4 @@ -%default {"preinstr":"", "result":"a0", "chkzero":"0"} +%def binop2addr(preinstr="", result="a0", chkzero="0", instr=""): /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". diff --git a/runtime/interpreter/mterp/mips64/binopLit16.S b/runtime/interpreter/mterp/mips64/binopLit16.S index 925775824c..7cb2b97605 100644 --- a/runtime/interpreter/mterp/mips64/binopLit16.S +++ b/runtime/interpreter/mterp/mips64/binopLit16.S @@ -1,4 +1,4 @@ -%default {"preinstr":"", "result":"a0", "chkzero":"0"} +%def binopLit16(preinstr="", result="a0", chkzero="0", instr=""): /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". diff --git a/runtime/interpreter/mterp/mips64/binopLit8.S b/runtime/interpreter/mterp/mips64/binopLit8.S index f4a0bba9b9..3c0449f179 100644 --- a/runtime/interpreter/mterp/mips64/binopLit8.S +++ b/runtime/interpreter/mterp/mips64/binopLit8.S @@ -1,4 +1,4 @@ -%default {"preinstr":"", "result":"a0", "chkzero":"0"} +%def binopLit8(preinstr="", result="a0", chkzero="0", instr=""): /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". diff --git a/runtime/interpreter/mterp/mips64/binopWide.S b/runtime/interpreter/mterp/mips64/binopWide.S index 732f0d60f9..2206b31630 100644 --- a/runtime/interpreter/mterp/mips64/binopWide.S +++ b/runtime/interpreter/mterp/mips64/binopWide.S @@ -1,4 +1,4 @@ -%default {"preinstr":"", "result":"a0", "chkzero":"0"} +%def binopWide(preinstr="", result="a0", chkzero="0", instr=""): /* * Generic 64-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0 op a1". diff --git a/runtime/interpreter/mterp/mips64/binopWide2addr.S b/runtime/interpreter/mterp/mips64/binopWide2addr.S index 45d8d82960..8758a806db 100644 --- a/runtime/interpreter/mterp/mips64/binopWide2addr.S +++ b/runtime/interpreter/mterp/mips64/binopWide2addr.S @@ -1,4 +1,4 @@ -%default {"preinstr":"", "result":"a0", "chkzero":"0"} +%def binopWide2addr(preinstr="", result="a0", chkzero="0", instr=""): /* * Generic 64-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". diff --git a/runtime/interpreter/mterp/mips64/const.S b/runtime/interpreter/mterp/mips64/const.S index 2ec1173a7c..5de2404fc7 100644 --- a/runtime/interpreter/mterp/mips64/const.S +++ b/runtime/interpreter/mterp/mips64/const.S @@ -1,4 +1,4 @@ -%default { "helper":"UndefinedConstHandler" } +%def const(helper="UndefinedConstHandler"): /* const/class vAA, type@BBBB */ /* const/method-handle vAA, method_handle@BBBB */ /* const/method-type vAA, proto@BBBB */ diff --git a/runtime/interpreter/mterp/mips64/entry.S b/runtime/interpreter/mterp/mips64/entry.S index ed965aa201..0c64137fa8 100644 --- a/runtime/interpreter/mterp/mips64/entry.S +++ b/runtime/interpreter/mterp/mips64/entry.S @@ -1,3 +1,4 @@ +%def entry(): /* * Copyright (C) 2016 The Android Open Source Project * diff --git a/runtime/interpreter/mterp/mips64/fallback.S b/runtime/interpreter/mterp/mips64/fallback.S index 560b994b08..71abfeb23d 100644 --- a/runtime/interpreter/mterp/mips64/fallback.S +++ b/runtime/interpreter/mterp/mips64/fallback.S @@ -1,2 +1,3 @@ +%def fallback(): /* Transfer stub to alternate interpreter */ b MterpFallback diff --git a/runtime/interpreter/mterp/mips64/fbinop.S b/runtime/interpreter/mterp/mips64/fbinop.S index f19dd1c3d9..5090528201 100644 --- a/runtime/interpreter/mterp/mips64/fbinop.S +++ b/runtime/interpreter/mterp/mips64/fbinop.S @@ -1,4 +1,4 @@ -%default {} +%def fbinop(instr=""): /*: * Generic 32-bit floating-point operation. * diff --git a/runtime/interpreter/mterp/mips64/fbinop2addr.S b/runtime/interpreter/mterp/mips64/fbinop2addr.S index 2e2cd7e8e9..fe5ad2bec4 100644 --- a/runtime/interpreter/mterp/mips64/fbinop2addr.S +++ b/runtime/interpreter/mterp/mips64/fbinop2addr.S @@ -1,4 +1,4 @@ -%default {} +%def fbinop2addr(instr=""): /*: * Generic 32-bit "/2addr" floating-point operation. * diff --git a/runtime/interpreter/mterp/mips64/fbinopWide.S b/runtime/interpreter/mterp/mips64/fbinopWide.S index 8915c9447c..ca7765bb82 100644 --- a/runtime/interpreter/mterp/mips64/fbinopWide.S +++ b/runtime/interpreter/mterp/mips64/fbinopWide.S @@ -1,4 +1,4 @@ -%default {} +%def fbinopWide(instr=""): /*: * Generic 64-bit floating-point operation. * diff --git a/runtime/interpreter/mterp/mips64/fbinopWide2addr.S b/runtime/interpreter/mterp/mips64/fbinopWide2addr.S index a3f4eaa8cc..a4dfd4c793 100644 --- a/runtime/interpreter/mterp/mips64/fbinopWide2addr.S +++ b/runtime/interpreter/mterp/mips64/fbinopWide2addr.S @@ -1,4 +1,4 @@ -%default {} +%def fbinopWide2addr(instr=""): /*: * Generic 64-bit "/2addr" floating-point operation. * diff --git a/runtime/interpreter/mterp/mips64/fcmp.S b/runtime/interpreter/mterp/mips64/fcmp.S index 2e1a3e4c3d..bc40f9627e 100644 --- a/runtime/interpreter/mterp/mips64/fcmp.S +++ b/runtime/interpreter/mterp/mips64/fcmp.S @@ -1,4 +1,4 @@ -%default {} +%def fcmp(gt_bias=""): /* * Compare two floating-point values. Puts 0, 1, or -1 into the * destination register based on the results of the comparison. diff --git a/runtime/interpreter/mterp/mips64/fcmpWide.S b/runtime/interpreter/mterp/mips64/fcmpWide.S index 2a3a341a3d..05f33e6afa 100644 --- a/runtime/interpreter/mterp/mips64/fcmpWide.S +++ b/runtime/interpreter/mterp/mips64/fcmpWide.S @@ -1,4 +1,4 @@ -%default {} +%def fcmpWide(gt_bias=""): /* * Compare two floating-point values. Puts 0, 1, or -1 into the * destination register based on the results of the comparison. diff --git a/runtime/interpreter/mterp/mips64/fcvtFooter.S b/runtime/interpreter/mterp/mips64/fcvtFooter.S index 06e9507817..711f3f3e25 100644 --- a/runtime/interpreter/mterp/mips64/fcvtFooter.S +++ b/runtime/interpreter/mterp/mips64/fcvtFooter.S @@ -1,3 +1,4 @@ +%def fcvtFooter(suffix="", valreg=""): /* * Stores a specified register containing the result of conversion * from or to a floating-point type and jumps to the next instruction. diff --git a/runtime/interpreter/mterp/mips64/fcvtHeader.S b/runtime/interpreter/mterp/mips64/fcvtHeader.S index 8742e42c39..688b6be0f7 100644 --- a/runtime/interpreter/mterp/mips64/fcvtHeader.S +++ b/runtime/interpreter/mterp/mips64/fcvtHeader.S @@ -1,3 +1,4 @@ +%def fcvtHeader(suffix="", valreg=""): /* * Loads a specified register from vB. Used primarily for conversions * from or to a floating-point type. diff --git a/runtime/interpreter/mterp/mips64/field.S b/runtime/interpreter/mterp/mips64/field.S index 1333ed77b7..d61b06afd4 100644 --- a/runtime/interpreter/mterp/mips64/field.S +++ b/runtime/interpreter/mterp/mips64/field.S @@ -1 +1,2 @@ +%def field(helper=""): TODO diff --git a/runtime/interpreter/mterp/mips64/footer.S b/runtime/interpreter/mterp/mips64/footer.S index 779b1fb88f..5673151f1c 100644 --- a/runtime/interpreter/mterp/mips64/footer.S +++ b/runtime/interpreter/mterp/mips64/footer.S @@ -1,3 +1,4 @@ +%def footer(): /* * We've detected a condition that will result in an exception, but the exception * has not yet been thrown. Just bail out to the reference interpreter to deal with it. diff --git a/runtime/interpreter/mterp/mips64/header.S b/runtime/interpreter/mterp/mips64/header.S index 7e1446c0c6..42c712654d 100644 --- a/runtime/interpreter/mterp/mips64/header.S +++ b/runtime/interpreter/mterp/mips64/header.S @@ -1,3 +1,4 @@ +%def header(): /* * Copyright (C) 2016 The Android Open Source Project * diff --git a/runtime/interpreter/mterp/mips64/instruction_end.S b/runtime/interpreter/mterp/mips64/instruction_end.S index 32c725c7d9..3d4429365a 100644 --- a/runtime/interpreter/mterp/mips64/instruction_end.S +++ b/runtime/interpreter/mterp/mips64/instruction_end.S @@ -1,3 +1,4 @@ +%def instruction_end(): .global artMterpAsmInstructionEnd artMterpAsmInstructionEnd: diff --git a/runtime/interpreter/mterp/mips64/instruction_end_alt.S b/runtime/interpreter/mterp/mips64/instruction_end_alt.S index f90916fc02..86a1068f10 100644 --- a/runtime/interpreter/mterp/mips64/instruction_end_alt.S +++ b/runtime/interpreter/mterp/mips64/instruction_end_alt.S @@ -1,3 +1,4 @@ +%def instruction_end_alt(): .global artMterpAsmAltInstructionEnd artMterpAsmAltInstructionEnd: diff --git a/runtime/interpreter/mterp/mips64/instruction_end_sister.S b/runtime/interpreter/mterp/mips64/instruction_end_sister.S index c5f4886697..8cc4513025 100644 --- a/runtime/interpreter/mterp/mips64/instruction_end_sister.S +++ b/runtime/interpreter/mterp/mips64/instruction_end_sister.S @@ -1,3 +1,4 @@ +%def instruction_end_sister(): .global artMterpAsmSisterEnd artMterpAsmSisterEnd: diff --git a/runtime/interpreter/mterp/mips64/instruction_start.S b/runtime/interpreter/mterp/mips64/instruction_start.S index 8874c20540..4b777f2fd5 100644 --- a/runtime/interpreter/mterp/mips64/instruction_start.S +++ b/runtime/interpreter/mterp/mips64/instruction_start.S @@ -1,3 +1,4 @@ +%def instruction_start(): .global artMterpAsmInstructionStart artMterpAsmInstructionStart = .L_op_nop diff --git a/runtime/interpreter/mterp/mips64/instruction_start_alt.S b/runtime/interpreter/mterp/mips64/instruction_start_alt.S index 0c9ffdb7d6..e7731b7505 100644 --- a/runtime/interpreter/mterp/mips64/instruction_start_alt.S +++ b/runtime/interpreter/mterp/mips64/instruction_start_alt.S @@ -1,3 +1,4 @@ +%def instruction_start_alt(): .global artMterpAsmAltInstructionStart artMterpAsmAltInstructionStart = .L_ALT_op_nop diff --git a/runtime/interpreter/mterp/mips64/instruction_start_sister.S b/runtime/interpreter/mterp/mips64/instruction_start_sister.S index 2ec51f7261..e09ea90b8e 100644 --- a/runtime/interpreter/mterp/mips64/instruction_start_sister.S +++ b/runtime/interpreter/mterp/mips64/instruction_start_sister.S @@ -1,3 +1,4 @@ +%def instruction_start_sister(): .global artMterpAsmSisterStart .text diff --git a/runtime/interpreter/mterp/mips64/invoke.S b/runtime/interpreter/mterp/mips64/invoke.S index be647b618b..caf5698f52 100644 --- a/runtime/interpreter/mterp/mips64/invoke.S +++ b/runtime/interpreter/mterp/mips64/invoke.S @@ -1,4 +1,4 @@ -%default { "helper":"UndefinedInvokeHandler" } +%def invoke(helper="UndefinedInvokeHandler"): /* * Generic invoke handler wrapper. */ diff --git a/runtime/interpreter/mterp/mips64/invoke_polymorphic.S b/runtime/interpreter/mterp/mips64/invoke_polymorphic.S index fa82083276..3a10554b66 100644 --- a/runtime/interpreter/mterp/mips64/invoke_polymorphic.S +++ b/runtime/interpreter/mterp/mips64/invoke_polymorphic.S @@ -1,4 +1,4 @@ -%default { "helper":"UndefinedInvokeHandler" } +%def invoke_polymorphic(helper="UndefinedInvokeHandler"): /* * invoke-polymorphic handler wrapper. */ diff --git a/runtime/interpreter/mterp/mips64/op_add_double.S b/runtime/interpreter/mterp/mips64/op_add_double.S index 1520e325f7..0c1f6a28be 100644 --- a/runtime/interpreter/mterp/mips64/op_add_double.S +++ b/runtime/interpreter/mterp/mips64/op_add_double.S @@ -1 +1,2 @@ -%include "mips64/fbinopWide.S" {"instr":"add.d f0, f0, f1"} +%def op_add_double(): +% fbinopWide(instr="add.d f0, f0, f1") diff --git a/runtime/interpreter/mterp/mips64/op_add_double_2addr.S b/runtime/interpreter/mterp/mips64/op_add_double_2addr.S index c14382ef20..f667996243 100644 --- a/runtime/interpreter/mterp/mips64/op_add_double_2addr.S +++ b/runtime/interpreter/mterp/mips64/op_add_double_2addr.S @@ -1 +1,2 @@ -%include "mips64/fbinopWide2addr.S" {"instr":"add.d f0, f0, f1"} +%def op_add_double_2addr(): +% fbinopWide2addr(instr="add.d f0, f0, f1") diff --git a/runtime/interpreter/mterp/mips64/op_add_float.S b/runtime/interpreter/mterp/mips64/op_add_float.S index c6ed558dc3..4c0f88c71a 100644 --- a/runtime/interpreter/mterp/mips64/op_add_float.S +++ b/runtime/interpreter/mterp/mips64/op_add_float.S @@ -1 +1,2 @@ -%include "mips64/fbinop.S" {"instr":"add.s f0, f0, f1"} +%def op_add_float(): +% fbinop(instr="add.s f0, f0, f1") diff --git a/runtime/interpreter/mterp/mips64/op_add_float_2addr.S b/runtime/interpreter/mterp/mips64/op_add_float_2addr.S index 4c20547b22..0bcc91aa27 100644 --- a/runtime/interpreter/mterp/mips64/op_add_float_2addr.S +++ b/runtime/interpreter/mterp/mips64/op_add_float_2addr.S @@ -1 +1,2 @@ -%include "mips64/fbinop2addr.S" {"instr":"add.s f0, f0, f1"} +%def op_add_float_2addr(): +% fbinop2addr(instr="add.s f0, f0, f1") diff --git a/runtime/interpreter/mterp/mips64/op_add_int.S b/runtime/interpreter/mterp/mips64/op_add_int.S index 6e569de71a..ed0fc012b8 100644 --- a/runtime/interpreter/mterp/mips64/op_add_int.S +++ b/runtime/interpreter/mterp/mips64/op_add_int.S @@ -1 +1,2 @@ -%include "mips64/binop.S" {"instr":"addu a0, a0, a1"} +%def op_add_int(): +% binop(instr="addu a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_add_int_2addr.S b/runtime/interpreter/mterp/mips64/op_add_int_2addr.S index 2a84124a3a..ed0b1314ef 100644 --- a/runtime/interpreter/mterp/mips64/op_add_int_2addr.S +++ b/runtime/interpreter/mterp/mips64/op_add_int_2addr.S @@ -1 +1,2 @@ -%include "mips64/binop2addr.S" {"instr":"addu a0, a0, a1"} +%def op_add_int_2addr(): +% binop2addr(instr="addu a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_add_int_lit16.S b/runtime/interpreter/mterp/mips64/op_add_int_lit16.S index 94b053bba3..126807a303 100644 --- a/runtime/interpreter/mterp/mips64/op_add_int_lit16.S +++ b/runtime/interpreter/mterp/mips64/op_add_int_lit16.S @@ -1 +1,2 @@ -%include "mips64/binopLit16.S" {"instr":"addu a0, a0, a1"} +%def op_add_int_lit16(): +% binopLit16(instr="addu a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_add_int_lit8.S b/runtime/interpreter/mterp/mips64/op_add_int_lit8.S index 3b6d734723..30184c40f5 100644 --- a/runtime/interpreter/mterp/mips64/op_add_int_lit8.S +++ b/runtime/interpreter/mterp/mips64/op_add_int_lit8.S @@ -1 +1,2 @@ -%include "mips64/binopLit8.S" {"instr":"addu a0, a0, a1"} +%def op_add_int_lit8(): +% binopLit8(instr="addu a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_add_long.S b/runtime/interpreter/mterp/mips64/op_add_long.S index c8d702f29f..72a1f24abb 100644 --- a/runtime/interpreter/mterp/mips64/op_add_long.S +++ b/runtime/interpreter/mterp/mips64/op_add_long.S @@ -1 +1,2 @@ -%include "mips64/binopWide.S" {"instr":"daddu a0, a0, a1"} +%def op_add_long(): +% binopWide(instr="daddu a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_add_long_2addr.S b/runtime/interpreter/mterp/mips64/op_add_long_2addr.S index 928ff54565..caf29e230d 100644 --- a/runtime/interpreter/mterp/mips64/op_add_long_2addr.S +++ b/runtime/interpreter/mterp/mips64/op_add_long_2addr.S @@ -1 +1,2 @@ -%include "mips64/binopWide2addr.S" {"instr":"daddu a0, a0, a1"} +%def op_add_long_2addr(): +% binopWide2addr(instr="daddu a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_aget.S b/runtime/interpreter/mterp/mips64/op_aget.S index 0472a0616b..60be23dc7a 100644 --- a/runtime/interpreter/mterp/mips64/op_aget.S +++ b/runtime/interpreter/mterp/mips64/op_aget.S @@ -1,4 +1,4 @@ -%default { "load":"lw", "shift":"2", "data_offset":"MIRROR_INT_ARRAY_DATA_OFFSET" } +%def op_aget(load="lw", shift="2", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"): /* * Array get, 32 bits or less. vAA <- vBB[vCC]. * diff --git a/runtime/interpreter/mterp/mips64/op_aget_boolean.S b/runtime/interpreter/mterp/mips64/op_aget_boolean.S index d5be01b7c5..7b28bc8e06 100644 --- a/runtime/interpreter/mterp/mips64/op_aget_boolean.S +++ b/runtime/interpreter/mterp/mips64/op_aget_boolean.S @@ -1 +1,2 @@ -%include "mips64/op_aget.S" { "load":"lbu", "shift":"0", "data_offset":"MIRROR_BOOLEAN_ARRAY_DATA_OFFSET" } +%def op_aget_boolean(): +% op_aget(load="lbu", shift="0", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/mips64/op_aget_byte.S b/runtime/interpreter/mterp/mips64/op_aget_byte.S index 084de8d4df..a4a0b7e9b7 100644 --- a/runtime/interpreter/mterp/mips64/op_aget_byte.S +++ b/runtime/interpreter/mterp/mips64/op_aget_byte.S @@ -1 +1,2 @@ -%include "mips64/op_aget.S" { "load":"lb", "shift":"0", "data_offset":"MIRROR_BYTE_ARRAY_DATA_OFFSET" } +%def op_aget_byte(): +% op_aget(load="lb", shift="0", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/mips64/op_aget_char.S b/runtime/interpreter/mterp/mips64/op_aget_char.S index 6c99ed52ad..465de097cd 100644 --- a/runtime/interpreter/mterp/mips64/op_aget_char.S +++ b/runtime/interpreter/mterp/mips64/op_aget_char.S @@ -1 +1,2 @@ -%include "mips64/op_aget.S" { "load":"lhu", "shift":"1", "data_offset":"MIRROR_CHAR_ARRAY_DATA_OFFSET" } +%def op_aget_char(): +% op_aget(load="lhu", shift="1", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/mips64/op_aget_object.S b/runtime/interpreter/mterp/mips64/op_aget_object.S index 6374a05e7b..48d751b197 100644 --- a/runtime/interpreter/mterp/mips64/op_aget_object.S +++ b/runtime/interpreter/mterp/mips64/op_aget_object.S @@ -1,3 +1,4 @@ +%def op_aget_object(): /* * Array object get. vAA <- vBB[vCC]. * diff --git a/runtime/interpreter/mterp/mips64/op_aget_short.S b/runtime/interpreter/mterp/mips64/op_aget_short.S index 0158b0a1a1..4faa9ad358 100644 --- a/runtime/interpreter/mterp/mips64/op_aget_short.S +++ b/runtime/interpreter/mterp/mips64/op_aget_short.S @@ -1 +1,2 @@ -%include "mips64/op_aget.S" { "load":"lh", "shift":"1", "data_offset":"MIRROR_SHORT_ARRAY_DATA_OFFSET" } +%def op_aget_short(): +% op_aget(load="lh", shift="1", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/mips64/op_aget_wide.S b/runtime/interpreter/mterp/mips64/op_aget_wide.S index 0945acae5a..99b0de9b64 100644 --- a/runtime/interpreter/mterp/mips64/op_aget_wide.S +++ b/runtime/interpreter/mterp/mips64/op_aget_wide.S @@ -1,3 +1,4 @@ +%def op_aget_wide(): /* * Array get, 64 bits. vAA <- vBB[vCC]. * diff --git a/runtime/interpreter/mterp/mips64/op_and_int.S b/runtime/interpreter/mterp/mips64/op_and_int.S index f0792a8351..740411ddf7 100644 --- a/runtime/interpreter/mterp/mips64/op_and_int.S +++ b/runtime/interpreter/mterp/mips64/op_and_int.S @@ -1 +1,2 @@ -%include "mips64/binop.S" {"instr":"and a0, a0, a1"} +%def op_and_int(): +% binop(instr="and a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_and_int_2addr.S b/runtime/interpreter/mterp/mips64/op_and_int_2addr.S index 08dc615518..8224e5f18a 100644 --- a/runtime/interpreter/mterp/mips64/op_and_int_2addr.S +++ b/runtime/interpreter/mterp/mips64/op_and_int_2addr.S @@ -1 +1,2 @@ -%include "mips64/binop2addr.S" {"instr":"and a0, a0, a1"} +%def op_and_int_2addr(): +% binop2addr(instr="and a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_and_int_lit16.S b/runtime/interpreter/mterp/mips64/op_and_int_lit16.S index 65d28ad20c..5031f500ce 100644 --- a/runtime/interpreter/mterp/mips64/op_and_int_lit16.S +++ b/runtime/interpreter/mterp/mips64/op_and_int_lit16.S @@ -1 +1,2 @@ -%include "mips64/binopLit16.S" {"instr":"and a0, a0, a1"} +%def op_and_int_lit16(): +% binopLit16(instr="and a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_and_int_lit8.S b/runtime/interpreter/mterp/mips64/op_and_int_lit8.S index ab84bb7ce2..7a7b8b5d5a 100644 --- a/runtime/interpreter/mterp/mips64/op_and_int_lit8.S +++ b/runtime/interpreter/mterp/mips64/op_and_int_lit8.S @@ -1 +1,2 @@ -%include "mips64/binopLit8.S" {"instr":"and a0, a0, a1"} +%def op_and_int_lit8(): +% binopLit8(instr="and a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_and_long.S b/runtime/interpreter/mterp/mips64/op_and_long.S index e383ba00ca..242ddf2e2c 100644 --- a/runtime/interpreter/mterp/mips64/op_and_long.S +++ b/runtime/interpreter/mterp/mips64/op_and_long.S @@ -1 +1,2 @@ -%include "mips64/binopWide.S" {"instr":"and a0, a0, a1"} +%def op_and_long(): +% binopWide(instr="and a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_and_long_2addr.S b/runtime/interpreter/mterp/mips64/op_and_long_2addr.S index f863bb9275..64b5a7e65e 100644 --- a/runtime/interpreter/mterp/mips64/op_and_long_2addr.S +++ b/runtime/interpreter/mterp/mips64/op_and_long_2addr.S @@ -1 +1,2 @@ -%include "mips64/binopWide2addr.S" {"instr":"and a0, a0, a1"} +%def op_and_long_2addr(): +% binopWide2addr(instr="and a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_aput.S b/runtime/interpreter/mterp/mips64/op_aput.S index 9bfda97d05..f4c04d01d0 100644 --- a/runtime/interpreter/mterp/mips64/op_aput.S +++ b/runtime/interpreter/mterp/mips64/op_aput.S @@ -1,4 +1,4 @@ -%default { "store":"sw", "shift":"2", "data_offset":"MIRROR_INT_ARRAY_DATA_OFFSET" } +%def op_aput(store="sw", shift="2", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"): /* * Array put, 32 bits or less. vBB[vCC] <- vAA. * diff --git a/runtime/interpreter/mterp/mips64/op_aput_boolean.S b/runtime/interpreter/mterp/mips64/op_aput_boolean.S index 6707a1f11d..098bbcd1c4 100644 --- a/runtime/interpreter/mterp/mips64/op_aput_boolean.S +++ b/runtime/interpreter/mterp/mips64/op_aput_boolean.S @@ -1 +1,2 @@ -%include "mips64/op_aput.S" { "store":"sb", "shift":"0", "data_offset":"MIRROR_BOOLEAN_ARRAY_DATA_OFFSET" } +%def op_aput_boolean(): +% op_aput(store="sb", shift="0", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/mips64/op_aput_byte.S b/runtime/interpreter/mterp/mips64/op_aput_byte.S index 7b9ce48379..f4b42ee6e8 100644 --- a/runtime/interpreter/mterp/mips64/op_aput_byte.S +++ b/runtime/interpreter/mterp/mips64/op_aput_byte.S @@ -1 +1,2 @@ -%include "mips64/op_aput.S" { "store":"sb", "shift":"0", "data_offset":"MIRROR_BYTE_ARRAY_DATA_OFFSET" } +%def op_aput_byte(): +% op_aput(store="sb", shift="0", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/mips64/op_aput_char.S b/runtime/interpreter/mterp/mips64/op_aput_char.S index 82bc8f7818..18eedae68d 100644 --- a/runtime/interpreter/mterp/mips64/op_aput_char.S +++ b/runtime/interpreter/mterp/mips64/op_aput_char.S @@ -1 +1,2 @@ -%include "mips64/op_aput.S" { "store":"sh", "shift":"1", "data_offset":"MIRROR_CHAR_ARRAY_DATA_OFFSET" } +%def op_aput_char(): +% op_aput(store="sh", shift="1", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/mips64/op_aput_object.S b/runtime/interpreter/mterp/mips64/op_aput_object.S index b132456a18..6b23e90e41 100644 --- a/runtime/interpreter/mterp/mips64/op_aput_object.S +++ b/runtime/interpreter/mterp/mips64/op_aput_object.S @@ -1,3 +1,4 @@ +%def op_aput_object(): /* * Store an object into an array. vBB[vCC] <- vAA. */ diff --git a/runtime/interpreter/mterp/mips64/op_aput_short.S b/runtime/interpreter/mterp/mips64/op_aput_short.S index a7af2945b1..61a3c0d6ea 100644 --- a/runtime/interpreter/mterp/mips64/op_aput_short.S +++ b/runtime/interpreter/mterp/mips64/op_aput_short.S @@ -1 +1,2 @@ -%include "mips64/op_aput.S" { "store":"sh", "shift":"1", "data_offset":"MIRROR_SHORT_ARRAY_DATA_OFFSET" } +%def op_aput_short(): +% op_aput(store="sh", shift="1", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/mips64/op_aput_wide.S b/runtime/interpreter/mterp/mips64/op_aput_wide.S index a1d7a3b51e..4fad5c462c 100644 --- a/runtime/interpreter/mterp/mips64/op_aput_wide.S +++ b/runtime/interpreter/mterp/mips64/op_aput_wide.S @@ -1,3 +1,4 @@ +%def op_aput_wide(): /* * Array put, 64 bits. vBB[vCC] <- vAA. * diff --git a/runtime/interpreter/mterp/mips64/op_array_length.S b/runtime/interpreter/mterp/mips64/op_array_length.S index 2d9e172d18..13b9a13b9c 100644 --- a/runtime/interpreter/mterp/mips64/op_array_length.S +++ b/runtime/interpreter/mterp/mips64/op_array_length.S @@ -1,3 +1,4 @@ +%def op_array_length(): /* * Return the length of an array. */ diff --git a/runtime/interpreter/mterp/mips64/op_check_cast.S b/runtime/interpreter/mterp/mips64/op_check_cast.S index 472595d824..b5f0f1fb27 100644 --- a/runtime/interpreter/mterp/mips64/op_check_cast.S +++ b/runtime/interpreter/mterp/mips64/op_check_cast.S @@ -1,3 +1,4 @@ +%def op_check_cast(): /* * Check to see if a cast from one class to another is allowed. */ diff --git a/runtime/interpreter/mterp/mips64/op_cmp_long.S b/runtime/interpreter/mterp/mips64/op_cmp_long.S index 6e9376cfab..87eba4421c 100644 --- a/runtime/interpreter/mterp/mips64/op_cmp_long.S +++ b/runtime/interpreter/mterp/mips64/op_cmp_long.S @@ -1,3 +1,4 @@ +%def op_cmp_long(): /* cmp-long vAA, vBB, vCC */ lbu a2, 2(rPC) # a2 <- BB lbu a3, 3(rPC) # a3 <- CC diff --git a/runtime/interpreter/mterp/mips64/op_cmpg_double.S b/runtime/interpreter/mterp/mips64/op_cmpg_double.S index a8e2ef9867..4c3117b7e7 100644 --- a/runtime/interpreter/mterp/mips64/op_cmpg_double.S +++ b/runtime/interpreter/mterp/mips64/op_cmpg_double.S @@ -1 +1,2 @@ -%include "mips64/fcmpWide.S" {"gt_bias":"1"} +%def op_cmpg_double(): +% fcmpWide(gt_bias="1") diff --git a/runtime/interpreter/mterp/mips64/op_cmpg_float.S b/runtime/interpreter/mterp/mips64/op_cmpg_float.S index 0c93eac7de..99c4530f82 100644 --- a/runtime/interpreter/mterp/mips64/op_cmpg_float.S +++ b/runtime/interpreter/mterp/mips64/op_cmpg_float.S @@ -1 +1,2 @@ -%include "mips64/fcmp.S" {"gt_bias":"1"} +%def op_cmpg_float(): +% fcmp(gt_bias="1") diff --git a/runtime/interpreter/mterp/mips64/op_cmpl_double.S b/runtime/interpreter/mterp/mips64/op_cmpl_double.S index 9111b067f6..4900bddffc 100644 --- a/runtime/interpreter/mterp/mips64/op_cmpl_double.S +++ b/runtime/interpreter/mterp/mips64/op_cmpl_double.S @@ -1 +1,2 @@ -%include "mips64/fcmpWide.S" {"gt_bias":"0"} +%def op_cmpl_double(): +% fcmpWide(gt_bias="0") diff --git a/runtime/interpreter/mterp/mips64/op_cmpl_float.S b/runtime/interpreter/mterp/mips64/op_cmpl_float.S index b047451842..159c66dc06 100644 --- a/runtime/interpreter/mterp/mips64/op_cmpl_float.S +++ b/runtime/interpreter/mterp/mips64/op_cmpl_float.S @@ -1 +1,2 @@ -%include "mips64/fcmp.S" {"gt_bias":"0"} +%def op_cmpl_float(): +% fcmp(gt_bias="0") diff --git a/runtime/interpreter/mterp/mips64/op_const.S b/runtime/interpreter/mterp/mips64/op_const.S index 4b0d69b763..619304264f 100644 --- a/runtime/interpreter/mterp/mips64/op_const.S +++ b/runtime/interpreter/mterp/mips64/op_const.S @@ -1,3 +1,4 @@ +%def op_const(): /* const vAA, #+BBBBbbbb */ srl a2, rINST, 8 # a2 <- AA lh a0, 2(rPC) # a0 <- bbbb (low) diff --git a/runtime/interpreter/mterp/mips64/op_const_16.S b/runtime/interpreter/mterp/mips64/op_const_16.S index 51e68a7df7..aac542d847 100644 --- a/runtime/interpreter/mterp/mips64/op_const_16.S +++ b/runtime/interpreter/mterp/mips64/op_const_16.S @@ -1,3 +1,4 @@ +%def op_const_16(): /* const/16 vAA, #+BBBB */ srl a2, rINST, 8 # a2 <- AA lh a0, 2(rPC) # a0 <- sign-extended BBBB diff --git a/runtime/interpreter/mterp/mips64/op_const_4.S b/runtime/interpreter/mterp/mips64/op_const_4.S index 0a58bff7b7..d26f4e56b1 100644 --- a/runtime/interpreter/mterp/mips64/op_const_4.S +++ b/runtime/interpreter/mterp/mips64/op_const_4.S @@ -1,3 +1,4 @@ +%def op_const_4(): /* const/4 vA, #+B */ ext a2, rINST, 8, 4 # a2 <- A seh a0, rINST # sign extend B in rINST diff --git a/runtime/interpreter/mterp/mips64/op_const_class.S b/runtime/interpreter/mterp/mips64/op_const_class.S index 3f0c716d5e..db12ec3141 100644 --- a/runtime/interpreter/mterp/mips64/op_const_class.S +++ b/runtime/interpreter/mterp/mips64/op_const_class.S @@ -1 +1,2 @@ -%include "mips64/const.S" { "helper":"MterpConstClass" } +%def op_const_class(): +% const(helper="MterpConstClass") diff --git a/runtime/interpreter/mterp/mips64/op_const_high16.S b/runtime/interpreter/mterp/mips64/op_const_high16.S index 43effb6f60..bf14ab6907 100644 --- a/runtime/interpreter/mterp/mips64/op_const_high16.S +++ b/runtime/interpreter/mterp/mips64/op_const_high16.S @@ -1,3 +1,4 @@ +%def op_const_high16(): /* const/high16 vAA, #+BBBB0000 */ srl a2, rINST, 8 # a2 <- AA lh a0, 2(rPC) # a0 <- BBBB diff --git a/runtime/interpreter/mterp/mips64/op_const_method_handle.S b/runtime/interpreter/mterp/mips64/op_const_method_handle.S index 43584d179c..2680c17aad 100644 --- a/runtime/interpreter/mterp/mips64/op_const_method_handle.S +++ b/runtime/interpreter/mterp/mips64/op_const_method_handle.S @@ -1 +1,2 @@ -%include "mips64/const.S" { "helper":"MterpConstMethodHandle" } +%def op_const_method_handle(): +% const(helper="MterpConstMethodHandle") diff --git a/runtime/interpreter/mterp/mips64/op_const_method_type.S b/runtime/interpreter/mterp/mips64/op_const_method_type.S index 553b28424a..ea814bf648 100644 --- a/runtime/interpreter/mterp/mips64/op_const_method_type.S +++ b/runtime/interpreter/mterp/mips64/op_const_method_type.S @@ -1 +1,2 @@ -%include "mips64/const.S" { "helper":"MterpConstMethodType" } +%def op_const_method_type(): +% const(helper="MterpConstMethodType") diff --git a/runtime/interpreter/mterp/mips64/op_const_string.S b/runtime/interpreter/mterp/mips64/op_const_string.S index 96cbb5a23a..41376f8703 100644 --- a/runtime/interpreter/mterp/mips64/op_const_string.S +++ b/runtime/interpreter/mterp/mips64/op_const_string.S @@ -1 +1,2 @@ -%include "mips64/const.S" { "helper":"MterpConstString" } +%def op_const_string(): +% const(helper="MterpConstString") diff --git a/runtime/interpreter/mterp/mips64/op_const_string_jumbo.S b/runtime/interpreter/mterp/mips64/op_const_string_jumbo.S index 47f2101c88..25ec0e2b8d 100644 --- a/runtime/interpreter/mterp/mips64/op_const_string_jumbo.S +++ b/runtime/interpreter/mterp/mips64/op_const_string_jumbo.S @@ -1,3 +1,4 @@ +%def op_const_string_jumbo(): /* const/string vAA, String//BBBBBBBB */ .extern MterpConstString EXPORT_PC diff --git a/runtime/interpreter/mterp/mips64/op_const_wide.S b/runtime/interpreter/mterp/mips64/op_const_wide.S index f7eaf7c231..7c4a99acac 100644 --- a/runtime/interpreter/mterp/mips64/op_const_wide.S +++ b/runtime/interpreter/mterp/mips64/op_const_wide.S @@ -1,3 +1,4 @@ +%def op_const_wide(): /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ srl a4, rINST, 8 # a4 <- AA lh a0, 2(rPC) # a0 <- bbbb (low) diff --git a/runtime/interpreter/mterp/mips64/op_const_wide_16.S b/runtime/interpreter/mterp/mips64/op_const_wide_16.S index 3a70937973..65f30682a7 100644 --- a/runtime/interpreter/mterp/mips64/op_const_wide_16.S +++ b/runtime/interpreter/mterp/mips64/op_const_wide_16.S @@ -1,3 +1,4 @@ +%def op_const_wide_16(): /* const-wide/16 vAA, #+BBBB */ srl a2, rINST, 8 # a2 <- AA lh a0, 2(rPC) # a0 <- sign-extended BBBB diff --git a/runtime/interpreter/mterp/mips64/op_const_wide_32.S b/runtime/interpreter/mterp/mips64/op_const_wide_32.S index 867197ce13..39fa0f9c02 100644 --- a/runtime/interpreter/mterp/mips64/op_const_wide_32.S +++ b/runtime/interpreter/mterp/mips64/op_const_wide_32.S @@ -1,3 +1,4 @@ +%def op_const_wide_32(): /* const-wide/32 vAA, #+BBBBbbbb */ srl a2, rINST, 8 # a2 <- AA lh a0, 2(rPC) # a0 <- bbbb (low) diff --git a/runtime/interpreter/mterp/mips64/op_const_wide_high16.S b/runtime/interpreter/mterp/mips64/op_const_wide_high16.S index d741631bcb..7c538c135d 100644 --- a/runtime/interpreter/mterp/mips64/op_const_wide_high16.S +++ b/runtime/interpreter/mterp/mips64/op_const_wide_high16.S @@ -1,3 +1,4 @@ +%def op_const_wide_high16(): /* const-wide/high16 vAA, #+BBBB000000000000 */ srl a2, rINST, 8 # a2 <- AA lh a0, 2(rPC) # a0 <- BBBB diff --git a/runtime/interpreter/mterp/mips64/op_div_double.S b/runtime/interpreter/mterp/mips64/op_div_double.S index 44998f0c29..c134dfb738 100644 --- a/runtime/interpreter/mterp/mips64/op_div_double.S +++ b/runtime/interpreter/mterp/mips64/op_div_double.S @@ -1 +1,2 @@ -%include "mips64/fbinopWide.S" {"instr":"div.d f0, f0, f1"} +%def op_div_double(): +% fbinopWide(instr="div.d f0, f0, f1") diff --git a/runtime/interpreter/mterp/mips64/op_div_double_2addr.S b/runtime/interpreter/mterp/mips64/op_div_double_2addr.S index 396af798f6..6ac1d757dc 100644 --- a/runtime/interpreter/mterp/mips64/op_div_double_2addr.S +++ b/runtime/interpreter/mterp/mips64/op_div_double_2addr.S @@ -1 +1,2 @@ -%include "mips64/fbinopWide2addr.S" {"instr":"div.d f0, f0, f1"} +%def op_div_double_2addr(): +% fbinopWide2addr(instr="div.d f0, f0, f1") diff --git a/runtime/interpreter/mterp/mips64/op_div_float.S b/runtime/interpreter/mterp/mips64/op_div_float.S index 7b09d52f02..97530321b7 100644 --- a/runtime/interpreter/mterp/mips64/op_div_float.S +++ b/runtime/interpreter/mterp/mips64/op_div_float.S @@ -1 +1,2 @@ -%include "mips64/fbinop.S" {"instr":"div.s f0, f0, f1"} +%def op_div_float(): +% fbinop(instr="div.s f0, f0, f1") diff --git a/runtime/interpreter/mterp/mips64/op_div_float_2addr.S b/runtime/interpreter/mterp/mips64/op_div_float_2addr.S index e74fddae6d..53421ce295 100644 --- a/runtime/interpreter/mterp/mips64/op_div_float_2addr.S +++ b/runtime/interpreter/mterp/mips64/op_div_float_2addr.S @@ -1 +1,2 @@ -%include "mips64/fbinop2addr.S" {"instr":"div.s f0, f0, f1"} +%def op_div_float_2addr(): +% fbinop2addr(instr="div.s f0, f0, f1") diff --git a/runtime/interpreter/mterp/mips64/op_div_int.S b/runtime/interpreter/mterp/mips64/op_div_int.S index fb04acbff8..da9bfcbdb0 100644 --- a/runtime/interpreter/mterp/mips64/op_div_int.S +++ b/runtime/interpreter/mterp/mips64/op_div_int.S @@ -1 +1,2 @@ -%include "mips64/binop.S" {"instr":"div a0, a0, a1", "chkzero":"1"} +%def op_div_int(): +% binop(instr="div a0, a0, a1", chkzero="1") diff --git a/runtime/interpreter/mterp/mips64/op_div_int_2addr.S b/runtime/interpreter/mterp/mips64/op_div_int_2addr.S index db29b844fb..7c9444277e 100644 --- a/runtime/interpreter/mterp/mips64/op_div_int_2addr.S +++ b/runtime/interpreter/mterp/mips64/op_div_int_2addr.S @@ -1 +1,2 @@ -%include "mips64/binop2addr.S" {"instr":"div a0, a0, a1", "chkzero":"1"} +%def op_div_int_2addr(): +% binop2addr(instr="div a0, a0, a1", chkzero="1") diff --git a/runtime/interpreter/mterp/mips64/op_div_int_lit16.S b/runtime/interpreter/mterp/mips64/op_div_int_lit16.S index e903ddee2c..4afe80e07d 100644 --- a/runtime/interpreter/mterp/mips64/op_div_int_lit16.S +++ b/runtime/interpreter/mterp/mips64/op_div_int_lit16.S @@ -1 +1,2 @@ -%include "mips64/binopLit16.S" {"instr":"div a0, a0, a1", "chkzero":"1"} +%def op_div_int_lit16(): +% binopLit16(instr="div a0, a0, a1", chkzero="1") diff --git a/runtime/interpreter/mterp/mips64/op_div_int_lit8.S b/runtime/interpreter/mterp/mips64/op_div_int_lit8.S index 055960546f..7e2df1b312 100644 --- a/runtime/interpreter/mterp/mips64/op_div_int_lit8.S +++ b/runtime/interpreter/mterp/mips64/op_div_int_lit8.S @@ -1 +1,2 @@ -%include "mips64/binopLit8.S" {"instr":"div a0, a0, a1", "chkzero":"1"} +%def op_div_int_lit8(): +% binopLit8(instr="div a0, a0, a1", chkzero="1") diff --git a/runtime/interpreter/mterp/mips64/op_div_long.S b/runtime/interpreter/mterp/mips64/op_div_long.S index 01fc2b281a..93c21874ba 100644 --- a/runtime/interpreter/mterp/mips64/op_div_long.S +++ b/runtime/interpreter/mterp/mips64/op_div_long.S @@ -1 +1,2 @@ -%include "mips64/binopWide.S" {"instr":"ddiv a0, a0, a1", "chkzero":"1"} +%def op_div_long(): +% binopWide(instr="ddiv a0, a0, a1", chkzero="1") diff --git a/runtime/interpreter/mterp/mips64/op_div_long_2addr.S b/runtime/interpreter/mterp/mips64/op_div_long_2addr.S index 9627ab8a24..74ecb20154 100644 --- a/runtime/interpreter/mterp/mips64/op_div_long_2addr.S +++ b/runtime/interpreter/mterp/mips64/op_div_long_2addr.S @@ -1 +1,2 @@ -%include "mips64/binopWide2addr.S" {"instr":"ddiv a0, a0, a1", "chkzero":"1"} +%def op_div_long_2addr(): +% binopWide2addr(instr="ddiv a0, a0, a1", chkzero="1") diff --git a/runtime/interpreter/mterp/mips64/op_double_to_float.S b/runtime/interpreter/mterp/mips64/op_double_to_float.S index 2b2acee591..f19b47fcae 100644 --- a/runtime/interpreter/mterp/mips64/op_double_to_float.S +++ b/runtime/interpreter/mterp/mips64/op_double_to_float.S @@ -1,8 +1,9 @@ +%def op_double_to_float(): /* * Conversion from or to floating-point happens in a floating-point register. * Therefore we load the input and store the output into or from a * floating-point register irrespective of the type. */ -%include "mips64/fcvtHeader.S" { "suffix":"_DOUBLE", "valreg":"f0" } +% fcvtHeader(suffix="_DOUBLE", valreg="f0") cvt.s.d f0, f0 -%include "mips64/fcvtFooter.S" { "suffix":"_FLOAT", "valreg":"f0" } +% fcvtFooter(suffix="_FLOAT", valreg="f0") diff --git a/runtime/interpreter/mterp/mips64/op_double_to_int.S b/runtime/interpreter/mterp/mips64/op_double_to_int.S index d09952233c..ba370a26bb 100644 --- a/runtime/interpreter/mterp/mips64/op_double_to_int.S +++ b/runtime/interpreter/mterp/mips64/op_double_to_int.S @@ -1,3 +1,4 @@ -%include "mips64/fcvtHeader.S" { "suffix":"_DOUBLE", "valreg":"f0" } +%def op_double_to_int(): +% fcvtHeader(suffix="_DOUBLE", valreg="f0") trunc.w.d f0, f0 -%include "mips64/fcvtFooter.S" { "suffix":"_FLOAT", "valreg":"f0" } +% fcvtFooter(suffix="_FLOAT", valreg="f0") diff --git a/runtime/interpreter/mterp/mips64/op_double_to_long.S b/runtime/interpreter/mterp/mips64/op_double_to_long.S index 9b65da5602..1050a725ab 100644 --- a/runtime/interpreter/mterp/mips64/op_double_to_long.S +++ b/runtime/interpreter/mterp/mips64/op_double_to_long.S @@ -1,3 +1,4 @@ -%include "mips64/fcvtHeader.S" { "suffix":"_DOUBLE", "valreg":"f0" } +%def op_double_to_long(): +% fcvtHeader(suffix="_DOUBLE", valreg="f0") trunc.l.d f0, f0 -%include "mips64/fcvtFooter.S" { "suffix":"_DOUBLE", "valreg":"f0" } +% fcvtFooter(suffix="_DOUBLE", valreg="f0") diff --git a/runtime/interpreter/mterp/mips64/op_fill_array_data.S b/runtime/interpreter/mterp/mips64/op_fill_array_data.S index c90f0b90ad..5ccff911c9 100644 --- a/runtime/interpreter/mterp/mips64/op_fill_array_data.S +++ b/runtime/interpreter/mterp/mips64/op_fill_array_data.S @@ -1,3 +1,4 @@ +%def op_fill_array_data(): /* fill-array-data vAA, +BBBBBBBB */ .extern MterpFillArrayData EXPORT_PC diff --git a/runtime/interpreter/mterp/mips64/op_filled_new_array.S b/runtime/interpreter/mterp/mips64/op_filled_new_array.S index 35f55c27a6..d86ce16cce 100644 --- a/runtime/interpreter/mterp/mips64/op_filled_new_array.S +++ b/runtime/interpreter/mterp/mips64/op_filled_new_array.S @@ -1,4 +1,4 @@ -%default { "helper":"MterpFilledNewArray" } +%def op_filled_new_array(helper="MterpFilledNewArray"): /* * Create a new array with elements filled from registers. * diff --git a/runtime/interpreter/mterp/mips64/op_filled_new_array_range.S b/runtime/interpreter/mterp/mips64/op_filled_new_array_range.S index a4e18f68d6..1667de149a 100644 --- a/runtime/interpreter/mterp/mips64/op_filled_new_array_range.S +++ b/runtime/interpreter/mterp/mips64/op_filled_new_array_range.S @@ -1 +1,2 @@ -%include "mips64/op_filled_new_array.S" { "helper":"MterpFilledNewArrayRange" } +%def op_filled_new_array_range(): +% op_filled_new_array(helper="MterpFilledNewArrayRange") diff --git a/runtime/interpreter/mterp/mips64/op_float_to_double.S b/runtime/interpreter/mterp/mips64/op_float_to_double.S index 6accfeeff6..feebdd8b1d 100644 --- a/runtime/interpreter/mterp/mips64/op_float_to_double.S +++ b/runtime/interpreter/mterp/mips64/op_float_to_double.S @@ -1,8 +1,9 @@ +%def op_float_to_double(): /* * Conversion from or to floating-point happens in a floating-point register. * Therefore we load the input and store the output into or from a * floating-point register irrespective of the type. */ -%include "mips64/fcvtHeader.S" { "suffix":"_FLOAT", "valreg":"f0" } +% fcvtHeader(suffix="_FLOAT", valreg="f0") cvt.d.s f0, f0 -%include "mips64/fcvtFooter.S" { "suffix":"_DOUBLE", "valreg":"f0" } +% fcvtFooter(suffix="_DOUBLE", valreg="f0") diff --git a/runtime/interpreter/mterp/mips64/op_float_to_int.S b/runtime/interpreter/mterp/mips64/op_float_to_int.S index 2806973935..cbfe85339c 100644 --- a/runtime/interpreter/mterp/mips64/op_float_to_int.S +++ b/runtime/interpreter/mterp/mips64/op_float_to_int.S @@ -1,3 +1,4 @@ -%include "mips64/fcvtHeader.S" { "suffix":"_FLOAT", "valreg":"f0" } +%def op_float_to_int(): +% fcvtHeader(suffix="_FLOAT", valreg="f0") trunc.w.s f0, f0 -%include "mips64/fcvtFooter.S" { "suffix":"_FLOAT", "valreg":"f0" } +% fcvtFooter(suffix="_FLOAT", valreg="f0") diff --git a/runtime/interpreter/mterp/mips64/op_float_to_long.S b/runtime/interpreter/mterp/mips64/op_float_to_long.S index c40c8a6680..ccf23b1006 100644 --- a/runtime/interpreter/mterp/mips64/op_float_to_long.S +++ b/runtime/interpreter/mterp/mips64/op_float_to_long.S @@ -1,3 +1,4 @@ -%include "mips64/fcvtHeader.S" { "suffix":"_FLOAT", "valreg":"f0" } +%def op_float_to_long(): +% fcvtHeader(suffix="_FLOAT", valreg="f0") trunc.l.s f0, f0 -%include "mips64/fcvtFooter.S" { "suffix":"_DOUBLE", "valreg":"f0" } +% fcvtFooter(suffix="_DOUBLE", valreg="f0") diff --git a/runtime/interpreter/mterp/mips64/op_goto.S b/runtime/interpreter/mterp/mips64/op_goto.S index 68fc83d0ca..371bae7d1c 100644 --- a/runtime/interpreter/mterp/mips64/op_goto.S +++ b/runtime/interpreter/mterp/mips64/op_goto.S @@ -1,3 +1,4 @@ +%def op_goto(): /* * Unconditional branch, 8-bit offset. * diff --git a/runtime/interpreter/mterp/mips64/op_goto_16.S b/runtime/interpreter/mterp/mips64/op_goto_16.S index ae56066352..3b0b52a0ce 100644 --- a/runtime/interpreter/mterp/mips64/op_goto_16.S +++ b/runtime/interpreter/mterp/mips64/op_goto_16.S @@ -1,3 +1,4 @@ +%def op_goto_16(): /* * Unconditional branch, 16-bit offset. * diff --git a/runtime/interpreter/mterp/mips64/op_goto_32.S b/runtime/interpreter/mterp/mips64/op_goto_32.S index 498b6d60ae..d48f0a04d5 100644 --- a/runtime/interpreter/mterp/mips64/op_goto_32.S +++ b/runtime/interpreter/mterp/mips64/op_goto_32.S @@ -1,3 +1,4 @@ +%def op_goto_32(): /* * Unconditional branch, 32-bit offset. * diff --git a/runtime/interpreter/mterp/mips64/op_if_eq.S b/runtime/interpreter/mterp/mips64/op_if_eq.S index aa35cadf17..da58674fd4 100644 --- a/runtime/interpreter/mterp/mips64/op_if_eq.S +++ b/runtime/interpreter/mterp/mips64/op_if_eq.S @@ -1 +1,2 @@ -%include "mips64/bincmp.S" { "condition":"eq" } +%def op_if_eq(): +% bincmp(condition="eq") diff --git a/runtime/interpreter/mterp/mips64/op_if_eqz.S b/runtime/interpreter/mterp/mips64/op_if_eqz.S index 0fe34187a0..0639664d47 100644 --- a/runtime/interpreter/mterp/mips64/op_if_eqz.S +++ b/runtime/interpreter/mterp/mips64/op_if_eqz.S @@ -1 +1,2 @@ -%include "mips64/zcmp.S" { "condition":"eq" } +%def op_if_eqz(): +% zcmp(condition="eq") diff --git a/runtime/interpreter/mterp/mips64/op_if_ge.S b/runtime/interpreter/mterp/mips64/op_if_ge.S index 59fdcc5b33..5b6ed2f994 100644 --- a/runtime/interpreter/mterp/mips64/op_if_ge.S +++ b/runtime/interpreter/mterp/mips64/op_if_ge.S @@ -1 +1,2 @@ -%include "mips64/bincmp.S" { "condition":"ge" } +%def op_if_ge(): +% bincmp(condition="ge") diff --git a/runtime/interpreter/mterp/mips64/op_if_gez.S b/runtime/interpreter/mterp/mips64/op_if_gez.S index 57f1f66ecd..ea6cda71fb 100644 --- a/runtime/interpreter/mterp/mips64/op_if_gez.S +++ b/runtime/interpreter/mterp/mips64/op_if_gez.S @@ -1 +1,2 @@ -%include "mips64/zcmp.S" { "condition":"ge" } +%def op_if_gez(): +% zcmp(condition="ge") diff --git a/runtime/interpreter/mterp/mips64/op_if_gt.S b/runtime/interpreter/mterp/mips64/op_if_gt.S index 26cc1195b5..201decff1a 100644 --- a/runtime/interpreter/mterp/mips64/op_if_gt.S +++ b/runtime/interpreter/mterp/mips64/op_if_gt.S @@ -1 +1,2 @@ -%include "mips64/bincmp.S" { "condition":"gt" } +%def op_if_gt(): +% bincmp(condition="gt") diff --git a/runtime/interpreter/mterp/mips64/op_if_gtz.S b/runtime/interpreter/mterp/mips64/op_if_gtz.S index 69fcacb82d..1fdbb6e8d2 100644 --- a/runtime/interpreter/mterp/mips64/op_if_gtz.S +++ b/runtime/interpreter/mterp/mips64/op_if_gtz.S @@ -1 +1,2 @@ -%include "mips64/zcmp.S" { "condition":"gt" } +%def op_if_gtz(): +% zcmp(condition="gt") diff --git a/runtime/interpreter/mterp/mips64/op_if_le.S b/runtime/interpreter/mterp/mips64/op_if_le.S index a7fce17c40..e6024f2b3e 100644 --- a/runtime/interpreter/mterp/mips64/op_if_le.S +++ b/runtime/interpreter/mterp/mips64/op_if_le.S @@ -1 +1,2 @@ -%include "mips64/bincmp.S" { "condition":"le" } +%def op_if_le(): +% bincmp(condition="le") diff --git a/runtime/interpreter/mterp/mips64/op_if_lez.S b/runtime/interpreter/mterp/mips64/op_if_lez.S index f3edcc6d99..62c0d2cd39 100644 --- a/runtime/interpreter/mterp/mips64/op_if_lez.S +++ b/runtime/interpreter/mterp/mips64/op_if_lez.S @@ -1 +1,2 @@ -%include "mips64/zcmp.S" { "condition":"le" } +%def op_if_lez(): +% zcmp(condition="le") diff --git a/runtime/interpreter/mterp/mips64/op_if_lt.S b/runtime/interpreter/mterp/mips64/op_if_lt.S index a975a31b57..4ef22fd798 100644 --- a/runtime/interpreter/mterp/mips64/op_if_lt.S +++ b/runtime/interpreter/mterp/mips64/op_if_lt.S @@ -1 +1,2 @@ -%include "mips64/bincmp.S" { "condition":"lt" } +%def op_if_lt(): +% bincmp(condition="lt") diff --git a/runtime/interpreter/mterp/mips64/op_if_ltz.S b/runtime/interpreter/mterp/mips64/op_if_ltz.S index c1d730d43f..84b2d0b53a 100644 --- a/runtime/interpreter/mterp/mips64/op_if_ltz.S +++ b/runtime/interpreter/mterp/mips64/op_if_ltz.S @@ -1 +1,2 @@ -%include "mips64/zcmp.S" { "condition":"lt" } +%def op_if_ltz(): +% zcmp(condition="lt") diff --git a/runtime/interpreter/mterp/mips64/op_if_ne.S b/runtime/interpreter/mterp/mips64/op_if_ne.S index f143ee917e..ec3a688b29 100644 --- a/runtime/interpreter/mterp/mips64/op_if_ne.S +++ b/runtime/interpreter/mterp/mips64/op_if_ne.S @@ -1 +1,2 @@ -%include "mips64/bincmp.S" { "condition":"ne" } +%def op_if_ne(): +% bincmp(condition="ne") diff --git a/runtime/interpreter/mterp/mips64/op_if_nez.S b/runtime/interpreter/mterp/mips64/op_if_nez.S index 1856b96dbc..7009c3acaa 100644 --- a/runtime/interpreter/mterp/mips64/op_if_nez.S +++ b/runtime/interpreter/mterp/mips64/op_if_nez.S @@ -1 +1,2 @@ -%include "mips64/zcmp.S" { "condition":"ne" } +%def op_if_nez(): +% zcmp(condition="ne") diff --git a/runtime/interpreter/mterp/mips64/op_iget.S b/runtime/interpreter/mterp/mips64/op_iget.S index e91f09923b..d09edc0a17 100644 --- a/runtime/interpreter/mterp/mips64/op_iget.S +++ b/runtime/interpreter/mterp/mips64/op_iget.S @@ -1,2 +1,2 @@ -%default { "is_object":"0", "helper":"MterpIGetU32"} -%include "mips64/field.S" { } +%def op_iget(is_object="0", helper="MterpIGetU32"): +% field(helper=helper) diff --git a/runtime/interpreter/mterp/mips64/op_iget_boolean.S b/runtime/interpreter/mterp/mips64/op_iget_boolean.S index dc2a42ad76..cb8edeec77 100644 --- a/runtime/interpreter/mterp/mips64/op_iget_boolean.S +++ b/runtime/interpreter/mterp/mips64/op_iget_boolean.S @@ -1 +1,2 @@ -%include "mips64/op_iget.S" { "helper":"MterpIGetU8" } +%def op_iget_boolean(): +% op_iget(helper="MterpIGetU8") diff --git a/runtime/interpreter/mterp/mips64/op_iget_boolean_quick.S b/runtime/interpreter/mterp/mips64/op_iget_boolean_quick.S index 979dc7079e..f3d2cb1e97 100644 --- a/runtime/interpreter/mterp/mips64/op_iget_boolean_quick.S +++ b/runtime/interpreter/mterp/mips64/op_iget_boolean_quick.S @@ -1 +1,2 @@ -%include "mips64/op_iget_quick.S" { "load":"lbu" } +%def op_iget_boolean_quick(): +% op_iget_quick(load="lbu") diff --git a/runtime/interpreter/mterp/mips64/op_iget_byte.S b/runtime/interpreter/mterp/mips64/op_iget_byte.S index c5bf6506e6..2b87fb16b5 100644 --- a/runtime/interpreter/mterp/mips64/op_iget_byte.S +++ b/runtime/interpreter/mterp/mips64/op_iget_byte.S @@ -1 +1,2 @@ -%include "mips64/op_iget.S" { "helper":"MterpIGetI8" } +%def op_iget_byte(): +% op_iget(helper="MterpIGetI8") diff --git a/runtime/interpreter/mterp/mips64/op_iget_byte_quick.S b/runtime/interpreter/mterp/mips64/op_iget_byte_quick.S index cb35556721..ddb469b3de 100644 --- a/runtime/interpreter/mterp/mips64/op_iget_byte_quick.S +++ b/runtime/interpreter/mterp/mips64/op_iget_byte_quick.S @@ -1 +1,2 @@ -%include "mips64/op_iget_quick.S" { "load":"lb" } +%def op_iget_byte_quick(): +% op_iget_quick(load="lb") diff --git a/runtime/interpreter/mterp/mips64/op_iget_char.S b/runtime/interpreter/mterp/mips64/op_iget_char.S index 3bf0c5aab9..001bd03e2b 100644 --- a/runtime/interpreter/mterp/mips64/op_iget_char.S +++ b/runtime/interpreter/mterp/mips64/op_iget_char.S @@ -1 +1,2 @@ -%include "mips64/op_iget.S" { "helper":"MterpIGetU16" } +%def op_iget_char(): +% op_iget(helper="MterpIGetU16") diff --git a/runtime/interpreter/mterp/mips64/op_iget_char_quick.S b/runtime/interpreter/mterp/mips64/op_iget_char_quick.S index 603456775b..ef0b350d4e 100644 --- a/runtime/interpreter/mterp/mips64/op_iget_char_quick.S +++ b/runtime/interpreter/mterp/mips64/op_iget_char_quick.S @@ -1 +1,2 @@ -%include "mips64/op_iget_quick.S" { "load":"lhu" } +%def op_iget_char_quick(): +% op_iget_quick(load="lhu") diff --git a/runtime/interpreter/mterp/mips64/op_iget_object.S b/runtime/interpreter/mterp/mips64/op_iget_object.S index 23fa187192..4e5f769547 100644 --- a/runtime/interpreter/mterp/mips64/op_iget_object.S +++ b/runtime/interpreter/mterp/mips64/op_iget_object.S @@ -1 +1,2 @@ -%include "mips64/op_iget.S" { "is_object":"1", "helper":"MterpIGetObj" } +%def op_iget_object(): +% op_iget(is_object="1", helper="MterpIGetObj") diff --git a/runtime/interpreter/mterp/mips64/op_iget_object_quick.S b/runtime/interpreter/mterp/mips64/op_iget_object_quick.S index 171d54301b..518b747e87 100644 --- a/runtime/interpreter/mterp/mips64/op_iget_object_quick.S +++ b/runtime/interpreter/mterp/mips64/op_iget_object_quick.S @@ -1,3 +1,4 @@ +%def op_iget_object_quick(): /* For: iget-object-quick */ /* op vA, vB, offset//CCCC */ .extern artIGetObjectFromMterp diff --git a/runtime/interpreter/mterp/mips64/op_iget_quick.S b/runtime/interpreter/mterp/mips64/op_iget_quick.S index fee6ab738c..eb597969aa 100644 --- a/runtime/interpreter/mterp/mips64/op_iget_quick.S +++ b/runtime/interpreter/mterp/mips64/op_iget_quick.S @@ -1,4 +1,4 @@ -%default { "load":"lw" } +%def op_iget_quick(load="lw"): /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ /* op vA, vB, offset//CCCC */ srl a2, rINST, 12 # a2 <- B diff --git a/runtime/interpreter/mterp/mips64/op_iget_short.S b/runtime/interpreter/mterp/mips64/op_iget_short.S index a9927fc982..a62c4d998f 100644 --- a/runtime/interpreter/mterp/mips64/op_iget_short.S +++ b/runtime/interpreter/mterp/mips64/op_iget_short.S @@ -1 +1,2 @@ -%include "mips64/op_iget.S" { "helper":"MterpIGetI16" } +%def op_iget_short(): +% op_iget(helper="MterpIGetI16") diff --git a/runtime/interpreter/mterp/mips64/op_iget_short_quick.S b/runtime/interpreter/mterp/mips64/op_iget_short_quick.S index 6e152dbf48..5957cb4600 100644 --- a/runtime/interpreter/mterp/mips64/op_iget_short_quick.S +++ b/runtime/interpreter/mterp/mips64/op_iget_short_quick.S @@ -1 +1,2 @@ -%include "mips64/op_iget_quick.S" { "load":"lh" } +%def op_iget_short_quick(): +% op_iget_quick(load="lh") diff --git a/runtime/interpreter/mterp/mips64/op_iget_wide.S b/runtime/interpreter/mterp/mips64/op_iget_wide.S index 40f364571f..9643cc3403 100644 --- a/runtime/interpreter/mterp/mips64/op_iget_wide.S +++ b/runtime/interpreter/mterp/mips64/op_iget_wide.S @@ -1 +1,2 @@ -%include "mips64/op_iget.S" { "helper":"MterpIGetU64" } +%def op_iget_wide(): +% op_iget(helper="MterpIGetU64") diff --git a/runtime/interpreter/mterp/mips64/op_iget_wide_quick.S b/runtime/interpreter/mterp/mips64/op_iget_wide_quick.S index 2adc6adf15..e914e0d446 100644 --- a/runtime/interpreter/mterp/mips64/op_iget_wide_quick.S +++ b/runtime/interpreter/mterp/mips64/op_iget_wide_quick.S @@ -1,3 +1,4 @@ +%def op_iget_wide_quick(): /* iget-wide-quick vA, vB, offset//CCCC */ srl a2, rINST, 12 # a2 <- B lhu a4, 2(rPC) # a4 <- field byte offset diff --git a/runtime/interpreter/mterp/mips64/op_instance_of.S b/runtime/interpreter/mterp/mips64/op_instance_of.S index 39a5dc7c26..1929944d32 100644 --- a/runtime/interpreter/mterp/mips64/op_instance_of.S +++ b/runtime/interpreter/mterp/mips64/op_instance_of.S @@ -1,3 +1,4 @@ +%def op_instance_of(): /* * Check to see if an object reference is an instance of a class. * diff --git a/runtime/interpreter/mterp/mips64/op_int_to_byte.S b/runtime/interpreter/mterp/mips64/op_int_to_byte.S index 1993e076a6..47440c6f3a 100644 --- a/runtime/interpreter/mterp/mips64/op_int_to_byte.S +++ b/runtime/interpreter/mterp/mips64/op_int_to_byte.S @@ -1 +1,2 @@ -%include "mips64/unop.S" {"instr":"seb a0, a0"} +%def op_int_to_byte(): +% unop(instr="seb a0, a0") diff --git a/runtime/interpreter/mterp/mips64/op_int_to_char.S b/runtime/interpreter/mterp/mips64/op_int_to_char.S index 8f03acd3f6..bea4e9e81b 100644 --- a/runtime/interpreter/mterp/mips64/op_int_to_char.S +++ b/runtime/interpreter/mterp/mips64/op_int_to_char.S @@ -1 +1,2 @@ -%include "mips64/unop.S" {"instr":"and a0, a0, 0xffff"} +%def op_int_to_char(): +% unop(instr="and a0, a0, 0xffff") diff --git a/runtime/interpreter/mterp/mips64/op_int_to_double.S b/runtime/interpreter/mterp/mips64/op_int_to_double.S index 6df71be394..6cc83ae282 100644 --- a/runtime/interpreter/mterp/mips64/op_int_to_double.S +++ b/runtime/interpreter/mterp/mips64/op_int_to_double.S @@ -1,8 +1,9 @@ +%def op_int_to_double(): /* * Conversion from or to floating-point happens in a floating-point register. * Therefore we load the input and store the output into or from a * floating-point register irrespective of the type. */ -%include "mips64/fcvtHeader.S" { "suffix":"_FLOAT", "valreg":"f0" } +% fcvtHeader(suffix="_FLOAT", valreg="f0") cvt.d.w f0, f0 -%include "mips64/fcvtFooter.S" { "suffix":"_DOUBLE", "valreg":"f0" } +% fcvtFooter(suffix="_DOUBLE", valreg="f0") diff --git a/runtime/interpreter/mterp/mips64/op_int_to_float.S b/runtime/interpreter/mterp/mips64/op_int_to_float.S index 77e9eba53a..837f8f9df3 100644 --- a/runtime/interpreter/mterp/mips64/op_int_to_float.S +++ b/runtime/interpreter/mterp/mips64/op_int_to_float.S @@ -1,8 +1,9 @@ +%def op_int_to_float(): /* * Conversion from or to floating-point happens in a floating-point register. * Therefore we load the input and store the output into or from a * floating-point register irrespective of the type. */ -%include "mips64/fcvtHeader.S" { "suffix":"_FLOAT", "valreg":"f0" } +% fcvtHeader(suffix="_FLOAT", valreg="f0") cvt.s.w f0, f0 -%include "mips64/fcvtFooter.S" { "suffix":"_FLOAT", "valreg":"f0" } +% fcvtFooter(suffix="_FLOAT", valreg="f0") diff --git a/runtime/interpreter/mterp/mips64/op_int_to_long.S b/runtime/interpreter/mterp/mips64/op_int_to_long.S index 7b9ad86fdc..c0cfd72f46 100644 --- a/runtime/interpreter/mterp/mips64/op_int_to_long.S +++ b/runtime/interpreter/mterp/mips64/op_int_to_long.S @@ -1,3 +1,4 @@ +%def op_int_to_long(): /* int-to-long vA, vB */ ext a3, rINST, 12, 4 # a3 <- B GET_VREG a0, a3 # a0 <- vB (sign-extended to 64 bits) diff --git a/runtime/interpreter/mterp/mips64/op_int_to_short.S b/runtime/interpreter/mterp/mips64/op_int_to_short.S index 4a3f2346cf..3d90de3e6a 100644 --- a/runtime/interpreter/mterp/mips64/op_int_to_short.S +++ b/runtime/interpreter/mterp/mips64/op_int_to_short.S @@ -1 +1,2 @@ -%include "mips64/unop.S" {"instr":"seh a0, a0"} +%def op_int_to_short(): +% unop(instr="seh a0, a0") diff --git a/runtime/interpreter/mterp/mips64/op_invoke_custom.S b/runtime/interpreter/mterp/mips64/op_invoke_custom.S index 964253d8b7..4bba9ee524 100644 --- a/runtime/interpreter/mterp/mips64/op_invoke_custom.S +++ b/runtime/interpreter/mterp/mips64/op_invoke_custom.S @@ -1 +1,2 @@ -%include "mips64/invoke.S" { "helper":"MterpInvokeCustom" } +%def op_invoke_custom(): +% invoke(helper="MterpInvokeCustom") diff --git a/runtime/interpreter/mterp/mips64/op_invoke_custom_range.S b/runtime/interpreter/mterp/mips64/op_invoke_custom_range.S index e6585e3646..57e61af1fa 100644 --- a/runtime/interpreter/mterp/mips64/op_invoke_custom_range.S +++ b/runtime/interpreter/mterp/mips64/op_invoke_custom_range.S @@ -1 +1,2 @@ -%include "mips64/invoke.S" { "helper":"MterpInvokeCustomRange" } +%def op_invoke_custom_range(): +% invoke(helper="MterpInvokeCustomRange") diff --git a/runtime/interpreter/mterp/mips64/op_invoke_direct.S b/runtime/interpreter/mterp/mips64/op_invoke_direct.S index 5047118e48..d3139cf39b 100644 --- a/runtime/interpreter/mterp/mips64/op_invoke_direct.S +++ b/runtime/interpreter/mterp/mips64/op_invoke_direct.S @@ -1 +1,2 @@ -%include "mips64/invoke.S" { "helper":"MterpInvokeDirect" } +%def op_invoke_direct(): +% invoke(helper="MterpInvokeDirect") diff --git a/runtime/interpreter/mterp/mips64/op_invoke_direct_range.S b/runtime/interpreter/mterp/mips64/op_invoke_direct_range.S index 5c9b95f5be..b4a161f48b 100644 --- a/runtime/interpreter/mterp/mips64/op_invoke_direct_range.S +++ b/runtime/interpreter/mterp/mips64/op_invoke_direct_range.S @@ -1 +1,2 @@ -%include "mips64/invoke.S" { "helper":"MterpInvokeDirectRange" } +%def op_invoke_direct_range(): +% invoke(helper="MterpInvokeDirectRange") diff --git a/runtime/interpreter/mterp/mips64/op_invoke_interface.S b/runtime/interpreter/mterp/mips64/op_invoke_interface.S index ed148adcbb..b064126253 100644 --- a/runtime/interpreter/mterp/mips64/op_invoke_interface.S +++ b/runtime/interpreter/mterp/mips64/op_invoke_interface.S @@ -1,4 +1,5 @@ -%include "mips64/invoke.S" { "helper":"MterpInvokeInterface" } +%def op_invoke_interface(): +% invoke(helper="MterpInvokeInterface") /* * Handle an interface method call. * diff --git a/runtime/interpreter/mterp/mips64/op_invoke_interface_range.S b/runtime/interpreter/mterp/mips64/op_invoke_interface_range.S index 91c231e0f4..2989115377 100644 --- a/runtime/interpreter/mterp/mips64/op_invoke_interface_range.S +++ b/runtime/interpreter/mterp/mips64/op_invoke_interface_range.S @@ -1 +1,2 @@ -%include "mips64/invoke.S" { "helper":"MterpInvokeInterfaceRange" } +%def op_invoke_interface_range(): +% invoke(helper="MterpInvokeInterfaceRange") diff --git a/runtime/interpreter/mterp/mips64/op_invoke_polymorphic.S b/runtime/interpreter/mterp/mips64/op_invoke_polymorphic.S index d9324d73bf..ce61f5aa0e 100644 --- a/runtime/interpreter/mterp/mips64/op_invoke_polymorphic.S +++ b/runtime/interpreter/mterp/mips64/op_invoke_polymorphic.S @@ -1 +1,2 @@ -%include "mips64/invoke_polymorphic.S" { "helper":"MterpInvokePolymorphic" } +%def op_invoke_polymorphic(): +% invoke_polymorphic(helper="MterpInvokePolymorphic") diff --git a/runtime/interpreter/mterp/mips64/op_invoke_polymorphic_range.S b/runtime/interpreter/mterp/mips64/op_invoke_polymorphic_range.S index 8e0ecb570a..16731bdb40 100644 --- a/runtime/interpreter/mterp/mips64/op_invoke_polymorphic_range.S +++ b/runtime/interpreter/mterp/mips64/op_invoke_polymorphic_range.S @@ -1 +1,2 @@ -%include "mips64/invoke_polymorphic.S" { "helper":"MterpInvokePolymorphicRange" } +%def op_invoke_polymorphic_range(): +% invoke_polymorphic(helper="MterpInvokePolymorphicRange") diff --git a/runtime/interpreter/mterp/mips64/op_invoke_static.S b/runtime/interpreter/mterp/mips64/op_invoke_static.S index 44f5cb7a78..8b104a66b0 100644 --- a/runtime/interpreter/mterp/mips64/op_invoke_static.S +++ b/runtime/interpreter/mterp/mips64/op_invoke_static.S @@ -1 +1,2 @@ -%include "mips64/invoke.S" { "helper":"MterpInvokeStatic" } +%def op_invoke_static(): +% invoke(helper="MterpInvokeStatic") diff --git a/runtime/interpreter/mterp/mips64/op_invoke_static_range.S b/runtime/interpreter/mterp/mips64/op_invoke_static_range.S index 289e5aa977..e0a546c92b 100644 --- a/runtime/interpreter/mterp/mips64/op_invoke_static_range.S +++ b/runtime/interpreter/mterp/mips64/op_invoke_static_range.S @@ -1 +1,2 @@ -%include "mips64/invoke.S" { "helper":"MterpInvokeStaticRange" } +%def op_invoke_static_range(): +% invoke(helper="MterpInvokeStaticRange") diff --git a/runtime/interpreter/mterp/mips64/op_invoke_super.S b/runtime/interpreter/mterp/mips64/op_invoke_super.S index b13fffe714..3c34c9942e 100644 --- a/runtime/interpreter/mterp/mips64/op_invoke_super.S +++ b/runtime/interpreter/mterp/mips64/op_invoke_super.S @@ -1,4 +1,5 @@ -%include "mips64/invoke.S" { "helper":"MterpInvokeSuper" } +%def op_invoke_super(): +% invoke(helper="MterpInvokeSuper") /* * Handle a "super" method call. * diff --git a/runtime/interpreter/mterp/mips64/op_invoke_super_range.S b/runtime/interpreter/mterp/mips64/op_invoke_super_range.S index 350b9757ba..caeafaa13c 100644 --- a/runtime/interpreter/mterp/mips64/op_invoke_super_range.S +++ b/runtime/interpreter/mterp/mips64/op_invoke_super_range.S @@ -1 +1,2 @@ -%include "mips64/invoke.S" { "helper":"MterpInvokeSuperRange" } +%def op_invoke_super_range(): +% invoke(helper="MterpInvokeSuperRange") diff --git a/runtime/interpreter/mterp/mips64/op_invoke_virtual.S b/runtime/interpreter/mterp/mips64/op_invoke_virtual.S index 0d26cda812..249177b813 100644 --- a/runtime/interpreter/mterp/mips64/op_invoke_virtual.S +++ b/runtime/interpreter/mterp/mips64/op_invoke_virtual.S @@ -1,4 +1,5 @@ -%include "mips64/invoke.S" { "helper":"MterpInvokeVirtual" } +%def op_invoke_virtual(): +% invoke(helper="MterpInvokeVirtual") /* * Handle a virtual method call. * diff --git a/runtime/interpreter/mterp/mips64/op_invoke_virtual_quick.S b/runtime/interpreter/mterp/mips64/op_invoke_virtual_quick.S index f39562c199..ea72c171ec 100644 --- a/runtime/interpreter/mterp/mips64/op_invoke_virtual_quick.S +++ b/runtime/interpreter/mterp/mips64/op_invoke_virtual_quick.S @@ -1 +1,2 @@ -%include "mips64/invoke.S" { "helper":"MterpInvokeVirtualQuick" } +%def op_invoke_virtual_quick(): +% invoke(helper="MterpInvokeVirtualQuick") diff --git a/runtime/interpreter/mterp/mips64/op_invoke_virtual_range.S b/runtime/interpreter/mterp/mips64/op_invoke_virtual_range.S index 0bb43f8fcc..baa0779593 100644 --- a/runtime/interpreter/mterp/mips64/op_invoke_virtual_range.S +++ b/runtime/interpreter/mterp/mips64/op_invoke_virtual_range.S @@ -1 +1,2 @@ -%include "mips64/invoke.S" { "helper":"MterpInvokeVirtualRange" } +%def op_invoke_virtual_range(): +% invoke(helper="MterpInvokeVirtualRange") diff --git a/runtime/interpreter/mterp/mips64/op_invoke_virtual_range_quick.S b/runtime/interpreter/mterp/mips64/op_invoke_virtual_range_quick.S index c4488513bd..1d961a0781 100644 --- a/runtime/interpreter/mterp/mips64/op_invoke_virtual_range_quick.S +++ b/runtime/interpreter/mterp/mips64/op_invoke_virtual_range_quick.S @@ -1 +1,2 @@ -%include "mips64/invoke.S" { "helper":"MterpInvokeVirtualQuickRange" } +%def op_invoke_virtual_range_quick(): +% invoke(helper="MterpInvokeVirtualQuickRange") diff --git a/runtime/interpreter/mterp/mips64/op_iput.S b/runtime/interpreter/mterp/mips64/op_iput.S index 81ab911b5e..e5351baf55 100644 --- a/runtime/interpreter/mterp/mips64/op_iput.S +++ b/runtime/interpreter/mterp/mips64/op_iput.S @@ -1,2 +1,2 @@ -%default { "is_object":"0", "helper":"MterpIPutU32" } -%include "mips64/field.S" { } +%def op_iput(is_object="0", helper="MterpIPutU32"): +% field(helper=helper) diff --git a/runtime/interpreter/mterp/mips64/op_iput_boolean.S b/runtime/interpreter/mterp/mips64/op_iput_boolean.S index 8e1d083759..9eb849877b 100644 --- a/runtime/interpreter/mterp/mips64/op_iput_boolean.S +++ b/runtime/interpreter/mterp/mips64/op_iput_boolean.S @@ -1 +1,2 @@ -%include "mips64/op_iput.S" { "helper":"MterpIPutU8" } +%def op_iput_boolean(): +% op_iput(helper="MterpIPutU8") diff --git a/runtime/interpreter/mterp/mips64/op_iput_boolean_quick.S b/runtime/interpreter/mterp/mips64/op_iput_boolean_quick.S index df99948e40..3d818a5a69 100644 --- a/runtime/interpreter/mterp/mips64/op_iput_boolean_quick.S +++ b/runtime/interpreter/mterp/mips64/op_iput_boolean_quick.S @@ -1 +1,2 @@ -%include "mips64/op_iput_quick.S" { "store":"sb" } +%def op_iput_boolean_quick(): +% op_iput_quick(store="sb") diff --git a/runtime/interpreter/mterp/mips64/op_iput_byte.S b/runtime/interpreter/mterp/mips64/op_iput_byte.S index ce3b614b0c..4b74f9fb0e 100644 --- a/runtime/interpreter/mterp/mips64/op_iput_byte.S +++ b/runtime/interpreter/mterp/mips64/op_iput_byte.S @@ -1 +1,2 @@ -%include "mips64/op_iput.S" { "helper":"MterpIPutI8" } +%def op_iput_byte(): +% op_iput(helper="MterpIPutI8") diff --git a/runtime/interpreter/mterp/mips64/op_iput_byte_quick.S b/runtime/interpreter/mterp/mips64/op_iput_byte_quick.S index df99948e40..06dc24e095 100644 --- a/runtime/interpreter/mterp/mips64/op_iput_byte_quick.S +++ b/runtime/interpreter/mterp/mips64/op_iput_byte_quick.S @@ -1 +1,2 @@ -%include "mips64/op_iput_quick.S" { "store":"sb" } +%def op_iput_byte_quick(): +% op_iput_quick(store="sb") diff --git a/runtime/interpreter/mterp/mips64/op_iput_char.S b/runtime/interpreter/mterp/mips64/op_iput_char.S index 1d587fad6b..64a249fc12 100644 --- a/runtime/interpreter/mterp/mips64/op_iput_char.S +++ b/runtime/interpreter/mterp/mips64/op_iput_char.S @@ -1 +1,2 @@ -%include "mips64/op_iput.S" { "helper":"MterpIPutU16" } +%def op_iput_char(): +% op_iput(helper="MterpIPutU16") diff --git a/runtime/interpreter/mterp/mips64/op_iput_char_quick.S b/runtime/interpreter/mterp/mips64/op_iput_char_quick.S index a6286b7b97..3b6af5b9fe 100644 --- a/runtime/interpreter/mterp/mips64/op_iput_char_quick.S +++ b/runtime/interpreter/mterp/mips64/op_iput_char_quick.S @@ -1 +1,2 @@ -%include "mips64/op_iput_quick.S" { "store":"sh" } +%def op_iput_char_quick(): +% op_iput_quick(store="sh") diff --git a/runtime/interpreter/mterp/mips64/op_iput_object.S b/runtime/interpreter/mterp/mips64/op_iput_object.S index d3316dd756..131edd5dbd 100644 --- a/runtime/interpreter/mterp/mips64/op_iput_object.S +++ b/runtime/interpreter/mterp/mips64/op_iput_object.S @@ -1 +1,2 @@ -%include "mips64/op_iput.S" { "is_object":"1", "helper":"MterpIPutObj" } +%def op_iput_object(): +% op_iput(is_object="1", helper="MterpIPutObj") diff --git a/runtime/interpreter/mterp/mips64/op_iput_object_quick.S b/runtime/interpreter/mterp/mips64/op_iput_object_quick.S index 658ef42a19..0a15857398 100644 --- a/runtime/interpreter/mterp/mips64/op_iput_object_quick.S +++ b/runtime/interpreter/mterp/mips64/op_iput_object_quick.S @@ -1,3 +1,4 @@ +%def op_iput_object_quick(): .extern MterpIputObjectQuick EXPORT_PC daddu a0, rFP, OFF_FP_SHADOWFRAME diff --git a/runtime/interpreter/mterp/mips64/op_iput_quick.S b/runtime/interpreter/mterp/mips64/op_iput_quick.S index b95adfcd4f..b38b75317f 100644 --- a/runtime/interpreter/mterp/mips64/op_iput_quick.S +++ b/runtime/interpreter/mterp/mips64/op_iput_quick.S @@ -1,4 +1,4 @@ -%default { "store":"sw" } +%def op_iput_quick(store="sw"): /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */ /* op vA, vB, offset//CCCC */ srl a2, rINST, 12 # a2 <- B diff --git a/runtime/interpreter/mterp/mips64/op_iput_short.S b/runtime/interpreter/mterp/mips64/op_iput_short.S index dd68bbeaaa..e631a3b259 100644 --- a/runtime/interpreter/mterp/mips64/op_iput_short.S +++ b/runtime/interpreter/mterp/mips64/op_iput_short.S @@ -1 +1,2 @@ -%include "mips64/op_iput.S" { "helper":"MterpIPutI16" } +%def op_iput_short(): +% op_iput(helper="MterpIPutI16") diff --git a/runtime/interpreter/mterp/mips64/op_iput_short_quick.S b/runtime/interpreter/mterp/mips64/op_iput_short_quick.S index a6286b7b97..fade093fc1 100644 --- a/runtime/interpreter/mterp/mips64/op_iput_short_quick.S +++ b/runtime/interpreter/mterp/mips64/op_iput_short_quick.S @@ -1 +1,2 @@ -%include "mips64/op_iput_quick.S" { "store":"sh" } +%def op_iput_short_quick(): +% op_iput_quick(store="sh") diff --git a/runtime/interpreter/mterp/mips64/op_iput_wide.S b/runtime/interpreter/mterp/mips64/op_iput_wide.S index 05194b33f3..2f34fd39f9 100644 --- a/runtime/interpreter/mterp/mips64/op_iput_wide.S +++ b/runtime/interpreter/mterp/mips64/op_iput_wide.S @@ -1 +1,2 @@ -%include "mips64/op_iput.S" { "helper":"MterpIPutU64" } +%def op_iput_wide(): +% op_iput(helper="MterpIPutU64") diff --git a/runtime/interpreter/mterp/mips64/op_iput_wide_quick.S b/runtime/interpreter/mterp/mips64/op_iput_wide_quick.S index 95a8ad8f9c..240f90200a 100644 --- a/runtime/interpreter/mterp/mips64/op_iput_wide_quick.S +++ b/runtime/interpreter/mterp/mips64/op_iput_wide_quick.S @@ -1,3 +1,4 @@ +%def op_iput_wide_quick(): /* iput-wide-quick vA, vB, offset//CCCC */ srl a2, rINST, 12 # a2 <- B lhu a3, 2(rPC) # a3 <- field byte offset diff --git a/runtime/interpreter/mterp/mips64/op_long_to_double.S b/runtime/interpreter/mterp/mips64/op_long_to_double.S index 8503e769b9..f4d346ca29 100644 --- a/runtime/interpreter/mterp/mips64/op_long_to_double.S +++ b/runtime/interpreter/mterp/mips64/op_long_to_double.S @@ -1,8 +1,9 @@ +%def op_long_to_double(): /* * Conversion from or to floating-point happens in a floating-point register. * Therefore we load the input and store the output into or from a * floating-point register irrespective of the type. */ -%include "mips64/fcvtHeader.S" { "suffix":"_DOUBLE", "valreg":"f0" } +% fcvtHeader(suffix="_DOUBLE", valreg="f0") cvt.d.l f0, f0 -%include "mips64/fcvtFooter.S" { "suffix":"_DOUBLE", "valreg":"f0" } +% fcvtFooter(suffix="_DOUBLE", valreg="f0") diff --git a/runtime/interpreter/mterp/mips64/op_long_to_float.S b/runtime/interpreter/mterp/mips64/op_long_to_float.S index 31f5c0e9b0..3c616d15e5 100644 --- a/runtime/interpreter/mterp/mips64/op_long_to_float.S +++ b/runtime/interpreter/mterp/mips64/op_long_to_float.S @@ -1,8 +1,9 @@ +%def op_long_to_float(): /* * Conversion from or to floating-point happens in a floating-point register. * Therefore we load the input and store the output into or from a * floating-point register irrespective of the type. */ -%include "mips64/fcvtHeader.S" { "suffix":"_DOUBLE", "valreg":"f0" } +% fcvtHeader(suffix="_DOUBLE", valreg="f0") cvt.s.l f0, f0 -%include "mips64/fcvtFooter.S" { "suffix":"_FLOAT", "valreg":"f0" } +% fcvtFooter(suffix="_FLOAT", valreg="f0") diff --git a/runtime/interpreter/mterp/mips64/op_long_to_int.S b/runtime/interpreter/mterp/mips64/op_long_to_int.S index 4ef4b512dc..eacb8f59ec 100644 --- a/runtime/interpreter/mterp/mips64/op_long_to_int.S +++ b/runtime/interpreter/mterp/mips64/op_long_to_int.S @@ -1,2 +1,3 @@ +%def op_long_to_int(): /* we ignore the high word, making this equivalent to a 32-bit reg move */ -%include "mips64/op_move.S" +% op_move() diff --git a/runtime/interpreter/mterp/mips64/op_monitor_enter.S b/runtime/interpreter/mterp/mips64/op_monitor_enter.S index 36ae50346e..47184f9a7b 100644 --- a/runtime/interpreter/mterp/mips64/op_monitor_enter.S +++ b/runtime/interpreter/mterp/mips64/op_monitor_enter.S @@ -1,3 +1,4 @@ +%def op_monitor_enter(): /* * Synchronize on an object. */ diff --git a/runtime/interpreter/mterp/mips64/op_monitor_exit.S b/runtime/interpreter/mterp/mips64/op_monitor_exit.S index 9945952017..58f8541aa2 100644 --- a/runtime/interpreter/mterp/mips64/op_monitor_exit.S +++ b/runtime/interpreter/mterp/mips64/op_monitor_exit.S @@ -1,3 +1,4 @@ +%def op_monitor_exit(): /* * Unlock an object. * diff --git a/runtime/interpreter/mterp/mips64/op_move.S b/runtime/interpreter/mterp/mips64/op_move.S index c79f6cde8d..c6de44ccf5 100644 --- a/runtime/interpreter/mterp/mips64/op_move.S +++ b/runtime/interpreter/mterp/mips64/op_move.S @@ -1,4 +1,4 @@ -%default { "is_object":"0" } +%def op_move(is_object="0"): /* for move, move-object, long-to-int */ /* op vA, vB */ ext a2, rINST, 8, 4 # a2 <- A diff --git a/runtime/interpreter/mterp/mips64/op_move_16.S b/runtime/interpreter/mterp/mips64/op_move_16.S index 9d5c4dce8c..68b7037939 100644 --- a/runtime/interpreter/mterp/mips64/op_move_16.S +++ b/runtime/interpreter/mterp/mips64/op_move_16.S @@ -1,4 +1,4 @@ -%default { "is_object":"0" } +%def op_move_16(is_object="0"): /* for: move/16, move-object/16 */ /* op vAAAA, vBBBB */ lhu a3, 4(rPC) # a3 <- BBBB diff --git a/runtime/interpreter/mterp/mips64/op_move_exception.S b/runtime/interpreter/mterp/mips64/op_move_exception.S index d226718c8f..8f441c7f7a 100644 --- a/runtime/interpreter/mterp/mips64/op_move_exception.S +++ b/runtime/interpreter/mterp/mips64/op_move_exception.S @@ -1,3 +1,4 @@ +%def op_move_exception(): /* move-exception vAA */ srl a2, rINST, 8 # a2 <- AA ld a0, THREAD_EXCEPTION_OFFSET(rSELF) # load exception obj diff --git a/runtime/interpreter/mterp/mips64/op_move_from16.S b/runtime/interpreter/mterp/mips64/op_move_from16.S index 6d6bde007f..f4c254c682 100644 --- a/runtime/interpreter/mterp/mips64/op_move_from16.S +++ b/runtime/interpreter/mterp/mips64/op_move_from16.S @@ -1,4 +1,4 @@ -%default { "is_object":"0" } +%def op_move_from16(is_object="0"): /* for: move/from16, move-object/from16 */ /* op vAA, vBBBB */ lhu a3, 2(rPC) # a3 <- BBBB diff --git a/runtime/interpreter/mterp/mips64/op_move_object.S b/runtime/interpreter/mterp/mips64/op_move_object.S index 47e0272a6c..dbb4d59710 100644 --- a/runtime/interpreter/mterp/mips64/op_move_object.S +++ b/runtime/interpreter/mterp/mips64/op_move_object.S @@ -1 +1,2 @@ -%include "mips64/op_move.S" {"is_object":"1"} +%def op_move_object(): +% op_move(is_object="1") diff --git a/runtime/interpreter/mterp/mips64/op_move_object_16.S b/runtime/interpreter/mterp/mips64/op_move_object_16.S index a777dcdaf8..40120379d5 100644 --- a/runtime/interpreter/mterp/mips64/op_move_object_16.S +++ b/runtime/interpreter/mterp/mips64/op_move_object_16.S @@ -1 +1,2 @@ -%include "mips64/op_move_16.S" {"is_object":"1"} +%def op_move_object_16(): +% op_move_16(is_object="1") diff --git a/runtime/interpreter/mterp/mips64/op_move_object_from16.S b/runtime/interpreter/mterp/mips64/op_move_object_from16.S index ab55ebd646..c82698e81e 100644 --- a/runtime/interpreter/mterp/mips64/op_move_object_from16.S +++ b/runtime/interpreter/mterp/mips64/op_move_object_from16.S @@ -1 +1,2 @@ -%include "mips64/op_move_from16.S" {"is_object":"1"} +%def op_move_object_from16(): +% op_move_from16(is_object="1") diff --git a/runtime/interpreter/mterp/mips64/op_move_result.S b/runtime/interpreter/mterp/mips64/op_move_result.S index 1ec28cb6d8..9d4bdfe0f0 100644 --- a/runtime/interpreter/mterp/mips64/op_move_result.S +++ b/runtime/interpreter/mterp/mips64/op_move_result.S @@ -1,4 +1,4 @@ -%default { "is_object":"0" } +%def op_move_result(is_object="0"): /* for: move-result, move-result-object */ /* op vAA */ srl a2, rINST, 8 # a2 <- AA diff --git a/runtime/interpreter/mterp/mips64/op_move_result_object.S b/runtime/interpreter/mterp/mips64/op_move_result_object.S index e76bc22c11..87aea2646a 100644 --- a/runtime/interpreter/mterp/mips64/op_move_result_object.S +++ b/runtime/interpreter/mterp/mips64/op_move_result_object.S @@ -1 +1,2 @@ -%include "mips64/op_move_result.S" {"is_object":"1"} +%def op_move_result_object(): +% op_move_result(is_object="1") diff --git a/runtime/interpreter/mterp/mips64/op_move_result_wide.S b/runtime/interpreter/mterp/mips64/op_move_result_wide.S index 3ba0d7288b..048ab3fa94 100644 --- a/runtime/interpreter/mterp/mips64/op_move_result_wide.S +++ b/runtime/interpreter/mterp/mips64/op_move_result_wide.S @@ -1,3 +1,4 @@ +%def op_move_result_wide(): /* for: move-result-wide */ /* op vAA */ srl a2, rINST, 8 # a2 <- AA diff --git a/runtime/interpreter/mterp/mips64/op_move_wide.S b/runtime/interpreter/mterp/mips64/op_move_wide.S index ea23f87ff0..94cfa47584 100644 --- a/runtime/interpreter/mterp/mips64/op_move_wide.S +++ b/runtime/interpreter/mterp/mips64/op_move_wide.S @@ -1,3 +1,4 @@ +%def op_move_wide(): /* move-wide vA, vB */ /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ ext a3, rINST, 12, 4 # a3 <- B diff --git a/runtime/interpreter/mterp/mips64/op_move_wide_16.S b/runtime/interpreter/mterp/mips64/op_move_wide_16.S index 8ec606834b..f3a923e33c 100644 --- a/runtime/interpreter/mterp/mips64/op_move_wide_16.S +++ b/runtime/interpreter/mterp/mips64/op_move_wide_16.S @@ -1,3 +1,4 @@ +%def op_move_wide_16(): /* move-wide/16 vAAAA, vBBBB */ /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ lhu a3, 4(rPC) # a3 <- BBBB diff --git a/runtime/interpreter/mterp/mips64/op_move_wide_from16.S b/runtime/interpreter/mterp/mips64/op_move_wide_from16.S index 11d5603fe1..822035e8fa 100644 --- a/runtime/interpreter/mterp/mips64/op_move_wide_from16.S +++ b/runtime/interpreter/mterp/mips64/op_move_wide_from16.S @@ -1,3 +1,4 @@ +%def op_move_wide_from16(): /* move-wide/from16 vAA, vBBBB */ /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ lhu a3, 2(rPC) # a3 <- BBBB diff --git a/runtime/interpreter/mterp/mips64/op_mul_double.S b/runtime/interpreter/mterp/mips64/op_mul_double.S index e7e17f7ece..84cf5af93e 100644 --- a/runtime/interpreter/mterp/mips64/op_mul_double.S +++ b/runtime/interpreter/mterp/mips64/op_mul_double.S @@ -1 +1,2 @@ -%include "mips64/fbinopWide.S" {"instr":"mul.d f0, f0, f1"} +%def op_mul_double(): +% fbinopWide(instr="mul.d f0, f0, f1") diff --git a/runtime/interpreter/mterp/mips64/op_mul_double_2addr.S b/runtime/interpreter/mterp/mips64/op_mul_double_2addr.S index f404d4688d..1ba6740c18 100644 --- a/runtime/interpreter/mterp/mips64/op_mul_double_2addr.S +++ b/runtime/interpreter/mterp/mips64/op_mul_double_2addr.S @@ -1 +1,2 @@ -%include "mips64/fbinopWide2addr.S" {"instr":"mul.d f0, f0, f1"} +%def op_mul_double_2addr(): +% fbinopWide2addr(instr="mul.d f0, f0, f1") diff --git a/runtime/interpreter/mterp/mips64/op_mul_float.S b/runtime/interpreter/mterp/mips64/op_mul_float.S index 9a695fca16..16594ede76 100644 --- a/runtime/interpreter/mterp/mips64/op_mul_float.S +++ b/runtime/interpreter/mterp/mips64/op_mul_float.S @@ -1 +1,2 @@ -%include "mips64/fbinop.S" {"instr":"mul.s f0, f0, f1"} +%def op_mul_float(): +% fbinop(instr="mul.s f0, f0, f1") diff --git a/runtime/interpreter/mterp/mips64/op_mul_float_2addr.S b/runtime/interpreter/mterp/mips64/op_mul_float_2addr.S index a134a34253..318ddab015 100644 --- a/runtime/interpreter/mterp/mips64/op_mul_float_2addr.S +++ b/runtime/interpreter/mterp/mips64/op_mul_float_2addr.S @@ -1 +1,2 @@ -%include "mips64/fbinop2addr.S" {"instr":"mul.s f0, f0, f1"} +%def op_mul_float_2addr(): +% fbinop2addr(instr="mul.s f0, f0, f1") diff --git a/runtime/interpreter/mterp/mips64/op_mul_int.S b/runtime/interpreter/mterp/mips64/op_mul_int.S index e1b90ff4e9..34e42f0783 100644 --- a/runtime/interpreter/mterp/mips64/op_mul_int.S +++ b/runtime/interpreter/mterp/mips64/op_mul_int.S @@ -1 +1,2 @@ -%include "mips64/binop.S" {"instr":"mul a0, a0, a1"} +%def op_mul_int(): +% binop(instr="mul a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_mul_int_2addr.S b/runtime/interpreter/mterp/mips64/op_mul_int_2addr.S index c0c4063d54..0224a6e2c1 100644 --- a/runtime/interpreter/mterp/mips64/op_mul_int_2addr.S +++ b/runtime/interpreter/mterp/mips64/op_mul_int_2addr.S @@ -1 +1,2 @@ -%include "mips64/binop2addr.S" {"instr":"mul a0, a0, a1"} +%def op_mul_int_2addr(): +% binop2addr(instr="mul a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_mul_int_lit16.S b/runtime/interpreter/mterp/mips64/op_mul_int_lit16.S index bb4fff8747..935d632e11 100644 --- a/runtime/interpreter/mterp/mips64/op_mul_int_lit16.S +++ b/runtime/interpreter/mterp/mips64/op_mul_int_lit16.S @@ -1 +1,2 @@ -%include "mips64/binopLit16.S" {"instr":"mul a0, a0, a1"} +%def op_mul_int_lit16(): +% binopLit16(instr="mul a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_mul_int_lit8.S b/runtime/interpreter/mterp/mips64/op_mul_int_lit8.S index da11ea9295..4a2bfca5c1 100644 --- a/runtime/interpreter/mterp/mips64/op_mul_int_lit8.S +++ b/runtime/interpreter/mterp/mips64/op_mul_int_lit8.S @@ -1 +1,2 @@ -%include "mips64/binopLit8.S" {"instr":"mul a0, a0, a1"} +%def op_mul_int_lit8(): +% binopLit8(instr="mul a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_mul_long.S b/runtime/interpreter/mterp/mips64/op_mul_long.S index ec32850606..296138d66e 100644 --- a/runtime/interpreter/mterp/mips64/op_mul_long.S +++ b/runtime/interpreter/mterp/mips64/op_mul_long.S @@ -1 +1,2 @@ -%include "mips64/binopWide.S" {"instr":"dmul a0, a0, a1"} +%def op_mul_long(): +% binopWide(instr="dmul a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_mul_long_2addr.S b/runtime/interpreter/mterp/mips64/op_mul_long_2addr.S index eb50cda03c..a99eaa49b8 100644 --- a/runtime/interpreter/mterp/mips64/op_mul_long_2addr.S +++ b/runtime/interpreter/mterp/mips64/op_mul_long_2addr.S @@ -1 +1,2 @@ -%include "mips64/binopWide2addr.S" {"instr":"dmul a0, a0, a1"} +%def op_mul_long_2addr(): +% binopWide2addr(instr="dmul a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_neg_double.S b/runtime/interpreter/mterp/mips64/op_neg_double.S index a135d61173..aa24c32791 100644 --- a/runtime/interpreter/mterp/mips64/op_neg_double.S +++ b/runtime/interpreter/mterp/mips64/op_neg_double.S @@ -1,3 +1,4 @@ -%include "mips64/fcvtHeader.S" { "suffix":"_DOUBLE", "valreg":"f0" } +%def op_neg_double(): +% fcvtHeader(suffix="_DOUBLE", valreg="f0") neg.d f0, f0 -%include "mips64/fcvtFooter.S" { "suffix":"_DOUBLE", "valreg":"f0" } +% fcvtFooter(suffix="_DOUBLE", valreg="f0") diff --git a/runtime/interpreter/mterp/mips64/op_neg_float.S b/runtime/interpreter/mterp/mips64/op_neg_float.S index 78019f03d8..1554a4db3d 100644 --- a/runtime/interpreter/mterp/mips64/op_neg_float.S +++ b/runtime/interpreter/mterp/mips64/op_neg_float.S @@ -1,3 +1,4 @@ -%include "mips64/fcvtHeader.S" { "suffix":"_FLOAT", "valreg":"f0" } +%def op_neg_float(): +% fcvtHeader(suffix="_FLOAT", valreg="f0") neg.s f0, f0 -%include "mips64/fcvtFooter.S" { "suffix":"_FLOAT", "valreg":"f0" } +% fcvtFooter(suffix="_FLOAT", valreg="f0") diff --git a/runtime/interpreter/mterp/mips64/op_neg_int.S b/runtime/interpreter/mterp/mips64/op_neg_int.S index 31538c0caa..9243a2154f 100644 --- a/runtime/interpreter/mterp/mips64/op_neg_int.S +++ b/runtime/interpreter/mterp/mips64/op_neg_int.S @@ -1 +1,2 @@ -%include "mips64/unop.S" {"instr":"subu a0, zero, a0"} +%def op_neg_int(): +% unop(instr="subu a0, zero, a0") diff --git a/runtime/interpreter/mterp/mips64/op_neg_long.S b/runtime/interpreter/mterp/mips64/op_neg_long.S index bc80d0623f..ad9d5599e5 100644 --- a/runtime/interpreter/mterp/mips64/op_neg_long.S +++ b/runtime/interpreter/mterp/mips64/op_neg_long.S @@ -1 +1,2 @@ -%include "mips64/unopWide.S" {"instr":"dsubu a0, zero, a0"} +%def op_neg_long(): +% unopWide(instr="dsubu a0, zero, a0") diff --git a/runtime/interpreter/mterp/mips64/op_new_array.S b/runtime/interpreter/mterp/mips64/op_new_array.S index d78b4ac32e..8da7d832fc 100644 --- a/runtime/interpreter/mterp/mips64/op_new_array.S +++ b/runtime/interpreter/mterp/mips64/op_new_array.S @@ -1,3 +1,4 @@ +%def op_new_array(): /* * Allocate an array of objects, specified with the array class * and a count. diff --git a/runtime/interpreter/mterp/mips64/op_new_instance.S b/runtime/interpreter/mterp/mips64/op_new_instance.S index cc5e13e00d..a14fd8f8e7 100644 --- a/runtime/interpreter/mterp/mips64/op_new_instance.S +++ b/runtime/interpreter/mterp/mips64/op_new_instance.S @@ -1,3 +1,4 @@ +%def op_new_instance(): /* * Create a new instance of a class. */ diff --git a/runtime/interpreter/mterp/mips64/op_nop.S b/runtime/interpreter/mterp/mips64/op_nop.S index cc803a791a..925fe4c979 100644 --- a/runtime/interpreter/mterp/mips64/op_nop.S +++ b/runtime/interpreter/mterp/mips64/op_nop.S @@ -1,3 +1,4 @@ +%def op_nop(): FETCH_ADVANCE_INST 1 # advance rPC, load rINST GET_INST_OPCODE v0 # extract opcode from rINST GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_not_int.S b/runtime/interpreter/mterp/mips64/op_not_int.S index 59540950cd..2fc1dd76fa 100644 --- a/runtime/interpreter/mterp/mips64/op_not_int.S +++ b/runtime/interpreter/mterp/mips64/op_not_int.S @@ -1 +1,2 @@ -%include "mips64/unop.S" {"instr":"nor a0, zero, a0"} +%def op_not_int(): +% unop(instr="nor a0, zero, a0") diff --git a/runtime/interpreter/mterp/mips64/op_not_long.S b/runtime/interpreter/mterp/mips64/op_not_long.S index c8f5da7e82..a551b3144c 100644 --- a/runtime/interpreter/mterp/mips64/op_not_long.S +++ b/runtime/interpreter/mterp/mips64/op_not_long.S @@ -1 +1,2 @@ -%include "mips64/unopWide.S" {"instr":"nor a0, zero, a0"} +%def op_not_long(): +% unopWide(instr="nor a0, zero, a0") diff --git a/runtime/interpreter/mterp/mips64/op_or_int.S b/runtime/interpreter/mterp/mips64/op_or_int.S index 0102355c55..df60be5896 100644 --- a/runtime/interpreter/mterp/mips64/op_or_int.S +++ b/runtime/interpreter/mterp/mips64/op_or_int.S @@ -1 +1,2 @@ -%include "mips64/binop.S" {"instr":"or a0, a0, a1"} +%def op_or_int(): +% binop(instr="or a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_or_int_2addr.S b/runtime/interpreter/mterp/mips64/op_or_int_2addr.S index eed89008c0..c202e6799b 100644 --- a/runtime/interpreter/mterp/mips64/op_or_int_2addr.S +++ b/runtime/interpreter/mterp/mips64/op_or_int_2addr.S @@ -1 +1,2 @@ -%include "mips64/binop2addr.S" {"instr":"or a0, a0, a1"} +%def op_or_int_2addr(): +% binop2addr(instr="or a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_or_int_lit16.S b/runtime/interpreter/mterp/mips64/op_or_int_lit16.S index 16a0f3e1a2..09961e8845 100644 --- a/runtime/interpreter/mterp/mips64/op_or_int_lit16.S +++ b/runtime/interpreter/mterp/mips64/op_or_int_lit16.S @@ -1 +1,2 @@ -%include "mips64/binopLit16.S" {"instr":"or a0, a0, a1"} +%def op_or_int_lit16(): +% binopLit16(instr="or a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_or_int_lit8.S b/runtime/interpreter/mterp/mips64/op_or_int_lit8.S index dbbf7904c6..1bd6809d90 100644 --- a/runtime/interpreter/mterp/mips64/op_or_int_lit8.S +++ b/runtime/interpreter/mterp/mips64/op_or_int_lit8.S @@ -1 +1,2 @@ -%include "mips64/binopLit8.S" {"instr":"or a0, a0, a1"} +%def op_or_int_lit8(): +% binopLit8(instr="or a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_or_long.S b/runtime/interpreter/mterp/mips64/op_or_long.S index e6f8639e52..65d4c44c5a 100644 --- a/runtime/interpreter/mterp/mips64/op_or_long.S +++ b/runtime/interpreter/mterp/mips64/op_or_long.S @@ -1 +1,2 @@ -%include "mips64/binopWide.S" {"instr":"or a0, a0, a1"} +%def op_or_long(): +% binopWide(instr="or a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_or_long_2addr.S b/runtime/interpreter/mterp/mips64/op_or_long_2addr.S index ad5e6c8e99..5ad0113d4a 100644 --- a/runtime/interpreter/mterp/mips64/op_or_long_2addr.S +++ b/runtime/interpreter/mterp/mips64/op_or_long_2addr.S @@ -1 +1,2 @@ -%include "mips64/binopWide2addr.S" {"instr":"or a0, a0, a1"} +%def op_or_long_2addr(): +% binopWide2addr(instr="or a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_packed_switch.S b/runtime/interpreter/mterp/mips64/op_packed_switch.S index 44e77a41d8..36c21077ab 100644 --- a/runtime/interpreter/mterp/mips64/op_packed_switch.S +++ b/runtime/interpreter/mterp/mips64/op_packed_switch.S @@ -1,4 +1,4 @@ -%default { "func":"MterpDoPackedSwitch" } +%def op_packed_switch(func="MterpDoPackedSwitch"): /* * Handle a packed-switch or sparse-switch instruction. In both cases * we decode it and hand it off to a helper function. diff --git a/runtime/interpreter/mterp/mips64/op_rem_double.S b/runtime/interpreter/mterp/mips64/op_rem_double.S index ba61cfdc71..16ad357a0a 100644 --- a/runtime/interpreter/mterp/mips64/op_rem_double.S +++ b/runtime/interpreter/mterp/mips64/op_rem_double.S @@ -1,3 +1,4 @@ +%def op_rem_double(): /* rem-double vAA, vBB, vCC */ .extern fmod lbu a2, 2(rPC) # a2 <- BB diff --git a/runtime/interpreter/mterp/mips64/op_rem_double_2addr.S b/runtime/interpreter/mterp/mips64/op_rem_double_2addr.S index c649f0d62c..230d70b37e 100644 --- a/runtime/interpreter/mterp/mips64/op_rem_double_2addr.S +++ b/runtime/interpreter/mterp/mips64/op_rem_double_2addr.S @@ -1,3 +1,4 @@ +%def op_rem_double_2addr(): /* rem-double/2addr vA, vB */ .extern fmod ext a2, rINST, 8, 4 # a2 <- A diff --git a/runtime/interpreter/mterp/mips64/op_rem_float.S b/runtime/interpreter/mterp/mips64/op_rem_float.S index 3967b0b02c..08c65164cd 100644 --- a/runtime/interpreter/mterp/mips64/op_rem_float.S +++ b/runtime/interpreter/mterp/mips64/op_rem_float.S @@ -1,3 +1,4 @@ +%def op_rem_float(): /* rem-float vAA, vBB, vCC */ .extern fmodf lbu a2, 2(rPC) # a2 <- BB diff --git a/runtime/interpreter/mterp/mips64/op_rem_float_2addr.S b/runtime/interpreter/mterp/mips64/op_rem_float_2addr.S index 3fed41e851..d35a0f4623 100644 --- a/runtime/interpreter/mterp/mips64/op_rem_float_2addr.S +++ b/runtime/interpreter/mterp/mips64/op_rem_float_2addr.S @@ -1,3 +1,4 @@ +%def op_rem_float_2addr(): /* rem-float/2addr vA, vB */ .extern fmodf ext a2, rINST, 8, 4 # a2 <- A diff --git a/runtime/interpreter/mterp/mips64/op_rem_int.S b/runtime/interpreter/mterp/mips64/op_rem_int.S index c05e9c49fc..542fe286ed 100644 --- a/runtime/interpreter/mterp/mips64/op_rem_int.S +++ b/runtime/interpreter/mterp/mips64/op_rem_int.S @@ -1 +1,2 @@ -%include "mips64/binop.S" {"instr":"mod a0, a0, a1", "chkzero":"1"} +%def op_rem_int(): +% binop(instr="mod a0, a0, a1", chkzero="1") diff --git a/runtime/interpreter/mterp/mips64/op_rem_int_2addr.S b/runtime/interpreter/mterp/mips64/op_rem_int_2addr.S index a4e162d3fa..da405767e7 100644 --- a/runtime/interpreter/mterp/mips64/op_rem_int_2addr.S +++ b/runtime/interpreter/mterp/mips64/op_rem_int_2addr.S @@ -1 +1,2 @@ -%include "mips64/binop2addr.S" {"instr":"mod a0, a0, a1", "chkzero":"1"} +%def op_rem_int_2addr(): +% binop2addr(instr="mod a0, a0, a1", chkzero="1") diff --git a/runtime/interpreter/mterp/mips64/op_rem_int_lit16.S b/runtime/interpreter/mterp/mips64/op_rem_int_lit16.S index 3284f1473c..2dc5173486 100644 --- a/runtime/interpreter/mterp/mips64/op_rem_int_lit16.S +++ b/runtime/interpreter/mterp/mips64/op_rem_int_lit16.S @@ -1 +1,2 @@ -%include "mips64/binopLit16.S" {"instr":"mod a0, a0, a1", "chkzero":"1"} +%def op_rem_int_lit16(): +% binopLit16(instr="mod a0, a0, a1", chkzero="1") diff --git a/runtime/interpreter/mterp/mips64/op_rem_int_lit8.S b/runtime/interpreter/mterp/mips64/op_rem_int_lit8.S index 1e6a584be5..4ea0ace7b5 100644 --- a/runtime/interpreter/mterp/mips64/op_rem_int_lit8.S +++ b/runtime/interpreter/mterp/mips64/op_rem_int_lit8.S @@ -1 +1,2 @@ -%include "mips64/binopLit8.S" {"instr":"mod a0, a0, a1", "chkzero":"1"} +%def op_rem_int_lit8(): +% binopLit8(instr="mod a0, a0, a1", chkzero="1") diff --git a/runtime/interpreter/mterp/mips64/op_rem_long.S b/runtime/interpreter/mterp/mips64/op_rem_long.S index 32b2d1916d..a10984ad0b 100644 --- a/runtime/interpreter/mterp/mips64/op_rem_long.S +++ b/runtime/interpreter/mterp/mips64/op_rem_long.S @@ -1 +1,2 @@ -%include "mips64/binopWide.S" {"instr":"dmod a0, a0, a1", "chkzero":"1"} +%def op_rem_long(): +% binopWide(instr="dmod a0, a0, a1", chkzero="1") diff --git a/runtime/interpreter/mterp/mips64/op_rem_long_2addr.S b/runtime/interpreter/mterp/mips64/op_rem_long_2addr.S index ad658e1fde..3cac4fba50 100644 --- a/runtime/interpreter/mterp/mips64/op_rem_long_2addr.S +++ b/runtime/interpreter/mterp/mips64/op_rem_long_2addr.S @@ -1 +1,2 @@ -%include "mips64/binopWide2addr.S" {"instr":"dmod a0, a0, a1", "chkzero":"1"} +%def op_rem_long_2addr(): +% binopWide2addr(instr="dmod a0, a0, a1", chkzero="1") diff --git a/runtime/interpreter/mterp/mips64/op_return.S b/runtime/interpreter/mterp/mips64/op_return.S index edd795f561..bfdf76a8e5 100644 --- a/runtime/interpreter/mterp/mips64/op_return.S +++ b/runtime/interpreter/mterp/mips64/op_return.S @@ -1,4 +1,4 @@ -%default {"instr":"GET_VREG"} +%def op_return(instr="GET_VREG"): /* * Return a 32-bit value. * diff --git a/runtime/interpreter/mterp/mips64/op_return_object.S b/runtime/interpreter/mterp/mips64/op_return_object.S index b69b8806d1..074c321ef7 100644 --- a/runtime/interpreter/mterp/mips64/op_return_object.S +++ b/runtime/interpreter/mterp/mips64/op_return_object.S @@ -1 +1,2 @@ -%include "mips64/op_return.S" {"instr":"GET_VREG_U"} +%def op_return_object(): +% op_return(instr="GET_VREG_U") diff --git a/runtime/interpreter/mterp/mips64/op_return_void.S b/runtime/interpreter/mterp/mips64/op_return_void.S index f6eee915a5..b5aa76cb69 100644 --- a/runtime/interpreter/mterp/mips64/op_return_void.S +++ b/runtime/interpreter/mterp/mips64/op_return_void.S @@ -1,3 +1,4 @@ +%def op_return_void(): .extern MterpThreadFenceForConstructor .extern MterpSuspendCheck jal MterpThreadFenceForConstructor diff --git a/runtime/interpreter/mterp/mips64/op_return_void_no_barrier.S b/runtime/interpreter/mterp/mips64/op_return_void_no_barrier.S index 4e9b640226..0baddbbaaf 100644 --- a/runtime/interpreter/mterp/mips64/op_return_void_no_barrier.S +++ b/runtime/interpreter/mterp/mips64/op_return_void_no_barrier.S @@ -1,3 +1,4 @@ +%def op_return_void_no_barrier(): .extern MterpSuspendCheck lw ra, THREAD_FLAGS_OFFSET(rSELF) move a0, rSELF diff --git a/runtime/interpreter/mterp/mips64/op_return_wide.S b/runtime/interpreter/mterp/mips64/op_return_wide.S index 91ca1fae59..dbcb704eb6 100644 --- a/runtime/interpreter/mterp/mips64/op_return_wide.S +++ b/runtime/interpreter/mterp/mips64/op_return_wide.S @@ -1,3 +1,4 @@ +%def op_return_wide(): /* * Return a 64-bit value. */ diff --git a/runtime/interpreter/mterp/mips64/op_rsub_int.S b/runtime/interpreter/mterp/mips64/op_rsub_int.S index fa31a0af5f..2d61e869e1 100644 --- a/runtime/interpreter/mterp/mips64/op_rsub_int.S +++ b/runtime/interpreter/mterp/mips64/op_rsub_int.S @@ -1 +1,2 @@ -%include "mips64/binopLit16.S" {"instr":"subu a0, a1, a0"} +%def op_rsub_int(): +% binopLit16(instr="subu a0, a1, a0") diff --git a/runtime/interpreter/mterp/mips64/op_rsub_int_lit8.S b/runtime/interpreter/mterp/mips64/op_rsub_int_lit8.S index c31ff32060..b9b214da94 100644 --- a/runtime/interpreter/mterp/mips64/op_rsub_int_lit8.S +++ b/runtime/interpreter/mterp/mips64/op_rsub_int_lit8.S @@ -1 +1,2 @@ -%include "mips64/binopLit8.S" {"instr":"subu a0, a1, a0"} +%def op_rsub_int_lit8(): +% binopLit8(instr="subu a0, a1, a0") diff --git a/runtime/interpreter/mterp/mips64/op_sget.S b/runtime/interpreter/mterp/mips64/op_sget.S index 200da35a12..8a6a66ab60 100644 --- a/runtime/interpreter/mterp/mips64/op_sget.S +++ b/runtime/interpreter/mterp/mips64/op_sget.S @@ -1,2 +1,2 @@ -%default { "is_object":"0", "helper":"MterpSGetU32" } -%include "mips64/field.S" { } +%def op_sget(is_object="0", helper="MterpSGetU32"): +% field(helper=helper) diff --git a/runtime/interpreter/mterp/mips64/op_sget_boolean.S b/runtime/interpreter/mterp/mips64/op_sget_boolean.S index 8abb396c57..d9c12c9b28 100644 --- a/runtime/interpreter/mterp/mips64/op_sget_boolean.S +++ b/runtime/interpreter/mterp/mips64/op_sget_boolean.S @@ -1 +1,2 @@ -%include "mips64/op_sget.S" {"helper":"MterpSGetU8"} +%def op_sget_boolean(): +% op_sget(helper="MterpSGetU8") diff --git a/runtime/interpreter/mterp/mips64/op_sget_byte.S b/runtime/interpreter/mterp/mips64/op_sget_byte.S index 68623f604c..37c6879cd4 100644 --- a/runtime/interpreter/mterp/mips64/op_sget_byte.S +++ b/runtime/interpreter/mterp/mips64/op_sget_byte.S @@ -1 +1,2 @@ -%include "mips64/op_sget.S" {"helper":"MterpSGetI8"} +%def op_sget_byte(): +% op_sget(helper="MterpSGetI8") diff --git a/runtime/interpreter/mterp/mips64/op_sget_char.S b/runtime/interpreter/mterp/mips64/op_sget_char.S index 3c7b962813..003bcd1683 100644 --- a/runtime/interpreter/mterp/mips64/op_sget_char.S +++ b/runtime/interpreter/mterp/mips64/op_sget_char.S @@ -1 +1,2 @@ -%include "mips64/op_sget.S" {"helper":"MterpSGetU16"} +%def op_sget_char(): +% op_sget(helper="MterpSGetU16") diff --git a/runtime/interpreter/mterp/mips64/op_sget_object.S b/runtime/interpreter/mterp/mips64/op_sget_object.S index 3b260e6ee2..7cf3597f44 100644 --- a/runtime/interpreter/mterp/mips64/op_sget_object.S +++ b/runtime/interpreter/mterp/mips64/op_sget_object.S @@ -1 +1,2 @@ -%include "mips64/op_sget.S" {"is_object":"1", "helper":"MterpSGetObj"} +%def op_sget_object(): +% op_sget(is_object="1", helper="MterpSGetObj") diff --git a/runtime/interpreter/mterp/mips64/op_sget_short.S b/runtime/interpreter/mterp/mips64/op_sget_short.S index 9a8579ba5b..afacb578d9 100644 --- a/runtime/interpreter/mterp/mips64/op_sget_short.S +++ b/runtime/interpreter/mterp/mips64/op_sget_short.S @@ -1 +1,2 @@ -%include "mips64/op_sget.S" {"helper":"MterpSGetI16"} +%def op_sget_short(): +% op_sget(helper="MterpSGetI16") diff --git a/runtime/interpreter/mterp/mips64/op_sget_wide.S b/runtime/interpreter/mterp/mips64/op_sget_wide.S index 14f232c073..fff2be6945 100644 --- a/runtime/interpreter/mterp/mips64/op_sget_wide.S +++ b/runtime/interpreter/mterp/mips64/op_sget_wide.S @@ -1 +1,2 @@ -%include "mips64/op_sget.S" {"helper":"MterpSGetU64"} +%def op_sget_wide(): +% op_sget(helper="MterpSGetU64") diff --git a/runtime/interpreter/mterp/mips64/op_shl_int.S b/runtime/interpreter/mterp/mips64/op_shl_int.S index 784481f335..efd213c09a 100644 --- a/runtime/interpreter/mterp/mips64/op_shl_int.S +++ b/runtime/interpreter/mterp/mips64/op_shl_int.S @@ -1 +1,2 @@ -%include "mips64/binop.S" {"instr":"sll a0, a0, a1"} +%def op_shl_int(): +% binop(instr="sll a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_shl_int_2addr.S b/runtime/interpreter/mterp/mips64/op_shl_int_2addr.S index a6c8a78ff6..0901e6b65a 100644 --- a/runtime/interpreter/mterp/mips64/op_shl_int_2addr.S +++ b/runtime/interpreter/mterp/mips64/op_shl_int_2addr.S @@ -1 +1,2 @@ -%include "mips64/binop2addr.S" {"instr":"sll a0, a0, a1"} +%def op_shl_int_2addr(): +% binop2addr(instr="sll a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_shl_int_lit8.S b/runtime/interpreter/mterp/mips64/op_shl_int_lit8.S index 36ef207edf..2263ec70c2 100644 --- a/runtime/interpreter/mterp/mips64/op_shl_int_lit8.S +++ b/runtime/interpreter/mterp/mips64/op_shl_int_lit8.S @@ -1 +1,2 @@ -%include "mips64/binopLit8.S" {"instr":"sll a0, a0, a1"} +%def op_shl_int_lit8(): +% binopLit8(instr="sll a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_shl_long.S b/runtime/interpreter/mterp/mips64/op_shl_long.S index 225a2cbc2a..9ef03d8cfa 100644 --- a/runtime/interpreter/mterp/mips64/op_shl_long.S +++ b/runtime/interpreter/mterp/mips64/op_shl_long.S @@ -1 +1,2 @@ -%include "mips64/binopWide.S" {"instr":"dsll a0, a0, a1"} +%def op_shl_long(): +% binopWide(instr="dsll a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_shl_long_2addr.S b/runtime/interpreter/mterp/mips64/op_shl_long_2addr.S index c04d8823f4..f748c3b045 100644 --- a/runtime/interpreter/mterp/mips64/op_shl_long_2addr.S +++ b/runtime/interpreter/mterp/mips64/op_shl_long_2addr.S @@ -1 +1,2 @@ -%include "mips64/binopWide2addr.S" {"instr":"dsll a0, a0, a1"} +%def op_shl_long_2addr(): +% binopWide2addr(instr="dsll a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_shr_int.S b/runtime/interpreter/mterp/mips64/op_shr_int.S index eded0373b1..8d55e7afa9 100644 --- a/runtime/interpreter/mterp/mips64/op_shr_int.S +++ b/runtime/interpreter/mterp/mips64/op_shr_int.S @@ -1 +1,2 @@ -%include "mips64/binop.S" {"instr":"sra a0, a0, a1"} +%def op_shr_int(): +% binop(instr="sra a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_shr_int_2addr.S b/runtime/interpreter/mterp/mips64/op_shr_int_2addr.S index 5b4d96f187..e102baa99f 100644 --- a/runtime/interpreter/mterp/mips64/op_shr_int_2addr.S +++ b/runtime/interpreter/mterp/mips64/op_shr_int_2addr.S @@ -1 +1,2 @@ -%include "mips64/binop2addr.S" {"instr":"sra a0, a0, a1"} +%def op_shr_int_2addr(): +% binop2addr(instr="sra a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_shr_int_lit8.S b/runtime/interpreter/mterp/mips64/op_shr_int_lit8.S index 175eb8633a..437c5c49a6 100644 --- a/runtime/interpreter/mterp/mips64/op_shr_int_lit8.S +++ b/runtime/interpreter/mterp/mips64/op_shr_int_lit8.S @@ -1 +1,2 @@ -%include "mips64/binopLit8.S" {"instr":"sra a0, a0, a1"} +%def op_shr_int_lit8(): +% binopLit8(instr="sra a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_shr_long.S b/runtime/interpreter/mterp/mips64/op_shr_long.S index 0db38c8510..1be48f299a 100644 --- a/runtime/interpreter/mterp/mips64/op_shr_long.S +++ b/runtime/interpreter/mterp/mips64/op_shr_long.S @@ -1 +1,2 @@ -%include "mips64/binopWide.S" {"instr":"dsra a0, a0, a1"} +%def op_shr_long(): +% binopWide(instr="dsra a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_shr_long_2addr.S b/runtime/interpreter/mterp/mips64/op_shr_long_2addr.S index 48131ad7e4..a15861fefd 100644 --- a/runtime/interpreter/mterp/mips64/op_shr_long_2addr.S +++ b/runtime/interpreter/mterp/mips64/op_shr_long_2addr.S @@ -1 +1,2 @@ -%include "mips64/binopWide2addr.S" {"instr":"dsra a0, a0, a1"} +%def op_shr_long_2addr(): +% binopWide2addr(instr="dsra a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_sparse_switch.S b/runtime/interpreter/mterp/mips64/op_sparse_switch.S index b065aaa95b..b74d7da816 100644 --- a/runtime/interpreter/mterp/mips64/op_sparse_switch.S +++ b/runtime/interpreter/mterp/mips64/op_sparse_switch.S @@ -1 +1,2 @@ -%include "mips64/op_packed_switch.S" { "func":"MterpDoSparseSwitch" } +%def op_sparse_switch(): +% op_packed_switch(func="MterpDoSparseSwitch") diff --git a/runtime/interpreter/mterp/mips64/op_sput.S b/runtime/interpreter/mterp/mips64/op_sput.S index 0bd683767f..cbd6ee96d3 100644 --- a/runtime/interpreter/mterp/mips64/op_sput.S +++ b/runtime/interpreter/mterp/mips64/op_sput.S @@ -1,2 +1,2 @@ -%default { "is_object":"0", "helper":"MterpSPutU32"} -%include "mips64/field.S" { } +%def op_sput(is_object="0", helper="MterpSPutU32"): +% field(helper=helper) diff --git a/runtime/interpreter/mterp/mips64/op_sput_boolean.S b/runtime/interpreter/mterp/mips64/op_sput_boolean.S index 2e769d5e1a..36fba8448b 100644 --- a/runtime/interpreter/mterp/mips64/op_sput_boolean.S +++ b/runtime/interpreter/mterp/mips64/op_sput_boolean.S @@ -1 +1,2 @@ -%include "mips64/op_sput.S" {"helper":"MterpSPutU8"} +%def op_sput_boolean(): +% op_sput(helper="MterpSPutU8") diff --git a/runtime/interpreter/mterp/mips64/op_sput_byte.S b/runtime/interpreter/mterp/mips64/op_sput_byte.S index 0b04b590ee..84ad4a0ff8 100644 --- a/runtime/interpreter/mterp/mips64/op_sput_byte.S +++ b/runtime/interpreter/mterp/mips64/op_sput_byte.S @@ -1 +1,2 @@ -%include "mips64/op_sput.S" {"helper":"MterpSPutI8"} +%def op_sput_byte(): +% op_sput(helper="MterpSPutI8") diff --git a/runtime/interpreter/mterp/mips64/op_sput_char.S b/runtime/interpreter/mterp/mips64/op_sput_char.S index 4a80375d65..9b8eeba578 100644 --- a/runtime/interpreter/mterp/mips64/op_sput_char.S +++ b/runtime/interpreter/mterp/mips64/op_sput_char.S @@ -1 +1,2 @@ -%include "mips64/op_sput.S" {"helper":"MterpSPutU16"} +%def op_sput_char(): +% op_sput(helper="MterpSPutU16") diff --git a/runtime/interpreter/mterp/mips64/op_sput_object.S b/runtime/interpreter/mterp/mips64/op_sput_object.S index 09bd0fb7ba..081360c40f 100644 --- a/runtime/interpreter/mterp/mips64/op_sput_object.S +++ b/runtime/interpreter/mterp/mips64/op_sput_object.S @@ -1 +1,2 @@ -%include "mips64/op_sput.S" {"is_object":"1", "helper":"MterpSPutObj"} +%def op_sput_object(): +% op_sput(is_object="1", helper="MterpSPutObj") diff --git a/runtime/interpreter/mterp/mips64/op_sput_short.S b/runtime/interpreter/mterp/mips64/op_sput_short.S index c00043b6b7..ee16513486 100644 --- a/runtime/interpreter/mterp/mips64/op_sput_short.S +++ b/runtime/interpreter/mterp/mips64/op_sput_short.S @@ -1 +1,2 @@ -%include "mips64/op_sput.S" {"helper":"MterpSPutI16"} +%def op_sput_short(): +% op_sput(helper="MterpSPutI16") diff --git a/runtime/interpreter/mterp/mips64/op_sput_wide.S b/runtime/interpreter/mterp/mips64/op_sput_wide.S index 070d17ff4d..44c1a188ed 100644 --- a/runtime/interpreter/mterp/mips64/op_sput_wide.S +++ b/runtime/interpreter/mterp/mips64/op_sput_wide.S @@ -1 +1,2 @@ -%include "mips64/op_sput.S" {"helper":"MterpSPutU64"} +%def op_sput_wide(): +% op_sput(helper="MterpSPutU64") diff --git a/runtime/interpreter/mterp/mips64/op_sub_double.S b/runtime/interpreter/mterp/mips64/op_sub_double.S index 40a6c89a10..aeb1b0f038 100644 --- a/runtime/interpreter/mterp/mips64/op_sub_double.S +++ b/runtime/interpreter/mterp/mips64/op_sub_double.S @@ -1 +1,2 @@ -%include "mips64/fbinopWide.S" {"instr":"sub.d f0, f0, f1"} +%def op_sub_double(): +% fbinopWide(instr="sub.d f0, f0, f1") diff --git a/runtime/interpreter/mterp/mips64/op_sub_double_2addr.S b/runtime/interpreter/mterp/mips64/op_sub_double_2addr.S index 984737e553..03457ac325 100644 --- a/runtime/interpreter/mterp/mips64/op_sub_double_2addr.S +++ b/runtime/interpreter/mterp/mips64/op_sub_double_2addr.S @@ -1 +1,2 @@ -%include "mips64/fbinopWide2addr.S" {"instr":"sub.d f0, f0, f1"} +%def op_sub_double_2addr(): +% fbinopWide2addr(instr="sub.d f0, f0, f1") diff --git a/runtime/interpreter/mterp/mips64/op_sub_float.S b/runtime/interpreter/mterp/mips64/op_sub_float.S index 9010592116..4afd1adf3e 100644 --- a/runtime/interpreter/mterp/mips64/op_sub_float.S +++ b/runtime/interpreter/mterp/mips64/op_sub_float.S @@ -1 +1,2 @@ -%include "mips64/fbinop.S" {"instr":"sub.s f0, f0, f1"} +%def op_sub_float(): +% fbinop(instr="sub.s f0, f0, f1") diff --git a/runtime/interpreter/mterp/mips64/op_sub_float_2addr.S b/runtime/interpreter/mterp/mips64/op_sub_float_2addr.S index e7d4ffe1ae..b4ade2c163 100644 --- a/runtime/interpreter/mterp/mips64/op_sub_float_2addr.S +++ b/runtime/interpreter/mterp/mips64/op_sub_float_2addr.S @@ -1 +1,2 @@ -%include "mips64/fbinop2addr.S" {"instr":"sub.s f0, f0, f1"} +%def op_sub_float_2addr(): +% fbinop2addr(instr="sub.s f0, f0, f1") diff --git a/runtime/interpreter/mterp/mips64/op_sub_int.S b/runtime/interpreter/mterp/mips64/op_sub_int.S index 609ea0575d..57f618d65a 100644 --- a/runtime/interpreter/mterp/mips64/op_sub_int.S +++ b/runtime/interpreter/mterp/mips64/op_sub_int.S @@ -1 +1,2 @@ -%include "mips64/binop.S" {"instr":"subu a0, a0, a1"} +%def op_sub_int(): +% binop(instr="subu a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_sub_int_2addr.S b/runtime/interpreter/mterp/mips64/op_sub_int_2addr.S index ba2f1e875b..445ffca50f 100644 --- a/runtime/interpreter/mterp/mips64/op_sub_int_2addr.S +++ b/runtime/interpreter/mterp/mips64/op_sub_int_2addr.S @@ -1 +1,2 @@ -%include "mips64/binop2addr.S" {"instr":"subu a0, a0, a1"} +%def op_sub_int_2addr(): +% binop2addr(instr="subu a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_sub_long.S b/runtime/interpreter/mterp/mips64/op_sub_long.S index 09a6afd26e..ba5fe49604 100644 --- a/runtime/interpreter/mterp/mips64/op_sub_long.S +++ b/runtime/interpreter/mterp/mips64/op_sub_long.S @@ -1 +1,2 @@ -%include "mips64/binopWide.S" {"instr":"dsubu a0, a0, a1"} +%def op_sub_long(): +% binopWide(instr="dsubu a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_sub_long_2addr.S b/runtime/interpreter/mterp/mips64/op_sub_long_2addr.S index b9ec82a19b..e22b4f6cba 100644 --- a/runtime/interpreter/mterp/mips64/op_sub_long_2addr.S +++ b/runtime/interpreter/mterp/mips64/op_sub_long_2addr.S @@ -1 +1,2 @@ -%include "mips64/binopWide2addr.S" {"instr":"dsubu a0, a0, a1"} +%def op_sub_long_2addr(): +% binopWide2addr(instr="dsubu a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_throw.S b/runtime/interpreter/mterp/mips64/op_throw.S index 6418d57ecc..7f26d88b2f 100644 --- a/runtime/interpreter/mterp/mips64/op_throw.S +++ b/runtime/interpreter/mterp/mips64/op_throw.S @@ -1,3 +1,4 @@ +%def op_throw(): /* * Throw an exception object in the current thread. */ diff --git a/runtime/interpreter/mterp/mips64/op_unused_3e.S b/runtime/interpreter/mterp/mips64/op_unused_3e.S index 29463d73fc..d889f1a5fb 100644 --- a/runtime/interpreter/mterp/mips64/op_unused_3e.S +++ b/runtime/interpreter/mterp/mips64/op_unused_3e.S @@ -1 +1,2 @@ -%include "mips64/unused.S" +%def op_unused_3e(): +% unused() diff --git a/runtime/interpreter/mterp/mips64/op_unused_3f.S b/runtime/interpreter/mterp/mips64/op_unused_3f.S index 29463d73fc..b3ebcfaeaa 100644 --- a/runtime/interpreter/mterp/mips64/op_unused_3f.S +++ b/runtime/interpreter/mterp/mips64/op_unused_3f.S @@ -1 +1,2 @@ -%include "mips64/unused.S" +%def op_unused_3f(): +% unused() diff --git a/runtime/interpreter/mterp/mips64/op_unused_40.S b/runtime/interpreter/mterp/mips64/op_unused_40.S index 29463d73fc..7920fb350f 100644 --- a/runtime/interpreter/mterp/mips64/op_unused_40.S +++ b/runtime/interpreter/mterp/mips64/op_unused_40.S @@ -1 +1,2 @@ -%include "mips64/unused.S" +%def op_unused_40(): +% unused() diff --git a/runtime/interpreter/mterp/mips64/op_unused_41.S b/runtime/interpreter/mterp/mips64/op_unused_41.S index 29463d73fc..5ed03b8506 100644 --- a/runtime/interpreter/mterp/mips64/op_unused_41.S +++ b/runtime/interpreter/mterp/mips64/op_unused_41.S @@ -1 +1,2 @@ -%include "mips64/unused.S" +%def op_unused_41(): +% unused() diff --git a/runtime/interpreter/mterp/mips64/op_unused_42.S b/runtime/interpreter/mterp/mips64/op_unused_42.S index 29463d73fc..ac32521add 100644 --- a/runtime/interpreter/mterp/mips64/op_unused_42.S +++ b/runtime/interpreter/mterp/mips64/op_unused_42.S @@ -1 +1,2 @@ -%include "mips64/unused.S" +%def op_unused_42(): +% unused() diff --git a/runtime/interpreter/mterp/mips64/op_unused_43.S b/runtime/interpreter/mterp/mips64/op_unused_43.S index 29463d73fc..33e2aa10f8 100644 --- a/runtime/interpreter/mterp/mips64/op_unused_43.S +++ b/runtime/interpreter/mterp/mips64/op_unused_43.S @@ -1 +1,2 @@ -%include "mips64/unused.S" +%def op_unused_43(): +% unused() diff --git a/runtime/interpreter/mterp/mips64/op_unused_79.S b/runtime/interpreter/mterp/mips64/op_unused_79.S index 29463d73fc..3c6dafc789 100644 --- a/runtime/interpreter/mterp/mips64/op_unused_79.S +++ b/runtime/interpreter/mterp/mips64/op_unused_79.S @@ -1 +1,2 @@ -%include "mips64/unused.S" +%def op_unused_79(): +% unused() diff --git a/runtime/interpreter/mterp/mips64/op_unused_7a.S b/runtime/interpreter/mterp/mips64/op_unused_7a.S index 29463d73fc..9c03cd5535 100644 --- a/runtime/interpreter/mterp/mips64/op_unused_7a.S +++ b/runtime/interpreter/mterp/mips64/op_unused_7a.S @@ -1 +1,2 @@ -%include "mips64/unused.S" +%def op_unused_7a(): +% unused() diff --git a/runtime/interpreter/mterp/mips64/op_unused_f3.S b/runtime/interpreter/mterp/mips64/op_unused_f3.S index 29463d73fc..ab10b78be2 100644 --- a/runtime/interpreter/mterp/mips64/op_unused_f3.S +++ b/runtime/interpreter/mterp/mips64/op_unused_f3.S @@ -1 +1,2 @@ -%include "mips64/unused.S" +%def op_unused_f3(): +% unused() diff --git a/runtime/interpreter/mterp/mips64/op_unused_f4.S b/runtime/interpreter/mterp/mips64/op_unused_f4.S index 29463d73fc..09229d6d99 100644 --- a/runtime/interpreter/mterp/mips64/op_unused_f4.S +++ b/runtime/interpreter/mterp/mips64/op_unused_f4.S @@ -1 +1,2 @@ -%include "mips64/unused.S" +%def op_unused_f4(): +% unused() diff --git a/runtime/interpreter/mterp/mips64/op_unused_f5.S b/runtime/interpreter/mterp/mips64/op_unused_f5.S index 29463d73fc..0d6149b5fd 100644 --- a/runtime/interpreter/mterp/mips64/op_unused_f5.S +++ b/runtime/interpreter/mterp/mips64/op_unused_f5.S @@ -1 +1,2 @@ -%include "mips64/unused.S" +%def op_unused_f5(): +% unused() diff --git a/runtime/interpreter/mterp/mips64/op_unused_f6.S b/runtime/interpreter/mterp/mips64/op_unused_f6.S index 29463d73fc..117b03de6d 100644 --- a/runtime/interpreter/mterp/mips64/op_unused_f6.S +++ b/runtime/interpreter/mterp/mips64/op_unused_f6.S @@ -1 +1,2 @@ -%include "mips64/unused.S" +%def op_unused_f6(): +% unused() diff --git a/runtime/interpreter/mterp/mips64/op_unused_f7.S b/runtime/interpreter/mterp/mips64/op_unused_f7.S index 29463d73fc..4e3a0f3c9a 100644 --- a/runtime/interpreter/mterp/mips64/op_unused_f7.S +++ b/runtime/interpreter/mterp/mips64/op_unused_f7.S @@ -1 +1,2 @@ -%include "mips64/unused.S" +%def op_unused_f7(): +% unused() diff --git a/runtime/interpreter/mterp/mips64/op_unused_f8.S b/runtime/interpreter/mterp/mips64/op_unused_f8.S index 29463d73fc..d1220752d7 100644 --- a/runtime/interpreter/mterp/mips64/op_unused_f8.S +++ b/runtime/interpreter/mterp/mips64/op_unused_f8.S @@ -1 +1,2 @@ -%include "mips64/unused.S" +%def op_unused_f8(): +% unused() diff --git a/runtime/interpreter/mterp/mips64/op_unused_f9.S b/runtime/interpreter/mterp/mips64/op_unused_f9.S index 29463d73fc..7d09a0ebcf 100644 --- a/runtime/interpreter/mterp/mips64/op_unused_f9.S +++ b/runtime/interpreter/mterp/mips64/op_unused_f9.S @@ -1 +1,2 @@ -%include "mips64/unused.S" +%def op_unused_f9(): +% unused() diff --git a/runtime/interpreter/mterp/mips64/op_unused_fc.S b/runtime/interpreter/mterp/mips64/op_unused_fc.S index 29463d73fc..06978191eb 100644 --- a/runtime/interpreter/mterp/mips64/op_unused_fc.S +++ b/runtime/interpreter/mterp/mips64/op_unused_fc.S @@ -1 +1,2 @@ -%include "mips64/unused.S" +%def op_unused_fc(): +% unused() diff --git a/runtime/interpreter/mterp/mips64/op_unused_fd.S b/runtime/interpreter/mterp/mips64/op_unused_fd.S index 29463d73fc..4bc2b4bdb6 100644 --- a/runtime/interpreter/mterp/mips64/op_unused_fd.S +++ b/runtime/interpreter/mterp/mips64/op_unused_fd.S @@ -1 +1,2 @@ -%include "mips64/unused.S" +%def op_unused_fd(): +% unused() diff --git a/runtime/interpreter/mterp/mips64/op_ushr_int.S b/runtime/interpreter/mterp/mips64/op_ushr_int.S index 37c90cb7ec..98d2dfbc9c 100644 --- a/runtime/interpreter/mterp/mips64/op_ushr_int.S +++ b/runtime/interpreter/mterp/mips64/op_ushr_int.S @@ -1 +1,2 @@ -%include "mips64/binop.S" {"instr":"srl a0, a0, a1"} +%def op_ushr_int(): +% binop(instr="srl a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_ushr_int_2addr.S b/runtime/interpreter/mterp/mips64/op_ushr_int_2addr.S index d6bf4135dc..9b89e21643 100644 --- a/runtime/interpreter/mterp/mips64/op_ushr_int_2addr.S +++ b/runtime/interpreter/mterp/mips64/op_ushr_int_2addr.S @@ -1 +1,2 @@ -%include "mips64/binop2addr.S" {"instr":"srl a0, a0, a1"} +%def op_ushr_int_2addr(): +% binop2addr(instr="srl a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_ushr_int_lit8.S b/runtime/interpreter/mterp/mips64/op_ushr_int_lit8.S index 2a2d843c8a..531c30a000 100644 --- a/runtime/interpreter/mterp/mips64/op_ushr_int_lit8.S +++ b/runtime/interpreter/mterp/mips64/op_ushr_int_lit8.S @@ -1 +1,2 @@ -%include "mips64/binopLit8.S" {"instr":"srl a0, a0, a1"} +%def op_ushr_int_lit8(): +% binopLit8(instr="srl a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_ushr_long.S b/runtime/interpreter/mterp/mips64/op_ushr_long.S index e724405f1f..e900f76f90 100644 --- a/runtime/interpreter/mterp/mips64/op_ushr_long.S +++ b/runtime/interpreter/mterp/mips64/op_ushr_long.S @@ -1 +1,2 @@ -%include "mips64/binopWide.S" {"instr":"dsrl a0, a0, a1"} +%def op_ushr_long(): +% binopWide(instr="dsrl a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_ushr_long_2addr.S b/runtime/interpreter/mterp/mips64/op_ushr_long_2addr.S index d2cf135566..e13fc75612 100644 --- a/runtime/interpreter/mterp/mips64/op_ushr_long_2addr.S +++ b/runtime/interpreter/mterp/mips64/op_ushr_long_2addr.S @@ -1 +1,2 @@ -%include "mips64/binopWide2addr.S" {"instr":"dsrl a0, a0, a1"} +%def op_ushr_long_2addr(): +% binopWide2addr(instr="dsrl a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_xor_int.S b/runtime/interpreter/mterp/mips64/op_xor_int.S index ee25ebc925..1379a344e0 100644 --- a/runtime/interpreter/mterp/mips64/op_xor_int.S +++ b/runtime/interpreter/mterp/mips64/op_xor_int.S @@ -1 +1,2 @@ -%include "mips64/binop.S" {"instr":"xor a0, a0, a1"} +%def op_xor_int(): +% binop(instr="xor a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_xor_int_2addr.S b/runtime/interpreter/mterp/mips64/op_xor_int_2addr.S index 0f0496729a..6dbe11c3a8 100644 --- a/runtime/interpreter/mterp/mips64/op_xor_int_2addr.S +++ b/runtime/interpreter/mterp/mips64/op_xor_int_2addr.S @@ -1 +1,2 @@ -%include "mips64/binop2addr.S" {"instr":"xor a0, a0, a1"} +%def op_xor_int_2addr(): +% binop2addr(instr="xor a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_xor_int_lit16.S b/runtime/interpreter/mterp/mips64/op_xor_int_lit16.S index ecb21aee07..f8cbce04f4 100644 --- a/runtime/interpreter/mterp/mips64/op_xor_int_lit16.S +++ b/runtime/interpreter/mterp/mips64/op_xor_int_lit16.S @@ -1 +1,2 @@ -%include "mips64/binopLit16.S" {"instr":"xor a0, a0, a1"} +%def op_xor_int_lit16(): +% binopLit16(instr="xor a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_xor_int_lit8.S b/runtime/interpreter/mterp/mips64/op_xor_int_lit8.S index 115ae99917..268a43aac8 100644 --- a/runtime/interpreter/mterp/mips64/op_xor_int_lit8.S +++ b/runtime/interpreter/mterp/mips64/op_xor_int_lit8.S @@ -1 +1,2 @@ -%include "mips64/binopLit8.S" {"instr":"xor a0, a0, a1"} +%def op_xor_int_lit8(): +% binopLit8(instr="xor a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_xor_long.S b/runtime/interpreter/mterp/mips64/op_xor_long.S index 7ebabc2710..75d4c07984 100644 --- a/runtime/interpreter/mterp/mips64/op_xor_long.S +++ b/runtime/interpreter/mterp/mips64/op_xor_long.S @@ -1 +1,2 @@ -%include "mips64/binopWide.S" {"instr":"xor a0, a0, a1"} +%def op_xor_long(): +% binopWide(instr="xor a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_xor_long_2addr.S b/runtime/interpreter/mterp/mips64/op_xor_long_2addr.S index 0f1919a21e..2e76613168 100644 --- a/runtime/interpreter/mterp/mips64/op_xor_long_2addr.S +++ b/runtime/interpreter/mterp/mips64/op_xor_long_2addr.S @@ -1 +1,2 @@ -%include "mips64/binopWide2addr.S" {"instr":"xor a0, a0, a1"} +%def op_xor_long_2addr(): +% binopWide2addr(instr="xor a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/unop.S b/runtime/interpreter/mterp/mips64/unop.S index e3f7ea0eda..860e6bbb6a 100644 --- a/runtime/interpreter/mterp/mips64/unop.S +++ b/runtime/interpreter/mterp/mips64/unop.S @@ -1,4 +1,4 @@ -%default {"preinstr":""} +%def unop(preinstr="", instr=""): /* * Generic 32-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "a0 = op a0". diff --git a/runtime/interpreter/mterp/mips64/unopWide.S b/runtime/interpreter/mterp/mips64/unopWide.S index c0dd1aa1d3..d0a6f5b766 100644 --- a/runtime/interpreter/mterp/mips64/unopWide.S +++ b/runtime/interpreter/mterp/mips64/unopWide.S @@ -1,4 +1,4 @@ -%default {"preinstr":""} +%def unopWide(preinstr="", instr=""): /* * Generic 64-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "a0 = op a0". diff --git a/runtime/interpreter/mterp/mips64/unused.S b/runtime/interpreter/mterp/mips64/unused.S index 30d38bd6cd..3d611d170b 100644 --- a/runtime/interpreter/mterp/mips64/unused.S +++ b/runtime/interpreter/mterp/mips64/unused.S @@ -1,3 +1,4 @@ +%def unused(): /* * Bail to reference interpreter to throw. */ diff --git a/runtime/interpreter/mterp/mips64/zcmp.S b/runtime/interpreter/mterp/mips64/zcmp.S index 75db49edd4..a0d2832514 100644 --- a/runtime/interpreter/mterp/mips64/zcmp.S +++ b/runtime/interpreter/mterp/mips64/zcmp.S @@ -1,3 +1,4 @@ +%def zcmp(condition=""): /* * Generic one-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform, e.g. for diff --git a/runtime/interpreter/mterp/out/mterp_arm.S b/runtime/interpreter/mterp/out/mterp_arm.S index 25512aec37..dc476b7ff8 100644 --- a/runtime/interpreter/mterp/out/mterp_arm.S +++ b/runtime/interpreter/mterp/out/mterp_arm.S @@ -1,10 +1,4 @@ -/* - * This file was generated automatically by gen-mterp.py for 'arm'. - * - * --> DO NOT EDIT <-- - */ - -/* File: arm/header.S */ +/* DO NOT EDIT: This file was generated by gen-mterp.py. */ /* * Copyright (C) 2016 The Android Open Source Project * @@ -317,8 +311,6 @@ unspecified registers or condition codes. .cfi_endproc .size \name, .-\name .endm - -/* File: arm/entry.S */ /* * Copyright (C) 2016 The Android Open Source Project * @@ -396,18 +388,14 @@ ENTRY ExecuteMterpImpl GOTO_OPCODE ip @ jump to next instruction /* NOTE: no fallthrough */ -/* File: arm/instruction_start.S */ - .type artMterpAsmInstructionStart, #object .hidden artMterpAsmInstructionStart .global artMterpAsmInstructionStart artMterpAsmInstructionStart = .L_op_nop .text - /* ------------------------------ */ .balign 128 .L_op_nop: /* 0x00 */ -/* File: arm/op_nop.S */ FETCH_ADVANCE_INST 1 @ advance to next instr, load rINST GET_INST_OPCODE ip @ ip<- opcode from rINST GOTO_OPCODE ip @ execute it @@ -415,7 +403,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move: /* 0x01 */ -/* File: arm/op_move.S */ /* for move, move-object, long-to-int */ /* op vA, vB */ mov r1, rINST, lsr #12 @ r1<- B from 15:12 @@ -433,7 +420,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_from16: /* 0x02 */ -/* File: arm/op_move_from16.S */ /* for: move/from16, move-object/from16 */ /* op vAA, vBBBB */ FETCH r1, 1 @ r1<- BBBB @@ -451,7 +437,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_16: /* 0x03 */ -/* File: arm/op_move_16.S */ /* for: move/16, move-object/16 */ /* op vAAAA, vBBBB */ FETCH r1, 2 @ r1<- BBBB @@ -469,7 +454,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_wide: /* 0x04 */ -/* File: arm/op_move_wide.S */ /* move-wide vA, vB */ /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ mov r3, rINST, lsr #12 @ r3<- B @@ -486,7 +470,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_wide_from16: /* 0x05 */ -/* File: arm/op_move_wide_from16.S */ /* move-wide/from16 vAA, vBBBB */ /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ FETCH r3, 1 @ r3<- BBBB @@ -503,7 +486,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_wide_16: /* 0x06 */ -/* File: arm/op_move_wide_16.S */ /* move-wide/16 vAAAA, vBBBB */ /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ FETCH r3, 2 @ r3<- BBBB @@ -520,8 +502,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_object: /* 0x07 */ -/* File: arm/op_move_object.S */ -/* File: arm/op_move.S */ /* for move, move-object, long-to-int */ /* op vA, vB */ mov r1, rINST, lsr #12 @ r1<- B from 15:12 @@ -536,12 +516,9 @@ artMterpAsmInstructionStart = .L_op_nop .endif GOTO_OPCODE ip @ execute next instruction - /* ------------------------------ */ .balign 128 .L_op_move_object_from16: /* 0x08 */ -/* File: arm/op_move_object_from16.S */ -/* File: arm/op_move_from16.S */ /* for: move/from16, move-object/from16 */ /* op vAA, vBBBB */ FETCH r1, 1 @ r1<- BBBB @@ -556,12 +533,9 @@ artMterpAsmInstructionStart = .L_op_nop .endif GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_move_object_16: /* 0x09 */ -/* File: arm/op_move_object_16.S */ -/* File: arm/op_move_16.S */ /* for: move/16, move-object/16 */ /* op vAAAA, vBBBB */ FETCH r1, 2 @ r1<- BBBB @@ -576,11 +550,9 @@ artMterpAsmInstructionStart = .L_op_nop .endif GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_move_result: /* 0x0a */ -/* File: arm/op_move_result.S */ /* for: move-result, move-result-object */ /* op vAA */ mov r2, rINST, lsr #8 @ r2<- AA @@ -598,7 +570,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_result_wide: /* 0x0b */ -/* File: arm/op_move_result_wide.S */ /* move-result-wide vAA */ mov rINST, rINST, lsr #8 @ rINST<- AA ldr r3, [rFP, #OFF_FP_RESULT_REGISTER] @@ -613,8 +584,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_result_object: /* 0x0c */ -/* File: arm/op_move_result_object.S */ -/* File: arm/op_move_result.S */ /* for: move-result, move-result-object */ /* op vAA */ mov r2, rINST, lsr #8 @ r2<- AA @@ -629,11 +598,9 @@ artMterpAsmInstructionStart = .L_op_nop .endif GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_move_exception: /* 0x0d */ -/* File: arm/op_move_exception.S */ /* move-exception vAA */ mov r2, rINST, lsr #8 @ r2<- AA ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] @@ -647,7 +614,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_return_void: /* 0x0e */ -/* File: arm/op_return_void.S */ .extern MterpThreadFenceForConstructor bl MterpThreadFenceForConstructor ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] @@ -661,7 +627,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_return: /* 0x0f */ -/* File: arm/op_return.S */ /* * Return a 32-bit value. * @@ -682,7 +647,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_return_wide: /* 0x10 */ -/* File: arm/op_return_wide.S */ /* * Return a 64-bit value. */ @@ -701,8 +665,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_return_object: /* 0x11 */ -/* File: arm/op_return_object.S */ -/* File: arm/op_return.S */ /* * Return a 32-bit value. * @@ -720,11 +682,9 @@ artMterpAsmInstructionStart = .L_op_nop mov r1, #0 b MterpReturn - /* ------------------------------ */ .balign 128 .L_op_const_4: /* 0x12 */ -/* File: arm/op_const_4.S */ /* const/4 vA, #+B */ sbfx r1, rINST, #12, #4 @ r1<- sssssssB (sign-extended) ubfx r0, rINST, #8, #4 @ r0<- A @@ -736,7 +696,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_16: /* 0x13 */ -/* File: arm/op_const_16.S */ /* const/16 vAA, #+BBBB */ FETCH_S r0, 1 @ r0<- ssssBBBB (sign-extended) mov r3, rINST, lsr #8 @ r3<- AA @@ -748,7 +707,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const: /* 0x14 */ -/* File: arm/op_const.S */ /* const vAA, #+BBBBbbbb */ mov r3, rINST, lsr #8 @ r3<- AA FETCH r0, 1 @ r0<- bbbb (low) @@ -762,7 +720,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_high16: /* 0x15 */ -/* File: arm/op_const_high16.S */ /* const/high16 vAA, #+BBBB0000 */ FETCH r0, 1 @ r0<- 0000BBBB (zero-extended) mov r3, rINST, lsr #8 @ r3<- AA @@ -775,7 +732,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_wide_16: /* 0x16 */ -/* File: arm/op_const_wide_16.S */ /* const-wide/16 vAA, #+BBBB */ FETCH_S r0, 1 @ r0<- ssssBBBB (sign-extended) mov r3, rINST, lsr #8 @ r3<- AA @@ -790,7 +746,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_wide_32: /* 0x17 */ -/* File: arm/op_const_wide_32.S */ /* const-wide/32 vAA, #+BBBBbbbb */ FETCH r0, 1 @ r0<- 0000bbbb (low) mov r3, rINST, lsr #8 @ r3<- AA @@ -807,7 +762,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_wide: /* 0x18 */ -/* File: arm/op_const_wide.S */ /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ FETCH r0, 1 @ r0<- bbbb (low) FETCH r1, 2 @ r1<- BBBB (low middle) @@ -826,7 +780,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_wide_high16: /* 0x19 */ -/* File: arm/op_const_wide_high16.S */ /* const-wide/high16 vAA, #+BBBB000000000000 */ FETCH r1, 1 @ r1<- 0000BBBB (zero-extended) mov r3, rINST, lsr #8 @ r3<- AA @@ -842,8 +795,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_string: /* 0x1a */ -/* File: arm/op_const_string.S */ -/* File: arm/const.S */ /* const/class vAA, type@BBBB */ /* const/method-handle vAA, method_handle@BBBB */ /* const/method-type vAA, proto@BBBB */ @@ -862,11 +813,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_const_string_jumbo: /* 0x1b */ -/* File: arm/op_const_string_jumbo.S */ /* const/string vAA, String@BBBBBBBB */ EXPORT_PC FETCH r0, 1 @ r0<- bbbb (low) @@ -886,8 +835,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_class: /* 0x1c */ -/* File: arm/op_const_class.S */ -/* File: arm/const.S */ /* const/class vAA, type@BBBB */ /* const/method-handle vAA, method_handle@BBBB */ /* const/method-type vAA, proto@BBBB */ @@ -906,11 +853,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_monitor_enter: /* 0x1d */ -/* File: arm/op_monitor_enter.S */ /* * Synchronize on an object. */ @@ -929,7 +874,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_monitor_exit: /* 0x1e */ -/* File: arm/op_monitor_exit.S */ /* * Unlock an object. * @@ -952,7 +896,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_check_cast: /* 0x1f */ -/* File: arm/op_check_cast.S */ /* * Check to see if a cast from one class to another is allowed. */ @@ -974,7 +917,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_instance_of: /* 0x20 */ -/* File: arm/op_instance_of.S */ /* * Check to see if an object reference is an instance of a class. * @@ -1002,7 +944,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_array_length: /* 0x21 */ -/* File: arm/op_array_length.S */ /* * Return the length of an array. */ @@ -1020,7 +961,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_new_instance: /* 0x22 */ -/* File: arm/op_new_instance.S */ /* * Create a new instance of a class. */ @@ -1039,7 +979,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_new_array: /* 0x23 */ -/* File: arm/op_new_array.S */ /* * Allocate an array of objects, specified with the array class * and a count. @@ -1063,7 +1002,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_filled_new_array: /* 0x24 */ -/* File: arm/op_filled_new_array.S */ /* * Create a new array with elements filled from registers. * @@ -1086,8 +1024,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_filled_new_array_range: /* 0x25 */ -/* File: arm/op_filled_new_array_range.S */ -/* File: arm/op_filled_new_array.S */ /* * Create a new array with elements filled from registers. * @@ -1107,11 +1043,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_fill_array_data: /* 0x26 */ -/* File: arm/op_fill_array_data.S */ /* fill-array-data vAA, +BBBBBBBB */ EXPORT_PC FETCH r0, 1 @ r0<- bbbb (lo) @@ -1130,7 +1064,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_throw: /* 0x27 */ -/* File: arm/op_throw.S */ /* * Throw an exception object in the current thread. */ @@ -1146,7 +1079,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_goto: /* 0x28 */ -/* File: arm/op_goto.S */ /* * Unconditional branch, 8-bit offset. * @@ -1160,7 +1092,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_goto_16: /* 0x29 */ -/* File: arm/op_goto_16.S */ /* * Unconditional branch, 16-bit offset. * @@ -1174,7 +1105,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_goto_32: /* 0x2a */ -/* File: arm/op_goto_32.S */ /* * Unconditional branch, 32-bit offset. * @@ -1195,7 +1125,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_packed_switch: /* 0x2b */ -/* File: arm/op_packed_switch.S */ /* * Handle a packed-switch or sparse-switch instruction. In both cases * we decode it and hand it off to a helper function. @@ -1219,8 +1148,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_sparse_switch: /* 0x2c */ -/* File: arm/op_sparse_switch.S */ -/* File: arm/op_packed_switch.S */ /* * Handle a packed-switch or sparse-switch instruction. In both cases * we decode it and hand it off to a helper function. @@ -1241,11 +1168,9 @@ artMterpAsmInstructionStart = .L_op_nop movs rINST, r0 b MterpCommonTakenBranch - /* ------------------------------ */ .balign 128 .L_op_cmpl_float: /* 0x2d */ -/* File: arm/op_cmpl_float.S */ /* * Compare two floating-point values. Puts 0, 1, or -1 into the * destination register based on the results of the comparison. @@ -1284,7 +1209,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_cmpg_float: /* 0x2e */ -/* File: arm/op_cmpg_float.S */ /* * Compare two floating-point values. Puts 0, 1, or -1 into the * destination register based on the results of the comparison. @@ -1323,7 +1247,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_cmpl_double: /* 0x2f */ -/* File: arm/op_cmpl_double.S */ /* * Compare two floating-point values. Puts 0, 1, or -1 into the * destination register based on the results of the comparison. @@ -1362,7 +1285,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_cmpg_double: /* 0x30 */ -/* File: arm/op_cmpg_double.S */ /* * Compare two floating-point values. Puts 0, 1, or -1 into the * destination register based on the results of the comparison. @@ -1401,7 +1323,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_cmp_long: /* 0x31 */ -/* File: arm/op_cmp_long.S */ /* * Compare two 64-bit values. Puts 0, 1, or -1 into the destination * register based on the results of the comparison. @@ -1429,8 +1350,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_if_eq: /* 0x32 */ -/* File: arm/op_if_eq.S */ -/* File: arm/bincmp.S */ /* * Generic two-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform. @@ -1451,12 +1370,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_ne: /* 0x33 */ -/* File: arm/op_if_ne.S */ -/* File: arm/bincmp.S */ /* * Generic two-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform. @@ -1477,12 +1393,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_lt: /* 0x34 */ -/* File: arm/op_if_lt.S */ -/* File: arm/bincmp.S */ /* * Generic two-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform. @@ -1503,12 +1416,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_ge: /* 0x35 */ -/* File: arm/op_if_ge.S */ -/* File: arm/bincmp.S */ /* * Generic two-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform. @@ -1529,12 +1439,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_gt: /* 0x36 */ -/* File: arm/op_if_gt.S */ -/* File: arm/bincmp.S */ /* * Generic two-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform. @@ -1555,12 +1462,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_le: /* 0x37 */ -/* File: arm/op_if_le.S */ -/* File: arm/bincmp.S */ /* * Generic two-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform. @@ -1581,12 +1485,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_eqz: /* 0x38 */ -/* File: arm/op_if_eqz.S */ -/* File: arm/zcmp.S */ /* * Generic one-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform. @@ -1605,12 +1506,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_nez: /* 0x39 */ -/* File: arm/op_if_nez.S */ -/* File: arm/zcmp.S */ /* * Generic one-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform. @@ -1629,12 +1527,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_ltz: /* 0x3a */ -/* File: arm/op_if_ltz.S */ -/* File: arm/zcmp.S */ /* * Generic one-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform. @@ -1653,12 +1548,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_gez: /* 0x3b */ -/* File: arm/op_if_gez.S */ -/* File: arm/zcmp.S */ /* * Generic one-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform. @@ -1677,12 +1569,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_gtz: /* 0x3c */ -/* File: arm/op_if_gtz.S */ -/* File: arm/zcmp.S */ /* * Generic one-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform. @@ -1701,12 +1590,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_lez: /* 0x3d */ -/* File: arm/op_if_lez.S */ -/* File: arm/zcmp.S */ /* * Generic one-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform. @@ -1725,77 +1611,57 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_unused_3e: /* 0x3e */ -/* File: arm/op_unused_3e.S */ -/* File: arm/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_3f: /* 0x3f */ -/* File: arm/op_unused_3f.S */ -/* File: arm/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_40: /* 0x40 */ -/* File: arm/op_unused_40.S */ -/* File: arm/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_41: /* 0x41 */ -/* File: arm/op_unused_41.S */ -/* File: arm/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_42: /* 0x42 */ -/* File: arm/op_unused_42.S */ -/* File: arm/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_43: /* 0x43 */ -/* File: arm/op_unused_43.S */ -/* File: arm/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_aget: /* 0x44 */ -/* File: arm/op_aget.S */ /* * Array get, 32 bits or less. vAA <- vBB[vCC]. * @@ -1828,7 +1694,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_aget_wide: /* 0x45 */ -/* File: arm/op_aget_wide.S */ /* * Array get, 64 bits. vAA <- vBB[vCC]. * @@ -1858,7 +1723,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_aget_object: /* 0x46 */ -/* File: arm/op_aget_object.S */ /* * Array object get. vAA <- vBB[vCC]. * @@ -1884,8 +1748,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_aget_boolean: /* 0x47 */ -/* File: arm/op_aget_boolean.S */ -/* File: arm/op_aget.S */ /* * Array get, 32 bits or less. vAA <- vBB[vCC]. * @@ -1915,12 +1777,9 @@ artMterpAsmInstructionStart = .L_op_nop SET_VREG r2, r9 @ vAA<- r2 GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_aget_byte: /* 0x48 */ -/* File: arm/op_aget_byte.S */ -/* File: arm/op_aget.S */ /* * Array get, 32 bits or less. vAA <- vBB[vCC]. * @@ -1950,12 +1809,9 @@ artMterpAsmInstructionStart = .L_op_nop SET_VREG r2, r9 @ vAA<- r2 GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_aget_char: /* 0x49 */ -/* File: arm/op_aget_char.S */ -/* File: arm/op_aget.S */ /* * Array get, 32 bits or less. vAA <- vBB[vCC]. * @@ -1985,12 +1841,9 @@ artMterpAsmInstructionStart = .L_op_nop SET_VREG r2, r9 @ vAA<- r2 GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_aget_short: /* 0x4a */ -/* File: arm/op_aget_short.S */ -/* File: arm/op_aget.S */ /* * Array get, 32 bits or less. vAA <- vBB[vCC]. * @@ -2020,11 +1873,9 @@ artMterpAsmInstructionStart = .L_op_nop SET_VREG r2, r9 @ vAA<- r2 GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_aput: /* 0x4b */ -/* File: arm/op_aput.S */ /* * Array put, 32 bits or less. vBB[vCC] <- vAA. * @@ -2057,7 +1908,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_aput_wide: /* 0x4c */ -/* File: arm/op_aput_wide.S */ /* * Array put, 64 bits. vBB[vCC] <- vAA. * @@ -2086,7 +1936,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_aput_object: /* 0x4d */ -/* File: arm/op_aput_object.S */ /* * Store an object into an array. vBB[vCC] <- vAA. */ @@ -2105,8 +1954,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_aput_boolean: /* 0x4e */ -/* File: arm/op_aput_boolean.S */ -/* File: arm/op_aput.S */ /* * Array put, 32 bits or less. vBB[vCC] <- vAA. * @@ -2136,12 +1983,9 @@ artMterpAsmInstructionStart = .L_op_nop strb r2, [r0, #MIRROR_BOOLEAN_ARRAY_DATA_OFFSET] @ vBB[vCC]<- r2 GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_aput_byte: /* 0x4f */ -/* File: arm/op_aput_byte.S */ -/* File: arm/op_aput.S */ /* * Array put, 32 bits or less. vBB[vCC] <- vAA. * @@ -2171,12 +2015,9 @@ artMterpAsmInstructionStart = .L_op_nop strb r2, [r0, #MIRROR_BYTE_ARRAY_DATA_OFFSET] @ vBB[vCC]<- r2 GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_aput_char: /* 0x50 */ -/* File: arm/op_aput_char.S */ -/* File: arm/op_aput.S */ /* * Array put, 32 bits or less. vBB[vCC] <- vAA. * @@ -2206,12 +2047,9 @@ artMterpAsmInstructionStart = .L_op_nop strh r2, [r0, #MIRROR_CHAR_ARRAY_DATA_OFFSET] @ vBB[vCC]<- r2 GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_aput_short: /* 0x51 */ -/* File: arm/op_aput_short.S */ -/* File: arm/op_aput.S */ /* * Array put, 32 bits or less. vBB[vCC] <- vAA. * @@ -2241,12 +2079,9 @@ artMterpAsmInstructionStart = .L_op_nop strh r2, [r0, #MIRROR_SHORT_ARRAY_DATA_OFFSET] @ vBB[vCC]<- r2 GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_iget: /* 0x52 */ -/* File: arm/op_iget.S */ -/* File: arm/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2263,13 +2098,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_iget_wide: /* 0x53 */ -/* File: arm/op_iget_wide.S */ -/* File: arm/op_iget.S */ -/* File: arm/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2286,14 +2117,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_iget_object: /* 0x54 */ -/* File: arm/op_iget_object.S */ -/* File: arm/op_iget.S */ -/* File: arm/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2310,14 +2136,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_iget_boolean: /* 0x55 */ -/* File: arm/op_iget_boolean.S */ -/* File: arm/op_iget.S */ -/* File: arm/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2334,14 +2155,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_iget_byte: /* 0x56 */ -/* File: arm/op_iget_byte.S */ -/* File: arm/op_iget.S */ -/* File: arm/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2358,14 +2174,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_iget_char: /* 0x57 */ -/* File: arm/op_iget_char.S */ -/* File: arm/op_iget.S */ -/* File: arm/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2382,14 +2193,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_iget_short: /* 0x58 */ -/* File: arm/op_iget_short.S */ -/* File: arm/op_iget.S */ -/* File: arm/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2406,13 +2212,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_iput: /* 0x59 */ -/* File: arm/op_iput.S */ -/* File: arm/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2429,13 +2231,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_iput_wide: /* 0x5a */ -/* File: arm/op_iput_wide.S */ -/* File: arm/op_iput.S */ -/* File: arm/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2452,14 +2250,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_iput_object: /* 0x5b */ -/* File: arm/op_iput_object.S */ -/* File: arm/op_iput.S */ -/* File: arm/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2476,14 +2269,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_iput_boolean: /* 0x5c */ -/* File: arm/op_iput_boolean.S */ -/* File: arm/op_iput.S */ -/* File: arm/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2500,14 +2288,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_iput_byte: /* 0x5d */ -/* File: arm/op_iput_byte.S */ -/* File: arm/op_iput.S */ -/* File: arm/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2524,14 +2307,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_iput_char: /* 0x5e */ -/* File: arm/op_iput_char.S */ -/* File: arm/op_iput.S */ -/* File: arm/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2548,14 +2326,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_iput_short: /* 0x5f */ -/* File: arm/op_iput_short.S */ -/* File: arm/op_iput.S */ -/* File: arm/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2572,13 +2345,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_sget: /* 0x60 */ -/* File: arm/op_sget.S */ -/* File: arm/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2595,13 +2364,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_sget_wide: /* 0x61 */ -/* File: arm/op_sget_wide.S */ -/* File: arm/op_sget.S */ -/* File: arm/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2618,14 +2383,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_sget_object: /* 0x62 */ -/* File: arm/op_sget_object.S */ -/* File: arm/op_sget.S */ -/* File: arm/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2642,14 +2402,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_sget_boolean: /* 0x63 */ -/* File: arm/op_sget_boolean.S */ -/* File: arm/op_sget.S */ -/* File: arm/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2666,14 +2421,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_sget_byte: /* 0x64 */ -/* File: arm/op_sget_byte.S */ -/* File: arm/op_sget.S */ -/* File: arm/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2690,14 +2440,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_sget_char: /* 0x65 */ -/* File: arm/op_sget_char.S */ -/* File: arm/op_sget.S */ -/* File: arm/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2714,14 +2459,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_sget_short: /* 0x66 */ -/* File: arm/op_sget_short.S */ -/* File: arm/op_sget.S */ -/* File: arm/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2738,13 +2478,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_sput: /* 0x67 */ -/* File: arm/op_sput.S */ -/* File: arm/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2761,13 +2497,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_sput_wide: /* 0x68 */ -/* File: arm/op_sput_wide.S */ -/* File: arm/op_sput.S */ -/* File: arm/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2784,14 +2516,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_sput_object: /* 0x69 */ -/* File: arm/op_sput_object.S */ -/* File: arm/op_sput.S */ -/* File: arm/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2808,14 +2535,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_sput_boolean: /* 0x6a */ -/* File: arm/op_sput_boolean.S */ -/* File: arm/op_sput.S */ -/* File: arm/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2832,14 +2554,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_sput_byte: /* 0x6b */ -/* File: arm/op_sput_byte.S */ -/* File: arm/op_sput.S */ -/* File: arm/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2856,14 +2573,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_sput_char: /* 0x6c */ -/* File: arm/op_sput_char.S */ -/* File: arm/op_sput.S */ -/* File: arm/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2880,14 +2592,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_sput_short: /* 0x6d */ -/* File: arm/op_sput_short.S */ -/* File: arm/op_sput.S */ -/* File: arm/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2904,13 +2611,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_invoke_virtual: /* 0x6e */ -/* File: arm/op_invoke_virtual.S */ -/* File: arm/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -2932,7 +2635,6 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip GOTO_OPCODE ip - /* * Handle a virtual method call. * @@ -2944,8 +2646,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_invoke_super: /* 0x6f */ -/* File: arm/op_invoke_super.S */ -/* File: arm/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -2967,7 +2667,6 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip GOTO_OPCODE ip - /* * Handle a "super" method call. * @@ -2979,8 +2678,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_invoke_direct: /* 0x70 */ -/* File: arm/op_invoke_direct.S */ -/* File: arm/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -3002,13 +2699,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip GOTO_OPCODE ip - - /* ------------------------------ */ .balign 128 .L_op_invoke_static: /* 0x71 */ -/* File: arm/op_invoke_static.S */ -/* File: arm/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -3030,14 +2723,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip GOTO_OPCODE ip - - - /* ------------------------------ */ .balign 128 .L_op_invoke_interface: /* 0x72 */ -/* File: arm/op_invoke_interface.S */ -/* File: arm/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -3059,7 +2747,6 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip GOTO_OPCODE ip - /* * Handle an interface method call. * @@ -3071,7 +2758,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_return_void_no_barrier: /* 0x73 */ -/* File: arm/op_return_void_no_barrier.S */ ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] mov r0, rSELF ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST @@ -3083,8 +2769,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_invoke_virtual_range: /* 0x74 */ -/* File: arm/op_invoke_virtual_range.S */ -/* File: arm/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -3106,13 +2790,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip GOTO_OPCODE ip - - /* ------------------------------ */ .balign 128 .L_op_invoke_super_range: /* 0x75 */ -/* File: arm/op_invoke_super_range.S */ -/* File: arm/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -3134,13 +2814,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip GOTO_OPCODE ip - - /* ------------------------------ */ .balign 128 .L_op_invoke_direct_range: /* 0x76 */ -/* File: arm/op_invoke_direct_range.S */ -/* File: arm/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -3162,13 +2838,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip GOTO_OPCODE ip - - /* ------------------------------ */ .balign 128 .L_op_invoke_static_range: /* 0x77 */ -/* File: arm/op_invoke_static_range.S */ -/* File: arm/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -3190,13 +2862,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip GOTO_OPCODE ip - - /* ------------------------------ */ .balign 128 .L_op_invoke_interface_range: /* 0x78 */ -/* File: arm/op_invoke_interface_range.S */ -/* File: arm/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -3218,35 +2886,25 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip GOTO_OPCODE ip - - /* ------------------------------ */ .balign 128 .L_op_unused_79: /* 0x79 */ -/* File: arm/op_unused_79.S */ -/* File: arm/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_7a: /* 0x7a */ -/* File: arm/op_unused_7a.S */ -/* File: arm/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_neg_int: /* 0x7b */ -/* File: arm/op_neg_int.S */ -/* File: arm/unop.S */ /* * Generic 32-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result = op r0". @@ -3267,12 +2925,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip @ jump to next instruction /* 8-9 instructions */ - /* ------------------------------ */ .balign 128 .L_op_not_int: /* 0x7c */ -/* File: arm/op_not_int.S */ -/* File: arm/unop.S */ /* * Generic 32-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result = op r0". @@ -3293,12 +2948,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip @ jump to next instruction /* 8-9 instructions */ - /* ------------------------------ */ .balign 128 .L_op_neg_long: /* 0x7d */ -/* File: arm/op_neg_long.S */ -/* File: arm/unopWide.S */ /* * Generic 64-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result = op r0/r1". @@ -3321,12 +2973,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip @ jump to next instruction /* 10-11 instructions */ - /* ------------------------------ */ .balign 128 .L_op_not_long: /* 0x7e */ -/* File: arm/op_not_long.S */ -/* File: arm/unopWide.S */ /* * Generic 64-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result = op r0/r1". @@ -3349,12 +2998,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip @ jump to next instruction /* 10-11 instructions */ - /* ------------------------------ */ .balign 128 .L_op_neg_float: /* 0x7f */ -/* File: arm/op_neg_float.S */ -/* File: arm/unop.S */ /* * Generic 32-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result = op r0". @@ -3375,12 +3021,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip @ jump to next instruction /* 8-9 instructions */ - /* ------------------------------ */ .balign 128 .L_op_neg_double: /* 0x80 */ -/* File: arm/op_neg_double.S */ -/* File: arm/unopWide.S */ /* * Generic 64-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result = op r0/r1". @@ -3403,12 +3046,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip @ jump to next instruction /* 10-11 instructions */ - /* ------------------------------ */ .balign 128 .L_op_int_to_long: /* 0x81 */ -/* File: arm/op_int_to_long.S */ -/* File: arm/unopWider.S */ /* * Generic 32bit-to-64bit unary operation. Provide an "instr" line * that specifies an instruction that performs "result = op r0", where @@ -3430,12 +3070,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip @ jump to next instruction /* 9-10 instructions */ - /* ------------------------------ */ .balign 128 .L_op_int_to_float: /* 0x82 */ -/* File: arm/op_int_to_float.S */ -/* File: arm/funop.S */ /* * Generic 32-bit unary floating-point operation. Provide an "instr" * line that specifies an instruction that performs "s1 = op s0". @@ -3454,12 +3091,9 @@ artMterpAsmInstructionStart = .L_op_nop fsts s1, [r9] @ vA<- s1 GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_int_to_double: /* 0x83 */ -/* File: arm/op_int_to_double.S */ -/* File: arm/funopWider.S */ /* * Generic 32bit-to-64bit floating point unary operation. Provide an * "instr" line that specifies an instruction that performs "d0 = op s0". @@ -3479,13 +3113,10 @@ artMterpAsmInstructionStart = .L_op_nop fstd d0, [r9] @ vA<- d0 GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_long_to_int: /* 0x84 */ -/* File: arm/op_long_to_int.S */ /* we ignore the high word, making this equivalent to a 32-bit reg move */ -/* File: arm/op_move.S */ /* for move, move-object, long-to-int */ /* op vA, vB */ mov r1, rINST, lsr #12 @ r1<- B from 15:12 @@ -3500,12 +3131,9 @@ artMterpAsmInstructionStart = .L_op_nop .endif GOTO_OPCODE ip @ execute next instruction - /* ------------------------------ */ .balign 128 .L_op_long_to_float: /* 0x85 */ -/* File: arm/op_long_to_float.S */ -/* File: arm/unopNarrower.S */ /* * Generic 64bit-to-32bit unary operation. Provide an "instr" line * that specifies an instruction that performs "result = op r0/r1", where @@ -3529,11 +3157,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip @ jump to next instruction /* 9-10 instructions */ - /* ------------------------------ */ .balign 128 .L_op_long_to_double: /* 0x86 */ -/* File: arm/op_long_to_double.S */ /* * Specialised 64-bit floating point operation. * @@ -3564,8 +3190,6 @@ constvalop_long_to_double: /* ------------------------------ */ .balign 128 .L_op_float_to_int: /* 0x87 */ -/* File: arm/op_float_to_int.S */ -/* File: arm/funop.S */ /* * Generic 32-bit unary floating-point operation. Provide an "instr" * line that specifies an instruction that performs "s1 = op s0". @@ -3584,12 +3208,9 @@ constvalop_long_to_double: fsts s1, [r9] @ vA<- s1 GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_float_to_long: /* 0x88 */ -/* File: arm/op_float_to_long.S */ -/* File: arm/unopWider.S */ /* * Generic 32bit-to-64bit unary operation. Provide an "instr" line * that specifies an instruction that performs "result = op r0", where @@ -3611,13 +3232,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 9-10 instructions */ - - /* ------------------------------ */ .balign 128 .L_op_float_to_double: /* 0x89 */ -/* File: arm/op_float_to_double.S */ -/* File: arm/funopWider.S */ /* * Generic 32bit-to-64bit floating point unary operation. Provide an * "instr" line that specifies an instruction that performs "d0 = op s0". @@ -3637,12 +3254,9 @@ constvalop_long_to_double: fstd d0, [r9] @ vA<- d0 GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_double_to_int: /* 0x8a */ -/* File: arm/op_double_to_int.S */ -/* File: arm/funopNarrower.S */ /* * Generic 64bit-to-32bit unary floating point operation. Provide an * "instr" line that specifies an instruction that performs "s0 = op d0". @@ -3661,12 +3275,9 @@ constvalop_long_to_double: fsts s0, [r9] @ vA<- s0 GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_double_to_long: /* 0x8b */ -/* File: arm/op_double_to_long.S */ -/* File: arm/unopWide.S */ /* * Generic 64-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result = op r0/r1". @@ -3689,13 +3300,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 10-11 instructions */ - - /* ------------------------------ */ .balign 128 .L_op_double_to_float: /* 0x8c */ -/* File: arm/op_double_to_float.S */ -/* File: arm/funopNarrower.S */ /* * Generic 64bit-to-32bit unary floating point operation. Provide an * "instr" line that specifies an instruction that performs "s0 = op d0". @@ -3714,12 +3321,9 @@ constvalop_long_to_double: fsts s0, [r9] @ vA<- s0 GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_int_to_byte: /* 0x8d */ -/* File: arm/op_int_to_byte.S */ -/* File: arm/unop.S */ /* * Generic 32-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result = op r0". @@ -3740,12 +3344,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 8-9 instructions */ - /* ------------------------------ */ .balign 128 .L_op_int_to_char: /* 0x8e */ -/* File: arm/op_int_to_char.S */ -/* File: arm/unop.S */ /* * Generic 32-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result = op r0". @@ -3766,12 +3367,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 8-9 instructions */ - /* ------------------------------ */ .balign 128 .L_op_int_to_short: /* 0x8f */ -/* File: arm/op_int_to_short.S */ -/* File: arm/unop.S */ /* * Generic 32-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result = op r0". @@ -3792,12 +3390,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 8-9 instructions */ - /* ------------------------------ */ .balign 128 .L_op_add_int: /* 0x90 */ -/* File: arm/op_add_int.S */ -/* File: arm/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = r0 op r1". @@ -3833,12 +3428,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 11-14 instructions */ - /* ------------------------------ */ .balign 128 .L_op_sub_int: /* 0x91 */ -/* File: arm/op_sub_int.S */ -/* File: arm/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = r0 op r1". @@ -3874,13 +3466,10 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 11-14 instructions */ - /* ------------------------------ */ .balign 128 .L_op_mul_int: /* 0x92 */ -/* File: arm/op_mul_int.S */ /* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ -/* File: arm/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = r0 op r1". @@ -3916,11 +3505,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 11-14 instructions */ - /* ------------------------------ */ .balign 128 .L_op_div_int: /* 0x93 */ -/* File: arm/op_div_int.S */ /* * Specialized 32-bit binary operation * @@ -3954,7 +3541,6 @@ constvalop_long_to_double: /* ------------------------------ */ .balign 128 .L_op_rem_int: /* 0x94 */ -/* File: arm/op_rem_int.S */ /* * Specialized 32-bit binary operation * @@ -3991,8 +3577,6 @@ constvalop_long_to_double: /* ------------------------------ */ .balign 128 .L_op_and_int: /* 0x95 */ -/* File: arm/op_and_int.S */ -/* File: arm/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = r0 op r1". @@ -4028,12 +3612,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 11-14 instructions */ - /* ------------------------------ */ .balign 128 .L_op_or_int: /* 0x96 */ -/* File: arm/op_or_int.S */ -/* File: arm/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = r0 op r1". @@ -4069,12 +3650,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 11-14 instructions */ - /* ------------------------------ */ .balign 128 .L_op_xor_int: /* 0x97 */ -/* File: arm/op_xor_int.S */ -/* File: arm/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = r0 op r1". @@ -4110,12 +3688,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 11-14 instructions */ - /* ------------------------------ */ .balign 128 .L_op_shl_int: /* 0x98 */ -/* File: arm/op_shl_int.S */ -/* File: arm/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = r0 op r1". @@ -4151,12 +3726,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 11-14 instructions */ - /* ------------------------------ */ .balign 128 .L_op_shr_int: /* 0x99 */ -/* File: arm/op_shr_int.S */ -/* File: arm/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = r0 op r1". @@ -4192,12 +3764,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 11-14 instructions */ - /* ------------------------------ */ .balign 128 .L_op_ushr_int: /* 0x9a */ -/* File: arm/op_ushr_int.S */ -/* File: arm/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = r0 op r1". @@ -4233,12 +3802,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 11-14 instructions */ - /* ------------------------------ */ .balign 128 .L_op_add_long: /* 0x9b */ -/* File: arm/op_add_long.S */ -/* File: arm/binopWide.S */ /* * Generic 64-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = r0-r1 op r2-r3". @@ -4277,12 +3843,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 14-17 instructions */ - /* ------------------------------ */ .balign 128 .L_op_sub_long: /* 0x9c */ -/* File: arm/op_sub_long.S */ -/* File: arm/binopWide.S */ /* * Generic 64-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = r0-r1 op r2-r3". @@ -4321,11 +3884,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 14-17 instructions */ - /* ------------------------------ */ .balign 128 .L_op_mul_long: /* 0x9d */ -/* File: arm/op_mul_long.S */ /* * Signed 64-bit integer multiply. * @@ -4367,8 +3928,6 @@ constvalop_long_to_double: /* ------------------------------ */ .balign 128 .L_op_div_long: /* 0x9e */ -/* File: arm/op_div_long.S */ -/* File: arm/binopWide.S */ /* * Generic 64-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = r0-r1 op r2-r3". @@ -4407,13 +3966,10 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 14-17 instructions */ - /* ------------------------------ */ .balign 128 .L_op_rem_long: /* 0x9f */ -/* File: arm/op_rem_long.S */ /* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ -/* File: arm/binopWide.S */ /* * Generic 64-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = r0-r1 op r2-r3". @@ -4452,12 +4008,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 14-17 instructions */ - /* ------------------------------ */ .balign 128 .L_op_and_long: /* 0xa0 */ -/* File: arm/op_and_long.S */ -/* File: arm/binopWide.S */ /* * Generic 64-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = r0-r1 op r2-r3". @@ -4496,12 +4049,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 14-17 instructions */ - /* ------------------------------ */ .balign 128 .L_op_or_long: /* 0xa1 */ -/* File: arm/op_or_long.S */ -/* File: arm/binopWide.S */ /* * Generic 64-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = r0-r1 op r2-r3". @@ -4540,12 +4090,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 14-17 instructions */ - /* ------------------------------ */ .balign 128 .L_op_xor_long: /* 0xa2 */ -/* File: arm/op_xor_long.S */ -/* File: arm/binopWide.S */ /* * Generic 64-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = r0-r1 op r2-r3". @@ -4584,11 +4131,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 14-17 instructions */ - /* ------------------------------ */ .balign 128 .L_op_shl_long: /* 0xa3 */ -/* File: arm/op_shl_long.S */ /* * Long integer shift. This is different from the generic 32/64-bit * binary operations because vAA/vBB are 64-bit but vCC (the shift @@ -4620,7 +4165,6 @@ constvalop_long_to_double: /* ------------------------------ */ .balign 128 .L_op_shr_long: /* 0xa4 */ -/* File: arm/op_shr_long.S */ /* * Long integer shift. This is different from the generic 32/64-bit * binary operations because vAA/vBB are 64-bit but vCC (the shift @@ -4652,7 +4196,6 @@ constvalop_long_to_double: /* ------------------------------ */ .balign 128 .L_op_ushr_long: /* 0xa5 */ -/* File: arm/op_ushr_long.S */ /* * Long integer shift. This is different from the generic 32/64-bit * binary operations because vAA/vBB are 64-bit but vCC (the shift @@ -4684,8 +4227,6 @@ constvalop_long_to_double: /* ------------------------------ */ .balign 128 .L_op_add_float: /* 0xa6 */ -/* File: arm/op_add_float.S */ -/* File: arm/fbinop.S */ /* * Generic 32-bit floating-point operation. Provide an "instr" line that * specifies an instruction that performs "s2 = s0 op s1". Because we @@ -4710,12 +4251,9 @@ constvalop_long_to_double: fsts s2, [r9] @ vAA<- s2 GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_sub_float: /* 0xa7 */ -/* File: arm/op_sub_float.S */ -/* File: arm/fbinop.S */ /* * Generic 32-bit floating-point operation. Provide an "instr" line that * specifies an instruction that performs "s2 = s0 op s1". Because we @@ -4740,12 +4278,9 @@ constvalop_long_to_double: fsts s2, [r9] @ vAA<- s2 GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_mul_float: /* 0xa8 */ -/* File: arm/op_mul_float.S */ -/* File: arm/fbinop.S */ /* * Generic 32-bit floating-point operation. Provide an "instr" line that * specifies an instruction that performs "s2 = s0 op s1". Because we @@ -4770,12 +4305,9 @@ constvalop_long_to_double: fsts s2, [r9] @ vAA<- s2 GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_div_float: /* 0xa9 */ -/* File: arm/op_div_float.S */ -/* File: arm/fbinop.S */ /* * Generic 32-bit floating-point operation. Provide an "instr" line that * specifies an instruction that performs "s2 = s0 op s1". Because we @@ -4800,13 +4332,10 @@ constvalop_long_to_double: fsts s2, [r9] @ vAA<- s2 GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_rem_float: /* 0xaa */ -/* File: arm/op_rem_float.S */ /* EABI doesn't define a float remainder function, but libm does */ -/* File: arm/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = r0 op r1". @@ -4842,12 +4371,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 11-14 instructions */ - /* ------------------------------ */ .balign 128 .L_op_add_double: /* 0xab */ -/* File: arm/op_add_double.S */ -/* File: arm/fbinopWide.S */ /* * Generic 64-bit double-precision floating point binary operation. * Provide an "instr" line that specifies an instruction that performs @@ -4872,12 +4398,9 @@ constvalop_long_to_double: fstd d2, [r9] @ vAA<- d2 GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_sub_double: /* 0xac */ -/* File: arm/op_sub_double.S */ -/* File: arm/fbinopWide.S */ /* * Generic 64-bit double-precision floating point binary operation. * Provide an "instr" line that specifies an instruction that performs @@ -4902,12 +4425,9 @@ constvalop_long_to_double: fstd d2, [r9] @ vAA<- d2 GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_mul_double: /* 0xad */ -/* File: arm/op_mul_double.S */ -/* File: arm/fbinopWide.S */ /* * Generic 64-bit double-precision floating point binary operation. * Provide an "instr" line that specifies an instruction that performs @@ -4932,12 +4452,9 @@ constvalop_long_to_double: fstd d2, [r9] @ vAA<- d2 GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_div_double: /* 0xae */ -/* File: arm/op_div_double.S */ -/* File: arm/fbinopWide.S */ /* * Generic 64-bit double-precision floating point binary operation. * Provide an "instr" line that specifies an instruction that performs @@ -4962,13 +4479,10 @@ constvalop_long_to_double: fstd d2, [r9] @ vAA<- d2 GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_rem_double: /* 0xaf */ -/* File: arm/op_rem_double.S */ /* EABI doesn't define a double remainder function, but libm does */ -/* File: arm/binopWide.S */ /* * Generic 64-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = r0-r1 op r2-r3". @@ -5007,12 +4521,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 14-17 instructions */ - /* ------------------------------ */ .balign 128 .L_op_add_int_2addr: /* 0xb0 */ -/* File: arm/op_add_int_2addr.S */ -/* File: arm/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0 op r1". @@ -5045,12 +4556,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_sub_int_2addr: /* 0xb1 */ -/* File: arm/op_sub_int_2addr.S */ -/* File: arm/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0 op r1". @@ -5083,13 +4591,10 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_mul_int_2addr: /* 0xb2 */ -/* File: arm/op_mul_int_2addr.S */ /* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ -/* File: arm/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0 op r1". @@ -5122,11 +4627,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_div_int_2addr: /* 0xb3 */ -/* File: arm/op_div_int_2addr.S */ /* * Specialized 32-bit binary operation * @@ -5155,11 +4658,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_rem_int_2addr: /* 0xb4 */ -/* File: arm/op_rem_int_2addr.S */ /* * Specialized 32-bit binary operation * @@ -5191,12 +4692,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_and_int_2addr: /* 0xb5 */ -/* File: arm/op_and_int_2addr.S */ -/* File: arm/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0 op r1". @@ -5229,12 +4727,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_or_int_2addr: /* 0xb6 */ -/* File: arm/op_or_int_2addr.S */ -/* File: arm/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0 op r1". @@ -5267,12 +4762,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_xor_int_2addr: /* 0xb7 */ -/* File: arm/op_xor_int_2addr.S */ -/* File: arm/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0 op r1". @@ -5305,12 +4797,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_shl_int_2addr: /* 0xb8 */ -/* File: arm/op_shl_int_2addr.S */ -/* File: arm/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0 op r1". @@ -5343,12 +4832,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_shr_int_2addr: /* 0xb9 */ -/* File: arm/op_shr_int_2addr.S */ -/* File: arm/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0 op r1". @@ -5381,12 +4867,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_ushr_int_2addr: /* 0xba */ -/* File: arm/op_ushr_int_2addr.S */ -/* File: arm/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0 op r1". @@ -5419,12 +4902,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_add_long_2addr: /* 0xbb */ -/* File: arm/op_add_long_2addr.S */ -/* File: arm/binopWide2addr.S */ /* * Generic 64-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0-r1 op r2-r3". @@ -5459,12 +4939,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 12-15 instructions */ - /* ------------------------------ */ .balign 128 .L_op_sub_long_2addr: /* 0xbc */ -/* File: arm/op_sub_long_2addr.S */ -/* File: arm/binopWide2addr.S */ /* * Generic 64-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0-r1 op r2-r3". @@ -5499,11 +4976,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 12-15 instructions */ - /* ------------------------------ */ .balign 128 .L_op_mul_long_2addr: /* 0xbd */ -/* File: arm/op_mul_long_2addr.S */ /* * Signed 64-bit integer multiply, "/2addr" version. * @@ -5532,8 +5007,6 @@ constvalop_long_to_double: /* ------------------------------ */ .balign 128 .L_op_div_long_2addr: /* 0xbe */ -/* File: arm/op_div_long_2addr.S */ -/* File: arm/binopWide2addr.S */ /* * Generic 64-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0-r1 op r2-r3". @@ -5568,13 +5041,10 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 12-15 instructions */ - /* ------------------------------ */ .balign 128 .L_op_rem_long_2addr: /* 0xbf */ -/* File: arm/op_rem_long_2addr.S */ /* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ -/* File: arm/binopWide2addr.S */ /* * Generic 64-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0-r1 op r2-r3". @@ -5609,12 +5079,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 12-15 instructions */ - /* ------------------------------ */ .balign 128 .L_op_and_long_2addr: /* 0xc0 */ -/* File: arm/op_and_long_2addr.S */ -/* File: arm/binopWide2addr.S */ /* * Generic 64-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0-r1 op r2-r3". @@ -5649,12 +5116,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 12-15 instructions */ - /* ------------------------------ */ .balign 128 .L_op_or_long_2addr: /* 0xc1 */ -/* File: arm/op_or_long_2addr.S */ -/* File: arm/binopWide2addr.S */ /* * Generic 64-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0-r1 op r2-r3". @@ -5689,12 +5153,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 12-15 instructions */ - /* ------------------------------ */ .balign 128 .L_op_xor_long_2addr: /* 0xc2 */ -/* File: arm/op_xor_long_2addr.S */ -/* File: arm/binopWide2addr.S */ /* * Generic 64-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0-r1 op r2-r3". @@ -5729,11 +5190,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 12-15 instructions */ - /* ------------------------------ */ .balign 128 .L_op_shl_long_2addr: /* 0xc3 */ -/* File: arm/op_shl_long_2addr.S */ /* * Long integer shift, 2addr version. vA is 64-bit value/result, vB is * 32-bit shift distance. @@ -5760,7 +5219,6 @@ constvalop_long_to_double: /* ------------------------------ */ .balign 128 .L_op_shr_long_2addr: /* 0xc4 */ -/* File: arm/op_shr_long_2addr.S */ /* * Long integer shift, 2addr version. vA is 64-bit value/result, vB is * 32-bit shift distance. @@ -5787,7 +5245,6 @@ constvalop_long_to_double: /* ------------------------------ */ .balign 128 .L_op_ushr_long_2addr: /* 0xc5 */ -/* File: arm/op_ushr_long_2addr.S */ /* * Long integer shift, 2addr version. vA is 64-bit value/result, vB is * 32-bit shift distance. @@ -5814,8 +5271,6 @@ constvalop_long_to_double: /* ------------------------------ */ .balign 128 .L_op_add_float_2addr: /* 0xc6 */ -/* File: arm/op_add_float_2addr.S */ -/* File: arm/fbinop2addr.S */ /* * Generic 32-bit floating point "/2addr" binary operation. Provide * an "instr" line that specifies an instruction that performs @@ -5836,12 +5291,9 @@ constvalop_long_to_double: fsts s2, [r9] @ vAA<- s2 GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_sub_float_2addr: /* 0xc7 */ -/* File: arm/op_sub_float_2addr.S */ -/* File: arm/fbinop2addr.S */ /* * Generic 32-bit floating point "/2addr" binary operation. Provide * an "instr" line that specifies an instruction that performs @@ -5862,12 +5314,9 @@ constvalop_long_to_double: fsts s2, [r9] @ vAA<- s2 GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_mul_float_2addr: /* 0xc8 */ -/* File: arm/op_mul_float_2addr.S */ -/* File: arm/fbinop2addr.S */ /* * Generic 32-bit floating point "/2addr" binary operation. Provide * an "instr" line that specifies an instruction that performs @@ -5888,12 +5337,9 @@ constvalop_long_to_double: fsts s2, [r9] @ vAA<- s2 GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_div_float_2addr: /* 0xc9 */ -/* File: arm/op_div_float_2addr.S */ -/* File: arm/fbinop2addr.S */ /* * Generic 32-bit floating point "/2addr" binary operation. Provide * an "instr" line that specifies an instruction that performs @@ -5914,13 +5360,10 @@ constvalop_long_to_double: fsts s2, [r9] @ vAA<- s2 GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_rem_float_2addr: /* 0xca */ -/* File: arm/op_rem_float_2addr.S */ /* EABI doesn't define a float remainder function, but libm does */ -/* File: arm/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0 op r1". @@ -5953,12 +5396,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_add_double_2addr: /* 0xcb */ -/* File: arm/op_add_double_2addr.S */ -/* File: arm/fbinopWide2addr.S */ /* * Generic 64-bit floating point "/2addr" binary operation. Provide * an "instr" line that specifies an instruction that performs @@ -5981,12 +5421,9 @@ constvalop_long_to_double: fstd d2, [r9] @ vAA<- d2 GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_sub_double_2addr: /* 0xcc */ -/* File: arm/op_sub_double_2addr.S */ -/* File: arm/fbinopWide2addr.S */ /* * Generic 64-bit floating point "/2addr" binary operation. Provide * an "instr" line that specifies an instruction that performs @@ -6009,12 +5446,9 @@ constvalop_long_to_double: fstd d2, [r9] @ vAA<- d2 GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_mul_double_2addr: /* 0xcd */ -/* File: arm/op_mul_double_2addr.S */ -/* File: arm/fbinopWide2addr.S */ /* * Generic 64-bit floating point "/2addr" binary operation. Provide * an "instr" line that specifies an instruction that performs @@ -6037,12 +5471,9 @@ constvalop_long_to_double: fstd d2, [r9] @ vAA<- d2 GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_div_double_2addr: /* 0xce */ -/* File: arm/op_div_double_2addr.S */ -/* File: arm/fbinopWide2addr.S */ /* * Generic 64-bit floating point "/2addr" binary operation. Provide * an "instr" line that specifies an instruction that performs @@ -6065,13 +5496,10 @@ constvalop_long_to_double: fstd d2, [r9] @ vAA<- d2 GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_rem_double_2addr: /* 0xcf */ -/* File: arm/op_rem_double_2addr.S */ /* EABI doesn't define a double remainder function, but libm does */ -/* File: arm/binopWide2addr.S */ /* * Generic 64-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0-r1 op r2-r3". @@ -6106,12 +5534,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 12-15 instructions */ - /* ------------------------------ */ .balign 128 .L_op_add_int_lit16: /* 0xd0 */ -/* File: arm/op_add_int_lit16.S */ -/* File: arm/binopLit16.S */ /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0 op r1". @@ -6141,13 +5566,10 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_rsub_int: /* 0xd1 */ -/* File: arm/op_rsub_int.S */ /* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ -/* File: arm/binopLit16.S */ /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0 op r1". @@ -6177,13 +5599,10 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_mul_int_lit16: /* 0xd2 */ -/* File: arm/op_mul_int_lit16.S */ /* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ -/* File: arm/binopLit16.S */ /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0 op r1". @@ -6213,11 +5632,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_div_int_lit16: /* 0xd3 */ -/* File: arm/op_div_int_lit16.S */ /* * Specialized 32-bit binary operation * @@ -6249,7 +5666,6 @@ constvalop_long_to_double: /* ------------------------------ */ .balign 128 .L_op_rem_int_lit16: /* 0xd4 */ -/* File: arm/op_rem_int_lit16.S */ /* * Specialized 32-bit binary operation * @@ -6284,8 +5700,6 @@ constvalop_long_to_double: /* ------------------------------ */ .balign 128 .L_op_and_int_lit16: /* 0xd5 */ -/* File: arm/op_and_int_lit16.S */ -/* File: arm/binopLit16.S */ /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0 op r1". @@ -6315,12 +5729,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_or_int_lit16: /* 0xd6 */ -/* File: arm/op_or_int_lit16.S */ -/* File: arm/binopLit16.S */ /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0 op r1". @@ -6350,12 +5761,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_xor_int_lit16: /* 0xd7 */ -/* File: arm/op_xor_int_lit16.S */ -/* File: arm/binopLit16.S */ /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0 op r1". @@ -6385,12 +5793,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_add_int_lit8: /* 0xd8 */ -/* File: arm/op_add_int_lit8.S */ -/* File: arm/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0 op r1". @@ -6426,12 +5831,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 10-12 instructions */ - /* ------------------------------ */ .balign 128 .L_op_rsub_int_lit8: /* 0xd9 */ -/* File: arm/op_rsub_int_lit8.S */ -/* File: arm/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0 op r1". @@ -6467,13 +5869,10 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 10-12 instructions */ - /* ------------------------------ */ .balign 128 .L_op_mul_int_lit8: /* 0xda */ -/* File: arm/op_mul_int_lit8.S */ /* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ -/* File: arm/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0 op r1". @@ -6509,11 +5908,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 10-12 instructions */ - /* ------------------------------ */ .balign 128 .L_op_div_int_lit8: /* 0xdb */ -/* File: arm/op_div_int_lit8.S */ /* * Specialized 32-bit binary operation * @@ -6546,7 +5943,6 @@ constvalop_long_to_double: /* ------------------------------ */ .balign 128 .L_op_rem_int_lit8: /* 0xdc */ -/* File: arm/op_rem_int_lit8.S */ /* * Specialized 32-bit binary operation * @@ -6582,8 +5978,6 @@ constvalop_long_to_double: /* ------------------------------ */ .balign 128 .L_op_and_int_lit8: /* 0xdd */ -/* File: arm/op_and_int_lit8.S */ -/* File: arm/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0 op r1". @@ -6619,12 +6013,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 10-12 instructions */ - /* ------------------------------ */ .balign 128 .L_op_or_int_lit8: /* 0xde */ -/* File: arm/op_or_int_lit8.S */ -/* File: arm/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0 op r1". @@ -6660,12 +6051,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 10-12 instructions */ - /* ------------------------------ */ .balign 128 .L_op_xor_int_lit8: /* 0xdf */ -/* File: arm/op_xor_int_lit8.S */ -/* File: arm/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0 op r1". @@ -6701,12 +6089,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 10-12 instructions */ - /* ------------------------------ */ .balign 128 .L_op_shl_int_lit8: /* 0xe0 */ -/* File: arm/op_shl_int_lit8.S */ -/* File: arm/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0 op r1". @@ -6742,12 +6127,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 10-12 instructions */ - /* ------------------------------ */ .balign 128 .L_op_shr_int_lit8: /* 0xe1 */ -/* File: arm/op_shr_int_lit8.S */ -/* File: arm/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0 op r1". @@ -6783,12 +6165,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 10-12 instructions */ - /* ------------------------------ */ .balign 128 .L_op_ushr_int_lit8: /* 0xe2 */ -/* File: arm/op_ushr_int_lit8.S */ -/* File: arm/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0 op r1". @@ -6824,11 +6203,9 @@ constvalop_long_to_double: GOTO_OPCODE ip @ jump to next instruction /* 10-12 instructions */ - /* ------------------------------ */ .balign 128 .L_op_iget_quick: /* 0xe3 */ -/* File: arm/op_iget_quick.S */ /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ /* op vA, vB, offset@CCCC */ mov r2, rINST, lsr #12 @ r2<- B @@ -6846,7 +6223,6 @@ constvalop_long_to_double: /* ------------------------------ */ .balign 128 .L_op_iget_wide_quick: /* 0xe4 */ -/* File: arm/op_iget_wide_quick.S */ /* iget-wide-quick vA, vB, offset@CCCC */ mov r2, rINST, lsr #12 @ r2<- B FETCH ip, 1 @ ip<- field byte offset @@ -6865,7 +6241,6 @@ constvalop_long_to_double: /* ------------------------------ */ .balign 128 .L_op_iget_object_quick: /* 0xe5 */ -/* File: arm/op_iget_object_quick.S */ /* For: iget-object-quick */ /* op vA, vB, offset@CCCC */ mov r2, rINST, lsr #12 @ r2<- B @@ -6886,7 +6261,6 @@ constvalop_long_to_double: /* ------------------------------ */ .balign 128 .L_op_iput_quick: /* 0xe6 */ -/* File: arm/op_iput_quick.S */ /* For: iput-quick, iput-object-quick */ /* op vA, vB, offset@CCCC */ mov r2, rINST, lsr #12 @ r2<- B @@ -6904,7 +6278,6 @@ constvalop_long_to_double: /* ------------------------------ */ .balign 128 .L_op_iput_wide_quick: /* 0xe7 */ -/* File: arm/op_iput_wide_quick.S */ /* iput-wide-quick vA, vB, offset@CCCC */ mov r2, rINST, lsr #12 @ r2<- B FETCH r3, 1 @ r3<- field byte offset @@ -6922,7 +6295,6 @@ constvalop_long_to_double: /* ------------------------------ */ .balign 128 .L_op_iput_object_quick: /* 0xe8 */ -/* File: arm/op_iput_object_quick.S */ EXPORT_PC add r0, rFP, #OFF_FP_SHADOWFRAME mov r1, rPC @@ -6937,8 +6309,6 @@ constvalop_long_to_double: /* ------------------------------ */ .balign 128 .L_op_invoke_virtual_quick: /* 0xe9 */ -/* File: arm/op_invoke_virtual_quick.S */ -/* File: arm/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -6960,13 +6330,9 @@ constvalop_long_to_double: GET_INST_OPCODE ip GOTO_OPCODE ip - - /* ------------------------------ */ .balign 128 .L_op_invoke_virtual_range_quick: /* 0xea */ -/* File: arm/op_invoke_virtual_range_quick.S */ -/* File: arm/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -6988,13 +6354,9 @@ constvalop_long_to_double: GET_INST_OPCODE ip GOTO_OPCODE ip - - /* ------------------------------ */ .balign 128 .L_op_iput_boolean_quick: /* 0xeb */ -/* File: arm/op_iput_boolean_quick.S */ -/* File: arm/op_iput_quick.S */ /* For: iput-quick, iput-object-quick */ /* op vA, vB, offset@CCCC */ mov r2, rINST, lsr #12 @ r2<- B @@ -7009,12 +6371,9 @@ constvalop_long_to_double: GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_iput_byte_quick: /* 0xec */ -/* File: arm/op_iput_byte_quick.S */ -/* File: arm/op_iput_quick.S */ /* For: iput-quick, iput-object-quick */ /* op vA, vB, offset@CCCC */ mov r2, rINST, lsr #12 @ r2<- B @@ -7029,12 +6388,9 @@ constvalop_long_to_double: GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_iput_char_quick: /* 0xed */ -/* File: arm/op_iput_char_quick.S */ -/* File: arm/op_iput_quick.S */ /* For: iput-quick, iput-object-quick */ /* op vA, vB, offset@CCCC */ mov r2, rINST, lsr #12 @ r2<- B @@ -7049,12 +6405,9 @@ constvalop_long_to_double: GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_iput_short_quick: /* 0xee */ -/* File: arm/op_iput_short_quick.S */ -/* File: arm/op_iput_quick.S */ /* For: iput-quick, iput-object-quick */ /* op vA, vB, offset@CCCC */ mov r2, rINST, lsr #12 @ r2<- B @@ -7069,12 +6422,9 @@ constvalop_long_to_double: GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_iget_boolean_quick: /* 0xef */ -/* File: arm/op_iget_boolean_quick.S */ -/* File: arm/op_iget_quick.S */ /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ /* op vA, vB, offset@CCCC */ mov r2, rINST, lsr #12 @ r2<- B @@ -7089,12 +6439,9 @@ constvalop_long_to_double: GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_iget_byte_quick: /* 0xf0 */ -/* File: arm/op_iget_byte_quick.S */ -/* File: arm/op_iget_quick.S */ /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ /* op vA, vB, offset@CCCC */ mov r2, rINST, lsr #12 @ r2<- B @@ -7109,12 +6456,9 @@ constvalop_long_to_double: GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_iget_char_quick: /* 0xf1 */ -/* File: arm/op_iget_char_quick.S */ -/* File: arm/op_iget_quick.S */ /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ /* op vA, vB, offset@CCCC */ mov r2, rINST, lsr #12 @ r2<- B @@ -7129,12 +6473,9 @@ constvalop_long_to_double: GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_iget_short_quick: /* 0xf2 */ -/* File: arm/op_iget_short_quick.S */ -/* File: arm/op_iget_quick.S */ /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ /* op vA, vB, offset@CCCC */ mov r2, rINST, lsr #12 @ r2<- B @@ -7149,89 +6490,65 @@ constvalop_long_to_double: GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_unused_f3: /* 0xf3 */ -/* File: arm/op_unused_f3.S */ -/* File: arm/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_f4: /* 0xf4 */ -/* File: arm/op_unused_f4.S */ -/* File: arm/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_f5: /* 0xf5 */ -/* File: arm/op_unused_f5.S */ -/* File: arm/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_f6: /* 0xf6 */ -/* File: arm/op_unused_f6.S */ -/* File: arm/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_f7: /* 0xf7 */ -/* File: arm/op_unused_f7.S */ -/* File: arm/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_f8: /* 0xf8 */ -/* File: arm/op_unused_f8.S */ -/* File: arm/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_f9: /* 0xf9 */ -/* File: arm/op_unused_f9.S */ -/* File: arm/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_invoke_polymorphic: /* 0xfa */ -/* File: arm/op_invoke_polymorphic.S */ -/* File: arm/invoke_polymorphic.S */ /* * invoke-polymorphic handler wrapper. */ @@ -7253,12 +6570,9 @@ constvalop_long_to_double: GET_INST_OPCODE ip GOTO_OPCODE ip - /* ------------------------------ */ .balign 128 .L_op_invoke_polymorphic_range: /* 0xfb */ -/* File: arm/op_invoke_polymorphic_range.S */ -/* File: arm/invoke_polymorphic.S */ /* * invoke-polymorphic handler wrapper. */ @@ -7280,12 +6594,9 @@ constvalop_long_to_double: GET_INST_OPCODE ip GOTO_OPCODE ip - /* ------------------------------ */ .balign 128 .L_op_invoke_custom: /* 0xfc */ -/* File: arm/op_invoke_custom.S */ -/* File: arm/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -7307,7 +6618,6 @@ constvalop_long_to_double: GET_INST_OPCODE ip GOTO_OPCODE ip - /* * Handle an invoke-custom invocation. * @@ -7319,8 +6629,6 @@ constvalop_long_to_double: /* ------------------------------ */ .balign 128 .L_op_invoke_custom_range: /* 0xfd */ -/* File: arm/op_invoke_custom_range.S */ -/* File: arm/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -7342,13 +6650,9 @@ constvalop_long_to_double: GET_INST_OPCODE ip GOTO_OPCODE ip - - /* ------------------------------ */ .balign 128 .L_op_const_method_handle: /* 0xfe */ -/* File: arm/op_const_method_handle.S */ -/* File: arm/const.S */ /* const/class vAA, type@BBBB */ /* const/method-handle vAA, method_handle@BBBB */ /* const/method-type vAA, proto@BBBB */ @@ -7367,12 +6671,9 @@ constvalop_long_to_double: GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_const_method_type: /* 0xff */ -/* File: arm/op_const_method_type.S */ -/* File: arm/const.S */ /* const/class vAA, type@BBBB */ /* const/method-handle vAA, method_handle@BBBB */ /* const/method-type vAA, proto@BBBB */ @@ -7391,32 +6692,19 @@ constvalop_long_to_double: GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction - .balign 128 -/* File: arm/instruction_end.S */ .type artMterpAsmInstructionEnd, #object .hidden artMterpAsmInstructionEnd .global artMterpAsmInstructionEnd artMterpAsmInstructionEnd: - -/* - * =========================================================================== - * Sister implementations - * =========================================================================== - */ -/* File: arm/instruction_start_sister.S */ - .type artMterpAsmSisterStart, #object .hidden artMterpAsmSisterStart .global artMterpAsmSisterStart .text .balign 4 artMterpAsmSisterStart: - - -/* continuation for op_float_to_long */ /* * Convert the float in r0 to a long in r0/r1. * @@ -7445,8 +6733,6 @@ f2l_maybeNaN: mov r0, #0 mov r1, #0 bx lr @ return 0 for NaN - -/* continuation for op_double_to_long */ /* * Convert the double in r0/r1 to a long in r0/r1. * @@ -7477,25 +6763,20 @@ d2l_maybeNaN: mov r0, #0 mov r1, #0 bx lr @ return 0 for NaN -/* File: arm/instruction_end_sister.S */ .type artMterpAsmSisterEnd, #object .hidden artMterpAsmSisterEnd .global artMterpAsmSisterEnd artMterpAsmSisterEnd: -/* File: arm/instruction_start_alt.S */ - .type artMterpAsmAltInstructionStart, #object .hidden artMterpAsmAltInstructionStart .global artMterpAsmAltInstructionStart artMterpAsmAltInstructionStart = .L_ALT_op_nop .text - /* ------------------------------ */ .balign 128 .L_ALT_op_nop: /* 0x00 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7513,7 +6794,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move: /* 0x01 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7531,7 +6811,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_from16: /* 0x02 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7549,7 +6828,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_16: /* 0x03 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7567,7 +6845,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_wide: /* 0x04 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7585,7 +6862,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_wide_from16: /* 0x05 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7603,7 +6879,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_wide_16: /* 0x06 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7621,7 +6896,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_object: /* 0x07 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7639,7 +6913,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_object_from16: /* 0x08 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7657,7 +6930,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_object_16: /* 0x09 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7675,7 +6947,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_result: /* 0x0a */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7693,7 +6964,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_result_wide: /* 0x0b */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7711,7 +6981,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_result_object: /* 0x0c */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7729,7 +6998,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_exception: /* 0x0d */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7747,7 +7015,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_return_void: /* 0x0e */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7765,7 +7032,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_return: /* 0x0f */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7783,7 +7049,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_return_wide: /* 0x10 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7801,7 +7066,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_return_object: /* 0x11 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7819,7 +7083,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_4: /* 0x12 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7837,7 +7100,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_16: /* 0x13 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7855,7 +7117,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const: /* 0x14 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7873,7 +7134,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_high16: /* 0x15 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7891,7 +7151,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_wide_16: /* 0x16 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7909,7 +7168,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_wide_32: /* 0x17 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7927,7 +7185,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_wide: /* 0x18 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7945,7 +7202,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_wide_high16: /* 0x19 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7963,7 +7219,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_string: /* 0x1a */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7981,7 +7236,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_string_jumbo: /* 0x1b */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7999,7 +7253,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_class: /* 0x1c */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8017,7 +7270,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_monitor_enter: /* 0x1d */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8035,7 +7287,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_monitor_exit: /* 0x1e */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8053,7 +7304,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_check_cast: /* 0x1f */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8071,7 +7321,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_instance_of: /* 0x20 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8089,7 +7338,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_array_length: /* 0x21 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8107,7 +7355,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_new_instance: /* 0x22 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8125,7 +7372,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_new_array: /* 0x23 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8143,7 +7389,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_filled_new_array: /* 0x24 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8161,7 +7406,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_filled_new_array_range: /* 0x25 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8179,7 +7423,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_fill_array_data: /* 0x26 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8197,7 +7440,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_throw: /* 0x27 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8215,7 +7457,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_goto: /* 0x28 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8233,7 +7474,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_goto_16: /* 0x29 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8251,7 +7491,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_goto_32: /* 0x2a */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8269,7 +7508,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_packed_switch: /* 0x2b */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8287,7 +7525,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sparse_switch: /* 0x2c */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8305,7 +7542,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_cmpl_float: /* 0x2d */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8323,7 +7559,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_cmpg_float: /* 0x2e */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8341,7 +7576,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_cmpl_double: /* 0x2f */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8359,7 +7593,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_cmpg_double: /* 0x30 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8377,7 +7610,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_cmp_long: /* 0x31 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8395,7 +7627,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_eq: /* 0x32 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8413,7 +7644,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_ne: /* 0x33 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8431,7 +7661,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_lt: /* 0x34 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8449,7 +7678,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_ge: /* 0x35 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8467,7 +7695,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_gt: /* 0x36 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8485,7 +7712,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_le: /* 0x37 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8503,7 +7729,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_eqz: /* 0x38 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8521,7 +7746,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_nez: /* 0x39 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8539,7 +7763,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_ltz: /* 0x3a */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8557,7 +7780,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_gez: /* 0x3b */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8575,7 +7797,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_gtz: /* 0x3c */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8593,7 +7814,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_lez: /* 0x3d */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8611,7 +7831,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_3e: /* 0x3e */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8629,7 +7848,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_3f: /* 0x3f */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8647,7 +7865,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_40: /* 0x40 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8665,7 +7882,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_41: /* 0x41 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8683,7 +7899,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_42: /* 0x42 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8701,7 +7916,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_43: /* 0x43 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8719,7 +7933,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aget: /* 0x44 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8737,7 +7950,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aget_wide: /* 0x45 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8755,7 +7967,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aget_object: /* 0x46 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8773,7 +7984,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aget_boolean: /* 0x47 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8791,7 +8001,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aget_byte: /* 0x48 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8809,7 +8018,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aget_char: /* 0x49 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8827,7 +8035,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aget_short: /* 0x4a */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8845,7 +8052,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aput: /* 0x4b */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8863,7 +8069,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aput_wide: /* 0x4c */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8881,7 +8086,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aput_object: /* 0x4d */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8899,7 +8103,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aput_boolean: /* 0x4e */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8917,7 +8120,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aput_byte: /* 0x4f */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8935,7 +8137,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aput_char: /* 0x50 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8953,7 +8154,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aput_short: /* 0x51 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8971,7 +8171,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget: /* 0x52 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8989,7 +8188,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_wide: /* 0x53 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9007,7 +8205,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_object: /* 0x54 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9025,7 +8222,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_boolean: /* 0x55 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9043,7 +8239,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_byte: /* 0x56 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9061,7 +8256,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_char: /* 0x57 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9079,7 +8273,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_short: /* 0x58 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9097,7 +8290,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput: /* 0x59 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9115,7 +8307,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_wide: /* 0x5a */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9133,7 +8324,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_object: /* 0x5b */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9151,7 +8341,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_boolean: /* 0x5c */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9169,7 +8358,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_byte: /* 0x5d */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9187,7 +8375,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_char: /* 0x5e */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9205,7 +8392,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_short: /* 0x5f */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9223,7 +8409,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sget: /* 0x60 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9241,7 +8426,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sget_wide: /* 0x61 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9259,7 +8443,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sget_object: /* 0x62 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9277,7 +8460,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sget_boolean: /* 0x63 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9295,7 +8477,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sget_byte: /* 0x64 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9313,7 +8494,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sget_char: /* 0x65 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9331,7 +8511,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sget_short: /* 0x66 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9349,7 +8528,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sput: /* 0x67 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9367,7 +8545,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sput_wide: /* 0x68 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9385,7 +8562,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sput_object: /* 0x69 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9403,7 +8579,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sput_boolean: /* 0x6a */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9421,7 +8596,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sput_byte: /* 0x6b */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9439,7 +8613,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sput_char: /* 0x6c */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9457,7 +8630,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sput_short: /* 0x6d */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9475,7 +8647,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_virtual: /* 0x6e */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9493,7 +8664,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_super: /* 0x6f */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9511,7 +8681,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_direct: /* 0x70 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9529,7 +8698,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_static: /* 0x71 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9547,7 +8715,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_interface: /* 0x72 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9565,7 +8732,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_return_void_no_barrier: /* 0x73 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9583,7 +8749,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_virtual_range: /* 0x74 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9601,7 +8766,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_super_range: /* 0x75 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9619,7 +8783,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_direct_range: /* 0x76 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9637,7 +8800,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_static_range: /* 0x77 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9655,7 +8817,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_interface_range: /* 0x78 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9673,7 +8834,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_79: /* 0x79 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9691,7 +8851,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_7a: /* 0x7a */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9709,7 +8868,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_neg_int: /* 0x7b */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9727,7 +8885,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_not_int: /* 0x7c */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9745,7 +8902,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_neg_long: /* 0x7d */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9763,7 +8919,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_not_long: /* 0x7e */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9781,7 +8936,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_neg_float: /* 0x7f */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9799,7 +8953,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_neg_double: /* 0x80 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9817,7 +8970,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_int_to_long: /* 0x81 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9835,7 +8987,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_int_to_float: /* 0x82 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9853,7 +9004,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_int_to_double: /* 0x83 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9871,7 +9021,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_long_to_int: /* 0x84 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9889,7 +9038,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_long_to_float: /* 0x85 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9907,7 +9055,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_long_to_double: /* 0x86 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9925,7 +9072,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_float_to_int: /* 0x87 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9943,7 +9089,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_float_to_long: /* 0x88 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9961,7 +9106,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_float_to_double: /* 0x89 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9979,7 +9123,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_double_to_int: /* 0x8a */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9997,7 +9140,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_double_to_long: /* 0x8b */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10015,7 +9157,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_double_to_float: /* 0x8c */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10033,7 +9174,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_int_to_byte: /* 0x8d */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10051,7 +9191,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_int_to_char: /* 0x8e */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10069,7 +9208,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_int_to_short: /* 0x8f */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10087,7 +9225,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_int: /* 0x90 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10105,7 +9242,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_int: /* 0x91 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10123,7 +9259,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_int: /* 0x92 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10141,7 +9276,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_int: /* 0x93 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10159,7 +9293,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_int: /* 0x94 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10177,7 +9310,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_and_int: /* 0x95 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10195,7 +9327,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_or_int: /* 0x96 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10213,7 +9344,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_xor_int: /* 0x97 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10231,7 +9361,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shl_int: /* 0x98 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10249,7 +9378,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shr_int: /* 0x99 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10267,7 +9395,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_ushr_int: /* 0x9a */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10285,7 +9412,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_long: /* 0x9b */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10303,7 +9429,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_long: /* 0x9c */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10321,7 +9446,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_long: /* 0x9d */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10339,7 +9463,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_long: /* 0x9e */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10357,7 +9480,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_long: /* 0x9f */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10375,7 +9497,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_and_long: /* 0xa0 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10393,7 +9514,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_or_long: /* 0xa1 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10411,7 +9531,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_xor_long: /* 0xa2 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10429,7 +9548,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shl_long: /* 0xa3 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10447,7 +9565,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shr_long: /* 0xa4 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10465,7 +9582,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_ushr_long: /* 0xa5 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10483,7 +9599,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_float: /* 0xa6 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10501,7 +9616,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_float: /* 0xa7 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10519,7 +9633,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_float: /* 0xa8 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10537,7 +9650,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_float: /* 0xa9 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10555,7 +9667,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_float: /* 0xaa */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10573,7 +9684,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_double: /* 0xab */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10591,7 +9701,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_double: /* 0xac */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10609,7 +9718,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_double: /* 0xad */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10627,7 +9735,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_double: /* 0xae */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10645,7 +9752,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_double: /* 0xaf */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10663,7 +9769,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_int_2addr: /* 0xb0 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10681,7 +9786,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_int_2addr: /* 0xb1 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10699,7 +9803,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_int_2addr: /* 0xb2 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10717,7 +9820,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_int_2addr: /* 0xb3 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10735,7 +9837,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_int_2addr: /* 0xb4 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10753,7 +9854,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_and_int_2addr: /* 0xb5 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10771,7 +9871,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_or_int_2addr: /* 0xb6 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10789,7 +9888,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_xor_int_2addr: /* 0xb7 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10807,7 +9905,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shl_int_2addr: /* 0xb8 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10825,7 +9922,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shr_int_2addr: /* 0xb9 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10843,7 +9939,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_ushr_int_2addr: /* 0xba */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10861,7 +9956,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_long_2addr: /* 0xbb */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10879,7 +9973,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_long_2addr: /* 0xbc */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10897,7 +9990,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_long_2addr: /* 0xbd */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10915,7 +10007,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_long_2addr: /* 0xbe */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10933,7 +10024,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_long_2addr: /* 0xbf */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10951,7 +10041,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_and_long_2addr: /* 0xc0 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10969,7 +10058,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_or_long_2addr: /* 0xc1 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10987,7 +10075,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_xor_long_2addr: /* 0xc2 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11005,7 +10092,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shl_long_2addr: /* 0xc3 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11023,7 +10109,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shr_long_2addr: /* 0xc4 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11041,7 +10126,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_ushr_long_2addr: /* 0xc5 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11059,7 +10143,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_float_2addr: /* 0xc6 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11077,7 +10160,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_float_2addr: /* 0xc7 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11095,7 +10177,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_float_2addr: /* 0xc8 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11113,7 +10194,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_float_2addr: /* 0xc9 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11131,7 +10211,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_float_2addr: /* 0xca */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11149,7 +10228,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_double_2addr: /* 0xcb */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11167,7 +10245,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_double_2addr: /* 0xcc */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11185,7 +10262,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_double_2addr: /* 0xcd */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11203,7 +10279,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_double_2addr: /* 0xce */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11221,7 +10296,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_double_2addr: /* 0xcf */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11239,7 +10313,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_int_lit16: /* 0xd0 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11257,7 +10330,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rsub_int: /* 0xd1 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11275,7 +10347,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_int_lit16: /* 0xd2 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11293,7 +10364,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_int_lit16: /* 0xd3 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11311,7 +10381,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_int_lit16: /* 0xd4 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11329,7 +10398,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_and_int_lit16: /* 0xd5 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11347,7 +10415,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_or_int_lit16: /* 0xd6 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11365,7 +10432,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_xor_int_lit16: /* 0xd7 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11383,7 +10449,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_int_lit8: /* 0xd8 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11401,7 +10466,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rsub_int_lit8: /* 0xd9 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11419,7 +10483,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_int_lit8: /* 0xda */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11437,7 +10500,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_int_lit8: /* 0xdb */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11455,7 +10517,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_int_lit8: /* 0xdc */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11473,7 +10534,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_and_int_lit8: /* 0xdd */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11491,7 +10551,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_or_int_lit8: /* 0xde */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11509,7 +10568,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_xor_int_lit8: /* 0xdf */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11527,7 +10585,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shl_int_lit8: /* 0xe0 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11545,7 +10602,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shr_int_lit8: /* 0xe1 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11563,7 +10619,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_ushr_int_lit8: /* 0xe2 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11581,7 +10636,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_quick: /* 0xe3 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11599,7 +10653,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_wide_quick: /* 0xe4 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11617,7 +10670,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_object_quick: /* 0xe5 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11635,7 +10687,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_quick: /* 0xe6 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11653,7 +10704,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_wide_quick: /* 0xe7 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11671,7 +10721,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_object_quick: /* 0xe8 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11689,7 +10738,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_virtual_quick: /* 0xe9 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11707,7 +10755,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_virtual_range_quick: /* 0xea */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11725,7 +10772,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_boolean_quick: /* 0xeb */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11743,7 +10789,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_byte_quick: /* 0xec */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11761,7 +10806,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_char_quick: /* 0xed */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11779,7 +10823,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_short_quick: /* 0xee */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11797,7 +10840,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_boolean_quick: /* 0xef */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11815,7 +10857,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_byte_quick: /* 0xf0 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11833,7 +10874,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_char_quick: /* 0xf1 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11851,7 +10891,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_short_quick: /* 0xf2 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11869,7 +10908,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_f3: /* 0xf3 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11887,7 +10925,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_f4: /* 0xf4 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11905,7 +10942,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_f5: /* 0xf5 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11923,7 +10959,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_f6: /* 0xf6 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11941,7 +10976,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_f7: /* 0xf7 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11959,7 +10993,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_f8: /* 0xf8 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11977,7 +11010,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_f9: /* 0xf9 */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11995,7 +11027,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_polymorphic: /* 0xfa */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -12013,7 +11044,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_polymorphic_range: /* 0xfb */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -12031,7 +11061,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_custom: /* 0xfc */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -12049,7 +11078,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_custom_range: /* 0xfd */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -12067,7 +11095,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_method_handle: /* 0xfe */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -12085,7 +11112,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_method_type: /* 0xff */ -/* File: arm/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -12101,14 +11127,11 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. .balign 128 -/* File: arm/instruction_end_alt.S */ .type artMterpAsmAltInstructionEnd, #object .hidden artMterpAsmAltInstructionEnd .global artMterpAsmAltInstructionEnd artMterpAsmAltInstructionEnd: - -/* File: arm/footer.S */ /* * =========================================================================== * Common subroutines and data @@ -12406,4 +11429,3 @@ MterpProfileActive: END ExecuteMterpImpl - diff --git a/runtime/interpreter/mterp/out/mterp_arm64.S b/runtime/interpreter/mterp/out/mterp_arm64.S index fd60c95a37..c8c9cdb0fe 100644 --- a/runtime/interpreter/mterp/out/mterp_arm64.S +++ b/runtime/interpreter/mterp/out/mterp_arm64.S @@ -1,10 +1,4 @@ -/* - * This file was generated automatically by gen-mterp.py for 'arm64'. - * - * --> DO NOT EDIT <-- - */ - -/* File: arm64/header.S */ +/* DO NOT EDIT: This file was generated by gen-mterp.py. */ /* * Copyright (C) 2016 The Android Open Source Project * @@ -358,8 +352,6 @@ codes. .cfi_endproc .size \name, .-\name .endm - -/* File: arm64/entry.S */ /* * Copyright (C) 2016 The Android Open Source Project * @@ -427,18 +419,14 @@ ENTRY ExecuteMterpImpl GOTO_OPCODE ip // jump to next instruction /* NOTE: no fallthrough */ -/* File: arm64/instruction_start.S */ - .type artMterpAsmInstructionStart, #object .hidden artMterpAsmInstructionStart .global artMterpAsmInstructionStart artMterpAsmInstructionStart = .L_op_nop .text - /* ------------------------------ */ .balign 128 .L_op_nop: /* 0x00 */ -/* File: arm64/op_nop.S */ FETCH_ADVANCE_INST 1 // advance to next instr, load rINST GET_INST_OPCODE ip // ip<- opcode from rINST GOTO_OPCODE ip // execute it @@ -446,7 +434,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move: /* 0x01 */ -/* File: arm64/op_move.S */ /* for move, move-object, long-to-int */ /* op vA, vB */ lsr w1, wINST, #12 // x1<- B from 15:12 @@ -464,7 +451,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_from16: /* 0x02 */ -/* File: arm64/op_move_from16.S */ /* for: move/from16, move-object/from16 */ /* op vAA, vBBBB */ FETCH w1, 1 // r1<- BBBB @@ -482,7 +468,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_16: /* 0x03 */ -/* File: arm64/op_move_16.S */ /* for: move/16, move-object/16 */ /* op vAAAA, vBBBB */ FETCH w1, 2 // w1<- BBBB @@ -500,7 +485,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_wide: /* 0x04 */ -/* File: arm64/op_move_wide.S */ /* move-wide vA, vB */ /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ lsr w3, wINST, #12 // w3<- B @@ -514,7 +498,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_wide_from16: /* 0x05 */ -/* File: arm64/op_move_wide_from16.S */ /* move-wide/from16 vAA, vBBBB */ /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ FETCH w3, 1 // w3<- BBBB @@ -528,7 +511,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_wide_16: /* 0x06 */ -/* File: arm64/op_move_wide_16.S */ /* move-wide/16 vAAAA, vBBBB */ /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ FETCH w3, 2 // w3<- BBBB @@ -542,8 +524,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_object: /* 0x07 */ -/* File: arm64/op_move_object.S */ -/* File: arm64/op_move.S */ /* for move, move-object, long-to-int */ /* op vA, vB */ lsr w1, wINST, #12 // x1<- B from 15:12 @@ -558,12 +538,9 @@ artMterpAsmInstructionStart = .L_op_nop .endif GOTO_OPCODE ip // execute next instruction - /* ------------------------------ */ .balign 128 .L_op_move_object_from16: /* 0x08 */ -/* File: arm64/op_move_object_from16.S */ -/* File: arm64/op_move_from16.S */ /* for: move/from16, move-object/from16 */ /* op vAA, vBBBB */ FETCH w1, 1 // r1<- BBBB @@ -578,12 +555,9 @@ artMterpAsmInstructionStart = .L_op_nop .endif GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_move_object_16: /* 0x09 */ -/* File: arm64/op_move_object_16.S */ -/* File: arm64/op_move_16.S */ /* for: move/16, move-object/16 */ /* op vAAAA, vBBBB */ FETCH w1, 2 // w1<- BBBB @@ -598,11 +572,9 @@ artMterpAsmInstructionStart = .L_op_nop .endif GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_move_result: /* 0x0a */ -/* File: arm64/op_move_result.S */ /* for: move-result, move-result-object */ /* op vAA */ lsr w2, wINST, #8 // r2<- AA @@ -620,7 +592,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_result_wide: /* 0x0b */ -/* File: arm64/op_move_result_wide.S */ /* for: move-result-wide */ /* op vAA */ lsr w2, wINST, #8 // r2<- AA @@ -634,8 +605,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_result_object: /* 0x0c */ -/* File: arm64/op_move_result_object.S */ -/* File: arm64/op_move_result.S */ /* for: move-result, move-result-object */ /* op vAA */ lsr w2, wINST, #8 // r2<- AA @@ -650,11 +619,9 @@ artMterpAsmInstructionStart = .L_op_nop .endif GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_move_exception: /* 0x0d */ -/* File: arm64/op_move_exception.S */ /* move-exception vAA */ lsr w2, wINST, #8 // w2<- AA ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] @@ -668,7 +635,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_return_void: /* 0x0e */ -/* File: arm64/op_return_void.S */ .extern MterpThreadFenceForConstructor bl MterpThreadFenceForConstructor ldr w7, [xSELF, #THREAD_FLAGS_OFFSET] @@ -685,7 +651,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_return: /* 0x0f */ -/* File: arm64/op_return.S */ /* * Return a 32-bit value. * @@ -709,7 +674,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_return_wide: /* 0x10 */ -/* File: arm64/op_return_wide.S */ /* * Return a 64-bit value. */ @@ -732,8 +696,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_return_object: /* 0x11 */ -/* File: arm64/op_return_object.S */ -/* File: arm64/op_return.S */ /* * Return a 32-bit value. * @@ -754,11 +716,9 @@ artMterpAsmInstructionStart = .L_op_nop bl MterpSuspendCheck // (self) b .Lop_return_object_return - /* ------------------------------ */ .balign 128 .L_op_const_4: /* 0x12 */ -/* File: arm64/op_const_4.S */ /* const/4 vA, #+B */ sbfx w1, wINST, #12, #4 // w1<- sssssssB ubfx w0, wINST, #8, #4 // w0<- A @@ -770,7 +730,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_16: /* 0x13 */ -/* File: arm64/op_const_16.S */ /* const/16 vAA, #+BBBB */ FETCH_S w0, 1 // w0<- ssssBBBB (sign-extended) lsr w3, wINST, #8 // w3<- AA @@ -782,7 +741,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const: /* 0x14 */ -/* File: arm64/op_const.S */ /* const vAA, #+BBBBbbbb */ lsr w3, wINST, #8 // w3<- AA FETCH w0, 1 // w0<- bbbb (low @@ -796,7 +754,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_high16: /* 0x15 */ -/* File: arm64/op_const_high16.S */ /* const/high16 vAA, #+BBBB0000 */ FETCH w0, 1 // r0<- 0000BBBB (zero-extended) lsr w3, wINST, #8 // r3<- AA @@ -809,7 +766,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_wide_16: /* 0x16 */ -/* File: arm64/op_const_wide_16.S */ /* const-wide/16 vAA, #+BBBB */ FETCH_S x0, 1 // x0<- ssssssssssssBBBB (sign-extended) lsr w3, wINST, #8 // w3<- AA @@ -821,7 +777,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_wide_32: /* 0x17 */ -/* File: arm64/op_const_wide_32.S */ /* const-wide/32 vAA, #+BBBBbbbb */ FETCH w0, 1 // x0<- 000000000000bbbb (low) lsr w3, wINST, #8 // w3<- AA @@ -835,7 +790,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_wide: /* 0x18 */ -/* File: arm64/op_const_wide.S */ /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ FETCH w0, 1 // w0<- bbbb (low) FETCH w1, 2 // w1<- BBBB (low middle) @@ -853,7 +807,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_wide_high16: /* 0x19 */ -/* File: arm64/op_const_wide_high16.S */ /* const-wide/high16 vAA, #+BBBB000000000000 */ FETCH w0, 1 // w0<- 0000BBBB (zero-extended) lsr w1, wINST, #8 // w1<- AA @@ -866,8 +819,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_string: /* 0x1a */ -/* File: arm64/op_const_string.S */ -/* File: arm64/const.S */ /* const/class vAA, type@BBBB */ /* const/method-handle vAA, method_handle@BBBB */ /* const/method-type vAA, proto@BBBB */ @@ -885,11 +836,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from rINST GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_const_string_jumbo: /* 0x1b */ -/* File: arm64/op_const_string_jumbo.S */ /* const/string vAA, String//BBBBBBBB */ EXPORT_PC FETCH w0, 1 // w0<- bbbb (low @@ -908,8 +857,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_class: /* 0x1c */ -/* File: arm64/op_const_class.S */ -/* File: arm64/const.S */ /* const/class vAA, type@BBBB */ /* const/method-handle vAA, method_handle@BBBB */ /* const/method-type vAA, proto@BBBB */ @@ -927,11 +874,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from rINST GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_monitor_enter: /* 0x1d */ -/* File: arm64/op_monitor_enter.S */ /* * Synchronize on an object. */ @@ -949,7 +894,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_monitor_exit: /* 0x1e */ -/* File: arm64/op_monitor_exit.S */ /* * Unlock an object. * @@ -971,7 +915,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_check_cast: /* 0x1f */ -/* File: arm64/op_check_cast.S */ /* * Check to see if a cast from one class to another is allowed. */ @@ -992,7 +935,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_instance_of: /* 0x20 */ -/* File: arm64/op_instance_of.S */ /* * Check to see if an object reference is an instance of a class. * @@ -1019,7 +961,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_array_length: /* 0x21 */ -/* File: arm64/op_array_length.S */ /* * Return the length of an array. */ @@ -1036,7 +977,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_new_instance: /* 0x22 */ -/* File: arm64/op_new_instance.S */ /* * Create a new instance of a class. */ @@ -1054,7 +994,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_new_array: /* 0x23 */ -/* File: arm64/op_new_array.S */ /* * Allocate an array of objects, specified with the array class * and a count. @@ -1077,7 +1016,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_filled_new_array: /* 0x24 */ -/* File: arm64/op_filled_new_array.S */ /* * Create a new array with elements filled from registers. * @@ -1099,8 +1037,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_filled_new_array_range: /* 0x25 */ -/* File: arm64/op_filled_new_array_range.S */ -/* File: arm64/op_filled_new_array.S */ /* * Create a new array with elements filled from registers. * @@ -1119,11 +1055,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from rINST GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_fill_array_data: /* 0x26 */ -/* File: arm64/op_fill_array_data.S */ /* fill-array-data vAA, +BBBBBBBB */ EXPORT_PC FETCH w0, 1 // x0<- 000000000000bbbb (lo) @@ -1141,7 +1075,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_throw: /* 0x27 */ -/* File: arm64/op_throw.S */ /* * Throw an exception object in the current thread. */ @@ -1156,7 +1089,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_goto: /* 0x28 */ -/* File: arm64/op_goto.S */ /* * Unconditional branch, 8-bit offset. * @@ -1170,7 +1102,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_goto_16: /* 0x29 */ -/* File: arm64/op_goto_16.S */ /* * Unconditional branch, 16-bit offset. * @@ -1184,7 +1115,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_goto_32: /* 0x2a */ -/* File: arm64/op_goto_32.S */ /* * Unconditional branch, 32-bit offset. * @@ -1205,7 +1135,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_packed_switch: /* 0x2b */ -/* File: arm64/op_packed_switch.S */ /* * Handle a packed-switch or sparse-switch instruction. In both cases * we decode it and hand it off to a helper function. @@ -1229,8 +1158,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_sparse_switch: /* 0x2c */ -/* File: arm64/op_sparse_switch.S */ -/* File: arm64/op_packed_switch.S */ /* * Handle a packed-switch or sparse-switch instruction. In both cases * we decode it and hand it off to a helper function. @@ -1251,12 +1178,9 @@ artMterpAsmInstructionStart = .L_op_nop sxtw xINST, w0 b MterpCommonTakenBranchNoFlags - /* ------------------------------ */ .balign 128 .L_op_cmpl_float: /* 0x2d */ -/* File: arm64/op_cmpl_float.S */ -/* File: arm64/fcmp.S */ /* * Compare two floating-point values. Puts 0, 1, or -1 into the * destination register based on the results of the comparison. @@ -1276,12 +1200,9 @@ artMterpAsmInstructionStart = .L_op_nop SET_VREG w0, w4 // vAA<- w0 GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_cmpg_float: /* 0x2e */ -/* File: arm64/op_cmpg_float.S */ -/* File: arm64/fcmp.S */ /* * Compare two floating-point values. Puts 0, 1, or -1 into the * destination register based on the results of the comparison. @@ -1301,12 +1222,9 @@ artMterpAsmInstructionStart = .L_op_nop SET_VREG w0, w4 // vAA<- w0 GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_cmpl_double: /* 0x2f */ -/* File: arm64/op_cmpl_double.S */ -/* File: arm64/fcmp.S */ /* * Compare two floating-point values. Puts 0, 1, or -1 into the * destination register based on the results of the comparison. @@ -1326,12 +1244,9 @@ artMterpAsmInstructionStart = .L_op_nop SET_VREG w0, w4 // vAA<- w0 GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_cmpg_double: /* 0x30 */ -/* File: arm64/op_cmpg_double.S */ -/* File: arm64/fcmp.S */ /* * Compare two floating-point values. Puts 0, 1, or -1 into the * destination register based on the results of the comparison. @@ -1351,11 +1266,9 @@ artMterpAsmInstructionStart = .L_op_nop SET_VREG w0, w4 // vAA<- w0 GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_cmp_long: /* 0x31 */ -/* File: arm64/op_cmp_long.S */ FETCH w0, 1 // w0<- CCBB lsr w4, wINST, #8 // w4<- AA and w2, w0, #255 // w2<- BB @@ -1373,8 +1286,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_if_eq: /* 0x32 */ -/* File: arm64/op_if_eq.S */ -/* File: arm64/bincmp.S */ /* * Generic two-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform. @@ -1395,12 +1306,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from wINST GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_ne: /* 0x33 */ -/* File: arm64/op_if_ne.S */ -/* File: arm64/bincmp.S */ /* * Generic two-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform. @@ -1421,12 +1329,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from wINST GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_lt: /* 0x34 */ -/* File: arm64/op_if_lt.S */ -/* File: arm64/bincmp.S */ /* * Generic two-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform. @@ -1447,12 +1352,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from wINST GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_ge: /* 0x35 */ -/* File: arm64/op_if_ge.S */ -/* File: arm64/bincmp.S */ /* * Generic two-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform. @@ -1473,12 +1375,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from wINST GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_gt: /* 0x36 */ -/* File: arm64/op_if_gt.S */ -/* File: arm64/bincmp.S */ /* * Generic two-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform. @@ -1499,12 +1398,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from wINST GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_le: /* 0x37 */ -/* File: arm64/op_if_le.S */ -/* File: arm64/bincmp.S */ /* * Generic two-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform. @@ -1525,12 +1421,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from wINST GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_eqz: /* 0x38 */ -/* File: arm64/op_if_eqz.S */ -/* File: arm64/zcmp.S */ /* * Generic one-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform. @@ -1551,12 +1444,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from wINST GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_nez: /* 0x39 */ -/* File: arm64/op_if_nez.S */ -/* File: arm64/zcmp.S */ /* * Generic one-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform. @@ -1577,12 +1467,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from wINST GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_ltz: /* 0x3a */ -/* File: arm64/op_if_ltz.S */ -/* File: arm64/zcmp.S */ /* * Generic one-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform. @@ -1603,12 +1490,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from wINST GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_gez: /* 0x3b */ -/* File: arm64/op_if_gez.S */ -/* File: arm64/zcmp.S */ /* * Generic one-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform. @@ -1629,12 +1513,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from wINST GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_gtz: /* 0x3c */ -/* File: arm64/op_if_gtz.S */ -/* File: arm64/zcmp.S */ /* * Generic one-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform. @@ -1655,12 +1536,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from wINST GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_lez: /* 0x3d */ -/* File: arm64/op_if_lez.S */ -/* File: arm64/zcmp.S */ /* * Generic one-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform. @@ -1681,77 +1559,57 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from wINST GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_unused_3e: /* 0x3e */ -/* File: arm64/op_unused_3e.S */ -/* File: arm64/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_3f: /* 0x3f */ -/* File: arm64/op_unused_3f.S */ -/* File: arm64/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_40: /* 0x40 */ -/* File: arm64/op_unused_40.S */ -/* File: arm64/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_41: /* 0x41 */ -/* File: arm64/op_unused_41.S */ -/* File: arm64/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_42: /* 0x42 */ -/* File: arm64/op_unused_42.S */ -/* File: arm64/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_43: /* 0x43 */ -/* File: arm64/op_unused_43.S */ -/* File: arm64/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_aget: /* 0x44 */ -/* File: arm64/op_aget.S */ /* * Array get, 32 bits or less. vAA <- vBB[vCC]. * @@ -1783,7 +1641,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_aget_wide: /* 0x45 */ -/* File: arm64/op_aget_wide.S */ /* * Array get, 64 bits. vAA <- vBB[vCC]. * @@ -1809,7 +1666,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_aget_object: /* 0x46 */ -/* File: arm64/op_aget_object.S */ /* * Array object get. vAA <- vBB[vCC]. * @@ -1834,8 +1690,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_aget_boolean: /* 0x47 */ -/* File: arm64/op_aget_boolean.S */ -/* File: arm64/op_aget.S */ /* * Array get, 32 bits or less. vAA <- vBB[vCC]. * @@ -1864,12 +1718,9 @@ artMterpAsmInstructionStart = .L_op_nop SET_VREG w2, w9 // vAA<- w2 GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_aget_byte: /* 0x48 */ -/* File: arm64/op_aget_byte.S */ -/* File: arm64/op_aget.S */ /* * Array get, 32 bits or less. vAA <- vBB[vCC]. * @@ -1898,12 +1749,9 @@ artMterpAsmInstructionStart = .L_op_nop SET_VREG w2, w9 // vAA<- w2 GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_aget_char: /* 0x49 */ -/* File: arm64/op_aget_char.S */ -/* File: arm64/op_aget.S */ /* * Array get, 32 bits or less. vAA <- vBB[vCC]. * @@ -1932,12 +1780,9 @@ artMterpAsmInstructionStart = .L_op_nop SET_VREG w2, w9 // vAA<- w2 GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_aget_short: /* 0x4a */ -/* File: arm64/op_aget_short.S */ -/* File: arm64/op_aget.S */ /* * Array get, 32 bits or less. vAA <- vBB[vCC]. * @@ -1966,11 +1811,9 @@ artMterpAsmInstructionStart = .L_op_nop SET_VREG w2, w9 // vAA<- w2 GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_aput: /* 0x4b */ -/* File: arm64/op_aput.S */ /* * Array put, 32 bits or less. vBB[vCC] <- vAA. * @@ -2002,7 +1845,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_aput_wide: /* 0x4c */ -/* File: arm64/op_aput_wide.S */ /* * Array put, 64 bits. vBB[vCC] <- vAA. * @@ -2028,7 +1870,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_aput_object: /* 0x4d */ -/* File: arm64/op_aput_object.S */ /* * Store an object into an array. vBB[vCC] <- vAA. */ @@ -2046,8 +1887,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_aput_boolean: /* 0x4e */ -/* File: arm64/op_aput_boolean.S */ -/* File: arm64/op_aput.S */ /* * Array put, 32 bits or less. vBB[vCC] <- vAA. * @@ -2076,12 +1915,9 @@ artMterpAsmInstructionStart = .L_op_nop strb w2, [x0, #MIRROR_BOOLEAN_ARRAY_DATA_OFFSET] // vBB[vCC]<- w2 GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_aput_byte: /* 0x4f */ -/* File: arm64/op_aput_byte.S */ -/* File: arm64/op_aput.S */ /* * Array put, 32 bits or less. vBB[vCC] <- vAA. * @@ -2110,12 +1946,9 @@ artMterpAsmInstructionStart = .L_op_nop strb w2, [x0, #MIRROR_BYTE_ARRAY_DATA_OFFSET] // vBB[vCC]<- w2 GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_aput_char: /* 0x50 */ -/* File: arm64/op_aput_char.S */ -/* File: arm64/op_aput.S */ /* * Array put, 32 bits or less. vBB[vCC] <- vAA. * @@ -2144,12 +1977,9 @@ artMterpAsmInstructionStart = .L_op_nop strh w2, [x0, #MIRROR_CHAR_ARRAY_DATA_OFFSET] // vBB[vCC]<- w2 GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_aput_short: /* 0x51 */ -/* File: arm64/op_aput_short.S */ -/* File: arm64/op_aput.S */ /* * Array put, 32 bits or less. vBB[vCC] <- vAA. * @@ -2178,12 +2008,9 @@ artMterpAsmInstructionStart = .L_op_nop strh w2, [x0, #MIRROR_SHORT_ARRAY_DATA_OFFSET] // vBB[vCC]<- w2 GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_iget: /* 0x52 */ -/* File: arm64/op_iget.S */ -/* File: arm64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2199,13 +2026,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from rINST GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_iget_wide: /* 0x53 */ -/* File: arm64/op_iget_wide.S */ -/* File: arm64/op_iget.S */ -/* File: arm64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2221,14 +2044,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from rINST GOTO_OPCODE ip // jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_iget_object: /* 0x54 */ -/* File: arm64/op_iget_object.S */ -/* File: arm64/op_iget.S */ -/* File: arm64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2244,14 +2062,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from rINST GOTO_OPCODE ip // jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_iget_boolean: /* 0x55 */ -/* File: arm64/op_iget_boolean.S */ -/* File: arm64/op_iget.S */ -/* File: arm64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2267,14 +2080,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from rINST GOTO_OPCODE ip // jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_iget_byte: /* 0x56 */ -/* File: arm64/op_iget_byte.S */ -/* File: arm64/op_iget.S */ -/* File: arm64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2290,14 +2098,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from rINST GOTO_OPCODE ip // jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_iget_char: /* 0x57 */ -/* File: arm64/op_iget_char.S */ -/* File: arm64/op_iget.S */ -/* File: arm64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2313,14 +2116,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from rINST GOTO_OPCODE ip // jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_iget_short: /* 0x58 */ -/* File: arm64/op_iget_short.S */ -/* File: arm64/op_iget.S */ -/* File: arm64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2336,13 +2134,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from rINST GOTO_OPCODE ip // jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_iput: /* 0x59 */ -/* File: arm64/op_iput.S */ -/* File: arm64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2358,13 +2152,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from rINST GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_iput_wide: /* 0x5a */ -/* File: arm64/op_iput_wide.S */ -/* File: arm64/op_iput.S */ -/* File: arm64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2380,14 +2170,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from rINST GOTO_OPCODE ip // jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_iput_object: /* 0x5b */ -/* File: arm64/op_iput_object.S */ -/* File: arm64/op_iput.S */ -/* File: arm64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2403,14 +2188,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from rINST GOTO_OPCODE ip // jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_iput_boolean: /* 0x5c */ -/* File: arm64/op_iput_boolean.S */ -/* File: arm64/op_iput.S */ -/* File: arm64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2426,14 +2206,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from rINST GOTO_OPCODE ip // jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_iput_byte: /* 0x5d */ -/* File: arm64/op_iput_byte.S */ -/* File: arm64/op_iput.S */ -/* File: arm64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2449,14 +2224,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from rINST GOTO_OPCODE ip // jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_iput_char: /* 0x5e */ -/* File: arm64/op_iput_char.S */ -/* File: arm64/op_iput.S */ -/* File: arm64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2472,14 +2242,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from rINST GOTO_OPCODE ip // jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_iput_short: /* 0x5f */ -/* File: arm64/op_iput_short.S */ -/* File: arm64/op_iput.S */ -/* File: arm64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2495,13 +2260,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from rINST GOTO_OPCODE ip // jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_sget: /* 0x60 */ -/* File: arm64/op_sget.S */ -/* File: arm64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2517,13 +2278,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from rINST GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_sget_wide: /* 0x61 */ -/* File: arm64/op_sget_wide.S */ -/* File: arm64/op_sget.S */ -/* File: arm64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2539,14 +2296,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from rINST GOTO_OPCODE ip // jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_sget_object: /* 0x62 */ -/* File: arm64/op_sget_object.S */ -/* File: arm64/op_sget.S */ -/* File: arm64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2562,14 +2314,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from rINST GOTO_OPCODE ip // jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_sget_boolean: /* 0x63 */ -/* File: arm64/op_sget_boolean.S */ -/* File: arm64/op_sget.S */ -/* File: arm64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2585,14 +2332,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from rINST GOTO_OPCODE ip // jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_sget_byte: /* 0x64 */ -/* File: arm64/op_sget_byte.S */ -/* File: arm64/op_sget.S */ -/* File: arm64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2608,14 +2350,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from rINST GOTO_OPCODE ip // jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_sget_char: /* 0x65 */ -/* File: arm64/op_sget_char.S */ -/* File: arm64/op_sget.S */ -/* File: arm64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2631,14 +2368,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from rINST GOTO_OPCODE ip // jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_sget_short: /* 0x66 */ -/* File: arm64/op_sget_short.S */ -/* File: arm64/op_sget.S */ -/* File: arm64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2654,13 +2386,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from rINST GOTO_OPCODE ip // jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_sput: /* 0x67 */ -/* File: arm64/op_sput.S */ -/* File: arm64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2676,13 +2404,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from rINST GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_sput_wide: /* 0x68 */ -/* File: arm64/op_sput_wide.S */ -/* File: arm64/op_sput.S */ -/* File: arm64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2698,14 +2422,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from rINST GOTO_OPCODE ip // jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_sput_object: /* 0x69 */ -/* File: arm64/op_sput_object.S */ -/* File: arm64/op_sput.S */ -/* File: arm64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2721,14 +2440,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from rINST GOTO_OPCODE ip // jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_sput_boolean: /* 0x6a */ -/* File: arm64/op_sput_boolean.S */ -/* File: arm64/op_sput.S */ -/* File: arm64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2744,14 +2458,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from rINST GOTO_OPCODE ip // jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_sput_byte: /* 0x6b */ -/* File: arm64/op_sput_byte.S */ -/* File: arm64/op_sput.S */ -/* File: arm64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2767,14 +2476,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from rINST GOTO_OPCODE ip // jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_sput_char: /* 0x6c */ -/* File: arm64/op_sput_char.S */ -/* File: arm64/op_sput.S */ -/* File: arm64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2790,14 +2494,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from rINST GOTO_OPCODE ip // jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_sput_short: /* 0x6d */ -/* File: arm64/op_sput_short.S */ -/* File: arm64/op_sput.S */ -/* File: arm64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2813,13 +2512,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from rINST GOTO_OPCODE ip // jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_invoke_virtual: /* 0x6e */ -/* File: arm64/op_invoke_virtual.S */ -/* File: arm64/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -2839,7 +2534,6 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip GOTO_OPCODE ip - /* * Handle a virtual method call. * @@ -2851,8 +2545,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_invoke_super: /* 0x6f */ -/* File: arm64/op_invoke_super.S */ -/* File: arm64/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -2872,7 +2564,6 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip GOTO_OPCODE ip - /* * Handle a "super" method call. * @@ -2884,8 +2575,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_invoke_direct: /* 0x70 */ -/* File: arm64/op_invoke_direct.S */ -/* File: arm64/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -2905,13 +2594,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip GOTO_OPCODE ip - - /* ------------------------------ */ .balign 128 .L_op_invoke_static: /* 0x71 */ -/* File: arm64/op_invoke_static.S */ -/* File: arm64/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -2931,14 +2616,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip GOTO_OPCODE ip - - - /* ------------------------------ */ .balign 128 .L_op_invoke_interface: /* 0x72 */ -/* File: arm64/op_invoke_interface.S */ -/* File: arm64/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -2958,7 +2638,6 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip GOTO_OPCODE ip - /* * Handle an interface method call. * @@ -2970,7 +2649,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_return_void_no_barrier: /* 0x73 */ -/* File: arm64/op_return_void_no_barrier.S */ ldr w7, [xSELF, #THREAD_FLAGS_OFFSET] mov x0, xSELF ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST @@ -2985,8 +2663,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_invoke_virtual_range: /* 0x74 */ -/* File: arm64/op_invoke_virtual_range.S */ -/* File: arm64/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -3006,13 +2682,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip GOTO_OPCODE ip - - /* ------------------------------ */ .balign 128 .L_op_invoke_super_range: /* 0x75 */ -/* File: arm64/op_invoke_super_range.S */ -/* File: arm64/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -3032,13 +2704,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip GOTO_OPCODE ip - - /* ------------------------------ */ .balign 128 .L_op_invoke_direct_range: /* 0x76 */ -/* File: arm64/op_invoke_direct_range.S */ -/* File: arm64/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -3058,13 +2726,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip GOTO_OPCODE ip - - /* ------------------------------ */ .balign 128 .L_op_invoke_static_range: /* 0x77 */ -/* File: arm64/op_invoke_static_range.S */ -/* File: arm64/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -3084,13 +2748,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip GOTO_OPCODE ip - - /* ------------------------------ */ .balign 128 .L_op_invoke_interface_range: /* 0x78 */ -/* File: arm64/op_invoke_interface_range.S */ -/* File: arm64/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -3110,35 +2770,25 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip GOTO_OPCODE ip - - /* ------------------------------ */ .balign 128 .L_op_unused_79: /* 0x79 */ -/* File: arm64/op_unused_79.S */ -/* File: arm64/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_7a: /* 0x7a */ -/* File: arm64/op_unused_7a.S */ -/* File: arm64/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_neg_int: /* 0x7b */ -/* File: arm64/op_neg_int.S */ -/* File: arm64/unop.S */ /* * Generic 32-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result = op w0". @@ -3158,12 +2808,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 8-9 instructions */ - /* ------------------------------ */ .balign 128 .L_op_not_int: /* 0x7c */ -/* File: arm64/op_not_int.S */ -/* File: arm64/unop.S */ /* * Generic 32-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result = op w0". @@ -3183,12 +2830,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 8-9 instructions */ - /* ------------------------------ */ .balign 128 .L_op_neg_long: /* 0x7d */ -/* File: arm64/op_neg_long.S */ -/* File: arm64/unopWide.S */ /* * Generic 64-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result = op x0". @@ -3206,12 +2850,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-11 instructions */ - /* ------------------------------ */ .balign 128 .L_op_not_long: /* 0x7e */ -/* File: arm64/op_not_long.S */ -/* File: arm64/unopWide.S */ /* * Generic 64-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result = op x0". @@ -3229,12 +2870,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-11 instructions */ - /* ------------------------------ */ .balign 128 .L_op_neg_float: /* 0x7f */ -/* File: arm64/op_neg_float.S */ -/* File: arm64/unop.S */ /* * Generic 32-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result = op w0". @@ -3254,12 +2892,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 8-9 instructions */ - /* ------------------------------ */ .balign 128 .L_op_neg_double: /* 0x80 */ -/* File: arm64/op_neg_double.S */ -/* File: arm64/unopWide.S */ /* * Generic 64-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result = op x0". @@ -3277,11 +2912,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-11 instructions */ - /* ------------------------------ */ .balign 128 .L_op_int_to_long: /* 0x81 */ -/* File: arm64/op_int_to_long.S */ /* int-to-long vA, vB */ lsr w3, wINST, #12 // w3<- B ubfx w4, wINST, #8, #4 // w4<- A @@ -3294,8 +2927,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_int_to_float: /* 0x82 */ -/* File: arm64/op_int_to_float.S */ -/* File: arm64/funopNarrow.S */ /* * Generic 32bit-to-32bit floating point unary operation. Provide an * "instr" line that specifies an instruction that performs "s0 = op w0". @@ -3313,12 +2944,9 @@ artMterpAsmInstructionStart = .L_op_nop SET_VREG s0, w4 // vA<- d0 GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_int_to_double: /* 0x83 */ -/* File: arm64/op_int_to_double.S */ -/* File: arm64/funopWider.S */ /* * Generic 32bit-to-64bit floating point unary operation. Provide an * "instr" line that specifies an instruction that performs "d0 = op w0". @@ -3335,13 +2963,10 @@ artMterpAsmInstructionStart = .L_op_nop SET_VREG_WIDE d0, w4 // vA<- d0 GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_long_to_int: /* 0x84 */ -/* File: arm64/op_long_to_int.S */ /* we ignore the high word, making this equivalent to a 32-bit reg move */ -/* File: arm64/op_move.S */ /* for move, move-object, long-to-int */ /* op vA, vB */ lsr w1, wINST, #12 // x1<- B from 15:12 @@ -3356,12 +2981,9 @@ artMterpAsmInstructionStart = .L_op_nop .endif GOTO_OPCODE ip // execute next instruction - /* ------------------------------ */ .balign 128 .L_op_long_to_float: /* 0x85 */ -/* File: arm64/op_long_to_float.S */ -/* File: arm64/funopNarrower.S */ /* * Generic 64bit-to-32bit floating point unary operation. Provide an * "instr" line that specifies an instruction that performs "s0 = op x0". @@ -3378,12 +3000,9 @@ artMterpAsmInstructionStart = .L_op_nop SET_VREG s0, w4 // vA<- d0 GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_long_to_double: /* 0x86 */ -/* File: arm64/op_long_to_double.S */ -/* File: arm64/funopWide.S */ /* * Generic 64bit-to-64bit floating point unary operation. Provide an * "instr" line that specifies an instruction that performs "d0 = op x0". @@ -3400,12 +3019,9 @@ artMterpAsmInstructionStart = .L_op_nop SET_VREG_WIDE d0, w4 // vA<- d0 GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_float_to_int: /* 0x87 */ -/* File: arm64/op_float_to_int.S */ -/* File: arm64/funopNarrow.S */ /* * Generic 32bit-to-32bit floating point unary operation. Provide an * "instr" line that specifies an instruction that performs "w0 = op s0". @@ -3423,12 +3039,9 @@ artMterpAsmInstructionStart = .L_op_nop SET_VREG w0, w4 // vA<- d0 GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_float_to_long: /* 0x88 */ -/* File: arm64/op_float_to_long.S */ -/* File: arm64/funopWider.S */ /* * Generic 32bit-to-64bit floating point unary operation. Provide an * "instr" line that specifies an instruction that performs "x0 = op s0". @@ -3445,12 +3058,9 @@ artMterpAsmInstructionStart = .L_op_nop SET_VREG_WIDE x0, w4 // vA<- d0 GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_float_to_double: /* 0x89 */ -/* File: arm64/op_float_to_double.S */ -/* File: arm64/funopWider.S */ /* * Generic 32bit-to-64bit floating point unary operation. Provide an * "instr" line that specifies an instruction that performs "d0 = op s0". @@ -3467,12 +3077,9 @@ artMterpAsmInstructionStart = .L_op_nop SET_VREG_WIDE d0, w4 // vA<- d0 GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_double_to_int: /* 0x8a */ -/* File: arm64/op_double_to_int.S */ -/* File: arm64/funopNarrower.S */ /* * Generic 64bit-to-32bit floating point unary operation. Provide an * "instr" line that specifies an instruction that performs "w0 = op d0". @@ -3489,12 +3096,9 @@ artMterpAsmInstructionStart = .L_op_nop SET_VREG w0, w4 // vA<- d0 GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_double_to_long: /* 0x8b */ -/* File: arm64/op_double_to_long.S */ -/* File: arm64/funopWide.S */ /* * Generic 64bit-to-64bit floating point unary operation. Provide an * "instr" line that specifies an instruction that performs "x0 = op d0". @@ -3511,12 +3115,9 @@ artMterpAsmInstructionStart = .L_op_nop SET_VREG_WIDE x0, w4 // vA<- d0 GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_double_to_float: /* 0x8c */ -/* File: arm64/op_double_to_float.S */ -/* File: arm64/funopNarrower.S */ /* * Generic 64bit-to-32bit floating point unary operation. Provide an * "instr" line that specifies an instruction that performs "s0 = op d0". @@ -3533,12 +3134,9 @@ artMterpAsmInstructionStart = .L_op_nop SET_VREG s0, w4 // vA<- d0 GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_int_to_byte: /* 0x8d */ -/* File: arm64/op_int_to_byte.S */ -/* File: arm64/unop.S */ /* * Generic 32-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result = op w0". @@ -3558,12 +3156,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 8-9 instructions */ - /* ------------------------------ */ .balign 128 .L_op_int_to_char: /* 0x8e */ -/* File: arm64/op_int_to_char.S */ -/* File: arm64/unop.S */ /* * Generic 32-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result = op w0". @@ -3583,12 +3178,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 8-9 instructions */ - /* ------------------------------ */ .balign 128 .L_op_int_to_short: /* 0x8f */ -/* File: arm64/op_int_to_short.S */ -/* File: arm64/unop.S */ /* * Generic 32-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result = op w0". @@ -3608,12 +3200,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 8-9 instructions */ - /* ------------------------------ */ .balign 128 .L_op_add_int: /* 0x90 */ -/* File: arm64/op_add_int.S */ -/* File: arm64/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = w0 op w1". @@ -3647,12 +3236,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 11-14 instructions */ - /* ------------------------------ */ .balign 128 .L_op_sub_int: /* 0x91 */ -/* File: arm64/op_sub_int.S */ -/* File: arm64/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = w0 op w1". @@ -3686,13 +3272,10 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 11-14 instructions */ - /* ------------------------------ */ .balign 128 .L_op_mul_int: /* 0x92 */ -/* File: arm64/op_mul_int.S */ /* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */ -/* File: arm64/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = w0 op w1". @@ -3726,12 +3309,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 11-14 instructions */ - /* ------------------------------ */ .balign 128 .L_op_div_int: /* 0x93 */ -/* File: arm64/op_div_int.S */ -/* File: arm64/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = w0 op w1". @@ -3765,12 +3345,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 11-14 instructions */ - /* ------------------------------ */ .balign 128 .L_op_rem_int: /* 0x94 */ -/* File: arm64/op_rem_int.S */ -/* File: arm64/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = w0 op w1". @@ -3804,12 +3381,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 11-14 instructions */ - /* ------------------------------ */ .balign 128 .L_op_and_int: /* 0x95 */ -/* File: arm64/op_and_int.S */ -/* File: arm64/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = w0 op w1". @@ -3843,12 +3417,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 11-14 instructions */ - /* ------------------------------ */ .balign 128 .L_op_or_int: /* 0x96 */ -/* File: arm64/op_or_int.S */ -/* File: arm64/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = w0 op w1". @@ -3882,12 +3453,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 11-14 instructions */ - /* ------------------------------ */ .balign 128 .L_op_xor_int: /* 0x97 */ -/* File: arm64/op_xor_int.S */ -/* File: arm64/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = w0 op w1". @@ -3921,12 +3489,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 11-14 instructions */ - /* ------------------------------ */ .balign 128 .L_op_shl_int: /* 0x98 */ -/* File: arm64/op_shl_int.S */ -/* File: arm64/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = w0 op w1". @@ -3960,12 +3525,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 11-14 instructions */ - /* ------------------------------ */ .balign 128 .L_op_shr_int: /* 0x99 */ -/* File: arm64/op_shr_int.S */ -/* File: arm64/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = w0 op w1". @@ -3999,12 +3561,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 11-14 instructions */ - /* ------------------------------ */ .balign 128 .L_op_ushr_int: /* 0x9a */ -/* File: arm64/op_ushr_int.S */ -/* File: arm64/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = w0 op w1". @@ -4038,12 +3597,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 11-14 instructions */ - /* ------------------------------ */ .balign 128 .L_op_add_long: /* 0x9b */ -/* File: arm64/op_add_long.S */ -/* File: arm64/binopWide.S */ /* * Generic 64-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = x1 op x2". @@ -4074,12 +3630,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 11-14 instructions */ - /* ------------------------------ */ .balign 128 .L_op_sub_long: /* 0x9c */ -/* File: arm64/op_sub_long.S */ -/* File: arm64/binopWide.S */ /* * Generic 64-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = x1 op x2". @@ -4110,12 +3663,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 11-14 instructions */ - /* ------------------------------ */ .balign 128 .L_op_mul_long: /* 0x9d */ -/* File: arm64/op_mul_long.S */ -/* File: arm64/binopWide.S */ /* * Generic 64-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = x1 op x2". @@ -4146,12 +3696,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 11-14 instructions */ - /* ------------------------------ */ .balign 128 .L_op_div_long: /* 0x9e */ -/* File: arm64/op_div_long.S */ -/* File: arm64/binopWide.S */ /* * Generic 64-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = x1 op x2". @@ -4182,12 +3729,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 11-14 instructions */ - /* ------------------------------ */ .balign 128 .L_op_rem_long: /* 0x9f */ -/* File: arm64/op_rem_long.S */ -/* File: arm64/binopWide.S */ /* * Generic 64-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = x1 op x2". @@ -4218,12 +3762,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 11-14 instructions */ - /* ------------------------------ */ .balign 128 .L_op_and_long: /* 0xa0 */ -/* File: arm64/op_and_long.S */ -/* File: arm64/binopWide.S */ /* * Generic 64-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = x1 op x2". @@ -4254,12 +3795,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 11-14 instructions */ - /* ------------------------------ */ .balign 128 .L_op_or_long: /* 0xa1 */ -/* File: arm64/op_or_long.S */ -/* File: arm64/binopWide.S */ /* * Generic 64-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = x1 op x2". @@ -4290,12 +3828,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 11-14 instructions */ - /* ------------------------------ */ .balign 128 .L_op_xor_long: /* 0xa2 */ -/* File: arm64/op_xor_long.S */ -/* File: arm64/binopWide.S */ /* * Generic 64-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = x1 op x2". @@ -4326,12 +3861,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 11-14 instructions */ - /* ------------------------------ */ .balign 128 .L_op_shl_long: /* 0xa3 */ -/* File: arm64/op_shl_long.S */ -/* File: arm64/shiftWide.S */ /* * 64-bit shift operation. * @@ -4351,12 +3883,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 11-14 instructions */ - /* ------------------------------ */ .balign 128 .L_op_shr_long: /* 0xa4 */ -/* File: arm64/op_shr_long.S */ -/* File: arm64/shiftWide.S */ /* * 64-bit shift operation. * @@ -4376,12 +3905,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 11-14 instructions */ - /* ------------------------------ */ .balign 128 .L_op_ushr_long: /* 0xa5 */ -/* File: arm64/op_ushr_long.S */ -/* File: arm64/shiftWide.S */ /* * 64-bit shift operation. * @@ -4401,12 +3927,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 11-14 instructions */ - /* ------------------------------ */ .balign 128 .L_op_add_float: /* 0xa6 */ -/* File: arm64/op_add_float.S */ -/* File: arm64/fbinop.S */ /*: * Generic 32-bit floating-point operation. * @@ -4426,12 +3949,9 @@ artMterpAsmInstructionStart = .L_op_nop SET_VREG s0, w1 GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_sub_float: /* 0xa7 */ -/* File: arm64/op_sub_float.S */ -/* File: arm64/fbinop.S */ /*: * Generic 32-bit floating-point operation. * @@ -4451,12 +3971,9 @@ artMterpAsmInstructionStart = .L_op_nop SET_VREG s0, w1 GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_mul_float: /* 0xa8 */ -/* File: arm64/op_mul_float.S */ -/* File: arm64/fbinop.S */ /*: * Generic 32-bit floating-point operation. * @@ -4476,12 +3993,9 @@ artMterpAsmInstructionStart = .L_op_nop SET_VREG s0, w1 GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_div_float: /* 0xa9 */ -/* File: arm64/op_div_float.S */ -/* File: arm64/fbinop.S */ /*: * Generic 32-bit floating-point operation. * @@ -4501,13 +4015,10 @@ artMterpAsmInstructionStart = .L_op_nop SET_VREG s0, w1 GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_rem_float: /* 0xaa */ -/* File: arm64/op_rem_float.S */ /* EABI doesn't define a float remainder function, but libm does */ -/* File: arm64/fbinop.S */ /*: * Generic 32-bit floating-point operation. * @@ -4527,12 +4038,9 @@ artMterpAsmInstructionStart = .L_op_nop SET_VREG s0, w1 GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_add_double: /* 0xab */ -/* File: arm64/op_add_double.S */ -/* File: arm64/binopWide.S */ /* * Generic 64-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = x1 op x2". @@ -4563,12 +4071,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 11-14 instructions */ - /* ------------------------------ */ .balign 128 .L_op_sub_double: /* 0xac */ -/* File: arm64/op_sub_double.S */ -/* File: arm64/binopWide.S */ /* * Generic 64-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = x1 op x2". @@ -4599,12 +4104,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 11-14 instructions */ - /* ------------------------------ */ .balign 128 .L_op_mul_double: /* 0xad */ -/* File: arm64/op_mul_double.S */ -/* File: arm64/binopWide.S */ /* * Generic 64-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = x1 op x2". @@ -4635,12 +4137,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 11-14 instructions */ - /* ------------------------------ */ .balign 128 .L_op_div_double: /* 0xae */ -/* File: arm64/op_div_double.S */ -/* File: arm64/binopWide.S */ /* * Generic 64-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = x1 op x2". @@ -4671,11 +4170,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 11-14 instructions */ - /* ------------------------------ */ .balign 128 .L_op_rem_double: /* 0xaf */ -/* File: arm64/op_rem_double.S */ /* rem vAA, vBB, vCC */ FETCH w0, 1 // w0<- CCBB lsr w2, w0, #8 // w2<- CC @@ -4693,8 +4190,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_add_int_2addr: /* 0xb0 */ -/* File: arm64/op_add_int_2addr.S */ -/* File: arm64/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = w0 op w1". @@ -4725,12 +4220,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_sub_int_2addr: /* 0xb1 */ -/* File: arm64/op_sub_int_2addr.S */ -/* File: arm64/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = w0 op w1". @@ -4761,13 +4253,10 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_mul_int_2addr: /* 0xb2 */ -/* File: arm64/op_mul_int_2addr.S */ /* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */ -/* File: arm64/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = w0 op w1". @@ -4798,12 +4287,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_div_int_2addr: /* 0xb3 */ -/* File: arm64/op_div_int_2addr.S */ -/* File: arm64/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = w0 op w1". @@ -4834,12 +4320,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_rem_int_2addr: /* 0xb4 */ -/* File: arm64/op_rem_int_2addr.S */ -/* File: arm64/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = w0 op w1". @@ -4870,12 +4353,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_and_int_2addr: /* 0xb5 */ -/* File: arm64/op_and_int_2addr.S */ -/* File: arm64/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = w0 op w1". @@ -4906,12 +4386,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_or_int_2addr: /* 0xb6 */ -/* File: arm64/op_or_int_2addr.S */ -/* File: arm64/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = w0 op w1". @@ -4942,12 +4419,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_xor_int_2addr: /* 0xb7 */ -/* File: arm64/op_xor_int_2addr.S */ -/* File: arm64/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = w0 op w1". @@ -4978,12 +4452,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_shl_int_2addr: /* 0xb8 */ -/* File: arm64/op_shl_int_2addr.S */ -/* File: arm64/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = w0 op w1". @@ -5014,12 +4485,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_shr_int_2addr: /* 0xb9 */ -/* File: arm64/op_shr_int_2addr.S */ -/* File: arm64/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = w0 op w1". @@ -5050,12 +4518,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_ushr_int_2addr: /* 0xba */ -/* File: arm64/op_ushr_int_2addr.S */ -/* File: arm64/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = w0 op w1". @@ -5086,12 +4551,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_add_long_2addr: /* 0xbb */ -/* File: arm64/op_add_long_2addr.S */ -/* File: arm64/binopWide2addr.S */ /* * Generic 64-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "x0 = x0 op x1". @@ -5121,12 +4583,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_sub_long_2addr: /* 0xbc */ -/* File: arm64/op_sub_long_2addr.S */ -/* File: arm64/binopWide2addr.S */ /* * Generic 64-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "x0 = x0 op x1". @@ -5156,12 +4615,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_mul_long_2addr: /* 0xbd */ -/* File: arm64/op_mul_long_2addr.S */ -/* File: arm64/binopWide2addr.S */ /* * Generic 64-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "x0 = x0 op x1". @@ -5191,12 +4647,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_div_long_2addr: /* 0xbe */ -/* File: arm64/op_div_long_2addr.S */ -/* File: arm64/binopWide2addr.S */ /* * Generic 64-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "x0 = x0 op x1". @@ -5226,12 +4679,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_rem_long_2addr: /* 0xbf */ -/* File: arm64/op_rem_long_2addr.S */ -/* File: arm64/binopWide2addr.S */ /* * Generic 64-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "x0 = x0 op x1". @@ -5261,12 +4711,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_and_long_2addr: /* 0xc0 */ -/* File: arm64/op_and_long_2addr.S */ -/* File: arm64/binopWide2addr.S */ /* * Generic 64-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "x0 = x0 op x1". @@ -5296,12 +4743,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_or_long_2addr: /* 0xc1 */ -/* File: arm64/op_or_long_2addr.S */ -/* File: arm64/binopWide2addr.S */ /* * Generic 64-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "x0 = x0 op x1". @@ -5331,12 +4775,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_xor_long_2addr: /* 0xc2 */ -/* File: arm64/op_xor_long_2addr.S */ -/* File: arm64/binopWide2addr.S */ /* * Generic 64-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "x0 = x0 op x1". @@ -5366,12 +4807,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_shl_long_2addr: /* 0xc3 */ -/* File: arm64/op_shl_long_2addr.S */ -/* File: arm64/shiftWide2addr.S */ /* * Generic 64-bit shift operation. */ @@ -5387,12 +4825,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_shr_long_2addr: /* 0xc4 */ -/* File: arm64/op_shr_long_2addr.S */ -/* File: arm64/shiftWide2addr.S */ /* * Generic 64-bit shift operation. */ @@ -5408,12 +4843,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_ushr_long_2addr: /* 0xc5 */ -/* File: arm64/op_ushr_long_2addr.S */ -/* File: arm64/shiftWide2addr.S */ /* * Generic 64-bit shift operation. */ @@ -5429,12 +4861,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_add_float_2addr: /* 0xc6 */ -/* File: arm64/op_add_float_2addr.S */ -/* File: arm64/fbinop2addr.S */ /* * Generic 32-bit floating point "/2addr" binary operation. Provide * an "instr" line that specifies an instruction that performs @@ -5453,12 +4882,9 @@ artMterpAsmInstructionStart = .L_op_nop SET_VREG s2, w9 GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_sub_float_2addr: /* 0xc7 */ -/* File: arm64/op_sub_float_2addr.S */ -/* File: arm64/fbinop2addr.S */ /* * Generic 32-bit floating point "/2addr" binary operation. Provide * an "instr" line that specifies an instruction that performs @@ -5477,12 +4903,9 @@ artMterpAsmInstructionStart = .L_op_nop SET_VREG s2, w9 GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_mul_float_2addr: /* 0xc8 */ -/* File: arm64/op_mul_float_2addr.S */ -/* File: arm64/fbinop2addr.S */ /* * Generic 32-bit floating point "/2addr" binary operation. Provide * an "instr" line that specifies an instruction that performs @@ -5501,12 +4924,9 @@ artMterpAsmInstructionStart = .L_op_nop SET_VREG s2, w9 GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_div_float_2addr: /* 0xc9 */ -/* File: arm64/op_div_float_2addr.S */ -/* File: arm64/fbinop2addr.S */ /* * Generic 32-bit floating point "/2addr" binary operation. Provide * an "instr" line that specifies an instruction that performs @@ -5525,11 +4945,9 @@ artMterpAsmInstructionStart = .L_op_nop SET_VREG s2, w9 GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_rem_float_2addr: /* 0xca */ -/* File: arm64/op_rem_float_2addr.S */ /* rem vA, vB */ lsr w3, wINST, #12 // w3<- B ubfx w9, wINST, #8, #4 // w9<- A @@ -5545,8 +4963,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_add_double_2addr: /* 0xcb */ -/* File: arm64/op_add_double_2addr.S */ -/* File: arm64/binopWide2addr.S */ /* * Generic 64-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "x0 = x0 op x1". @@ -5576,12 +4992,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_sub_double_2addr: /* 0xcc */ -/* File: arm64/op_sub_double_2addr.S */ -/* File: arm64/binopWide2addr.S */ /* * Generic 64-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "x0 = x0 op x1". @@ -5611,12 +5024,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_mul_double_2addr: /* 0xcd */ -/* File: arm64/op_mul_double_2addr.S */ -/* File: arm64/binopWide2addr.S */ /* * Generic 64-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "x0 = x0 op x1". @@ -5646,12 +5056,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_div_double_2addr: /* 0xce */ -/* File: arm64/op_div_double_2addr.S */ -/* File: arm64/binopWide2addr.S */ /* * Generic 64-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "x0 = x0 op x1". @@ -5681,11 +5088,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_rem_double_2addr: /* 0xcf */ -/* File: arm64/op_rem_double_2addr.S */ /* rem vA, vB */ lsr w1, wINST, #12 // w1<- B ubfx w2, wINST, #8, #4 // w2<- A @@ -5702,8 +5107,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_add_int_lit16: /* 0xd0 */ -/* File: arm64/op_add_int_lit16.S */ -/* File: arm64/binopLit16.S */ /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = w0 op w1". @@ -5732,13 +5135,10 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_rsub_int: /* 0xd1 */ -/* File: arm64/op_rsub_int.S */ /* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ -/* File: arm64/binopLit16.S */ /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = w0 op w1". @@ -5767,13 +5167,10 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_mul_int_lit16: /* 0xd2 */ -/* File: arm64/op_mul_int_lit16.S */ /* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */ -/* File: arm64/binopLit16.S */ /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = w0 op w1". @@ -5802,12 +5199,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_div_int_lit16: /* 0xd3 */ -/* File: arm64/op_div_int_lit16.S */ -/* File: arm64/binopLit16.S */ /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = w0 op w1". @@ -5836,12 +5230,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_rem_int_lit16: /* 0xd4 */ -/* File: arm64/op_rem_int_lit16.S */ -/* File: arm64/binopLit16.S */ /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = w0 op w1". @@ -5870,12 +5261,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_and_int_lit16: /* 0xd5 */ -/* File: arm64/op_and_int_lit16.S */ -/* File: arm64/binopLit16.S */ /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = w0 op w1". @@ -5904,12 +5292,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_or_int_lit16: /* 0xd6 */ -/* File: arm64/op_or_int_lit16.S */ -/* File: arm64/binopLit16.S */ /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = w0 op w1". @@ -5938,12 +5323,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_xor_int_lit16: /* 0xd7 */ -/* File: arm64/op_xor_int_lit16.S */ -/* File: arm64/binopLit16.S */ /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = w0 op w1". @@ -5972,12 +5354,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-13 instructions */ - /* ------------------------------ */ .balign 128 .L_op_add_int_lit8: /* 0xd8 */ -/* File: arm64/op_add_int_lit8.S */ -/* File: arm64/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = w0 op w1". @@ -6012,12 +5391,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-12 instructions */ - /* ------------------------------ */ .balign 128 .L_op_rsub_int_lit8: /* 0xd9 */ -/* File: arm64/op_rsub_int_lit8.S */ -/* File: arm64/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = w0 op w1". @@ -6052,13 +5428,10 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-12 instructions */ - /* ------------------------------ */ .balign 128 .L_op_mul_int_lit8: /* 0xda */ -/* File: arm64/op_mul_int_lit8.S */ /* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */ -/* File: arm64/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = w0 op w1". @@ -6093,12 +5466,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-12 instructions */ - /* ------------------------------ */ .balign 128 .L_op_div_int_lit8: /* 0xdb */ -/* File: arm64/op_div_int_lit8.S */ -/* File: arm64/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = w0 op w1". @@ -6133,12 +5503,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-12 instructions */ - /* ------------------------------ */ .balign 128 .L_op_rem_int_lit8: /* 0xdc */ -/* File: arm64/op_rem_int_lit8.S */ -/* File: arm64/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = w0 op w1". @@ -6173,12 +5540,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-12 instructions */ - /* ------------------------------ */ .balign 128 .L_op_and_int_lit8: /* 0xdd */ -/* File: arm64/op_and_int_lit8.S */ -/* File: arm64/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = w0 op w1". @@ -6213,12 +5577,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-12 instructions */ - /* ------------------------------ */ .balign 128 .L_op_or_int_lit8: /* 0xde */ -/* File: arm64/op_or_int_lit8.S */ -/* File: arm64/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = w0 op w1". @@ -6253,12 +5614,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-12 instructions */ - /* ------------------------------ */ .balign 128 .L_op_xor_int_lit8: /* 0xdf */ -/* File: arm64/op_xor_int_lit8.S */ -/* File: arm64/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = w0 op w1". @@ -6293,12 +5651,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-12 instructions */ - /* ------------------------------ */ .balign 128 .L_op_shl_int_lit8: /* 0xe0 */ -/* File: arm64/op_shl_int_lit8.S */ -/* File: arm64/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = w0 op w1". @@ -6333,12 +5688,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-12 instructions */ - /* ------------------------------ */ .balign 128 .L_op_shr_int_lit8: /* 0xe1 */ -/* File: arm64/op_shr_int_lit8.S */ -/* File: arm64/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = w0 op w1". @@ -6373,12 +5725,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-12 instructions */ - /* ------------------------------ */ .balign 128 .L_op_ushr_int_lit8: /* 0xe2 */ -/* File: arm64/op_ushr_int_lit8.S */ -/* File: arm64/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = w0 op w1". @@ -6413,11 +5762,9 @@ artMterpAsmInstructionStart = .L_op_nop GOTO_OPCODE ip // jump to next instruction /* 10-12 instructions */ - /* ------------------------------ */ .balign 128 .L_op_iget_quick: /* 0xe3 */ -/* File: arm64/op_iget_quick.S */ /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ /* op vA, vB, offset//CCCC */ lsr w2, wINST, #12 // w2<- B @@ -6435,7 +5782,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_iget_wide_quick: /* 0xe4 */ -/* File: arm64/op_iget_wide_quick.S */ /* iget-wide-quick vA, vB, offset//CCCC */ lsr w2, wINST, #12 // w2<- B FETCH w4, 1 // w4<- field byte offset @@ -6451,7 +5797,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_iget_object_quick: /* 0xe5 */ -/* File: arm64/op_iget_object_quick.S */ /* For: iget-object-quick */ /* op vA, vB, offset//CCCC */ lsr w2, wINST, #12 // w2<- B @@ -6471,7 +5816,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_iput_quick: /* 0xe6 */ -/* File: arm64/op_iput_quick.S */ /* For: iput-quick, iput-object-quick */ /* op vA, vB, offset//CCCC */ lsr w2, wINST, #12 // w2<- B @@ -6488,7 +5832,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_iput_wide_quick: /* 0xe7 */ -/* File: arm64/op_iput_wide_quick.S */ /* iput-wide-quick vA, vB, offset//CCCC */ lsr w2, wINST, #12 // w2<- B FETCH w3, 1 // w3<- field byte offset @@ -6504,7 +5847,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_iput_object_quick: /* 0xe8 */ -/* File: arm64/op_iput_object_quick.S */ EXPORT_PC add x0, xFP, #OFF_FP_SHADOWFRAME mov x1, xPC @@ -6518,8 +5860,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_invoke_virtual_quick: /* 0xe9 */ -/* File: arm64/op_invoke_virtual_quick.S */ -/* File: arm64/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -6539,13 +5879,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip GOTO_OPCODE ip - - /* ------------------------------ */ .balign 128 .L_op_invoke_virtual_range_quick: /* 0xea */ -/* File: arm64/op_invoke_virtual_range_quick.S */ -/* File: arm64/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -6565,13 +5901,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip GOTO_OPCODE ip - - /* ------------------------------ */ .balign 128 .L_op_iput_boolean_quick: /* 0xeb */ -/* File: arm64/op_iput_boolean_quick.S */ -/* File: arm64/op_iput_quick.S */ /* For: iput-quick, iput-object-quick */ /* op vA, vB, offset//CCCC */ lsr w2, wINST, #12 // w2<- B @@ -6585,12 +5917,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from rINST GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_iput_byte_quick: /* 0xec */ -/* File: arm64/op_iput_byte_quick.S */ -/* File: arm64/op_iput_quick.S */ /* For: iput-quick, iput-object-quick */ /* op vA, vB, offset//CCCC */ lsr w2, wINST, #12 // w2<- B @@ -6604,12 +5933,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from rINST GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_iput_char_quick: /* 0xed */ -/* File: arm64/op_iput_char_quick.S */ -/* File: arm64/op_iput_quick.S */ /* For: iput-quick, iput-object-quick */ /* op vA, vB, offset//CCCC */ lsr w2, wINST, #12 // w2<- B @@ -6623,12 +5949,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from rINST GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_iput_short_quick: /* 0xee */ -/* File: arm64/op_iput_short_quick.S */ -/* File: arm64/op_iput_quick.S */ /* For: iput-quick, iput-object-quick */ /* op vA, vB, offset//CCCC */ lsr w2, wINST, #12 // w2<- B @@ -6642,12 +5965,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from rINST GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_iget_boolean_quick: /* 0xef */ -/* File: arm64/op_iget_boolean_quick.S */ -/* File: arm64/op_iget_quick.S */ /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ /* op vA, vB, offset//CCCC */ lsr w2, wINST, #12 // w2<- B @@ -6662,12 +5982,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from rINST GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_iget_byte_quick: /* 0xf0 */ -/* File: arm64/op_iget_byte_quick.S */ -/* File: arm64/op_iget_quick.S */ /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ /* op vA, vB, offset//CCCC */ lsr w2, wINST, #12 // w2<- B @@ -6682,12 +5999,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from rINST GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_iget_char_quick: /* 0xf1 */ -/* File: arm64/op_iget_char_quick.S */ -/* File: arm64/op_iget_quick.S */ /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ /* op vA, vB, offset//CCCC */ lsr w2, wINST, #12 // w2<- B @@ -6702,12 +6016,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from rINST GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_iget_short_quick: /* 0xf2 */ -/* File: arm64/op_iget_short_quick.S */ -/* File: arm64/op_iget_quick.S */ /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ /* op vA, vB, offset//CCCC */ lsr w2, wINST, #12 // w2<- B @@ -6722,89 +6033,65 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from rINST GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_unused_f3: /* 0xf3 */ -/* File: arm64/op_unused_f3.S */ -/* File: arm64/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_f4: /* 0xf4 */ -/* File: arm64/op_unused_f4.S */ -/* File: arm64/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_f5: /* 0xf5 */ -/* File: arm64/op_unused_f5.S */ -/* File: arm64/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_f6: /* 0xf6 */ -/* File: arm64/op_unused_f6.S */ -/* File: arm64/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_f7: /* 0xf7 */ -/* File: arm64/op_unused_f7.S */ -/* File: arm64/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_f8: /* 0xf8 */ -/* File: arm64/op_unused_f8.S */ -/* File: arm64/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_f9: /* 0xf9 */ -/* File: arm64/op_unused_f9.S */ -/* File: arm64/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_invoke_polymorphic: /* 0xfa */ -/* File: arm64/op_invoke_polymorphic.S */ -/* File: arm64/invoke_polymorphic.S */ /* * invoke-polymorphic handler wrapper. */ @@ -6824,12 +6111,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip GOTO_OPCODE ip - /* ------------------------------ */ .balign 128 .L_op_invoke_polymorphic_range: /* 0xfb */ -/* File: arm64/op_invoke_polymorphic_range.S */ -/* File: arm64/invoke_polymorphic.S */ /* * invoke-polymorphic handler wrapper. */ @@ -6849,12 +6133,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip GOTO_OPCODE ip - /* ------------------------------ */ .balign 128 .L_op_invoke_custom: /* 0xfc */ -/* File: arm64/op_invoke_custom.S */ -/* File: arm64/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -6874,13 +6155,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip GOTO_OPCODE ip - - /* ------------------------------ */ .balign 128 .L_op_invoke_custom_range: /* 0xfd */ -/* File: arm64/op_invoke_custom_range.S */ -/* File: arm64/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -6900,13 +6177,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip GOTO_OPCODE ip - - /* ------------------------------ */ .balign 128 .L_op_const_method_handle: /* 0xfe */ -/* File: arm64/op_const_method_handle.S */ -/* File: arm64/const.S */ /* const/class vAA, type@BBBB */ /* const/method-handle vAA, method_handle@BBBB */ /* const/method-type vAA, proto@BBBB */ @@ -6924,12 +6197,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from rINST GOTO_OPCODE ip // jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_const_method_type: /* 0xff */ -/* File: arm64/op_const_method_type.S */ -/* File: arm64/const.S */ /* const/class vAA, type@BBBB */ /* const/method-handle vAA, method_handle@BBBB */ /* const/method-type vAA, proto@BBBB */ @@ -6947,23 +6217,13 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE ip // extract opcode from rINST GOTO_OPCODE ip // jump to next instruction - .balign 128 -/* File: arm64/instruction_end.S */ .type artMterpAsmInstructionEnd, #object .hidden artMterpAsmInstructionEnd .global artMterpAsmInstructionEnd artMterpAsmInstructionEnd: - -/* - * =========================================================================== - * Sister implementations - * =========================================================================== - */ -/* File: arm64/instruction_start_sister.S */ - .type artMterpAsmSisterStart, #object .hidden artMterpAsmSisterStart .global artMterpAsmSisterStart @@ -6971,21 +6231,16 @@ artMterpAsmInstructionEnd: .balign 4 artMterpAsmSisterStart: -/* File: arm64/instruction_end_sister.S */ - .type artMterpAsmSisterEnd, #object .hidden artMterpAsmSisterEnd .global artMterpAsmSisterEnd artMterpAsmSisterEnd: - -/* File: arm64/footer.S */ /* * =========================================================================== * Common subroutines and data * =========================================================================== */ - /* * We've detected a condition that will result in an exception, but the exception * has not yet been thrown. Just bail out to the reference interpreter to deal with it. @@ -7188,7 +6443,6 @@ MterpCommonTakenBranchNoFlags: GET_INST_OPCODE ip // extract opcode from wINST GOTO_OPCODE ip // jump to next instruction - /* * Check for suspend check request. Assumes wINST already loaded, xPC advanced and * still needs to get the opcode and branch to it, and flags are in lr. @@ -7285,19 +6539,14 @@ MterpProfileActive: RESTORE_TWO_REGS_DECREASE_FRAME xPROFILE, x27, 80 ret - -/* File: arm64/instruction_start_alt.S */ - .type artMterpAsmAltInstructionStart, #object .hidden artMterpAsmAltInstructionStart .global artMterpAsmAltInstructionStart artMterpAsmAltInstructionStart = .L_ALT_op_nop .text - /* ------------------------------ */ .balign 128 .L_ALT_op_nop: /* 0x00 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7314,7 +6563,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move: /* 0x01 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7331,7 +6579,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_from16: /* 0x02 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7348,7 +6595,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_16: /* 0x03 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7365,7 +6611,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_wide: /* 0x04 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7382,7 +6627,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_wide_from16: /* 0x05 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7399,7 +6643,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_wide_16: /* 0x06 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7416,7 +6659,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_object: /* 0x07 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7433,7 +6675,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_object_from16: /* 0x08 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7450,7 +6691,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_object_16: /* 0x09 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7467,7 +6707,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_result: /* 0x0a */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7484,7 +6723,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_result_wide: /* 0x0b */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7501,7 +6739,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_result_object: /* 0x0c */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7518,7 +6755,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_exception: /* 0x0d */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7535,7 +6771,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_return_void: /* 0x0e */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7552,7 +6787,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_return: /* 0x0f */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7569,7 +6803,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_return_wide: /* 0x10 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7586,7 +6819,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_return_object: /* 0x11 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7603,7 +6835,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_4: /* 0x12 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7620,7 +6851,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_16: /* 0x13 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7637,7 +6867,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const: /* 0x14 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7654,7 +6883,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_high16: /* 0x15 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7671,7 +6899,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_wide_16: /* 0x16 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7688,7 +6915,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_wide_32: /* 0x17 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7705,7 +6931,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_wide: /* 0x18 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7722,7 +6947,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_wide_high16: /* 0x19 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7739,7 +6963,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_string: /* 0x1a */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7756,7 +6979,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_string_jumbo: /* 0x1b */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7773,7 +6995,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_class: /* 0x1c */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7790,7 +7011,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_monitor_enter: /* 0x1d */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7807,7 +7027,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_monitor_exit: /* 0x1e */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7824,7 +7043,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_check_cast: /* 0x1f */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7841,7 +7059,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_instance_of: /* 0x20 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7858,7 +7075,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_array_length: /* 0x21 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7875,7 +7091,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_new_instance: /* 0x22 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7892,7 +7107,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_new_array: /* 0x23 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7909,7 +7123,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_filled_new_array: /* 0x24 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7926,7 +7139,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_filled_new_array_range: /* 0x25 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7943,7 +7155,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_fill_array_data: /* 0x26 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7960,7 +7171,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_throw: /* 0x27 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7977,7 +7187,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_goto: /* 0x28 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7994,7 +7203,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_goto_16: /* 0x29 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8011,7 +7219,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_goto_32: /* 0x2a */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8028,7 +7235,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_packed_switch: /* 0x2b */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8045,7 +7251,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sparse_switch: /* 0x2c */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8062,7 +7267,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_cmpl_float: /* 0x2d */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8079,7 +7283,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_cmpg_float: /* 0x2e */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8096,7 +7299,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_cmpl_double: /* 0x2f */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8113,7 +7315,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_cmpg_double: /* 0x30 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8130,7 +7331,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_cmp_long: /* 0x31 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8147,7 +7347,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_eq: /* 0x32 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8164,7 +7363,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_ne: /* 0x33 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8181,7 +7379,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_lt: /* 0x34 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8198,7 +7395,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_ge: /* 0x35 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8215,7 +7411,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_gt: /* 0x36 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8232,7 +7427,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_le: /* 0x37 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8249,7 +7443,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_eqz: /* 0x38 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8266,7 +7459,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_nez: /* 0x39 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8283,7 +7475,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_ltz: /* 0x3a */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8300,7 +7491,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_gez: /* 0x3b */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8317,7 +7507,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_gtz: /* 0x3c */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8334,7 +7523,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_lez: /* 0x3d */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8351,7 +7539,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_3e: /* 0x3e */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8368,7 +7555,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_3f: /* 0x3f */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8385,7 +7571,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_40: /* 0x40 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8402,7 +7587,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_41: /* 0x41 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8419,7 +7603,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_42: /* 0x42 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8436,7 +7619,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_43: /* 0x43 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8453,7 +7635,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aget: /* 0x44 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8470,7 +7651,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aget_wide: /* 0x45 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8487,7 +7667,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aget_object: /* 0x46 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8504,7 +7683,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aget_boolean: /* 0x47 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8521,7 +7699,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aget_byte: /* 0x48 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8538,7 +7715,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aget_char: /* 0x49 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8555,7 +7731,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aget_short: /* 0x4a */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8572,7 +7747,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aput: /* 0x4b */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8589,7 +7763,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aput_wide: /* 0x4c */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8606,7 +7779,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aput_object: /* 0x4d */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8623,7 +7795,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aput_boolean: /* 0x4e */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8640,7 +7811,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aput_byte: /* 0x4f */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8657,7 +7827,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aput_char: /* 0x50 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8674,7 +7843,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aput_short: /* 0x51 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8691,7 +7859,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget: /* 0x52 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8708,7 +7875,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_wide: /* 0x53 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8725,7 +7891,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_object: /* 0x54 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8742,7 +7907,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_boolean: /* 0x55 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8759,7 +7923,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_byte: /* 0x56 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8776,7 +7939,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_char: /* 0x57 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8793,7 +7955,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_short: /* 0x58 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8810,7 +7971,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput: /* 0x59 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8827,7 +7987,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_wide: /* 0x5a */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8844,7 +8003,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_object: /* 0x5b */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8861,7 +8019,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_boolean: /* 0x5c */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8878,7 +8035,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_byte: /* 0x5d */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8895,7 +8051,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_char: /* 0x5e */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8912,7 +8067,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_short: /* 0x5f */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8929,7 +8083,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sget: /* 0x60 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8946,7 +8099,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sget_wide: /* 0x61 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8963,7 +8115,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sget_object: /* 0x62 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8980,7 +8131,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sget_boolean: /* 0x63 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8997,7 +8147,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sget_byte: /* 0x64 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9014,7 +8163,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sget_char: /* 0x65 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9031,7 +8179,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sget_short: /* 0x66 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9048,7 +8195,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sput: /* 0x67 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9065,7 +8211,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sput_wide: /* 0x68 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9082,7 +8227,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sput_object: /* 0x69 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9099,7 +8243,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sput_boolean: /* 0x6a */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9116,7 +8259,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sput_byte: /* 0x6b */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9133,7 +8275,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sput_char: /* 0x6c */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9150,7 +8291,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sput_short: /* 0x6d */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9167,7 +8307,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_virtual: /* 0x6e */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9184,7 +8323,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_super: /* 0x6f */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9201,7 +8339,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_direct: /* 0x70 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9218,7 +8355,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_static: /* 0x71 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9235,7 +8371,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_interface: /* 0x72 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9252,7 +8387,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_return_void_no_barrier: /* 0x73 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9269,7 +8403,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_virtual_range: /* 0x74 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9286,7 +8419,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_super_range: /* 0x75 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9303,7 +8435,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_direct_range: /* 0x76 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9320,7 +8451,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_static_range: /* 0x77 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9337,7 +8467,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_interface_range: /* 0x78 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9354,7 +8483,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_79: /* 0x79 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9371,7 +8499,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_7a: /* 0x7a */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9388,7 +8515,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_neg_int: /* 0x7b */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9405,7 +8531,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_not_int: /* 0x7c */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9422,7 +8547,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_neg_long: /* 0x7d */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9439,7 +8563,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_not_long: /* 0x7e */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9456,7 +8579,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_neg_float: /* 0x7f */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9473,7 +8595,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_neg_double: /* 0x80 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9490,7 +8611,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_int_to_long: /* 0x81 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9507,7 +8627,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_int_to_float: /* 0x82 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9524,7 +8643,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_int_to_double: /* 0x83 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9541,7 +8659,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_long_to_int: /* 0x84 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9558,7 +8675,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_long_to_float: /* 0x85 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9575,7 +8691,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_long_to_double: /* 0x86 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9592,7 +8707,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_float_to_int: /* 0x87 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9609,7 +8723,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_float_to_long: /* 0x88 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9626,7 +8739,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_float_to_double: /* 0x89 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9643,7 +8755,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_double_to_int: /* 0x8a */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9660,7 +8771,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_double_to_long: /* 0x8b */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9677,7 +8787,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_double_to_float: /* 0x8c */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9694,7 +8803,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_int_to_byte: /* 0x8d */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9711,7 +8819,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_int_to_char: /* 0x8e */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9728,7 +8835,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_int_to_short: /* 0x8f */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9745,7 +8851,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_int: /* 0x90 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9762,7 +8867,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_int: /* 0x91 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9779,7 +8883,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_int: /* 0x92 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9796,7 +8899,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_int: /* 0x93 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9813,7 +8915,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_int: /* 0x94 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9830,7 +8931,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_and_int: /* 0x95 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9847,7 +8947,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_or_int: /* 0x96 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9864,7 +8963,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_xor_int: /* 0x97 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9881,7 +8979,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shl_int: /* 0x98 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9898,7 +8995,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shr_int: /* 0x99 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9915,7 +9011,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_ushr_int: /* 0x9a */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9932,7 +9027,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_long: /* 0x9b */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9949,7 +9043,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_long: /* 0x9c */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9966,7 +9059,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_long: /* 0x9d */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9983,7 +9075,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_long: /* 0x9e */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10000,7 +9091,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_long: /* 0x9f */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10017,7 +9107,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_and_long: /* 0xa0 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10034,7 +9123,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_or_long: /* 0xa1 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10051,7 +9139,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_xor_long: /* 0xa2 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10068,7 +9155,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shl_long: /* 0xa3 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10085,7 +9171,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shr_long: /* 0xa4 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10102,7 +9187,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_ushr_long: /* 0xa5 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10119,7 +9203,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_float: /* 0xa6 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10136,7 +9219,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_float: /* 0xa7 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10153,7 +9235,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_float: /* 0xa8 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10170,7 +9251,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_float: /* 0xa9 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10187,7 +9267,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_float: /* 0xaa */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10204,7 +9283,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_double: /* 0xab */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10221,7 +9299,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_double: /* 0xac */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10238,7 +9315,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_double: /* 0xad */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10255,7 +9331,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_double: /* 0xae */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10272,7 +9347,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_double: /* 0xaf */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10289,7 +9363,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_int_2addr: /* 0xb0 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10306,7 +9379,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_int_2addr: /* 0xb1 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10323,7 +9395,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_int_2addr: /* 0xb2 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10340,7 +9411,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_int_2addr: /* 0xb3 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10357,7 +9427,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_int_2addr: /* 0xb4 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10374,7 +9443,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_and_int_2addr: /* 0xb5 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10391,7 +9459,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_or_int_2addr: /* 0xb6 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10408,7 +9475,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_xor_int_2addr: /* 0xb7 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10425,7 +9491,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shl_int_2addr: /* 0xb8 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10442,7 +9507,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shr_int_2addr: /* 0xb9 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10459,7 +9523,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_ushr_int_2addr: /* 0xba */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10476,7 +9539,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_long_2addr: /* 0xbb */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10493,7 +9555,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_long_2addr: /* 0xbc */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10510,7 +9571,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_long_2addr: /* 0xbd */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10527,7 +9587,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_long_2addr: /* 0xbe */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10544,7 +9603,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_long_2addr: /* 0xbf */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10561,7 +9619,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_and_long_2addr: /* 0xc0 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10578,7 +9635,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_or_long_2addr: /* 0xc1 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10595,7 +9651,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_xor_long_2addr: /* 0xc2 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10612,7 +9667,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shl_long_2addr: /* 0xc3 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10629,7 +9683,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shr_long_2addr: /* 0xc4 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10646,7 +9699,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_ushr_long_2addr: /* 0xc5 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10663,7 +9715,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_float_2addr: /* 0xc6 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10680,7 +9731,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_float_2addr: /* 0xc7 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10697,7 +9747,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_float_2addr: /* 0xc8 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10714,7 +9763,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_float_2addr: /* 0xc9 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10731,7 +9779,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_float_2addr: /* 0xca */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10748,7 +9795,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_double_2addr: /* 0xcb */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10765,7 +9811,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_double_2addr: /* 0xcc */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10782,7 +9827,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_double_2addr: /* 0xcd */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10799,7 +9843,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_double_2addr: /* 0xce */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10816,7 +9859,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_double_2addr: /* 0xcf */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10833,7 +9875,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_int_lit16: /* 0xd0 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10850,7 +9891,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rsub_int: /* 0xd1 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10867,7 +9907,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_int_lit16: /* 0xd2 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10884,7 +9923,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_int_lit16: /* 0xd3 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10901,7 +9939,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_int_lit16: /* 0xd4 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10918,7 +9955,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_and_int_lit16: /* 0xd5 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10935,7 +9971,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_or_int_lit16: /* 0xd6 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10952,7 +9987,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_xor_int_lit16: /* 0xd7 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10969,7 +10003,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_int_lit8: /* 0xd8 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10986,7 +10019,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rsub_int_lit8: /* 0xd9 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11003,7 +10035,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_int_lit8: /* 0xda */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11020,7 +10051,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_int_lit8: /* 0xdb */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11037,7 +10067,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_int_lit8: /* 0xdc */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11054,7 +10083,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_and_int_lit8: /* 0xdd */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11071,7 +10099,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_or_int_lit8: /* 0xde */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11088,7 +10115,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_xor_int_lit8: /* 0xdf */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11105,7 +10131,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shl_int_lit8: /* 0xe0 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11122,7 +10147,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shr_int_lit8: /* 0xe1 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11139,7 +10163,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_ushr_int_lit8: /* 0xe2 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11156,7 +10179,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_quick: /* 0xe3 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11173,7 +10195,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_wide_quick: /* 0xe4 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11190,7 +10211,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_object_quick: /* 0xe5 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11207,7 +10227,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_quick: /* 0xe6 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11224,7 +10243,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_wide_quick: /* 0xe7 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11241,7 +10259,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_object_quick: /* 0xe8 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11258,7 +10275,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_virtual_quick: /* 0xe9 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11275,7 +10291,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_virtual_range_quick: /* 0xea */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11292,7 +10307,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_boolean_quick: /* 0xeb */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11309,7 +10323,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_byte_quick: /* 0xec */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11326,7 +10339,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_char_quick: /* 0xed */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11343,7 +10355,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_short_quick: /* 0xee */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11360,7 +10371,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_boolean_quick: /* 0xef */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11377,7 +10387,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_byte_quick: /* 0xf0 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11394,7 +10403,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_char_quick: /* 0xf1 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11411,7 +10419,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_short_quick: /* 0xf2 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11428,7 +10435,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_f3: /* 0xf3 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11445,7 +10451,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_f4: /* 0xf4 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11462,7 +10467,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_f5: /* 0xf5 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11479,7 +10483,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_f6: /* 0xf6 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11496,7 +10499,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_f7: /* 0xf7 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11513,7 +10515,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_f8: /* 0xf8 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11530,7 +10531,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_f9: /* 0xf9 */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11547,7 +10547,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_polymorphic: /* 0xfa */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11564,7 +10563,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_polymorphic_range: /* 0xfb */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11581,7 +10579,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_custom: /* 0xfc */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11598,7 +10595,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_custom_range: /* 0xfd */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11615,7 +10611,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_method_handle: /* 0xfe */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11632,7 +10627,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_method_type: /* 0xff */ -/* File: arm64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11647,16 +10641,12 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. .balign 128 -/* File: arm64/instruction_end_alt.S */ .type artMterpAsmAltInstructionEnd, #object .hidden artMterpAsmAltInstructionEnd .global artMterpAsmAltInstructionEnd artMterpAsmAltInstructionEnd: - -/* File: arm64/close_cfi.S */ // Close out the cfi info. We're treating mterp as a single function. END ExecuteMterpImpl - diff --git a/runtime/interpreter/mterp/out/mterp_mips.S b/runtime/interpreter/mterp/out/mterp_mips.S index 1f5bea0873..f2f3453e0a 100644 --- a/runtime/interpreter/mterp/out/mterp_mips.S +++ b/runtime/interpreter/mterp/out/mterp_mips.S @@ -1,10 +1,4 @@ -/* - * This file was generated automatically by gen-mterp.py for 'mips'. - * - * --> DO NOT EDIT <-- - */ - -/* File: mips/header.S */ +/* DO NOT EDIT: This file was generated by gen-mterp.py. */ /* * Copyright (C) 2016 The Android Open Source Project * @@ -670,7 +664,6 @@ #define STORE64_F(rlo, rhi, rbase) STORE64_off_F(rlo, rhi, rbase, 0) #define LOAD64_F(rlo, rhi, rbase) LOAD64_off_F(rlo, rhi, rbase, 0) - #define LOAD_base_offMirrorArray_length(rd, rbase) LOAD_RB_OFF(rd, rbase, MIRROR_ARRAY_LENGTH_OFFSET) #define STACK_STORE(rd, off) sw rd, off(sp) @@ -732,8 +725,6 @@ #define LONG_MIN_HIGH 0x80000000 #define LONG_MIN_AS_FLOAT 0xDF000000 #define LONG_MIN_AS_DOUBLE_HIGH 0xC3E00000 - -/* File: mips/entry.S */ /* * Copyright (C) 2016 The Android Open Source Project * @@ -810,16 +801,12 @@ ExecuteMterpImpl: GOTO_OPCODE(t0) # jump to next instruction /* NOTE: no fallthrough */ -/* File: mips/instruction_start.S */ - .global artMterpAsmInstructionStart artMterpAsmInstructionStart = .L_op_nop .text - /* ------------------------------ */ .balign 128 .L_op_nop: /* 0x00 */ -/* File: mips/op_nop.S */ FETCH_ADVANCE_INST(1) # advance rPC, load rINST GET_INST_OPCODE(t0) # extract opcode from rINST GOTO_OPCODE(t0) # jump to next instruction @@ -827,7 +814,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move: /* 0x01 */ -/* File: mips/op_move.S */ /* for move, move-object, long-to-int */ /* op vA, vB */ GET_OPB(a1) # a1 <- B from 15:12 @@ -844,7 +830,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_from16: /* 0x02 */ -/* File: mips/op_move_from16.S */ /* for: move/from16, move-object/from16 */ /* op vAA, vBBBB */ FETCH(a1, 1) # a1 <- BBBB @@ -861,7 +846,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_16: /* 0x03 */ -/* File: mips/op_move_16.S */ /* for: move/16, move-object/16 */ /* op vAAAA, vBBBB */ FETCH(a1, 2) # a1 <- BBBB @@ -878,7 +862,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_wide: /* 0x04 */ -/* File: mips/op_move_wide.S */ /* move-wide vA, vB */ /* NOTE: regs can overlap, e.g. "move v6, v7" or "move v7, v6" */ GET_OPA4(a2) # a2 <- A(+) @@ -892,7 +875,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_wide_from16: /* 0x05 */ -/* File: mips/op_move_wide_from16.S */ /* move-wide/from16 vAA, vBBBB */ /* NOTE: regs can overlap, e.g. "move v6, v7" or "move v7, v6" */ FETCH(a3, 1) # a3 <- BBBB @@ -906,7 +888,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_wide_16: /* 0x06 */ -/* File: mips/op_move_wide_16.S */ /* move-wide/16 vAAAA, vBBBB */ /* NOTE: regs can overlap, e.g. "move v6, v7" or "move v7, v6" */ FETCH(a3, 2) # a3 <- BBBB @@ -920,8 +901,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_object: /* 0x07 */ -/* File: mips/op_move_object.S */ -/* File: mips/op_move.S */ /* for move, move-object, long-to-int */ /* op vA, vB */ GET_OPB(a1) # a1 <- B from 15:12 @@ -935,12 +914,9 @@ artMterpAsmInstructionStart = .L_op_nop SET_VREG_GOTO(a2, a0, t0) # fp[A] <- a2 .endif - /* ------------------------------ */ .balign 128 .L_op_move_object_from16: /* 0x08 */ -/* File: mips/op_move_object_from16.S */ -/* File: mips/op_move_from16.S */ /* for: move/from16, move-object/from16 */ /* op vAA, vBBBB */ FETCH(a1, 1) # a1 <- BBBB @@ -954,12 +930,9 @@ artMterpAsmInstructionStart = .L_op_nop SET_VREG_GOTO(a2, a0, t0) # fp[AA] <- a2 .endif - /* ------------------------------ */ .balign 128 .L_op_move_object_16: /* 0x09 */ -/* File: mips/op_move_object_16.S */ -/* File: mips/op_move_16.S */ /* for: move/16, move-object/16 */ /* op vAAAA, vBBBB */ FETCH(a1, 2) # a1 <- BBBB @@ -973,11 +946,9 @@ artMterpAsmInstructionStart = .L_op_nop SET_VREG_GOTO(a2, a0, t0) # fp[AAAA] <- a2 .endif - /* ------------------------------ */ .balign 128 .L_op_move_result: /* 0x0a */ -/* File: mips/op_move_result.S */ /* for: move-result, move-result-object */ /* op vAA */ GET_OPA(a2) # a2 <- AA @@ -994,7 +965,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_result_wide: /* 0x0b */ -/* File: mips/op_move_result_wide.S */ /* move-result-wide vAA */ GET_OPA(a2) # a2 <- AA lw a3, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType @@ -1006,8 +976,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_result_object: /* 0x0c */ -/* File: mips/op_move_result_object.S */ -/* File: mips/op_move_result.S */ /* for: move-result, move-result-object */ /* op vAA */ GET_OPA(a2) # a2 <- AA @@ -1021,11 +989,9 @@ artMterpAsmInstructionStart = .L_op_nop SET_VREG_GOTO(a0, a2, t0) # fp[AA] <- a0 .endif - /* ------------------------------ */ .balign 128 .L_op_move_exception: /* 0x0d */ -/* File: mips/op_move_exception.S */ /* move-exception vAA */ GET_OPA(a2) # a2 <- AA lw a3, THREAD_EXCEPTION_OFFSET(rSELF) # get exception obj @@ -1039,7 +1005,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_return_void: /* 0x0e */ -/* File: mips/op_return_void.S */ .extern MterpThreadFenceForConstructor JAL(MterpThreadFenceForConstructor) lw ra, THREAD_FLAGS_OFFSET(rSELF) @@ -1055,7 +1020,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_return: /* 0x0f */ -/* File: mips/op_return.S */ /* * Return a 32-bit value. * @@ -1078,7 +1042,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_return_wide: /* 0x10 */ -/* File: mips/op_return_wide.S */ /* * Return a 64-bit value. */ @@ -1099,8 +1062,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_return_object: /* 0x11 */ -/* File: mips/op_return_object.S */ -/* File: mips/op_return.S */ /* * Return a 32-bit value. * @@ -1120,11 +1081,9 @@ artMterpAsmInstructionStart = .L_op_nop move v1, zero b MterpReturn - /* ------------------------------ */ .balign 128 .L_op_const_4: /* 0x12 */ -/* File: mips/op_const_4.S */ /* const/4 vA, +B */ sll a1, rINST, 16 # a1 <- Bxxx0000 GET_OPA(a0) # a0 <- A+ @@ -1137,7 +1096,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_16: /* 0x13 */ -/* File: mips/op_const_16.S */ /* const/16 vAA, +BBBB */ FETCH_S(a0, 1) # a0 <- ssssBBBB (sign-extended) GET_OPA(a3) # a3 <- AA @@ -1148,7 +1106,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const: /* 0x14 */ -/* File: mips/op_const.S */ /* const vAA, +BBBBbbbb */ GET_OPA(a3) # a3 <- AA FETCH(a0, 1) # a0 <- bbbb (low) @@ -1161,7 +1118,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_high16: /* 0x15 */ -/* File: mips/op_const_high16.S */ /* const/high16 vAA, +BBBB0000 */ FETCH(a0, 1) # a0 <- 0000BBBB (zero-extended) GET_OPA(a3) # a3 <- AA @@ -1173,7 +1129,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_wide_16: /* 0x16 */ -/* File: mips/op_const_wide_16.S */ /* const-wide/16 vAA, +BBBB */ FETCH_S(a0, 1) # a0 <- ssssBBBB (sign-extended) GET_OPA(a3) # a3 <- AA @@ -1185,7 +1140,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_wide_32: /* 0x17 */ -/* File: mips/op_const_wide_32.S */ /* const-wide/32 vAA, +BBBBbbbb */ FETCH(a0, 1) # a0 <- 0000bbbb (low) GET_OPA(a3) # a3 <- AA @@ -1199,7 +1153,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_wide: /* 0x18 */ -/* File: mips/op_const_wide.S */ /* const-wide vAA, +HHHHhhhhBBBBbbbb */ FETCH(a0, 1) # a0 <- bbbb (low) FETCH(a1, 2) # a1 <- BBBB (low middle) @@ -1215,7 +1168,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_wide_high16: /* 0x19 */ -/* File: mips/op_const_wide_high16.S */ /* const-wide/high16 vAA, +BBBB000000000000 */ FETCH(a1, 1) # a1 <- 0000BBBB (zero-extended) GET_OPA(a3) # a3 <- AA @@ -1228,8 +1180,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_string: /* 0x1a */ -/* File: mips/op_const_string.S */ -/* File: mips/const.S */ /* const/class vAA, type@BBBB */ /* const/method-handle vAA, method_handle@BBBB */ /* const/method-type vAA, proto@BBBB */ @@ -1247,11 +1197,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE(t0) # extract opcode from rINST GOTO_OPCODE(t0) # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_const_string_jumbo: /* 0x1b */ -/* File: mips/op_const_string_jumbo.S */ /* const/string vAA, string@BBBBBBBB */ EXPORT_PC() FETCH(a0, 1) # a0 <- bbbb (low) @@ -1270,8 +1218,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_class: /* 0x1c */ -/* File: mips/op_const_class.S */ -/* File: mips/const.S */ /* const/class vAA, type@BBBB */ /* const/method-handle vAA, method_handle@BBBB */ /* const/method-type vAA, proto@BBBB */ @@ -1289,11 +1235,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE(t0) # extract opcode from rINST GOTO_OPCODE(t0) # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_monitor_enter: /* 0x1d */ -/* File: mips/op_monitor_enter.S */ /* * Synchronize on an object. */ @@ -1311,7 +1255,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_monitor_exit: /* 0x1e */ -/* File: mips/op_monitor_exit.S */ /* * Unlock an object. * @@ -1333,7 +1276,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_check_cast: /* 0x1f */ -/* File: mips/op_check_cast.S */ /* * Check to see if a cast from one class to another is allowed. */ @@ -1354,7 +1296,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_instance_of: /* 0x20 */ -/* File: mips/op_instance_of.S */ /* * Check to see if an object reference is an instance of a class. * @@ -1380,7 +1321,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_array_length: /* 0x21 */ -/* File: mips/op_array_length.S */ /* * Return the length of an array. */ @@ -1398,7 +1338,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_new_instance: /* 0x22 */ -/* File: mips/op_new_instance.S */ /* * Create a new instance of a class. */ @@ -1416,7 +1355,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_new_array: /* 0x23 */ -/* File: mips/op_new_array.S */ /* * Allocate an array of objects, specified with the array class * and a count. @@ -1439,7 +1377,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_filled_new_array: /* 0x24 */ -/* File: mips/op_filled_new_array.S */ /* * Create a new array with elements filled from registers. * @@ -1461,8 +1398,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_filled_new_array_range: /* 0x25 */ -/* File: mips/op_filled_new_array_range.S */ -/* File: mips/op_filled_new_array.S */ /* * Create a new array with elements filled from registers. * @@ -1481,11 +1416,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE(t0) # extract opcode from rINST GOTO_OPCODE(t0) # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_fill_array_data: /* 0x26 */ -/* File: mips/op_fill_array_data.S */ /* fill-array-data vAA, +BBBBBBBB */ EXPORT_PC() FETCH(a1, 1) # a1 <- bbbb (lo) @@ -1503,7 +1436,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_throw: /* 0x27 */ -/* File: mips/op_throw.S */ /* * Throw an exception object in the current thread. */ @@ -1519,7 +1451,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_goto: /* 0x28 */ -/* File: mips/op_goto.S */ /* * Unconditional branch, 8-bit offset. * @@ -1534,7 +1465,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_goto_16: /* 0x29 */ -/* File: mips/op_goto_16.S */ /* * Unconditional branch, 16-bit offset. * @@ -1548,7 +1478,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_goto_32: /* 0x2a */ -/* File: mips/op_goto_32.S */ /* * Unconditional branch, 32-bit offset. * @@ -1567,7 +1496,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_packed_switch: /* 0x2b */ -/* File: mips/op_packed_switch.S */ /* * Handle a packed-switch or sparse-switch instruction. In both cases * we decode it and hand it off to a helper function. @@ -1591,8 +1519,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_sparse_switch: /* 0x2c */ -/* File: mips/op_sparse_switch.S */ -/* File: mips/op_packed_switch.S */ /* * Handle a packed-switch or sparse-switch instruction. In both cases * we decode it and hand it off to a helper function. @@ -1613,11 +1539,9 @@ artMterpAsmInstructionStart = .L_op_nop move rINST, v0 b MterpCommonTakenBranchNoFlags - /* ------------------------------ */ .balign 128 .L_op_cmpl_float: /* 0x2d */ -/* File: mips/op_cmpl_float.S */ /* * Compare two floating-point values. Puts 0(==), 1(>), or -1(<) * into the destination register based on the comparison results. @@ -1671,8 +1595,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_cmpg_float: /* 0x2e */ -/* File: mips/op_cmpg_float.S */ -/* File: mips/op_cmpl_float.S */ /* * Compare two floating-point values. Puts 0(==), 1(>), or -1(<) * into the destination register based on the comparison results. @@ -1723,11 +1645,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(rTEMP, rOBJ, t0) # vAA <- rTEMP - /* ------------------------------ */ .balign 128 .L_op_cmpl_double: /* 0x2f */ -/* File: mips/op_cmpl_double.S */ /* * Compare two floating-point values. Puts 0(==), 1(>), or -1(<) * into the destination register based on the comparison results. @@ -1783,8 +1703,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_cmpg_double: /* 0x30 */ -/* File: mips/op_cmpg_double.S */ -/* File: mips/op_cmpl_double.S */ /* * Compare two floating-point values. Puts 0(==), 1(>), or -1(<) * into the destination register based on the comparison results. @@ -1837,11 +1755,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(rTEMP, rOBJ, t0) # vAA <- rTEMP - /* ------------------------------ */ .balign 128 .L_op_cmp_long: /* 0x31 */ -/* File: mips/op_cmp_long.S */ /* * Compare two 64-bit values * x = y return 0 @@ -1880,8 +1796,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_if_eq: /* 0x32 */ -/* File: mips/op_if_eq.S */ -/* File: mips/bincmp.S */ /* * Generic two-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform. @@ -1901,12 +1815,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE(t0) # extract opcode from rINST GOTO_OPCODE(t0) # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_ne: /* 0x33 */ -/* File: mips/op_if_ne.S */ -/* File: mips/bincmp.S */ /* * Generic two-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform. @@ -1926,12 +1837,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE(t0) # extract opcode from rINST GOTO_OPCODE(t0) # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_lt: /* 0x34 */ -/* File: mips/op_if_lt.S */ -/* File: mips/bincmp.S */ /* * Generic two-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform. @@ -1951,12 +1859,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE(t0) # extract opcode from rINST GOTO_OPCODE(t0) # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_ge: /* 0x35 */ -/* File: mips/op_if_ge.S */ -/* File: mips/bincmp.S */ /* * Generic two-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform. @@ -1976,12 +1881,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE(t0) # extract opcode from rINST GOTO_OPCODE(t0) # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_gt: /* 0x36 */ -/* File: mips/op_if_gt.S */ -/* File: mips/bincmp.S */ /* * Generic two-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform. @@ -2001,12 +1903,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE(t0) # extract opcode from rINST GOTO_OPCODE(t0) # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_le: /* 0x37 */ -/* File: mips/op_if_le.S */ -/* File: mips/bincmp.S */ /* * Generic two-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform. @@ -2026,12 +1925,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE(t0) # extract opcode from rINST GOTO_OPCODE(t0) # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_eqz: /* 0x38 */ -/* File: mips/op_if_eqz.S */ -/* File: mips/zcmp.S */ /* * Generic one-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform. @@ -2049,12 +1945,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE(t0) # extract opcode from rINST GOTO_OPCODE(t0) # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_nez: /* 0x39 */ -/* File: mips/op_if_nez.S */ -/* File: mips/zcmp.S */ /* * Generic one-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform. @@ -2072,12 +1965,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE(t0) # extract opcode from rINST GOTO_OPCODE(t0) # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_ltz: /* 0x3a */ -/* File: mips/op_if_ltz.S */ -/* File: mips/zcmp.S */ /* * Generic one-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform. @@ -2095,12 +1985,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE(t0) # extract opcode from rINST GOTO_OPCODE(t0) # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_gez: /* 0x3b */ -/* File: mips/op_if_gez.S */ -/* File: mips/zcmp.S */ /* * Generic one-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform. @@ -2118,12 +2005,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE(t0) # extract opcode from rINST GOTO_OPCODE(t0) # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_gtz: /* 0x3c */ -/* File: mips/op_if_gtz.S */ -/* File: mips/zcmp.S */ /* * Generic one-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform. @@ -2141,12 +2025,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE(t0) # extract opcode from rINST GOTO_OPCODE(t0) # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_lez: /* 0x3d */ -/* File: mips/op_if_lez.S */ -/* File: mips/zcmp.S */ /* * Generic one-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform. @@ -2164,77 +2045,57 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE(t0) # extract opcode from rINST GOTO_OPCODE(t0) # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_unused_3e: /* 0x3e */ -/* File: mips/op_unused_3e.S */ -/* File: mips/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_3f: /* 0x3f */ -/* File: mips/op_unused_3f.S */ -/* File: mips/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_40: /* 0x40 */ -/* File: mips/op_unused_40.S */ -/* File: mips/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_41: /* 0x41 */ -/* File: mips/op_unused_41.S */ -/* File: mips/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_42: /* 0x42 */ -/* File: mips/op_unused_42.S */ -/* File: mips/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_43: /* 0x43 */ -/* File: mips/op_unused_43.S */ -/* File: mips/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_aget: /* 0x44 */ -/* File: mips/op_aget.S */ /* * Array get, 32 bits or less. vAA <- vBB[vCC]. * @@ -2266,7 +2127,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_aget_wide: /* 0x45 */ -/* File: mips/op_aget_wide.S */ /* * Array get, 64 bits. vAA <- vBB[vCC]. * @@ -2293,7 +2153,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_aget_object: /* 0x46 */ -/* File: mips/op_aget_object.S */ /* * Array object get. vAA <- vBB[vCC]. * @@ -2317,8 +2176,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_aget_boolean: /* 0x47 */ -/* File: mips/op_aget_boolean.S */ -/* File: mips/op_aget.S */ /* * Array get, 32 bits or less. vAA <- vBB[vCC]. * @@ -2347,12 +2204,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a2, rOBJ, t0) # vAA <- a2 - /* ------------------------------ */ .balign 128 .L_op_aget_byte: /* 0x48 */ -/* File: mips/op_aget_byte.S */ -/* File: mips/op_aget.S */ /* * Array get, 32 bits or less. vAA <- vBB[vCC]. * @@ -2381,12 +2235,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a2, rOBJ, t0) # vAA <- a2 - /* ------------------------------ */ .balign 128 .L_op_aget_char: /* 0x49 */ -/* File: mips/op_aget_char.S */ -/* File: mips/op_aget.S */ /* * Array get, 32 bits or less. vAA <- vBB[vCC]. * @@ -2415,12 +2266,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a2, rOBJ, t0) # vAA <- a2 - /* ------------------------------ */ .balign 128 .L_op_aget_short: /* 0x4a */ -/* File: mips/op_aget_short.S */ -/* File: mips/op_aget.S */ /* * Array get, 32 bits or less. vAA <- vBB[vCC]. * @@ -2449,11 +2297,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a2, rOBJ, t0) # vAA <- a2 - /* ------------------------------ */ .balign 128 .L_op_aput: /* 0x4b */ -/* File: mips/op_aput.S */ /* * Array put, 32 bits or less. vBB[vCC] <- vAA. @@ -2484,7 +2330,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_aput_wide: /* 0x4c */ -/* File: mips/op_aput_wide.S */ /* * Array put, 64 bits. vBB[vCC] <- vAA. */ @@ -2513,7 +2358,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_aput_object: /* 0x4d */ -/* File: mips/op_aput_object.S */ /* * Store an object into an array. vBB[vCC] <- vAA. * @@ -2532,8 +2376,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_aput_boolean: /* 0x4e */ -/* File: mips/op_aput_boolean.S */ -/* File: mips/op_aput.S */ /* * Array put, 32 bits or less. vBB[vCC] <- vAA. @@ -2561,12 +2403,9 @@ artMterpAsmInstructionStart = .L_op_nop sb a2, MIRROR_BOOLEAN_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 JR(t0) # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_aput_byte: /* 0x4f */ -/* File: mips/op_aput_byte.S */ -/* File: mips/op_aput.S */ /* * Array put, 32 bits or less. vBB[vCC] <- vAA. @@ -2594,12 +2433,9 @@ artMterpAsmInstructionStart = .L_op_nop sb a2, MIRROR_BYTE_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 JR(t0) # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_aput_char: /* 0x50 */ -/* File: mips/op_aput_char.S */ -/* File: mips/op_aput.S */ /* * Array put, 32 bits or less. vBB[vCC] <- vAA. @@ -2627,12 +2463,9 @@ artMterpAsmInstructionStart = .L_op_nop sh a2, MIRROR_CHAR_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 JR(t0) # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_aput_short: /* 0x51 */ -/* File: mips/op_aput_short.S */ -/* File: mips/op_aput.S */ /* * Array put, 32 bits or less. vBB[vCC] <- vAA. @@ -2660,284 +2493,149 @@ artMterpAsmInstructionStart = .L_op_nop sh a2, MIRROR_SHORT_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 JR(t0) # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_iget: /* 0x52 */ -/* File: mips/op_iget.S */ -/* File: mips/field.S */ TODO - /* ------------------------------ */ .balign 128 .L_op_iget_wide: /* 0x53 */ -/* File: mips/op_iget_wide.S */ -/* File: mips/op_iget.S */ -/* File: mips/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_iget_object: /* 0x54 */ -/* File: mips/op_iget_object.S */ -/* File: mips/op_iget.S */ -/* File: mips/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_iget_boolean: /* 0x55 */ -/* File: mips/op_iget_boolean.S */ -/* File: mips/op_iget.S */ -/* File: mips/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_iget_byte: /* 0x56 */ -/* File: mips/op_iget_byte.S */ -/* File: mips/op_iget.S */ -/* File: mips/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_iget_char: /* 0x57 */ -/* File: mips/op_iget_char.S */ -/* File: mips/op_iget.S */ -/* File: mips/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_iget_short: /* 0x58 */ -/* File: mips/op_iget_short.S */ -/* File: mips/op_iget.S */ -/* File: mips/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_iput: /* 0x59 */ -/* File: mips/op_iput.S */ -/* File: mips/field.S */ TODO - /* ------------------------------ */ .balign 128 .L_op_iput_wide: /* 0x5a */ -/* File: mips/op_iput_wide.S */ -/* File: mips/op_iput.S */ -/* File: mips/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_iput_object: /* 0x5b */ -/* File: mips/op_iput_object.S */ -/* File: mips/op_iput.S */ -/* File: mips/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_iput_boolean: /* 0x5c */ -/* File: mips/op_iput_boolean.S */ -/* File: mips/op_iput.S */ -/* File: mips/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_iput_byte: /* 0x5d */ -/* File: mips/op_iput_byte.S */ -/* File: mips/op_iput.S */ -/* File: mips/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_iput_char: /* 0x5e */ -/* File: mips/op_iput_char.S */ -/* File: mips/op_iput.S */ -/* File: mips/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_iput_short: /* 0x5f */ -/* File: mips/op_iput_short.S */ -/* File: mips/op_iput.S */ -/* File: mips/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_sget: /* 0x60 */ -/* File: mips/op_sget.S */ -/* File: mips/field.S */ TODO - /* ------------------------------ */ .balign 128 .L_op_sget_wide: /* 0x61 */ -/* File: mips/op_sget_wide.S */ -/* File: mips/op_sget.S */ -/* File: mips/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_sget_object: /* 0x62 */ -/* File: mips/op_sget_object.S */ -/* File: mips/op_sget.S */ -/* File: mips/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_sget_boolean: /* 0x63 */ -/* File: mips/op_sget_boolean.S */ -/* File: mips/op_sget.S */ -/* File: mips/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_sget_byte: /* 0x64 */ -/* File: mips/op_sget_byte.S */ -/* File: mips/op_sget.S */ -/* File: mips/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_sget_char: /* 0x65 */ -/* File: mips/op_sget_char.S */ -/* File: mips/op_sget.S */ -/* File: mips/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_sget_short: /* 0x66 */ -/* File: mips/op_sget_short.S */ -/* File: mips/op_sget.S */ -/* File: mips/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_sput: /* 0x67 */ -/* File: mips/op_sput.S */ -/* File: mips/field.S */ TODO - /* ------------------------------ */ .balign 128 .L_op_sput_wide: /* 0x68 */ -/* File: mips/op_sput_wide.S */ -/* File: mips/op_sput.S */ -/* File: mips/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_sput_object: /* 0x69 */ -/* File: mips/op_sput_object.S */ -/* File: mips/op_sput.S */ -/* File: mips/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_sput_boolean: /* 0x6a */ -/* File: mips/op_sput_boolean.S */ -/* File: mips/op_sput.S */ -/* File: mips/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_sput_byte: /* 0x6b */ -/* File: mips/op_sput_byte.S */ -/* File: mips/op_sput.S */ -/* File: mips/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_sput_char: /* 0x6c */ -/* File: mips/op_sput_char.S */ -/* File: mips/op_sput.S */ -/* File: mips/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_sput_short: /* 0x6d */ -/* File: mips/op_sput_short.S */ -/* File: mips/op_sput.S */ -/* File: mips/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_invoke_virtual: /* 0x6e */ -/* File: mips/op_invoke_virtual.S */ -/* File: mips/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -2957,12 +2655,9 @@ TODO GET_INST_OPCODE(t0) GOTO_OPCODE(t0) - /* ------------------------------ */ .balign 128 .L_op_invoke_super: /* 0x6f */ -/* File: mips/op_invoke_super.S */ -/* File: mips/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -2982,12 +2677,9 @@ TODO GET_INST_OPCODE(t0) GOTO_OPCODE(t0) - /* ------------------------------ */ .balign 128 .L_op_invoke_direct: /* 0x70 */ -/* File: mips/op_invoke_direct.S */ -/* File: mips/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -3007,12 +2699,9 @@ TODO GET_INST_OPCODE(t0) GOTO_OPCODE(t0) - /* ------------------------------ */ .balign 128 .L_op_invoke_static: /* 0x71 */ -/* File: mips/op_invoke_static.S */ -/* File: mips/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -3032,12 +2721,9 @@ TODO GET_INST_OPCODE(t0) GOTO_OPCODE(t0) - /* ------------------------------ */ .balign 128 .L_op_invoke_interface: /* 0x72 */ -/* File: mips/op_invoke_interface.S */ -/* File: mips/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -3057,11 +2743,9 @@ TODO GET_INST_OPCODE(t0) GOTO_OPCODE(t0) - /* ------------------------------ */ .balign 128 .L_op_return_void_no_barrier: /* 0x73 */ -/* File: mips/op_return_void_no_barrier.S */ lw ra, THREAD_FLAGS_OFFSET(rSELF) move a0, rSELF and ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST @@ -3075,8 +2759,6 @@ TODO /* ------------------------------ */ .balign 128 .L_op_invoke_virtual_range: /* 0x74 */ -/* File: mips/op_invoke_virtual_range.S */ -/* File: mips/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -3096,12 +2778,9 @@ TODO GET_INST_OPCODE(t0) GOTO_OPCODE(t0) - /* ------------------------------ */ .balign 128 .L_op_invoke_super_range: /* 0x75 */ -/* File: mips/op_invoke_super_range.S */ -/* File: mips/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -3121,12 +2800,9 @@ TODO GET_INST_OPCODE(t0) GOTO_OPCODE(t0) - /* ------------------------------ */ .balign 128 .L_op_invoke_direct_range: /* 0x76 */ -/* File: mips/op_invoke_direct_range.S */ -/* File: mips/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -3146,12 +2822,9 @@ TODO GET_INST_OPCODE(t0) GOTO_OPCODE(t0) - /* ------------------------------ */ .balign 128 .L_op_invoke_static_range: /* 0x77 */ -/* File: mips/op_invoke_static_range.S */ -/* File: mips/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -3171,12 +2844,9 @@ TODO GET_INST_OPCODE(t0) GOTO_OPCODE(t0) - /* ------------------------------ */ .balign 128 .L_op_invoke_interface_range: /* 0x78 */ -/* File: mips/op_invoke_interface_range.S */ -/* File: mips/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -3196,34 +2866,25 @@ TODO GET_INST_OPCODE(t0) GOTO_OPCODE(t0) - /* ------------------------------ */ .balign 128 .L_op_unused_79: /* 0x79 */ -/* File: mips/op_unused_79.S */ -/* File: mips/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_7a: /* 0x7a */ -/* File: mips/op_unused_7a.S */ -/* File: mips/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_neg_int: /* 0x7b */ -/* File: mips/op_neg_int.S */ -/* File: mips/unop.S */ /* * Generic 32-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result0 = op a0". @@ -3242,12 +2903,9 @@ TODO GET_INST_OPCODE(t1) # extract opcode from rINST SET_VREG_GOTO(a0, t0, t1) # vA <- result0 - /* ------------------------------ */ .balign 128 .L_op_not_int: /* 0x7c */ -/* File: mips/op_not_int.S */ -/* File: mips/unop.S */ /* * Generic 32-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result0 = op a0". @@ -3266,12 +2924,9 @@ TODO GET_INST_OPCODE(t1) # extract opcode from rINST SET_VREG_GOTO(a0, t0, t1) # vA <- result0 - /* ------------------------------ */ .balign 128 .L_op_neg_long: /* 0x7d */ -/* File: mips/op_neg_long.S */ -/* File: mips/unopWide.S */ /* * Generic 64-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result0/result1 = op a0/a1". @@ -3290,12 +2945,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vA/vA+1 <- a0/a1 - /* ------------------------------ */ .balign 128 .L_op_not_long: /* 0x7e */ -/* File: mips/op_not_long.S */ -/* File: mips/unopWide.S */ /* * Generic 64-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result0/result1 = op a0/a1". @@ -3314,12 +2966,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vA/vA+1 <- a0/a1 - /* ------------------------------ */ .balign 128 .L_op_neg_float: /* 0x7f */ -/* File: mips/op_neg_float.S */ -/* File: mips/unop.S */ /* * Generic 32-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result0 = op a0". @@ -3338,12 +2987,9 @@ TODO GET_INST_OPCODE(t1) # extract opcode from rINST SET_VREG_GOTO(a0, t0, t1) # vA <- result0 - /* ------------------------------ */ .balign 128 .L_op_neg_double: /* 0x80 */ -/* File: mips/op_neg_double.S */ -/* File: mips/unopWide.S */ /* * Generic 64-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result0/result1 = op a0/a1". @@ -3362,12 +3008,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vA/vA+1 <- a0/a1 - /* ------------------------------ */ .balign 128 .L_op_int_to_long: /* 0x81 */ -/* File: mips/op_int_to_long.S */ -/* File: mips/unopWider.S */ /* * Generic 32bit-to-64bit unary operation. Provide an "instr" line * that specifies an instruction that performs "result0/result1 = op a0". @@ -3384,12 +3027,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vA/vA+1 <- a0/a1 - /* ------------------------------ */ .balign 128 .L_op_int_to_float: /* 0x82 */ -/* File: mips/op_int_to_float.S */ -/* File: mips/funop.S */ /* * Generic 32-bit floating-point unary operation. Provide an "instr" * line that specifies an instruction that performs "fv0 = op fa0". @@ -3406,12 +3046,9 @@ TODO GET_INST_OPCODE(t1) # extract opcode from rINST SET_VREG_F_GOTO(fv0, rOBJ, t1) # vA <- fv0 - /* ------------------------------ */ .balign 128 .L_op_int_to_double: /* 0x83 */ -/* File: mips/op_int_to_double.S */ -/* File: mips/funopWider.S */ /* * Generic 32bit-to-64bit floating-point unary operation. Provide an "instr" * line that specifies an instruction that performs "fv0 = op fa0". @@ -3427,13 +3064,10 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vA/vA+1 <- fv0 - /* ------------------------------ */ .balign 128 .L_op_long_to_int: /* 0x84 */ -/* File: mips/op_long_to_int.S */ /* we ignore the high word, making this equivalent to a 32-bit reg move */ -/* File: mips/op_move.S */ /* for move, move-object, long-to-int */ /* op vA, vB */ GET_OPB(a1) # a1 <- B from 15:12 @@ -3447,11 +3081,9 @@ TODO SET_VREG_GOTO(a2, a0, t0) # fp[A] <- a2 .endif - /* ------------------------------ */ .balign 128 .L_op_long_to_float: /* 0x85 */ -/* File: mips/op_long_to_float.S */ /* * long-to-float */ @@ -3476,7 +3108,6 @@ TODO /* ------------------------------ */ .balign 128 .L_op_long_to_double: /* 0x86 */ -/* File: mips/op_long_to_double.S */ /* * long-to-double */ @@ -3501,7 +3132,6 @@ TODO /* ------------------------------ */ .balign 128 .L_op_float_to_int: /* 0x87 */ -/* File: mips/op_float_to_int.S */ /* * float-to-int * @@ -3535,7 +3165,6 @@ TODO /* ------------------------------ */ .balign 128 .L_op_float_to_long: /* 0x88 */ -/* File: mips/op_float_to_long.S */ /* * float-to-long * @@ -3580,8 +3209,6 @@ TODO /* ------------------------------ */ .balign 128 .L_op_float_to_double: /* 0x89 */ -/* File: mips/op_float_to_double.S */ -/* File: mips/funopWider.S */ /* * Generic 32bit-to-64bit floating-point unary operation. Provide an "instr" * line that specifies an instruction that performs "fv0 = op fa0". @@ -3597,11 +3224,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vA/vA+1 <- fv0 - /* ------------------------------ */ .balign 128 .L_op_double_to_int: /* 0x8a */ -/* File: mips/op_double_to_int.S */ /* * double-to-int * @@ -3637,7 +3262,6 @@ TODO /* ------------------------------ */ .balign 128 .L_op_double_to_long: /* 0x8b */ -/* File: mips/op_double_to_long.S */ /* * double-to-long * @@ -3684,8 +3308,6 @@ TODO /* ------------------------------ */ .balign 128 .L_op_double_to_float: /* 0x8c */ -/* File: mips/op_double_to_float.S */ -/* File: mips/unopNarrower.S */ /* * Generic 64bit-to-32bit floating-point unary operation. Provide an "instr" * line that specifies an instruction that performs "fv0 = op fa0". @@ -3702,12 +3324,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_F_GOTO(fv0, rOBJ, t0) # vA <- fv0 - /* ------------------------------ */ .balign 128 .L_op_int_to_byte: /* 0x8d */ -/* File: mips/op_int_to_byte.S */ -/* File: mips/unop.S */ /* * Generic 32-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result0 = op a0". @@ -3726,12 +3345,9 @@ TODO GET_INST_OPCODE(t1) # extract opcode from rINST SET_VREG_GOTO(a0, t0, t1) # vA <- result0 - /* ------------------------------ */ .balign 128 .L_op_int_to_char: /* 0x8e */ -/* File: mips/op_int_to_char.S */ -/* File: mips/unop.S */ /* * Generic 32-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result0 = op a0". @@ -3750,12 +3366,9 @@ TODO GET_INST_OPCODE(t1) # extract opcode from rINST SET_VREG_GOTO(a0, t0, t1) # vA <- result0 - /* ------------------------------ */ .balign 128 .L_op_int_to_short: /* 0x8f */ -/* File: mips/op_int_to_short.S */ -/* File: mips/unop.S */ /* * Generic 32-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result0 = op a0". @@ -3774,12 +3387,9 @@ TODO GET_INST_OPCODE(t1) # extract opcode from rINST SET_VREG_GOTO(a0, t0, t1) # vA <- result0 - /* ------------------------------ */ .balign 128 .L_op_add_int: /* 0x90 */ -/* File: mips/op_add_int.S */ -/* File: mips/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0 op a1". @@ -3812,12 +3422,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - /* ------------------------------ */ .balign 128 .L_op_sub_int: /* 0x91 */ -/* File: mips/op_sub_int.S */ -/* File: mips/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0 op a1". @@ -3850,12 +3457,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - /* ------------------------------ */ .balign 128 .L_op_mul_int: /* 0x92 */ -/* File: mips/op_mul_int.S */ -/* File: mips/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0 op a1". @@ -3888,13 +3492,10 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - /* ------------------------------ */ .balign 128 .L_op_div_int: /* 0x93 */ -/* File: mips/op_div_int.S */ #ifdef MIPS32REVGE6 -/* File: mips/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0 op a1". @@ -3926,9 +3527,7 @@ TODO div a0, a0, a1 # a0 <- op, a0-a3 changed GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - #else -/* File: mips/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0 op a1". @@ -3960,15 +3559,12 @@ TODO mflo a0 # a0 <- op, a0-a3 changed GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - #endif /* ------------------------------ */ .balign 128 .L_op_rem_int: /* 0x94 */ -/* File: mips/op_rem_int.S */ #ifdef MIPS32REVGE6 -/* File: mips/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0 op a1". @@ -4000,9 +3596,7 @@ TODO mod a0, a0, a1 # a0 <- op, a0-a3 changed GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - #else -/* File: mips/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0 op a1". @@ -4034,14 +3628,11 @@ TODO mfhi a0 # a0 <- op, a0-a3 changed GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - #endif /* ------------------------------ */ .balign 128 .L_op_and_int: /* 0x95 */ -/* File: mips/op_and_int.S */ -/* File: mips/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0 op a1". @@ -4074,12 +3665,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - /* ------------------------------ */ .balign 128 .L_op_or_int: /* 0x96 */ -/* File: mips/op_or_int.S */ -/* File: mips/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0 op a1". @@ -4112,12 +3700,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - /* ------------------------------ */ .balign 128 .L_op_xor_int: /* 0x97 */ -/* File: mips/op_xor_int.S */ -/* File: mips/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0 op a1". @@ -4150,12 +3735,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - /* ------------------------------ */ .balign 128 .L_op_shl_int: /* 0x98 */ -/* File: mips/op_shl_int.S */ -/* File: mips/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0 op a1". @@ -4188,12 +3770,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - /* ------------------------------ */ .balign 128 .L_op_shr_int: /* 0x99 */ -/* File: mips/op_shr_int.S */ -/* File: mips/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0 op a1". @@ -4226,12 +3805,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - /* ------------------------------ */ .balign 128 .L_op_ushr_int: /* 0x9a */ -/* File: mips/op_ushr_int.S */ -/* File: mips/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0 op a1". @@ -4264,11 +3840,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - /* ------------------------------ */ .balign 128 .L_op_add_long: /* 0x9b */ -/* File: mips/op_add_long.S */ /* * The compiler generates the following sequence for * [v1 v0] = [a1 a0] + [a3 a2]; @@ -4277,7 +3851,6 @@ TODO * sltu v1,v0,a2 * addu v1,v1,a1 */ -/* File: mips/binopWide.S */ /* * Generic 64-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0-a1 op a2-a3". @@ -4312,11 +3885,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vAA/vAA+1 <- v0/v1 - /* ------------------------------ */ .balign 128 .L_op_sub_long: /* 0x9c */ -/* File: mips/op_sub_long.S */ /* * For little endian the code sequence looks as follows: * subu v0,a0,a2 @@ -4324,7 +3895,6 @@ TODO * sltu a0,a0,v0 * subu v1,v1,a0 */ -/* File: mips/binopWide.S */ /* * Generic 64-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0-a1 op a2-a3". @@ -4359,11 +3929,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vAA/vAA+1 <- v0/v1 - /* ------------------------------ */ .balign 128 .L_op_mul_long: /* 0x9d */ -/* File: mips/op_mul_long.S */ /* * Signed 64-bit integer multiply. * a1 a0 @@ -4405,8 +3973,6 @@ TODO /* ------------------------------ */ .balign 128 .L_op_div_long: /* 0x9e */ -/* File: mips/op_div_long.S */ -/* File: mips/binopWide.S */ /* * Generic 64-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0-a1 op a2-a3". @@ -4441,12 +4007,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vAA/vAA+1 <- v0/v1 - /* ------------------------------ */ .balign 128 .L_op_rem_long: /* 0x9f */ -/* File: mips/op_rem_long.S */ -/* File: mips/binopWide.S */ /* * Generic 64-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0-a1 op a2-a3". @@ -4481,12 +4044,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vAA/vAA+1 <- v0/v1 - /* ------------------------------ */ .balign 128 .L_op_and_long: /* 0xa0 */ -/* File: mips/op_and_long.S */ -/* File: mips/binopWide.S */ /* * Generic 64-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0-a1 op a2-a3". @@ -4521,12 +4081,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vAA/vAA+1 <- a0/a1 - /* ------------------------------ */ .balign 128 .L_op_or_long: /* 0xa1 */ -/* File: mips/op_or_long.S */ -/* File: mips/binopWide.S */ /* * Generic 64-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0-a1 op a2-a3". @@ -4561,12 +4118,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vAA/vAA+1 <- a0/a1 - /* ------------------------------ */ .balign 128 .L_op_xor_long: /* 0xa2 */ -/* File: mips/op_xor_long.S */ -/* File: mips/binopWide.S */ /* * Generic 64-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0-a1 op a2-a3". @@ -4601,11 +4155,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vAA/vAA+1 <- a0/a1 - /* ------------------------------ */ .balign 128 .L_op_shl_long: /* 0xa3 */ -/* File: mips/op_shl_long.S */ /* * Long integer shift. This is different from the generic 32/64-bit * binary operations because vAA/vBB are 64-bit but vCC (the shift @@ -4637,7 +4189,6 @@ TODO /* ------------------------------ */ .balign 128 .L_op_shr_long: /* 0xa4 */ -/* File: mips/op_shr_long.S */ /* * Long integer shift. This is different from the generic 32/64-bit * binary operations because vAA/vBB are 64-bit but vCC (the shift @@ -4668,7 +4219,6 @@ TODO /* ------------------------------ */ .balign 128 .L_op_ushr_long: /* 0xa5 */ -/* File: mips/op_ushr_long.S */ /* * Long integer shift. This is different from the generic 32/64-bit * binary operations because vAA/vBB are 64-bit but vCC (the shift @@ -4700,8 +4250,6 @@ TODO /* ------------------------------ */ .balign 128 .L_op_add_float: /* 0xa6 */ -/* File: mips/op_add_float.S */ -/* File: mips/fbinop.S */ /* * Generic 32-bit binary float operation. * @@ -4721,12 +4269,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_F_GOTO(fv0, rOBJ, t0) # vAA <- fv0 - /* ------------------------------ */ .balign 128 .L_op_sub_float: /* 0xa7 */ -/* File: mips/op_sub_float.S */ -/* File: mips/fbinop.S */ /* * Generic 32-bit binary float operation. * @@ -4746,12 +4291,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_F_GOTO(fv0, rOBJ, t0) # vAA <- fv0 - /* ------------------------------ */ .balign 128 .L_op_mul_float: /* 0xa8 */ -/* File: mips/op_mul_float.S */ -/* File: mips/fbinop.S */ /* * Generic 32-bit binary float operation. * @@ -4771,12 +4313,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_F_GOTO(fv0, rOBJ, t0) # vAA <- fv0 - /* ------------------------------ */ .balign 128 .L_op_div_float: /* 0xa9 */ -/* File: mips/op_div_float.S */ -/* File: mips/fbinop.S */ /* * Generic 32-bit binary float operation. * @@ -4796,12 +4335,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_F_GOTO(fv0, rOBJ, t0) # vAA <- fv0 - /* ------------------------------ */ .balign 128 .L_op_rem_float: /* 0xaa */ -/* File: mips/op_rem_float.S */ -/* File: mips/fbinop.S */ /* * Generic 32-bit binary float operation. * @@ -4821,12 +4357,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_F_GOTO(fv0, rOBJ, t0) # vAA <- fv0 - /* ------------------------------ */ .balign 128 .L_op_add_double: /* 0xab */ -/* File: mips/op_add_double.S */ -/* File: mips/fbinopWide.S */ /* * Generic 64-bit floating-point binary operation. Provide an "instr" * line that specifies an instruction that performs "fv0 = fa0 op fa1". @@ -4851,12 +4384,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vAA/vAA+1 <- fv0 - /* ------------------------------ */ .balign 128 .L_op_sub_double: /* 0xac */ -/* File: mips/op_sub_double.S */ -/* File: mips/fbinopWide.S */ /* * Generic 64-bit floating-point binary operation. Provide an "instr" * line that specifies an instruction that performs "fv0 = fa0 op fa1". @@ -4881,12 +4411,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vAA/vAA+1 <- fv0 - /* ------------------------------ */ .balign 128 .L_op_mul_double: /* 0xad */ -/* File: mips/op_mul_double.S */ -/* File: mips/fbinopWide.S */ /* * Generic 64-bit floating-point binary operation. Provide an "instr" * line that specifies an instruction that performs "fv0 = fa0 op fa1". @@ -4911,12 +4438,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vAA/vAA+1 <- fv0 - /* ------------------------------ */ .balign 128 .L_op_div_double: /* 0xae */ -/* File: mips/op_div_double.S */ -/* File: mips/fbinopWide.S */ /* * Generic 64-bit floating-point binary operation. Provide an "instr" * line that specifies an instruction that performs "fv0 = fa0 op fa1". @@ -4941,12 +4465,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vAA/vAA+1 <- fv0 - /* ------------------------------ */ .balign 128 .L_op_rem_double: /* 0xaf */ -/* File: mips/op_rem_double.S */ -/* File: mips/fbinopWide.S */ /* * Generic 64-bit floating-point binary operation. Provide an "instr" * line that specifies an instruction that performs "fv0 = fa0 op fa1". @@ -4971,12 +4492,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vAA/vAA+1 <- fv0 - /* ------------------------------ */ .balign 128 .L_op_add_int_2addr: /* 0xb0 */ -/* File: mips/op_add_int_2addr.S */ -/* File: mips/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -5005,12 +4523,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - /* ------------------------------ */ .balign 128 .L_op_sub_int_2addr: /* 0xb1 */ -/* File: mips/op_sub_int_2addr.S */ -/* File: mips/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -5039,12 +4554,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - /* ------------------------------ */ .balign 128 .L_op_mul_int_2addr: /* 0xb2 */ -/* File: mips/op_mul_int_2addr.S */ -/* File: mips/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -5073,13 +4585,10 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - /* ------------------------------ */ .balign 128 .L_op_div_int_2addr: /* 0xb3 */ -/* File: mips/op_div_int_2addr.S */ #ifdef MIPS32REVGE6 -/* File: mips/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -5107,9 +4616,7 @@ TODO div a0, a0, a1 # a0 <- op, a0-a3 changed GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - #else -/* File: mips/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -5137,15 +4644,12 @@ TODO mflo a0 # a0 <- op, a0-a3 changed GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - #endif /* ------------------------------ */ .balign 128 .L_op_rem_int_2addr: /* 0xb4 */ -/* File: mips/op_rem_int_2addr.S */ #ifdef MIPS32REVGE6 -/* File: mips/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -5173,9 +4677,7 @@ TODO mod a0, a0, a1 # a0 <- op, a0-a3 changed GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - #else -/* File: mips/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -5203,14 +4705,11 @@ TODO mfhi a0 # a0 <- op, a0-a3 changed GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - #endif /* ------------------------------ */ .balign 128 .L_op_and_int_2addr: /* 0xb5 */ -/* File: mips/op_and_int_2addr.S */ -/* File: mips/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -5239,12 +4738,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - /* ------------------------------ */ .balign 128 .L_op_or_int_2addr: /* 0xb6 */ -/* File: mips/op_or_int_2addr.S */ -/* File: mips/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -5273,12 +4769,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - /* ------------------------------ */ .balign 128 .L_op_xor_int_2addr: /* 0xb7 */ -/* File: mips/op_xor_int_2addr.S */ -/* File: mips/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -5307,12 +4800,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - /* ------------------------------ */ .balign 128 .L_op_shl_int_2addr: /* 0xb8 */ -/* File: mips/op_shl_int_2addr.S */ -/* File: mips/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -5341,12 +4831,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - /* ------------------------------ */ .balign 128 .L_op_shr_int_2addr: /* 0xb9 */ -/* File: mips/op_shr_int_2addr.S */ -/* File: mips/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -5375,12 +4862,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - /* ------------------------------ */ .balign 128 .L_op_ushr_int_2addr: /* 0xba */ -/* File: mips/op_ushr_int_2addr.S */ -/* File: mips/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -5409,15 +4893,12 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - /* ------------------------------ */ .balign 128 .L_op_add_long_2addr: /* 0xbb */ -/* File: mips/op_add_long_2addr.S */ /* * See op_add_long.S for details */ -/* File: mips/binopWide2addr.S */ /* * Generic 64-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0-a1 op a2-a3". @@ -5448,15 +4929,12 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vA/vA+1 <- v0/v1 - /* ------------------------------ */ .balign 128 .L_op_sub_long_2addr: /* 0xbc */ -/* File: mips/op_sub_long_2addr.S */ /* * See op_sub_long.S for more details */ -/* File: mips/binopWide2addr.S */ /* * Generic 64-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0-a1 op a2-a3". @@ -5487,11 +4965,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vA/vA+1 <- v0/v1 - /* ------------------------------ */ .balign 128 .L_op_mul_long_2addr: /* 0xbd */ -/* File: mips/op_mul_long_2addr.S */ /* * See op_mul_long.S for more details */ @@ -5525,8 +5001,6 @@ TODO /* ------------------------------ */ .balign 128 .L_op_div_long_2addr: /* 0xbe */ -/* File: mips/op_div_long_2addr.S */ -/* File: mips/binopWide2addr.S */ /* * Generic 64-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0-a1 op a2-a3". @@ -5557,12 +5031,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vA/vA+1 <- v0/v1 - /* ------------------------------ */ .balign 128 .L_op_rem_long_2addr: /* 0xbf */ -/* File: mips/op_rem_long_2addr.S */ -/* File: mips/binopWide2addr.S */ /* * Generic 64-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0-a1 op a2-a3". @@ -5593,12 +5064,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vA/vA+1 <- v0/v1 - /* ------------------------------ */ .balign 128 .L_op_and_long_2addr: /* 0xc0 */ -/* File: mips/op_and_long_2addr.S */ -/* File: mips/binopWide2addr.S */ /* * Generic 64-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0-a1 op a2-a3". @@ -5629,12 +5097,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vA/vA+1 <- a0/a1 - /* ------------------------------ */ .balign 128 .L_op_or_long_2addr: /* 0xc1 */ -/* File: mips/op_or_long_2addr.S */ -/* File: mips/binopWide2addr.S */ /* * Generic 64-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0-a1 op a2-a3". @@ -5665,12 +5130,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vA/vA+1 <- a0/a1 - /* ------------------------------ */ .balign 128 .L_op_xor_long_2addr: /* 0xc2 */ -/* File: mips/op_xor_long_2addr.S */ -/* File: mips/binopWide2addr.S */ /* * Generic 64-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0-a1 op a2-a3". @@ -5701,11 +5163,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vA/vA+1 <- a0/a1 - /* ------------------------------ */ .balign 128 .L_op_shl_long_2addr: /* 0xc3 */ -/* File: mips/op_shl_long_2addr.S */ /* * Long integer shift, 2addr version. vA is 64-bit value/result, vB is * 32-bit shift distance. @@ -5733,7 +5193,6 @@ TODO /* ------------------------------ */ .balign 128 .L_op_shr_long_2addr: /* 0xc4 */ -/* File: mips/op_shr_long_2addr.S */ /* * Long integer shift, 2addr version. vA is 64-bit value/result, vB is * 32-bit shift distance. @@ -5760,7 +5219,6 @@ TODO /* ------------------------------ */ .balign 128 .L_op_ushr_long_2addr: /* 0xc5 */ -/* File: mips/op_ushr_long_2addr.S */ /* * Long integer shift, 2addr version. vA is 64-bit value/result, vB is * 32-bit shift distance. @@ -5788,8 +5246,6 @@ TODO /* ------------------------------ */ .balign 128 .L_op_add_float_2addr: /* 0xc6 */ -/* File: mips/op_add_float_2addr.S */ -/* File: mips/fbinop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" * that specifies an instruction that performs "fv0 = fa0 op fa1". @@ -5809,12 +5265,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_F_GOTO(fv0, rOBJ, t0) # vA <- result - /* ------------------------------ */ .balign 128 .L_op_sub_float_2addr: /* 0xc7 */ -/* File: mips/op_sub_float_2addr.S */ -/* File: mips/fbinop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" * that specifies an instruction that performs "fv0 = fa0 op fa1". @@ -5834,12 +5287,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_F_GOTO(fv0, rOBJ, t0) # vA <- result - /* ------------------------------ */ .balign 128 .L_op_mul_float_2addr: /* 0xc8 */ -/* File: mips/op_mul_float_2addr.S */ -/* File: mips/fbinop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" * that specifies an instruction that performs "fv0 = fa0 op fa1". @@ -5859,12 +5309,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_F_GOTO(fv0, rOBJ, t0) # vA <- result - /* ------------------------------ */ .balign 128 .L_op_div_float_2addr: /* 0xc9 */ -/* File: mips/op_div_float_2addr.S */ -/* File: mips/fbinop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" * that specifies an instruction that performs "fv0 = fa0 op fa1". @@ -5884,12 +5331,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_F_GOTO(fv0, rOBJ, t0) # vA <- result - /* ------------------------------ */ .balign 128 .L_op_rem_float_2addr: /* 0xca */ -/* File: mips/op_rem_float_2addr.S */ -/* File: mips/fbinop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" * that specifies an instruction that performs "fv0 = fa0 op fa1". @@ -5909,12 +5353,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_F_GOTO(fv0, rOBJ, t0) # vA <- result - /* ------------------------------ */ .balign 128 .L_op_add_double_2addr: /* 0xcb */ -/* File: mips/op_add_double_2addr.S */ -/* File: mips/fbinopWide2addr.S */ /* * Generic 64-bit floating-point "/2addr" binary operation. * Provide an "instr" line that specifies an instruction that @@ -5937,12 +5378,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vA/vA+1 <- fv0 - /* ------------------------------ */ .balign 128 .L_op_sub_double_2addr: /* 0xcc */ -/* File: mips/op_sub_double_2addr.S */ -/* File: mips/fbinopWide2addr.S */ /* * Generic 64-bit floating-point "/2addr" binary operation. * Provide an "instr" line that specifies an instruction that @@ -5965,12 +5403,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vA/vA+1 <- fv0 - /* ------------------------------ */ .balign 128 .L_op_mul_double_2addr: /* 0xcd */ -/* File: mips/op_mul_double_2addr.S */ -/* File: mips/fbinopWide2addr.S */ /* * Generic 64-bit floating-point "/2addr" binary operation. * Provide an "instr" line that specifies an instruction that @@ -5993,12 +5428,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vA/vA+1 <- fv0 - /* ------------------------------ */ .balign 128 .L_op_div_double_2addr: /* 0xce */ -/* File: mips/op_div_double_2addr.S */ -/* File: mips/fbinopWide2addr.S */ /* * Generic 64-bit floating-point "/2addr" binary operation. * Provide an "instr" line that specifies an instruction that @@ -6021,12 +5453,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vA/vA+1 <- fv0 - /* ------------------------------ */ .balign 128 .L_op_rem_double_2addr: /* 0xcf */ -/* File: mips/op_rem_double_2addr.S */ -/* File: mips/fbinopWide2addr.S */ /* * Generic 64-bit floating-point "/2addr" binary operation. * Provide an "instr" line that specifies an instruction that @@ -6049,12 +5478,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vA/vA+1 <- fv0 - /* ------------------------------ */ .balign 128 .L_op_add_int_lit16: /* 0xd0 */ -/* File: mips/op_add_int_lit16.S */ -/* File: mips/binopLit16.S */ /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -6083,13 +5509,10 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - /* ------------------------------ */ .balign 128 .L_op_rsub_int: /* 0xd1 */ -/* File: mips/op_rsub_int.S */ /* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ -/* File: mips/binopLit16.S */ /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -6118,12 +5541,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - /* ------------------------------ */ .balign 128 .L_op_mul_int_lit16: /* 0xd2 */ -/* File: mips/op_mul_int_lit16.S */ -/* File: mips/binopLit16.S */ /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -6152,13 +5572,10 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - /* ------------------------------ */ .balign 128 .L_op_div_int_lit16: /* 0xd3 */ -/* File: mips/op_div_int_lit16.S */ #ifdef MIPS32REVGE6 -/* File: mips/binopLit16.S */ /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -6186,9 +5603,7 @@ TODO div a0, a0, a1 # a0 <- op, a0-a3 changed GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - #else -/* File: mips/binopLit16.S */ /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -6216,15 +5631,12 @@ TODO mflo a0 # a0 <- op, a0-a3 changed GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - #endif /* ------------------------------ */ .balign 128 .L_op_rem_int_lit16: /* 0xd4 */ -/* File: mips/op_rem_int_lit16.S */ #ifdef MIPS32REVGE6 -/* File: mips/binopLit16.S */ /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -6252,9 +5664,7 @@ TODO mod a0, a0, a1 # a0 <- op, a0-a3 changed GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - #else -/* File: mips/binopLit16.S */ /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -6282,14 +5692,11 @@ TODO mfhi a0 # a0 <- op, a0-a3 changed GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - #endif /* ------------------------------ */ .balign 128 .L_op_and_int_lit16: /* 0xd5 */ -/* File: mips/op_and_int_lit16.S */ -/* File: mips/binopLit16.S */ /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -6318,12 +5725,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - /* ------------------------------ */ .balign 128 .L_op_or_int_lit16: /* 0xd6 */ -/* File: mips/op_or_int_lit16.S */ -/* File: mips/binopLit16.S */ /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -6352,12 +5756,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - /* ------------------------------ */ .balign 128 .L_op_xor_int_lit16: /* 0xd7 */ -/* File: mips/op_xor_int_lit16.S */ -/* File: mips/binopLit16.S */ /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -6386,12 +5787,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - /* ------------------------------ */ .balign 128 .L_op_add_int_lit8: /* 0xd8 */ -/* File: mips/op_add_int_lit8.S */ -/* File: mips/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -6422,12 +5820,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - /* ------------------------------ */ .balign 128 .L_op_rsub_int_lit8: /* 0xd9 */ -/* File: mips/op_rsub_int_lit8.S */ -/* File: mips/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -6458,12 +5853,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - /* ------------------------------ */ .balign 128 .L_op_mul_int_lit8: /* 0xda */ -/* File: mips/op_mul_int_lit8.S */ -/* File: mips/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -6494,13 +5886,10 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - /* ------------------------------ */ .balign 128 .L_op_div_int_lit8: /* 0xdb */ -/* File: mips/op_div_int_lit8.S */ #ifdef MIPS32REVGE6 -/* File: mips/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -6530,9 +5919,7 @@ TODO div a0, a0, a1 # a0 <- op, a0-a3 changed GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - #else -/* File: mips/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -6562,15 +5949,12 @@ TODO mflo a0 # a0 <- op, a0-a3 changed GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - #endif /* ------------------------------ */ .balign 128 .L_op_rem_int_lit8: /* 0xdc */ -/* File: mips/op_rem_int_lit8.S */ #ifdef MIPS32REVGE6 -/* File: mips/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -6600,9 +5984,7 @@ TODO mod a0, a0, a1 # a0 <- op, a0-a3 changed GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - #else -/* File: mips/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -6632,14 +6014,11 @@ TODO mfhi a0 # a0 <- op, a0-a3 changed GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - #endif /* ------------------------------ */ .balign 128 .L_op_and_int_lit8: /* 0xdd */ -/* File: mips/op_and_int_lit8.S */ -/* File: mips/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -6670,12 +6049,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - /* ------------------------------ */ .balign 128 .L_op_or_int_lit8: /* 0xde */ -/* File: mips/op_or_int_lit8.S */ -/* File: mips/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -6706,12 +6082,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - /* ------------------------------ */ .balign 128 .L_op_xor_int_lit8: /* 0xdf */ -/* File: mips/op_xor_int_lit8.S */ -/* File: mips/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -6742,12 +6115,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - /* ------------------------------ */ .balign 128 .L_op_shl_int_lit8: /* 0xe0 */ -/* File: mips/op_shl_int_lit8.S */ -/* File: mips/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -6778,12 +6148,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - /* ------------------------------ */ .balign 128 .L_op_shr_int_lit8: /* 0xe1 */ -/* File: mips/op_shr_int_lit8.S */ -/* File: mips/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -6814,12 +6181,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - /* ------------------------------ */ .balign 128 .L_op_ushr_int_lit8: /* 0xe2 */ -/* File: mips/op_ushr_int_lit8.S */ -/* File: mips/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -6850,11 +6214,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - /* ------------------------------ */ .balign 128 .L_op_iget_quick: /* 0xe3 */ -/* File: mips/op_iget_quick.S */ /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ /* op vA, vB, offset@CCCC */ GET_OPB(a2) # a2 <- B @@ -6872,7 +6234,6 @@ TODO /* ------------------------------ */ .balign 128 .L_op_iget_wide_quick: /* 0xe4 */ -/* File: mips/op_iget_wide_quick.S */ /* iget-wide-quick vA, vB, offset@CCCC */ GET_OPB(a2) # a2 <- B GET_VREG(a3, a2) # a3 <- object we're operating on @@ -6889,7 +6250,6 @@ TODO /* ------------------------------ */ .balign 128 .L_op_iget_object_quick: /* 0xe5 */ -/* File: mips/op_iget_object_quick.S */ /* For: iget-object-quick */ /* op vA, vB, offset@CCCC */ GET_OPB(a2) # a2 <- B @@ -6908,7 +6268,6 @@ TODO /* ------------------------------ */ .balign 128 .L_op_iput_quick: /* 0xe6 */ -/* File: mips/op_iput_quick.S */ /* For: iput-quick, iput-object-quick */ /* op vA, vB, offset@CCCC */ GET_OPB(a2) # a2 <- B @@ -6927,7 +6286,6 @@ TODO /* ------------------------------ */ .balign 128 .L_op_iput_wide_quick: /* 0xe7 */ -/* File: mips/op_iput_wide_quick.S */ /* iput-wide-quick vA, vB, offset@CCCC */ GET_OPA4(a0) # a0 <- A(+) GET_OPB(a1) # a1 <- B @@ -6947,7 +6305,6 @@ TODO /* ------------------------------ */ .balign 128 .L_op_iput_object_quick: /* 0xe8 */ -/* File: mips/op_iput_object_quick.S */ /* For: iput-object-quick */ /* op vA, vB, offset@CCCC */ EXPORT_PC() @@ -6963,8 +6320,6 @@ TODO /* ------------------------------ */ .balign 128 .L_op_invoke_virtual_quick: /* 0xe9 */ -/* File: mips/op_invoke_virtual_quick.S */ -/* File: mips/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -6984,12 +6339,9 @@ TODO GET_INST_OPCODE(t0) GOTO_OPCODE(t0) - /* ------------------------------ */ .balign 128 .L_op_invoke_virtual_range_quick: /* 0xea */ -/* File: mips/op_invoke_virtual_range_quick.S */ -/* File: mips/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -7009,12 +6361,9 @@ TODO GET_INST_OPCODE(t0) GOTO_OPCODE(t0) - /* ------------------------------ */ .balign 128 .L_op_iput_boolean_quick: /* 0xeb */ -/* File: mips/op_iput_boolean_quick.S */ -/* File: mips/op_iput_quick.S */ /* For: iput-quick, iput-object-quick */ /* op vA, vB, offset@CCCC */ GET_OPB(a2) # a2 <- B @@ -7030,12 +6379,9 @@ TODO sb a0, 0(t0) # obj.field (8/16/32 bits) <- a0 JR(t1) # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_iput_byte_quick: /* 0xec */ -/* File: mips/op_iput_byte_quick.S */ -/* File: mips/op_iput_quick.S */ /* For: iput-quick, iput-object-quick */ /* op vA, vB, offset@CCCC */ GET_OPB(a2) # a2 <- B @@ -7051,12 +6397,9 @@ TODO sb a0, 0(t0) # obj.field (8/16/32 bits) <- a0 JR(t1) # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_iput_char_quick: /* 0xed */ -/* File: mips/op_iput_char_quick.S */ -/* File: mips/op_iput_quick.S */ /* For: iput-quick, iput-object-quick */ /* op vA, vB, offset@CCCC */ GET_OPB(a2) # a2 <- B @@ -7072,12 +6415,9 @@ TODO sh a0, 0(t0) # obj.field (8/16/32 bits) <- a0 JR(t1) # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_iput_short_quick: /* 0xee */ -/* File: mips/op_iput_short_quick.S */ -/* File: mips/op_iput_quick.S */ /* For: iput-quick, iput-object-quick */ /* op vA, vB, offset@CCCC */ GET_OPB(a2) # a2 <- B @@ -7093,12 +6433,9 @@ TODO sh a0, 0(t0) # obj.field (8/16/32 bits) <- a0 JR(t1) # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_iget_boolean_quick: /* 0xef */ -/* File: mips/op_iget_boolean_quick.S */ -/* File: mips/op_iget_quick.S */ /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ /* op vA, vB, offset@CCCC */ GET_OPB(a2) # a2 <- B @@ -7113,12 +6450,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, a2, t0) # fp[A] <- a0 - /* ------------------------------ */ .balign 128 .L_op_iget_byte_quick: /* 0xf0 */ -/* File: mips/op_iget_byte_quick.S */ -/* File: mips/op_iget_quick.S */ /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ /* op vA, vB, offset@CCCC */ GET_OPB(a2) # a2 <- B @@ -7133,12 +6467,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, a2, t0) # fp[A] <- a0 - /* ------------------------------ */ .balign 128 .L_op_iget_char_quick: /* 0xf1 */ -/* File: mips/op_iget_char_quick.S */ -/* File: mips/op_iget_quick.S */ /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ /* op vA, vB, offset@CCCC */ GET_OPB(a2) # a2 <- B @@ -7153,12 +6484,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, a2, t0) # fp[A] <- a0 - /* ------------------------------ */ .balign 128 .L_op_iget_short_quick: /* 0xf2 */ -/* File: mips/op_iget_short_quick.S */ -/* File: mips/op_iget_quick.S */ /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ /* op vA, vB, offset@CCCC */ GET_OPB(a2) # a2 <- B @@ -7173,89 +6501,65 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, a2, t0) # fp[A] <- a0 - /* ------------------------------ */ .balign 128 .L_op_unused_f3: /* 0xf3 */ -/* File: mips/op_unused_f3.S */ -/* File: mips/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_f4: /* 0xf4 */ -/* File: mips/op_unused_f4.S */ -/* File: mips/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_f5: /* 0xf5 */ -/* File: mips/op_unused_f5.S */ -/* File: mips/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_f6: /* 0xf6 */ -/* File: mips/op_unused_f6.S */ -/* File: mips/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_f7: /* 0xf7 */ -/* File: mips/op_unused_f7.S */ -/* File: mips/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_f8: /* 0xf8 */ -/* File: mips/op_unused_f8.S */ -/* File: mips/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_f9: /* 0xf9 */ -/* File: mips/op_unused_f9.S */ -/* File: mips/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_invoke_polymorphic: /* 0xfa */ -/* File: mips/op_invoke_polymorphic.S */ -/* File: mips/invoke_polymorphic.S */ /* * invoke-polymorphic handler wrapper. */ @@ -7275,12 +6579,9 @@ TODO GET_INST_OPCODE(t0) GOTO_OPCODE(t0) - /* ------------------------------ */ .balign 128 .L_op_invoke_polymorphic_range: /* 0xfb */ -/* File: mips/op_invoke_polymorphic_range.S */ -/* File: mips/invoke_polymorphic.S */ /* * invoke-polymorphic handler wrapper. */ @@ -7300,12 +6601,9 @@ TODO GET_INST_OPCODE(t0) GOTO_OPCODE(t0) - /* ------------------------------ */ .balign 128 .L_op_invoke_custom: /* 0xfc */ -/* File: mips/op_invoke_custom.S */ -/* File: mips/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -7325,12 +6623,9 @@ TODO GET_INST_OPCODE(t0) GOTO_OPCODE(t0) - /* ------------------------------ */ .balign 128 .L_op_invoke_custom_range: /* 0xfd */ -/* File: mips/op_invoke_custom_range.S */ -/* File: mips/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -7350,12 +6645,9 @@ TODO GET_INST_OPCODE(t0) GOTO_OPCODE(t0) - /* ------------------------------ */ .balign 128 .L_op_const_method_handle: /* 0xfe */ -/* File: mips/op_const_method_handle.S */ -/* File: mips/const.S */ /* const/class vAA, type@BBBB */ /* const/method-handle vAA, method_handle@BBBB */ /* const/method-type vAA, proto@BBBB */ @@ -7373,12 +6665,9 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST GOTO_OPCODE(t0) # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_const_method_type: /* 0xff */ -/* File: mips/op_const_method_type.S */ -/* File: mips/const.S */ /* const/class vAA, type@BBBB */ /* const/method-handle vAA, method_handle@BBBB */ /* const/method-type vAA, proto@BBBB */ @@ -7396,29 +6685,16 @@ TODO GET_INST_OPCODE(t0) # extract opcode from rINST GOTO_OPCODE(t0) # jump to next instruction - .balign 128 -/* File: mips/instruction_end.S */ .global artMterpAsmInstructionEnd artMterpAsmInstructionEnd: - -/* - * =========================================================================== - * Sister implementations - * =========================================================================== - */ -/* File: mips/instruction_start_sister.S */ - .global artMterpAsmSisterStart .text .balign 4 artMterpAsmSisterStart: - -/* continuation for op_float_to_long */ - #ifndef MIPS32REVGE6 .Lop_float_to_long_get_opcode: GET_INST_OPCODE(t1) # extract opcode from rINST @@ -7426,8 +6702,6 @@ artMterpAsmSisterStart: SET_VREG64_GOTO(rRESULT0, rRESULT1, rOBJ, t1) # vA/vA+1 <- v0/v1 #endif -/* continuation for op_double_to_long */ - #ifndef MIPS32REVGE6 .Lop_double_to_long_get_opcode: GET_INST_OPCODE(t1) # extract opcode from rINST @@ -7435,58 +6709,39 @@ artMterpAsmSisterStart: SET_VREG64_GOTO(rRESULT0, rRESULT1, rOBJ, t1) # vA/vA+1 <- v0/v1 #endif -/* continuation for op_mul_long */ - .Lop_mul_long_finish: GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG64_GOTO(v0, v1, a0, t0) # vAA/vAA+1 <- v0(low)/v1(high) -/* continuation for op_shl_long */ - .Lop_shl_long_finish: SET_VREG64_GOTO(zero, v0, t2, t0) # vAA/vAA+1 <- rlo/rhi -/* continuation for op_shr_long */ - .Lop_shr_long_finish: sra a3, a1, 31 # a3<- sign(ah) SET_VREG64_GOTO(v1, a3, t3, t0) # vAA/VAA+1 <- rlo/rhi -/* continuation for op_ushr_long */ - .Lop_ushr_long_finish: SET_VREG64_GOTO(v1, zero, rOBJ, t0) # vAA/vAA+1 <- rlo/rhi -/* continuation for op_shl_long_2addr */ - .Lop_shl_long_2addr_finish: SET_VREG64_GOTO(zero, v0, rOBJ, t0) # vA/vA+1 <- rlo/rhi -/* continuation for op_shr_long_2addr */ - .Lop_shr_long_2addr_finish: sra a3, a1, 31 # a3<- sign(ah) SET_VREG64_GOTO(v1, a3, t2, t0) # vA/vA+1 <- rlo/rhi -/* continuation for op_ushr_long_2addr */ - .Lop_ushr_long_2addr_finish: SET_VREG64_GOTO(v1, zero, t3, t0) # vA/vA+1 <- rlo/rhi -/* File: mips/instruction_end_sister.S */ .global artMterpAsmSisterEnd artMterpAsmSisterEnd: -/* File: mips/instruction_start_alt.S */ - .global artMterpAsmAltInstructionStart artMterpAsmAltInstructionStart = .L_ALT_op_nop .text - /* ------------------------------ */ .balign 128 .L_ALT_op_nop: /* 0x00 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7504,7 +6759,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move: /* 0x01 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7522,7 +6776,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_from16: /* 0x02 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7540,7 +6793,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_16: /* 0x03 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7558,7 +6810,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_wide: /* 0x04 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7576,7 +6827,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_wide_from16: /* 0x05 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7594,7 +6844,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_wide_16: /* 0x06 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7612,7 +6861,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_object: /* 0x07 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7630,7 +6878,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_object_from16: /* 0x08 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7648,7 +6895,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_object_16: /* 0x09 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7666,7 +6912,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_result: /* 0x0a */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7684,7 +6929,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_result_wide: /* 0x0b */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7702,7 +6946,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_result_object: /* 0x0c */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7720,7 +6963,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_exception: /* 0x0d */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7738,7 +6980,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_return_void: /* 0x0e */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7756,7 +6997,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_return: /* 0x0f */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7774,7 +7014,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_return_wide: /* 0x10 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7792,7 +7031,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_return_object: /* 0x11 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7810,7 +7048,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_4: /* 0x12 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7828,7 +7065,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_16: /* 0x13 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7846,7 +7082,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const: /* 0x14 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7864,7 +7099,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_high16: /* 0x15 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7882,7 +7116,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_wide_16: /* 0x16 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7900,7 +7133,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_wide_32: /* 0x17 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7918,7 +7150,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_wide: /* 0x18 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7936,7 +7167,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_wide_high16: /* 0x19 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7954,7 +7184,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_string: /* 0x1a */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7972,7 +7201,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_string_jumbo: /* 0x1b */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7990,7 +7218,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_class: /* 0x1c */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8008,7 +7235,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_monitor_enter: /* 0x1d */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8026,7 +7252,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_monitor_exit: /* 0x1e */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8044,7 +7269,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_check_cast: /* 0x1f */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8062,7 +7286,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_instance_of: /* 0x20 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8080,7 +7303,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_array_length: /* 0x21 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8098,7 +7320,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_new_instance: /* 0x22 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8116,7 +7337,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_new_array: /* 0x23 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8134,7 +7354,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_filled_new_array: /* 0x24 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8152,7 +7371,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_filled_new_array_range: /* 0x25 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8170,7 +7388,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_fill_array_data: /* 0x26 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8188,7 +7405,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_throw: /* 0x27 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8206,7 +7422,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_goto: /* 0x28 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8224,7 +7439,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_goto_16: /* 0x29 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8242,7 +7456,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_goto_32: /* 0x2a */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8260,7 +7473,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_packed_switch: /* 0x2b */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8278,7 +7490,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sparse_switch: /* 0x2c */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8296,7 +7507,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_cmpl_float: /* 0x2d */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8314,7 +7524,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_cmpg_float: /* 0x2e */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8332,7 +7541,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_cmpl_double: /* 0x2f */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8350,7 +7558,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_cmpg_double: /* 0x30 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8368,7 +7575,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_cmp_long: /* 0x31 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8386,7 +7592,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_eq: /* 0x32 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8404,7 +7609,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_ne: /* 0x33 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8422,7 +7626,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_lt: /* 0x34 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8440,7 +7643,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_ge: /* 0x35 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8458,7 +7660,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_gt: /* 0x36 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8476,7 +7677,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_le: /* 0x37 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8494,7 +7694,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_eqz: /* 0x38 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8512,7 +7711,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_nez: /* 0x39 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8530,7 +7728,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_ltz: /* 0x3a */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8548,7 +7745,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_gez: /* 0x3b */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8566,7 +7762,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_gtz: /* 0x3c */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8584,7 +7779,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_lez: /* 0x3d */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8602,7 +7796,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_3e: /* 0x3e */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8620,7 +7813,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_3f: /* 0x3f */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8638,7 +7830,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_40: /* 0x40 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8656,7 +7847,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_41: /* 0x41 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8674,7 +7864,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_42: /* 0x42 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8692,7 +7881,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_43: /* 0x43 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8710,7 +7898,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aget: /* 0x44 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8728,7 +7915,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aget_wide: /* 0x45 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8746,7 +7932,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aget_object: /* 0x46 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8764,7 +7949,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aget_boolean: /* 0x47 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8782,7 +7966,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aget_byte: /* 0x48 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8800,7 +7983,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aget_char: /* 0x49 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8818,7 +8000,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aget_short: /* 0x4a */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8836,7 +8017,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aput: /* 0x4b */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8854,7 +8034,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aput_wide: /* 0x4c */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8872,7 +8051,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aput_object: /* 0x4d */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8890,7 +8068,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aput_boolean: /* 0x4e */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8908,7 +8085,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aput_byte: /* 0x4f */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8926,7 +8102,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aput_char: /* 0x50 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8944,7 +8119,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aput_short: /* 0x51 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8962,7 +8136,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget: /* 0x52 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8980,7 +8153,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_wide: /* 0x53 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8998,7 +8170,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_object: /* 0x54 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9016,7 +8187,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_boolean: /* 0x55 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9034,7 +8204,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_byte: /* 0x56 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9052,7 +8221,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_char: /* 0x57 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9070,7 +8238,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_short: /* 0x58 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9088,7 +8255,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput: /* 0x59 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9106,7 +8272,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_wide: /* 0x5a */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9124,7 +8289,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_object: /* 0x5b */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9142,7 +8306,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_boolean: /* 0x5c */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9160,7 +8323,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_byte: /* 0x5d */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9178,7 +8340,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_char: /* 0x5e */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9196,7 +8357,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_short: /* 0x5f */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9214,7 +8374,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sget: /* 0x60 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9232,7 +8391,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sget_wide: /* 0x61 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9250,7 +8408,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sget_object: /* 0x62 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9268,7 +8425,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sget_boolean: /* 0x63 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9286,7 +8442,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sget_byte: /* 0x64 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9304,7 +8459,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sget_char: /* 0x65 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9322,7 +8476,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sget_short: /* 0x66 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9340,7 +8493,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sput: /* 0x67 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9358,7 +8510,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sput_wide: /* 0x68 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9376,7 +8527,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sput_object: /* 0x69 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9394,7 +8544,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sput_boolean: /* 0x6a */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9412,7 +8561,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sput_byte: /* 0x6b */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9430,7 +8578,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sput_char: /* 0x6c */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9448,7 +8595,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sput_short: /* 0x6d */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9466,7 +8612,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_virtual: /* 0x6e */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9484,7 +8629,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_super: /* 0x6f */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9502,7 +8646,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_direct: /* 0x70 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9520,7 +8663,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_static: /* 0x71 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9538,7 +8680,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_interface: /* 0x72 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9556,7 +8697,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_return_void_no_barrier: /* 0x73 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9574,7 +8714,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_virtual_range: /* 0x74 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9592,7 +8731,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_super_range: /* 0x75 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9610,7 +8748,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_direct_range: /* 0x76 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9628,7 +8765,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_static_range: /* 0x77 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9646,7 +8782,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_interface_range: /* 0x78 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9664,7 +8799,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_79: /* 0x79 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9682,7 +8816,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_7a: /* 0x7a */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9700,7 +8833,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_neg_int: /* 0x7b */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9718,7 +8850,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_not_int: /* 0x7c */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9736,7 +8867,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_neg_long: /* 0x7d */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9754,7 +8884,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_not_long: /* 0x7e */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9772,7 +8901,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_neg_float: /* 0x7f */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9790,7 +8918,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_neg_double: /* 0x80 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9808,7 +8935,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_int_to_long: /* 0x81 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9826,7 +8952,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_int_to_float: /* 0x82 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9844,7 +8969,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_int_to_double: /* 0x83 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9862,7 +8986,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_long_to_int: /* 0x84 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9880,7 +9003,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_long_to_float: /* 0x85 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9898,7 +9020,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_long_to_double: /* 0x86 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9916,7 +9037,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_float_to_int: /* 0x87 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9934,7 +9054,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_float_to_long: /* 0x88 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9952,7 +9071,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_float_to_double: /* 0x89 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9970,7 +9088,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_double_to_int: /* 0x8a */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9988,7 +9105,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_double_to_long: /* 0x8b */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10006,7 +9122,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_double_to_float: /* 0x8c */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10024,7 +9139,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_int_to_byte: /* 0x8d */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10042,7 +9156,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_int_to_char: /* 0x8e */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10060,7 +9173,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_int_to_short: /* 0x8f */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10078,7 +9190,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_int: /* 0x90 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10096,7 +9207,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_int: /* 0x91 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10114,7 +9224,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_int: /* 0x92 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10132,7 +9241,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_int: /* 0x93 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10150,7 +9258,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_int: /* 0x94 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10168,7 +9275,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_and_int: /* 0x95 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10186,7 +9292,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_or_int: /* 0x96 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10204,7 +9309,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_xor_int: /* 0x97 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10222,7 +9326,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shl_int: /* 0x98 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10240,7 +9343,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shr_int: /* 0x99 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10258,7 +9360,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_ushr_int: /* 0x9a */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10276,7 +9377,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_long: /* 0x9b */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10294,7 +9394,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_long: /* 0x9c */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10312,7 +9411,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_long: /* 0x9d */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10330,7 +9428,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_long: /* 0x9e */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10348,7 +9445,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_long: /* 0x9f */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10366,7 +9462,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_and_long: /* 0xa0 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10384,7 +9479,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_or_long: /* 0xa1 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10402,7 +9496,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_xor_long: /* 0xa2 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10420,7 +9513,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shl_long: /* 0xa3 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10438,7 +9530,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shr_long: /* 0xa4 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10456,7 +9547,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_ushr_long: /* 0xa5 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10474,7 +9564,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_float: /* 0xa6 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10492,7 +9581,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_float: /* 0xa7 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10510,7 +9598,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_float: /* 0xa8 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10528,7 +9615,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_float: /* 0xa9 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10546,7 +9632,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_float: /* 0xaa */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10564,7 +9649,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_double: /* 0xab */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10582,7 +9666,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_double: /* 0xac */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10600,7 +9683,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_double: /* 0xad */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10618,7 +9700,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_double: /* 0xae */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10636,7 +9717,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_double: /* 0xaf */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10654,7 +9734,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_int_2addr: /* 0xb0 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10672,7 +9751,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_int_2addr: /* 0xb1 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10690,7 +9768,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_int_2addr: /* 0xb2 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10708,7 +9785,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_int_2addr: /* 0xb3 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10726,7 +9802,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_int_2addr: /* 0xb4 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10744,7 +9819,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_and_int_2addr: /* 0xb5 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10762,7 +9836,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_or_int_2addr: /* 0xb6 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10780,7 +9853,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_xor_int_2addr: /* 0xb7 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10798,7 +9870,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shl_int_2addr: /* 0xb8 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10816,7 +9887,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shr_int_2addr: /* 0xb9 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10834,7 +9904,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_ushr_int_2addr: /* 0xba */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10852,7 +9921,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_long_2addr: /* 0xbb */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10870,7 +9938,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_long_2addr: /* 0xbc */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10888,7 +9955,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_long_2addr: /* 0xbd */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10906,7 +9972,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_long_2addr: /* 0xbe */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10924,7 +9989,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_long_2addr: /* 0xbf */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10942,7 +10006,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_and_long_2addr: /* 0xc0 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10960,7 +10023,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_or_long_2addr: /* 0xc1 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10978,7 +10040,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_xor_long_2addr: /* 0xc2 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10996,7 +10057,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shl_long_2addr: /* 0xc3 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11014,7 +10074,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shr_long_2addr: /* 0xc4 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11032,7 +10091,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_ushr_long_2addr: /* 0xc5 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11050,7 +10108,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_float_2addr: /* 0xc6 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11068,7 +10125,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_float_2addr: /* 0xc7 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11086,7 +10142,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_float_2addr: /* 0xc8 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11104,7 +10159,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_float_2addr: /* 0xc9 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11122,7 +10176,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_float_2addr: /* 0xca */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11140,7 +10193,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_double_2addr: /* 0xcb */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11158,7 +10210,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_double_2addr: /* 0xcc */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11176,7 +10227,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_double_2addr: /* 0xcd */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11194,7 +10244,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_double_2addr: /* 0xce */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11212,7 +10261,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_double_2addr: /* 0xcf */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11230,7 +10278,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_int_lit16: /* 0xd0 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11248,7 +10295,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rsub_int: /* 0xd1 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11266,7 +10312,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_int_lit16: /* 0xd2 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11284,7 +10329,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_int_lit16: /* 0xd3 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11302,7 +10346,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_int_lit16: /* 0xd4 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11320,7 +10363,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_and_int_lit16: /* 0xd5 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11338,7 +10380,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_or_int_lit16: /* 0xd6 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11356,7 +10397,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_xor_int_lit16: /* 0xd7 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11374,7 +10414,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_int_lit8: /* 0xd8 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11392,7 +10431,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rsub_int_lit8: /* 0xd9 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11410,7 +10448,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_int_lit8: /* 0xda */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11428,7 +10465,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_int_lit8: /* 0xdb */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11446,7 +10482,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_int_lit8: /* 0xdc */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11464,7 +10499,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_and_int_lit8: /* 0xdd */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11482,7 +10516,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_or_int_lit8: /* 0xde */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11500,7 +10533,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_xor_int_lit8: /* 0xdf */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11518,7 +10550,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shl_int_lit8: /* 0xe0 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11536,7 +10567,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shr_int_lit8: /* 0xe1 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11554,7 +10584,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_ushr_int_lit8: /* 0xe2 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11572,7 +10601,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_quick: /* 0xe3 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11590,7 +10618,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_wide_quick: /* 0xe4 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11608,7 +10635,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_object_quick: /* 0xe5 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11626,7 +10652,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_quick: /* 0xe6 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11644,7 +10669,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_wide_quick: /* 0xe7 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11662,7 +10686,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_object_quick: /* 0xe8 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11680,7 +10703,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_virtual_quick: /* 0xe9 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11698,7 +10720,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_virtual_range_quick: /* 0xea */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11716,7 +10737,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_boolean_quick: /* 0xeb */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11734,7 +10754,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_byte_quick: /* 0xec */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11752,7 +10771,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_char_quick: /* 0xed */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11770,7 +10788,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_short_quick: /* 0xee */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11788,7 +10805,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_boolean_quick: /* 0xef */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11806,7 +10822,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_byte_quick: /* 0xf0 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11824,7 +10839,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_char_quick: /* 0xf1 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11842,7 +10856,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_short_quick: /* 0xf2 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11860,7 +10873,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_f3: /* 0xf3 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11878,7 +10890,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_f4: /* 0xf4 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11896,7 +10907,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_f5: /* 0xf5 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11914,7 +10924,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_f6: /* 0xf6 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11932,7 +10941,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_f7: /* 0xf7 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11950,7 +10958,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_f8: /* 0xf8 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11968,7 +10975,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_f9: /* 0xf9 */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11986,7 +10992,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_polymorphic: /* 0xfa */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -12004,7 +11009,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_polymorphic_range: /* 0xfb */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -12022,7 +11026,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_custom: /* 0xfc */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -12040,7 +11043,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_custom_range: /* 0xfd */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -12058,7 +11060,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_method_handle: /* 0xfe */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -12076,7 +11077,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_method_type: /* 0xff */ -/* File: mips/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -12092,12 +11092,9 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) .balign 128 -/* File: mips/instruction_end_alt.S */ .global artMterpAsmAltInstructionEnd artMterpAsmAltInstructionEnd: - -/* File: mips/footer.S */ /* * =========================================================================== * Common subroutines and data @@ -12386,4 +11383,3 @@ MterpProfileActive: .cfi_endproc .end ExecuteMterpImpl - diff --git a/runtime/interpreter/mterp/out/mterp_mips64.S b/runtime/interpreter/mterp/out/mterp_mips64.S index 40a8396f77..cf95a57a0e 100644 --- a/runtime/interpreter/mterp/out/mterp_mips64.S +++ b/runtime/interpreter/mterp/out/mterp_mips64.S @@ -1,10 +1,4 @@ -/* - * This file was generated automatically by gen-mterp.py for 'mips64'. - * - * --> DO NOT EDIT <-- - */ - -/* File: mips64/header.S */ +/* DO NOT EDIT: This file was generated by gen-mterp.py. */ /* * Copyright (C) 2016 The Android Open Source Project * @@ -333,8 +327,6 @@ The following registers have fixed assignments: #define LONG_MIN 0x8000000000000000 #define LONG_MIN_AS_FLOAT 0xDF000000 #define LONG_MIN_AS_DOUBLE 0xC3E0000000000000 - -/* File: mips64/entry.S */ /* * Copyright (C) 2016 The Android Open Source Project * @@ -430,16 +422,12 @@ ExecuteMterpImpl: /* NOTE: no fallthrough */ -/* File: mips64/instruction_start.S */ - .global artMterpAsmInstructionStart artMterpAsmInstructionStart = .L_op_nop .text - /* ------------------------------ */ .balign 128 .L_op_nop: /* 0x00 */ -/* File: mips64/op_nop.S */ FETCH_ADVANCE_INST 1 # advance rPC, load rINST GET_INST_OPCODE v0 # extract opcode from rINST GOTO_OPCODE v0 # jump to next instruction @@ -447,7 +435,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move: /* 0x01 */ -/* File: mips64/op_move.S */ /* for move, move-object, long-to-int */ /* op vA, vB */ ext a2, rINST, 8, 4 # a2 <- A @@ -465,7 +452,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_from16: /* 0x02 */ -/* File: mips64/op_move_from16.S */ /* for: move/from16, move-object/from16 */ /* op vAA, vBBBB */ lhu a3, 2(rPC) # a3 <- BBBB @@ -483,7 +469,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_16: /* 0x03 */ -/* File: mips64/op_move_16.S */ /* for: move/16, move-object/16 */ /* op vAAAA, vBBBB */ lhu a3, 4(rPC) # a3 <- BBBB @@ -501,7 +486,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_wide: /* 0x04 */ -/* File: mips64/op_move_wide.S */ /* move-wide vA, vB */ /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ ext a3, rINST, 12, 4 # a3 <- B @@ -515,7 +499,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_wide_from16: /* 0x05 */ -/* File: mips64/op_move_wide_from16.S */ /* move-wide/from16 vAA, vBBBB */ /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ lhu a3, 2(rPC) # a3 <- BBBB @@ -529,7 +512,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_wide_16: /* 0x06 */ -/* File: mips64/op_move_wide_16.S */ /* move-wide/16 vAAAA, vBBBB */ /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ lhu a3, 4(rPC) # a3 <- BBBB @@ -543,8 +525,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_object: /* 0x07 */ -/* File: mips64/op_move_object.S */ -/* File: mips64/op_move.S */ /* for move, move-object, long-to-int */ /* op vA, vB */ ext a2, rINST, 8, 4 # a2 <- A @@ -559,12 +539,9 @@ artMterpAsmInstructionStart = .L_op_nop .endif GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_move_object_from16: /* 0x08 */ -/* File: mips64/op_move_object_from16.S */ -/* File: mips64/op_move_from16.S */ /* for: move/from16, move-object/from16 */ /* op vAA, vBBBB */ lhu a3, 2(rPC) # a3 <- BBBB @@ -579,12 +556,9 @@ artMterpAsmInstructionStart = .L_op_nop .endif GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_move_object_16: /* 0x09 */ -/* File: mips64/op_move_object_16.S */ -/* File: mips64/op_move_16.S */ /* for: move/16, move-object/16 */ /* op vAAAA, vBBBB */ lhu a3, 4(rPC) # a3 <- BBBB @@ -599,11 +573,9 @@ artMterpAsmInstructionStart = .L_op_nop .endif GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_move_result: /* 0x0a */ -/* File: mips64/op_move_result.S */ /* for: move-result, move-result-object */ /* op vAA */ srl a2, rINST, 8 # a2 <- AA @@ -621,7 +593,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_result_wide: /* 0x0b */ -/* File: mips64/op_move_result_wide.S */ /* for: move-result-wide */ /* op vAA */ srl a2, rINST, 8 # a2 <- AA @@ -635,8 +606,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_result_object: /* 0x0c */ -/* File: mips64/op_move_result_object.S */ -/* File: mips64/op_move_result.S */ /* for: move-result, move-result-object */ /* op vAA */ srl a2, rINST, 8 # a2 <- AA @@ -651,11 +620,9 @@ artMterpAsmInstructionStart = .L_op_nop .endif GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_move_exception: /* 0x0d */ -/* File: mips64/op_move_exception.S */ /* move-exception vAA */ srl a2, rINST, 8 # a2 <- AA ld a0, THREAD_EXCEPTION_OFFSET(rSELF) # load exception obj @@ -668,7 +635,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_return_void: /* 0x0e */ -/* File: mips64/op_return_void.S */ .extern MterpThreadFenceForConstructor .extern MterpSuspendCheck jal MterpThreadFenceForConstructor @@ -684,7 +650,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_return: /* 0x0f */ -/* File: mips64/op_return.S */ /* * Return a 32-bit value. * @@ -707,7 +672,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_return_wide: /* 0x10 */ -/* File: mips64/op_return_wide.S */ /* * Return a 64-bit value. */ @@ -729,8 +693,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_return_object: /* 0x11 */ -/* File: mips64/op_return_object.S */ -/* File: mips64/op_return.S */ /* * Return a 32-bit value. * @@ -750,11 +712,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_VREG_U a0, a2 # a0 <- vAA b MterpReturn - /* ------------------------------ */ .balign 128 .L_op_const_4: /* 0x12 */ -/* File: mips64/op_const_4.S */ /* const/4 vA, #+B */ ext a2, rINST, 8, 4 # a2 <- A seh a0, rINST # sign extend B in rINST @@ -767,7 +727,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_16: /* 0x13 */ -/* File: mips64/op_const_16.S */ /* const/16 vAA, #+BBBB */ srl a2, rINST, 8 # a2 <- AA lh a0, 2(rPC) # a0 <- sign-extended BBBB @@ -779,7 +738,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const: /* 0x14 */ -/* File: mips64/op_const.S */ /* const vAA, #+BBBBbbbb */ srl a2, rINST, 8 # a2 <- AA lh a0, 2(rPC) # a0 <- bbbb (low) @@ -793,7 +751,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_high16: /* 0x15 */ -/* File: mips64/op_const_high16.S */ /* const/high16 vAA, #+BBBB0000 */ srl a2, rINST, 8 # a2 <- AA lh a0, 2(rPC) # a0 <- BBBB @@ -806,7 +763,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_wide_16: /* 0x16 */ -/* File: mips64/op_const_wide_16.S */ /* const-wide/16 vAA, #+BBBB */ srl a2, rINST, 8 # a2 <- AA lh a0, 2(rPC) # a0 <- sign-extended BBBB @@ -818,7 +774,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_wide_32: /* 0x17 */ -/* File: mips64/op_const_wide_32.S */ /* const-wide/32 vAA, #+BBBBbbbb */ srl a2, rINST, 8 # a2 <- AA lh a0, 2(rPC) # a0 <- bbbb (low) @@ -832,7 +787,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_wide: /* 0x18 */ -/* File: mips64/op_const_wide.S */ /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ srl a4, rINST, 8 # a4 <- AA lh a0, 2(rPC) # a0 <- bbbb (low) @@ -850,7 +804,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_wide_high16: /* 0x19 */ -/* File: mips64/op_const_wide_high16.S */ /* const-wide/high16 vAA, #+BBBB000000000000 */ srl a2, rINST, 8 # a2 <- AA lh a0, 2(rPC) # a0 <- BBBB @@ -863,8 +816,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_string: /* 0x1a */ -/* File: mips64/op_const_string.S */ -/* File: mips64/const.S */ /* const/class vAA, type@BBBB */ /* const/method-handle vAA, method_handle@BBBB */ /* const/method-type vAA, proto@BBBB */ @@ -882,11 +833,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE v0 # extract opcode from rINST GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_const_string_jumbo: /* 0x1b */ -/* File: mips64/op_const_string_jumbo.S */ /* const/string vAA, String//BBBBBBBB */ .extern MterpConstString EXPORT_PC @@ -906,8 +855,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_class: /* 0x1c */ -/* File: mips64/op_const_class.S */ -/* File: mips64/const.S */ /* const/class vAA, type@BBBB */ /* const/method-handle vAA, method_handle@BBBB */ /* const/method-type vAA, proto@BBBB */ @@ -925,11 +872,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE v0 # extract opcode from rINST GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_monitor_enter: /* 0x1d */ -/* File: mips64/op_monitor_enter.S */ /* * Synchronize on an object. */ @@ -948,7 +893,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_monitor_exit: /* 0x1e */ -/* File: mips64/op_monitor_exit.S */ /* * Unlock an object. * @@ -971,7 +915,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_check_cast: /* 0x1f */ -/* File: mips64/op_check_cast.S */ /* * Check to see if a cast from one class to another is allowed. */ @@ -993,7 +936,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_instance_of: /* 0x20 */ -/* File: mips64/op_instance_of.S */ /* * Check to see if an object reference is an instance of a class. * @@ -1021,7 +963,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_array_length: /* 0x21 */ -/* File: mips64/op_array_length.S */ /* * Return the length of an array. */ @@ -1038,7 +979,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_new_instance: /* 0x22 */ -/* File: mips64/op_new_instance.S */ /* * Create a new instance of a class. */ @@ -1057,7 +997,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_new_array: /* 0x23 */ -/* File: mips64/op_new_array.S */ /* * Allocate an array of objects, specified with the array class * and a count. @@ -1081,7 +1020,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_filled_new_array: /* 0x24 */ -/* File: mips64/op_filled_new_array.S */ /* * Create a new array with elements filled from registers. * @@ -1103,8 +1041,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_filled_new_array_range: /* 0x25 */ -/* File: mips64/op_filled_new_array_range.S */ -/* File: mips64/op_filled_new_array.S */ /* * Create a new array with elements filled from registers. * @@ -1123,11 +1059,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE v0 # extract opcode from rINST GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_fill_array_data: /* 0x26 */ -/* File: mips64/op_fill_array_data.S */ /* fill-array-data vAA, +BBBBBBBB */ .extern MterpFillArrayData EXPORT_PC @@ -1146,7 +1080,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_throw: /* 0x27 */ -/* File: mips64/op_throw.S */ /* * Throw an exception object in the current thread. */ @@ -1161,7 +1094,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_goto: /* 0x28 */ -/* File: mips64/op_goto.S */ /* * Unconditional branch, 8-bit offset. * @@ -1176,7 +1108,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_goto_16: /* 0x29 */ -/* File: mips64/op_goto_16.S */ /* * Unconditional branch, 16-bit offset. * @@ -1190,7 +1121,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_goto_32: /* 0x2a */ -/* File: mips64/op_goto_32.S */ /* * Unconditional branch, 32-bit offset. * @@ -1209,7 +1139,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_packed_switch: /* 0x2b */ -/* File: mips64/op_packed_switch.S */ /* * Handle a packed-switch or sparse-switch instruction. In both cases * we decode it and hand it off to a helper function. @@ -1234,8 +1163,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_sparse_switch: /* 0x2c */ -/* File: mips64/op_sparse_switch.S */ -/* File: mips64/op_packed_switch.S */ /* * Handle a packed-switch or sparse-switch instruction. In both cases * we decode it and hand it off to a helper function. @@ -1257,12 +1184,9 @@ artMterpAsmInstructionStart = .L_op_nop move rINST, v0 b MterpCommonTakenBranchNoFlags - /* ------------------------------ */ .balign 128 .L_op_cmpl_float: /* 0x2d */ -/* File: mips64/op_cmpl_float.S */ -/* File: mips64/fcmp.S */ /* * Compare two floating-point values. Puts 0, 1, or -1 into the * destination register based on the results of the comparison. @@ -1295,12 +1219,9 @@ artMterpAsmInstructionStart = .L_op_nop SET_VREG a0, a4 # vAA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_cmpg_float: /* 0x2e */ -/* File: mips64/op_cmpg_float.S */ -/* File: mips64/fcmp.S */ /* * Compare two floating-point values. Puts 0, 1, or -1 into the * destination register based on the results of the comparison. @@ -1333,12 +1254,9 @@ artMterpAsmInstructionStart = .L_op_nop SET_VREG a0, a4 # vAA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_cmpl_double: /* 0x2f */ -/* File: mips64/op_cmpl_double.S */ -/* File: mips64/fcmpWide.S */ /* * Compare two floating-point values. Puts 0, 1, or -1 into the * destination register based on the results of the comparison. @@ -1371,12 +1289,9 @@ artMterpAsmInstructionStart = .L_op_nop SET_VREG a0, a4 # vAA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_cmpg_double: /* 0x30 */ -/* File: mips64/op_cmpg_double.S */ -/* File: mips64/fcmpWide.S */ /* * Compare two floating-point values. Puts 0, 1, or -1 into the * destination register based on the results of the comparison. @@ -1409,11 +1324,9 @@ artMterpAsmInstructionStart = .L_op_nop SET_VREG a0, a4 # vAA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_cmp_long: /* 0x31 */ -/* File: mips64/op_cmp_long.S */ /* cmp-long vAA, vBB, vCC */ lbu a2, 2(rPC) # a2 <- BB lbu a3, 3(rPC) # a3 <- CC @@ -1431,8 +1344,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_if_eq: /* 0x32 */ -/* File: mips64/op_if_eq.S */ -/* File: mips64/bincmp.S */ /* * Generic two-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform, e.g. for @@ -1453,12 +1364,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE v0 # extract opcode from rINST GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_ne: /* 0x33 */ -/* File: mips64/op_if_ne.S */ -/* File: mips64/bincmp.S */ /* * Generic two-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform, e.g. for @@ -1479,12 +1387,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE v0 # extract opcode from rINST GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_lt: /* 0x34 */ -/* File: mips64/op_if_lt.S */ -/* File: mips64/bincmp.S */ /* * Generic two-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform, e.g. for @@ -1505,12 +1410,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE v0 # extract opcode from rINST GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_ge: /* 0x35 */ -/* File: mips64/op_if_ge.S */ -/* File: mips64/bincmp.S */ /* * Generic two-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform, e.g. for @@ -1531,12 +1433,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE v0 # extract opcode from rINST GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_gt: /* 0x36 */ -/* File: mips64/op_if_gt.S */ -/* File: mips64/bincmp.S */ /* * Generic two-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform, e.g. for @@ -1557,12 +1456,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE v0 # extract opcode from rINST GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_le: /* 0x37 */ -/* File: mips64/op_if_le.S */ -/* File: mips64/bincmp.S */ /* * Generic two-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform, e.g. for @@ -1583,12 +1479,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE v0 # extract opcode from rINST GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_eqz: /* 0x38 */ -/* File: mips64/op_if_eqz.S */ -/* File: mips64/zcmp.S */ /* * Generic one-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform, e.g. for @@ -1607,12 +1500,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE v0 # extract opcode from rINST GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_nez: /* 0x39 */ -/* File: mips64/op_if_nez.S */ -/* File: mips64/zcmp.S */ /* * Generic one-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform, e.g. for @@ -1631,12 +1521,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE v0 # extract opcode from rINST GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_ltz: /* 0x3a */ -/* File: mips64/op_if_ltz.S */ -/* File: mips64/zcmp.S */ /* * Generic one-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform, e.g. for @@ -1655,12 +1542,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE v0 # extract opcode from rINST GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_gez: /* 0x3b */ -/* File: mips64/op_if_gez.S */ -/* File: mips64/zcmp.S */ /* * Generic one-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform, e.g. for @@ -1679,12 +1563,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE v0 # extract opcode from rINST GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_gtz: /* 0x3c */ -/* File: mips64/op_if_gtz.S */ -/* File: mips64/zcmp.S */ /* * Generic one-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform, e.g. for @@ -1703,12 +1584,9 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE v0 # extract opcode from rINST GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_if_lez: /* 0x3d */ -/* File: mips64/op_if_lez.S */ -/* File: mips64/zcmp.S */ /* * Generic one-operand compare-and-branch operation. Provide a "condition" * fragment that specifies the comparison to perform, e.g. for @@ -1727,77 +1605,57 @@ artMterpAsmInstructionStart = .L_op_nop GET_INST_OPCODE v0 # extract opcode from rINST GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_unused_3e: /* 0x3e */ -/* File: mips64/op_unused_3e.S */ -/* File: mips64/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_3f: /* 0x3f */ -/* File: mips64/op_unused_3f.S */ -/* File: mips64/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_40: /* 0x40 */ -/* File: mips64/op_unused_40.S */ -/* File: mips64/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_41: /* 0x41 */ -/* File: mips64/op_unused_41.S */ -/* File: mips64/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_42: /* 0x42 */ -/* File: mips64/op_unused_42.S */ -/* File: mips64/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_43: /* 0x43 */ -/* File: mips64/op_unused_43.S */ -/* File: mips64/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_aget: /* 0x44 */ -/* File: mips64/op_aget.S */ /* * Array get, 32 bits or less. vAA <- vBB[vCC]. * @@ -1830,7 +1688,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_aget_wide: /* 0x45 */ -/* File: mips64/op_aget_wide.S */ /* * Array get, 64 bits. vAA <- vBB[vCC]. * @@ -1856,7 +1713,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_aget_object: /* 0x46 */ -/* File: mips64/op_aget_object.S */ /* * Array object get. vAA <- vBB[vCC]. * @@ -1882,8 +1738,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_aget_boolean: /* 0x47 */ -/* File: mips64/op_aget_boolean.S */ -/* File: mips64/op_aget.S */ /* * Array get, 32 bits or less. vAA <- vBB[vCC]. * @@ -1913,12 +1767,9 @@ artMterpAsmInstructionStart = .L_op_nop SET_VREG a2, a4 # vAA <- a2 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_aget_byte: /* 0x48 */ -/* File: mips64/op_aget_byte.S */ -/* File: mips64/op_aget.S */ /* * Array get, 32 bits or less. vAA <- vBB[vCC]. * @@ -1948,12 +1799,9 @@ artMterpAsmInstructionStart = .L_op_nop SET_VREG a2, a4 # vAA <- a2 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_aget_char: /* 0x49 */ -/* File: mips64/op_aget_char.S */ -/* File: mips64/op_aget.S */ /* * Array get, 32 bits or less. vAA <- vBB[vCC]. * @@ -1983,12 +1831,9 @@ artMterpAsmInstructionStart = .L_op_nop SET_VREG a2, a4 # vAA <- a2 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_aget_short: /* 0x4a */ -/* File: mips64/op_aget_short.S */ -/* File: mips64/op_aget.S */ /* * Array get, 32 bits or less. vAA <- vBB[vCC]. * @@ -2018,11 +1863,9 @@ artMterpAsmInstructionStart = .L_op_nop SET_VREG a2, a4 # vAA <- a2 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_aput: /* 0x4b */ -/* File: mips64/op_aput.S */ /* * Array put, 32 bits or less. vBB[vCC] <- vAA. * @@ -2055,7 +1898,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_aput_wide: /* 0x4c */ -/* File: mips64/op_aput_wide.S */ /* * Array put, 64 bits. vBB[vCC] <- vAA. * @@ -2081,7 +1923,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_aput_object: /* 0x4d */ -/* File: mips64/op_aput_object.S */ /* * Store an object into an array. vBB[vCC] <- vAA. */ @@ -2100,8 +1941,6 @@ artMterpAsmInstructionStart = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_aput_boolean: /* 0x4e */ -/* File: mips64/op_aput_boolean.S */ -/* File: mips64/op_aput.S */ /* * Array put, 32 bits or less. vBB[vCC] <- vAA. * @@ -2131,12 +1970,9 @@ artMterpAsmInstructionStart = .L_op_nop sb a2, MIRROR_BOOLEAN_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_aput_byte: /* 0x4f */ -/* File: mips64/op_aput_byte.S */ -/* File: mips64/op_aput.S */ /* * Array put, 32 bits or less. vBB[vCC] <- vAA. * @@ -2166,12 +2002,9 @@ artMterpAsmInstructionStart = .L_op_nop sb a2, MIRROR_BYTE_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_aput_char: /* 0x50 */ -/* File: mips64/op_aput_char.S */ -/* File: mips64/op_aput.S */ /* * Array put, 32 bits or less. vBB[vCC] <- vAA. * @@ -2201,12 +2034,9 @@ artMterpAsmInstructionStart = .L_op_nop sh a2, MIRROR_CHAR_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_aput_short: /* 0x51 */ -/* File: mips64/op_aput_short.S */ -/* File: mips64/op_aput.S */ /* * Array put, 32 bits or less. vBB[vCC] <- vAA. * @@ -2236,284 +2066,149 @@ artMterpAsmInstructionStart = .L_op_nop sh a2, MIRROR_SHORT_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_iget: /* 0x52 */ -/* File: mips64/op_iget.S */ -/* File: mips64/field.S */ TODO - /* ------------------------------ */ .balign 128 .L_op_iget_wide: /* 0x53 */ -/* File: mips64/op_iget_wide.S */ -/* File: mips64/op_iget.S */ -/* File: mips64/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_iget_object: /* 0x54 */ -/* File: mips64/op_iget_object.S */ -/* File: mips64/op_iget.S */ -/* File: mips64/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_iget_boolean: /* 0x55 */ -/* File: mips64/op_iget_boolean.S */ -/* File: mips64/op_iget.S */ -/* File: mips64/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_iget_byte: /* 0x56 */ -/* File: mips64/op_iget_byte.S */ -/* File: mips64/op_iget.S */ -/* File: mips64/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_iget_char: /* 0x57 */ -/* File: mips64/op_iget_char.S */ -/* File: mips64/op_iget.S */ -/* File: mips64/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_iget_short: /* 0x58 */ -/* File: mips64/op_iget_short.S */ -/* File: mips64/op_iget.S */ -/* File: mips64/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_iput: /* 0x59 */ -/* File: mips64/op_iput.S */ -/* File: mips64/field.S */ TODO - /* ------------------------------ */ .balign 128 .L_op_iput_wide: /* 0x5a */ -/* File: mips64/op_iput_wide.S */ -/* File: mips64/op_iput.S */ -/* File: mips64/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_iput_object: /* 0x5b */ -/* File: mips64/op_iput_object.S */ -/* File: mips64/op_iput.S */ -/* File: mips64/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_iput_boolean: /* 0x5c */ -/* File: mips64/op_iput_boolean.S */ -/* File: mips64/op_iput.S */ -/* File: mips64/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_iput_byte: /* 0x5d */ -/* File: mips64/op_iput_byte.S */ -/* File: mips64/op_iput.S */ -/* File: mips64/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_iput_char: /* 0x5e */ -/* File: mips64/op_iput_char.S */ -/* File: mips64/op_iput.S */ -/* File: mips64/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_iput_short: /* 0x5f */ -/* File: mips64/op_iput_short.S */ -/* File: mips64/op_iput.S */ -/* File: mips64/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_sget: /* 0x60 */ -/* File: mips64/op_sget.S */ -/* File: mips64/field.S */ TODO - /* ------------------------------ */ .balign 128 .L_op_sget_wide: /* 0x61 */ -/* File: mips64/op_sget_wide.S */ -/* File: mips64/op_sget.S */ -/* File: mips64/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_sget_object: /* 0x62 */ -/* File: mips64/op_sget_object.S */ -/* File: mips64/op_sget.S */ -/* File: mips64/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_sget_boolean: /* 0x63 */ -/* File: mips64/op_sget_boolean.S */ -/* File: mips64/op_sget.S */ -/* File: mips64/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_sget_byte: /* 0x64 */ -/* File: mips64/op_sget_byte.S */ -/* File: mips64/op_sget.S */ -/* File: mips64/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_sget_char: /* 0x65 */ -/* File: mips64/op_sget_char.S */ -/* File: mips64/op_sget.S */ -/* File: mips64/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_sget_short: /* 0x66 */ -/* File: mips64/op_sget_short.S */ -/* File: mips64/op_sget.S */ -/* File: mips64/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_sput: /* 0x67 */ -/* File: mips64/op_sput.S */ -/* File: mips64/field.S */ TODO - /* ------------------------------ */ .balign 128 .L_op_sput_wide: /* 0x68 */ -/* File: mips64/op_sput_wide.S */ -/* File: mips64/op_sput.S */ -/* File: mips64/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_sput_object: /* 0x69 */ -/* File: mips64/op_sput_object.S */ -/* File: mips64/op_sput.S */ -/* File: mips64/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_sput_boolean: /* 0x6a */ -/* File: mips64/op_sput_boolean.S */ -/* File: mips64/op_sput.S */ -/* File: mips64/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_sput_byte: /* 0x6b */ -/* File: mips64/op_sput_byte.S */ -/* File: mips64/op_sput.S */ -/* File: mips64/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_sput_char: /* 0x6c */ -/* File: mips64/op_sput_char.S */ -/* File: mips64/op_sput.S */ -/* File: mips64/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_sput_short: /* 0x6d */ -/* File: mips64/op_sput_short.S */ -/* File: mips64/op_sput.S */ -/* File: mips64/field.S */ TODO - - /* ------------------------------ */ .balign 128 .L_op_invoke_virtual: /* 0x6e */ -/* File: mips64/op_invoke_virtual.S */ -/* File: mips64/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -2533,7 +2228,6 @@ TODO bnezc v0, MterpFallback GET_INST_OPCODE v0 GOTO_OPCODE v0 - /* * Handle a virtual method call. * @@ -2545,8 +2239,6 @@ TODO /* ------------------------------ */ .balign 128 .L_op_invoke_super: /* 0x6f */ -/* File: mips64/op_invoke_super.S */ -/* File: mips64/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -2566,7 +2258,6 @@ TODO bnezc v0, MterpFallback GET_INST_OPCODE v0 GOTO_OPCODE v0 - /* * Handle a "super" method call. * @@ -2578,8 +2269,6 @@ TODO /* ------------------------------ */ .balign 128 .L_op_invoke_direct: /* 0x70 */ -/* File: mips64/op_invoke_direct.S */ -/* File: mips64/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -2600,12 +2289,9 @@ TODO GET_INST_OPCODE v0 GOTO_OPCODE v0 - /* ------------------------------ */ .balign 128 .L_op_invoke_static: /* 0x71 */ -/* File: mips64/op_invoke_static.S */ -/* File: mips64/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -2626,12 +2312,9 @@ TODO GET_INST_OPCODE v0 GOTO_OPCODE v0 - /* ------------------------------ */ .balign 128 .L_op_invoke_interface: /* 0x72 */ -/* File: mips64/op_invoke_interface.S */ -/* File: mips64/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -2651,7 +2334,6 @@ TODO bnezc v0, MterpFallback GET_INST_OPCODE v0 GOTO_OPCODE v0 - /* * Handle an interface method call. * @@ -2663,7 +2345,6 @@ TODO /* ------------------------------ */ .balign 128 .L_op_return_void_no_barrier: /* 0x73 */ -/* File: mips64/op_return_void_no_barrier.S */ .extern MterpSuspendCheck lw ra, THREAD_FLAGS_OFFSET(rSELF) move a0, rSELF @@ -2677,8 +2358,6 @@ TODO /* ------------------------------ */ .balign 128 .L_op_invoke_virtual_range: /* 0x74 */ -/* File: mips64/op_invoke_virtual_range.S */ -/* File: mips64/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -2699,12 +2378,9 @@ TODO GET_INST_OPCODE v0 GOTO_OPCODE v0 - /* ------------------------------ */ .balign 128 .L_op_invoke_super_range: /* 0x75 */ -/* File: mips64/op_invoke_super_range.S */ -/* File: mips64/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -2725,12 +2401,9 @@ TODO GET_INST_OPCODE v0 GOTO_OPCODE v0 - /* ------------------------------ */ .balign 128 .L_op_invoke_direct_range: /* 0x76 */ -/* File: mips64/op_invoke_direct_range.S */ -/* File: mips64/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -2751,12 +2424,9 @@ TODO GET_INST_OPCODE v0 GOTO_OPCODE v0 - /* ------------------------------ */ .balign 128 .L_op_invoke_static_range: /* 0x77 */ -/* File: mips64/op_invoke_static_range.S */ -/* File: mips64/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -2777,12 +2447,9 @@ TODO GET_INST_OPCODE v0 GOTO_OPCODE v0 - /* ------------------------------ */ .balign 128 .L_op_invoke_interface_range: /* 0x78 */ -/* File: mips64/op_invoke_interface_range.S */ -/* File: mips64/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -2803,34 +2470,25 @@ TODO GET_INST_OPCODE v0 GOTO_OPCODE v0 - /* ------------------------------ */ .balign 128 .L_op_unused_79: /* 0x79 */ -/* File: mips64/op_unused_79.S */ -/* File: mips64/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_7a: /* 0x7a */ -/* File: mips64/op_unused_7a.S */ -/* File: mips64/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_neg_int: /* 0x7b */ -/* File: mips64/op_neg_int.S */ -/* File: mips64/unop.S */ /* * Generic 32-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "a0 = op a0". @@ -2849,12 +2507,9 @@ TODO SET_VREG a0, a2 # vA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_not_int: /* 0x7c */ -/* File: mips64/op_not_int.S */ -/* File: mips64/unop.S */ /* * Generic 32-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "a0 = op a0". @@ -2873,12 +2528,9 @@ TODO SET_VREG a0, a2 # vA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_neg_long: /* 0x7d */ -/* File: mips64/op_neg_long.S */ -/* File: mips64/unopWide.S */ /* * Generic 64-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "a0 = op a0". @@ -2896,12 +2548,9 @@ TODO SET_VREG_WIDE a0, a2 # vA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_not_long: /* 0x7e */ -/* File: mips64/op_not_long.S */ -/* File: mips64/unopWide.S */ /* * Generic 64-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "a0 = op a0". @@ -2919,12 +2568,9 @@ TODO SET_VREG_WIDE a0, a2 # vA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_neg_float: /* 0x7f */ -/* File: mips64/op_neg_float.S */ -/* File: mips64/fcvtHeader.S */ /* * Loads a specified register from vB. Used primarily for conversions * from or to a floating-point type. @@ -2940,9 +2586,7 @@ TODO srl a2, rINST, 12 # a2 <- B GET_VREG_FLOAT f0, a2 FETCH_ADVANCE_INST 1 # advance rPC, load rINST - neg.s f0, f0 -/* File: mips64/fcvtFooter.S */ /* * Stores a specified register containing the result of conversion * from or to a floating-point type and jumps to the next instruction. @@ -2962,12 +2606,9 @@ TODO SET_VREG_FLOAT f0, a1 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_neg_double: /* 0x80 */ -/* File: mips64/op_neg_double.S */ -/* File: mips64/fcvtHeader.S */ /* * Loads a specified register from vB. Used primarily for conversions * from or to a floating-point type. @@ -2983,9 +2624,7 @@ TODO srl a2, rINST, 12 # a2 <- B GET_VREG_DOUBLE f0, a2 FETCH_ADVANCE_INST 1 # advance rPC, load rINST - neg.d f0, f0 -/* File: mips64/fcvtFooter.S */ /* * Stores a specified register containing the result of conversion * from or to a floating-point type and jumps to the next instruction. @@ -3005,11 +2644,9 @@ TODO SET_VREG_DOUBLE f0, a1 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_int_to_long: /* 0x81 */ -/* File: mips64/op_int_to_long.S */ /* int-to-long vA, vB */ ext a3, rINST, 12, 4 # a3 <- B GET_VREG a0, a3 # a0 <- vB (sign-extended to 64 bits) @@ -3022,13 +2659,11 @@ TODO /* ------------------------------ */ .balign 128 .L_op_int_to_float: /* 0x82 */ -/* File: mips64/op_int_to_float.S */ /* * Conversion from or to floating-point happens in a floating-point register. * Therefore we load the input and store the output into or from a * floating-point register irrespective of the type. */ -/* File: mips64/fcvtHeader.S */ /* * Loads a specified register from vB. Used primarily for conversions * from or to a floating-point type. @@ -3044,9 +2679,7 @@ TODO srl a2, rINST, 12 # a2 <- B GET_VREG_FLOAT f0, a2 FETCH_ADVANCE_INST 1 # advance rPC, load rINST - cvt.s.w f0, f0 -/* File: mips64/fcvtFooter.S */ /* * Stores a specified register containing the result of conversion * from or to a floating-point type and jumps to the next instruction. @@ -3066,17 +2699,14 @@ TODO SET_VREG_FLOAT f0, a1 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_int_to_double: /* 0x83 */ -/* File: mips64/op_int_to_double.S */ /* * Conversion from or to floating-point happens in a floating-point register. * Therefore we load the input and store the output into or from a * floating-point register irrespective of the type. */ -/* File: mips64/fcvtHeader.S */ /* * Loads a specified register from vB. Used primarily for conversions * from or to a floating-point type. @@ -3092,9 +2722,7 @@ TODO srl a2, rINST, 12 # a2 <- B GET_VREG_FLOAT f0, a2 FETCH_ADVANCE_INST 1 # advance rPC, load rINST - cvt.d.w f0, f0 -/* File: mips64/fcvtFooter.S */ /* * Stores a specified register containing the result of conversion * from or to a floating-point type and jumps to the next instruction. @@ -3114,13 +2742,10 @@ TODO SET_VREG_DOUBLE f0, a1 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_long_to_int: /* 0x84 */ -/* File: mips64/op_long_to_int.S */ /* we ignore the high word, making this equivalent to a 32-bit reg move */ -/* File: mips64/op_move.S */ /* for move, move-object, long-to-int */ /* op vA, vB */ ext a2, rINST, 8, 4 # a2 <- A @@ -3135,17 +2760,14 @@ TODO .endif GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_long_to_float: /* 0x85 */ -/* File: mips64/op_long_to_float.S */ /* * Conversion from or to floating-point happens in a floating-point register. * Therefore we load the input and store the output into or from a * floating-point register irrespective of the type. */ -/* File: mips64/fcvtHeader.S */ /* * Loads a specified register from vB. Used primarily for conversions * from or to a floating-point type. @@ -3161,9 +2783,7 @@ TODO srl a2, rINST, 12 # a2 <- B GET_VREG_DOUBLE f0, a2 FETCH_ADVANCE_INST 1 # advance rPC, load rINST - cvt.s.l f0, f0 -/* File: mips64/fcvtFooter.S */ /* * Stores a specified register containing the result of conversion * from or to a floating-point type and jumps to the next instruction. @@ -3183,17 +2803,14 @@ TODO SET_VREG_FLOAT f0, a1 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_long_to_double: /* 0x86 */ -/* File: mips64/op_long_to_double.S */ /* * Conversion from or to floating-point happens in a floating-point register. * Therefore we load the input and store the output into or from a * floating-point register irrespective of the type. */ -/* File: mips64/fcvtHeader.S */ /* * Loads a specified register from vB. Used primarily for conversions * from or to a floating-point type. @@ -3209,9 +2826,7 @@ TODO srl a2, rINST, 12 # a2 <- B GET_VREG_DOUBLE f0, a2 FETCH_ADVANCE_INST 1 # advance rPC, load rINST - cvt.d.l f0, f0 -/* File: mips64/fcvtFooter.S */ /* * Stores a specified register containing the result of conversion * from or to a floating-point type and jumps to the next instruction. @@ -3231,12 +2846,9 @@ TODO SET_VREG_DOUBLE f0, a1 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_float_to_int: /* 0x87 */ -/* File: mips64/op_float_to_int.S */ -/* File: mips64/fcvtHeader.S */ /* * Loads a specified register from vB. Used primarily for conversions * from or to a floating-point type. @@ -3252,9 +2864,7 @@ TODO srl a2, rINST, 12 # a2 <- B GET_VREG_FLOAT f0, a2 FETCH_ADVANCE_INST 1 # advance rPC, load rINST - trunc.w.s f0, f0 -/* File: mips64/fcvtFooter.S */ /* * Stores a specified register containing the result of conversion * from or to a floating-point type and jumps to the next instruction. @@ -3274,12 +2884,9 @@ TODO SET_VREG_FLOAT f0, a1 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_float_to_long: /* 0x88 */ -/* File: mips64/op_float_to_long.S */ -/* File: mips64/fcvtHeader.S */ /* * Loads a specified register from vB. Used primarily for conversions * from or to a floating-point type. @@ -3295,9 +2902,7 @@ TODO srl a2, rINST, 12 # a2 <- B GET_VREG_FLOAT f0, a2 FETCH_ADVANCE_INST 1 # advance rPC, load rINST - trunc.l.s f0, f0 -/* File: mips64/fcvtFooter.S */ /* * Stores a specified register containing the result of conversion * from or to a floating-point type and jumps to the next instruction. @@ -3317,17 +2922,14 @@ TODO SET_VREG_DOUBLE f0, a1 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_float_to_double: /* 0x89 */ -/* File: mips64/op_float_to_double.S */ /* * Conversion from or to floating-point happens in a floating-point register. * Therefore we load the input and store the output into or from a * floating-point register irrespective of the type. */ -/* File: mips64/fcvtHeader.S */ /* * Loads a specified register from vB. Used primarily for conversions * from or to a floating-point type. @@ -3343,9 +2945,7 @@ TODO srl a2, rINST, 12 # a2 <- B GET_VREG_FLOAT f0, a2 FETCH_ADVANCE_INST 1 # advance rPC, load rINST - cvt.d.s f0, f0 -/* File: mips64/fcvtFooter.S */ /* * Stores a specified register containing the result of conversion * from or to a floating-point type and jumps to the next instruction. @@ -3365,12 +2965,9 @@ TODO SET_VREG_DOUBLE f0, a1 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_double_to_int: /* 0x8a */ -/* File: mips64/op_double_to_int.S */ -/* File: mips64/fcvtHeader.S */ /* * Loads a specified register from vB. Used primarily for conversions * from or to a floating-point type. @@ -3386,9 +2983,7 @@ TODO srl a2, rINST, 12 # a2 <- B GET_VREG_DOUBLE f0, a2 FETCH_ADVANCE_INST 1 # advance rPC, load rINST - trunc.w.d f0, f0 -/* File: mips64/fcvtFooter.S */ /* * Stores a specified register containing the result of conversion * from or to a floating-point type and jumps to the next instruction. @@ -3408,12 +3003,9 @@ TODO SET_VREG_FLOAT f0, a1 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_double_to_long: /* 0x8b */ -/* File: mips64/op_double_to_long.S */ -/* File: mips64/fcvtHeader.S */ /* * Loads a specified register from vB. Used primarily for conversions * from or to a floating-point type. @@ -3429,9 +3021,7 @@ TODO srl a2, rINST, 12 # a2 <- B GET_VREG_DOUBLE f0, a2 FETCH_ADVANCE_INST 1 # advance rPC, load rINST - trunc.l.d f0, f0 -/* File: mips64/fcvtFooter.S */ /* * Stores a specified register containing the result of conversion * from or to a floating-point type and jumps to the next instruction. @@ -3451,17 +3041,14 @@ TODO SET_VREG_DOUBLE f0, a1 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_double_to_float: /* 0x8c */ -/* File: mips64/op_double_to_float.S */ /* * Conversion from or to floating-point happens in a floating-point register. * Therefore we load the input and store the output into or from a * floating-point register irrespective of the type. */ -/* File: mips64/fcvtHeader.S */ /* * Loads a specified register from vB. Used primarily for conversions * from or to a floating-point type. @@ -3477,9 +3064,7 @@ TODO srl a2, rINST, 12 # a2 <- B GET_VREG_DOUBLE f0, a2 FETCH_ADVANCE_INST 1 # advance rPC, load rINST - cvt.s.d f0, f0 -/* File: mips64/fcvtFooter.S */ /* * Stores a specified register containing the result of conversion * from or to a floating-point type and jumps to the next instruction. @@ -3499,12 +3084,9 @@ TODO SET_VREG_FLOAT f0, a1 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_int_to_byte: /* 0x8d */ -/* File: mips64/op_int_to_byte.S */ -/* File: mips64/unop.S */ /* * Generic 32-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "a0 = op a0". @@ -3523,12 +3105,9 @@ TODO SET_VREG a0, a2 # vA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_int_to_char: /* 0x8e */ -/* File: mips64/op_int_to_char.S */ -/* File: mips64/unop.S */ /* * Generic 32-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "a0 = op a0". @@ -3547,12 +3126,9 @@ TODO SET_VREG a0, a2 # vA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_int_to_short: /* 0x8f */ -/* File: mips64/op_int_to_short.S */ -/* File: mips64/unop.S */ /* * Generic 32-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "a0 = op a0". @@ -3571,12 +3147,9 @@ TODO SET_VREG a0, a2 # vA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_add_int: /* 0x90 */ -/* File: mips64/op_add_int.S */ -/* File: mips64/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0 op a1". @@ -3607,12 +3180,9 @@ TODO SET_VREG a0, a4 # vAA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_sub_int: /* 0x91 */ -/* File: mips64/op_sub_int.S */ -/* File: mips64/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0 op a1". @@ -3643,12 +3213,9 @@ TODO SET_VREG a0, a4 # vAA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_mul_int: /* 0x92 */ -/* File: mips64/op_mul_int.S */ -/* File: mips64/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0 op a1". @@ -3679,12 +3246,9 @@ TODO SET_VREG a0, a4 # vAA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_div_int: /* 0x93 */ -/* File: mips64/op_div_int.S */ -/* File: mips64/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0 op a1". @@ -3715,12 +3279,9 @@ TODO SET_VREG a0, a4 # vAA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_rem_int: /* 0x94 */ -/* File: mips64/op_rem_int.S */ -/* File: mips64/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0 op a1". @@ -3751,12 +3312,9 @@ TODO SET_VREG a0, a4 # vAA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_and_int: /* 0x95 */ -/* File: mips64/op_and_int.S */ -/* File: mips64/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0 op a1". @@ -3787,12 +3345,9 @@ TODO SET_VREG a0, a4 # vAA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_or_int: /* 0x96 */ -/* File: mips64/op_or_int.S */ -/* File: mips64/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0 op a1". @@ -3823,12 +3378,9 @@ TODO SET_VREG a0, a4 # vAA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_xor_int: /* 0x97 */ -/* File: mips64/op_xor_int.S */ -/* File: mips64/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0 op a1". @@ -3859,12 +3411,9 @@ TODO SET_VREG a0, a4 # vAA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_shl_int: /* 0x98 */ -/* File: mips64/op_shl_int.S */ -/* File: mips64/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0 op a1". @@ -3895,12 +3444,9 @@ TODO SET_VREG a0, a4 # vAA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_shr_int: /* 0x99 */ -/* File: mips64/op_shr_int.S */ -/* File: mips64/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0 op a1". @@ -3931,12 +3477,9 @@ TODO SET_VREG a0, a4 # vAA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_ushr_int: /* 0x9a */ -/* File: mips64/op_ushr_int.S */ -/* File: mips64/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0 op a1". @@ -3967,12 +3510,9 @@ TODO SET_VREG a0, a4 # vAA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_add_long: /* 0x9b */ -/* File: mips64/op_add_long.S */ -/* File: mips64/binopWide.S */ /* * Generic 64-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0 op a1". @@ -4003,12 +3543,9 @@ TODO SET_VREG_WIDE a0, a4 # vAA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_sub_long: /* 0x9c */ -/* File: mips64/op_sub_long.S */ -/* File: mips64/binopWide.S */ /* * Generic 64-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0 op a1". @@ -4039,12 +3576,9 @@ TODO SET_VREG_WIDE a0, a4 # vAA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_mul_long: /* 0x9d */ -/* File: mips64/op_mul_long.S */ -/* File: mips64/binopWide.S */ /* * Generic 64-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0 op a1". @@ -4075,12 +3609,9 @@ TODO SET_VREG_WIDE a0, a4 # vAA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_div_long: /* 0x9e */ -/* File: mips64/op_div_long.S */ -/* File: mips64/binopWide.S */ /* * Generic 64-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0 op a1". @@ -4111,12 +3642,9 @@ TODO SET_VREG_WIDE a0, a4 # vAA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_rem_long: /* 0x9f */ -/* File: mips64/op_rem_long.S */ -/* File: mips64/binopWide.S */ /* * Generic 64-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0 op a1". @@ -4147,12 +3675,9 @@ TODO SET_VREG_WIDE a0, a4 # vAA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_and_long: /* 0xa0 */ -/* File: mips64/op_and_long.S */ -/* File: mips64/binopWide.S */ /* * Generic 64-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0 op a1". @@ -4183,12 +3708,9 @@ TODO SET_VREG_WIDE a0, a4 # vAA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_or_long: /* 0xa1 */ -/* File: mips64/op_or_long.S */ -/* File: mips64/binopWide.S */ /* * Generic 64-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0 op a1". @@ -4219,12 +3741,9 @@ TODO SET_VREG_WIDE a0, a4 # vAA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_xor_long: /* 0xa2 */ -/* File: mips64/op_xor_long.S */ -/* File: mips64/binopWide.S */ /* * Generic 64-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0 op a1". @@ -4255,12 +3774,9 @@ TODO SET_VREG_WIDE a0, a4 # vAA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_shl_long: /* 0xa3 */ -/* File: mips64/op_shl_long.S */ -/* File: mips64/binopWide.S */ /* * Generic 64-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0 op a1". @@ -4291,12 +3807,9 @@ TODO SET_VREG_WIDE a0, a4 # vAA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_shr_long: /* 0xa4 */ -/* File: mips64/op_shr_long.S */ -/* File: mips64/binopWide.S */ /* * Generic 64-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0 op a1". @@ -4327,12 +3840,9 @@ TODO SET_VREG_WIDE a0, a4 # vAA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_ushr_long: /* 0xa5 */ -/* File: mips64/op_ushr_long.S */ -/* File: mips64/binopWide.S */ /* * Generic 64-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = a0 op a1". @@ -4363,12 +3873,9 @@ TODO SET_VREG_WIDE a0, a4 # vAA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_add_float: /* 0xa6 */ -/* File: mips64/op_add_float.S */ -/* File: mips64/fbinop.S */ /*: * Generic 32-bit floating-point operation. * @@ -4387,12 +3894,9 @@ TODO SET_VREG_FLOAT f0, a4 # vAA <- f0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_sub_float: /* 0xa7 */ -/* File: mips64/op_sub_float.S */ -/* File: mips64/fbinop.S */ /*: * Generic 32-bit floating-point operation. * @@ -4411,12 +3915,9 @@ TODO SET_VREG_FLOAT f0, a4 # vAA <- f0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_mul_float: /* 0xa8 */ -/* File: mips64/op_mul_float.S */ -/* File: mips64/fbinop.S */ /*: * Generic 32-bit floating-point operation. * @@ -4435,12 +3936,9 @@ TODO SET_VREG_FLOAT f0, a4 # vAA <- f0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_div_float: /* 0xa9 */ -/* File: mips64/op_div_float.S */ -/* File: mips64/fbinop.S */ /*: * Generic 32-bit floating-point operation. * @@ -4459,11 +3957,9 @@ TODO SET_VREG_FLOAT f0, a4 # vAA <- f0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_rem_float: /* 0xaa */ -/* File: mips64/op_rem_float.S */ /* rem-float vAA, vBB, vCC */ .extern fmodf lbu a2, 2(rPC) # a2 <- BB @@ -4480,8 +3976,6 @@ TODO /* ------------------------------ */ .balign 128 .L_op_add_double: /* 0xab */ -/* File: mips64/op_add_double.S */ -/* File: mips64/fbinopWide.S */ /*: * Generic 64-bit floating-point operation. * @@ -4500,12 +3994,9 @@ TODO SET_VREG_DOUBLE f0, a4 # vAA <- f0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_sub_double: /* 0xac */ -/* File: mips64/op_sub_double.S */ -/* File: mips64/fbinopWide.S */ /*: * Generic 64-bit floating-point operation. * @@ -4524,12 +4015,9 @@ TODO SET_VREG_DOUBLE f0, a4 # vAA <- f0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_mul_double: /* 0xad */ -/* File: mips64/op_mul_double.S */ -/* File: mips64/fbinopWide.S */ /*: * Generic 64-bit floating-point operation. * @@ -4548,12 +4036,9 @@ TODO SET_VREG_DOUBLE f0, a4 # vAA <- f0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_div_double: /* 0xae */ -/* File: mips64/op_div_double.S */ -/* File: mips64/fbinopWide.S */ /*: * Generic 64-bit floating-point operation. * @@ -4572,11 +4057,9 @@ TODO SET_VREG_DOUBLE f0, a4 # vAA <- f0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_rem_double: /* 0xaf */ -/* File: mips64/op_rem_double.S */ /* rem-double vAA, vBB, vCC */ .extern fmod lbu a2, 2(rPC) # a2 <- BB @@ -4593,8 +4076,6 @@ TODO /* ------------------------------ */ .balign 128 .L_op_add_int_2addr: /* 0xb0 */ -/* File: mips64/op_add_int_2addr.S */ -/* File: mips64/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -4625,12 +4106,9 @@ TODO SET_VREG a0, a2 # vA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_sub_int_2addr: /* 0xb1 */ -/* File: mips64/op_sub_int_2addr.S */ -/* File: mips64/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -4661,12 +4139,9 @@ TODO SET_VREG a0, a2 # vA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_mul_int_2addr: /* 0xb2 */ -/* File: mips64/op_mul_int_2addr.S */ -/* File: mips64/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -4697,12 +4172,9 @@ TODO SET_VREG a0, a2 # vA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_div_int_2addr: /* 0xb3 */ -/* File: mips64/op_div_int_2addr.S */ -/* File: mips64/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -4733,12 +4205,9 @@ TODO SET_VREG a0, a2 # vA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_rem_int_2addr: /* 0xb4 */ -/* File: mips64/op_rem_int_2addr.S */ -/* File: mips64/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -4769,12 +4238,9 @@ TODO SET_VREG a0, a2 # vA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_and_int_2addr: /* 0xb5 */ -/* File: mips64/op_and_int_2addr.S */ -/* File: mips64/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -4805,12 +4271,9 @@ TODO SET_VREG a0, a2 # vA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_or_int_2addr: /* 0xb6 */ -/* File: mips64/op_or_int_2addr.S */ -/* File: mips64/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -4841,12 +4304,9 @@ TODO SET_VREG a0, a2 # vA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_xor_int_2addr: /* 0xb7 */ -/* File: mips64/op_xor_int_2addr.S */ -/* File: mips64/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -4877,12 +4337,9 @@ TODO SET_VREG a0, a2 # vA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_shl_int_2addr: /* 0xb8 */ -/* File: mips64/op_shl_int_2addr.S */ -/* File: mips64/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -4913,12 +4370,9 @@ TODO SET_VREG a0, a2 # vA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_shr_int_2addr: /* 0xb9 */ -/* File: mips64/op_shr_int_2addr.S */ -/* File: mips64/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -4949,12 +4403,9 @@ TODO SET_VREG a0, a2 # vA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_ushr_int_2addr: /* 0xba */ -/* File: mips64/op_ushr_int_2addr.S */ -/* File: mips64/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -4985,12 +4436,9 @@ TODO SET_VREG a0, a2 # vA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_add_long_2addr: /* 0xbb */ -/* File: mips64/op_add_long_2addr.S */ -/* File: mips64/binopWide2addr.S */ /* * Generic 64-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -5021,12 +4469,9 @@ TODO SET_VREG_WIDE a0, a2 # vA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_sub_long_2addr: /* 0xbc */ -/* File: mips64/op_sub_long_2addr.S */ -/* File: mips64/binopWide2addr.S */ /* * Generic 64-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -5057,12 +4502,9 @@ TODO SET_VREG_WIDE a0, a2 # vA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_mul_long_2addr: /* 0xbd */ -/* File: mips64/op_mul_long_2addr.S */ -/* File: mips64/binopWide2addr.S */ /* * Generic 64-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -5093,12 +4535,9 @@ TODO SET_VREG_WIDE a0, a2 # vA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_div_long_2addr: /* 0xbe */ -/* File: mips64/op_div_long_2addr.S */ -/* File: mips64/binopWide2addr.S */ /* * Generic 64-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -5129,12 +4568,9 @@ TODO SET_VREG_WIDE a0, a2 # vA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_rem_long_2addr: /* 0xbf */ -/* File: mips64/op_rem_long_2addr.S */ -/* File: mips64/binopWide2addr.S */ /* * Generic 64-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -5165,12 +4601,9 @@ TODO SET_VREG_WIDE a0, a2 # vA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_and_long_2addr: /* 0xc0 */ -/* File: mips64/op_and_long_2addr.S */ -/* File: mips64/binopWide2addr.S */ /* * Generic 64-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -5201,12 +4634,9 @@ TODO SET_VREG_WIDE a0, a2 # vA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_or_long_2addr: /* 0xc1 */ -/* File: mips64/op_or_long_2addr.S */ -/* File: mips64/binopWide2addr.S */ /* * Generic 64-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -5237,12 +4667,9 @@ TODO SET_VREG_WIDE a0, a2 # vA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_xor_long_2addr: /* 0xc2 */ -/* File: mips64/op_xor_long_2addr.S */ -/* File: mips64/binopWide2addr.S */ /* * Generic 64-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -5273,12 +4700,9 @@ TODO SET_VREG_WIDE a0, a2 # vA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_shl_long_2addr: /* 0xc3 */ -/* File: mips64/op_shl_long_2addr.S */ -/* File: mips64/binopWide2addr.S */ /* * Generic 64-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -5309,12 +4733,9 @@ TODO SET_VREG_WIDE a0, a2 # vA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_shr_long_2addr: /* 0xc4 */ -/* File: mips64/op_shr_long_2addr.S */ -/* File: mips64/binopWide2addr.S */ /* * Generic 64-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -5345,12 +4766,9 @@ TODO SET_VREG_WIDE a0, a2 # vA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_ushr_long_2addr: /* 0xc5 */ -/* File: mips64/op_ushr_long_2addr.S */ -/* File: mips64/binopWide2addr.S */ /* * Generic 64-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -5381,12 +4799,9 @@ TODO SET_VREG_WIDE a0, a2 # vA <- a0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_add_float_2addr: /* 0xc6 */ -/* File: mips64/op_add_float_2addr.S */ -/* File: mips64/fbinop2addr.S */ /*: * Generic 32-bit "/2addr" floating-point operation. * @@ -5404,12 +4819,9 @@ TODO SET_VREG_FLOAT f0, a2 # vA <- f0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_sub_float_2addr: /* 0xc7 */ -/* File: mips64/op_sub_float_2addr.S */ -/* File: mips64/fbinop2addr.S */ /*: * Generic 32-bit "/2addr" floating-point operation. * @@ -5427,12 +4839,9 @@ TODO SET_VREG_FLOAT f0, a2 # vA <- f0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_mul_float_2addr: /* 0xc8 */ -/* File: mips64/op_mul_float_2addr.S */ -/* File: mips64/fbinop2addr.S */ /*: * Generic 32-bit "/2addr" floating-point operation. * @@ -5450,12 +4859,9 @@ TODO SET_VREG_FLOAT f0, a2 # vA <- f0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_div_float_2addr: /* 0xc9 */ -/* File: mips64/op_div_float_2addr.S */ -/* File: mips64/fbinop2addr.S */ /*: * Generic 32-bit "/2addr" floating-point operation. * @@ -5473,11 +4879,9 @@ TODO SET_VREG_FLOAT f0, a2 # vA <- f0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_rem_float_2addr: /* 0xca */ -/* File: mips64/op_rem_float_2addr.S */ /* rem-float/2addr vA, vB */ .extern fmodf ext a2, rINST, 8, 4 # a2 <- A @@ -5494,8 +4898,6 @@ TODO /* ------------------------------ */ .balign 128 .L_op_add_double_2addr: /* 0xcb */ -/* File: mips64/op_add_double_2addr.S */ -/* File: mips64/fbinopWide2addr.S */ /*: * Generic 64-bit "/2addr" floating-point operation. * @@ -5513,12 +4915,9 @@ TODO SET_VREG_DOUBLE f0, a2 # vA <- f0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_sub_double_2addr: /* 0xcc */ -/* File: mips64/op_sub_double_2addr.S */ -/* File: mips64/fbinopWide2addr.S */ /*: * Generic 64-bit "/2addr" floating-point operation. * @@ -5536,12 +4935,9 @@ TODO SET_VREG_DOUBLE f0, a2 # vA <- f0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_mul_double_2addr: /* 0xcd */ -/* File: mips64/op_mul_double_2addr.S */ -/* File: mips64/fbinopWide2addr.S */ /*: * Generic 64-bit "/2addr" floating-point operation. * @@ -5559,12 +4955,9 @@ TODO SET_VREG_DOUBLE f0, a2 # vA <- f0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_div_double_2addr: /* 0xce */ -/* File: mips64/op_div_double_2addr.S */ -/* File: mips64/fbinopWide2addr.S */ /*: * Generic 64-bit "/2addr" floating-point operation. * @@ -5582,11 +4975,9 @@ TODO SET_VREG_DOUBLE f0, a2 # vA <- f0 GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_rem_double_2addr: /* 0xcf */ -/* File: mips64/op_rem_double_2addr.S */ /* rem-double/2addr vA, vB */ .extern fmod ext a2, rINST, 8, 4 # a2 <- A @@ -5603,8 +4994,6 @@ TODO /* ------------------------------ */ .balign 128 .L_op_add_int_lit16: /* 0xd0 */ -/* File: mips64/op_add_int_lit16.S */ -/* File: mips64/binopLit16.S */ /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -5632,13 +5021,9 @@ TODO SET_VREG a0, a2 # vA <- a0 GOTO_OPCODE v0 # jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_rsub_int: /* 0xd1 */ -/* File: mips64/op_rsub_int.S */ -/* File: mips64/binopLit16.S */ /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -5666,13 +5051,9 @@ TODO SET_VREG a0, a2 # vA <- a0 GOTO_OPCODE v0 # jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_mul_int_lit16: /* 0xd2 */ -/* File: mips64/op_mul_int_lit16.S */ -/* File: mips64/binopLit16.S */ /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -5700,13 +5081,9 @@ TODO SET_VREG a0, a2 # vA <- a0 GOTO_OPCODE v0 # jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_div_int_lit16: /* 0xd3 */ -/* File: mips64/op_div_int_lit16.S */ -/* File: mips64/binopLit16.S */ /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -5734,13 +5111,9 @@ TODO SET_VREG a0, a2 # vA <- a0 GOTO_OPCODE v0 # jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_rem_int_lit16: /* 0xd4 */ -/* File: mips64/op_rem_int_lit16.S */ -/* File: mips64/binopLit16.S */ /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -5768,13 +5141,9 @@ TODO SET_VREG a0, a2 # vA <- a0 GOTO_OPCODE v0 # jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_and_int_lit16: /* 0xd5 */ -/* File: mips64/op_and_int_lit16.S */ -/* File: mips64/binopLit16.S */ /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -5802,13 +5171,9 @@ TODO SET_VREG a0, a2 # vA <- a0 GOTO_OPCODE v0 # jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_or_int_lit16: /* 0xd6 */ -/* File: mips64/op_or_int_lit16.S */ -/* File: mips64/binopLit16.S */ /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -5836,13 +5201,9 @@ TODO SET_VREG a0, a2 # vA <- a0 GOTO_OPCODE v0 # jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_xor_int_lit16: /* 0xd7 */ -/* File: mips64/op_xor_int_lit16.S */ -/* File: mips64/binopLit16.S */ /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -5870,13 +5231,9 @@ TODO SET_VREG a0, a2 # vA <- a0 GOTO_OPCODE v0 # jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_add_int_lit8: /* 0xd8 */ -/* File: mips64/op_add_int_lit8.S */ -/* File: mips64/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -5905,13 +5262,9 @@ TODO SET_VREG a0, a2 # vAA <- a0 GOTO_OPCODE v0 # jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_rsub_int_lit8: /* 0xd9 */ -/* File: mips64/op_rsub_int_lit8.S */ -/* File: mips64/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -5940,13 +5293,9 @@ TODO SET_VREG a0, a2 # vAA <- a0 GOTO_OPCODE v0 # jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_mul_int_lit8: /* 0xda */ -/* File: mips64/op_mul_int_lit8.S */ -/* File: mips64/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -5975,13 +5324,9 @@ TODO SET_VREG a0, a2 # vAA <- a0 GOTO_OPCODE v0 # jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_div_int_lit8: /* 0xdb */ -/* File: mips64/op_div_int_lit8.S */ -/* File: mips64/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -6010,13 +5355,9 @@ TODO SET_VREG a0, a2 # vAA <- a0 GOTO_OPCODE v0 # jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_rem_int_lit8: /* 0xdc */ -/* File: mips64/op_rem_int_lit8.S */ -/* File: mips64/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -6045,13 +5386,9 @@ TODO SET_VREG a0, a2 # vAA <- a0 GOTO_OPCODE v0 # jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_and_int_lit8: /* 0xdd */ -/* File: mips64/op_and_int_lit8.S */ -/* File: mips64/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -6080,13 +5417,9 @@ TODO SET_VREG a0, a2 # vAA <- a0 GOTO_OPCODE v0 # jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_or_int_lit8: /* 0xde */ -/* File: mips64/op_or_int_lit8.S */ -/* File: mips64/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -6115,13 +5448,9 @@ TODO SET_VREG a0, a2 # vAA <- a0 GOTO_OPCODE v0 # jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_xor_int_lit8: /* 0xdf */ -/* File: mips64/op_xor_int_lit8.S */ -/* File: mips64/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -6150,13 +5479,9 @@ TODO SET_VREG a0, a2 # vAA <- a0 GOTO_OPCODE v0 # jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_shl_int_lit8: /* 0xe0 */ -/* File: mips64/op_shl_int_lit8.S */ -/* File: mips64/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -6185,13 +5510,9 @@ TODO SET_VREG a0, a2 # vAA <- a0 GOTO_OPCODE v0 # jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_shr_int_lit8: /* 0xe1 */ -/* File: mips64/op_shr_int_lit8.S */ -/* File: mips64/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -6220,13 +5541,9 @@ TODO SET_VREG a0, a2 # vAA <- a0 GOTO_OPCODE v0 # jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_ushr_int_lit8: /* 0xe2 */ -/* File: mips64/op_ushr_int_lit8.S */ -/* File: mips64/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = a0 op a1". @@ -6255,12 +5572,9 @@ TODO SET_VREG a0, a2 # vAA <- a0 GOTO_OPCODE v0 # jump to next instruction - - /* ------------------------------ */ .balign 128 .L_op_iget_quick: /* 0xe3 */ -/* File: mips64/op_iget_quick.S */ /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ /* op vA, vB, offset//CCCC */ srl a2, rINST, 12 # a2 <- B @@ -6278,7 +5592,6 @@ TODO /* ------------------------------ */ .balign 128 .L_op_iget_wide_quick: /* 0xe4 */ -/* File: mips64/op_iget_wide_quick.S */ /* iget-wide-quick vA, vB, offset//CCCC */ srl a2, rINST, 12 # a2 <- B lhu a4, 2(rPC) # a4 <- field byte offset @@ -6297,7 +5610,6 @@ TODO /* ------------------------------ */ .balign 128 .L_op_iget_object_quick: /* 0xe5 */ -/* File: mips64/op_iget_object_quick.S */ /* For: iget-object-quick */ /* op vA, vB, offset//CCCC */ .extern artIGetObjectFromMterp @@ -6318,7 +5630,6 @@ TODO /* ------------------------------ */ .balign 128 .L_op_iput_quick: /* 0xe6 */ -/* File: mips64/op_iput_quick.S */ /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */ /* op vA, vB, offset//CCCC */ srl a2, rINST, 12 # a2 <- B @@ -6336,7 +5647,6 @@ TODO /* ------------------------------ */ .balign 128 .L_op_iput_wide_quick: /* 0xe7 */ -/* File: mips64/op_iput_wide_quick.S */ /* iput-wide-quick vA, vB, offset//CCCC */ srl a2, rINST, 12 # a2 <- B lhu a3, 2(rPC) # a3 <- field byte offset @@ -6355,7 +5665,6 @@ TODO /* ------------------------------ */ .balign 128 .L_op_iput_object_quick: /* 0xe8 */ -/* File: mips64/op_iput_object_quick.S */ .extern MterpIputObjectQuick EXPORT_PC daddu a0, rFP, OFF_FP_SHADOWFRAME @@ -6370,8 +5679,6 @@ TODO /* ------------------------------ */ .balign 128 .L_op_invoke_virtual_quick: /* 0xe9 */ -/* File: mips64/op_invoke_virtual_quick.S */ -/* File: mips64/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -6392,12 +5699,9 @@ TODO GET_INST_OPCODE v0 GOTO_OPCODE v0 - /* ------------------------------ */ .balign 128 .L_op_invoke_virtual_range_quick: /* 0xea */ -/* File: mips64/op_invoke_virtual_range_quick.S */ -/* File: mips64/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -6418,12 +5722,9 @@ TODO GET_INST_OPCODE v0 GOTO_OPCODE v0 - /* ------------------------------ */ .balign 128 .L_op_iput_boolean_quick: /* 0xeb */ -/* File: mips64/op_iput_boolean_quick.S */ -/* File: mips64/op_iput_quick.S */ /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */ /* op vA, vB, offset//CCCC */ srl a2, rINST, 12 # a2 <- B @@ -6438,12 +5739,9 @@ TODO GET_INST_OPCODE v0 # extract opcode from rINST GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_iput_byte_quick: /* 0xec */ -/* File: mips64/op_iput_byte_quick.S */ -/* File: mips64/op_iput_quick.S */ /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */ /* op vA, vB, offset//CCCC */ srl a2, rINST, 12 # a2 <- B @@ -6458,12 +5756,9 @@ TODO GET_INST_OPCODE v0 # extract opcode from rINST GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_iput_char_quick: /* 0xed */ -/* File: mips64/op_iput_char_quick.S */ -/* File: mips64/op_iput_quick.S */ /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */ /* op vA, vB, offset//CCCC */ srl a2, rINST, 12 # a2 <- B @@ -6478,12 +5773,9 @@ TODO GET_INST_OPCODE v0 # extract opcode from rINST GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_iput_short_quick: /* 0xee */ -/* File: mips64/op_iput_short_quick.S */ -/* File: mips64/op_iput_quick.S */ /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */ /* op vA, vB, offset//CCCC */ srl a2, rINST, 12 # a2 <- B @@ -6498,12 +5790,9 @@ TODO GET_INST_OPCODE v0 # extract opcode from rINST GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_iget_boolean_quick: /* 0xef */ -/* File: mips64/op_iget_boolean_quick.S */ -/* File: mips64/op_iget_quick.S */ /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ /* op vA, vB, offset//CCCC */ srl a2, rINST, 12 # a2 <- B @@ -6518,12 +5807,9 @@ TODO GET_INST_OPCODE v0 # extract opcode from rINST GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_iget_byte_quick: /* 0xf0 */ -/* File: mips64/op_iget_byte_quick.S */ -/* File: mips64/op_iget_quick.S */ /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ /* op vA, vB, offset//CCCC */ srl a2, rINST, 12 # a2 <- B @@ -6538,12 +5824,9 @@ TODO GET_INST_OPCODE v0 # extract opcode from rINST GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_iget_char_quick: /* 0xf1 */ -/* File: mips64/op_iget_char_quick.S */ -/* File: mips64/op_iget_quick.S */ /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ /* op vA, vB, offset//CCCC */ srl a2, rINST, 12 # a2 <- B @@ -6558,12 +5841,9 @@ TODO GET_INST_OPCODE v0 # extract opcode from rINST GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_iget_short_quick: /* 0xf2 */ -/* File: mips64/op_iget_short_quick.S */ -/* File: mips64/op_iget_quick.S */ /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ /* op vA, vB, offset//CCCC */ srl a2, rINST, 12 # a2 <- B @@ -6578,89 +5858,65 @@ TODO GET_INST_OPCODE v0 # extract opcode from rINST GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_unused_f3: /* 0xf3 */ -/* File: mips64/op_unused_f3.S */ -/* File: mips64/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_f4: /* 0xf4 */ -/* File: mips64/op_unused_f4.S */ -/* File: mips64/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_f5: /* 0xf5 */ -/* File: mips64/op_unused_f5.S */ -/* File: mips64/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_f6: /* 0xf6 */ -/* File: mips64/op_unused_f6.S */ -/* File: mips64/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_f7: /* 0xf7 */ -/* File: mips64/op_unused_f7.S */ -/* File: mips64/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_f8: /* 0xf8 */ -/* File: mips64/op_unused_f8.S */ -/* File: mips64/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_f9: /* 0xf9 */ -/* File: mips64/op_unused_f9.S */ -/* File: mips64/unused.S */ /* * Bail to reference interpreter to throw. */ b MterpFallback - /* ------------------------------ */ .balign 128 .L_op_invoke_polymorphic: /* 0xfa */ -/* File: mips64/op_invoke_polymorphic.S */ -/* File: mips64/invoke_polymorphic.S */ /* * invoke-polymorphic handler wrapper. */ @@ -6681,12 +5937,9 @@ TODO GET_INST_OPCODE v0 GOTO_OPCODE v0 - /* ------------------------------ */ .balign 128 .L_op_invoke_polymorphic_range: /* 0xfb */ -/* File: mips64/op_invoke_polymorphic_range.S */ -/* File: mips64/invoke_polymorphic.S */ /* * invoke-polymorphic handler wrapper. */ @@ -6707,12 +5960,9 @@ TODO GET_INST_OPCODE v0 GOTO_OPCODE v0 - /* ------------------------------ */ .balign 128 .L_op_invoke_custom: /* 0xfc */ -/* File: mips64/op_invoke_custom.S */ -/* File: mips64/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -6733,12 +5983,9 @@ TODO GET_INST_OPCODE v0 GOTO_OPCODE v0 - /* ------------------------------ */ .balign 128 .L_op_invoke_custom_range: /* 0xfd */ -/* File: mips64/op_invoke_custom_range.S */ -/* File: mips64/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -6759,12 +6006,9 @@ TODO GET_INST_OPCODE v0 GOTO_OPCODE v0 - /* ------------------------------ */ .balign 128 .L_op_const_method_handle: /* 0xfe */ -/* File: mips64/op_const_method_handle.S */ -/* File: mips64/const.S */ /* const/class vAA, type@BBBB */ /* const/method-handle vAA, method_handle@BBBB */ /* const/method-type vAA, proto@BBBB */ @@ -6782,12 +6026,9 @@ TODO GET_INST_OPCODE v0 # extract opcode from rINST GOTO_OPCODE v0 # jump to next instruction - /* ------------------------------ */ .balign 128 .L_op_const_method_type: /* 0xff */ -/* File: mips64/op_const_method_type.S */ -/* File: mips64/const.S */ /* const/class vAA, type@BBBB */ /* const/method-handle vAA, method_handle@BBBB */ /* const/method-type vAA, proto@BBBB */ @@ -6805,41 +6046,25 @@ TODO GET_INST_OPCODE v0 # extract opcode from rINST GOTO_OPCODE v0 # jump to next instruction - .balign 128 -/* File: mips64/instruction_end.S */ .global artMterpAsmInstructionEnd artMterpAsmInstructionEnd: - -/* - * =========================================================================== - * Sister implementations - * =========================================================================== - */ -/* File: mips64/instruction_start_sister.S */ - .global artMterpAsmSisterStart .text .balign 4 artMterpAsmSisterStart: -/* File: mips64/instruction_end_sister.S */ - .global artMterpAsmSisterEnd artMterpAsmSisterEnd: -/* File: mips64/instruction_start_alt.S */ - .global artMterpAsmAltInstructionStart artMterpAsmAltInstructionStart = .L_ALT_op_nop .text - /* ------------------------------ */ .balign 128 .L_ALT_op_nop: /* 0x00 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6858,7 +6083,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move: /* 0x01 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6877,7 +6101,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_from16: /* 0x02 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6896,7 +6119,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_16: /* 0x03 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6915,7 +6137,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_wide: /* 0x04 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6934,7 +6155,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_wide_from16: /* 0x05 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6953,7 +6173,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_wide_16: /* 0x06 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6972,7 +6191,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_object: /* 0x07 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6991,7 +6209,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_object_from16: /* 0x08 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7010,7 +6227,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_object_16: /* 0x09 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7029,7 +6245,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_result: /* 0x0a */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7048,7 +6263,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_result_wide: /* 0x0b */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7067,7 +6281,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_result_object: /* 0x0c */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7086,7 +6299,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_exception: /* 0x0d */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7105,7 +6317,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_return_void: /* 0x0e */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7124,7 +6335,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_return: /* 0x0f */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7143,7 +6353,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_return_wide: /* 0x10 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7162,7 +6371,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_return_object: /* 0x11 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7181,7 +6389,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_4: /* 0x12 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7200,7 +6407,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_16: /* 0x13 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7219,7 +6425,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const: /* 0x14 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7238,7 +6443,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_high16: /* 0x15 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7257,7 +6461,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_wide_16: /* 0x16 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7276,7 +6479,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_wide_32: /* 0x17 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7295,7 +6497,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_wide: /* 0x18 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7314,7 +6515,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_wide_high16: /* 0x19 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7333,7 +6533,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_string: /* 0x1a */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7352,7 +6551,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_string_jumbo: /* 0x1b */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7371,7 +6569,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_class: /* 0x1c */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7390,7 +6587,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_monitor_enter: /* 0x1d */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7409,7 +6605,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_monitor_exit: /* 0x1e */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7428,7 +6623,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_check_cast: /* 0x1f */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7447,7 +6641,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_instance_of: /* 0x20 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7466,7 +6659,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_array_length: /* 0x21 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7485,7 +6677,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_new_instance: /* 0x22 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7504,7 +6695,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_new_array: /* 0x23 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7523,7 +6713,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_filled_new_array: /* 0x24 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7542,7 +6731,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_filled_new_array_range: /* 0x25 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7561,7 +6749,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_fill_array_data: /* 0x26 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7580,7 +6767,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_throw: /* 0x27 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7599,7 +6785,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_goto: /* 0x28 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7618,7 +6803,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_goto_16: /* 0x29 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7637,7 +6821,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_goto_32: /* 0x2a */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7656,7 +6839,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_packed_switch: /* 0x2b */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7675,7 +6857,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sparse_switch: /* 0x2c */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7694,7 +6875,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_cmpl_float: /* 0x2d */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7713,7 +6893,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_cmpg_float: /* 0x2e */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7732,7 +6911,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_cmpl_double: /* 0x2f */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7751,7 +6929,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_cmpg_double: /* 0x30 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7770,7 +6947,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_cmp_long: /* 0x31 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7789,7 +6965,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_eq: /* 0x32 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7808,7 +6983,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_ne: /* 0x33 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7827,7 +7001,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_lt: /* 0x34 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7846,7 +7019,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_ge: /* 0x35 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7865,7 +7037,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_gt: /* 0x36 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7884,7 +7055,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_le: /* 0x37 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7903,7 +7073,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_eqz: /* 0x38 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7922,7 +7091,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_nez: /* 0x39 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7941,7 +7109,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_ltz: /* 0x3a */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7960,7 +7127,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_gez: /* 0x3b */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7979,7 +7145,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_gtz: /* 0x3c */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7998,7 +7163,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_lez: /* 0x3d */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8017,7 +7181,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_3e: /* 0x3e */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8036,7 +7199,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_3f: /* 0x3f */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8055,7 +7217,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_40: /* 0x40 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8074,7 +7235,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_41: /* 0x41 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8093,7 +7253,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_42: /* 0x42 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8112,7 +7271,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_43: /* 0x43 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8131,7 +7289,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aget: /* 0x44 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8150,7 +7307,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aget_wide: /* 0x45 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8169,7 +7325,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aget_object: /* 0x46 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8188,7 +7343,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aget_boolean: /* 0x47 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8207,7 +7361,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aget_byte: /* 0x48 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8226,7 +7379,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aget_char: /* 0x49 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8245,7 +7397,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aget_short: /* 0x4a */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8264,7 +7415,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aput: /* 0x4b */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8283,7 +7433,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aput_wide: /* 0x4c */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8302,7 +7451,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aput_object: /* 0x4d */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8321,7 +7469,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aput_boolean: /* 0x4e */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8340,7 +7487,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aput_byte: /* 0x4f */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8359,7 +7505,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aput_char: /* 0x50 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8378,7 +7523,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aput_short: /* 0x51 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8397,7 +7541,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget: /* 0x52 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8416,7 +7559,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_wide: /* 0x53 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8435,7 +7577,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_object: /* 0x54 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8454,7 +7595,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_boolean: /* 0x55 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8473,7 +7613,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_byte: /* 0x56 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8492,7 +7631,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_char: /* 0x57 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8511,7 +7649,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_short: /* 0x58 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8530,7 +7667,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput: /* 0x59 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8549,7 +7685,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_wide: /* 0x5a */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8568,7 +7703,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_object: /* 0x5b */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8587,7 +7721,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_boolean: /* 0x5c */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8606,7 +7739,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_byte: /* 0x5d */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8625,7 +7757,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_char: /* 0x5e */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8644,7 +7775,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_short: /* 0x5f */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8663,7 +7793,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sget: /* 0x60 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8682,7 +7811,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sget_wide: /* 0x61 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8701,7 +7829,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sget_object: /* 0x62 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8720,7 +7847,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sget_boolean: /* 0x63 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8739,7 +7865,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sget_byte: /* 0x64 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8758,7 +7883,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sget_char: /* 0x65 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8777,7 +7901,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sget_short: /* 0x66 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8796,7 +7919,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sput: /* 0x67 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8815,7 +7937,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sput_wide: /* 0x68 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8834,7 +7955,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sput_object: /* 0x69 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8853,7 +7973,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sput_boolean: /* 0x6a */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8872,7 +7991,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sput_byte: /* 0x6b */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8891,7 +8009,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sput_char: /* 0x6c */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8910,7 +8027,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sput_short: /* 0x6d */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8929,7 +8045,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_virtual: /* 0x6e */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8948,7 +8063,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_super: /* 0x6f */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8967,7 +8081,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_direct: /* 0x70 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8986,7 +8099,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_static: /* 0x71 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9005,7 +8117,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_interface: /* 0x72 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9024,7 +8135,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_return_void_no_barrier: /* 0x73 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9043,7 +8153,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_virtual_range: /* 0x74 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9062,7 +8171,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_super_range: /* 0x75 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9081,7 +8189,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_direct_range: /* 0x76 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9100,7 +8207,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_static_range: /* 0x77 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9119,7 +8225,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_interface_range: /* 0x78 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9138,7 +8243,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_79: /* 0x79 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9157,7 +8261,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_7a: /* 0x7a */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9176,7 +8279,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_neg_int: /* 0x7b */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9195,7 +8297,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_not_int: /* 0x7c */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9214,7 +8315,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_neg_long: /* 0x7d */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9233,7 +8333,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_not_long: /* 0x7e */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9252,7 +8351,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_neg_float: /* 0x7f */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9271,7 +8369,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_neg_double: /* 0x80 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9290,7 +8387,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_int_to_long: /* 0x81 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9309,7 +8405,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_int_to_float: /* 0x82 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9328,7 +8423,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_int_to_double: /* 0x83 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9347,7 +8441,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_long_to_int: /* 0x84 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9366,7 +8459,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_long_to_float: /* 0x85 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9385,7 +8477,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_long_to_double: /* 0x86 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9404,7 +8495,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_float_to_int: /* 0x87 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9423,7 +8513,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_float_to_long: /* 0x88 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9442,7 +8531,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_float_to_double: /* 0x89 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9461,7 +8549,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_double_to_int: /* 0x8a */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9480,7 +8567,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_double_to_long: /* 0x8b */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9499,7 +8585,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_double_to_float: /* 0x8c */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9518,7 +8603,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_int_to_byte: /* 0x8d */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9537,7 +8621,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_int_to_char: /* 0x8e */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9556,7 +8639,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_int_to_short: /* 0x8f */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9575,7 +8657,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_int: /* 0x90 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9594,7 +8675,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_int: /* 0x91 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9613,7 +8693,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_int: /* 0x92 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9632,7 +8711,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_int: /* 0x93 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9651,7 +8729,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_int: /* 0x94 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9670,7 +8747,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_and_int: /* 0x95 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9689,7 +8765,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_or_int: /* 0x96 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9708,7 +8783,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_xor_int: /* 0x97 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9727,7 +8801,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shl_int: /* 0x98 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9746,7 +8819,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shr_int: /* 0x99 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9765,7 +8837,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_ushr_int: /* 0x9a */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9784,7 +8855,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_long: /* 0x9b */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9803,7 +8873,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_long: /* 0x9c */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9822,7 +8891,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_long: /* 0x9d */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9841,7 +8909,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_long: /* 0x9e */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9860,7 +8927,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_long: /* 0x9f */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9879,7 +8945,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_and_long: /* 0xa0 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9898,7 +8963,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_or_long: /* 0xa1 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9917,7 +8981,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_xor_long: /* 0xa2 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9936,7 +8999,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shl_long: /* 0xa3 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9955,7 +9017,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shr_long: /* 0xa4 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9974,7 +9035,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_ushr_long: /* 0xa5 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9993,7 +9053,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_float: /* 0xa6 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10012,7 +9071,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_float: /* 0xa7 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10031,7 +9089,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_float: /* 0xa8 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10050,7 +9107,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_float: /* 0xa9 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10069,7 +9125,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_float: /* 0xaa */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10088,7 +9143,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_double: /* 0xab */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10107,7 +9161,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_double: /* 0xac */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10126,7 +9179,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_double: /* 0xad */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10145,7 +9197,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_double: /* 0xae */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10164,7 +9215,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_double: /* 0xaf */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10183,7 +9233,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_int_2addr: /* 0xb0 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10202,7 +9251,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_int_2addr: /* 0xb1 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10221,7 +9269,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_int_2addr: /* 0xb2 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10240,7 +9287,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_int_2addr: /* 0xb3 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10259,7 +9305,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_int_2addr: /* 0xb4 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10278,7 +9323,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_and_int_2addr: /* 0xb5 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10297,7 +9341,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_or_int_2addr: /* 0xb6 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10316,7 +9359,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_xor_int_2addr: /* 0xb7 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10335,7 +9377,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shl_int_2addr: /* 0xb8 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10354,7 +9395,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shr_int_2addr: /* 0xb9 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10373,7 +9413,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_ushr_int_2addr: /* 0xba */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10392,7 +9431,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_long_2addr: /* 0xbb */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10411,7 +9449,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_long_2addr: /* 0xbc */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10430,7 +9467,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_long_2addr: /* 0xbd */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10449,7 +9485,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_long_2addr: /* 0xbe */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10468,7 +9503,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_long_2addr: /* 0xbf */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10487,7 +9521,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_and_long_2addr: /* 0xc0 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10506,7 +9539,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_or_long_2addr: /* 0xc1 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10525,7 +9557,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_xor_long_2addr: /* 0xc2 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10544,7 +9575,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shl_long_2addr: /* 0xc3 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10563,7 +9593,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shr_long_2addr: /* 0xc4 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10582,7 +9611,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_ushr_long_2addr: /* 0xc5 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10601,7 +9629,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_float_2addr: /* 0xc6 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10620,7 +9647,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_float_2addr: /* 0xc7 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10639,7 +9665,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_float_2addr: /* 0xc8 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10658,7 +9683,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_float_2addr: /* 0xc9 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10677,7 +9701,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_float_2addr: /* 0xca */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10696,7 +9719,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_double_2addr: /* 0xcb */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10715,7 +9737,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_double_2addr: /* 0xcc */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10734,7 +9755,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_double_2addr: /* 0xcd */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10753,7 +9773,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_double_2addr: /* 0xce */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10772,7 +9791,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_double_2addr: /* 0xcf */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10791,7 +9809,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_int_lit16: /* 0xd0 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10810,7 +9827,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rsub_int: /* 0xd1 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10829,7 +9845,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_int_lit16: /* 0xd2 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10848,7 +9863,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_int_lit16: /* 0xd3 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10867,7 +9881,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_int_lit16: /* 0xd4 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10886,7 +9899,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_and_int_lit16: /* 0xd5 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10905,7 +9917,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_or_int_lit16: /* 0xd6 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10924,7 +9935,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_xor_int_lit16: /* 0xd7 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10943,7 +9953,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_int_lit8: /* 0xd8 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10962,7 +9971,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rsub_int_lit8: /* 0xd9 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10981,7 +9989,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_int_lit8: /* 0xda */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11000,7 +10007,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_int_lit8: /* 0xdb */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11019,7 +10025,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_int_lit8: /* 0xdc */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11038,7 +10043,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_and_int_lit8: /* 0xdd */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11057,7 +10061,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_or_int_lit8: /* 0xde */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11076,7 +10079,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_xor_int_lit8: /* 0xdf */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11095,7 +10097,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shl_int_lit8: /* 0xe0 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11114,7 +10115,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shr_int_lit8: /* 0xe1 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11133,7 +10133,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_ushr_int_lit8: /* 0xe2 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11152,7 +10151,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_quick: /* 0xe3 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11171,7 +10169,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_wide_quick: /* 0xe4 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11190,7 +10187,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_object_quick: /* 0xe5 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11209,7 +10205,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_quick: /* 0xe6 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11228,7 +10223,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_wide_quick: /* 0xe7 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11247,7 +10241,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_object_quick: /* 0xe8 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11266,7 +10259,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_virtual_quick: /* 0xe9 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11285,7 +10277,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_virtual_range_quick: /* 0xea */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11304,7 +10295,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_boolean_quick: /* 0xeb */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11323,7 +10313,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_byte_quick: /* 0xec */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11342,7 +10331,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_char_quick: /* 0xed */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11361,7 +10349,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_short_quick: /* 0xee */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11380,7 +10367,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_boolean_quick: /* 0xef */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11399,7 +10385,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_byte_quick: /* 0xf0 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11418,7 +10403,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_char_quick: /* 0xf1 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11437,7 +10421,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_short_quick: /* 0xf2 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11456,7 +10439,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_f3: /* 0xf3 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11475,7 +10457,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_f4: /* 0xf4 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11494,7 +10475,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_f5: /* 0xf5 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11513,7 +10493,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_f6: /* 0xf6 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11532,7 +10511,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_f7: /* 0xf7 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11551,7 +10529,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_f8: /* 0xf8 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11570,7 +10547,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_f9: /* 0xf9 */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11589,7 +10565,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_polymorphic: /* 0xfa */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11608,7 +10583,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_polymorphic_range: /* 0xfb */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11627,7 +10601,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_custom: /* 0xfc */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11646,7 +10619,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_custom_range: /* 0xfd */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11665,7 +10637,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_method_handle: /* 0xfe */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11684,7 +10655,6 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_method_type: /* 0xff */ -/* File: mips64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11701,12 +10671,9 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. .balign 128 -/* File: mips64/instruction_end_alt.S */ .global artMterpAsmAltInstructionEnd artMterpAsmAltInstructionEnd: - -/* File: mips64/footer.S */ /* * We've detected a condition that will result in an exception, but the exception * has not yet been thrown. Just bail out to the reference interpreter to deal with it. @@ -11880,7 +10847,7 @@ MterpCommonTakenBranchNoFlags: EXPORT_PC jal MterpMaybeDoOnStackReplacement # (self, shadow_frame, offset) bnezc v0, MterpOnStackReplacement - FETCH_ADVANCE_INST 2 + FETCH_ADVANCE_INST 2 GET_INST_OPCODE v0 # extract opcode from rINST GOTO_OPCODE v0 # jump to next instruction @@ -11983,4 +10950,3 @@ MterpProfileActive: .cfi_endproc .set reorder .size ExecuteMterpImpl, .-ExecuteMterpImpl - diff --git a/runtime/interpreter/mterp/out/mterp_x86.S b/runtime/interpreter/mterp/out/mterp_x86.S index 32811ff370..5a1bbf264b 100644 --- a/runtime/interpreter/mterp/out/mterp_x86.S +++ b/runtime/interpreter/mterp/out/mterp_x86.S @@ -1,10 +1,4 @@ -/* - * This file was generated automatically by gen-mterp.py for 'x86'. - * - * --> DO NOT EDIT <-- - */ - -/* File: x86/header.S */ +/* DO NOT EDIT: This file was generated by gen-mterp.py. */ /* * Copyright (C) 2016 The Android Open Source Project * @@ -321,8 +315,6 @@ unspecified registers or condition codes. movl MACRO_LITERAL(0), (rREFS,\_vreg,4) movl MACRO_LITERAL(0), 4(rREFS,\_vreg,4) .endm - -/* File: x86/entry.S */ /* * Copyright (C) 2016 The Android Open Source Project * @@ -407,24 +399,19 @@ SYMBOL(ExecuteMterpImpl): GOTO_NEXT /* NOTE: no fallthrough */ -/* File: x86/instruction_start.S */ - OBJECT_TYPE(artMterpAsmInstructionStart) ASM_HIDDEN SYMBOL(artMterpAsmInstructionStart) .global SYMBOL(artMterpAsmInstructionStart) SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .text - /* ------------------------------ */ .balign 128 .L_op_nop: /* 0x00 */ -/* File: x86/op_nop.S */ ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 /* ------------------------------ */ .balign 128 .L_op_move: /* 0x01 */ -/* File: x86/op_move.S */ /* for move, move-object, long-to-int */ /* op vA, vB */ movzbl rINSTbl, %eax # eax <- BA @@ -441,7 +428,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_from16: /* 0x02 */ -/* File: x86/op_move_from16.S */ /* for: move/from16, move-object/from16 */ /* op vAA, vBBBB */ movzx rINSTbl, %eax # eax <- AA @@ -457,7 +443,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_16: /* 0x03 */ -/* File: x86/op_move_16.S */ /* for: move/16, move-object/16 */ /* op vAAAA, vBBBB */ movzwl 4(rPC), %ecx # ecx <- BBBB @@ -473,7 +458,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_wide: /* 0x04 */ -/* File: x86/op_move_wide.S */ /* move-wide vA, vB */ /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ movzbl rINSTbl, %ecx # ecx <- BA @@ -486,7 +470,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_wide_from16: /* 0x05 */ -/* File: x86/op_move_wide_from16.S */ /* move-wide/from16 vAA, vBBBB */ /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ movzwl 2(rPC), %ecx # ecx <- BBBB @@ -498,7 +481,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_wide_16: /* 0x06 */ -/* File: x86/op_move_wide_16.S */ /* move-wide/16 vAAAA, vBBBB */ /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ movzwl 4(rPC), %ecx # ecx<- BBBB @@ -510,8 +492,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_object: /* 0x07 */ -/* File: x86/op_move_object.S */ -/* File: x86/op_move.S */ /* for move, move-object, long-to-int */ /* op vA, vB */ movzbl rINSTbl, %eax # eax <- BA @@ -525,12 +505,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_move_object_from16: /* 0x08 */ -/* File: x86/op_move_object_from16.S */ -/* File: x86/op_move_from16.S */ /* for: move/from16, move-object/from16 */ /* op vAA, vBBBB */ movzx rINSTbl, %eax # eax <- AA @@ -543,12 +520,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_move_object_16: /* 0x09 */ -/* File: x86/op_move_object_16.S */ -/* File: x86/op_move_16.S */ /* for: move/16, move-object/16 */ /* op vAAAA, vBBBB */ movzwl 4(rPC), %ecx # ecx <- BBBB @@ -561,11 +535,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 - /* ------------------------------ */ .balign 128 .L_op_move_result: /* 0x0a */ -/* File: x86/op_move_result.S */ /* for: move-result, move-result-object */ /* op vAA */ movl OFF_FP_RESULT_REGISTER(rFP), %eax # get pointer to result JType. @@ -580,7 +552,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_result_wide: /* 0x0b */ -/* File: x86/op_move_result_wide.S */ /* move-result-wide vAA */ movl OFF_FP_RESULT_REGISTER(rFP), %eax # get pointer to result JType. movl 4(%eax), %ecx # Get high @@ -592,8 +563,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_result_object: /* 0x0c */ -/* File: x86/op_move_result_object.S */ -/* File: x86/op_move_result.S */ /* for: move-result, move-result-object */ /* op vAA */ movl OFF_FP_RESULT_REGISTER(rFP), %eax # get pointer to result JType. @@ -605,11 +574,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_move_exception: /* 0x0d */ -/* File: x86/op_move_exception.S */ /* move-exception vAA */ movl rSELF, %ecx movl THREAD_EXCEPTION_OFFSET(%ecx), %eax @@ -620,7 +587,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_return_void: /* 0x0e */ -/* File: x86/op_return_void.S */ .extern MterpThreadFenceForConstructor call SYMBOL(MterpThreadFenceForConstructor) movl rSELF, %eax @@ -636,7 +602,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_return: /* 0x0f */ -/* File: x86/op_return.S */ /* * Return a 32-bit value. * @@ -658,7 +623,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_return_wide: /* 0x10 */ -/* File: x86/op_return_wide.S */ /* * Return a 64-bit value. */ @@ -678,8 +642,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_return_object: /* 0x11 */ -/* File: x86/op_return_object.S */ -/* File: x86/op_return.S */ /* * Return a 32-bit value. * @@ -698,11 +660,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop xorl %ecx, %ecx jmp MterpReturn - /* ------------------------------ */ .balign 128 .L_op_const_4: /* 0x12 */ -/* File: x86/op_const_4.S */ /* const/4 vA, #+B */ movsx rINSTbl, %eax # eax <-ssssssBx movl $0xf, rINST @@ -714,7 +674,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_16: /* 0x13 */ -/* File: x86/op_const_16.S */ /* const/16 vAA, #+BBBB */ movswl 2(rPC), %ecx # ecx <- ssssBBBB SET_VREG %ecx, rINST # vAA <- ssssBBBB @@ -723,7 +682,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const: /* 0x14 */ -/* File: x86/op_const.S */ /* const vAA, #+BBBBbbbb */ movl 2(rPC), %eax # grab all 32 bits at once SET_VREG %eax, rINST # vAA<- eax @@ -732,7 +690,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_high16: /* 0x15 */ -/* File: x86/op_const_high16.S */ /* const/high16 vAA, #+BBBB0000 */ movzwl 2(rPC), %eax # eax <- 0000BBBB sall $16, %eax # eax <- BBBB0000 @@ -742,7 +699,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_wide_16: /* 0x16 */ -/* File: x86/op_const_wide_16.S */ /* const-wide/16 vAA, #+BBBB */ movswl 2(rPC), %eax # eax <- ssssBBBB movl rIBASE, %ecx # preserve rIBASE (cltd trashes it) @@ -755,7 +711,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_wide_32: /* 0x17 */ -/* File: x86/op_const_wide_32.S */ /* const-wide/32 vAA, #+BBBBbbbb */ movl 2(rPC), %eax # eax <- BBBBbbbb movl rIBASE, %ecx # preserve rIBASE (cltd trashes it) @@ -768,7 +723,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_wide: /* 0x18 */ -/* File: x86/op_const_wide.S */ /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ movl 2(rPC), %eax # eax <- lsw movzbl rINSTbl, %ecx # ecx <- AA @@ -780,7 +734,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_wide_high16: /* 0x19 */ -/* File: x86/op_const_wide_high16.S */ /* const-wide/high16 vAA, #+BBBB000000000000 */ movzwl 2(rPC), %eax # eax <- 0000BBBB sall $16, %eax # eax <- BBBB0000 @@ -792,8 +745,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_string: /* 0x1a */ -/* File: x86/op_const_string.S */ -/* File: x86/const.S */ /* const/class vAA, type@BBBB */ /* const/method-handle vAA, method_handle@BBBB */ /* const/method-type vAA, proto@BBBB */ @@ -813,11 +764,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop jnz MterpPossibleException ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_const_string_jumbo: /* 0x1b */ -/* File: x86/op_const_string_jumbo.S */ /* const/string vAA, String@BBBBBBBB */ EXPORT_PC movl 2(rPC), %eax # eax <- BBBB @@ -836,8 +785,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_class: /* 0x1c */ -/* File: x86/op_const_class.S */ -/* File: x86/const.S */ /* const/class vAA, type@BBBB */ /* const/method-handle vAA, method_handle@BBBB */ /* const/method-type vAA, proto@BBBB */ @@ -857,11 +804,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop jnz MterpPossibleException ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_monitor_enter: /* 0x1d */ -/* File: x86/op_monitor_enter.S */ /* * Synchronize on an object. */ @@ -880,7 +825,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_monitor_exit: /* 0x1e */ -/* File: x86/op_monitor_exit.S */ /* * Unlock an object. * @@ -903,7 +847,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_check_cast: /* 0x1f */ -/* File: x86/op_check_cast.S */ /* * Check to see if a cast from one class to another is allowed. */ @@ -926,7 +869,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_instance_of: /* 0x20 */ -/* File: x86/op_instance_of.S */ /* * Check to see if an object reference is an instance of a class. * @@ -957,7 +899,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_array_length: /* 0x21 */ -/* File: x86/op_array_length.S */ /* * Return the length of an array. */ @@ -974,7 +915,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_new_instance: /* 0x22 */ -/* File: x86/op_new_instance.S */ /* * Create a new instance of a class. */ @@ -995,7 +935,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_new_array: /* 0x23 */ -/* File: x86/op_new_array.S */ /* * Allocate an array of objects, specified with the array class * and a count. @@ -1021,7 +960,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_filled_new_array: /* 0x24 */ -/* File: x86/op_filled_new_array.S */ /* * Create a new array with elements filled from registers. * @@ -1045,8 +983,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_filled_new_array_range: /* 0x25 */ -/* File: x86/op_filled_new_array_range.S */ -/* File: x86/op_filled_new_array.S */ /* * Create a new array with elements filled from registers. * @@ -1067,11 +1003,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop jz MterpPossibleException ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 - /* ------------------------------ */ .balign 128 .L_op_fill_array_data: /* 0x26 */ -/* File: x86/op_fill_array_data.S */ /* fill-array-data vAA, +BBBBBBBB */ EXPORT_PC movl 2(rPC), %ecx # ecx <- BBBBbbbb @@ -1088,7 +1022,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_throw: /* 0x27 */ -/* File: x86/op_throw.S */ /* * Throw an exception object in the current thread. */ @@ -1104,7 +1037,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_goto: /* 0x28 */ -/* File: x86/op_goto.S */ /* * Unconditional branch, 8-bit offset. * @@ -1119,7 +1051,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_goto_16: /* 0x29 */ -/* File: x86/op_goto_16.S */ /* * Unconditional branch, 16-bit offset. * @@ -1134,7 +1065,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_goto_32: /* 0x2a */ -/* File: x86/op_goto_32.S */ /* * Unconditional branch, 32-bit offset. * @@ -1154,7 +1084,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_packed_switch: /* 0x2b */ -/* File: x86/op_packed_switch.S */ /* * Handle a packed-switch or sparse-switch instruction. In both cases * we decode it and hand it off to a helper function. @@ -1179,8 +1108,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_sparse_switch: /* 0x2c */ -/* File: x86/op_sparse_switch.S */ -/* File: x86/op_packed_switch.S */ /* * Handle a packed-switch or sparse-switch instruction. In both cases * we decode it and hand it off to a helper function. @@ -1202,12 +1129,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop movl %eax, rINST jmp MterpCommonTakenBranch - /* ------------------------------ */ .balign 128 .L_op_cmpl_float: /* 0x2d */ -/* File: x86/op_cmpl_float.S */ -/* File: x86/fpcmp.S */ /* * Compare two floating-point values. Puts 0, 1, or -1 into the * destination register based on the results of the comparison. @@ -1243,12 +1167,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %eax, rINST ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_cmpg_float: /* 0x2e */ -/* File: x86/op_cmpg_float.S */ -/* File: x86/fpcmp.S */ /* * Compare two floating-point values. Puts 0, 1, or -1 into the * destination register based on the results of the comparison. @@ -1284,12 +1205,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %eax, rINST ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_cmpl_double: /* 0x2f */ -/* File: x86/op_cmpl_double.S */ -/* File: x86/fpcmp.S */ /* * Compare two floating-point values. Puts 0, 1, or -1 into the * destination register based on the results of the comparison. @@ -1325,12 +1243,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %eax, rINST ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_cmpg_double: /* 0x30 */ -/* File: x86/op_cmpg_double.S */ -/* File: x86/fpcmp.S */ /* * Compare two floating-point values. Puts 0, 1, or -1 into the * destination register based on the results of the comparison. @@ -1366,11 +1281,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %eax, rINST ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_cmp_long: /* 0x31 */ -/* File: x86/op_cmp_long.S */ /* * Compare two 64-bit values. Puts 0, 1, or -1 into the destination * register based on the results of the comparison. @@ -1402,8 +1315,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_if_eq: /* 0x32 */ -/* File: x86/op_if_eq.S */ -/* File: x86/bincmp.S */ /* * Generic two-operand compare-and-branch operation. Provide a "revcmp" * fragment that specifies the *reverse* comparison to perform, e.g. @@ -1426,12 +1337,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop je .L_check_not_taken_osr ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_if_ne: /* 0x33 */ -/* File: x86/op_if_ne.S */ -/* File: x86/bincmp.S */ /* * Generic two-operand compare-and-branch operation. Provide a "revcmp" * fragment that specifies the *reverse* comparison to perform, e.g. @@ -1454,12 +1362,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop je .L_check_not_taken_osr ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_if_lt: /* 0x34 */ -/* File: x86/op_if_lt.S */ -/* File: x86/bincmp.S */ /* * Generic two-operand compare-and-branch operation. Provide a "revcmp" * fragment that specifies the *reverse* comparison to perform, e.g. @@ -1482,12 +1387,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop je .L_check_not_taken_osr ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_if_ge: /* 0x35 */ -/* File: x86/op_if_ge.S */ -/* File: x86/bincmp.S */ /* * Generic two-operand compare-and-branch operation. Provide a "revcmp" * fragment that specifies the *reverse* comparison to perform, e.g. @@ -1510,12 +1412,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop je .L_check_not_taken_osr ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_if_gt: /* 0x36 */ -/* File: x86/op_if_gt.S */ -/* File: x86/bincmp.S */ /* * Generic two-operand compare-and-branch operation. Provide a "revcmp" * fragment that specifies the *reverse* comparison to perform, e.g. @@ -1538,12 +1437,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop je .L_check_not_taken_osr ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_if_le: /* 0x37 */ -/* File: x86/op_if_le.S */ -/* File: x86/bincmp.S */ /* * Generic two-operand compare-and-branch operation. Provide a "revcmp" * fragment that specifies the *reverse* comparison to perform, e.g. @@ -1566,12 +1462,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop je .L_check_not_taken_osr ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_if_eqz: /* 0x38 */ -/* File: x86/op_if_eqz.S */ -/* File: x86/zcmp.S */ /* * Generic one-operand compare-and-branch operation. Provide a "revcmp" * fragment that specifies the *reverse* comparison to perform, e.g. @@ -1590,12 +1483,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop je .L_check_not_taken_osr ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_if_nez: /* 0x39 */ -/* File: x86/op_if_nez.S */ -/* File: x86/zcmp.S */ /* * Generic one-operand compare-and-branch operation. Provide a "revcmp" * fragment that specifies the *reverse* comparison to perform, e.g. @@ -1614,12 +1504,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop je .L_check_not_taken_osr ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_if_ltz: /* 0x3a */ -/* File: x86/op_if_ltz.S */ -/* File: x86/zcmp.S */ /* * Generic one-operand compare-and-branch operation. Provide a "revcmp" * fragment that specifies the *reverse* comparison to perform, e.g. @@ -1638,12 +1525,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop je .L_check_not_taken_osr ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_if_gez: /* 0x3b */ -/* File: x86/op_if_gez.S */ -/* File: x86/zcmp.S */ /* * Generic one-operand compare-and-branch operation. Provide a "revcmp" * fragment that specifies the *reverse* comparison to perform, e.g. @@ -1662,12 +1546,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop je .L_check_not_taken_osr ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_if_gtz: /* 0x3c */ -/* File: x86/op_if_gtz.S */ -/* File: x86/zcmp.S */ /* * Generic one-operand compare-and-branch operation. Provide a "revcmp" * fragment that specifies the *reverse* comparison to perform, e.g. @@ -1686,12 +1567,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop je .L_check_not_taken_osr ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_if_lez: /* 0x3d */ -/* File: x86/op_if_lez.S */ -/* File: x86/zcmp.S */ /* * Generic one-operand compare-and-branch operation. Provide a "revcmp" * fragment that specifies the *reverse* comparison to perform, e.g. @@ -1710,77 +1588,57 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop je .L_check_not_taken_osr ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_unused_3e: /* 0x3e */ -/* File: x86/op_unused_3e.S */ -/* File: x86/unused.S */ /* * Bail to reference interpreter to throw. */ jmp MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_3f: /* 0x3f */ -/* File: x86/op_unused_3f.S */ -/* File: x86/unused.S */ /* * Bail to reference interpreter to throw. */ jmp MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_40: /* 0x40 */ -/* File: x86/op_unused_40.S */ -/* File: x86/unused.S */ /* * Bail to reference interpreter to throw. */ jmp MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_41: /* 0x41 */ -/* File: x86/op_unused_41.S */ -/* File: x86/unused.S */ /* * Bail to reference interpreter to throw. */ jmp MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_42: /* 0x42 */ -/* File: x86/op_unused_42.S */ -/* File: x86/unused.S */ /* * Bail to reference interpreter to throw. */ jmp MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_43: /* 0x43 */ -/* File: x86/op_unused_43.S */ -/* File: x86/unused.S */ /* * Bail to reference interpreter to throw. */ jmp MterpFallback - /* ------------------------------ */ .balign 128 .L_op_aget: /* 0x44 */ -/* File: x86/op_aget.S */ /* * Array get, 32 bits or less. vAA <- vBB[vCC]. * @@ -1803,7 +1661,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_aget_wide: /* 0x45 */ -/* File: x86/op_aget_wide.S */ /* * Array get, 64 bits. vAA <- vBB[vCC]. */ @@ -1824,7 +1681,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_aget_object: /* 0x46 */ -/* File: x86/op_aget_object.S */ /* * Array object get. vAA <- vBB[vCC]. * @@ -1849,8 +1705,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_aget_boolean: /* 0x47 */ -/* File: x86/op_aget_boolean.S */ -/* File: x86/op_aget.S */ /* * Array get, 32 bits or less. vAA <- vBB[vCC]. * @@ -1870,12 +1724,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %eax, rINST ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_aget_byte: /* 0x48 */ -/* File: x86/op_aget_byte.S */ -/* File: x86/op_aget.S */ /* * Array get, 32 bits or less. vAA <- vBB[vCC]. * @@ -1895,12 +1746,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %eax, rINST ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_aget_char: /* 0x49 */ -/* File: x86/op_aget_char.S */ -/* File: x86/op_aget.S */ /* * Array get, 32 bits or less. vAA <- vBB[vCC]. * @@ -1920,12 +1768,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %eax, rINST ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_aget_short: /* 0x4a */ -/* File: x86/op_aget_short.S */ -/* File: x86/op_aget.S */ /* * Array get, 32 bits or less. vAA <- vBB[vCC]. * @@ -1945,11 +1790,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %eax, rINST ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_aput: /* 0x4b */ -/* File: x86/op_aput.S */ /* * Array put, 32 bits or less. vBB[vCC] <- vAA. * @@ -1973,7 +1816,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_aput_wide: /* 0x4c */ -/* File: x86/op_aput_wide.S */ /* * Array put, 64 bits. vBB[vCC] <- vAA. * @@ -1995,7 +1837,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_aput_object: /* 0x4d */ -/* File: x86/op_aput_object.S */ /* * Store an object into an array. vBB[vCC] <- vAA. */ @@ -2015,8 +1856,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_aput_boolean: /* 0x4e */ -/* File: x86/op_aput_boolean.S */ -/* File: x86/op_aput.S */ /* * Array put, 32 bits or less. vBB[vCC] <- vAA. * @@ -2037,12 +1876,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop movb rINSTbl, (%eax) ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_aput_byte: /* 0x4f */ -/* File: x86/op_aput_byte.S */ -/* File: x86/op_aput.S */ /* * Array put, 32 bits or less. vBB[vCC] <- vAA. * @@ -2063,12 +1899,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop movb rINSTbl, (%eax) ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_aput_char: /* 0x50 */ -/* File: x86/op_aput_char.S */ -/* File: x86/op_aput.S */ /* * Array put, 32 bits or less. vBB[vCC] <- vAA. * @@ -2089,12 +1922,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop movw rINSTw, (%eax) ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_aput_short: /* 0x51 */ -/* File: x86/op_aput_short.S */ -/* File: x86/op_aput.S */ /* * Array put, 32 bits or less. vBB[vCC] <- vAA. * @@ -2115,12 +1945,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop movw rINSTw, (%eax) ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_iget: /* 0x52 */ -/* File: x86/op_iget.S */ -/* File: x86/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2138,13 +1965,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop RESTORE_IBASE ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_iget_wide: /* 0x53 */ -/* File: x86/op_iget_wide.S */ -/* File: x86/op_iget.S */ -/* File: x86/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2162,14 +1985,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop RESTORE_IBASE ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_iget_object: /* 0x54 */ -/* File: x86/op_iget_object.S */ -/* File: x86/op_iget.S */ -/* File: x86/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2187,14 +2005,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop RESTORE_IBASE ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_iget_boolean: /* 0x55 */ -/* File: x86/op_iget_boolean.S */ -/* File: x86/op_iget.S */ -/* File: x86/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2212,14 +2025,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop RESTORE_IBASE ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_iget_byte: /* 0x56 */ -/* File: x86/op_iget_byte.S */ -/* File: x86/op_iget.S */ -/* File: x86/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2237,14 +2045,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop RESTORE_IBASE ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_iget_char: /* 0x57 */ -/* File: x86/op_iget_char.S */ -/* File: x86/op_iget.S */ -/* File: x86/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2262,14 +2065,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop RESTORE_IBASE ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_iget_short: /* 0x58 */ -/* File: x86/op_iget_short.S */ -/* File: x86/op_iget.S */ -/* File: x86/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2287,13 +2085,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop RESTORE_IBASE ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_iput: /* 0x59 */ -/* File: x86/op_iput.S */ -/* File: x86/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2311,13 +2105,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop RESTORE_IBASE ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_iput_wide: /* 0x5a */ -/* File: x86/op_iput_wide.S */ -/* File: x86/op_iput.S */ -/* File: x86/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2335,14 +2125,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop RESTORE_IBASE ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_iput_object: /* 0x5b */ -/* File: x86/op_iput_object.S */ -/* File: x86/op_iput.S */ -/* File: x86/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2360,14 +2145,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop RESTORE_IBASE ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_iput_boolean: /* 0x5c */ -/* File: x86/op_iput_boolean.S */ -/* File: x86/op_iput.S */ -/* File: x86/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2385,14 +2165,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop RESTORE_IBASE ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_iput_byte: /* 0x5d */ -/* File: x86/op_iput_byte.S */ -/* File: x86/op_iput.S */ -/* File: x86/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2410,14 +2185,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop RESTORE_IBASE ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_iput_char: /* 0x5e */ -/* File: x86/op_iput_char.S */ -/* File: x86/op_iput.S */ -/* File: x86/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2435,14 +2205,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop RESTORE_IBASE ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_iput_short: /* 0x5f */ -/* File: x86/op_iput_short.S */ -/* File: x86/op_iput.S */ -/* File: x86/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2460,13 +2225,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop RESTORE_IBASE ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_sget: /* 0x60 */ -/* File: x86/op_sget.S */ -/* File: x86/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2484,13 +2245,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop RESTORE_IBASE ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_sget_wide: /* 0x61 */ -/* File: x86/op_sget_wide.S */ -/* File: x86/op_sget.S */ -/* File: x86/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2508,14 +2265,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop RESTORE_IBASE ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_sget_object: /* 0x62 */ -/* File: x86/op_sget_object.S */ -/* File: x86/op_sget.S */ -/* File: x86/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2533,14 +2285,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop RESTORE_IBASE ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_sget_boolean: /* 0x63 */ -/* File: x86/op_sget_boolean.S */ -/* File: x86/op_sget.S */ -/* File: x86/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2558,14 +2305,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop RESTORE_IBASE ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_sget_byte: /* 0x64 */ -/* File: x86/op_sget_byte.S */ -/* File: x86/op_sget.S */ -/* File: x86/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2583,14 +2325,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop RESTORE_IBASE ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_sget_char: /* 0x65 */ -/* File: x86/op_sget_char.S */ -/* File: x86/op_sget.S */ -/* File: x86/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2608,14 +2345,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop RESTORE_IBASE ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_sget_short: /* 0x66 */ -/* File: x86/op_sget_short.S */ -/* File: x86/op_sget.S */ -/* File: x86/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2633,13 +2365,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop RESTORE_IBASE ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_sput: /* 0x67 */ -/* File: x86/op_sput.S */ -/* File: x86/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2657,13 +2385,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop RESTORE_IBASE ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_sput_wide: /* 0x68 */ -/* File: x86/op_sput_wide.S */ -/* File: x86/op_sput.S */ -/* File: x86/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2681,14 +2405,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop RESTORE_IBASE ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_sput_object: /* 0x69 */ -/* File: x86/op_sput_object.S */ -/* File: x86/op_sput.S */ -/* File: x86/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2706,14 +2425,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop RESTORE_IBASE ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_sput_boolean: /* 0x6a */ -/* File: x86/op_sput_boolean.S */ -/* File: x86/op_sput.S */ -/* File: x86/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2731,14 +2445,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop RESTORE_IBASE ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_sput_byte: /* 0x6b */ -/* File: x86/op_sput_byte.S */ -/* File: x86/op_sput.S */ -/* File: x86/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2756,14 +2465,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop RESTORE_IBASE ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_sput_char: /* 0x6c */ -/* File: x86/op_sput_char.S */ -/* File: x86/op_sput.S */ -/* File: x86/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2781,14 +2485,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop RESTORE_IBASE ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_sput_short: /* 0x6d */ -/* File: x86/op_sput_short.S */ -/* File: x86/op_sput.S */ -/* File: x86/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2806,13 +2505,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop RESTORE_IBASE ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_invoke_virtual: /* 0x6e */ -/* File: x86/op_invoke_virtual.S */ -/* File: x86/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -2837,7 +2532,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop RESTORE_IBASE FETCH_INST GOTO_NEXT - /* * Handle a virtual method call. * @@ -2849,8 +2543,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_invoke_super: /* 0x6f */ -/* File: x86/op_invoke_super.S */ -/* File: x86/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -2875,7 +2567,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop RESTORE_IBASE FETCH_INST GOTO_NEXT - /* * Handle a "super" method call. * @@ -2887,8 +2578,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_invoke_direct: /* 0x70 */ -/* File: x86/op_invoke_direct.S */ -/* File: x86/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -2914,12 +2603,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop FETCH_INST GOTO_NEXT - /* ------------------------------ */ .balign 128 .L_op_invoke_static: /* 0x71 */ -/* File: x86/op_invoke_static.S */ -/* File: x86/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -2945,13 +2631,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop FETCH_INST GOTO_NEXT - - /* ------------------------------ */ .balign 128 .L_op_invoke_interface: /* 0x72 */ -/* File: x86/op_invoke_interface.S */ -/* File: x86/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -2976,7 +2658,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop RESTORE_IBASE FETCH_INST GOTO_NEXT - /* * Handle an interface method call. * @@ -2988,7 +2669,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_return_void_no_barrier: /* 0x73 */ -/* File: x86/op_return_void_no_barrier.S */ movl rSELF, %eax testl $(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(%eax) jz 1f @@ -3002,8 +2682,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_invoke_virtual_range: /* 0x74 */ -/* File: x86/op_invoke_virtual_range.S */ -/* File: x86/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -3029,12 +2707,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop FETCH_INST GOTO_NEXT - /* ------------------------------ */ .balign 128 .L_op_invoke_super_range: /* 0x75 */ -/* File: x86/op_invoke_super_range.S */ -/* File: x86/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -3060,12 +2735,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop FETCH_INST GOTO_NEXT - /* ------------------------------ */ .balign 128 .L_op_invoke_direct_range: /* 0x76 */ -/* File: x86/op_invoke_direct_range.S */ -/* File: x86/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -3091,12 +2763,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop FETCH_INST GOTO_NEXT - /* ------------------------------ */ .balign 128 .L_op_invoke_static_range: /* 0x77 */ -/* File: x86/op_invoke_static_range.S */ -/* File: x86/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -3122,12 +2791,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop FETCH_INST GOTO_NEXT - /* ------------------------------ */ .balign 128 .L_op_invoke_interface_range: /* 0x78 */ -/* File: x86/op_invoke_interface_range.S */ -/* File: x86/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -3153,34 +2819,25 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop FETCH_INST GOTO_NEXT - /* ------------------------------ */ .balign 128 .L_op_unused_79: /* 0x79 */ -/* File: x86/op_unused_79.S */ -/* File: x86/unused.S */ /* * Bail to reference interpreter to throw. */ jmp MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_7a: /* 0x7a */ -/* File: x86/op_unused_7a.S */ -/* File: x86/unused.S */ /* * Bail to reference interpreter to throw. */ jmp MterpFallback - /* ------------------------------ */ .balign 128 .L_op_neg_int: /* 0x7b */ -/* File: x86/op_neg_int.S */ -/* File: x86/unop.S */ /* * Generic 32-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result = op eax". @@ -3194,12 +2851,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %eax, %ecx ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_not_int: /* 0x7c */ -/* File: x86/op_not_int.S */ -/* File: x86/unop.S */ /* * Generic 32-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result = op eax". @@ -3213,11 +2867,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %eax, %ecx ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_neg_long: /* 0x7d */ -/* File: x86/op_neg_long.S */ /* unop vA, vB */ movzbl rINSTbl, %ecx # ecx <- BA sarl $4, %ecx # ecx <- B @@ -3231,11 +2883,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG_HIGH %ecx, rINST # v[A+1] <- ecx ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_not_long: /* 0x7e */ -/* File: x86/op_not_long.S */ /* unop vA, vB */ movzbl rINSTbl, %ecx # ecx <- BA sarl $4, %ecx # ecx <- B @@ -3251,8 +2901,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_neg_float: /* 0x7f */ -/* File: x86/op_neg_float.S */ -/* File: x86/fpcvt.S */ /* * Generic 32-bit FP conversion operation. */ @@ -3270,12 +2918,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_neg_double: /* 0x80 */ -/* File: x86/op_neg_double.S */ -/* File: x86/fpcvt.S */ /* * Generic 32-bit FP conversion operation. */ @@ -3293,11 +2938,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_int_to_long: /* 0x81 */ -/* File: x86/op_int_to_long.S */ /* int to long vA, vB */ movzbl rINSTbl, %eax # eax <- +A sarl $4, %eax # eax <- B @@ -3310,12 +2953,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop movl %ecx, rIBASE ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_int_to_float: /* 0x82 */ -/* File: x86/op_int_to_float.S */ -/* File: x86/fpcvt.S */ /* * Generic 32-bit FP conversion operation. */ @@ -3333,12 +2973,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_int_to_double: /* 0x83 */ -/* File: x86/op_int_to_double.S */ -/* File: x86/fpcvt.S */ /* * Generic 32-bit FP conversion operation. */ @@ -3356,13 +2993,10 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_long_to_int: /* 0x84 */ -/* File: x86/op_long_to_int.S */ /* we ignore the high word, making this equivalent to a 32-bit reg move */ -/* File: x86/op_move.S */ /* for move, move-object, long-to-int */ /* op vA, vB */ movzbl rINSTbl, %eax # eax <- BA @@ -3376,12 +3010,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_long_to_float: /* 0x85 */ -/* File: x86/op_long_to_float.S */ -/* File: x86/fpcvt.S */ /* * Generic 32-bit FP conversion operation. */ @@ -3399,12 +3030,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_long_to_double: /* 0x86 */ -/* File: x86/op_long_to_double.S */ -/* File: x86/fpcvt.S */ /* * Generic 32-bit FP conversion operation. */ @@ -3422,12 +3050,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_float_to_int: /* 0x87 */ -/* File: x86/op_float_to_int.S */ -/* File: x86/cvtfp_int.S */ /* On fp to int conversions, Java requires that * if the result > maxint, it should be clamped to maxint. If it is less * than minint, it should be clamped to minint. If it is a nan, the result @@ -3489,12 +3114,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .endif jmp .Lop_float_to_int_finish - /* ------------------------------ */ .balign 128 .L_op_float_to_long: /* 0x88 */ -/* File: x86/op_float_to_long.S */ -/* File: x86/cvtfp_int.S */ /* On fp to int conversions, Java requires that * if the result > maxint, it should be clamped to maxint. If it is less * than minint, it should be clamped to minint. If it is a nan, the result @@ -3556,12 +3178,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .endif jmp .Lop_float_to_long_finish - /* ------------------------------ */ .balign 128 .L_op_float_to_double: /* 0x89 */ -/* File: x86/op_float_to_double.S */ -/* File: x86/fpcvt.S */ /* * Generic 32-bit FP conversion operation. */ @@ -3579,12 +3198,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_double_to_int: /* 0x8a */ -/* File: x86/op_double_to_int.S */ -/* File: x86/cvtfp_int.S */ /* On fp to int conversions, Java requires that * if the result > maxint, it should be clamped to maxint. If it is less * than minint, it should be clamped to minint. If it is a nan, the result @@ -3646,12 +3262,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .endif jmp .Lop_double_to_int_finish - /* ------------------------------ */ .balign 128 .L_op_double_to_long: /* 0x8b */ -/* File: x86/op_double_to_long.S */ -/* File: x86/cvtfp_int.S */ /* On fp to int conversions, Java requires that * if the result > maxint, it should be clamped to maxint. If it is less * than minint, it should be clamped to minint. If it is a nan, the result @@ -3713,12 +3326,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .endif jmp .Lop_double_to_long_finish - /* ------------------------------ */ .balign 128 .L_op_double_to_float: /* 0x8c */ -/* File: x86/op_double_to_float.S */ -/* File: x86/fpcvt.S */ /* * Generic 32-bit FP conversion operation. */ @@ -3736,12 +3346,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_int_to_byte: /* 0x8d */ -/* File: x86/op_int_to_byte.S */ -/* File: x86/unop.S */ /* * Generic 32-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result = op eax". @@ -3755,12 +3362,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %eax, %ecx ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_int_to_char: /* 0x8e */ -/* File: x86/op_int_to_char.S */ -/* File: x86/unop.S */ /* * Generic 32-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result = op eax". @@ -3774,12 +3378,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %eax, %ecx ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_int_to_short: /* 0x8f */ -/* File: x86/op_int_to_short.S */ -/* File: x86/unop.S */ /* * Generic 32-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result = op eax". @@ -3793,12 +3394,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %eax, %ecx ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_add_int: /* 0x90 */ -/* File: x86/op_add_int.S */ -/* File: x86/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = eax op (rFP,%ecx,4)". @@ -3816,12 +3414,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %eax, rINST ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_sub_int: /* 0x91 */ -/* File: x86/op_sub_int.S */ -/* File: x86/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = eax op (rFP,%ecx,4)". @@ -3839,11 +3434,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %eax, rINST ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_mul_int: /* 0x92 */ -/* File: x86/op_mul_int.S */ /* * 32-bit binary multiplication. */ @@ -3860,8 +3453,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_div_int: /* 0x93 */ -/* File: x86/op_div_int.S */ -/* File: x86/bindiv.S */ /* * 32-bit binary div/rem operation. Handles special case of op0=minint and * op1=-1. @@ -3910,12 +3501,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop mov LOCAL0(%esp), rIBASE ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_rem_int: /* 0x94 */ -/* File: x86/op_rem_int.S */ -/* File: x86/bindiv.S */ /* * 32-bit binary div/rem operation. Handles special case of op0=minint and * op1=-1. @@ -3964,12 +3552,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop mov LOCAL0(%esp), rIBASE ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_and_int: /* 0x95 */ -/* File: x86/op_and_int.S */ -/* File: x86/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = eax op (rFP,%ecx,4)". @@ -3987,12 +3572,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %eax, rINST ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_or_int: /* 0x96 */ -/* File: x86/op_or_int.S */ -/* File: x86/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = eax op (rFP,%ecx,4)". @@ -4010,12 +3592,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %eax, rINST ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_xor_int: /* 0x97 */ -/* File: x86/op_xor_int.S */ -/* File: x86/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = eax op (rFP,%ecx,4)". @@ -4033,12 +3612,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %eax, rINST ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_shl_int: /* 0x98 */ -/* File: x86/op_shl_int.S */ -/* File: x86/binop1.S */ /* * Generic 32-bit binary operation in which both operands loaded to * registers (op0 in eax, op1 in ecx). @@ -4052,12 +3628,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %eax, rINST ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_shr_int: /* 0x99 */ -/* File: x86/op_shr_int.S */ -/* File: x86/binop1.S */ /* * Generic 32-bit binary operation in which both operands loaded to * registers (op0 in eax, op1 in ecx). @@ -4071,12 +3644,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %eax, rINST ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_ushr_int: /* 0x9a */ -/* File: x86/op_ushr_int.S */ -/* File: x86/binop1.S */ /* * Generic 32-bit binary operation in which both operands loaded to * registers (op0 in eax, op1 in ecx). @@ -4090,12 +3660,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %eax, rINST ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_add_long: /* 0x9b */ -/* File: x86/op_add_long.S */ -/* File: x86/binopWide.S */ /* * Generic 64-bit binary operation. */ @@ -4112,12 +3679,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG_HIGH %eax, rINST # v[AA+1] <- eax ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_sub_long: /* 0x9c */ -/* File: x86/op_sub_long.S */ -/* File: x86/binopWide.S */ /* * Generic 64-bit binary operation. */ @@ -4134,11 +3698,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG_HIGH %eax, rINST # v[AA+1] <- eax ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_mul_long: /* 0x9d */ -/* File: x86/op_mul_long.S */ /* * Signed 64-bit integer multiply. * @@ -4176,7 +3738,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_div_long: /* 0x9e */ -/* File: x86/op_div_long.S */ /* art_quick_* methods has quick abi, * so use eax, ecx, edx, ebx for args */ @@ -4203,8 +3764,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_rem_long: /* 0x9f */ -/* File: x86/op_rem_long.S */ -/* File: x86/op_div_long.S */ /* art_quick_* methods has quick abi, * so use eax, ecx, edx, ebx for args */ @@ -4228,12 +3787,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop mov LOCAL0(%esp), rIBASE # restore rIBASE/%edx ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_and_long: /* 0xa0 */ -/* File: x86/op_and_long.S */ -/* File: x86/binopWide.S */ /* * Generic 64-bit binary operation. */ @@ -4250,12 +3806,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG_HIGH %eax, rINST # v[AA+1] <- eax ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_or_long: /* 0xa1 */ -/* File: x86/op_or_long.S */ -/* File: x86/binopWide.S */ /* * Generic 64-bit binary operation. */ @@ -4272,12 +3825,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG_HIGH %eax, rINST # v[AA+1] <- eax ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_xor_long: /* 0xa2 */ -/* File: x86/op_xor_long.S */ -/* File: x86/binopWide.S */ /* * Generic 64-bit binary operation. */ @@ -4294,11 +3844,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG_HIGH %eax, rINST # v[AA+1] <- eax ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_shl_long: /* 0xa3 */ -/* File: x86/op_shl_long.S */ /* * Long integer shift. This is different from the generic 32/64-bit * binary operations because vAA/vBB are 64-bit but vCC (the shift @@ -4332,7 +3880,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_shr_long: /* 0xa4 */ -/* File: x86/op_shr_long.S */ /* * Long integer shift. This is different from the generic 32/64-bit * binary operations because vAA/vBB are 64-bit but vCC (the shift @@ -4366,7 +3913,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_ushr_long: /* 0xa5 */ -/* File: x86/op_ushr_long.S */ /* * Long integer shift. This is different from the generic 32/64-bit * binary operations because vAA/vBB are 64-bit but vCC (the shift @@ -4400,8 +3946,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_add_float: /* 0xa6 */ -/* File: x86/op_add_float.S */ -/* File: x86/sseBinop.S */ movzbl 2(rPC), %ecx # ecx <- BB movzbl 3(rPC), %eax # eax <- CC movss VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src @@ -4411,12 +3955,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop movss %xmm0, VREG_REF_ADDRESS(rINST) # clear ref ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_sub_float: /* 0xa7 */ -/* File: x86/op_sub_float.S */ -/* File: x86/sseBinop.S */ movzbl 2(rPC), %ecx # ecx <- BB movzbl 3(rPC), %eax # eax <- CC movss VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src @@ -4426,12 +3967,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop movss %xmm0, VREG_REF_ADDRESS(rINST) # clear ref ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_mul_float: /* 0xa8 */ -/* File: x86/op_mul_float.S */ -/* File: x86/sseBinop.S */ movzbl 2(rPC), %ecx # ecx <- BB movzbl 3(rPC), %eax # eax <- CC movss VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src @@ -4441,12 +3979,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop movss %xmm0, VREG_REF_ADDRESS(rINST) # clear ref ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_div_float: /* 0xa9 */ -/* File: x86/op_div_float.S */ -/* File: x86/sseBinop.S */ movzbl 2(rPC), %ecx # ecx <- BB movzbl 3(rPC), %eax # eax <- CC movss VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src @@ -4456,11 +3991,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop movss %xmm0, VREG_REF_ADDRESS(rINST) # clear ref ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_rem_float: /* 0xaa */ -/* File: x86/op_rem_float.S */ /* rem_float vAA, vBB, vCC */ movzbl 3(rPC), %ecx # ecx <- BB movzbl 2(rPC), %eax # eax <- CC @@ -4479,8 +4012,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_add_double: /* 0xab */ -/* File: x86/op_add_double.S */ -/* File: x86/sseBinop.S */ movzbl 2(rPC), %ecx # ecx <- BB movzbl 3(rPC), %eax # eax <- CC movsd VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src @@ -4490,12 +4021,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop movsd %xmm0, VREG_REF_ADDRESS(rINST) # clear ref ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_sub_double: /* 0xac */ -/* File: x86/op_sub_double.S */ -/* File: x86/sseBinop.S */ movzbl 2(rPC), %ecx # ecx <- BB movzbl 3(rPC), %eax # eax <- CC movsd VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src @@ -4505,12 +4033,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop movsd %xmm0, VREG_REF_ADDRESS(rINST) # clear ref ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_mul_double: /* 0xad */ -/* File: x86/op_mul_double.S */ -/* File: x86/sseBinop.S */ movzbl 2(rPC), %ecx # ecx <- BB movzbl 3(rPC), %eax # eax <- CC movsd VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src @@ -4520,12 +4045,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop movsd %xmm0, VREG_REF_ADDRESS(rINST) # clear ref ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_div_double: /* 0xae */ -/* File: x86/op_div_double.S */ -/* File: x86/sseBinop.S */ movzbl 2(rPC), %ecx # ecx <- BB movzbl 3(rPC), %eax # eax <- CC movsd VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src @@ -4535,11 +4057,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop movsd %xmm0, VREG_REF_ADDRESS(rINST) # clear ref ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_rem_double: /* 0xaf */ -/* File: x86/op_rem_double.S */ /* rem_double vAA, vBB, vCC */ movzbl 3(rPC), %ecx # ecx <- BB movzbl 2(rPC), %eax # eax <- CC @@ -4558,8 +4078,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_add_int_2addr: /* 0xb0 */ -/* File: x86/op_add_int_2addr.S */ -/* File: x86/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0 op r1". @@ -4579,12 +4097,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop CLEAR_REF %ecx ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_sub_int_2addr: /* 0xb1 */ -/* File: x86/op_sub_int_2addr.S */ -/* File: x86/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0 op r1". @@ -4604,11 +4119,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop CLEAR_REF %ecx ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_mul_int_2addr: /* 0xb2 */ -/* File: x86/op_mul_int_2addr.S */ /* mul vA, vB */ movzx rINSTbl, %ecx # ecx <- A+ sarl $4, rINST # rINST <- B @@ -4623,8 +4136,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_div_int_2addr: /* 0xb3 */ -/* File: x86/op_div_int_2addr.S */ -/* File: x86/bindiv2addr.S */ /* * 32-bit binary div/rem operation. Handles special case of op0=minint and * op1=-1. @@ -4654,12 +4165,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop mov LOCAL0(%esp), rIBASE ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_rem_int_2addr: /* 0xb4 */ -/* File: x86/op_rem_int_2addr.S */ -/* File: x86/bindiv2addr.S */ /* * 32-bit binary div/rem operation. Handles special case of op0=minint and * op1=-1. @@ -4689,12 +4197,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop mov LOCAL0(%esp), rIBASE ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_and_int_2addr: /* 0xb5 */ -/* File: x86/op_and_int_2addr.S */ -/* File: x86/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0 op r1". @@ -4714,12 +4219,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop CLEAR_REF %ecx ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_or_int_2addr: /* 0xb6 */ -/* File: x86/op_or_int_2addr.S */ -/* File: x86/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0 op r1". @@ -4739,12 +4241,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop CLEAR_REF %ecx ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_xor_int_2addr: /* 0xb7 */ -/* File: x86/op_xor_int_2addr.S */ -/* File: x86/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0 op r1". @@ -4764,12 +4263,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop CLEAR_REF %ecx ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_shl_int_2addr: /* 0xb8 */ -/* File: x86/op_shl_int_2addr.S */ -/* File: x86/shop2addr.S */ /* * Generic 32-bit "shift/2addr" operation. */ @@ -4783,12 +4279,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %eax, rINST ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_shr_int_2addr: /* 0xb9 */ -/* File: x86/op_shr_int_2addr.S */ -/* File: x86/shop2addr.S */ /* * Generic 32-bit "shift/2addr" operation. */ @@ -4802,12 +4295,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %eax, rINST ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_ushr_int_2addr: /* 0xba */ -/* File: x86/op_ushr_int_2addr.S */ -/* File: x86/shop2addr.S */ /* * Generic 32-bit "shift/2addr" operation. */ @@ -4821,12 +4311,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %eax, rINST ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_add_long_2addr: /* 0xbb */ -/* File: x86/op_add_long_2addr.S */ -/* File: x86/binopWide2addr.S */ /* * Generic 64-bit binary operation. */ @@ -4841,12 +4328,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop CLEAR_WIDE_REF rINST ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_sub_long_2addr: /* 0xbc */ -/* File: x86/op_sub_long_2addr.S */ -/* File: x86/binopWide2addr.S */ /* * Generic 64-bit binary operation. */ @@ -4861,11 +4345,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop CLEAR_WIDE_REF rINST ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_mul_long_2addr: /* 0xbd */ -/* File: x86/op_mul_long_2addr.S */ /* * Signed 64-bit integer multiply, 2-addr version * @@ -4905,7 +4387,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_div_long_2addr: /* 0xbe */ -/* File: x86/op_div_long_2addr.S */ /* art_quick_* methods has quick abi, * so use eax, ecx, edx, ebx for args */ @@ -4934,8 +4415,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_rem_long_2addr: /* 0xbf */ -/* File: x86/op_rem_long_2addr.S */ -/* File: x86/op_div_long_2addr.S */ /* art_quick_* methods has quick abi, * so use eax, ecx, edx, ebx for args */ @@ -4961,12 +4440,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop mov LOCAL0(%esp), rIBASE # restore rIBASE/%edx ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_and_long_2addr: /* 0xc0 */ -/* File: x86/op_and_long_2addr.S */ -/* File: x86/binopWide2addr.S */ /* * Generic 64-bit binary operation. */ @@ -4981,12 +4457,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop CLEAR_WIDE_REF rINST ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_or_long_2addr: /* 0xc1 */ -/* File: x86/op_or_long_2addr.S */ -/* File: x86/binopWide2addr.S */ /* * Generic 64-bit binary operation. */ @@ -5001,12 +4474,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop CLEAR_WIDE_REF rINST ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_xor_long_2addr: /* 0xc2 */ -/* File: x86/op_xor_long_2addr.S */ -/* File: x86/binopWide2addr.S */ /* * Generic 64-bit binary operation. */ @@ -5021,11 +4491,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop CLEAR_WIDE_REF rINST ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_shl_long_2addr: /* 0xc3 */ -/* File: x86/op_shl_long_2addr.S */ /* * Long integer shift, 2addr version. vA is 64-bit value/result, vB is * 32-bit shift distance. @@ -5056,7 +4524,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_shr_long_2addr: /* 0xc4 */ -/* File: x86/op_shr_long_2addr.S */ /* * Long integer shift, 2addr version. vA is 64-bit value/result, vB is * 32-bit shift distance. @@ -5087,7 +4554,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_ushr_long_2addr: /* 0xc5 */ -/* File: x86/op_ushr_long_2addr.S */ /* * Long integer shift, 2addr version. vA is 64-bit value/result, vB is * 32-bit shift distance. @@ -5118,8 +4584,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_add_float_2addr: /* 0xc6 */ -/* File: x86/op_add_float_2addr.S */ -/* File: x86/sseBinop2Addr.S */ movzx rINSTbl, %ecx # ecx <- A+ andl $0xf, %ecx # ecx <- A movss VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src @@ -5130,12 +4594,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop movss %xmm0, VREG_REF_ADDRESS(rINST) # clear ref ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_sub_float_2addr: /* 0xc7 */ -/* File: x86/op_sub_float_2addr.S */ -/* File: x86/sseBinop2Addr.S */ movzx rINSTbl, %ecx # ecx <- A+ andl $0xf, %ecx # ecx <- A movss VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src @@ -5146,12 +4607,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop movss %xmm0, VREG_REF_ADDRESS(rINST) # clear ref ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_mul_float_2addr: /* 0xc8 */ -/* File: x86/op_mul_float_2addr.S */ -/* File: x86/sseBinop2Addr.S */ movzx rINSTbl, %ecx # ecx <- A+ andl $0xf, %ecx # ecx <- A movss VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src @@ -5162,12 +4620,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop movss %xmm0, VREG_REF_ADDRESS(rINST) # clear ref ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_div_float_2addr: /* 0xc9 */ -/* File: x86/op_div_float_2addr.S */ -/* File: x86/sseBinop2Addr.S */ movzx rINSTbl, %ecx # ecx <- A+ andl $0xf, %ecx # ecx <- A movss VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src @@ -5178,11 +4633,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop movss %xmm0, VREG_REF_ADDRESS(rINST) # clear ref ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_rem_float_2addr: /* 0xca */ -/* File: x86/op_rem_float_2addr.S */ /* rem_float/2addr vA, vB */ movzx rINSTbl, %ecx # ecx <- A+ sarl $4, rINST # rINST <- B @@ -5202,8 +4655,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_add_double_2addr: /* 0xcb */ -/* File: x86/op_add_double_2addr.S */ -/* File: x86/sseBinop2Addr.S */ movzx rINSTbl, %ecx # ecx <- A+ andl $0xf, %ecx # ecx <- A movsd VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src @@ -5214,12 +4665,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop movsd %xmm0, VREG_REF_ADDRESS(rINST) # clear ref ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_sub_double_2addr: /* 0xcc */ -/* File: x86/op_sub_double_2addr.S */ -/* File: x86/sseBinop2Addr.S */ movzx rINSTbl, %ecx # ecx <- A+ andl $0xf, %ecx # ecx <- A movsd VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src @@ -5230,12 +4678,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop movsd %xmm0, VREG_REF_ADDRESS(rINST) # clear ref ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_mul_double_2addr: /* 0xcd */ -/* File: x86/op_mul_double_2addr.S */ -/* File: x86/sseBinop2Addr.S */ movzx rINSTbl, %ecx # ecx <- A+ andl $0xf, %ecx # ecx <- A movsd VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src @@ -5246,12 +4691,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop movsd %xmm0, VREG_REF_ADDRESS(rINST) # clear ref ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_div_double_2addr: /* 0xce */ -/* File: x86/op_div_double_2addr.S */ -/* File: x86/sseBinop2Addr.S */ movzx rINSTbl, %ecx # ecx <- A+ andl $0xf, %ecx # ecx <- A movsd VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src @@ -5262,11 +4704,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop movsd %xmm0, VREG_REF_ADDRESS(rINST) # clear ref ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_rem_double_2addr: /* 0xcf */ -/* File: x86/op_rem_double_2addr.S */ /* rem_double/2addr vA, vB */ movzx rINSTbl, %ecx # ecx <- A+ sarl $4, rINST # rINST <- B @@ -5286,8 +4726,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_add_int_lit16: /* 0xd0 */ -/* File: x86/op_add_int_lit16.S */ -/* File: x86/binopLit16.S */ /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = eax op ecx". @@ -5307,13 +4745,10 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %eax, rINST ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_rsub_int: /* 0xd1 */ -/* File: x86/op_rsub_int.S */ /* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ -/* File: x86/binopLit16.S */ /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = eax op ecx". @@ -5333,11 +4768,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %ecx, rINST ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_mul_int_lit16: /* 0xd2 */ -/* File: x86/op_mul_int_lit16.S */ /* mul/lit16 vA, vB, #+CCCC */ /* Need A in rINST, ssssCCCC in ecx, vB in eax */ movzbl rINSTbl, %eax # eax <- 000000BA @@ -5354,8 +4787,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_div_int_lit16: /* 0xd3 */ -/* File: x86/op_div_int_lit16.S */ -/* File: x86/bindivLit16.S */ /* * 32-bit binary div/rem operation. Handles special case of op0=minint and * op1=-1. @@ -5385,12 +4816,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop mov LOCAL0(%esp), rIBASE ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_rem_int_lit16: /* 0xd4 */ -/* File: x86/op_rem_int_lit16.S */ -/* File: x86/bindivLit16.S */ /* * 32-bit binary div/rem operation. Handles special case of op0=minint and * op1=-1. @@ -5420,12 +4848,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop mov LOCAL0(%esp), rIBASE ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_and_int_lit16: /* 0xd5 */ -/* File: x86/op_and_int_lit16.S */ -/* File: x86/binopLit16.S */ /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = eax op ecx". @@ -5445,12 +4870,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %eax, rINST ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_or_int_lit16: /* 0xd6 */ -/* File: x86/op_or_int_lit16.S */ -/* File: x86/binopLit16.S */ /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = eax op ecx". @@ -5470,12 +4892,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %eax, rINST ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_xor_int_lit16: /* 0xd7 */ -/* File: x86/op_xor_int_lit16.S */ -/* File: x86/binopLit16.S */ /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = eax op ecx". @@ -5495,12 +4914,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %eax, rINST ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_add_int_lit8: /* 0xd8 */ -/* File: x86/op_add_int_lit8.S */ -/* File: x86/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = eax op ecx". @@ -5519,12 +4935,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %eax, rINST ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_rsub_int_lit8: /* 0xd9 */ -/* File: x86/op_rsub_int_lit8.S */ -/* File: x86/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = eax op ecx". @@ -5543,11 +4956,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %ecx, rINST ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_mul_int_lit8: /* 0xda */ -/* File: x86/op_mul_int_lit8.S */ /* mul/lit8 vAA, vBB, #+CC */ movzbl 2(rPC), %eax # eax <- BB movl rIBASE, %ecx @@ -5561,8 +4972,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_div_int_lit8: /* 0xdb */ -/* File: x86/op_div_int_lit8.S */ -/* File: x86/bindivLit8.S */ /* * 32-bit div/rem "lit8" binary operation. Handles special case of * op0=minint & op1=-1 @@ -5589,12 +4998,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop mov LOCAL0(%esp), rIBASE ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_rem_int_lit8: /* 0xdc */ -/* File: x86/op_rem_int_lit8.S */ -/* File: x86/bindivLit8.S */ /* * 32-bit div/rem "lit8" binary operation. Handles special case of * op0=minint & op1=-1 @@ -5621,12 +5027,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop mov LOCAL0(%esp), rIBASE ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_and_int_lit8: /* 0xdd */ -/* File: x86/op_and_int_lit8.S */ -/* File: x86/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = eax op ecx". @@ -5645,12 +5048,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %eax, rINST ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_or_int_lit8: /* 0xde */ -/* File: x86/op_or_int_lit8.S */ -/* File: x86/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = eax op ecx". @@ -5669,12 +5069,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %eax, rINST ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_xor_int_lit8: /* 0xdf */ -/* File: x86/op_xor_int_lit8.S */ -/* File: x86/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = eax op ecx". @@ -5693,12 +5090,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %eax, rINST ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_shl_int_lit8: /* 0xe0 */ -/* File: x86/op_shl_int_lit8.S */ -/* File: x86/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = eax op ecx". @@ -5717,12 +5111,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %eax, rINST ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_shr_int_lit8: /* 0xe1 */ -/* File: x86/op_shr_int_lit8.S */ -/* File: x86/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = eax op ecx". @@ -5741,12 +5132,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %eax, rINST ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_ushr_int_lit8: /* 0xe2 */ -/* File: x86/op_ushr_int_lit8.S */ -/* File: x86/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = eax op ecx". @@ -5765,11 +5153,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %eax, rINST ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_iget_quick: /* 0xe3 */ -/* File: x86/op_iget_quick.S */ /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ /* op vA, vB, offset@CCCC */ movzbl rINSTbl, %ecx # ecx <- BA @@ -5786,7 +5172,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_iget_wide_quick: /* 0xe4 */ -/* File: x86/op_iget_wide_quick.S */ /* iget-wide-quick vA, vB, offset@CCCC */ movzbl rINSTbl, %ecx # ecx <- BA sarl $4, %ecx # ecx <- B @@ -5802,7 +5187,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_iget_object_quick: /* 0xe5 */ -/* File: x86/op_iget_object_quick.S */ /* For: iget-object-quick */ /* op vA, vB, offset@CCCC */ movzbl rINSTbl, %ecx # ecx <- BA @@ -5824,7 +5208,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_iput_quick: /* 0xe6 */ -/* File: x86/op_iput_quick.S */ /* For: iput-quick, iput-object-quick */ /* op vA, vB, offset@CCCC */ movzbl rINSTbl, %ecx # ecx <- BA @@ -5841,7 +5224,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_iput_wide_quick: /* 0xe7 */ -/* File: x86/op_iput_wide_quick.S */ /* iput-wide-quick vA, vB, offset@CCCC */ movzbl rINSTbl, %ecx # ecx<- BA sarl $4, %ecx # ecx<- B @@ -5858,7 +5240,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_iput_object_quick: /* 0xe8 */ -/* File: x86/op_iput_object_quick.S */ EXPORT_PC leal OFF_FP_SHADOWFRAME(rFP), %eax movl %eax, OUT_ARG0(%esp) @@ -5874,8 +5255,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_invoke_virtual_quick: /* 0xe9 */ -/* File: x86/op_invoke_virtual_quick.S */ -/* File: x86/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -5901,12 +5280,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop FETCH_INST GOTO_NEXT - /* ------------------------------ */ .balign 128 .L_op_invoke_virtual_range_quick: /* 0xea */ -/* File: x86/op_invoke_virtual_range_quick.S */ -/* File: x86/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -5932,12 +5308,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop FETCH_INST GOTO_NEXT - /* ------------------------------ */ .balign 128 .L_op_iput_boolean_quick: /* 0xeb */ -/* File: x86/op_iput_boolean_quick.S */ -/* File: x86/op_iput_quick.S */ /* For: iput-quick, iput-object-quick */ /* op vA, vB, offset@CCCC */ movzbl rINSTbl, %ecx # ecx <- BA @@ -5951,12 +5324,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop movb rINSTbl, (%ecx,%eax,1) ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_iput_byte_quick: /* 0xec */ -/* File: x86/op_iput_byte_quick.S */ -/* File: x86/op_iput_quick.S */ /* For: iput-quick, iput-object-quick */ /* op vA, vB, offset@CCCC */ movzbl rINSTbl, %ecx # ecx <- BA @@ -5970,12 +5340,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop movb rINSTbl, (%ecx,%eax,1) ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_iput_char_quick: /* 0xed */ -/* File: x86/op_iput_char_quick.S */ -/* File: x86/op_iput_quick.S */ /* For: iput-quick, iput-object-quick */ /* op vA, vB, offset@CCCC */ movzbl rINSTbl, %ecx # ecx <- BA @@ -5989,12 +5356,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop movw rINSTw, (%ecx,%eax,1) ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_iput_short_quick: /* 0xee */ -/* File: x86/op_iput_short_quick.S */ -/* File: x86/op_iput_quick.S */ /* For: iput-quick, iput-object-quick */ /* op vA, vB, offset@CCCC */ movzbl rINSTbl, %ecx # ecx <- BA @@ -6008,12 +5372,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop movw rINSTw, (%ecx,%eax,1) ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_iget_boolean_quick: /* 0xef */ -/* File: x86/op_iget_boolean_quick.S */ -/* File: x86/op_iget_quick.S */ /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ /* op vA, vB, offset@CCCC */ movzbl rINSTbl, %ecx # ecx <- BA @@ -6027,12 +5388,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %eax, rINST # fp[A] <- value ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_iget_byte_quick: /* 0xf0 */ -/* File: x86/op_iget_byte_quick.S */ -/* File: x86/op_iget_quick.S */ /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ /* op vA, vB, offset@CCCC */ movzbl rINSTbl, %ecx # ecx <- BA @@ -6046,12 +5404,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %eax, rINST # fp[A] <- value ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_iget_char_quick: /* 0xf1 */ -/* File: x86/op_iget_char_quick.S */ -/* File: x86/op_iget_quick.S */ /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ /* op vA, vB, offset@CCCC */ movzbl rINSTbl, %ecx # ecx <- BA @@ -6065,12 +5420,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %eax, rINST # fp[A] <- value ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_iget_short_quick: /* 0xf2 */ -/* File: x86/op_iget_short_quick.S */ -/* File: x86/op_iget_quick.S */ /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ /* op vA, vB, offset@CCCC */ movzbl rINSTbl, %ecx # ecx <- BA @@ -6084,89 +5436,65 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %eax, rINST # fp[A] <- value ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_unused_f3: /* 0xf3 */ -/* File: x86/op_unused_f3.S */ -/* File: x86/unused.S */ /* * Bail to reference interpreter to throw. */ jmp MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_f4: /* 0xf4 */ -/* File: x86/op_unused_f4.S */ -/* File: x86/unused.S */ /* * Bail to reference interpreter to throw. */ jmp MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_f5: /* 0xf5 */ -/* File: x86/op_unused_f5.S */ -/* File: x86/unused.S */ /* * Bail to reference interpreter to throw. */ jmp MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_f6: /* 0xf6 */ -/* File: x86/op_unused_f6.S */ -/* File: x86/unused.S */ /* * Bail to reference interpreter to throw. */ jmp MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_f7: /* 0xf7 */ -/* File: x86/op_unused_f7.S */ -/* File: x86/unused.S */ /* * Bail to reference interpreter to throw. */ jmp MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_f8: /* 0xf8 */ -/* File: x86/op_unused_f8.S */ -/* File: x86/unused.S */ /* * Bail to reference interpreter to throw. */ jmp MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_f9: /* 0xf9 */ -/* File: x86/op_unused_f9.S */ -/* File: x86/unused.S */ /* * Bail to reference interpreter to throw. */ jmp MterpFallback - /* ------------------------------ */ .balign 128 .L_op_invoke_polymorphic: /* 0xfa */ -/* File: x86/op_invoke_polymorphic.S */ -/* File: x86/invoke_polymorphic.S */ /* * invoke-polymorphic handler wrapper. */ @@ -6192,12 +5520,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop FETCH_INST GOTO_NEXT - /* ------------------------------ */ .balign 128 .L_op_invoke_polymorphic_range: /* 0xfb */ -/* File: x86/op_invoke_polymorphic_range.S */ -/* File: x86/invoke_polymorphic.S */ /* * invoke-polymorphic handler wrapper. */ @@ -6223,12 +5548,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop FETCH_INST GOTO_NEXT - /* ------------------------------ */ .balign 128 .L_op_invoke_custom: /* 0xfc */ -/* File: x86/op_invoke_custom.S */ -/* File: x86/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -6254,12 +5576,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop FETCH_INST GOTO_NEXT - /* ------------------------------ */ .balign 128 .L_op_invoke_custom_range: /* 0xfd */ -/* File: x86/op_invoke_custom_range.S */ -/* File: x86/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -6285,12 +5604,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop FETCH_INST GOTO_NEXT - /* ------------------------------ */ .balign 128 .L_op_const_method_handle: /* 0xfe */ -/* File: x86/op_const_method_handle.S */ -/* File: x86/const.S */ /* const/class vAA, type@BBBB */ /* const/method-handle vAA, method_handle@BBBB */ /* const/method-type vAA, proto@BBBB */ @@ -6310,12 +5626,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop jnz MterpPossibleException ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_const_method_type: /* 0xff */ -/* File: x86/op_const_method_type.S */ -/* File: x86/const.S */ /* const/class vAA, type@BBBB */ /* const/method-handle vAA, method_handle@BBBB */ /* const/method-type vAA, proto@BBBB */ @@ -6335,23 +5648,13 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop jnz MterpPossibleException ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - .balign 128 -/* File: x86/instruction_end.S */ OBJECT_TYPE(artMterpAsmInstructionEnd) ASM_HIDDEN SYMBOL(artMterpAsmInstructionEnd) .global SYMBOL(artMterpAsmInstructionEnd) SYMBOL(artMterpAsmInstructionEnd): - -/* - * =========================================================================== - * Sister implementations - * =========================================================================== - */ -/* File: x86/instruction_start_sister.S */ - OBJECT_TYPE(artMterpAsmSisterStart) ASM_HIDDEN SYMBOL(artMterpAsmSisterStart) .global SYMBOL(artMterpAsmSisterStart) @@ -6359,25 +5662,19 @@ SYMBOL(artMterpAsmInstructionEnd): .balign 4 SYMBOL(artMterpAsmSisterStart): -/* File: x86/instruction_end_sister.S */ - OBJECT_TYPE(artMterpAsmSisterEnd) ASM_HIDDEN SYMBOL(artMterpAsmSisterEnd) .global SYMBOL(artMterpAsmSisterEnd) SYMBOL(artMterpAsmSisterEnd): -/* File: x86/instruction_start_alt.S */ - OBJECT_TYPE(artMterpAsmAltInstructionStart) ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionStart) .global SYMBOL(artMterpAsmAltInstructionStart) .text SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop - /* ------------------------------ */ .balign 128 .L_ALT_op_nop: /* 0x00 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6401,7 +5698,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move: /* 0x01 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6425,7 +5721,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_from16: /* 0x02 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6449,7 +5744,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_16: /* 0x03 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6473,7 +5767,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_wide: /* 0x04 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6497,7 +5790,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_wide_from16: /* 0x05 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6521,7 +5813,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_wide_16: /* 0x06 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6545,7 +5836,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_object: /* 0x07 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6569,7 +5859,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_object_from16: /* 0x08 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6593,7 +5882,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_object_16: /* 0x09 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6617,7 +5905,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_result: /* 0x0a */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6641,7 +5928,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_result_wide: /* 0x0b */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6665,7 +5951,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_result_object: /* 0x0c */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6689,7 +5974,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_exception: /* 0x0d */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6713,7 +5997,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_return_void: /* 0x0e */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6737,7 +6020,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_return: /* 0x0f */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6761,7 +6043,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_return_wide: /* 0x10 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6785,7 +6066,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_return_object: /* 0x11 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6809,7 +6089,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_4: /* 0x12 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6833,7 +6112,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_16: /* 0x13 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6857,7 +6135,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const: /* 0x14 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6881,7 +6158,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_high16: /* 0x15 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6905,7 +6181,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_wide_16: /* 0x16 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6929,7 +6204,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_wide_32: /* 0x17 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6953,7 +6227,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_wide: /* 0x18 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6977,7 +6250,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_wide_high16: /* 0x19 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7001,7 +6273,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_string: /* 0x1a */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7025,7 +6296,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_string_jumbo: /* 0x1b */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7049,7 +6319,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_class: /* 0x1c */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7073,7 +6342,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_monitor_enter: /* 0x1d */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7097,7 +6365,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_monitor_exit: /* 0x1e */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7121,7 +6388,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_check_cast: /* 0x1f */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7145,7 +6411,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_instance_of: /* 0x20 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7169,7 +6434,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_array_length: /* 0x21 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7193,7 +6457,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_new_instance: /* 0x22 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7217,7 +6480,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_new_array: /* 0x23 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7241,7 +6503,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_filled_new_array: /* 0x24 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7265,7 +6526,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_filled_new_array_range: /* 0x25 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7289,7 +6549,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_fill_array_data: /* 0x26 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7313,7 +6572,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_throw: /* 0x27 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7337,7 +6595,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_goto: /* 0x28 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7361,7 +6618,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_goto_16: /* 0x29 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7385,7 +6641,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_goto_32: /* 0x2a */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7409,7 +6664,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_packed_switch: /* 0x2b */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7433,7 +6687,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sparse_switch: /* 0x2c */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7457,7 +6710,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_cmpl_float: /* 0x2d */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7481,7 +6733,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_cmpg_float: /* 0x2e */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7505,7 +6756,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_cmpl_double: /* 0x2f */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7529,7 +6779,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_cmpg_double: /* 0x30 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7553,7 +6802,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_cmp_long: /* 0x31 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7577,7 +6825,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_eq: /* 0x32 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7601,7 +6848,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_ne: /* 0x33 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7625,7 +6871,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_lt: /* 0x34 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7649,7 +6894,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_ge: /* 0x35 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7673,7 +6917,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_gt: /* 0x36 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7697,7 +6940,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_le: /* 0x37 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7721,7 +6963,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_eqz: /* 0x38 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7745,7 +6986,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_nez: /* 0x39 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7769,7 +7009,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_ltz: /* 0x3a */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7793,7 +7032,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_gez: /* 0x3b */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7817,7 +7055,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_gtz: /* 0x3c */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7841,7 +7078,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_lez: /* 0x3d */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7865,7 +7101,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_3e: /* 0x3e */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7889,7 +7124,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_3f: /* 0x3f */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7913,7 +7147,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_40: /* 0x40 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7937,7 +7170,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_41: /* 0x41 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7961,7 +7193,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_42: /* 0x42 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7985,7 +7216,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_43: /* 0x43 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8009,7 +7239,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aget: /* 0x44 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8033,7 +7262,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aget_wide: /* 0x45 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8057,7 +7285,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aget_object: /* 0x46 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8081,7 +7308,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aget_boolean: /* 0x47 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8105,7 +7331,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aget_byte: /* 0x48 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8129,7 +7354,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aget_char: /* 0x49 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8153,7 +7377,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aget_short: /* 0x4a */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8177,7 +7400,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aput: /* 0x4b */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8201,7 +7423,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aput_wide: /* 0x4c */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8225,7 +7446,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aput_object: /* 0x4d */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8249,7 +7469,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aput_boolean: /* 0x4e */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8273,7 +7492,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aput_byte: /* 0x4f */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8297,7 +7515,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aput_char: /* 0x50 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8321,7 +7538,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aput_short: /* 0x51 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8345,7 +7561,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget: /* 0x52 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8369,7 +7584,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_wide: /* 0x53 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8393,7 +7607,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_object: /* 0x54 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8417,7 +7630,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_boolean: /* 0x55 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8441,7 +7653,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_byte: /* 0x56 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8465,7 +7676,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_char: /* 0x57 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8489,7 +7699,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_short: /* 0x58 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8513,7 +7722,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput: /* 0x59 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8537,7 +7745,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_wide: /* 0x5a */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8561,7 +7768,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_object: /* 0x5b */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8585,7 +7791,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_boolean: /* 0x5c */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8609,7 +7814,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_byte: /* 0x5d */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8633,7 +7837,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_char: /* 0x5e */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8657,7 +7860,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_short: /* 0x5f */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8681,7 +7883,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sget: /* 0x60 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8705,7 +7906,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sget_wide: /* 0x61 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8729,7 +7929,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sget_object: /* 0x62 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8753,7 +7952,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sget_boolean: /* 0x63 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8777,7 +7975,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sget_byte: /* 0x64 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8801,7 +7998,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sget_char: /* 0x65 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8825,7 +8021,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sget_short: /* 0x66 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8849,7 +8044,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sput: /* 0x67 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8873,7 +8067,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sput_wide: /* 0x68 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8897,7 +8090,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sput_object: /* 0x69 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8921,7 +8113,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sput_boolean: /* 0x6a */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8945,7 +8136,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sput_byte: /* 0x6b */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8969,7 +8159,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sput_char: /* 0x6c */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8993,7 +8182,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sput_short: /* 0x6d */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9017,7 +8205,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_virtual: /* 0x6e */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9041,7 +8228,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_super: /* 0x6f */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9065,7 +8251,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_direct: /* 0x70 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9089,7 +8274,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_static: /* 0x71 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9113,7 +8297,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_interface: /* 0x72 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9137,7 +8320,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_return_void_no_barrier: /* 0x73 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9161,7 +8343,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_virtual_range: /* 0x74 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9185,7 +8366,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_super_range: /* 0x75 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9209,7 +8389,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_direct_range: /* 0x76 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9233,7 +8412,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_static_range: /* 0x77 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9257,7 +8435,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_interface_range: /* 0x78 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9281,7 +8458,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_79: /* 0x79 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9305,7 +8481,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_7a: /* 0x7a */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9329,7 +8504,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_neg_int: /* 0x7b */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9353,7 +8527,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_not_int: /* 0x7c */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9377,7 +8550,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_neg_long: /* 0x7d */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9401,7 +8573,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_not_long: /* 0x7e */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9425,7 +8596,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_neg_float: /* 0x7f */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9449,7 +8619,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_neg_double: /* 0x80 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9473,7 +8642,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_int_to_long: /* 0x81 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9497,7 +8665,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_int_to_float: /* 0x82 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9521,7 +8688,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_int_to_double: /* 0x83 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9545,7 +8711,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_long_to_int: /* 0x84 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9569,7 +8734,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_long_to_float: /* 0x85 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9593,7 +8757,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_long_to_double: /* 0x86 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9617,7 +8780,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_float_to_int: /* 0x87 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9641,7 +8803,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_float_to_long: /* 0x88 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9665,7 +8826,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_float_to_double: /* 0x89 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9689,7 +8849,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_double_to_int: /* 0x8a */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9713,7 +8872,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_double_to_long: /* 0x8b */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9737,7 +8895,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_double_to_float: /* 0x8c */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9761,7 +8918,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_int_to_byte: /* 0x8d */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9785,7 +8941,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_int_to_char: /* 0x8e */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9809,7 +8964,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_int_to_short: /* 0x8f */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9833,7 +8987,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_int: /* 0x90 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9857,7 +9010,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_int: /* 0x91 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9881,7 +9033,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_int: /* 0x92 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9905,7 +9056,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_int: /* 0x93 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9929,7 +9079,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_int: /* 0x94 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9953,7 +9102,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_and_int: /* 0x95 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9977,7 +9125,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_or_int: /* 0x96 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10001,7 +9148,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_xor_int: /* 0x97 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10025,7 +9171,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shl_int: /* 0x98 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10049,7 +9194,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shr_int: /* 0x99 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10073,7 +9217,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_ushr_int: /* 0x9a */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10097,7 +9240,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_long: /* 0x9b */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10121,7 +9263,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_long: /* 0x9c */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10145,7 +9286,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_long: /* 0x9d */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10169,7 +9309,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_long: /* 0x9e */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10193,7 +9332,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_long: /* 0x9f */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10217,7 +9355,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_and_long: /* 0xa0 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10241,7 +9378,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_or_long: /* 0xa1 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10265,7 +9401,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_xor_long: /* 0xa2 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10289,7 +9424,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shl_long: /* 0xa3 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10313,7 +9447,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shr_long: /* 0xa4 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10337,7 +9470,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_ushr_long: /* 0xa5 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10361,7 +9493,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_float: /* 0xa6 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10385,7 +9516,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_float: /* 0xa7 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10409,7 +9539,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_float: /* 0xa8 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10433,7 +9562,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_float: /* 0xa9 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10457,7 +9585,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_float: /* 0xaa */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10481,7 +9608,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_double: /* 0xab */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10505,7 +9631,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_double: /* 0xac */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10529,7 +9654,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_double: /* 0xad */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10553,7 +9677,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_double: /* 0xae */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10577,7 +9700,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_double: /* 0xaf */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10601,7 +9723,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_int_2addr: /* 0xb0 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10625,7 +9746,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_int_2addr: /* 0xb1 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10649,7 +9769,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_int_2addr: /* 0xb2 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10673,7 +9792,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_int_2addr: /* 0xb3 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10697,7 +9815,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_int_2addr: /* 0xb4 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10721,7 +9838,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_and_int_2addr: /* 0xb5 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10745,7 +9861,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_or_int_2addr: /* 0xb6 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10769,7 +9884,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_xor_int_2addr: /* 0xb7 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10793,7 +9907,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shl_int_2addr: /* 0xb8 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10817,7 +9930,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shr_int_2addr: /* 0xb9 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10841,7 +9953,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_ushr_int_2addr: /* 0xba */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10865,7 +9976,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_long_2addr: /* 0xbb */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10889,7 +9999,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_long_2addr: /* 0xbc */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10913,7 +10022,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_long_2addr: /* 0xbd */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10937,7 +10045,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_long_2addr: /* 0xbe */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10961,7 +10068,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_long_2addr: /* 0xbf */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10985,7 +10091,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_and_long_2addr: /* 0xc0 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11009,7 +10114,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_or_long_2addr: /* 0xc1 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11033,7 +10137,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_xor_long_2addr: /* 0xc2 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11057,7 +10160,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shl_long_2addr: /* 0xc3 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11081,7 +10183,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shr_long_2addr: /* 0xc4 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11105,7 +10206,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_ushr_long_2addr: /* 0xc5 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11129,7 +10229,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_float_2addr: /* 0xc6 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11153,7 +10252,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_float_2addr: /* 0xc7 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11177,7 +10275,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_float_2addr: /* 0xc8 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11201,7 +10298,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_float_2addr: /* 0xc9 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11225,7 +10321,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_float_2addr: /* 0xca */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11249,7 +10344,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_double_2addr: /* 0xcb */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11273,7 +10367,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_double_2addr: /* 0xcc */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11297,7 +10390,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_double_2addr: /* 0xcd */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11321,7 +10413,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_double_2addr: /* 0xce */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11345,7 +10436,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_double_2addr: /* 0xcf */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11369,7 +10459,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_int_lit16: /* 0xd0 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11393,7 +10482,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rsub_int: /* 0xd1 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11417,7 +10505,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_int_lit16: /* 0xd2 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11441,7 +10528,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_int_lit16: /* 0xd3 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11465,7 +10551,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_int_lit16: /* 0xd4 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11489,7 +10574,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_and_int_lit16: /* 0xd5 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11513,7 +10597,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_or_int_lit16: /* 0xd6 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11537,7 +10620,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_xor_int_lit16: /* 0xd7 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11561,7 +10643,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_int_lit8: /* 0xd8 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11585,7 +10666,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rsub_int_lit8: /* 0xd9 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11609,7 +10689,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_int_lit8: /* 0xda */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11633,7 +10712,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_int_lit8: /* 0xdb */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11657,7 +10735,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_int_lit8: /* 0xdc */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11681,7 +10758,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_and_int_lit8: /* 0xdd */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11705,7 +10781,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_or_int_lit8: /* 0xde */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11729,7 +10804,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_xor_int_lit8: /* 0xdf */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11753,7 +10827,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shl_int_lit8: /* 0xe0 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11777,7 +10850,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shr_int_lit8: /* 0xe1 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11801,7 +10873,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_ushr_int_lit8: /* 0xe2 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11825,7 +10896,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_quick: /* 0xe3 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11849,7 +10919,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_wide_quick: /* 0xe4 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11873,7 +10942,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_object_quick: /* 0xe5 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11897,7 +10965,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_quick: /* 0xe6 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11921,7 +10988,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_wide_quick: /* 0xe7 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11945,7 +11011,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_object_quick: /* 0xe8 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11969,7 +11034,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_virtual_quick: /* 0xe9 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11993,7 +11057,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_virtual_range_quick: /* 0xea */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -12017,7 +11080,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_boolean_quick: /* 0xeb */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -12041,7 +11103,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_byte_quick: /* 0xec */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -12065,7 +11126,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_char_quick: /* 0xed */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -12089,7 +11149,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_short_quick: /* 0xee */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -12113,7 +11172,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_boolean_quick: /* 0xef */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -12137,7 +11195,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_byte_quick: /* 0xf0 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -12161,7 +11218,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_char_quick: /* 0xf1 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -12185,7 +11241,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_short_quick: /* 0xf2 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -12209,7 +11264,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_f3: /* 0xf3 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -12233,7 +11287,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_f4: /* 0xf4 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -12257,7 +11310,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_f5: /* 0xf5 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -12281,7 +11333,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_f6: /* 0xf6 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -12305,7 +11356,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_f7: /* 0xf7 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -12329,7 +11379,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_f8: /* 0xf8 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -12353,7 +11402,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_f9: /* 0xf9 */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -12377,7 +11425,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_polymorphic: /* 0xfa */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -12401,7 +11448,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_polymorphic_range: /* 0xfb */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -12425,7 +11471,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_custom: /* 0xfc */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -12449,7 +11494,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_custom_range: /* 0xfd */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -12473,7 +11517,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_method_handle: /* 0xfe */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -12497,7 +11540,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_method_type: /* 0xff */ -/* File: x86/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -12519,14 +11561,11 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop jmp .L_op_nop+(255*128) .balign 128 -/* File: x86/instruction_end_alt.S */ OBJECT_TYPE(artMterpAsmAltInstructionEnd) ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionEnd) .global SYMBOL(artMterpAsmAltInstructionEnd) SYMBOL(artMterpAsmAltInstructionEnd): - -/* File: x86/footer.S */ /* * =========================================================================== * Common subroutines and data @@ -12852,4 +11891,3 @@ MRestoreFrame: ret .cfi_endproc SIZE(ExecuteMterpImpl,ExecuteMterpImpl) - diff --git a/runtime/interpreter/mterp/out/mterp_x86_64.S b/runtime/interpreter/mterp/out/mterp_x86_64.S index 6d8bb4c7c4..1c45059e07 100644 --- a/runtime/interpreter/mterp/out/mterp_x86_64.S +++ b/runtime/interpreter/mterp/out/mterp_x86_64.S @@ -1,10 +1,4 @@ -/* - * This file was generated automatically by gen-mterp.py for 'x86_64'. - * - * --> DO NOT EDIT <-- - */ - -/* File: x86_64/header.S */ +/* DO NOT EDIT: This file was generated by gen-mterp.py. */ /* * Copyright (C) 2016 The Android Open Source Project * @@ -307,8 +301,6 @@ unspecified registers or condition codes. movl MACRO_LITERAL(0), (rREFS,\_vreg,4) movl MACRO_LITERAL(0), 4(rREFS,\_vreg,4) .endm - -/* File: x86_64/entry.S */ /* * Copyright (C) 2016 The Android Open Source Project * @@ -389,24 +381,19 @@ SYMBOL(ExecuteMterpImpl): GOTO_NEXT /* NOTE: no fallthrough */ -/* File: x86_64/instruction_start.S */ - OBJECT_TYPE(artMterpAsmInstructionStart) ASM_HIDDEN SYMBOL(artMterpAsmInstructionStart) .global SYMBOL(artMterpAsmInstructionStart) SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .text - /* ------------------------------ */ .balign 128 .L_op_nop: /* 0x00 */ -/* File: x86_64/op_nop.S */ ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 /* ------------------------------ */ .balign 128 .L_op_move: /* 0x01 */ -/* File: x86_64/op_move.S */ /* for move, move-object, long-to-int */ /* op vA, vB */ movl rINST, %eax # eax <- BA @@ -423,7 +410,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_from16: /* 0x02 */ -/* File: x86_64/op_move_from16.S */ /* for: move/from16, move-object/from16 */ /* op vAA, vBBBB */ movzwq 2(rPC), %rax # eax <- BBBB @@ -438,7 +424,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_16: /* 0x03 */ -/* File: x86_64/op_move_16.S */ /* for: move/16, move-object/16 */ /* op vAAAA, vBBBB */ movzwq 4(rPC), %rcx # ecx <- BBBB @@ -454,7 +439,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_wide: /* 0x04 */ -/* File: x86_64/op_move_wide.S */ /* move-wide vA, vB */ /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ movl rINST, %ecx # ecx <- BA @@ -467,7 +451,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_wide_from16: /* 0x05 */ -/* File: x86_64/op_move_wide_from16.S */ /* move-wide/from16 vAA, vBBBB */ /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ movzwl 2(rPC), %ecx # ecx <- BBBB @@ -478,7 +461,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_wide_16: /* 0x06 */ -/* File: x86_64/op_move_wide_16.S */ /* move-wide/16 vAAAA, vBBBB */ /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ movzwq 4(rPC), %rcx # ecx<- BBBB @@ -490,8 +472,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_object: /* 0x07 */ -/* File: x86_64/op_move_object.S */ -/* File: x86_64/op_move.S */ /* for move, move-object, long-to-int */ /* op vA, vB */ movl rINST, %eax # eax <- BA @@ -505,12 +485,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_move_object_from16: /* 0x08 */ -/* File: x86_64/op_move_object_from16.S */ -/* File: x86_64/op_move_from16.S */ /* for: move/from16, move-object/from16 */ /* op vAA, vBBBB */ movzwq 2(rPC), %rax # eax <- BBBB @@ -522,12 +499,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_move_object_16: /* 0x09 */ -/* File: x86_64/op_move_object_16.S */ -/* File: x86_64/op_move_16.S */ /* for: move/16, move-object/16 */ /* op vAAAA, vBBBB */ movzwq 4(rPC), %rcx # ecx <- BBBB @@ -540,11 +514,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 - /* ------------------------------ */ .balign 128 .L_op_move_result: /* 0x0a */ -/* File: x86_64/op_move_result.S */ /* for: move-result, move-result-object */ /* op vAA */ movq OFF_FP_RESULT_REGISTER(rFP), %rax # get pointer to result JType. @@ -559,7 +531,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_result_wide: /* 0x0b */ -/* File: x86_64/op_move_result_wide.S */ /* move-result-wide vAA */ movq OFF_FP_RESULT_REGISTER(rFP), %rax # get pointer to result JType. movq (%rax), %rdx # Get wide @@ -569,8 +540,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_move_result_object: /* 0x0c */ -/* File: x86_64/op_move_result_object.S */ -/* File: x86_64/op_move_result.S */ /* for: move-result, move-result-object */ /* op vAA */ movq OFF_FP_RESULT_REGISTER(rFP), %rax # get pointer to result JType. @@ -582,11 +551,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_move_exception: /* 0x0d */ -/* File: x86_64/op_move_exception.S */ /* move-exception vAA */ movq rSELF, %rcx movl THREAD_EXCEPTION_OFFSET(%rcx), %eax @@ -597,7 +564,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_return_void: /* 0x0e */ -/* File: x86_64/op_return_void.S */ .extern MterpThreadFenceForConstructor call SYMBOL(MterpThreadFenceForConstructor) movq rSELF, OUT_ARG0 @@ -611,7 +577,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_return: /* 0x0f */ -/* File: x86_64/op_return.S */ /* * Return a 32-bit value. * @@ -631,7 +596,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_return_wide: /* 0x10 */ -/* File: x86_64/op_return_wide.S */ /* * Return a 64-bit value. */ @@ -649,8 +613,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_return_object: /* 0x11 */ -/* File: x86_64/op_return_object.S */ -/* File: x86_64/op_return.S */ /* * Return a 32-bit value. * @@ -667,11 +629,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop GET_VREG %eax, rINSTq # eax <- vAA jmp MterpReturn - /* ------------------------------ */ .balign 128 .L_op_const_4: /* 0x12 */ -/* File: x86_64/op_const_4.S */ /* const/4 vA, #+B */ movsbl rINSTbl, %eax # eax <-ssssssBx movl $0xf, rINST @@ -683,7 +643,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_16: /* 0x13 */ -/* File: x86_64/op_const_16.S */ /* const/16 vAA, #+BBBB */ movswl 2(rPC), %ecx # ecx <- ssssBBBB SET_VREG %ecx, rINSTq # vAA <- ssssBBBB @@ -692,7 +651,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const: /* 0x14 */ -/* File: x86_64/op_const.S */ /* const vAA, #+BBBBbbbb */ movl 2(rPC), %eax # grab all 32 bits at once SET_VREG %eax, rINSTq # vAA<- eax @@ -701,7 +659,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_high16: /* 0x15 */ -/* File: x86_64/op_const_high16.S */ /* const/high16 vAA, #+BBBB0000 */ movzwl 2(rPC), %eax # eax <- 0000BBBB sall $16, %eax # eax <- BBBB0000 @@ -711,7 +668,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_wide_16: /* 0x16 */ -/* File: x86_64/op_const_wide_16.S */ /* const-wide/16 vAA, #+BBBB */ movswq 2(rPC), %rax # rax <- ssssBBBB SET_WIDE_VREG %rax, rINSTq # store @@ -720,7 +676,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_wide_32: /* 0x17 */ -/* File: x86_64/op_const_wide_32.S */ /* const-wide/32 vAA, #+BBBBbbbb */ movslq 2(rPC), %rax # eax <- ssssssssBBBBbbbb SET_WIDE_VREG %rax, rINSTq # store @@ -729,7 +684,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_wide: /* 0x18 */ -/* File: x86_64/op_const_wide.S */ /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ movq 2(rPC), %rax # rax <- HHHHhhhhBBBBbbbb SET_WIDE_VREG %rax, rINSTq @@ -738,7 +692,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_wide_high16: /* 0x19 */ -/* File: x86_64/op_const_wide_high16.S */ /* const-wide/high16 vAA, #+BBBB000000000000 */ movzwq 2(rPC), %rax # eax <- 0000BBBB salq $48, %rax # eax <- BBBB0000 @@ -748,8 +701,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_string: /* 0x1a */ -/* File: x86_64/op_const_string.S */ -/* File: x86_64/const.S */ /* const/class vAA, type@BBBB */ /* const/method-handle vAA, method_handle@BBBB */ /* const/method-type vAA, proto@BBBB */ @@ -765,11 +716,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop jnz MterpPossibleException ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_const_string_jumbo: /* 0x1b */ -/* File: x86_64/op_const_string_jumbo.S */ /* const/string vAA, String@BBBBBBBB */ EXPORT_PC movl 2(rPC), OUT_32_ARG0 # OUT_32_ARG0 <- BBBB @@ -784,8 +733,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_const_class: /* 0x1c */ -/* File: x86_64/op_const_class.S */ -/* File: x86_64/const.S */ /* const/class vAA, type@BBBB */ /* const/method-handle vAA, method_handle@BBBB */ /* const/method-type vAA, proto@BBBB */ @@ -801,11 +748,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop jnz MterpPossibleException ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_monitor_enter: /* 0x1d */ -/* File: x86_64/op_monitor_enter.S */ /* * Synchronize on an object. */ @@ -821,7 +766,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_monitor_exit: /* 0x1e */ -/* File: x86_64/op_monitor_exit.S */ /* * Unlock an object. * @@ -841,7 +785,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_check_cast: /* 0x1f */ -/* File: x86_64/op_check_cast.S */ /* * Check to see if a cast from one class to another is allowed. */ @@ -859,7 +802,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_instance_of: /* 0x20 */ -/* File: x86_64/op_instance_of.S */ /* * Check to see if an object reference is an instance of a class. * @@ -886,7 +828,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_array_length: /* 0x21 */ -/* File: x86_64/op_array_length.S */ /* * Return the length of an array. */ @@ -903,7 +844,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_new_instance: /* 0x22 */ -/* File: x86_64/op_new_instance.S */ /* * Create a new instance of a class. */ @@ -921,7 +861,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_new_array: /* 0x23 */ -/* File: x86_64/op_new_array.S */ /* * Allocate an array of objects, specified with the array class * and a count. @@ -944,7 +883,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_filled_new_array: /* 0x24 */ -/* File: x86_64/op_filled_new_array.S */ /* * Create a new array with elements filled from registers. * @@ -965,8 +903,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_filled_new_array_range: /* 0x25 */ -/* File: x86_64/op_filled_new_array_range.S */ -/* File: x86_64/op_filled_new_array.S */ /* * Create a new array with elements filled from registers. * @@ -984,11 +920,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop jz MterpPossibleException ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 - /* ------------------------------ */ .balign 128 .L_op_fill_array_data: /* 0x26 */ -/* File: x86_64/op_fill_array_data.S */ /* fill-array-data vAA, +BBBBBBBB */ EXPORT_PC movslq 2(rPC), %rcx # rcx <- ssssssssBBBBbbbb @@ -1002,7 +936,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_throw: /* 0x27 */ -/* File: x86_64/op_throw.S */ /* * Throw an exception object in the current thread. */ @@ -1018,7 +951,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_goto: /* 0x28 */ -/* File: x86_64/op_goto.S */ /* * Unconditional branch, 8-bit offset. * @@ -1033,7 +965,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_goto_16: /* 0x29 */ -/* File: x86_64/op_goto_16.S */ /* * Unconditional branch, 16-bit offset. * @@ -1048,7 +979,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_goto_32: /* 0x2a */ -/* File: x86_64/op_goto_32.S */ /* * Unconditional branch, 32-bit offset. * @@ -1066,7 +996,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_packed_switch: /* 0x2b */ -/* File: x86_64/op_packed_switch.S */ /* * Handle a packed-switch or sparse-switch instruction. In both cases * we decode it and hand it off to a helper function. @@ -1088,8 +1017,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_sparse_switch: /* 0x2c */ -/* File: x86_64/op_sparse_switch.S */ -/* File: x86_64/op_packed_switch.S */ /* * Handle a packed-switch or sparse-switch instruction. In both cases * we decode it and hand it off to a helper function. @@ -1108,12 +1035,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop movslq %eax, rINSTq jmp MterpCommonTakenBranch - /* ------------------------------ */ .balign 128 .L_op_cmpl_float: /* 0x2d */ -/* File: x86_64/op_cmpl_float.S */ -/* File: x86_64/fpcmp.S */ /* * Compare two floating-point values. Puts 0, 1, or -1 into the * destination register based on the results of the comparison. @@ -1149,12 +1073,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %eax, rINSTq ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_cmpg_float: /* 0x2e */ -/* File: x86_64/op_cmpg_float.S */ -/* File: x86_64/fpcmp.S */ /* * Compare two floating-point values. Puts 0, 1, or -1 into the * destination register based on the results of the comparison. @@ -1190,12 +1111,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %eax, rINSTq ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_cmpl_double: /* 0x2f */ -/* File: x86_64/op_cmpl_double.S */ -/* File: x86_64/fpcmp.S */ /* * Compare two floating-point values. Puts 0, 1, or -1 into the * destination register based on the results of the comparison. @@ -1231,12 +1149,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %eax, rINSTq ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_cmpg_double: /* 0x30 */ -/* File: x86_64/op_cmpg_double.S */ -/* File: x86_64/fpcmp.S */ /* * Compare two floating-point values. Puts 0, 1, or -1 into the * destination register based on the results of the comparison. @@ -1272,11 +1187,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_VREG %eax, rINSTq ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_cmp_long: /* 0x31 */ -/* File: x86_64/op_cmp_long.S */ /* * Compare two 64-bit values. Puts 0, 1, or -1 into the destination * register based on the results of the comparison. @@ -1298,8 +1211,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_if_eq: /* 0x32 */ -/* File: x86_64/op_if_eq.S */ -/* File: x86_64/bincmp.S */ /* * Generic two-operand compare-and-branch operation. Provide a "revcmp" * fragment that specifies the *reverse* comparison to perform, e.g. @@ -1322,12 +1233,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop je .L_check_not_taken_osr ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_if_ne: /* 0x33 */ -/* File: x86_64/op_if_ne.S */ -/* File: x86_64/bincmp.S */ /* * Generic two-operand compare-and-branch operation. Provide a "revcmp" * fragment that specifies the *reverse* comparison to perform, e.g. @@ -1350,12 +1258,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop je .L_check_not_taken_osr ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_if_lt: /* 0x34 */ -/* File: x86_64/op_if_lt.S */ -/* File: x86_64/bincmp.S */ /* * Generic two-operand compare-and-branch operation. Provide a "revcmp" * fragment that specifies the *reverse* comparison to perform, e.g. @@ -1378,12 +1283,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop je .L_check_not_taken_osr ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_if_ge: /* 0x35 */ -/* File: x86_64/op_if_ge.S */ -/* File: x86_64/bincmp.S */ /* * Generic two-operand compare-and-branch operation. Provide a "revcmp" * fragment that specifies the *reverse* comparison to perform, e.g. @@ -1406,12 +1308,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop je .L_check_not_taken_osr ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_if_gt: /* 0x36 */ -/* File: x86_64/op_if_gt.S */ -/* File: x86_64/bincmp.S */ /* * Generic two-operand compare-and-branch operation. Provide a "revcmp" * fragment that specifies the *reverse* comparison to perform, e.g. @@ -1434,12 +1333,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop je .L_check_not_taken_osr ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_if_le: /* 0x37 */ -/* File: x86_64/op_if_le.S */ -/* File: x86_64/bincmp.S */ /* * Generic two-operand compare-and-branch operation. Provide a "revcmp" * fragment that specifies the *reverse* comparison to perform, e.g. @@ -1462,12 +1358,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop je .L_check_not_taken_osr ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_if_eqz: /* 0x38 */ -/* File: x86_64/op_if_eqz.S */ -/* File: x86_64/zcmp.S */ /* * Generic one-operand compare-and-branch operation. Provide a "revcmp" * fragment that specifies the *reverse* comparison to perform, e.g. @@ -1486,12 +1379,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop je .L_check_not_taken_osr ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_if_nez: /* 0x39 */ -/* File: x86_64/op_if_nez.S */ -/* File: x86_64/zcmp.S */ /* * Generic one-operand compare-and-branch operation. Provide a "revcmp" * fragment that specifies the *reverse* comparison to perform, e.g. @@ -1510,12 +1400,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop je .L_check_not_taken_osr ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_if_ltz: /* 0x3a */ -/* File: x86_64/op_if_ltz.S */ -/* File: x86_64/zcmp.S */ /* * Generic one-operand compare-and-branch operation. Provide a "revcmp" * fragment that specifies the *reverse* comparison to perform, e.g. @@ -1534,12 +1421,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop je .L_check_not_taken_osr ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_if_gez: /* 0x3b */ -/* File: x86_64/op_if_gez.S */ -/* File: x86_64/zcmp.S */ /* * Generic one-operand compare-and-branch operation. Provide a "revcmp" * fragment that specifies the *reverse* comparison to perform, e.g. @@ -1558,12 +1442,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop je .L_check_not_taken_osr ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_if_gtz: /* 0x3c */ -/* File: x86_64/op_if_gtz.S */ -/* File: x86_64/zcmp.S */ /* * Generic one-operand compare-and-branch operation. Provide a "revcmp" * fragment that specifies the *reverse* comparison to perform, e.g. @@ -1582,12 +1463,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop je .L_check_not_taken_osr ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_if_lez: /* 0x3d */ -/* File: x86_64/op_if_lez.S */ -/* File: x86_64/zcmp.S */ /* * Generic one-operand compare-and-branch operation. Provide a "revcmp" * fragment that specifies the *reverse* comparison to perform, e.g. @@ -1606,77 +1484,57 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop je .L_check_not_taken_osr ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_unused_3e: /* 0x3e */ -/* File: x86_64/op_unused_3e.S */ -/* File: x86_64/unused.S */ /* * Bail to reference interpreter to throw. */ jmp MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_3f: /* 0x3f */ -/* File: x86_64/op_unused_3f.S */ -/* File: x86_64/unused.S */ /* * Bail to reference interpreter to throw. */ jmp MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_40: /* 0x40 */ -/* File: x86_64/op_unused_40.S */ -/* File: x86_64/unused.S */ /* * Bail to reference interpreter to throw. */ jmp MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_41: /* 0x41 */ -/* File: x86_64/op_unused_41.S */ -/* File: x86_64/unused.S */ /* * Bail to reference interpreter to throw. */ jmp MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_42: /* 0x42 */ -/* File: x86_64/op_unused_42.S */ -/* File: x86_64/unused.S */ /* * Bail to reference interpreter to throw. */ jmp MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_43: /* 0x43 */ -/* File: x86_64/op_unused_43.S */ -/* File: x86_64/unused.S */ /* * Bail to reference interpreter to throw. */ jmp MterpFallback - /* ------------------------------ */ .balign 128 .L_op_aget: /* 0x44 */ -/* File: x86_64/op_aget.S */ /* * Array get, 32 bits or less. vAA <- vBB[vCC]. * @@ -1704,8 +1562,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_aget_wide: /* 0x45 */ -/* File: x86_64/op_aget_wide.S */ -/* File: x86_64/op_aget.S */ /* * Array get, 32 bits or less. vAA <- vBB[vCC]. * @@ -1730,11 +1586,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_aget_object: /* 0x46 */ -/* File: x86_64/op_aget_object.S */ /* * Array object get. vAA <- vBB[vCC]. * @@ -1756,8 +1610,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_aget_boolean: /* 0x47 */ -/* File: x86_64/op_aget_boolean.S */ -/* File: x86_64/op_aget.S */ /* * Array get, 32 bits or less. vAA <- vBB[vCC]. * @@ -1782,12 +1634,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_aget_byte: /* 0x48 */ -/* File: x86_64/op_aget_byte.S */ -/* File: x86_64/op_aget.S */ /* * Array get, 32 bits or less. vAA <- vBB[vCC]. * @@ -1812,12 +1661,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_aget_char: /* 0x49 */ -/* File: x86_64/op_aget_char.S */ -/* File: x86_64/op_aget.S */ /* * Array get, 32 bits or less. vAA <- vBB[vCC]. * @@ -1842,12 +1688,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_aget_short: /* 0x4a */ -/* File: x86_64/op_aget_short.S */ -/* File: x86_64/op_aget.S */ /* * Array get, 32 bits or less. vAA <- vBB[vCC]. * @@ -1872,11 +1715,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_aput: /* 0x4b */ -/* File: x86_64/op_aput.S */ /* * Array put, 32 bits or less. vBB[vCC] <- vAA. * @@ -1903,8 +1744,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_aput_wide: /* 0x4c */ -/* File: x86_64/op_aput_wide.S */ -/* File: x86_64/op_aput.S */ /* * Array put, 32 bits or less. vBB[vCC] <- vAA. * @@ -1928,11 +1767,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop movq rINSTq, MIRROR_WIDE_ARRAY_DATA_OFFSET(%rax,%rcx,8) ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_aput_object: /* 0x4d */ -/* File: x86_64/op_aput_object.S */ /* * Store an object into an array. vBB[vCC] <- vAA. */ @@ -1950,8 +1787,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_aput_boolean: /* 0x4e */ -/* File: x86_64/op_aput_boolean.S */ -/* File: x86_64/op_aput.S */ /* * Array put, 32 bits or less. vBB[vCC] <- vAA. * @@ -1975,12 +1810,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop movb rINSTbl, MIRROR_BOOLEAN_ARRAY_DATA_OFFSET(%rax,%rcx,1) ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_aput_byte: /* 0x4f */ -/* File: x86_64/op_aput_byte.S */ -/* File: x86_64/op_aput.S */ /* * Array put, 32 bits or less. vBB[vCC] <- vAA. * @@ -2004,12 +1836,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop movb rINSTbl, MIRROR_BYTE_ARRAY_DATA_OFFSET(%rax,%rcx,1) ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_aput_char: /* 0x50 */ -/* File: x86_64/op_aput_char.S */ -/* File: x86_64/op_aput.S */ /* * Array put, 32 bits or less. vBB[vCC] <- vAA. * @@ -2033,12 +1862,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop movw rINSTw, MIRROR_CHAR_ARRAY_DATA_OFFSET(%rax,%rcx,2) ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_aput_short: /* 0x51 */ -/* File: x86_64/op_aput_short.S */ -/* File: x86_64/op_aput.S */ /* * Array put, 32 bits or less. vBB[vCC] <- vAA. * @@ -2062,12 +1888,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop movw rINSTw, MIRROR_SHORT_ARRAY_DATA_OFFSET(%rax,%rcx,2) ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_iget: /* 0x52 */ -/* File: x86_64/op_iget.S */ -/* File: x86_64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2082,13 +1905,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop jz MterpPossibleException ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_iget_wide: /* 0x53 */ -/* File: x86_64/op_iget_wide.S */ -/* File: x86_64/op_iget.S */ -/* File: x86_64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2103,14 +1922,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop jz MterpPossibleException ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_iget_object: /* 0x54 */ -/* File: x86_64/op_iget_object.S */ -/* File: x86_64/op_iget.S */ -/* File: x86_64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2125,14 +1939,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop jz MterpPossibleException ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_iget_boolean: /* 0x55 */ -/* File: x86_64/op_iget_boolean.S */ -/* File: x86_64/op_iget.S */ -/* File: x86_64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2147,14 +1956,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop jz MterpPossibleException ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_iget_byte: /* 0x56 */ -/* File: x86_64/op_iget_byte.S */ -/* File: x86_64/op_iget.S */ -/* File: x86_64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2169,14 +1973,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop jz MterpPossibleException ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_iget_char: /* 0x57 */ -/* File: x86_64/op_iget_char.S */ -/* File: x86_64/op_iget.S */ -/* File: x86_64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2191,14 +1990,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop jz MterpPossibleException ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_iget_short: /* 0x58 */ -/* File: x86_64/op_iget_short.S */ -/* File: x86_64/op_iget.S */ -/* File: x86_64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2213,13 +2007,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop jz MterpPossibleException ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_iput: /* 0x59 */ -/* File: x86_64/op_iput.S */ -/* File: x86_64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2234,13 +2024,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop jz MterpPossibleException ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_iput_wide: /* 0x5a */ -/* File: x86_64/op_iput_wide.S */ -/* File: x86_64/op_iput.S */ -/* File: x86_64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2255,14 +2041,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop jz MterpPossibleException ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_iput_object: /* 0x5b */ -/* File: x86_64/op_iput_object.S */ -/* File: x86_64/op_iput.S */ -/* File: x86_64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2277,14 +2058,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop jz MterpPossibleException ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_iput_boolean: /* 0x5c */ -/* File: x86_64/op_iput_boolean.S */ -/* File: x86_64/op_iput.S */ -/* File: x86_64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2299,14 +2075,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop jz MterpPossibleException ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_iput_byte: /* 0x5d */ -/* File: x86_64/op_iput_byte.S */ -/* File: x86_64/op_iput.S */ -/* File: x86_64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2321,14 +2092,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop jz MterpPossibleException ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_iput_char: /* 0x5e */ -/* File: x86_64/op_iput_char.S */ -/* File: x86_64/op_iput.S */ -/* File: x86_64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2343,14 +2109,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop jz MterpPossibleException ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_iput_short: /* 0x5f */ -/* File: x86_64/op_iput_short.S */ -/* File: x86_64/op_iput.S */ -/* File: x86_64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2365,13 +2126,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop jz MterpPossibleException ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_sget: /* 0x60 */ -/* File: x86_64/op_sget.S */ -/* File: x86_64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2386,13 +2143,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop jz MterpPossibleException ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_sget_wide: /* 0x61 */ -/* File: x86_64/op_sget_wide.S */ -/* File: x86_64/op_sget.S */ -/* File: x86_64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2407,14 +2160,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop jz MterpPossibleException ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_sget_object: /* 0x62 */ -/* File: x86_64/op_sget_object.S */ -/* File: x86_64/op_sget.S */ -/* File: x86_64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2429,14 +2177,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop jz MterpPossibleException ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_sget_boolean: /* 0x63 */ -/* File: x86_64/op_sget_boolean.S */ -/* File: x86_64/op_sget.S */ -/* File: x86_64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2451,14 +2194,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop jz MterpPossibleException ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_sget_byte: /* 0x64 */ -/* File: x86_64/op_sget_byte.S */ -/* File: x86_64/op_sget.S */ -/* File: x86_64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2473,14 +2211,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop jz MterpPossibleException ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_sget_char: /* 0x65 */ -/* File: x86_64/op_sget_char.S */ -/* File: x86_64/op_sget.S */ -/* File: x86_64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2495,14 +2228,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop jz MterpPossibleException ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_sget_short: /* 0x66 */ -/* File: x86_64/op_sget_short.S */ -/* File: x86_64/op_sget.S */ -/* File: x86_64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2517,13 +2245,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop jz MterpPossibleException ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_sput: /* 0x67 */ -/* File: x86_64/op_sput.S */ -/* File: x86_64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2538,13 +2262,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop jz MterpPossibleException ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_sput_wide: /* 0x68 */ -/* File: x86_64/op_sput_wide.S */ -/* File: x86_64/op_sput.S */ -/* File: x86_64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2559,14 +2279,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop jz MterpPossibleException ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_sput_object: /* 0x69 */ -/* File: x86_64/op_sput_object.S */ -/* File: x86_64/op_sput.S */ -/* File: x86_64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2581,14 +2296,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop jz MterpPossibleException ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_sput_boolean: /* 0x6a */ -/* File: x86_64/op_sput_boolean.S */ -/* File: x86_64/op_sput.S */ -/* File: x86_64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2603,14 +2313,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop jz MterpPossibleException ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_sput_byte: /* 0x6b */ -/* File: x86_64/op_sput_byte.S */ -/* File: x86_64/op_sput.S */ -/* File: x86_64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2625,14 +2330,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop jz MterpPossibleException ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_sput_char: /* 0x6c */ -/* File: x86_64/op_sput_char.S */ -/* File: x86_64/op_sput.S */ -/* File: x86_64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2647,14 +2347,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop jz MterpPossibleException ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_sput_short: /* 0x6d */ -/* File: x86_64/op_sput_short.S */ -/* File: x86_64/op_sput.S */ -/* File: x86_64/field.S */ /* * General field read / write (iget-* iput-* sget-* sput-*). */ @@ -2669,13 +2364,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop jz MterpPossibleException ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - /* ------------------------------ */ .balign 128 .L_op_invoke_virtual: /* 0x6e */ -/* File: x86_64/op_invoke_virtual.S */ -/* File: x86_64/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -2697,7 +2388,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop jnz MterpFallback FETCH_INST GOTO_NEXT - /* * Handle a virtual method call. * @@ -2709,8 +2399,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_invoke_super: /* 0x6f */ -/* File: x86_64/op_invoke_super.S */ -/* File: x86_64/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -2732,7 +2420,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop jnz MterpFallback FETCH_INST GOTO_NEXT - /* * Handle a "super" method call. * @@ -2744,8 +2431,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_invoke_direct: /* 0x70 */ -/* File: x86_64/op_invoke_direct.S */ -/* File: x86_64/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -2768,12 +2453,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop FETCH_INST GOTO_NEXT - /* ------------------------------ */ .balign 128 .L_op_invoke_static: /* 0x71 */ -/* File: x86_64/op_invoke_static.S */ -/* File: x86_64/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -2796,13 +2478,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop FETCH_INST GOTO_NEXT - - /* ------------------------------ */ .balign 128 .L_op_invoke_interface: /* 0x72 */ -/* File: x86_64/op_invoke_interface.S */ -/* File: x86_64/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -2824,7 +2502,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop jnz MterpFallback FETCH_INST GOTO_NEXT - /* * Handle an interface method call. * @@ -2836,7 +2513,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_return_void_no_barrier: /* 0x73 */ -/* File: x86_64/op_return_void_no_barrier.S */ movq rSELF, OUT_ARG0 testl $(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(OUT_ARG0) jz 1f @@ -2848,8 +2524,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop /* ------------------------------ */ .balign 128 .L_op_invoke_virtual_range: /* 0x74 */ -/* File: x86_64/op_invoke_virtual_range.S */ -/* File: x86_64/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -2872,12 +2546,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop FETCH_INST GOTO_NEXT - /* ------------------------------ */ .balign 128 .L_op_invoke_super_range: /* 0x75 */ -/* File: x86_64/op_invoke_super_range.S */ -/* File: x86_64/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -2900,12 +2571,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop FETCH_INST GOTO_NEXT - /* ------------------------------ */ .balign 128 .L_op_invoke_direct_range: /* 0x76 */ -/* File: x86_64/op_invoke_direct_range.S */ -/* File: x86_64/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -2928,12 +2596,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop FETCH_INST GOTO_NEXT - /* ------------------------------ */ .balign 128 .L_op_invoke_static_range: /* 0x77 */ -/* File: x86_64/op_invoke_static_range.S */ -/* File: x86_64/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -2956,12 +2621,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop FETCH_INST GOTO_NEXT - /* ------------------------------ */ .balign 128 .L_op_invoke_interface_range: /* 0x78 */ -/* File: x86_64/op_invoke_interface_range.S */ -/* File: x86_64/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -2984,34 +2646,25 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop FETCH_INST GOTO_NEXT - /* ------------------------------ */ .balign 128 .L_op_unused_79: /* 0x79 */ -/* File: x86_64/op_unused_79.S */ -/* File: x86_64/unused.S */ /* * Bail to reference interpreter to throw. */ jmp MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_7a: /* 0x7a */ -/* File: x86_64/op_unused_7a.S */ -/* File: x86_64/unused.S */ /* * Bail to reference interpreter to throw. */ jmp MterpFallback - /* ------------------------------ */ .balign 128 .L_op_neg_int: /* 0x7b */ -/* File: x86_64/op_neg_int.S */ -/* File: x86_64/unop.S */ /* * Generic 32/64-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result = op eax". @@ -3034,12 +2687,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_not_int: /* 0x7c */ -/* File: x86_64/op_not_int.S */ -/* File: x86_64/unop.S */ /* * Generic 32/64-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result = op eax". @@ -3062,12 +2712,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_neg_long: /* 0x7d */ -/* File: x86_64/op_neg_long.S */ -/* File: x86_64/unop.S */ /* * Generic 32/64-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result = op eax". @@ -3090,12 +2737,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_not_long: /* 0x7e */ -/* File: x86_64/op_not_long.S */ -/* File: x86_64/unop.S */ /* * Generic 32/64-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result = op eax". @@ -3118,12 +2762,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_neg_float: /* 0x7f */ -/* File: x86_64/op_neg_float.S */ -/* File: x86_64/unop.S */ /* * Generic 32/64-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result = op eax". @@ -3146,12 +2787,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_neg_double: /* 0x80 */ -/* File: x86_64/op_neg_double.S */ -/* File: x86_64/unop.S */ /* * Generic 32/64-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result = op eax". @@ -3174,11 +2812,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_int_to_long: /* 0x81 */ -/* File: x86_64/op_int_to_long.S */ /* int to long vA, vB */ movzbq rINSTbl, %rax # rax <- +A sarl $4, %eax # eax <- B @@ -3187,12 +2823,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop SET_WIDE_VREG %rax, rINSTq # v[A] <- %rax ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_int_to_float: /* 0x82 */ -/* File: x86_64/op_int_to_float.S */ -/* File: x86_64/fpcvt.S */ /* * Generic 32-bit FP conversion operation. */ @@ -3210,12 +2843,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_int_to_double: /* 0x83 */ -/* File: x86_64/op_int_to_double.S */ -/* File: x86_64/fpcvt.S */ /* * Generic 32-bit FP conversion operation. */ @@ -3233,13 +2863,10 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_long_to_int: /* 0x84 */ -/* File: x86_64/op_long_to_int.S */ /* we ignore the high word, making this equivalent to a 32-bit reg move */ -/* File: x86_64/op_move.S */ /* for move, move-object, long-to-int */ /* op vA, vB */ movl rINST, %eax # eax <- BA @@ -3253,12 +2880,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_long_to_float: /* 0x85 */ -/* File: x86_64/op_long_to_float.S */ -/* File: x86_64/fpcvt.S */ /* * Generic 32-bit FP conversion operation. */ @@ -3276,12 +2900,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_long_to_double: /* 0x86 */ -/* File: x86_64/op_long_to_double.S */ -/* File: x86_64/fpcvt.S */ /* * Generic 32-bit FP conversion operation. */ @@ -3299,12 +2920,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_float_to_int: /* 0x87 */ -/* File: x86_64/op_float_to_int.S */ -/* File: x86_64/cvtfp_int.S */ /* On fp to int conversions, Java requires that * if the result > maxint, it should be clamped to maxint. If it is less * than minint, it should be clamped to minint. If it is a nan, the result @@ -3332,12 +2950,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_float_to_long: /* 0x88 */ -/* File: x86_64/op_float_to_long.S */ -/* File: x86_64/cvtfp_int.S */ /* On fp to int conversions, Java requires that * if the result > maxint, it should be clamped to maxint. If it is less * than minint, it should be clamped to minint. If it is a nan, the result @@ -3365,12 +2980,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_float_to_double: /* 0x89 */ -/* File: x86_64/op_float_to_double.S */ -/* File: x86_64/fpcvt.S */ /* * Generic 32-bit FP conversion operation. */ @@ -3388,12 +3000,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_double_to_int: /* 0x8a */ -/* File: x86_64/op_double_to_int.S */ -/* File: x86_64/cvtfp_int.S */ /* On fp to int conversions, Java requires that * if the result > maxint, it should be clamped to maxint. If it is less * than minint, it should be clamped to minint. If it is a nan, the result @@ -3421,12 +3030,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_double_to_long: /* 0x8b */ -/* File: x86_64/op_double_to_long.S */ -/* File: x86_64/cvtfp_int.S */ /* On fp to int conversions, Java requires that * if the result > maxint, it should be clamped to maxint. If it is less * than minint, it should be clamped to minint. If it is a nan, the result @@ -3454,12 +3060,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_double_to_float: /* 0x8c */ -/* File: x86_64/op_double_to_float.S */ -/* File: x86_64/fpcvt.S */ /* * Generic 32-bit FP conversion operation. */ @@ -3477,12 +3080,9 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_int_to_byte: /* 0x8d */ -/* File: x86_64/op_int_to_byte.S */ -/* File: x86_64/unop.S */ /* * Generic 32/64-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result = op eax". @@ -3505,12 +3105,9 @@ movsbl %al, %eax .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_int_to_char: /* 0x8e */ -/* File: x86_64/op_int_to_char.S */ -/* File: x86_64/unop.S */ /* * Generic 32/64-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result = op eax". @@ -3533,12 +3130,9 @@ movzwl %ax,%eax .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_int_to_short: /* 0x8f */ -/* File: x86_64/op_int_to_short.S */ -/* File: x86_64/unop.S */ /* * Generic 32/64-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result = op eax". @@ -3561,12 +3155,9 @@ movswl %ax, %eax .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_add_int: /* 0x90 */ -/* File: x86_64/op_add_int.S */ -/* File: x86_64/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = eax op (rFP,%ecx,4)". @@ -3584,12 +3175,9 @@ movswl %ax, %eax SET_VREG %eax, rINSTq ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_sub_int: /* 0x91 */ -/* File: x86_64/op_sub_int.S */ -/* File: x86_64/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = eax op (rFP,%ecx,4)". @@ -3607,12 +3195,9 @@ movswl %ax, %eax SET_VREG %eax, rINSTq ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_mul_int: /* 0x92 */ -/* File: x86_64/op_mul_int.S */ -/* File: x86_64/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = eax op (rFP,%ecx,4)". @@ -3630,12 +3215,9 @@ movswl %ax, %eax SET_VREG %eax, rINSTq ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_div_int: /* 0x93 */ -/* File: x86_64/op_div_int.S */ -/* File: x86_64/bindiv.S */ /* * 32-bit binary div/rem operation. Handles special case of op1=-1. */ @@ -3670,12 +3252,9 @@ movswl %ax, %eax .endif jmp 1b - /* ------------------------------ */ .balign 128 .L_op_rem_int: /* 0x94 */ -/* File: x86_64/op_rem_int.S */ -/* File: x86_64/bindiv.S */ /* * 32-bit binary div/rem operation. Handles special case of op1=-1. */ @@ -3710,12 +3289,9 @@ movswl %ax, %eax .endif jmp 1b - /* ------------------------------ */ .balign 128 .L_op_and_int: /* 0x95 */ -/* File: x86_64/op_and_int.S */ -/* File: x86_64/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = eax op (rFP,%ecx,4)". @@ -3733,12 +3309,9 @@ movswl %ax, %eax SET_VREG %eax, rINSTq ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_or_int: /* 0x96 */ -/* File: x86_64/op_or_int.S */ -/* File: x86_64/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = eax op (rFP,%ecx,4)". @@ -3756,12 +3329,9 @@ movswl %ax, %eax SET_VREG %eax, rINSTq ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_xor_int: /* 0x97 */ -/* File: x86_64/op_xor_int.S */ -/* File: x86_64/binop.S */ /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = eax op (rFP,%ecx,4)". @@ -3779,12 +3349,9 @@ movswl %ax, %eax SET_VREG %eax, rINSTq ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_shl_int: /* 0x98 */ -/* File: x86_64/op_shl_int.S */ -/* File: x86_64/binop1.S */ /* * Generic 32-bit binary operation in which both operands loaded to * registers (op0 in eax, op1 in ecx). @@ -3804,12 +3371,9 @@ movswl %ax, %eax .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_shr_int: /* 0x99 */ -/* File: x86_64/op_shr_int.S */ -/* File: x86_64/binop1.S */ /* * Generic 32-bit binary operation in which both operands loaded to * registers (op0 in eax, op1 in ecx). @@ -3829,12 +3393,9 @@ movswl %ax, %eax .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_ushr_int: /* 0x9a */ -/* File: x86_64/op_ushr_int.S */ -/* File: x86_64/binop1.S */ /* * Generic 32-bit binary operation in which both operands loaded to * registers (op0 in eax, op1 in ecx). @@ -3854,12 +3415,9 @@ movswl %ax, %eax .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_add_long: /* 0x9b */ -/* File: x86_64/op_add_long.S */ -/* File: x86_64/binopWide.S */ /* * Generic 64-bit binary operation. */ @@ -3871,12 +3429,9 @@ movswl %ax, %eax SET_WIDE_VREG %rax, rINSTq # v[AA] <- rax ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_sub_long: /* 0x9c */ -/* File: x86_64/op_sub_long.S */ -/* File: x86_64/binopWide.S */ /* * Generic 64-bit binary operation. */ @@ -3888,12 +3443,9 @@ movswl %ax, %eax SET_WIDE_VREG %rax, rINSTq # v[AA] <- rax ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_mul_long: /* 0x9d */ -/* File: x86_64/op_mul_long.S */ -/* File: x86_64/binopWide.S */ /* * Generic 64-bit binary operation. */ @@ -3905,12 +3457,9 @@ movswl %ax, %eax SET_WIDE_VREG %rax, rINSTq # v[AA] <- rax ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_div_long: /* 0x9e */ -/* File: x86_64/op_div_long.S */ -/* File: x86_64/bindiv.S */ /* * 32-bit binary div/rem operation. Handles special case of op1=-1. */ @@ -3945,12 +3494,9 @@ movswl %ax, %eax .endif jmp 1b - /* ------------------------------ */ .balign 128 .L_op_rem_long: /* 0x9f */ -/* File: x86_64/op_rem_long.S */ -/* File: x86_64/bindiv.S */ /* * 32-bit binary div/rem operation. Handles special case of op1=-1. */ @@ -3985,12 +3531,9 @@ movswl %ax, %eax .endif jmp 1b - /* ------------------------------ */ .balign 128 .L_op_and_long: /* 0xa0 */ -/* File: x86_64/op_and_long.S */ -/* File: x86_64/binopWide.S */ /* * Generic 64-bit binary operation. */ @@ -4002,12 +3545,9 @@ movswl %ax, %eax SET_WIDE_VREG %rax, rINSTq # v[AA] <- rax ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_or_long: /* 0xa1 */ -/* File: x86_64/op_or_long.S */ -/* File: x86_64/binopWide.S */ /* * Generic 64-bit binary operation. */ @@ -4019,12 +3559,9 @@ movswl %ax, %eax SET_WIDE_VREG %rax, rINSTq # v[AA] <- rax ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_xor_long: /* 0xa2 */ -/* File: x86_64/op_xor_long.S */ -/* File: x86_64/binopWide.S */ /* * Generic 64-bit binary operation. */ @@ -4036,12 +3573,9 @@ movswl %ax, %eax SET_WIDE_VREG %rax, rINSTq # v[AA] <- rax ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_shl_long: /* 0xa3 */ -/* File: x86_64/op_shl_long.S */ -/* File: x86_64/binop1.S */ /* * Generic 32-bit binary operation in which both operands loaded to * registers (op0 in eax, op1 in ecx). @@ -4061,12 +3595,9 @@ movswl %ax, %eax .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_shr_long: /* 0xa4 */ -/* File: x86_64/op_shr_long.S */ -/* File: x86_64/binop1.S */ /* * Generic 32-bit binary operation in which both operands loaded to * registers (op0 in eax, op1 in ecx). @@ -4086,12 +3617,9 @@ movswl %ax, %eax .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_ushr_long: /* 0xa5 */ -/* File: x86_64/op_ushr_long.S */ -/* File: x86_64/binop1.S */ /* * Generic 32-bit binary operation in which both operands loaded to * registers (op0 in eax, op1 in ecx). @@ -4111,12 +3639,9 @@ movswl %ax, %eax .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_add_float: /* 0xa6 */ -/* File: x86_64/op_add_float.S */ -/* File: x86_64/sseBinop.S */ movzbq 2(rPC), %rcx # ecx <- BB movzbq 3(rPC), %rax # eax <- CC movss VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src @@ -4126,12 +3651,9 @@ movswl %ax, %eax movss %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_sub_float: /* 0xa7 */ -/* File: x86_64/op_sub_float.S */ -/* File: x86_64/sseBinop.S */ movzbq 2(rPC), %rcx # ecx <- BB movzbq 3(rPC), %rax # eax <- CC movss VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src @@ -4141,12 +3663,9 @@ movswl %ax, %eax movss %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_mul_float: /* 0xa8 */ -/* File: x86_64/op_mul_float.S */ -/* File: x86_64/sseBinop.S */ movzbq 2(rPC), %rcx # ecx <- BB movzbq 3(rPC), %rax # eax <- CC movss VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src @@ -4156,12 +3675,9 @@ movswl %ax, %eax movss %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_div_float: /* 0xa9 */ -/* File: x86_64/op_div_float.S */ -/* File: x86_64/sseBinop.S */ movzbq 2(rPC), %rcx # ecx <- BB movzbq 3(rPC), %rax # eax <- CC movss VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src @@ -4171,11 +3687,9 @@ movswl %ax, %eax movss %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_rem_float: /* 0xaa */ -/* File: x86_64/op_rem_float.S */ /* rem_float vAA, vBB, vCC */ movzbq 3(rPC), %rcx # ecx <- BB movzbq 2(rPC), %rax # eax <- CC @@ -4194,8 +3708,6 @@ movswl %ax, %eax /* ------------------------------ */ .balign 128 .L_op_add_double: /* 0xab */ -/* File: x86_64/op_add_double.S */ -/* File: x86_64/sseBinop.S */ movzbq 2(rPC), %rcx # ecx <- BB movzbq 3(rPC), %rax # eax <- CC movsd VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src @@ -4205,12 +3717,9 @@ movswl %ax, %eax movsd %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_sub_double: /* 0xac */ -/* File: x86_64/op_sub_double.S */ -/* File: x86_64/sseBinop.S */ movzbq 2(rPC), %rcx # ecx <- BB movzbq 3(rPC), %rax # eax <- CC movsd VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src @@ -4220,12 +3729,9 @@ movswl %ax, %eax movsd %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_mul_double: /* 0xad */ -/* File: x86_64/op_mul_double.S */ -/* File: x86_64/sseBinop.S */ movzbq 2(rPC), %rcx # ecx <- BB movzbq 3(rPC), %rax # eax <- CC movsd VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src @@ -4235,12 +3741,9 @@ movswl %ax, %eax movsd %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_div_double: /* 0xae */ -/* File: x86_64/op_div_double.S */ -/* File: x86_64/sseBinop.S */ movzbq 2(rPC), %rcx # ecx <- BB movzbq 3(rPC), %rax # eax <- CC movsd VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src @@ -4250,11 +3753,9 @@ movswl %ax, %eax movsd %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_rem_double: /* 0xaf */ -/* File: x86_64/op_rem_double.S */ /* rem_double vAA, vBB, vCC */ movzbq 3(rPC), %rcx # ecx <- BB movzbq 2(rPC), %rax # eax <- CC @@ -4273,8 +3774,6 @@ movswl %ax, %eax /* ------------------------------ */ .balign 128 .L_op_add_int_2addr: /* 0xb0 */ -/* File: x86_64/op_add_int_2addr.S */ -/* File: x86_64/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0 op r1". @@ -4294,12 +3793,9 @@ movswl %ax, %eax CLEAR_REF %rcx ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_sub_int_2addr: /* 0xb1 */ -/* File: x86_64/op_sub_int_2addr.S */ -/* File: x86_64/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0 op r1". @@ -4319,11 +3815,9 @@ movswl %ax, %eax CLEAR_REF %rcx ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_mul_int_2addr: /* 0xb2 */ -/* File: x86_64/op_mul_int_2addr.S */ /* mul vA, vB */ movl rINST, %ecx # rcx <- A+ sarl $4, rINST # rINST <- B @@ -4336,8 +3830,6 @@ movswl %ax, %eax /* ------------------------------ */ .balign 128 .L_op_div_int_2addr: /* 0xb3 */ -/* File: x86_64/op_div_int_2addr.S */ -/* File: x86_64/bindiv2addr.S */ /* * 32-bit binary div/rem operation. Handles special case of op1=-1. */ @@ -4373,12 +3865,9 @@ movswl %ax, %eax .endif jmp 1b - /* ------------------------------ */ .balign 128 .L_op_rem_int_2addr: /* 0xb4 */ -/* File: x86_64/op_rem_int_2addr.S */ -/* File: x86_64/bindiv2addr.S */ /* * 32-bit binary div/rem operation. Handles special case of op1=-1. */ @@ -4414,12 +3903,9 @@ movswl %ax, %eax .endif jmp 1b - /* ------------------------------ */ .balign 128 .L_op_and_int_2addr: /* 0xb5 */ -/* File: x86_64/op_and_int_2addr.S */ -/* File: x86_64/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0 op r1". @@ -4439,12 +3925,9 @@ movswl %ax, %eax CLEAR_REF %rcx ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_or_int_2addr: /* 0xb6 */ -/* File: x86_64/op_or_int_2addr.S */ -/* File: x86_64/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0 op r1". @@ -4464,12 +3947,9 @@ movswl %ax, %eax CLEAR_REF %rcx ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_xor_int_2addr: /* 0xb7 */ -/* File: x86_64/op_xor_int_2addr.S */ -/* File: x86_64/binop2addr.S */ /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0 op r1". @@ -4489,12 +3969,9 @@ movswl %ax, %eax CLEAR_REF %rcx ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_shl_int_2addr: /* 0xb8 */ -/* File: x86_64/op_shl_int_2addr.S */ -/* File: x86_64/shop2addr.S */ /* * Generic 32-bit "shift/2addr" operation. */ @@ -4514,12 +3991,9 @@ movswl %ax, %eax .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_shr_int_2addr: /* 0xb9 */ -/* File: x86_64/op_shr_int_2addr.S */ -/* File: x86_64/shop2addr.S */ /* * Generic 32-bit "shift/2addr" operation. */ @@ -4539,12 +4013,9 @@ movswl %ax, %eax .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_ushr_int_2addr: /* 0xba */ -/* File: x86_64/op_ushr_int_2addr.S */ -/* File: x86_64/shop2addr.S */ /* * Generic 32-bit "shift/2addr" operation. */ @@ -4564,12 +4035,9 @@ movswl %ax, %eax .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_add_long_2addr: /* 0xbb */ -/* File: x86_64/op_add_long_2addr.S */ -/* File: x86_64/binopWide2addr.S */ /* * Generic 64-bit binary operation. */ @@ -4582,12 +4050,9 @@ movswl %ax, %eax CLEAR_WIDE_REF %rcx ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_sub_long_2addr: /* 0xbc */ -/* File: x86_64/op_sub_long_2addr.S */ -/* File: x86_64/binopWide2addr.S */ /* * Generic 64-bit binary operation. */ @@ -4600,11 +4065,9 @@ movswl %ax, %eax CLEAR_WIDE_REF %rcx ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_mul_long_2addr: /* 0xbd */ -/* File: x86_64/op_mul_long_2addr.S */ /* mul vA, vB */ movl rINST, %ecx # rcx <- A+ sarl $4, rINST # rINST <- B @@ -4617,8 +4080,6 @@ movswl %ax, %eax /* ------------------------------ */ .balign 128 .L_op_div_long_2addr: /* 0xbe */ -/* File: x86_64/op_div_long_2addr.S */ -/* File: x86_64/bindiv2addr.S */ /* * 32-bit binary div/rem operation. Handles special case of op1=-1. */ @@ -4654,12 +4115,9 @@ movswl %ax, %eax .endif jmp 1b - /* ------------------------------ */ .balign 128 .L_op_rem_long_2addr: /* 0xbf */ -/* File: x86_64/op_rem_long_2addr.S */ -/* File: x86_64/bindiv2addr.S */ /* * 32-bit binary div/rem operation. Handles special case of op1=-1. */ @@ -4695,12 +4153,9 @@ movswl %ax, %eax .endif jmp 1b - /* ------------------------------ */ .balign 128 .L_op_and_long_2addr: /* 0xc0 */ -/* File: x86_64/op_and_long_2addr.S */ -/* File: x86_64/binopWide2addr.S */ /* * Generic 64-bit binary operation. */ @@ -4713,12 +4168,9 @@ movswl %ax, %eax CLEAR_WIDE_REF %rcx ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_or_long_2addr: /* 0xc1 */ -/* File: x86_64/op_or_long_2addr.S */ -/* File: x86_64/binopWide2addr.S */ /* * Generic 64-bit binary operation. */ @@ -4731,12 +4183,9 @@ movswl %ax, %eax CLEAR_WIDE_REF %rcx ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_xor_long_2addr: /* 0xc2 */ -/* File: x86_64/op_xor_long_2addr.S */ -/* File: x86_64/binopWide2addr.S */ /* * Generic 64-bit binary operation. */ @@ -4749,12 +4198,9 @@ movswl %ax, %eax CLEAR_WIDE_REF %rcx ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_shl_long_2addr: /* 0xc3 */ -/* File: x86_64/op_shl_long_2addr.S */ -/* File: x86_64/shop2addr.S */ /* * Generic 32-bit "shift/2addr" operation. */ @@ -4774,12 +4220,9 @@ movswl %ax, %eax .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_shr_long_2addr: /* 0xc4 */ -/* File: x86_64/op_shr_long_2addr.S */ -/* File: x86_64/shop2addr.S */ /* * Generic 32-bit "shift/2addr" operation. */ @@ -4799,12 +4242,9 @@ movswl %ax, %eax .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_ushr_long_2addr: /* 0xc5 */ -/* File: x86_64/op_ushr_long_2addr.S */ -/* File: x86_64/shop2addr.S */ /* * Generic 32-bit "shift/2addr" operation. */ @@ -4824,12 +4264,9 @@ movswl %ax, %eax .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_add_float_2addr: /* 0xc6 */ -/* File: x86_64/op_add_float_2addr.S */ -/* File: x86_64/sseBinop2Addr.S */ movl rINST, %ecx # ecx <- A+ andl $0xf, %ecx # ecx <- A movss VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src @@ -4840,12 +4277,9 @@ movswl %ax, %eax movss %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_sub_float_2addr: /* 0xc7 */ -/* File: x86_64/op_sub_float_2addr.S */ -/* File: x86_64/sseBinop2Addr.S */ movl rINST, %ecx # ecx <- A+ andl $0xf, %ecx # ecx <- A movss VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src @@ -4856,12 +4290,9 @@ movswl %ax, %eax movss %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_mul_float_2addr: /* 0xc8 */ -/* File: x86_64/op_mul_float_2addr.S */ -/* File: x86_64/sseBinop2Addr.S */ movl rINST, %ecx # ecx <- A+ andl $0xf, %ecx # ecx <- A movss VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src @@ -4872,12 +4303,9 @@ movswl %ax, %eax movss %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_div_float_2addr: /* 0xc9 */ -/* File: x86_64/op_div_float_2addr.S */ -/* File: x86_64/sseBinop2Addr.S */ movl rINST, %ecx # ecx <- A+ andl $0xf, %ecx # ecx <- A movss VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src @@ -4888,11 +4316,9 @@ movswl %ax, %eax movss %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_rem_float_2addr: /* 0xca */ -/* File: x86_64/op_rem_float_2addr.S */ /* rem_float/2addr vA, vB */ movzbq rINSTbl, %rcx # ecx <- A+ sarl $4, rINST # rINST <- B @@ -4912,8 +4338,6 @@ movswl %ax, %eax /* ------------------------------ */ .balign 128 .L_op_add_double_2addr: /* 0xcb */ -/* File: x86_64/op_add_double_2addr.S */ -/* File: x86_64/sseBinop2Addr.S */ movl rINST, %ecx # ecx <- A+ andl $0xf, %ecx # ecx <- A movsd VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src @@ -4924,12 +4348,9 @@ movswl %ax, %eax movsd %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_sub_double_2addr: /* 0xcc */ -/* File: x86_64/op_sub_double_2addr.S */ -/* File: x86_64/sseBinop2Addr.S */ movl rINST, %ecx # ecx <- A+ andl $0xf, %ecx # ecx <- A movsd VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src @@ -4940,12 +4361,9 @@ movswl %ax, %eax movsd %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_mul_double_2addr: /* 0xcd */ -/* File: x86_64/op_mul_double_2addr.S */ -/* File: x86_64/sseBinop2Addr.S */ movl rINST, %ecx # ecx <- A+ andl $0xf, %ecx # ecx <- A movsd VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src @@ -4956,12 +4374,9 @@ movswl %ax, %eax movsd %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_div_double_2addr: /* 0xce */ -/* File: x86_64/op_div_double_2addr.S */ -/* File: x86_64/sseBinop2Addr.S */ movl rINST, %ecx # ecx <- A+ andl $0xf, %ecx # ecx <- A movsd VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src @@ -4972,11 +4387,9 @@ movswl %ax, %eax movsd %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - /* ------------------------------ */ .balign 128 .L_op_rem_double_2addr: /* 0xcf */ -/* File: x86_64/op_rem_double_2addr.S */ /* rem_double/2addr vA, vB */ movzbq rINSTbl, %rcx # ecx <- A+ sarl $4, rINST # rINST <- B @@ -4996,8 +4409,6 @@ movswl %ax, %eax /* ------------------------------ */ .balign 128 .L_op_add_int_lit16: /* 0xd0 */ -/* File: x86_64/op_add_int_lit16.S */ -/* File: x86_64/binopLit16.S */ /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = eax op ecx". @@ -5017,13 +4428,10 @@ movswl %ax, %eax SET_VREG %eax, rINSTq ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_rsub_int: /* 0xd1 */ -/* File: x86_64/op_rsub_int.S */ /* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ -/* File: x86_64/binopLit16.S */ /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = eax op ecx". @@ -5043,12 +4451,9 @@ movswl %ax, %eax SET_VREG %ecx, rINSTq ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_mul_int_lit16: /* 0xd2 */ -/* File: x86_64/op_mul_int_lit16.S */ -/* File: x86_64/binopLit16.S */ /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = eax op ecx". @@ -5068,12 +4473,9 @@ movswl %ax, %eax SET_VREG %eax, rINSTq ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_div_int_lit16: /* 0xd3 */ -/* File: x86_64/op_div_int_lit16.S */ -/* File: x86_64/bindivLit16.S */ /* * 32-bit binary div/rem operation. Handles special case of op1=-1. */ @@ -5101,12 +4503,9 @@ movswl %ax, %eax .endif jmp 1b - /* ------------------------------ */ .balign 128 .L_op_rem_int_lit16: /* 0xd4 */ -/* File: x86_64/op_rem_int_lit16.S */ -/* File: x86_64/bindivLit16.S */ /* * 32-bit binary div/rem operation. Handles special case of op1=-1. */ @@ -5134,12 +4533,9 @@ movswl %ax, %eax .endif jmp 1b - /* ------------------------------ */ .balign 128 .L_op_and_int_lit16: /* 0xd5 */ -/* File: x86_64/op_and_int_lit16.S */ -/* File: x86_64/binopLit16.S */ /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = eax op ecx". @@ -5159,12 +4555,9 @@ movswl %ax, %eax SET_VREG %eax, rINSTq ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_or_int_lit16: /* 0xd6 */ -/* File: x86_64/op_or_int_lit16.S */ -/* File: x86_64/binopLit16.S */ /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = eax op ecx". @@ -5184,12 +4577,9 @@ movswl %ax, %eax SET_VREG %eax, rINSTq ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_xor_int_lit16: /* 0xd7 */ -/* File: x86_64/op_xor_int_lit16.S */ -/* File: x86_64/binopLit16.S */ /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = eax op ecx". @@ -5209,12 +4599,9 @@ movswl %ax, %eax SET_VREG %eax, rINSTq ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_add_int_lit8: /* 0xd8 */ -/* File: x86_64/op_add_int_lit8.S */ -/* File: x86_64/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = eax op ecx". @@ -5233,12 +4620,9 @@ movswl %ax, %eax SET_VREG %eax, rINSTq ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_rsub_int_lit8: /* 0xd9 */ -/* File: x86_64/op_rsub_int_lit8.S */ -/* File: x86_64/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = eax op ecx". @@ -5257,12 +4641,9 @@ movswl %ax, %eax SET_VREG %ecx, rINSTq ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_mul_int_lit8: /* 0xda */ -/* File: x86_64/op_mul_int_lit8.S */ -/* File: x86_64/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = eax op ecx". @@ -5281,12 +4662,9 @@ movswl %ax, %eax SET_VREG %eax, rINSTq ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_div_int_lit8: /* 0xdb */ -/* File: x86_64/op_div_int_lit8.S */ -/* File: x86_64/bindivLit8.S */ /* * 32-bit div/rem "lit8" binary operation. Handles special case of * op0=minint & op1=-1 @@ -5312,12 +4690,9 @@ movswl %ax, %eax .endif jmp 1b - /* ------------------------------ */ .balign 128 .L_op_rem_int_lit8: /* 0xdc */ -/* File: x86_64/op_rem_int_lit8.S */ -/* File: x86_64/bindivLit8.S */ /* * 32-bit div/rem "lit8" binary operation. Handles special case of * op0=minint & op1=-1 @@ -5343,12 +4718,9 @@ movswl %ax, %eax .endif jmp 1b - /* ------------------------------ */ .balign 128 .L_op_and_int_lit8: /* 0xdd */ -/* File: x86_64/op_and_int_lit8.S */ -/* File: x86_64/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = eax op ecx". @@ -5367,12 +4739,9 @@ movswl %ax, %eax SET_VREG %eax, rINSTq ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_or_int_lit8: /* 0xde */ -/* File: x86_64/op_or_int_lit8.S */ -/* File: x86_64/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = eax op ecx". @@ -5391,12 +4760,9 @@ movswl %ax, %eax SET_VREG %eax, rINSTq ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_xor_int_lit8: /* 0xdf */ -/* File: x86_64/op_xor_int_lit8.S */ -/* File: x86_64/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = eax op ecx". @@ -5415,12 +4781,9 @@ movswl %ax, %eax SET_VREG %eax, rINSTq ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_shl_int_lit8: /* 0xe0 */ -/* File: x86_64/op_shl_int_lit8.S */ -/* File: x86_64/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = eax op ecx". @@ -5439,12 +4802,9 @@ movswl %ax, %eax SET_VREG %eax, rINSTq ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_shr_int_lit8: /* 0xe1 */ -/* File: x86_64/op_shr_int_lit8.S */ -/* File: x86_64/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = eax op ecx". @@ -5463,12 +4823,9 @@ movswl %ax, %eax SET_VREG %eax, rINSTq ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_ushr_int_lit8: /* 0xe2 */ -/* File: x86_64/op_ushr_int_lit8.S */ -/* File: x86_64/binopLit8.S */ /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = eax op ecx". @@ -5487,11 +4844,9 @@ movswl %ax, %eax SET_VREG %eax, rINSTq ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_iget_quick: /* 0xe3 */ -/* File: x86_64/op_iget_quick.S */ /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick, iget-wide-quick */ /* op vA, vB, offset@CCCC */ movl rINST, %ecx # rcx <- BA @@ -5513,8 +4868,6 @@ movswl %ax, %eax /* ------------------------------ */ .balign 128 .L_op_iget_wide_quick: /* 0xe4 */ -/* File: x86_64/op_iget_wide_quick.S */ -/* File: x86_64/op_iget_quick.S */ /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick, iget-wide-quick */ /* op vA, vB, offset@CCCC */ movl rINST, %ecx # rcx <- BA @@ -5533,11 +4886,9 @@ movswl %ax, %eax .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_iget_object_quick: /* 0xe5 */ -/* File: x86_64/op_iget_object_quick.S */ /* For: iget-object-quick */ /* op vA, vB, offset@CCCC */ .extern artIGetObjectFromMterp @@ -5557,7 +4908,6 @@ movswl %ax, %eax /* ------------------------------ */ .balign 128 .L_op_iput_quick: /* 0xe6 */ -/* File: x86_64/op_iput_quick.S */ /* For: iput-quick, iput-object-quick */ /* op vA, vB, offset@CCCC */ movzbq rINSTbl, %rcx # rcx <- BA @@ -5574,7 +4924,6 @@ movswl %ax, %eax /* ------------------------------ */ .balign 128 .L_op_iput_wide_quick: /* 0xe7 */ -/* File: x86_64/op_iput_wide_quick.S */ /* iput-wide-quick vA, vB, offset@CCCC */ movzbq rINSTbl, %rcx # rcx<- BA sarl $4, %ecx # ecx<- B @@ -5591,7 +4940,6 @@ movswl %ax, %eax /* ------------------------------ */ .balign 128 .L_op_iput_object_quick: /* 0xe8 */ -/* File: x86_64/op_iput_object_quick.S */ EXPORT_PC leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG0 movq rPC, OUT_ARG1 @@ -5605,8 +4953,6 @@ movswl %ax, %eax /* ------------------------------ */ .balign 128 .L_op_invoke_virtual_quick: /* 0xe9 */ -/* File: x86_64/op_invoke_virtual_quick.S */ -/* File: x86_64/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -5629,12 +4975,9 @@ movswl %ax, %eax FETCH_INST GOTO_NEXT - /* ------------------------------ */ .balign 128 .L_op_invoke_virtual_range_quick: /* 0xea */ -/* File: x86_64/op_invoke_virtual_range_quick.S */ -/* File: x86_64/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -5657,12 +5000,9 @@ movswl %ax, %eax FETCH_INST GOTO_NEXT - /* ------------------------------ */ .balign 128 .L_op_iput_boolean_quick: /* 0xeb */ -/* File: x86_64/op_iput_boolean_quick.S */ -/* File: x86_64/op_iput_quick.S */ /* For: iput-quick, iput-object-quick */ /* op vA, vB, offset@CCCC */ movzbq rINSTbl, %rcx # rcx <- BA @@ -5676,12 +5016,9 @@ movswl %ax, %eax movb rINSTbl, (%rcx,%rax,1) ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_iput_byte_quick: /* 0xec */ -/* File: x86_64/op_iput_byte_quick.S */ -/* File: x86_64/op_iput_quick.S */ /* For: iput-quick, iput-object-quick */ /* op vA, vB, offset@CCCC */ movzbq rINSTbl, %rcx # rcx <- BA @@ -5695,12 +5032,9 @@ movswl %ax, %eax movb rINSTbl, (%rcx,%rax,1) ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_iput_char_quick: /* 0xed */ -/* File: x86_64/op_iput_char_quick.S */ -/* File: x86_64/op_iput_quick.S */ /* For: iput-quick, iput-object-quick */ /* op vA, vB, offset@CCCC */ movzbq rINSTbl, %rcx # rcx <- BA @@ -5714,12 +5048,9 @@ movswl %ax, %eax movw rINSTw, (%rcx,%rax,1) ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_iput_short_quick: /* 0xee */ -/* File: x86_64/op_iput_short_quick.S */ -/* File: x86_64/op_iput_quick.S */ /* For: iput-quick, iput-object-quick */ /* op vA, vB, offset@CCCC */ movzbq rINSTbl, %rcx # rcx <- BA @@ -5733,12 +5064,9 @@ movswl %ax, %eax movw rINSTw, (%rcx,%rax,1) ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_iget_boolean_quick: /* 0xef */ -/* File: x86_64/op_iget_boolean_quick.S */ -/* File: x86_64/op_iget_quick.S */ /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick, iget-wide-quick */ /* op vA, vB, offset@CCCC */ movl rINST, %ecx # rcx <- BA @@ -5757,12 +5085,9 @@ movswl %ax, %eax .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_iget_byte_quick: /* 0xf0 */ -/* File: x86_64/op_iget_byte_quick.S */ -/* File: x86_64/op_iget_quick.S */ /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick, iget-wide-quick */ /* op vA, vB, offset@CCCC */ movl rINST, %ecx # rcx <- BA @@ -5781,12 +5106,9 @@ movswl %ax, %eax .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_iget_char_quick: /* 0xf1 */ -/* File: x86_64/op_iget_char_quick.S */ -/* File: x86_64/op_iget_quick.S */ /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick, iget-wide-quick */ /* op vA, vB, offset@CCCC */ movl rINST, %ecx # rcx <- BA @@ -5805,12 +5127,9 @@ movswl %ax, %eax .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_iget_short_quick: /* 0xf2 */ -/* File: x86_64/op_iget_short_quick.S */ -/* File: x86_64/op_iget_quick.S */ /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick, iget-wide-quick */ /* op vA, vB, offset@CCCC */ movl rINST, %ecx # rcx <- BA @@ -5829,89 +5148,65 @@ movswl %ax, %eax .endif ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_unused_f3: /* 0xf3 */ -/* File: x86_64/op_unused_f3.S */ -/* File: x86_64/unused.S */ /* * Bail to reference interpreter to throw. */ jmp MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_f4: /* 0xf4 */ -/* File: x86_64/op_unused_f4.S */ -/* File: x86_64/unused.S */ /* * Bail to reference interpreter to throw. */ jmp MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_f5: /* 0xf5 */ -/* File: x86_64/op_unused_f5.S */ -/* File: x86_64/unused.S */ /* * Bail to reference interpreter to throw. */ jmp MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_f6: /* 0xf6 */ -/* File: x86_64/op_unused_f6.S */ -/* File: x86_64/unused.S */ /* * Bail to reference interpreter to throw. */ jmp MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_f7: /* 0xf7 */ -/* File: x86_64/op_unused_f7.S */ -/* File: x86_64/unused.S */ /* * Bail to reference interpreter to throw. */ jmp MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_f8: /* 0xf8 */ -/* File: x86_64/op_unused_f8.S */ -/* File: x86_64/unused.S */ /* * Bail to reference interpreter to throw. */ jmp MterpFallback - /* ------------------------------ */ .balign 128 .L_op_unused_f9: /* 0xf9 */ -/* File: x86_64/op_unused_f9.S */ -/* File: x86_64/unused.S */ /* * Bail to reference interpreter to throw. */ jmp MterpFallback - /* ------------------------------ */ .balign 128 .L_op_invoke_polymorphic: /* 0xfa */ -/* File: x86_64/op_invoke_polymorphic.S */ -/* File: x86_64/invoke_polymorphic.S */ /* * invoke-polymorphic handler wrapper. */ @@ -5934,12 +5229,9 @@ movswl %ax, %eax FETCH_INST GOTO_NEXT - /* ------------------------------ */ .balign 128 .L_op_invoke_polymorphic_range: /* 0xfb */ -/* File: x86_64/op_invoke_polymorphic_range.S */ -/* File: x86_64/invoke_polymorphic.S */ /* * invoke-polymorphic handler wrapper. */ @@ -5962,12 +5254,9 @@ movswl %ax, %eax FETCH_INST GOTO_NEXT - /* ------------------------------ */ .balign 128 .L_op_invoke_custom: /* 0xfc */ -/* File: x86_64/op_invoke_custom.S */ -/* File: x86_64/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -5990,12 +5279,9 @@ movswl %ax, %eax FETCH_INST GOTO_NEXT - /* ------------------------------ */ .balign 128 .L_op_invoke_custom_range: /* 0xfd */ -/* File: x86_64/op_invoke_custom_range.S */ -/* File: x86_64/invoke.S */ /* * Generic invoke handler wrapper. */ @@ -6018,12 +5304,9 @@ movswl %ax, %eax FETCH_INST GOTO_NEXT - /* ------------------------------ */ .balign 128 .L_op_const_method_handle: /* 0xfe */ -/* File: x86_64/op_const_method_handle.S */ -/* File: x86_64/const.S */ /* const/class vAA, type@BBBB */ /* const/method-handle vAA, method_handle@BBBB */ /* const/method-type vAA, proto@BBBB */ @@ -6039,12 +5322,9 @@ movswl %ax, %eax jnz MterpPossibleException ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - /* ------------------------------ */ .balign 128 .L_op_const_method_type: /* 0xff */ -/* File: x86_64/op_const_method_type.S */ -/* File: x86_64/const.S */ /* const/class vAA, type@BBBB */ /* const/method-handle vAA, method_handle@BBBB */ /* const/method-type vAA, proto@BBBB */ @@ -6060,23 +5340,13 @@ movswl %ax, %eax jnz MterpPossibleException ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - .balign 128 -/* File: x86_64/instruction_end.S */ OBJECT_TYPE(artMterpAsmInstructionEnd) ASM_HIDDEN SYMBOL(artMterpAsmInstructionEnd) .global SYMBOL(artMterpAsmInstructionEnd) SYMBOL(artMterpAsmInstructionEnd): - -/* - * =========================================================================== - * Sister implementations - * =========================================================================== - */ -/* File: x86_64/instruction_start_sister.S */ - OBJECT_TYPE(artMterpAsmSisterStart) ASM_HIDDEN SYMBOL(artMterpAsmSisterStart) .global SYMBOL(artMterpAsmSisterStart) @@ -6084,25 +5354,19 @@ SYMBOL(artMterpAsmInstructionEnd): .balign 4 SYMBOL(artMterpAsmSisterStart): -/* File: x86_64/instruction_end_sister.S */ - OBJECT_TYPE(artMterpAsmSisterEnd) ASM_HIDDEN SYMBOL(artMterpAsmSisterEnd) .global SYMBOL(artMterpAsmSisterEnd) SYMBOL(artMterpAsmSisterEnd): -/* File: x86_64/instruction_start_alt.S */ - OBJECT_TYPE(artMterpAsmAltInstructionStart) ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionStart) .global SYMBOL(artMterpAsmAltInstructionStart) .text SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop - /* ------------------------------ */ .balign 128 .L_ALT_op_nop: /* 0x00 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6124,7 +5388,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move: /* 0x01 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6146,7 +5409,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_from16: /* 0x02 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6168,7 +5430,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_16: /* 0x03 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6190,7 +5451,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_wide: /* 0x04 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6212,7 +5472,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_wide_from16: /* 0x05 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6234,7 +5493,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_wide_16: /* 0x06 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6256,7 +5514,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_object: /* 0x07 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6278,7 +5535,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_object_from16: /* 0x08 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6300,7 +5556,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_object_16: /* 0x09 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6322,7 +5577,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_result: /* 0x0a */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6344,7 +5598,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_result_wide: /* 0x0b */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6366,7 +5619,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_result_object: /* 0x0c */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6388,7 +5640,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_move_exception: /* 0x0d */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6410,7 +5661,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_return_void: /* 0x0e */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6432,7 +5682,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_return: /* 0x0f */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6454,7 +5703,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_return_wide: /* 0x10 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6476,7 +5724,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_return_object: /* 0x11 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6498,7 +5745,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_4: /* 0x12 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6520,7 +5766,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_16: /* 0x13 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6542,7 +5787,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const: /* 0x14 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6564,7 +5808,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_high16: /* 0x15 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6586,7 +5829,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_wide_16: /* 0x16 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6608,7 +5850,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_wide_32: /* 0x17 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6630,7 +5871,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_wide: /* 0x18 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6652,7 +5892,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_wide_high16: /* 0x19 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6674,7 +5913,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_string: /* 0x1a */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6696,7 +5934,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_string_jumbo: /* 0x1b */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6718,7 +5955,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_class: /* 0x1c */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6740,7 +5976,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_monitor_enter: /* 0x1d */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6762,7 +5997,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_monitor_exit: /* 0x1e */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6784,7 +6018,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_check_cast: /* 0x1f */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6806,7 +6039,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_instance_of: /* 0x20 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6828,7 +6060,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_array_length: /* 0x21 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6850,7 +6081,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_new_instance: /* 0x22 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6872,7 +6102,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_new_array: /* 0x23 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6894,7 +6123,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_filled_new_array: /* 0x24 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6916,7 +6144,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_filled_new_array_range: /* 0x25 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6938,7 +6165,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_fill_array_data: /* 0x26 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6960,7 +6186,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_throw: /* 0x27 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -6982,7 +6207,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_goto: /* 0x28 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7004,7 +6228,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_goto_16: /* 0x29 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7026,7 +6249,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_goto_32: /* 0x2a */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7048,7 +6270,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_packed_switch: /* 0x2b */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7070,7 +6291,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sparse_switch: /* 0x2c */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7092,7 +6312,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_cmpl_float: /* 0x2d */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7114,7 +6333,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_cmpg_float: /* 0x2e */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7136,7 +6354,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_cmpl_double: /* 0x2f */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7158,7 +6375,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_cmpg_double: /* 0x30 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7180,7 +6396,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_cmp_long: /* 0x31 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7202,7 +6417,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_eq: /* 0x32 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7224,7 +6438,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_ne: /* 0x33 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7246,7 +6459,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_lt: /* 0x34 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7268,7 +6480,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_ge: /* 0x35 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7290,7 +6501,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_gt: /* 0x36 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7312,7 +6522,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_le: /* 0x37 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7334,7 +6543,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_eqz: /* 0x38 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7356,7 +6564,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_nez: /* 0x39 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7378,7 +6585,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_ltz: /* 0x3a */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7400,7 +6606,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_gez: /* 0x3b */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7422,7 +6627,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_gtz: /* 0x3c */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7444,7 +6648,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_if_lez: /* 0x3d */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7466,7 +6669,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_3e: /* 0x3e */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7488,7 +6690,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_3f: /* 0x3f */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7510,7 +6711,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_40: /* 0x40 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7532,7 +6732,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_41: /* 0x41 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7554,7 +6753,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_42: /* 0x42 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7576,7 +6774,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_43: /* 0x43 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7598,7 +6795,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aget: /* 0x44 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7620,7 +6816,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aget_wide: /* 0x45 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7642,7 +6837,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aget_object: /* 0x46 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7664,7 +6858,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aget_boolean: /* 0x47 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7686,7 +6879,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aget_byte: /* 0x48 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7708,7 +6900,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aget_char: /* 0x49 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7730,7 +6921,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aget_short: /* 0x4a */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7752,7 +6942,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aput: /* 0x4b */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7774,7 +6963,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aput_wide: /* 0x4c */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7796,7 +6984,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aput_object: /* 0x4d */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7818,7 +7005,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aput_boolean: /* 0x4e */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7840,7 +7026,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aput_byte: /* 0x4f */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7862,7 +7047,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aput_char: /* 0x50 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7884,7 +7068,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_aput_short: /* 0x51 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7906,7 +7089,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget: /* 0x52 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7928,7 +7110,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_wide: /* 0x53 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7950,7 +7131,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_object: /* 0x54 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7972,7 +7152,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_boolean: /* 0x55 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -7994,7 +7173,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_byte: /* 0x56 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8016,7 +7194,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_char: /* 0x57 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8038,7 +7215,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_short: /* 0x58 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8060,7 +7236,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput: /* 0x59 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8082,7 +7257,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_wide: /* 0x5a */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8104,7 +7278,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_object: /* 0x5b */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8126,7 +7299,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_boolean: /* 0x5c */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8148,7 +7320,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_byte: /* 0x5d */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8170,7 +7341,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_char: /* 0x5e */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8192,7 +7362,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_short: /* 0x5f */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8214,7 +7383,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sget: /* 0x60 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8236,7 +7404,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sget_wide: /* 0x61 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8258,7 +7425,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sget_object: /* 0x62 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8280,7 +7446,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sget_boolean: /* 0x63 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8302,7 +7467,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sget_byte: /* 0x64 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8324,7 +7488,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sget_char: /* 0x65 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8346,7 +7509,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sget_short: /* 0x66 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8368,7 +7530,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sput: /* 0x67 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8390,7 +7551,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sput_wide: /* 0x68 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8412,7 +7572,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sput_object: /* 0x69 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8434,7 +7593,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sput_boolean: /* 0x6a */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8456,7 +7614,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sput_byte: /* 0x6b */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8478,7 +7635,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sput_char: /* 0x6c */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8500,7 +7656,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sput_short: /* 0x6d */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8522,7 +7677,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_virtual: /* 0x6e */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8544,7 +7698,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_super: /* 0x6f */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8566,7 +7719,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_direct: /* 0x70 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8588,7 +7740,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_static: /* 0x71 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8610,7 +7761,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_interface: /* 0x72 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8632,7 +7782,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_return_void_no_barrier: /* 0x73 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8654,7 +7803,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_virtual_range: /* 0x74 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8676,7 +7824,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_super_range: /* 0x75 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8698,7 +7845,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_direct_range: /* 0x76 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8720,7 +7866,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_static_range: /* 0x77 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8742,7 +7887,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_interface_range: /* 0x78 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8764,7 +7908,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_79: /* 0x79 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8786,7 +7929,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_7a: /* 0x7a */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8808,7 +7950,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_neg_int: /* 0x7b */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8830,7 +7971,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_not_int: /* 0x7c */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8852,7 +7992,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_neg_long: /* 0x7d */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8874,7 +8013,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_not_long: /* 0x7e */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8896,7 +8034,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_neg_float: /* 0x7f */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8918,7 +8055,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_neg_double: /* 0x80 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8940,7 +8076,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_int_to_long: /* 0x81 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8962,7 +8097,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_int_to_float: /* 0x82 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -8984,7 +8118,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_int_to_double: /* 0x83 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9006,7 +8139,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_long_to_int: /* 0x84 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9028,7 +8160,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_long_to_float: /* 0x85 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9050,7 +8181,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_long_to_double: /* 0x86 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9072,7 +8202,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_float_to_int: /* 0x87 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9094,7 +8223,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_float_to_long: /* 0x88 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9116,7 +8244,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_float_to_double: /* 0x89 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9138,7 +8265,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_double_to_int: /* 0x8a */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9160,7 +8286,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_double_to_long: /* 0x8b */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9182,7 +8307,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_double_to_float: /* 0x8c */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9204,7 +8328,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_int_to_byte: /* 0x8d */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9226,7 +8349,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_int_to_char: /* 0x8e */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9248,7 +8370,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_int_to_short: /* 0x8f */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9270,7 +8391,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_int: /* 0x90 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9292,7 +8412,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_int: /* 0x91 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9314,7 +8433,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_int: /* 0x92 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9336,7 +8454,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_int: /* 0x93 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9358,7 +8475,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_int: /* 0x94 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9380,7 +8496,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_and_int: /* 0x95 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9402,7 +8517,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_or_int: /* 0x96 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9424,7 +8538,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_xor_int: /* 0x97 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9446,7 +8559,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shl_int: /* 0x98 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9468,7 +8580,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shr_int: /* 0x99 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9490,7 +8601,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_ushr_int: /* 0x9a */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9512,7 +8622,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_long: /* 0x9b */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9534,7 +8643,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_long: /* 0x9c */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9556,7 +8664,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_long: /* 0x9d */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9578,7 +8685,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_long: /* 0x9e */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9600,7 +8706,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_long: /* 0x9f */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9622,7 +8727,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_and_long: /* 0xa0 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9644,7 +8748,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_or_long: /* 0xa1 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9666,7 +8769,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_xor_long: /* 0xa2 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9688,7 +8790,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shl_long: /* 0xa3 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9710,7 +8811,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shr_long: /* 0xa4 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9732,7 +8832,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_ushr_long: /* 0xa5 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9754,7 +8853,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_float: /* 0xa6 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9776,7 +8874,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_float: /* 0xa7 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9798,7 +8895,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_float: /* 0xa8 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9820,7 +8916,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_float: /* 0xa9 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9842,7 +8937,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_float: /* 0xaa */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9864,7 +8958,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_double: /* 0xab */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9886,7 +8979,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_double: /* 0xac */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9908,7 +9000,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_double: /* 0xad */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9930,7 +9021,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_double: /* 0xae */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9952,7 +9042,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_double: /* 0xaf */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9974,7 +9063,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_int_2addr: /* 0xb0 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -9996,7 +9084,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_int_2addr: /* 0xb1 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10018,7 +9105,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_int_2addr: /* 0xb2 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10040,7 +9126,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_int_2addr: /* 0xb3 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10062,7 +9147,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_int_2addr: /* 0xb4 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10084,7 +9168,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_and_int_2addr: /* 0xb5 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10106,7 +9189,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_or_int_2addr: /* 0xb6 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10128,7 +9210,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_xor_int_2addr: /* 0xb7 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10150,7 +9231,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shl_int_2addr: /* 0xb8 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10172,7 +9252,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shr_int_2addr: /* 0xb9 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10194,7 +9273,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_ushr_int_2addr: /* 0xba */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10216,7 +9294,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_long_2addr: /* 0xbb */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10238,7 +9315,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_long_2addr: /* 0xbc */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10260,7 +9336,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_long_2addr: /* 0xbd */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10282,7 +9357,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_long_2addr: /* 0xbe */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10304,7 +9378,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_long_2addr: /* 0xbf */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10326,7 +9399,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_and_long_2addr: /* 0xc0 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10348,7 +9420,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_or_long_2addr: /* 0xc1 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10370,7 +9441,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_xor_long_2addr: /* 0xc2 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10392,7 +9462,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shl_long_2addr: /* 0xc3 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10414,7 +9483,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shr_long_2addr: /* 0xc4 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10436,7 +9504,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_ushr_long_2addr: /* 0xc5 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10458,7 +9525,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_float_2addr: /* 0xc6 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10480,7 +9546,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_float_2addr: /* 0xc7 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10502,7 +9567,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_float_2addr: /* 0xc8 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10524,7 +9588,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_float_2addr: /* 0xc9 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10546,7 +9609,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_float_2addr: /* 0xca */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10568,7 +9630,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_double_2addr: /* 0xcb */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10590,7 +9651,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_sub_double_2addr: /* 0xcc */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10612,7 +9672,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_double_2addr: /* 0xcd */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10634,7 +9693,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_double_2addr: /* 0xce */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10656,7 +9714,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_double_2addr: /* 0xcf */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10678,7 +9735,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_int_lit16: /* 0xd0 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10700,7 +9756,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rsub_int: /* 0xd1 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10722,7 +9777,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_int_lit16: /* 0xd2 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10744,7 +9798,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_int_lit16: /* 0xd3 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10766,7 +9819,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_int_lit16: /* 0xd4 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10788,7 +9840,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_and_int_lit16: /* 0xd5 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10810,7 +9861,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_or_int_lit16: /* 0xd6 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10832,7 +9882,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_xor_int_lit16: /* 0xd7 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10854,7 +9903,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_add_int_lit8: /* 0xd8 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10876,7 +9924,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rsub_int_lit8: /* 0xd9 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10898,7 +9945,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_mul_int_lit8: /* 0xda */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10920,7 +9966,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_div_int_lit8: /* 0xdb */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10942,7 +9987,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_rem_int_lit8: /* 0xdc */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10964,7 +10008,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_and_int_lit8: /* 0xdd */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -10986,7 +10029,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_or_int_lit8: /* 0xde */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11008,7 +10050,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_xor_int_lit8: /* 0xdf */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11030,7 +10071,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shl_int_lit8: /* 0xe0 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11052,7 +10092,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_shr_int_lit8: /* 0xe1 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11074,7 +10113,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_ushr_int_lit8: /* 0xe2 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11096,7 +10134,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_quick: /* 0xe3 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11118,7 +10155,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_wide_quick: /* 0xe4 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11140,7 +10176,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_object_quick: /* 0xe5 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11162,7 +10197,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_quick: /* 0xe6 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11184,7 +10218,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_wide_quick: /* 0xe7 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11206,7 +10239,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_object_quick: /* 0xe8 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11228,7 +10260,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_virtual_quick: /* 0xe9 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11250,7 +10281,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_virtual_range_quick: /* 0xea */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11272,7 +10302,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_boolean_quick: /* 0xeb */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11294,7 +10323,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_byte_quick: /* 0xec */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11316,7 +10344,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_char_quick: /* 0xed */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11338,7 +10365,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iput_short_quick: /* 0xee */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11360,7 +10386,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_boolean_quick: /* 0xef */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11382,7 +10407,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_byte_quick: /* 0xf0 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11404,7 +10428,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_char_quick: /* 0xf1 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11426,7 +10449,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_iget_short_quick: /* 0xf2 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11448,7 +10470,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_f3: /* 0xf3 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11470,7 +10491,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_f4: /* 0xf4 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11492,7 +10512,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_f5: /* 0xf5 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11514,7 +10533,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_f6: /* 0xf6 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11536,7 +10554,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_f7: /* 0xf7 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11558,7 +10575,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_f8: /* 0xf8 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11580,7 +10596,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_unused_f9: /* 0xf9 */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11602,7 +10617,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_polymorphic: /* 0xfa */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11624,7 +10638,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_polymorphic_range: /* 0xfb */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11646,7 +10659,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_custom: /* 0xfc */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11668,7 +10680,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_invoke_custom_range: /* 0xfd */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11690,7 +10701,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_method_handle: /* 0xfe */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11712,7 +10722,6 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop /* ------------------------------ */ .balign 128 .L_ALT_op_const_method_type: /* 0xff */ -/* File: x86_64/alt_stub.S */ /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction @@ -11732,14 +10741,11 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop jmp .L_op_nop+(255*128) .balign 128 -/* File: x86_64/instruction_end_alt.S */ OBJECT_TYPE(artMterpAsmAltInstructionEnd) ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionEnd) .global SYMBOL(artMterpAsmAltInstructionEnd) SYMBOL(artMterpAsmAltInstructionEnd): - -/* File: x86_64/footer.S */ /* * =========================================================================== * Common subroutines and data @@ -12037,4 +11043,3 @@ MRestoreFrame: ret .cfi_endproc SIZE(ExecuteMterpImpl,ExecuteMterpImpl) - diff --git a/runtime/interpreter/mterp/rebuild.sh b/runtime/interpreter/mterp/rebuild.sh deleted file mode 100755 index ca3dcd9a13..0000000000 --- a/runtime/interpreter/mterp/rebuild.sh +++ /dev/null @@ -1,23 +0,0 @@ -#!/bin/sh -# -# Copyright (C) 2016 The Android Open Source Project -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -# -# Rebuild for all known targets. Necessary until the stuff in "out" gets -# generated as part of the build. -# -set -e - -for arch in arm x86 mips arm64 x86_64 mips64; do TARGET_ARCH_EXT=$arch make -f Makefile_mterp; done diff --git a/runtime/interpreter/mterp/x86/alt_stub.S b/runtime/interpreter/mterp/x86/alt_stub.S index a5b39b80e9..79e3f74d1a 100644 --- a/runtime/interpreter/mterp/x86/alt_stub.S +++ b/runtime/interpreter/mterp/x86/alt_stub.S @@ -1,3 +1,4 @@ +%def alt_stub(): /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction diff --git a/runtime/interpreter/mterp/x86/bincmp.S b/runtime/interpreter/mterp/x86/bincmp.S index ee32278d5b..28ea08e341 100644 --- a/runtime/interpreter/mterp/x86/bincmp.S +++ b/runtime/interpreter/mterp/x86/bincmp.S @@ -1,3 +1,4 @@ +%def bincmp(revcmp=""): /* * Generic two-operand compare-and-branch operation. Provide a "revcmp" * fragment that specifies the *reverse* comparison to perform, e.g. diff --git a/runtime/interpreter/mterp/x86/bindiv.S b/runtime/interpreter/mterp/x86/bindiv.S index e87ba45546..e59e6ad680 100644 --- a/runtime/interpreter/mterp/x86/bindiv.S +++ b/runtime/interpreter/mterp/x86/bindiv.S @@ -1,4 +1,4 @@ -%default {"result":"","special":"","rem":""} +%def bindiv(result="", special="", rem=""): /* * 32-bit binary div/rem operation. Handles special case of op0=minint and * op1=-1. diff --git a/runtime/interpreter/mterp/x86/bindiv2addr.S b/runtime/interpreter/mterp/x86/bindiv2addr.S index e620996c9f..40c22bb271 100644 --- a/runtime/interpreter/mterp/x86/bindiv2addr.S +++ b/runtime/interpreter/mterp/x86/bindiv2addr.S @@ -1,4 +1,4 @@ -%default {"result":"","special":""} +%def bindiv2addr(result="", special=""): /* * 32-bit binary div/rem operation. Handles special case of op0=minint and * op1=-1. diff --git a/runtime/interpreter/mterp/x86/bindivLit16.S b/runtime/interpreter/mterp/x86/bindivLit16.S index be094aee49..a89f452031 100644 --- a/runtime/interpreter/mterp/x86/bindivLit16.S +++ b/runtime/interpreter/mterp/x86/bindivLit16.S @@ -1,4 +1,4 @@ -%default {"result":"","special":""} +%def bindivLit16(result="", special=""): /* * 32-bit binary div/rem operation. Handles special case of op0=minint and * op1=-1. diff --git a/runtime/interpreter/mterp/x86/bindivLit8.S b/runtime/interpreter/mterp/x86/bindivLit8.S index fddb54574d..ce130194b0 100644 --- a/runtime/interpreter/mterp/x86/bindivLit8.S +++ b/runtime/interpreter/mterp/x86/bindivLit8.S @@ -1,4 +1,4 @@ -%default {"result":"","special":""} +%def bindivLit8(result="", special=""): /* * 32-bit div/rem "lit8" binary operation. Handles special case of * op0=minint & op1=-1 diff --git a/runtime/interpreter/mterp/x86/binop.S b/runtime/interpreter/mterp/x86/binop.S index d895235212..c82737209d 100644 --- a/runtime/interpreter/mterp/x86/binop.S +++ b/runtime/interpreter/mterp/x86/binop.S @@ -1,4 +1,4 @@ -%default {"result":"%eax"} +%def binop(result="%eax", instr=""): /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = eax op (rFP,%ecx,4)". diff --git a/runtime/interpreter/mterp/x86/binop1.S b/runtime/interpreter/mterp/x86/binop1.S index 5049bb325e..e6ae857eed 100644 --- a/runtime/interpreter/mterp/x86/binop1.S +++ b/runtime/interpreter/mterp/x86/binop1.S @@ -1,4 +1,4 @@ -%default {"result":"%eax","tmp":"%ecx"} +%def binop1(result="%eax", tmp="%ecx", instr=""): /* * Generic 32-bit binary operation in which both operands loaded to * registers (op0 in eax, op1 in ecx). diff --git a/runtime/interpreter/mterp/x86/binop2addr.S b/runtime/interpreter/mterp/x86/binop2addr.S index f126234a40..0b74364897 100644 --- a/runtime/interpreter/mterp/x86/binop2addr.S +++ b/runtime/interpreter/mterp/x86/binop2addr.S @@ -1,4 +1,4 @@ -%default {"result":"%eax"} +%def binop2addr(result="%eax", instr=""): /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0 op r1". diff --git a/runtime/interpreter/mterp/x86/binopLit16.S b/runtime/interpreter/mterp/x86/binopLit16.S index 2fd59de936..5b162f16ca 100644 --- a/runtime/interpreter/mterp/x86/binopLit16.S +++ b/runtime/interpreter/mterp/x86/binopLit16.S @@ -1,4 +1,4 @@ -%default {"result":"%eax"} +%def binopLit16(result="%eax", instr=""): /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = eax op ecx". diff --git a/runtime/interpreter/mterp/x86/binopLit8.S b/runtime/interpreter/mterp/x86/binopLit8.S index 67cead27d5..c2ebc1800c 100644 --- a/runtime/interpreter/mterp/x86/binopLit8.S +++ b/runtime/interpreter/mterp/x86/binopLit8.S @@ -1,4 +1,4 @@ -%default {"result":"%eax"} +%def binopLit8(result="%eax", instr=""): /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = eax op ecx". diff --git a/runtime/interpreter/mterp/x86/binopWide.S b/runtime/interpreter/mterp/x86/binopWide.S index da1293d5b9..1e878c8991 100644 --- a/runtime/interpreter/mterp/x86/binopWide.S +++ b/runtime/interpreter/mterp/x86/binopWide.S @@ -1,3 +1,4 @@ +%def binopWide(instr1="", instr2=""): /* * Generic 64-bit binary operation. */ diff --git a/runtime/interpreter/mterp/x86/binopWide2addr.S b/runtime/interpreter/mterp/x86/binopWide2addr.S index da816f468b..65da1df36c 100644 --- a/runtime/interpreter/mterp/x86/binopWide2addr.S +++ b/runtime/interpreter/mterp/x86/binopWide2addr.S @@ -1,3 +1,4 @@ +%def binopWide2addr(instr1="", instr2=""): /* * Generic 64-bit binary operation. */ diff --git a/runtime/interpreter/mterp/x86/const.S b/runtime/interpreter/mterp/x86/const.S index f0cac1a19b..aad76bb4ee 100644 --- a/runtime/interpreter/mterp/x86/const.S +++ b/runtime/interpreter/mterp/x86/const.S @@ -1,4 +1,4 @@ -%default { "helper":"UndefinedConstHandler" } +%def const(helper="UndefinedConstHandler"): /* const/class vAA, type@BBBB */ /* const/method-handle vAA, method_handle@BBBB */ /* const/method-type vAA, proto@BBBB */ diff --git a/runtime/interpreter/mterp/x86/cvtfp_int.S b/runtime/interpreter/mterp/x86/cvtfp_int.S index a8bad639d6..0bc9908e94 100644 --- a/runtime/interpreter/mterp/x86/cvtfp_int.S +++ b/runtime/interpreter/mterp/x86/cvtfp_int.S @@ -1,4 +1,4 @@ -%default {"srcdouble":"1","tgtlong":"1"} +%def cvtfp_int(srcdouble="1", tgtlong="1"): /* On fp to int conversions, Java requires that * if the result > maxint, it should be clamped to maxint. If it is less * than minint, it should be clamped to minint. If it is a nan, the result diff --git a/runtime/interpreter/mterp/x86/entry.S b/runtime/interpreter/mterp/x86/entry.S index 939dc61d95..b6291c1393 100644 --- a/runtime/interpreter/mterp/x86/entry.S +++ b/runtime/interpreter/mterp/x86/entry.S @@ -1,3 +1,4 @@ +%def entry(): /* * Copyright (C) 2016 The Android Open Source Project * diff --git a/runtime/interpreter/mterp/x86/fallback.S b/runtime/interpreter/mterp/x86/fallback.S index 8d61166f63..e3c2e2bd40 100644 --- a/runtime/interpreter/mterp/x86/fallback.S +++ b/runtime/interpreter/mterp/x86/fallback.S @@ -1,3 +1,4 @@ +%def fallback(): /* Transfer stub to alternate interpreter */ jmp MterpFallback diff --git a/runtime/interpreter/mterp/x86/field.S b/runtime/interpreter/mterp/x86/field.S index 8432c744ea..06362d866b 100644 --- a/runtime/interpreter/mterp/x86/field.S +++ b/runtime/interpreter/mterp/x86/field.S @@ -1,4 +1,4 @@ -%default { } +%def field(helper=""): /* * General field read / write (iget-* iput-* sget-* sput-*). */ diff --git a/runtime/interpreter/mterp/x86/footer.S b/runtime/interpreter/mterp/x86/footer.S index 0b08cf98a3..31cc067d5a 100644 --- a/runtime/interpreter/mterp/x86/footer.S +++ b/runtime/interpreter/mterp/x86/footer.S @@ -1,3 +1,4 @@ +%def footer(): /* * =========================================================================== * Common subroutines and data diff --git a/runtime/interpreter/mterp/x86/fpcmp.S b/runtime/interpreter/mterp/x86/fpcmp.S index 5f9eef9d09..7cd18f6227 100644 --- a/runtime/interpreter/mterp/x86/fpcmp.S +++ b/runtime/interpreter/mterp/x86/fpcmp.S @@ -1,4 +1,4 @@ -%default {"suff":"d","nanval":"pos"} +%def fpcmp(suff="d", nanval="pos"): /* * Compare two floating-point values. Puts 0, 1, or -1 into the * destination register based on the results of the comparison. diff --git a/runtime/interpreter/mterp/x86/fpcvt.S b/runtime/interpreter/mterp/x86/fpcvt.S index 780828518f..4280f1580e 100644 --- a/runtime/interpreter/mterp/x86/fpcvt.S +++ b/runtime/interpreter/mterp/x86/fpcvt.S @@ -1,4 +1,4 @@ -%default {"instr":"","load":"","store":"","wide":"0"} +%def fpcvt(instr="", load="", store="", wide="0"): /* * Generic 32-bit FP conversion operation. */ diff --git a/runtime/interpreter/mterp/x86/header.S b/runtime/interpreter/mterp/x86/header.S index a79db27abf..f0d14fea19 100644 --- a/runtime/interpreter/mterp/x86/header.S +++ b/runtime/interpreter/mterp/x86/header.S @@ -1,3 +1,4 @@ +%def header(): /* * Copyright (C) 2016 The Android Open Source Project * diff --git a/runtime/interpreter/mterp/x86/instruction_end.S b/runtime/interpreter/mterp/x86/instruction_end.S index 94587f83b7..5a24b66dec 100644 --- a/runtime/interpreter/mterp/x86/instruction_end.S +++ b/runtime/interpreter/mterp/x86/instruction_end.S @@ -1,3 +1,4 @@ +%def instruction_end(): OBJECT_TYPE(artMterpAsmInstructionEnd) ASM_HIDDEN SYMBOL(artMterpAsmInstructionEnd) diff --git a/runtime/interpreter/mterp/x86/instruction_end_alt.S b/runtime/interpreter/mterp/x86/instruction_end_alt.S index 7757bce9a7..d037db988c 100644 --- a/runtime/interpreter/mterp/x86/instruction_end_alt.S +++ b/runtime/interpreter/mterp/x86/instruction_end_alt.S @@ -1,3 +1,4 @@ +%def instruction_end_alt(): OBJECT_TYPE(artMterpAsmAltInstructionEnd) ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionEnd) diff --git a/runtime/interpreter/mterp/x86/instruction_end_sister.S b/runtime/interpreter/mterp/x86/instruction_end_sister.S index 8eb79accdf..7b1ec89d60 100644 --- a/runtime/interpreter/mterp/x86/instruction_end_sister.S +++ b/runtime/interpreter/mterp/x86/instruction_end_sister.S @@ -1,3 +1,4 @@ +%def instruction_end_sister(): OBJECT_TYPE(artMterpAsmSisterEnd) ASM_HIDDEN SYMBOL(artMterpAsmSisterEnd) diff --git a/runtime/interpreter/mterp/x86/instruction_start.S b/runtime/interpreter/mterp/x86/instruction_start.S index 5d29a81993..dee581b60f 100644 --- a/runtime/interpreter/mterp/x86/instruction_start.S +++ b/runtime/interpreter/mterp/x86/instruction_start.S @@ -1,3 +1,4 @@ +%def instruction_start(): OBJECT_TYPE(artMterpAsmInstructionStart) ASM_HIDDEN SYMBOL(artMterpAsmInstructionStart) diff --git a/runtime/interpreter/mterp/x86/instruction_start_alt.S b/runtime/interpreter/mterp/x86/instruction_start_alt.S index 8dcf5bfaf9..66650e7a6e 100644 --- a/runtime/interpreter/mterp/x86/instruction_start_alt.S +++ b/runtime/interpreter/mterp/x86/instruction_start_alt.S @@ -1,3 +1,4 @@ +%def instruction_start_alt(): OBJECT_TYPE(artMterpAsmAltInstructionStart) ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionStart) diff --git a/runtime/interpreter/mterp/x86/instruction_start_sister.S b/runtime/interpreter/mterp/x86/instruction_start_sister.S index 796e98b09a..8c156adf7e 100644 --- a/runtime/interpreter/mterp/x86/instruction_start_sister.S +++ b/runtime/interpreter/mterp/x86/instruction_start_sister.S @@ -1,3 +1,4 @@ +%def instruction_start_sister(): OBJECT_TYPE(artMterpAsmSisterStart) ASM_HIDDEN SYMBOL(artMterpAsmSisterStart) diff --git a/runtime/interpreter/mterp/x86/invoke.S b/runtime/interpreter/mterp/x86/invoke.S index c23053becb..eb5cdbc786 100644 --- a/runtime/interpreter/mterp/x86/invoke.S +++ b/runtime/interpreter/mterp/x86/invoke.S @@ -1,4 +1,4 @@ -%default { "helper":"UndefinedInvokeHandler" } +%def invoke(helper="UndefinedInvokeHandler"): /* * Generic invoke handler wrapper. */ diff --git a/runtime/interpreter/mterp/x86/invoke_polymorphic.S b/runtime/interpreter/mterp/x86/invoke_polymorphic.S index 5690b22028..63196ec360 100644 --- a/runtime/interpreter/mterp/x86/invoke_polymorphic.S +++ b/runtime/interpreter/mterp/x86/invoke_polymorphic.S @@ -1,4 +1,4 @@ -%default { "helper":"UndefinedInvokeHandler" } +%def invoke_polymorphic(helper="UndefinedInvokeHandler"): /* * invoke-polymorphic handler wrapper. */ diff --git a/runtime/interpreter/mterp/x86/op_add_double.S b/runtime/interpreter/mterp/x86/op_add_double.S index de2708f442..a00923928b 100644 --- a/runtime/interpreter/mterp/x86/op_add_double.S +++ b/runtime/interpreter/mterp/x86/op_add_double.S @@ -1 +1,2 @@ -%include "x86/sseBinop.S" {"instr":"adds","suff":"d"} +%def op_add_double(): +% sseBinop(instr="adds", suff="d") diff --git a/runtime/interpreter/mterp/x86/op_add_double_2addr.S b/runtime/interpreter/mterp/x86/op_add_double_2addr.S index 538c9ab76e..8cb45a9a20 100644 --- a/runtime/interpreter/mterp/x86/op_add_double_2addr.S +++ b/runtime/interpreter/mterp/x86/op_add_double_2addr.S @@ -1 +1,2 @@ -%include "x86/sseBinop2Addr.S" {"instr":"adds","suff":"d"} +%def op_add_double_2addr(): +% sseBinop2Addr(instr="adds", suff="d") diff --git a/runtime/interpreter/mterp/x86/op_add_float.S b/runtime/interpreter/mterp/x86/op_add_float.S index 80b173658b..dee28c7b8b 100644 --- a/runtime/interpreter/mterp/x86/op_add_float.S +++ b/runtime/interpreter/mterp/x86/op_add_float.S @@ -1 +1,2 @@ -%include "x86/sseBinop.S" {"instr":"adds","suff":"s"} +%def op_add_float(): +% sseBinop(instr="adds", suff="s") diff --git a/runtime/interpreter/mterp/x86/op_add_float_2addr.S b/runtime/interpreter/mterp/x86/op_add_float_2addr.S index 6649253976..4deb4451ce 100644 --- a/runtime/interpreter/mterp/x86/op_add_float_2addr.S +++ b/runtime/interpreter/mterp/x86/op_add_float_2addr.S @@ -1 +1,2 @@ -%include "x86/sseBinop2Addr.S" {"instr":"adds","suff":"s"} +%def op_add_float_2addr(): +% sseBinop2Addr(instr="adds", suff="s") diff --git a/runtime/interpreter/mterp/x86/op_add_int.S b/runtime/interpreter/mterp/x86/op_add_int.S index f71a56b65e..9c4455ab64 100644 --- a/runtime/interpreter/mterp/x86/op_add_int.S +++ b/runtime/interpreter/mterp/x86/op_add_int.S @@ -1 +1,2 @@ -%include "x86/binop.S" {"instr":"addl (rFP,%ecx,4), %eax"} +%def op_add_int(): +% binop(instr="addl (rFP,%ecx,4), %eax") diff --git a/runtime/interpreter/mterp/x86/op_add_int_2addr.S b/runtime/interpreter/mterp/x86/op_add_int_2addr.S index 5d43b6517d..b04ae4c57f 100644 --- a/runtime/interpreter/mterp/x86/op_add_int_2addr.S +++ b/runtime/interpreter/mterp/x86/op_add_int_2addr.S @@ -1 +1,2 @@ -%include "x86/binop2addr.S" {"instr":"addl %eax, (rFP,%ecx,4)"} +%def op_add_int_2addr(): +% binop2addr(instr="addl %eax, (rFP,%ecx,4)") diff --git a/runtime/interpreter/mterp/x86/op_add_int_lit16.S b/runtime/interpreter/mterp/x86/op_add_int_lit16.S index 4f34d173f2..a43103019e 100644 --- a/runtime/interpreter/mterp/x86/op_add_int_lit16.S +++ b/runtime/interpreter/mterp/x86/op_add_int_lit16.S @@ -1 +1,2 @@ -%include "x86/binopLit16.S" {"instr":"addl %ecx, %eax"} +%def op_add_int_lit16(): +% binopLit16(instr="addl %ecx, %eax") diff --git a/runtime/interpreter/mterp/x86/op_add_int_lit8.S b/runtime/interpreter/mterp/x86/op_add_int_lit8.S index 3f14744dcd..3205aee0cb 100644 --- a/runtime/interpreter/mterp/x86/op_add_int_lit8.S +++ b/runtime/interpreter/mterp/x86/op_add_int_lit8.S @@ -1 +1,2 @@ -%include "x86/binopLit8.S" {"instr":"addl %ecx, %eax"} +%def op_add_int_lit8(): +% binopLit8(instr="addl %ecx, %eax") diff --git a/runtime/interpreter/mterp/x86/op_add_long.S b/runtime/interpreter/mterp/x86/op_add_long.S index dce0c26527..24a922601f 100644 --- a/runtime/interpreter/mterp/x86/op_add_long.S +++ b/runtime/interpreter/mterp/x86/op_add_long.S @@ -1 +1,2 @@ -%include "x86/binopWide.S" {"instr1":"addl (rFP,%ecx,4), rIBASE", "instr2":"adcl 4(rFP,%ecx,4), %eax"} +%def op_add_long(): +% binopWide(instr1="addl (rFP,%ecx,4), rIBASE", instr2="adcl 4(rFP,%ecx,4), %eax") diff --git a/runtime/interpreter/mterp/x86/op_add_long_2addr.S b/runtime/interpreter/mterp/x86/op_add_long_2addr.S index 7847640e38..e020714a74 100644 --- a/runtime/interpreter/mterp/x86/op_add_long_2addr.S +++ b/runtime/interpreter/mterp/x86/op_add_long_2addr.S @@ -1 +1,2 @@ -%include "x86/binopWide2addr.S" {"instr1":"addl %eax, (rFP,rINST,4)","instr2":"adcl %ecx, 4(rFP,rINST,4)"} +%def op_add_long_2addr(): +% binopWide2addr(instr1="addl %eax, (rFP,rINST,4)", instr2="adcl %ecx, 4(rFP,rINST,4)") diff --git a/runtime/interpreter/mterp/x86/op_aget.S b/runtime/interpreter/mterp/x86/op_aget.S index 338386ff40..fc57a91146 100644 --- a/runtime/interpreter/mterp/x86/op_aget.S +++ b/runtime/interpreter/mterp/x86/op_aget.S @@ -1,4 +1,4 @@ -%default { "load":"movl", "shift":"4", "data_offset":"MIRROR_INT_ARRAY_DATA_OFFSET" } +%def op_aget(load="movl", shift="4", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"): /* * Array get, 32 bits or less. vAA <- vBB[vCC]. * diff --git a/runtime/interpreter/mterp/x86/op_aget_boolean.S b/runtime/interpreter/mterp/x86/op_aget_boolean.S index d910c94e45..279e6fc739 100644 --- a/runtime/interpreter/mterp/x86/op_aget_boolean.S +++ b/runtime/interpreter/mterp/x86/op_aget_boolean.S @@ -1 +1,2 @@ -%include "x86/op_aget.S" { "load":"movzbl", "shift":"1", "data_offset":"MIRROR_BOOLEAN_ARRAY_DATA_OFFSET" } +%def op_aget_boolean(): +% op_aget(load="movzbl", shift="1", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/x86/op_aget_byte.S b/runtime/interpreter/mterp/x86/op_aget_byte.S index aba9ffc25a..1989450743 100644 --- a/runtime/interpreter/mterp/x86/op_aget_byte.S +++ b/runtime/interpreter/mterp/x86/op_aget_byte.S @@ -1 +1,2 @@ -%include "x86/op_aget.S" { "load":"movsbl", "shift":"1", "data_offset":"MIRROR_BYTE_ARRAY_DATA_OFFSET" } +%def op_aget_byte(): +% op_aget(load="movsbl", shift="1", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/x86/op_aget_char.S b/runtime/interpreter/mterp/x86/op_aget_char.S index 748e4108b3..a35269bd65 100644 --- a/runtime/interpreter/mterp/x86/op_aget_char.S +++ b/runtime/interpreter/mterp/x86/op_aget_char.S @@ -1 +1,2 @@ -%include "x86/op_aget.S" { "load":"movzwl", "shift":"2", "data_offset":"MIRROR_CHAR_ARRAY_DATA_OFFSET" } +%def op_aget_char(): +% op_aget(load="movzwl", shift="2", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/x86/op_aget_object.S b/runtime/interpreter/mterp/x86/op_aget_object.S index 35ec053854..4cf90e94a4 100644 --- a/runtime/interpreter/mterp/x86/op_aget_object.S +++ b/runtime/interpreter/mterp/x86/op_aget_object.S @@ -1,3 +1,4 @@ +%def op_aget_object(): /* * Array object get. vAA <- vBB[vCC]. * diff --git a/runtime/interpreter/mterp/x86/op_aget_short.S b/runtime/interpreter/mterp/x86/op_aget_short.S index 6eaf5d922d..ca51ec8052 100644 --- a/runtime/interpreter/mterp/x86/op_aget_short.S +++ b/runtime/interpreter/mterp/x86/op_aget_short.S @@ -1 +1,2 @@ -%include "x86/op_aget.S" { "load":"movswl", "shift":"2", "data_offset":"MIRROR_SHORT_ARRAY_DATA_OFFSET" } +%def op_aget_short(): +% op_aget(load="movswl", shift="2", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/x86/op_aget_wide.S b/runtime/interpreter/mterp/x86/op_aget_wide.S index 92c612a25c..03cf50a5b8 100644 --- a/runtime/interpreter/mterp/x86/op_aget_wide.S +++ b/runtime/interpreter/mterp/x86/op_aget_wide.S @@ -1,3 +1,4 @@ +%def op_aget_wide(): /* * Array get, 64 bits. vAA <- vBB[vCC]. */ diff --git a/runtime/interpreter/mterp/x86/op_and_int.S b/runtime/interpreter/mterp/x86/op_and_int.S index 6272c4e30d..ffa28d70fa 100644 --- a/runtime/interpreter/mterp/x86/op_and_int.S +++ b/runtime/interpreter/mterp/x86/op_and_int.S @@ -1 +1,2 @@ -%include "x86/binop.S" {"instr":"andl (rFP,%ecx,4), %eax"} +%def op_and_int(): +% binop(instr="andl (rFP,%ecx,4), %eax") diff --git a/runtime/interpreter/mterp/x86/op_and_int_2addr.S b/runtime/interpreter/mterp/x86/op_and_int_2addr.S index 95df873171..8648980c19 100644 --- a/runtime/interpreter/mterp/x86/op_and_int_2addr.S +++ b/runtime/interpreter/mterp/x86/op_and_int_2addr.S @@ -1 +1,2 @@ -%include "x86/binop2addr.S" {"instr":"andl %eax, (rFP,%ecx,4)"} +%def op_and_int_2addr(): +% binop2addr(instr="andl %eax, (rFP,%ecx,4)") diff --git a/runtime/interpreter/mterp/x86/op_and_int_lit16.S b/runtime/interpreter/mterp/x86/op_and_int_lit16.S index b062064106..d7752b1230 100644 --- a/runtime/interpreter/mterp/x86/op_and_int_lit16.S +++ b/runtime/interpreter/mterp/x86/op_and_int_lit16.S @@ -1 +1,2 @@ -%include "x86/binopLit16.S" {"instr":"andl %ecx, %eax"} +%def op_and_int_lit16(): +% binopLit16(instr="andl %ecx, %eax") diff --git a/runtime/interpreter/mterp/x86/op_and_int_lit8.S b/runtime/interpreter/mterp/x86/op_and_int_lit8.S index 99915dfa30..a353178a88 100644 --- a/runtime/interpreter/mterp/x86/op_and_int_lit8.S +++ b/runtime/interpreter/mterp/x86/op_and_int_lit8.S @@ -1 +1,2 @@ -%include "x86/binopLit8.S" {"instr":"andl %ecx, %eax"} +%def op_and_int_lit8(): +% binopLit8(instr="andl %ecx, %eax") diff --git a/runtime/interpreter/mterp/x86/op_and_long.S b/runtime/interpreter/mterp/x86/op_and_long.S index f8514ea802..15164aee79 100644 --- a/runtime/interpreter/mterp/x86/op_and_long.S +++ b/runtime/interpreter/mterp/x86/op_and_long.S @@ -1 +1,2 @@ -%include "x86/binopWide.S" {"instr1":"andl (rFP,%ecx,4), rIBASE", "instr2":"andl 4(rFP,%ecx,4), %eax"} +%def op_and_long(): +% binopWide(instr1="andl (rFP,%ecx,4), rIBASE", instr2="andl 4(rFP,%ecx,4), %eax") diff --git a/runtime/interpreter/mterp/x86/op_and_long_2addr.S b/runtime/interpreter/mterp/x86/op_and_long_2addr.S index 37249b8153..173c159f98 100644 --- a/runtime/interpreter/mterp/x86/op_and_long_2addr.S +++ b/runtime/interpreter/mterp/x86/op_and_long_2addr.S @@ -1 +1,2 @@ -%include "x86/binopWide2addr.S" {"instr1":"andl %eax, (rFP,rINST,4)","instr2":"andl %ecx, 4(rFP,rINST,4)"} +%def op_and_long_2addr(): +% binopWide2addr(instr1="andl %eax, (rFP,rINST,4)", instr2="andl %ecx, 4(rFP,rINST,4)") diff --git a/runtime/interpreter/mterp/x86/op_aput.S b/runtime/interpreter/mterp/x86/op_aput.S index 9d8c52d127..60bcc5027d 100644 --- a/runtime/interpreter/mterp/x86/op_aput.S +++ b/runtime/interpreter/mterp/x86/op_aput.S @@ -1,4 +1,4 @@ -%default { "reg":"rINST", "store":"movl", "shift":"4", "data_offset":"MIRROR_INT_ARRAY_DATA_OFFSET" } +%def op_aput(reg="rINST", store="movl", shift="4", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"): /* * Array put, 32 bits or less. vBB[vCC] <- vAA. * diff --git a/runtime/interpreter/mterp/x86/op_aput_boolean.S b/runtime/interpreter/mterp/x86/op_aput_boolean.S index e7fdd53924..8420b5af8f 100644 --- a/runtime/interpreter/mterp/x86/op_aput_boolean.S +++ b/runtime/interpreter/mterp/x86/op_aput_boolean.S @@ -1 +1,2 @@ -%include "x86/op_aput.S" { "reg":"rINSTbl", "store":"movb", "shift":"1", "data_offset":"MIRROR_BOOLEAN_ARRAY_DATA_OFFSET" } +%def op_aput_boolean(): +% op_aput(reg="rINSTbl", store="movb", shift="1", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/x86/op_aput_byte.S b/runtime/interpreter/mterp/x86/op_aput_byte.S index 491d03cd72..6c181a48d9 100644 --- a/runtime/interpreter/mterp/x86/op_aput_byte.S +++ b/runtime/interpreter/mterp/x86/op_aput_byte.S @@ -1 +1,2 @@ -%include "x86/op_aput.S" { "reg":"rINSTbl", "store":"movb", "shift":"1", "data_offset":"MIRROR_BYTE_ARRAY_DATA_OFFSET" } +%def op_aput_byte(): +% op_aput(reg="rINSTbl", store="movb", shift="1", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/x86/op_aput_char.S b/runtime/interpreter/mterp/x86/op_aput_char.S index ca42cf0c74..3f4602a7f4 100644 --- a/runtime/interpreter/mterp/x86/op_aput_char.S +++ b/runtime/interpreter/mterp/x86/op_aput_char.S @@ -1 +1,2 @@ -%include "x86/op_aput.S" { "reg":"rINSTw", "store":"movw", "shift":"2", "data_offset":"MIRROR_CHAR_ARRAY_DATA_OFFSET" } +%def op_aput_char(): +% op_aput(reg="rINSTw", store="movw", shift="2", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/x86/op_aput_object.S b/runtime/interpreter/mterp/x86/op_aput_object.S index 980b26a401..5d0bb0b894 100644 --- a/runtime/interpreter/mterp/x86/op_aput_object.S +++ b/runtime/interpreter/mterp/x86/op_aput_object.S @@ -1,3 +1,4 @@ +%def op_aput_object(): /* * Store an object into an array. vBB[vCC] <- vAA. */ diff --git a/runtime/interpreter/mterp/x86/op_aput_short.S b/runtime/interpreter/mterp/x86/op_aput_short.S index 5e634821cc..e76d83368b 100644 --- a/runtime/interpreter/mterp/x86/op_aput_short.S +++ b/runtime/interpreter/mterp/x86/op_aput_short.S @@ -1 +1,2 @@ -%include "x86/op_aput.S" { "reg":"rINSTw", "store":"movw", "shift":"2", "data_offset":"MIRROR_SHORT_ARRAY_DATA_OFFSET" } +%def op_aput_short(): +% op_aput(reg="rINSTw", store="movw", shift="2", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/x86/op_aput_wide.S b/runtime/interpreter/mterp/x86/op_aput_wide.S index 43ef64a54a..c59f7b37ae 100644 --- a/runtime/interpreter/mterp/x86/op_aput_wide.S +++ b/runtime/interpreter/mterp/x86/op_aput_wide.S @@ -1,3 +1,4 @@ +%def op_aput_wide(): /* * Array put, 64 bits. vBB[vCC] <- vAA. * diff --git a/runtime/interpreter/mterp/x86/op_array_length.S b/runtime/interpreter/mterp/x86/op_array_length.S index 60ed80b541..c9d8930643 100644 --- a/runtime/interpreter/mterp/x86/op_array_length.S +++ b/runtime/interpreter/mterp/x86/op_array_length.S @@ -1,3 +1,4 @@ +%def op_array_length(): /* * Return the length of an array. */ diff --git a/runtime/interpreter/mterp/x86/op_check_cast.S b/runtime/interpreter/mterp/x86/op_check_cast.S index d090aa3785..12f8543777 100644 --- a/runtime/interpreter/mterp/x86/op_check_cast.S +++ b/runtime/interpreter/mterp/x86/op_check_cast.S @@ -1,3 +1,4 @@ +%def op_check_cast(): /* * Check to see if a cast from one class to another is allowed. */ diff --git a/runtime/interpreter/mterp/x86/op_cmp_long.S b/runtime/interpreter/mterp/x86/op_cmp_long.S index 1f729b078e..0e33874a33 100644 --- a/runtime/interpreter/mterp/x86/op_cmp_long.S +++ b/runtime/interpreter/mterp/x86/op_cmp_long.S @@ -1,3 +1,4 @@ +%def op_cmp_long(): /* * Compare two 64-bit values. Puts 0, 1, or -1 into the destination * register based on the results of the comparison. diff --git a/runtime/interpreter/mterp/x86/op_cmpg_double.S b/runtime/interpreter/mterp/x86/op_cmpg_double.S index a73ba550d2..1c04e997f1 100644 --- a/runtime/interpreter/mterp/x86/op_cmpg_double.S +++ b/runtime/interpreter/mterp/x86/op_cmpg_double.S @@ -1 +1,2 @@ -%include "x86/fpcmp.S" {"suff":"d","nanval":"pos"} +%def op_cmpg_double(): +% fpcmp(suff="d", nanval="pos") diff --git a/runtime/interpreter/mterp/x86/op_cmpg_float.S b/runtime/interpreter/mterp/x86/op_cmpg_float.S index 648051b583..797c3d52d7 100644 --- a/runtime/interpreter/mterp/x86/op_cmpg_float.S +++ b/runtime/interpreter/mterp/x86/op_cmpg_float.S @@ -1 +1,2 @@ -%include "x86/fpcmp.S" {"suff":"s","nanval":"pos"} +%def op_cmpg_float(): +% fpcmp(suff="s", nanval="pos") diff --git a/runtime/interpreter/mterp/x86/op_cmpl_double.S b/runtime/interpreter/mterp/x86/op_cmpl_double.S index 058163e899..cbe8db713b 100644 --- a/runtime/interpreter/mterp/x86/op_cmpl_double.S +++ b/runtime/interpreter/mterp/x86/op_cmpl_double.S @@ -1 +1,2 @@ -%include "x86/fpcmp.S" {"suff":"d","nanval":"neg"} +%def op_cmpl_double(): +% fpcmp(suff="d", nanval="neg") diff --git a/runtime/interpreter/mterp/x86/op_cmpl_float.S b/runtime/interpreter/mterp/x86/op_cmpl_float.S index 302f078475..068f4cb5c1 100644 --- a/runtime/interpreter/mterp/x86/op_cmpl_float.S +++ b/runtime/interpreter/mterp/x86/op_cmpl_float.S @@ -1 +1,2 @@ -%include "x86/fpcmp.S" {"suff":"s","nanval":"neg"} +%def op_cmpl_float(): +% fpcmp(suff="s", nanval="neg") diff --git a/runtime/interpreter/mterp/x86/op_const.S b/runtime/interpreter/mterp/x86/op_const.S index 544d63b22a..dc4342f571 100644 --- a/runtime/interpreter/mterp/x86/op_const.S +++ b/runtime/interpreter/mterp/x86/op_const.S @@ -1,3 +1,4 @@ +%def op_const(): /* const vAA, #+BBBBbbbb */ movl 2(rPC), %eax # grab all 32 bits at once SET_VREG %eax, rINST # vAA<- eax diff --git a/runtime/interpreter/mterp/x86/op_const_16.S b/runtime/interpreter/mterp/x86/op_const_16.S index 97cd5faf2f..84678ae2a9 100644 --- a/runtime/interpreter/mterp/x86/op_const_16.S +++ b/runtime/interpreter/mterp/x86/op_const_16.S @@ -1,3 +1,4 @@ +%def op_const_16(): /* const/16 vAA, #+BBBB */ movswl 2(rPC), %ecx # ecx <- ssssBBBB SET_VREG %ecx, rINST # vAA <- ssssBBBB diff --git a/runtime/interpreter/mterp/x86/op_const_4.S b/runtime/interpreter/mterp/x86/op_const_4.S index a60ba96c5a..8cfd9c096d 100644 --- a/runtime/interpreter/mterp/x86/op_const_4.S +++ b/runtime/interpreter/mterp/x86/op_const_4.S @@ -1,3 +1,4 @@ +%def op_const_4(): /* const/4 vA, #+B */ movsx rINSTbl, %eax # eax <-ssssssBx movl $$0xf, rINST diff --git a/runtime/interpreter/mterp/x86/op_const_class.S b/runtime/interpreter/mterp/x86/op_const_class.S index 71648b5df7..db12ec3141 100644 --- a/runtime/interpreter/mterp/x86/op_const_class.S +++ b/runtime/interpreter/mterp/x86/op_const_class.S @@ -1 +1,2 @@ -%include "x86/const.S" { "helper":"MterpConstClass" } +%def op_const_class(): +% const(helper="MterpConstClass") diff --git a/runtime/interpreter/mterp/x86/op_const_high16.S b/runtime/interpreter/mterp/x86/op_const_high16.S index 576967af99..5252ba21ba 100644 --- a/runtime/interpreter/mterp/x86/op_const_high16.S +++ b/runtime/interpreter/mterp/x86/op_const_high16.S @@ -1,3 +1,4 @@ +%def op_const_high16(): /* const/high16 vAA, #+BBBB0000 */ movzwl 2(rPC), %eax # eax <- 0000BBBB sall $$16, %eax # eax <- BBBB0000 diff --git a/runtime/interpreter/mterp/x86/op_const_method_handle.S b/runtime/interpreter/mterp/x86/op_const_method_handle.S index 77948fd8f9..2680c17aad 100644 --- a/runtime/interpreter/mterp/x86/op_const_method_handle.S +++ b/runtime/interpreter/mterp/x86/op_const_method_handle.S @@ -1 +1,2 @@ -%include "x86/const.S" { "helper":"MterpConstMethodHandle" } +%def op_const_method_handle(): +% const(helper="MterpConstMethodHandle") diff --git a/runtime/interpreter/mterp/x86/op_const_method_type.S b/runtime/interpreter/mterp/x86/op_const_method_type.S index 03c6ce5350..ea814bf648 100644 --- a/runtime/interpreter/mterp/x86/op_const_method_type.S +++ b/runtime/interpreter/mterp/x86/op_const_method_type.S @@ -1 +1,2 @@ -%include "x86/const.S" { "helper":"MterpConstMethodType" } +%def op_const_method_type(): +% const(helper="MterpConstMethodType") diff --git a/runtime/interpreter/mterp/x86/op_const_string.S b/runtime/interpreter/mterp/x86/op_const_string.S index 5553aab557..41376f8703 100644 --- a/runtime/interpreter/mterp/x86/op_const_string.S +++ b/runtime/interpreter/mterp/x86/op_const_string.S @@ -1 +1,2 @@ -%include "x86/const.S" { "helper":"MterpConstString" } +%def op_const_string(): +% const(helper="MterpConstString") diff --git a/runtime/interpreter/mterp/x86/op_const_string_jumbo.S b/runtime/interpreter/mterp/x86/op_const_string_jumbo.S index e7f952a306..dc70c255ce 100644 --- a/runtime/interpreter/mterp/x86/op_const_string_jumbo.S +++ b/runtime/interpreter/mterp/x86/op_const_string_jumbo.S @@ -1,3 +1,4 @@ +%def op_const_string_jumbo(): /* const/string vAA, String@BBBBBBBB */ EXPORT_PC movl 2(rPC), %eax # eax <- BBBB diff --git a/runtime/interpreter/mterp/x86/op_const_wide.S b/runtime/interpreter/mterp/x86/op_const_wide.S index 3750728128..d076e837aa 100644 --- a/runtime/interpreter/mterp/x86/op_const_wide.S +++ b/runtime/interpreter/mterp/x86/op_const_wide.S @@ -1,3 +1,4 @@ +%def op_const_wide(): /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ movl 2(rPC), %eax # eax <- lsw movzbl rINSTbl, %ecx # ecx <- AA diff --git a/runtime/interpreter/mterp/x86/op_const_wide_16.S b/runtime/interpreter/mterp/x86/op_const_wide_16.S index 1331c329dc..328cdeedce 100644 --- a/runtime/interpreter/mterp/x86/op_const_wide_16.S +++ b/runtime/interpreter/mterp/x86/op_const_wide_16.S @@ -1,3 +1,4 @@ +%def op_const_wide_16(): /* const-wide/16 vAA, #+BBBB */ movswl 2(rPC), %eax # eax <- ssssBBBB movl rIBASE, %ecx # preserve rIBASE (cltd trashes it) diff --git a/runtime/interpreter/mterp/x86/op_const_wide_32.S b/runtime/interpreter/mterp/x86/op_const_wide_32.S index ed7d62b396..c4b5b6714d 100644 --- a/runtime/interpreter/mterp/x86/op_const_wide_32.S +++ b/runtime/interpreter/mterp/x86/op_const_wide_32.S @@ -1,3 +1,4 @@ +%def op_const_wide_32(): /* const-wide/32 vAA, #+BBBBbbbb */ movl 2(rPC), %eax # eax <- BBBBbbbb movl rIBASE, %ecx # preserve rIBASE (cltd trashes it) diff --git a/runtime/interpreter/mterp/x86/op_const_wide_high16.S b/runtime/interpreter/mterp/x86/op_const_wide_high16.S index 11b9310be5..f99e674ce1 100644 --- a/runtime/interpreter/mterp/x86/op_const_wide_high16.S +++ b/runtime/interpreter/mterp/x86/op_const_wide_high16.S @@ -1,3 +1,4 @@ +%def op_const_wide_high16(): /* const-wide/high16 vAA, #+BBBB000000000000 */ movzwl 2(rPC), %eax # eax <- 0000BBBB sall $$16, %eax # eax <- BBBB0000 diff --git a/runtime/interpreter/mterp/x86/op_div_double.S b/runtime/interpreter/mterp/x86/op_div_double.S index 575716dc9d..6b342f89bf 100644 --- a/runtime/interpreter/mterp/x86/op_div_double.S +++ b/runtime/interpreter/mterp/x86/op_div_double.S @@ -1 +1,2 @@ -%include "x86/sseBinop.S" {"instr":"divs","suff":"d"} +%def op_div_double(): +% sseBinop(instr="divs", suff="d") diff --git a/runtime/interpreter/mterp/x86/op_div_double_2addr.S b/runtime/interpreter/mterp/x86/op_div_double_2addr.S index 8229a31d67..212c82547e 100644 --- a/runtime/interpreter/mterp/x86/op_div_double_2addr.S +++ b/runtime/interpreter/mterp/x86/op_div_double_2addr.S @@ -1 +1,2 @@ -%include "x86/sseBinop2Addr.S" {"instr":"divs","suff":"d"} +%def op_div_double_2addr(): +% sseBinop2Addr(instr="divs", suff="d") diff --git a/runtime/interpreter/mterp/x86/op_div_float.S b/runtime/interpreter/mterp/x86/op_div_float.S index 250f1dccc6..b6537d9d89 100644 --- a/runtime/interpreter/mterp/x86/op_div_float.S +++ b/runtime/interpreter/mterp/x86/op_div_float.S @@ -1 +1,2 @@ -%include "x86/sseBinop.S" {"instr":"divs","suff":"s"} +%def op_div_float(): +% sseBinop(instr="divs", suff="s") diff --git a/runtime/interpreter/mterp/x86/op_div_float_2addr.S b/runtime/interpreter/mterp/x86/op_div_float_2addr.S index c30d148356..19ae27d61a 100644 --- a/runtime/interpreter/mterp/x86/op_div_float_2addr.S +++ b/runtime/interpreter/mterp/x86/op_div_float_2addr.S @@ -1 +1,2 @@ -%include "x86/sseBinop2Addr.S" {"instr":"divs","suff":"s"} +%def op_div_float_2addr(): +% sseBinop2Addr(instr="divs", suff="s") diff --git a/runtime/interpreter/mterp/x86/op_div_int.S b/runtime/interpreter/mterp/x86/op_div_int.S index 5fc8fa519e..4df3b927b4 100644 --- a/runtime/interpreter/mterp/x86/op_div_int.S +++ b/runtime/interpreter/mterp/x86/op_div_int.S @@ -1 +1,2 @@ -%include "x86/bindiv.S" {"result":"%eax","special":"$0x80000000","rem":"0"} +%def op_div_int(): +% bindiv(result="%eax", special="$0x80000000", rem="0") diff --git a/runtime/interpreter/mterp/x86/op_div_int_2addr.S b/runtime/interpreter/mterp/x86/op_div_int_2addr.S index 04cf1bae6a..d43135f0dd 100644 --- a/runtime/interpreter/mterp/x86/op_div_int_2addr.S +++ b/runtime/interpreter/mterp/x86/op_div_int_2addr.S @@ -1 +1,2 @@ -%include "x86/bindiv2addr.S" {"result":"%eax","special":"$0x80000000"} +%def op_div_int_2addr(): +% bindiv2addr(result="%eax", special="$0x80000000") diff --git a/runtime/interpreter/mterp/x86/op_div_int_lit16.S b/runtime/interpreter/mterp/x86/op_div_int_lit16.S index dd396bb68a..e561eae38e 100644 --- a/runtime/interpreter/mterp/x86/op_div_int_lit16.S +++ b/runtime/interpreter/mterp/x86/op_div_int_lit16.S @@ -1 +1,2 @@ -%include "x86/bindivLit16.S" {"result":"%eax","special":"$0x80000000"} +%def op_div_int_lit16(): +% bindivLit16(result="%eax", special="$0x80000000") diff --git a/runtime/interpreter/mterp/x86/op_div_int_lit8.S b/runtime/interpreter/mterp/x86/op_div_int_lit8.S index 3cbd9d0cf5..5facee247e 100644 --- a/runtime/interpreter/mterp/x86/op_div_int_lit8.S +++ b/runtime/interpreter/mterp/x86/op_div_int_lit8.S @@ -1 +1,2 @@ -%include "x86/bindivLit8.S" {"result":"%eax","special":"$0x80000000"} +%def op_div_int_lit8(): +% bindivLit8(result="%eax", special="$0x80000000") diff --git a/runtime/interpreter/mterp/x86/op_div_long.S b/runtime/interpreter/mterp/x86/op_div_long.S index e56a035f1d..2fdf6ad1bf 100644 --- a/runtime/interpreter/mterp/x86/op_div_long.S +++ b/runtime/interpreter/mterp/x86/op_div_long.S @@ -1,4 +1,4 @@ -%default {"routine":"art_quick_ldiv"} +%def op_div_long(routine="art_quick_ldiv"): /* art_quick_* methods has quick abi, * so use eax, ecx, edx, ebx for args */ diff --git a/runtime/interpreter/mterp/x86/op_div_long_2addr.S b/runtime/interpreter/mterp/x86/op_div_long_2addr.S index 159cc44444..b3d81a4580 100644 --- a/runtime/interpreter/mterp/x86/op_div_long_2addr.S +++ b/runtime/interpreter/mterp/x86/op_div_long_2addr.S @@ -1,4 +1,4 @@ -%default {"routine":"art_quick_ldiv"} +%def op_div_long_2addr(routine="art_quick_ldiv"): /* art_quick_* methods has quick abi, * so use eax, ecx, edx, ebx for args */ diff --git a/runtime/interpreter/mterp/x86/op_double_to_float.S b/runtime/interpreter/mterp/x86/op_double_to_float.S index 5135d60ed7..a52b505368 100644 --- a/runtime/interpreter/mterp/x86/op_double_to_float.S +++ b/runtime/interpreter/mterp/x86/op_double_to_float.S @@ -1 +1,2 @@ -%include "x86/fpcvt.S" {"load":"fldl","store":"fstps"} +%def op_double_to_float(): +% fpcvt(load="fldl", store="fstps") diff --git a/runtime/interpreter/mterp/x86/op_double_to_int.S b/runtime/interpreter/mterp/x86/op_double_to_int.S index 9c4e11cf9e..65c31fbf5e 100644 --- a/runtime/interpreter/mterp/x86/op_double_to_int.S +++ b/runtime/interpreter/mterp/x86/op_double_to_int.S @@ -1 +1,2 @@ -%include "x86/cvtfp_int.S" {"srcdouble":"1","tgtlong":"0"} +%def op_double_to_int(): +% cvtfp_int(srcdouble="1", tgtlong="0") diff --git a/runtime/interpreter/mterp/x86/op_double_to_long.S b/runtime/interpreter/mterp/x86/op_double_to_long.S index fe0eee24d0..1eb74bf539 100644 --- a/runtime/interpreter/mterp/x86/op_double_to_long.S +++ b/runtime/interpreter/mterp/x86/op_double_to_long.S @@ -1 +1,2 @@ -%include "x86/cvtfp_int.S" {"srcdouble":"1","tgtlong":"1"} +%def op_double_to_long(): +% cvtfp_int(srcdouble="1", tgtlong="1") diff --git a/runtime/interpreter/mterp/x86/op_fill_array_data.S b/runtime/interpreter/mterp/x86/op_fill_array_data.S index 5855284901..f121787f62 100644 --- a/runtime/interpreter/mterp/x86/op_fill_array_data.S +++ b/runtime/interpreter/mterp/x86/op_fill_array_data.S @@ -1,3 +1,4 @@ +%def op_fill_array_data(): /* fill-array-data vAA, +BBBBBBBB */ EXPORT_PC movl 2(rPC), %ecx # ecx <- BBBBbbbb diff --git a/runtime/interpreter/mterp/x86/op_filled_new_array.S b/runtime/interpreter/mterp/x86/op_filled_new_array.S index 35b2fe8dfc..8e5bd03978 100644 --- a/runtime/interpreter/mterp/x86/op_filled_new_array.S +++ b/runtime/interpreter/mterp/x86/op_filled_new_array.S @@ -1,4 +1,4 @@ -%default { "helper":"MterpFilledNewArray" } +%def op_filled_new_array(helper="MterpFilledNewArray"): /* * Create a new array with elements filled from registers. * diff --git a/runtime/interpreter/mterp/x86/op_filled_new_array_range.S b/runtime/interpreter/mterp/x86/op_filled_new_array_range.S index 841059e4e2..1667de149a 100644 --- a/runtime/interpreter/mterp/x86/op_filled_new_array_range.S +++ b/runtime/interpreter/mterp/x86/op_filled_new_array_range.S @@ -1 +1,2 @@ -%include "x86/op_filled_new_array.S" { "helper":"MterpFilledNewArrayRange" } +%def op_filled_new_array_range(): +% op_filled_new_array(helper="MterpFilledNewArrayRange") diff --git a/runtime/interpreter/mterp/x86/op_float_to_double.S b/runtime/interpreter/mterp/x86/op_float_to_double.S index 12a3e14caa..152bb00859 100644 --- a/runtime/interpreter/mterp/x86/op_float_to_double.S +++ b/runtime/interpreter/mterp/x86/op_float_to_double.S @@ -1 +1,2 @@ -%include "x86/fpcvt.S" {"load":"flds","store":"fstpl","wide":"1"} +%def op_float_to_double(): +% fpcvt(load="flds", store="fstpl", wide="1") diff --git a/runtime/interpreter/mterp/x86/op_float_to_int.S b/runtime/interpreter/mterp/x86/op_float_to_int.S index ac57388744..1f8e5cc1e5 100644 --- a/runtime/interpreter/mterp/x86/op_float_to_int.S +++ b/runtime/interpreter/mterp/x86/op_float_to_int.S @@ -1 +1,2 @@ -%include "x86/cvtfp_int.S" {"srcdouble":"0","tgtlong":"0"} +%def op_float_to_int(): +% cvtfp_int(srcdouble="0", tgtlong="0") diff --git a/runtime/interpreter/mterp/x86/op_float_to_long.S b/runtime/interpreter/mterp/x86/op_float_to_long.S index be1d9821b3..a0567691c2 100644 --- a/runtime/interpreter/mterp/x86/op_float_to_long.S +++ b/runtime/interpreter/mterp/x86/op_float_to_long.S @@ -1 +1,2 @@ -%include "x86/cvtfp_int.S" {"srcdouble":"0","tgtlong":"1"} +%def op_float_to_long(): +% cvtfp_int(srcdouble="0", tgtlong="1") diff --git a/runtime/interpreter/mterp/x86/op_goto.S b/runtime/interpreter/mterp/x86/op_goto.S index 1827d68eed..b6236fe9a8 100644 --- a/runtime/interpreter/mterp/x86/op_goto.S +++ b/runtime/interpreter/mterp/x86/op_goto.S @@ -1,3 +1,4 @@ +%def op_goto(): /* * Unconditional branch, 8-bit offset. * diff --git a/runtime/interpreter/mterp/x86/op_goto_16.S b/runtime/interpreter/mterp/x86/op_goto_16.S index ea5ea9001f..a8c2bf590d 100644 --- a/runtime/interpreter/mterp/x86/op_goto_16.S +++ b/runtime/interpreter/mterp/x86/op_goto_16.S @@ -1,3 +1,4 @@ +%def op_goto_16(): /* * Unconditional branch, 16-bit offset. * diff --git a/runtime/interpreter/mterp/x86/op_goto_32.S b/runtime/interpreter/mterp/x86/op_goto_32.S index 4becaf34b1..87d0e338e0 100644 --- a/runtime/interpreter/mterp/x86/op_goto_32.S +++ b/runtime/interpreter/mterp/x86/op_goto_32.S @@ -1,3 +1,4 @@ +%def op_goto_32(): /* * Unconditional branch, 32-bit offset. * diff --git a/runtime/interpreter/mterp/x86/op_if_eq.S b/runtime/interpreter/mterp/x86/op_if_eq.S index 5413d98580..4d1f6a54d2 100644 --- a/runtime/interpreter/mterp/x86/op_if_eq.S +++ b/runtime/interpreter/mterp/x86/op_if_eq.S @@ -1 +1,2 @@ -%include "x86/bincmp.S" { "revcmp":"ne" } +%def op_if_eq(): +% bincmp(revcmp="ne") diff --git a/runtime/interpreter/mterp/x86/op_if_eqz.S b/runtime/interpreter/mterp/x86/op_if_eqz.S index 53dc99ef90..12de558550 100644 --- a/runtime/interpreter/mterp/x86/op_if_eqz.S +++ b/runtime/interpreter/mterp/x86/op_if_eqz.S @@ -1 +1,2 @@ -%include "x86/zcmp.S" { "revcmp":"ne" } +%def op_if_eqz(): +% zcmp(revcmp="ne") diff --git a/runtime/interpreter/mterp/x86/op_if_ge.S b/runtime/interpreter/mterp/x86/op_if_ge.S index c2ba3c6d51..684902776f 100644 --- a/runtime/interpreter/mterp/x86/op_if_ge.S +++ b/runtime/interpreter/mterp/x86/op_if_ge.S @@ -1 +1,2 @@ -%include "x86/bincmp.S" { "revcmp":"l" } +%def op_if_ge(): +% bincmp(revcmp="l") diff --git a/runtime/interpreter/mterp/x86/op_if_gez.S b/runtime/interpreter/mterp/x86/op_if_gez.S index cd2c77237d..87bdcbfa32 100644 --- a/runtime/interpreter/mterp/x86/op_if_gez.S +++ b/runtime/interpreter/mterp/x86/op_if_gez.S @@ -1 +1,2 @@ -%include "x86/zcmp.S" { "revcmp":"l" } +%def op_if_gez(): +% zcmp(revcmp="l") diff --git a/runtime/interpreter/mterp/x86/op_if_gt.S b/runtime/interpreter/mterp/x86/op_if_gt.S index 9fe84bb786..4a521006b3 100644 --- a/runtime/interpreter/mterp/x86/op_if_gt.S +++ b/runtime/interpreter/mterp/x86/op_if_gt.S @@ -1 +1,2 @@ -%include "x86/bincmp.S" { "revcmp":"le" } +%def op_if_gt(): +% bincmp(revcmp="le") diff --git a/runtime/interpreter/mterp/x86/op_if_gtz.S b/runtime/interpreter/mterp/x86/op_if_gtz.S index b454ffdb34..a0b2e3a35b 100644 --- a/runtime/interpreter/mterp/x86/op_if_gtz.S +++ b/runtime/interpreter/mterp/x86/op_if_gtz.S @@ -1 +1,2 @@ -%include "x86/zcmp.S" { "revcmp":"le" } +%def op_if_gtz(): +% zcmp(revcmp="le") diff --git a/runtime/interpreter/mterp/x86/op_if_le.S b/runtime/interpreter/mterp/x86/op_if_le.S index 93571a7083..69e94db79f 100644 --- a/runtime/interpreter/mterp/x86/op_if_le.S +++ b/runtime/interpreter/mterp/x86/op_if_le.S @@ -1 +1,2 @@ -%include "x86/bincmp.S" { "revcmp":"g" } +%def op_if_le(): +% bincmp(revcmp="g") diff --git a/runtime/interpreter/mterp/x86/op_if_lez.S b/runtime/interpreter/mterp/x86/op_if_lez.S index 779c77f2be..42e69d969a 100644 --- a/runtime/interpreter/mterp/x86/op_if_lez.S +++ b/runtime/interpreter/mterp/x86/op_if_lez.S @@ -1 +1,2 @@ -%include "x86/zcmp.S" { "revcmp":"g" } +%def op_if_lez(): +% zcmp(revcmp="g") diff --git a/runtime/interpreter/mterp/x86/op_if_lt.S b/runtime/interpreter/mterp/x86/op_if_lt.S index 1fb1521054..052aabe1e7 100644 --- a/runtime/interpreter/mterp/x86/op_if_lt.S +++ b/runtime/interpreter/mterp/x86/op_if_lt.S @@ -1 +1,2 @@ -%include "x86/bincmp.S" { "revcmp":"ge" } +%def op_if_lt(): +% bincmp(revcmp="ge") diff --git a/runtime/interpreter/mterp/x86/op_if_ltz.S b/runtime/interpreter/mterp/x86/op_if_ltz.S index 155c356e4c..8e13e48c2a 100644 --- a/runtime/interpreter/mterp/x86/op_if_ltz.S +++ b/runtime/interpreter/mterp/x86/op_if_ltz.S @@ -1 +1,2 @@ -%include "x86/zcmp.S" { "revcmp":"ge" } +%def op_if_ltz(): +% zcmp(revcmp="ge") diff --git a/runtime/interpreter/mterp/x86/op_if_ne.S b/runtime/interpreter/mterp/x86/op_if_ne.S index 7e1b065fc0..2cfd8a9a1e 100644 --- a/runtime/interpreter/mterp/x86/op_if_ne.S +++ b/runtime/interpreter/mterp/x86/op_if_ne.S @@ -1 +1,2 @@ -%include "x86/bincmp.S" { "revcmp":"e" } +%def op_if_ne(): +% bincmp(revcmp="e") diff --git a/runtime/interpreter/mterp/x86/op_if_nez.S b/runtime/interpreter/mterp/x86/op_if_nez.S index 8951f5b19f..261a173a38 100644 --- a/runtime/interpreter/mterp/x86/op_if_nez.S +++ b/runtime/interpreter/mterp/x86/op_if_nez.S @@ -1 +1,2 @@ -%include "x86/zcmp.S" { "revcmp":"e" } +%def op_if_nez(): +% zcmp(revcmp="e") diff --git a/runtime/interpreter/mterp/x86/op_iget.S b/runtime/interpreter/mterp/x86/op_iget.S index d85d54c515..d09edc0a17 100644 --- a/runtime/interpreter/mterp/x86/op_iget.S +++ b/runtime/interpreter/mterp/x86/op_iget.S @@ -1,2 +1,2 @@ -%default { "is_object":"0", "helper":"MterpIGetU32"} -%include "x86/field.S" { } +%def op_iget(is_object="0", helper="MterpIGetU32"): +% field(helper=helper) diff --git a/runtime/interpreter/mterp/x86/op_iget_boolean.S b/runtime/interpreter/mterp/x86/op_iget_boolean.S index ddccc41cda..cb8edeec77 100644 --- a/runtime/interpreter/mterp/x86/op_iget_boolean.S +++ b/runtime/interpreter/mterp/x86/op_iget_boolean.S @@ -1 +1,2 @@ -%include "x86/op_iget.S" { "helper":"MterpIGetU8" } +%def op_iget_boolean(): +% op_iget(helper="MterpIGetU8") diff --git a/runtime/interpreter/mterp/x86/op_iget_boolean_quick.S b/runtime/interpreter/mterp/x86/op_iget_boolean_quick.S index 02b0c16cf2..4e1676844b 100644 --- a/runtime/interpreter/mterp/x86/op_iget_boolean_quick.S +++ b/runtime/interpreter/mterp/x86/op_iget_boolean_quick.S @@ -1 +1,2 @@ -%include "x86/op_iget_quick.S" { "load":"movsbl" } +%def op_iget_boolean_quick(): +% op_iget_quick(load="movsbl") diff --git a/runtime/interpreter/mterp/x86/op_iget_byte.S b/runtime/interpreter/mterp/x86/op_iget_byte.S index cd46d3de08..2b87fb16b5 100644 --- a/runtime/interpreter/mterp/x86/op_iget_byte.S +++ b/runtime/interpreter/mterp/x86/op_iget_byte.S @@ -1 +1,2 @@ -%include "x86/op_iget.S" { "helper":"MterpIGetI8" } +%def op_iget_byte(): +% op_iget(helper="MterpIGetI8") diff --git a/runtime/interpreter/mterp/x86/op_iget_byte_quick.S b/runtime/interpreter/mterp/x86/op_iget_byte_quick.S index 02b0c16cf2..b92936c28d 100644 --- a/runtime/interpreter/mterp/x86/op_iget_byte_quick.S +++ b/runtime/interpreter/mterp/x86/op_iget_byte_quick.S @@ -1 +1,2 @@ -%include "x86/op_iget_quick.S" { "load":"movsbl" } +%def op_iget_byte_quick(): +% op_iget_quick(load="movsbl") diff --git a/runtime/interpreter/mterp/x86/op_iget_char.S b/runtime/interpreter/mterp/x86/op_iget_char.S index 99697349ae..001bd03e2b 100644 --- a/runtime/interpreter/mterp/x86/op_iget_char.S +++ b/runtime/interpreter/mterp/x86/op_iget_char.S @@ -1 +1,2 @@ -%include "x86/op_iget.S" { "helper":"MterpIGetU16" } +%def op_iget_char(): +% op_iget(helper="MterpIGetU16") diff --git a/runtime/interpreter/mterp/x86/op_iget_char_quick.S b/runtime/interpreter/mterp/x86/op_iget_char_quick.S index a5d971278d..d6f836b28e 100644 --- a/runtime/interpreter/mterp/x86/op_iget_char_quick.S +++ b/runtime/interpreter/mterp/x86/op_iget_char_quick.S @@ -1 +1,2 @@ -%include "x86/op_iget_quick.S" { "load":"movzwl" } +%def op_iget_char_quick(): +% op_iget_quick(load="movzwl") diff --git a/runtime/interpreter/mterp/x86/op_iget_object.S b/runtime/interpreter/mterp/x86/op_iget_object.S index 3d421fcf7f..4e5f769547 100644 --- a/runtime/interpreter/mterp/x86/op_iget_object.S +++ b/runtime/interpreter/mterp/x86/op_iget_object.S @@ -1 +1,2 @@ -%include "x86/op_iget.S" { "is_object":"1", "helper":"MterpIGetObj" } +%def op_iget_object(): +% op_iget(is_object="1", helper="MterpIGetObj") diff --git a/runtime/interpreter/mterp/x86/op_iget_object_quick.S b/runtime/interpreter/mterp/x86/op_iget_object_quick.S index b1551a0179..66340e91d2 100644 --- a/runtime/interpreter/mterp/x86/op_iget_object_quick.S +++ b/runtime/interpreter/mterp/x86/op_iget_object_quick.S @@ -1,3 +1,4 @@ +%def op_iget_object_quick(): /* For: iget-object-quick */ /* op vA, vB, offset@CCCC */ movzbl rINSTbl, %ecx # ecx <- BA diff --git a/runtime/interpreter/mterp/x86/op_iget_quick.S b/runtime/interpreter/mterp/x86/op_iget_quick.S index 1b7440fc9a..8ca2c86f3f 100644 --- a/runtime/interpreter/mterp/x86/op_iget_quick.S +++ b/runtime/interpreter/mterp/x86/op_iget_quick.S @@ -1,4 +1,4 @@ -%default { "load":"movl"} +%def op_iget_quick(load="movl"): /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ /* op vA, vB, offset@CCCC */ movzbl rINSTbl, %ecx # ecx <- BA diff --git a/runtime/interpreter/mterp/x86/op_iget_short.S b/runtime/interpreter/mterp/x86/op_iget_short.S index c7477f5db3..a62c4d998f 100644 --- a/runtime/interpreter/mterp/x86/op_iget_short.S +++ b/runtime/interpreter/mterp/x86/op_iget_short.S @@ -1 +1,2 @@ -%include "x86/op_iget.S" { "helper":"MterpIGetI16" } +%def op_iget_short(): +% op_iget(helper="MterpIGetI16") diff --git a/runtime/interpreter/mterp/x86/op_iget_short_quick.S b/runtime/interpreter/mterp/x86/op_iget_short_quick.S index 2c3aeb67eb..f5e48d621a 100644 --- a/runtime/interpreter/mterp/x86/op_iget_short_quick.S +++ b/runtime/interpreter/mterp/x86/op_iget_short_quick.S @@ -1 +1,2 @@ -%include "x86/op_iget_quick.S" { "load":"movswl" } +%def op_iget_short_quick(): +% op_iget_quick(load="movswl") diff --git a/runtime/interpreter/mterp/x86/op_iget_wide.S b/runtime/interpreter/mterp/x86/op_iget_wide.S index 741a64e4cb..9643cc3403 100644 --- a/runtime/interpreter/mterp/x86/op_iget_wide.S +++ b/runtime/interpreter/mterp/x86/op_iget_wide.S @@ -1 +1,2 @@ -%include "x86/op_iget.S" { "helper":"MterpIGetU64" } +%def op_iget_wide(): +% op_iget(helper="MterpIGetU64") diff --git a/runtime/interpreter/mterp/x86/op_iget_wide_quick.S b/runtime/interpreter/mterp/x86/op_iget_wide_quick.S index 7ce74cc71b..c1a13269f3 100644 --- a/runtime/interpreter/mterp/x86/op_iget_wide_quick.S +++ b/runtime/interpreter/mterp/x86/op_iget_wide_quick.S @@ -1,3 +1,4 @@ +%def op_iget_wide_quick(): /* iget-wide-quick vA, vB, offset@CCCC */ movzbl rINSTbl, %ecx # ecx <- BA sarl $$4, %ecx # ecx <- B diff --git a/runtime/interpreter/mterp/x86/op_instance_of.S b/runtime/interpreter/mterp/x86/op_instance_of.S index e6fe5b2cec..ae1afae855 100644 --- a/runtime/interpreter/mterp/x86/op_instance_of.S +++ b/runtime/interpreter/mterp/x86/op_instance_of.S @@ -1,3 +1,4 @@ +%def op_instance_of(): /* * Check to see if an object reference is an instance of a class. * diff --git a/runtime/interpreter/mterp/x86/op_int_to_byte.S b/runtime/interpreter/mterp/x86/op_int_to_byte.S index b4e8d22c98..80e4d5c310 100644 --- a/runtime/interpreter/mterp/x86/op_int_to_byte.S +++ b/runtime/interpreter/mterp/x86/op_int_to_byte.S @@ -1 +1,2 @@ -%include "x86/unop.S" {"instr":"movsbl %al, %eax"} +%def op_int_to_byte(): +% unop(instr="movsbl %al, %eax") diff --git a/runtime/interpreter/mterp/x86/op_int_to_char.S b/runtime/interpreter/mterp/x86/op_int_to_char.S index 4608971469..83e9868ef3 100644 --- a/runtime/interpreter/mterp/x86/op_int_to_char.S +++ b/runtime/interpreter/mterp/x86/op_int_to_char.S @@ -1 +1,2 @@ -%include "x86/unop.S" {"instr":"movzwl %ax,%eax"} +%def op_int_to_char(): +% unop(instr="movzwl %ax,%eax") diff --git a/runtime/interpreter/mterp/x86/op_int_to_double.S b/runtime/interpreter/mterp/x86/op_int_to_double.S index 3e9921eb8f..e304d8eaf5 100644 --- a/runtime/interpreter/mterp/x86/op_int_to_double.S +++ b/runtime/interpreter/mterp/x86/op_int_to_double.S @@ -1 +1,2 @@ -%include "x86/fpcvt.S" {"load":"fildl","store":"fstpl","wide":"1"} +%def op_int_to_double(): +% fpcvt(load="fildl", store="fstpl", wide="1") diff --git a/runtime/interpreter/mterp/x86/op_int_to_float.S b/runtime/interpreter/mterp/x86/op_int_to_float.S index 849540da09..fe00097c69 100644 --- a/runtime/interpreter/mterp/x86/op_int_to_float.S +++ b/runtime/interpreter/mterp/x86/op_int_to_float.S @@ -1 +1,2 @@ -%include "x86/fpcvt.S" {"load":"fildl","store":"fstps"} +%def op_int_to_float(): +% fpcvt(load="fildl", store="fstps") diff --git a/runtime/interpreter/mterp/x86/op_int_to_long.S b/runtime/interpreter/mterp/x86/op_int_to_long.S index 6f9ea269f4..849197382f 100644 --- a/runtime/interpreter/mterp/x86/op_int_to_long.S +++ b/runtime/interpreter/mterp/x86/op_int_to_long.S @@ -1,3 +1,4 @@ +%def op_int_to_long(): /* int to long vA, vB */ movzbl rINSTbl, %eax # eax <- +A sarl $$4, %eax # eax <- B diff --git a/runtime/interpreter/mterp/x86/op_int_to_short.S b/runtime/interpreter/mterp/x86/op_int_to_short.S index 90d0ae65b1..e4db90b801 100644 --- a/runtime/interpreter/mterp/x86/op_int_to_short.S +++ b/runtime/interpreter/mterp/x86/op_int_to_short.S @@ -1 +1,2 @@ -%include "x86/unop.S" {"instr":"movswl %ax, %eax"} +%def op_int_to_short(): +% unop(instr="movswl %ax, %eax") diff --git a/runtime/interpreter/mterp/x86/op_invoke_custom.S b/runtime/interpreter/mterp/x86/op_invoke_custom.S index eddd5b33a3..4bba9ee524 100644 --- a/runtime/interpreter/mterp/x86/op_invoke_custom.S +++ b/runtime/interpreter/mterp/x86/op_invoke_custom.S @@ -1 +1,2 @@ -%include "x86/invoke.S" { "helper":"MterpInvokeCustom" } +%def op_invoke_custom(): +% invoke(helper="MterpInvokeCustom") diff --git a/runtime/interpreter/mterp/x86/op_invoke_custom_range.S b/runtime/interpreter/mterp/x86/op_invoke_custom_range.S index 1a4e884166..57e61af1fa 100644 --- a/runtime/interpreter/mterp/x86/op_invoke_custom_range.S +++ b/runtime/interpreter/mterp/x86/op_invoke_custom_range.S @@ -1 +1,2 @@ -%include "x86/invoke.S" { "helper":"MterpInvokeCustomRange" } +%def op_invoke_custom_range(): +% invoke(helper="MterpInvokeCustomRange") diff --git a/runtime/interpreter/mterp/x86/op_invoke_direct.S b/runtime/interpreter/mterp/x86/op_invoke_direct.S index 76fb9a6786..d3139cf39b 100644 --- a/runtime/interpreter/mterp/x86/op_invoke_direct.S +++ b/runtime/interpreter/mterp/x86/op_invoke_direct.S @@ -1 +1,2 @@ -%include "x86/invoke.S" { "helper":"MterpInvokeDirect" } +%def op_invoke_direct(): +% invoke(helper="MterpInvokeDirect") diff --git a/runtime/interpreter/mterp/x86/op_invoke_direct_range.S b/runtime/interpreter/mterp/x86/op_invoke_direct_range.S index a6ab6049f5..b4a161f48b 100644 --- a/runtime/interpreter/mterp/x86/op_invoke_direct_range.S +++ b/runtime/interpreter/mterp/x86/op_invoke_direct_range.S @@ -1 +1,2 @@ -%include "x86/invoke.S" { "helper":"MterpInvokeDirectRange" } +%def op_invoke_direct_range(): +% invoke(helper="MterpInvokeDirectRange") diff --git a/runtime/interpreter/mterp/x86/op_invoke_interface.S b/runtime/interpreter/mterp/x86/op_invoke_interface.S index 91c24f5db6..559b9768d9 100644 --- a/runtime/interpreter/mterp/x86/op_invoke_interface.S +++ b/runtime/interpreter/mterp/x86/op_invoke_interface.S @@ -1,4 +1,5 @@ -%include "x86/invoke.S" { "helper":"MterpInvokeInterface" } +%def op_invoke_interface(): +% invoke(helper="MterpInvokeInterface") /* * Handle an interface method call. * diff --git a/runtime/interpreter/mterp/x86/op_invoke_interface_range.S b/runtime/interpreter/mterp/x86/op_invoke_interface_range.S index e478beb596..2989115377 100644 --- a/runtime/interpreter/mterp/x86/op_invoke_interface_range.S +++ b/runtime/interpreter/mterp/x86/op_invoke_interface_range.S @@ -1 +1,2 @@ -%include "x86/invoke.S" { "helper":"MterpInvokeInterfaceRange" } +%def op_invoke_interface_range(): +% invoke(helper="MterpInvokeInterfaceRange") diff --git a/runtime/interpreter/mterp/x86/op_invoke_polymorphic.S b/runtime/interpreter/mterp/x86/op_invoke_polymorphic.S index 3907689476..ce61f5aa0e 100644 --- a/runtime/interpreter/mterp/x86/op_invoke_polymorphic.S +++ b/runtime/interpreter/mterp/x86/op_invoke_polymorphic.S @@ -1 +1,2 @@ -%include "x86/invoke_polymorphic.S" { "helper":"MterpInvokePolymorphic" } +%def op_invoke_polymorphic(): +% invoke_polymorphic(helper="MterpInvokePolymorphic") diff --git a/runtime/interpreter/mterp/x86/op_invoke_polymorphic_range.S b/runtime/interpreter/mterp/x86/op_invoke_polymorphic_range.S index 59a823076d..16731bdb40 100644 --- a/runtime/interpreter/mterp/x86/op_invoke_polymorphic_range.S +++ b/runtime/interpreter/mterp/x86/op_invoke_polymorphic_range.S @@ -1 +1,2 @@ -%include "x86/invoke_polymorphic.S" { "helper":"MterpInvokePolymorphicRange" } +%def op_invoke_polymorphic_range(): +% invoke_polymorphic(helper="MterpInvokePolymorphicRange") diff --git a/runtime/interpreter/mterp/x86/op_invoke_static.S b/runtime/interpreter/mterp/x86/op_invoke_static.S index b4c1236f7a..3e38d36a27 100644 --- a/runtime/interpreter/mterp/x86/op_invoke_static.S +++ b/runtime/interpreter/mterp/x86/op_invoke_static.S @@ -1,2 +1,3 @@ -%include "x86/invoke.S" { "helper":"MterpInvokeStatic" } +%def op_invoke_static(): +% invoke(helper="MterpInvokeStatic") diff --git a/runtime/interpreter/mterp/x86/op_invoke_static_range.S b/runtime/interpreter/mterp/x86/op_invoke_static_range.S index 3dc8a26856..e0a546c92b 100644 --- a/runtime/interpreter/mterp/x86/op_invoke_static_range.S +++ b/runtime/interpreter/mterp/x86/op_invoke_static_range.S @@ -1 +1,2 @@ -%include "x86/invoke.S" { "helper":"MterpInvokeStaticRange" } +%def op_invoke_static_range(): +% invoke(helper="MterpInvokeStaticRange") diff --git a/runtime/interpreter/mterp/x86/op_invoke_super.S b/runtime/interpreter/mterp/x86/op_invoke_super.S index be20edd07c..5b2055010e 100644 --- a/runtime/interpreter/mterp/x86/op_invoke_super.S +++ b/runtime/interpreter/mterp/x86/op_invoke_super.S @@ -1,4 +1,5 @@ -%include "x86/invoke.S" { "helper":"MterpInvokeSuper" } +%def op_invoke_super(): +% invoke(helper="MterpInvokeSuper") /* * Handle a "super" method call. * diff --git a/runtime/interpreter/mterp/x86/op_invoke_super_range.S b/runtime/interpreter/mterp/x86/op_invoke_super_range.S index f36bf72bcf..caeafaa13c 100644 --- a/runtime/interpreter/mterp/x86/op_invoke_super_range.S +++ b/runtime/interpreter/mterp/x86/op_invoke_super_range.S @@ -1 +1,2 @@ -%include "x86/invoke.S" { "helper":"MterpInvokeSuperRange" } +%def op_invoke_super_range(): +% invoke(helper="MterpInvokeSuperRange") diff --git a/runtime/interpreter/mterp/x86/op_invoke_virtual.S b/runtime/interpreter/mterp/x86/op_invoke_virtual.S index 7e9c456a95..e27eeedacc 100644 --- a/runtime/interpreter/mterp/x86/op_invoke_virtual.S +++ b/runtime/interpreter/mterp/x86/op_invoke_virtual.S @@ -1,4 +1,5 @@ -%include "x86/invoke.S" { "helper":"MterpInvokeVirtual" } +%def op_invoke_virtual(): +% invoke(helper="MterpInvokeVirtual") /* * Handle a virtual method call. * diff --git a/runtime/interpreter/mterp/x86/op_invoke_virtual_quick.S b/runtime/interpreter/mterp/x86/op_invoke_virtual_quick.S index 2dc9ab6298..ea72c171ec 100644 --- a/runtime/interpreter/mterp/x86/op_invoke_virtual_quick.S +++ b/runtime/interpreter/mterp/x86/op_invoke_virtual_quick.S @@ -1 +1,2 @@ -%include "x86/invoke.S" { "helper":"MterpInvokeVirtualQuick" } +%def op_invoke_virtual_quick(): +% invoke(helper="MterpInvokeVirtualQuick") diff --git a/runtime/interpreter/mterp/x86/op_invoke_virtual_range.S b/runtime/interpreter/mterp/x86/op_invoke_virtual_range.S index d1d20d29ac..baa0779593 100644 --- a/runtime/interpreter/mterp/x86/op_invoke_virtual_range.S +++ b/runtime/interpreter/mterp/x86/op_invoke_virtual_range.S @@ -1 +1,2 @@ -%include "x86/invoke.S" { "helper":"MterpInvokeVirtualRange" } +%def op_invoke_virtual_range(): +% invoke(helper="MterpInvokeVirtualRange") diff --git a/runtime/interpreter/mterp/x86/op_invoke_virtual_range_quick.S b/runtime/interpreter/mterp/x86/op_invoke_virtual_range_quick.S index 21bfc55b73..1d961a0781 100644 --- a/runtime/interpreter/mterp/x86/op_invoke_virtual_range_quick.S +++ b/runtime/interpreter/mterp/x86/op_invoke_virtual_range_quick.S @@ -1 +1,2 @@ -%include "x86/invoke.S" { "helper":"MterpInvokeVirtualQuickRange" } +%def op_invoke_virtual_range_quick(): +% invoke(helper="MterpInvokeVirtualQuickRange") diff --git a/runtime/interpreter/mterp/x86/op_iput.S b/runtime/interpreter/mterp/x86/op_iput.S index 3628ffdb56..e5351baf55 100644 --- a/runtime/interpreter/mterp/x86/op_iput.S +++ b/runtime/interpreter/mterp/x86/op_iput.S @@ -1,2 +1,2 @@ -%default { "is_object":"0", "helper":"MterpIPutU32" } -%include "x86/field.S" { } +%def op_iput(is_object="0", helper="MterpIPutU32"): +% field(helper=helper) diff --git a/runtime/interpreter/mterp/x86/op_iput_boolean.S b/runtime/interpreter/mterp/x86/op_iput_boolean.S index fdd530374e..9eb849877b 100644 --- a/runtime/interpreter/mterp/x86/op_iput_boolean.S +++ b/runtime/interpreter/mterp/x86/op_iput_boolean.S @@ -1 +1,2 @@ -%include "x86/op_iput.S" { "helper":"MterpIPutU8" } +%def op_iput_boolean(): +% op_iput(helper="MterpIPutU8") diff --git a/runtime/interpreter/mterp/x86/op_iput_boolean_quick.S b/runtime/interpreter/mterp/x86/op_iput_boolean_quick.S index 93865de169..c304c76b51 100644 --- a/runtime/interpreter/mterp/x86/op_iput_boolean_quick.S +++ b/runtime/interpreter/mterp/x86/op_iput_boolean_quick.S @@ -1 +1,2 @@ -%include "x86/op_iput_quick.S" { "reg":"rINSTbl", "store":"movb" } +%def op_iput_boolean_quick(): +% op_iput_quick(reg="rINSTbl", store="movb") diff --git a/runtime/interpreter/mterp/x86/op_iput_byte.S b/runtime/interpreter/mterp/x86/op_iput_byte.S index b81850c538..4b74f9fb0e 100644 --- a/runtime/interpreter/mterp/x86/op_iput_byte.S +++ b/runtime/interpreter/mterp/x86/op_iput_byte.S @@ -1 +1,2 @@ -%include "x86/op_iput.S" { "helper":"MterpIPutI8" } +%def op_iput_byte(): +% op_iput(helper="MterpIPutI8") diff --git a/runtime/interpreter/mterp/x86/op_iput_byte_quick.S b/runtime/interpreter/mterp/x86/op_iput_byte_quick.S index 93865de169..dac18e63cc 100644 --- a/runtime/interpreter/mterp/x86/op_iput_byte_quick.S +++ b/runtime/interpreter/mterp/x86/op_iput_byte_quick.S @@ -1 +1,2 @@ -%include "x86/op_iput_quick.S" { "reg":"rINSTbl", "store":"movb" } +%def op_iput_byte_quick(): +% op_iput_quick(reg="rINSTbl", store="movb") diff --git a/runtime/interpreter/mterp/x86/op_iput_char.S b/runtime/interpreter/mterp/x86/op_iput_char.S index dde385371e..64a249fc12 100644 --- a/runtime/interpreter/mterp/x86/op_iput_char.S +++ b/runtime/interpreter/mterp/x86/op_iput_char.S @@ -1 +1,2 @@ -%include "x86/op_iput.S" { "helper":"MterpIPutU16" } +%def op_iput_char(): +% op_iput(helper="MterpIPutU16") diff --git a/runtime/interpreter/mterp/x86/op_iput_char_quick.S b/runtime/interpreter/mterp/x86/op_iput_char_quick.S index 4ec80290c6..21a25812b1 100644 --- a/runtime/interpreter/mterp/x86/op_iput_char_quick.S +++ b/runtime/interpreter/mterp/x86/op_iput_char_quick.S @@ -1 +1,2 @@ -%include "x86/op_iput_quick.S" { "reg":"rINSTw", "store":"movw" } +%def op_iput_char_quick(): +% op_iput_quick(reg="rINSTw", store="movw") diff --git a/runtime/interpreter/mterp/x86/op_iput_object.S b/runtime/interpreter/mterp/x86/op_iput_object.S index a124b7ed41..131edd5dbd 100644 --- a/runtime/interpreter/mterp/x86/op_iput_object.S +++ b/runtime/interpreter/mterp/x86/op_iput_object.S @@ -1 +1,2 @@ -%include "x86/op_iput.S" { "is_object":"1", "helper":"MterpIPutObj" } +%def op_iput_object(): +% op_iput(is_object="1", helper="MterpIPutObj") diff --git a/runtime/interpreter/mterp/x86/op_iput_object_quick.S b/runtime/interpreter/mterp/x86/op_iput_object_quick.S index cb779295b7..6b6fb2d553 100644 --- a/runtime/interpreter/mterp/x86/op_iput_object_quick.S +++ b/runtime/interpreter/mterp/x86/op_iput_object_quick.S @@ -1,3 +1,4 @@ +%def op_iput_object_quick(): EXPORT_PC leal OFF_FP_SHADOWFRAME(rFP), %eax movl %eax, OUT_ARG0(%esp) diff --git a/runtime/interpreter/mterp/x86/op_iput_quick.S b/runtime/interpreter/mterp/x86/op_iput_quick.S index b67cee0859..5198cfe5dc 100644 --- a/runtime/interpreter/mterp/x86/op_iput_quick.S +++ b/runtime/interpreter/mterp/x86/op_iput_quick.S @@ -1,4 +1,4 @@ -%default { "reg":"rINST", "store":"movl" } +%def op_iput_quick(reg="rINST", store="movl"): /* For: iput-quick, iput-object-quick */ /* op vA, vB, offset@CCCC */ movzbl rINSTbl, %ecx # ecx <- BA diff --git a/runtime/interpreter/mterp/x86/op_iput_short.S b/runtime/interpreter/mterp/x86/op_iput_short.S index 130e875bb2..e631a3b259 100644 --- a/runtime/interpreter/mterp/x86/op_iput_short.S +++ b/runtime/interpreter/mterp/x86/op_iput_short.S @@ -1 +1,2 @@ -%include "x86/op_iput.S" { "helper":"MterpIPutI16" } +%def op_iput_short(): +% op_iput(helper="MterpIPutI16") diff --git a/runtime/interpreter/mterp/x86/op_iput_short_quick.S b/runtime/interpreter/mterp/x86/op_iput_short_quick.S index 4ec80290c6..5eb28d6922 100644 --- a/runtime/interpreter/mterp/x86/op_iput_short_quick.S +++ b/runtime/interpreter/mterp/x86/op_iput_short_quick.S @@ -1 +1,2 @@ -%include "x86/op_iput_quick.S" { "reg":"rINSTw", "store":"movw" } +%def op_iput_short_quick(): +% op_iput_quick(reg="rINSTw", store="movw") diff --git a/runtime/interpreter/mterp/x86/op_iput_wide.S b/runtime/interpreter/mterp/x86/op_iput_wide.S index 2820ede182..2f34fd39f9 100644 --- a/runtime/interpreter/mterp/x86/op_iput_wide.S +++ b/runtime/interpreter/mterp/x86/op_iput_wide.S @@ -1 +1,2 @@ -%include "x86/op_iput.S" { "helper":"MterpIPutU64" } +%def op_iput_wide(): +% op_iput(helper="MterpIPutU64") diff --git a/runtime/interpreter/mterp/x86/op_iput_wide_quick.S b/runtime/interpreter/mterp/x86/op_iput_wide_quick.S index 17de6f8502..6e1feefffc 100644 --- a/runtime/interpreter/mterp/x86/op_iput_wide_quick.S +++ b/runtime/interpreter/mterp/x86/op_iput_wide_quick.S @@ -1,3 +1,4 @@ +%def op_iput_wide_quick(): /* iput-wide-quick vA, vB, offset@CCCC */ movzbl rINSTbl, %ecx # ecx<- BA sarl $$4, %ecx # ecx<- B diff --git a/runtime/interpreter/mterp/x86/op_long_to_double.S b/runtime/interpreter/mterp/x86/op_long_to_double.S index 2c7f905259..858cb2e6b5 100644 --- a/runtime/interpreter/mterp/x86/op_long_to_double.S +++ b/runtime/interpreter/mterp/x86/op_long_to_double.S @@ -1 +1,2 @@ -%include "x86/fpcvt.S" {"load":"fildll","store":"fstpl","wide":"1"} +%def op_long_to_double(): +% fpcvt(load="fildll", store="fstpl", wide="1") diff --git a/runtime/interpreter/mterp/x86/op_long_to_float.S b/runtime/interpreter/mterp/x86/op_long_to_float.S index e500e39d46..b26085af31 100644 --- a/runtime/interpreter/mterp/x86/op_long_to_float.S +++ b/runtime/interpreter/mterp/x86/op_long_to_float.S @@ -1 +1,2 @@ -%include "x86/fpcvt.S" {"load":"fildll","store":"fstps"} +%def op_long_to_float(): +% fpcvt(load="fildll", store="fstps") diff --git a/runtime/interpreter/mterp/x86/op_long_to_int.S b/runtime/interpreter/mterp/x86/op_long_to_int.S index 1c39b96d5c..eacb8f59ec 100644 --- a/runtime/interpreter/mterp/x86/op_long_to_int.S +++ b/runtime/interpreter/mterp/x86/op_long_to_int.S @@ -1,2 +1,3 @@ +%def op_long_to_int(): /* we ignore the high word, making this equivalent to a 32-bit reg move */ -%include "x86/op_move.S" +% op_move() diff --git a/runtime/interpreter/mterp/x86/op_monitor_enter.S b/runtime/interpreter/mterp/x86/op_monitor_enter.S index b35c68488a..d28ab4c307 100644 --- a/runtime/interpreter/mterp/x86/op_monitor_enter.S +++ b/runtime/interpreter/mterp/x86/op_monitor_enter.S @@ -1,3 +1,4 @@ +%def op_monitor_enter(): /* * Synchronize on an object. */ diff --git a/runtime/interpreter/mterp/x86/op_monitor_exit.S b/runtime/interpreter/mterp/x86/op_monitor_exit.S index 2d17d5e7c5..63a8287519 100644 --- a/runtime/interpreter/mterp/x86/op_monitor_exit.S +++ b/runtime/interpreter/mterp/x86/op_monitor_exit.S @@ -1,3 +1,4 @@ +%def op_monitor_exit(): /* * Unlock an object. * diff --git a/runtime/interpreter/mterp/x86/op_move.S b/runtime/interpreter/mterp/x86/op_move.S index ea173b97d6..e02375596a 100644 --- a/runtime/interpreter/mterp/x86/op_move.S +++ b/runtime/interpreter/mterp/x86/op_move.S @@ -1,4 +1,4 @@ -%default { "is_object":"0" } +%def op_move(is_object="0"): /* for move, move-object, long-to-int */ /* op vA, vB */ movzbl rINSTbl, %eax # eax <- BA diff --git a/runtime/interpreter/mterp/x86/op_move_16.S b/runtime/interpreter/mterp/x86/op_move_16.S index 454deb5d08..0b4f8396f4 100644 --- a/runtime/interpreter/mterp/x86/op_move_16.S +++ b/runtime/interpreter/mterp/x86/op_move_16.S @@ -1,4 +1,4 @@ -%default { "is_object":"0" } +%def op_move_16(is_object="0"): /* for: move/16, move-object/16 */ /* op vAAAA, vBBBB */ movzwl 4(rPC), %ecx # ecx <- BBBB diff --git a/runtime/interpreter/mterp/x86/op_move_exception.S b/runtime/interpreter/mterp/x86/op_move_exception.S index d8dc74fdac..cadce40350 100644 --- a/runtime/interpreter/mterp/x86/op_move_exception.S +++ b/runtime/interpreter/mterp/x86/op_move_exception.S @@ -1,3 +1,4 @@ +%def op_move_exception(): /* move-exception vAA */ movl rSELF, %ecx movl THREAD_EXCEPTION_OFFSET(%ecx), %eax diff --git a/runtime/interpreter/mterp/x86/op_move_from16.S b/runtime/interpreter/mterp/x86/op_move_from16.S index e86985536e..b8a9c8bceb 100644 --- a/runtime/interpreter/mterp/x86/op_move_from16.S +++ b/runtime/interpreter/mterp/x86/op_move_from16.S @@ -1,4 +1,4 @@ -%default { "is_object":"0" } +%def op_move_from16(is_object="0"): /* for: move/from16, move-object/from16 */ /* op vAA, vBBBB */ movzx rINSTbl, %eax # eax <- AA diff --git a/runtime/interpreter/mterp/x86/op_move_object.S b/runtime/interpreter/mterp/x86/op_move_object.S index a6a7c90195..dbb4d59710 100644 --- a/runtime/interpreter/mterp/x86/op_move_object.S +++ b/runtime/interpreter/mterp/x86/op_move_object.S @@ -1 +1,2 @@ -%include "x86/op_move.S" {"is_object":"1"} +%def op_move_object(): +% op_move(is_object="1") diff --git a/runtime/interpreter/mterp/x86/op_move_object_16.S b/runtime/interpreter/mterp/x86/op_move_object_16.S index e0c8527a29..40120379d5 100644 --- a/runtime/interpreter/mterp/x86/op_move_object_16.S +++ b/runtime/interpreter/mterp/x86/op_move_object_16.S @@ -1 +1,2 @@ -%include "x86/op_move_16.S" {"is_object":"1"} +%def op_move_object_16(): +% op_move_16(is_object="1") diff --git a/runtime/interpreter/mterp/x86/op_move_object_from16.S b/runtime/interpreter/mterp/x86/op_move_object_from16.S index e623820470..c82698e81e 100644 --- a/runtime/interpreter/mterp/x86/op_move_object_from16.S +++ b/runtime/interpreter/mterp/x86/op_move_object_from16.S @@ -1 +1,2 @@ -%include "x86/op_move_from16.S" {"is_object":"1"} +%def op_move_object_from16(): +% op_move_from16(is_object="1") diff --git a/runtime/interpreter/mterp/x86/op_move_result.S b/runtime/interpreter/mterp/x86/op_move_result.S index f6f2129f66..c287faadf5 100644 --- a/runtime/interpreter/mterp/x86/op_move_result.S +++ b/runtime/interpreter/mterp/x86/op_move_result.S @@ -1,4 +1,4 @@ -%default { "is_object":"0" } +%def op_move_result(is_object="0"): /* for: move-result, move-result-object */ /* op vAA */ movl OFF_FP_RESULT_REGISTER(rFP), %eax # get pointer to result JType. diff --git a/runtime/interpreter/mterp/x86/op_move_result_object.S b/runtime/interpreter/mterp/x86/op_move_result_object.S index cbf5e1db60..87aea2646a 100644 --- a/runtime/interpreter/mterp/x86/op_move_result_object.S +++ b/runtime/interpreter/mterp/x86/op_move_result_object.S @@ -1 +1,2 @@ -%include "x86/op_move_result.S" {"is_object":"1"} +%def op_move_result_object(): +% op_move_result(is_object="1") diff --git a/runtime/interpreter/mterp/x86/op_move_result_wide.S b/runtime/interpreter/mterp/x86/op_move_result_wide.S index 7818cceaf9..68b1d803b0 100644 --- a/runtime/interpreter/mterp/x86/op_move_result_wide.S +++ b/runtime/interpreter/mterp/x86/op_move_result_wide.S @@ -1,3 +1,4 @@ +%def op_move_result_wide(): /* move-result-wide vAA */ movl OFF_FP_RESULT_REGISTER(rFP), %eax # get pointer to result JType. movl 4(%eax), %ecx # Get high diff --git a/runtime/interpreter/mterp/x86/op_move_wide.S b/runtime/interpreter/mterp/x86/op_move_wide.S index 79ce7b77bc..0559d01f87 100644 --- a/runtime/interpreter/mterp/x86/op_move_wide.S +++ b/runtime/interpreter/mterp/x86/op_move_wide.S @@ -1,3 +1,4 @@ +%def op_move_wide(): /* move-wide vA, vB */ /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ movzbl rINSTbl, %ecx # ecx <- BA diff --git a/runtime/interpreter/mterp/x86/op_move_wide_16.S b/runtime/interpreter/mterp/x86/op_move_wide_16.S index a6b8596b98..13a5e0d83a 100644 --- a/runtime/interpreter/mterp/x86/op_move_wide_16.S +++ b/runtime/interpreter/mterp/x86/op_move_wide_16.S @@ -1,3 +1,4 @@ +%def op_move_wide_16(): /* move-wide/16 vAAAA, vBBBB */ /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ movzwl 4(rPC), %ecx # ecx<- BBBB diff --git a/runtime/interpreter/mterp/x86/op_move_wide_from16.S b/runtime/interpreter/mterp/x86/op_move_wide_from16.S index ec344de95f..5380a8fa8a 100644 --- a/runtime/interpreter/mterp/x86/op_move_wide_from16.S +++ b/runtime/interpreter/mterp/x86/op_move_wide_from16.S @@ -1,3 +1,4 @@ +%def op_move_wide_from16(): /* move-wide/from16 vAA, vBBBB */ /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ movzwl 2(rPC), %ecx # ecx <- BBBB diff --git a/runtime/interpreter/mterp/x86/op_mul_double.S b/runtime/interpreter/mterp/x86/op_mul_double.S index 7cef4c0870..5353028798 100644 --- a/runtime/interpreter/mterp/x86/op_mul_double.S +++ b/runtime/interpreter/mterp/x86/op_mul_double.S @@ -1 +1,2 @@ -%include "x86/sseBinop.S" {"instr":"muls","suff":"d"} +%def op_mul_double(): +% sseBinop(instr="muls", suff="d") diff --git a/runtime/interpreter/mterp/x86/op_mul_double_2addr.S b/runtime/interpreter/mterp/x86/op_mul_double_2addr.S index bb722b6901..7a6dcd0cb8 100644 --- a/runtime/interpreter/mterp/x86/op_mul_double_2addr.S +++ b/runtime/interpreter/mterp/x86/op_mul_double_2addr.S @@ -1 +1,2 @@ -%include "x86/sseBinop2Addr.S" {"instr":"muls","suff":"d"} +%def op_mul_double_2addr(): +% sseBinop2Addr(instr="muls", suff="d") diff --git a/runtime/interpreter/mterp/x86/op_mul_float.S b/runtime/interpreter/mterp/x86/op_mul_float.S index 115623047a..b9eeeeeb69 100644 --- a/runtime/interpreter/mterp/x86/op_mul_float.S +++ b/runtime/interpreter/mterp/x86/op_mul_float.S @@ -1 +1,2 @@ -%include "x86/sseBinop.S" {"instr":"muls","suff":"s"} +%def op_mul_float(): +% sseBinop(instr="muls", suff="s") diff --git a/runtime/interpreter/mterp/x86/op_mul_float_2addr.S b/runtime/interpreter/mterp/x86/op_mul_float_2addr.S index e9316dff69..949af7b254 100644 --- a/runtime/interpreter/mterp/x86/op_mul_float_2addr.S +++ b/runtime/interpreter/mterp/x86/op_mul_float_2addr.S @@ -1 +1,2 @@ -%include "x86/sseBinop2Addr.S" {"instr":"muls","suff":"s"} +%def op_mul_float_2addr(): +% sseBinop2Addr(instr="muls", suff="s") diff --git a/runtime/interpreter/mterp/x86/op_mul_int.S b/runtime/interpreter/mterp/x86/op_mul_int.S index 77f4659d6a..93884860d6 100644 --- a/runtime/interpreter/mterp/x86/op_mul_int.S +++ b/runtime/interpreter/mterp/x86/op_mul_int.S @@ -1,3 +1,4 @@ +%def op_mul_int(): /* * 32-bit binary multiplication. */ diff --git a/runtime/interpreter/mterp/x86/op_mul_int_2addr.S b/runtime/interpreter/mterp/x86/op_mul_int_2addr.S index da699ae19b..34e9b31bc6 100644 --- a/runtime/interpreter/mterp/x86/op_mul_int_2addr.S +++ b/runtime/interpreter/mterp/x86/op_mul_int_2addr.S @@ -1,3 +1,4 @@ +%def op_mul_int_2addr(): /* mul vA, vB */ movzx rINSTbl, %ecx # ecx <- A+ sarl $$4, rINST # rINST <- B diff --git a/runtime/interpreter/mterp/x86/op_mul_int_lit16.S b/runtime/interpreter/mterp/x86/op_mul_int_lit16.S index 056f491bef..491fde41b0 100644 --- a/runtime/interpreter/mterp/x86/op_mul_int_lit16.S +++ b/runtime/interpreter/mterp/x86/op_mul_int_lit16.S @@ -1,3 +1,4 @@ +%def op_mul_int_lit16(): /* mul/lit16 vA, vB, #+CCCC */ /* Need A in rINST, ssssCCCC in ecx, vB in eax */ movzbl rINSTbl, %eax # eax <- 000000BA diff --git a/runtime/interpreter/mterp/x86/op_mul_int_lit8.S b/runtime/interpreter/mterp/x86/op_mul_int_lit8.S index 59b384426c..d76973c776 100644 --- a/runtime/interpreter/mterp/x86/op_mul_int_lit8.S +++ b/runtime/interpreter/mterp/x86/op_mul_int_lit8.S @@ -1,3 +1,4 @@ +%def op_mul_int_lit8(): /* mul/lit8 vAA, vBB, #+CC */ movzbl 2(rPC), %eax # eax <- BB movl rIBASE, %ecx diff --git a/runtime/interpreter/mterp/x86/op_mul_long.S b/runtime/interpreter/mterp/x86/op_mul_long.S index f35ca1372b..0359272521 100644 --- a/runtime/interpreter/mterp/x86/op_mul_long.S +++ b/runtime/interpreter/mterp/x86/op_mul_long.S @@ -1,3 +1,4 @@ +%def op_mul_long(): /* * Signed 64-bit integer multiply. * diff --git a/runtime/interpreter/mterp/x86/op_mul_long_2addr.S b/runtime/interpreter/mterp/x86/op_mul_long_2addr.S index 565a57cd39..b48f58d298 100644 --- a/runtime/interpreter/mterp/x86/op_mul_long_2addr.S +++ b/runtime/interpreter/mterp/x86/op_mul_long_2addr.S @@ -1,3 +1,4 @@ +%def op_mul_long_2addr(): /* * Signed 64-bit integer multiply, 2-addr version * diff --git a/runtime/interpreter/mterp/x86/op_neg_double.S b/runtime/interpreter/mterp/x86/op_neg_double.S index fac4322f8e..df290535e2 100644 --- a/runtime/interpreter/mterp/x86/op_neg_double.S +++ b/runtime/interpreter/mterp/x86/op_neg_double.S @@ -1 +1,2 @@ -%include "x86/fpcvt.S" {"instr":"fchs","load":"fldl","store":"fstpl","wide":"1"} +%def op_neg_double(): +% fpcvt(instr="fchs", load="fldl", store="fstpl", wide="1") diff --git a/runtime/interpreter/mterp/x86/op_neg_float.S b/runtime/interpreter/mterp/x86/op_neg_float.S index 30f071b991..0abe45c7cc 100644 --- a/runtime/interpreter/mterp/x86/op_neg_float.S +++ b/runtime/interpreter/mterp/x86/op_neg_float.S @@ -1 +1,2 @@ -%include "x86/fpcvt.S" {"instr":"fchs","load":"flds","store":"fstps"} +%def op_neg_float(): +% fpcvt(instr="fchs", load="flds", store="fstps") diff --git a/runtime/interpreter/mterp/x86/op_neg_int.S b/runtime/interpreter/mterp/x86/op_neg_int.S index 67d4d182aa..24604a9b0c 100644 --- a/runtime/interpreter/mterp/x86/op_neg_int.S +++ b/runtime/interpreter/mterp/x86/op_neg_int.S @@ -1 +1,2 @@ -%include "x86/unop.S" {"instr":"negl %eax"} +%def op_neg_int(): +% unop(instr="negl %eax") diff --git a/runtime/interpreter/mterp/x86/op_neg_long.S b/runtime/interpreter/mterp/x86/op_neg_long.S index 30da247208..75f32798f4 100644 --- a/runtime/interpreter/mterp/x86/op_neg_long.S +++ b/runtime/interpreter/mterp/x86/op_neg_long.S @@ -1,3 +1,4 @@ +%def op_neg_long(): /* unop vA, vB */ movzbl rINSTbl, %ecx # ecx <- BA sarl $$4, %ecx # ecx <- B diff --git a/runtime/interpreter/mterp/x86/op_new_array.S b/runtime/interpreter/mterp/x86/op_new_array.S index 16226e989c..e59e106103 100644 --- a/runtime/interpreter/mterp/x86/op_new_array.S +++ b/runtime/interpreter/mterp/x86/op_new_array.S @@ -1,3 +1,4 @@ +%def op_new_array(): /* * Allocate an array of objects, specified with the array class * and a count. diff --git a/runtime/interpreter/mterp/x86/op_new_instance.S b/runtime/interpreter/mterp/x86/op_new_instance.S index f976accb1e..81631c6ae7 100644 --- a/runtime/interpreter/mterp/x86/op_new_instance.S +++ b/runtime/interpreter/mterp/x86/op_new_instance.S @@ -1,3 +1,4 @@ +%def op_new_instance(): /* * Create a new instance of a class. */ diff --git a/runtime/interpreter/mterp/x86/op_nop.S b/runtime/interpreter/mterp/x86/op_nop.S index 4cb68e392e..aa4a843ab5 100644 --- a/runtime/interpreter/mterp/x86/op_nop.S +++ b/runtime/interpreter/mterp/x86/op_nop.S @@ -1 +1,2 @@ +%def op_nop(): ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/op_not_int.S b/runtime/interpreter/mterp/x86/op_not_int.S index 335ab09a5a..c95ac08d18 100644 --- a/runtime/interpreter/mterp/x86/op_not_int.S +++ b/runtime/interpreter/mterp/x86/op_not_int.S @@ -1 +1,2 @@ -%include "x86/unop.S" {"instr":"notl %eax"} +%def op_not_int(): +% unop(instr="notl %eax") diff --git a/runtime/interpreter/mterp/x86/op_not_long.S b/runtime/interpreter/mterp/x86/op_not_long.S index 8f706e13be..c79f9d02f9 100644 --- a/runtime/interpreter/mterp/x86/op_not_long.S +++ b/runtime/interpreter/mterp/x86/op_not_long.S @@ -1,3 +1,4 @@ +%def op_not_long(): /* unop vA, vB */ movzbl rINSTbl, %ecx # ecx <- BA sarl $$4, %ecx # ecx <- B diff --git a/runtime/interpreter/mterp/x86/op_or_int.S b/runtime/interpreter/mterp/x86/op_or_int.S index ebe2ec2cd6..f44ac0d604 100644 --- a/runtime/interpreter/mterp/x86/op_or_int.S +++ b/runtime/interpreter/mterp/x86/op_or_int.S @@ -1 +1,2 @@ -%include "x86/binop.S" {"instr":"orl (rFP,%ecx,4), %eax"} +%def op_or_int(): +% binop(instr="orl (rFP,%ecx,4), %eax") diff --git a/runtime/interpreter/mterp/x86/op_or_int_2addr.S b/runtime/interpreter/mterp/x86/op_or_int_2addr.S index 36c17db5a7..f0f278c3ce 100644 --- a/runtime/interpreter/mterp/x86/op_or_int_2addr.S +++ b/runtime/interpreter/mterp/x86/op_or_int_2addr.S @@ -1 +1,2 @@ -%include "x86/binop2addr.S" {"instr":"orl %eax, (rFP,%ecx,4)"} +%def op_or_int_2addr(): +% binop2addr(instr="orl %eax, (rFP,%ecx,4)") diff --git a/runtime/interpreter/mterp/x86/op_or_int_lit16.S b/runtime/interpreter/mterp/x86/op_or_int_lit16.S index 0a88ff5902..ba9b6bff18 100644 --- a/runtime/interpreter/mterp/x86/op_or_int_lit16.S +++ b/runtime/interpreter/mterp/x86/op_or_int_lit16.S @@ -1 +1,2 @@ -%include "x86/binopLit16.S" {"instr":"orl %ecx, %eax"} +%def op_or_int_lit16(): +% binopLit16(instr="orl %ecx, %eax") diff --git a/runtime/interpreter/mterp/x86/op_or_int_lit8.S b/runtime/interpreter/mterp/x86/op_or_int_lit8.S index 0670b6785e..758109bc05 100644 --- a/runtime/interpreter/mterp/x86/op_or_int_lit8.S +++ b/runtime/interpreter/mterp/x86/op_or_int_lit8.S @@ -1 +1,2 @@ -%include "x86/binopLit8.S" {"instr":"orl %ecx, %eax"} +%def op_or_int_lit8(): +% binopLit8(instr="orl %ecx, %eax") diff --git a/runtime/interpreter/mterp/x86/op_or_long.S b/runtime/interpreter/mterp/x86/op_or_long.S index 09ca539f2a..389081d6fb 100644 --- a/runtime/interpreter/mterp/x86/op_or_long.S +++ b/runtime/interpreter/mterp/x86/op_or_long.S @@ -1 +1,2 @@ -%include "x86/binopWide.S" {"instr1":"orl (rFP,%ecx,4), rIBASE", "instr2":"orl 4(rFP,%ecx,4), %eax"} +%def op_or_long(): +% binopWide(instr1="orl (rFP,%ecx,4), rIBASE", instr2="orl 4(rFP,%ecx,4), %eax") diff --git a/runtime/interpreter/mterp/x86/op_or_long_2addr.S b/runtime/interpreter/mterp/x86/op_or_long_2addr.S index 2062e81e35..5beb9a2e01 100644 --- a/runtime/interpreter/mterp/x86/op_or_long_2addr.S +++ b/runtime/interpreter/mterp/x86/op_or_long_2addr.S @@ -1 +1,2 @@ -%include "x86/binopWide2addr.S" {"instr1":"orl %eax, (rFP,rINST,4)","instr2":"orl %ecx, 4(rFP,rINST,4)"} +%def op_or_long_2addr(): +% binopWide2addr(instr1="orl %eax, (rFP,rINST,4)", instr2="orl %ecx, 4(rFP,rINST,4)") diff --git a/runtime/interpreter/mterp/x86/op_packed_switch.S b/runtime/interpreter/mterp/x86/op_packed_switch.S index fcb7509ebf..b4c393fb84 100644 --- a/runtime/interpreter/mterp/x86/op_packed_switch.S +++ b/runtime/interpreter/mterp/x86/op_packed_switch.S @@ -1,4 +1,4 @@ -%default { "func":"MterpDoPackedSwitch" } +%def op_packed_switch(func="MterpDoPackedSwitch"): /* * Handle a packed-switch or sparse-switch instruction. In both cases * we decode it and hand it off to a helper function. diff --git a/runtime/interpreter/mterp/x86/op_rem_double.S b/runtime/interpreter/mterp/x86/op_rem_double.S index 4b52a06042..df7b740576 100644 --- a/runtime/interpreter/mterp/x86/op_rem_double.S +++ b/runtime/interpreter/mterp/x86/op_rem_double.S @@ -1,3 +1,4 @@ +%def op_rem_double(): /* rem_double vAA, vBB, vCC */ movzbl 3(rPC), %ecx # ecx <- BB movzbl 2(rPC), %eax # eax <- CC diff --git a/runtime/interpreter/mterp/x86/op_rem_double_2addr.S b/runtime/interpreter/mterp/x86/op_rem_double_2addr.S index 5a0e669787..fb4e393700 100644 --- a/runtime/interpreter/mterp/x86/op_rem_double_2addr.S +++ b/runtime/interpreter/mterp/x86/op_rem_double_2addr.S @@ -1,3 +1,4 @@ +%def op_rem_double_2addr(): /* rem_double/2addr vA, vB */ movzx rINSTbl, %ecx # ecx <- A+ sarl $$4, rINST # rINST <- B diff --git a/runtime/interpreter/mterp/x86/op_rem_float.S b/runtime/interpreter/mterp/x86/op_rem_float.S index 05e0bf1132..9b436f2759 100644 --- a/runtime/interpreter/mterp/x86/op_rem_float.S +++ b/runtime/interpreter/mterp/x86/op_rem_float.S @@ -1,3 +1,4 @@ +%def op_rem_float(): /* rem_float vAA, vBB, vCC */ movzbl 3(rPC), %ecx # ecx <- BB movzbl 2(rPC), %eax # eax <- CC diff --git a/runtime/interpreter/mterp/x86/op_rem_float_2addr.S b/runtime/interpreter/mterp/x86/op_rem_float_2addr.S index 29f84e635a..81d44c8b14 100644 --- a/runtime/interpreter/mterp/x86/op_rem_float_2addr.S +++ b/runtime/interpreter/mterp/x86/op_rem_float_2addr.S @@ -1,3 +1,4 @@ +%def op_rem_float_2addr(): /* rem_float/2addr vA, vB */ movzx rINSTbl, %ecx # ecx <- A+ sarl $$4, rINST # rINST <- B diff --git a/runtime/interpreter/mterp/x86/op_rem_int.S b/runtime/interpreter/mterp/x86/op_rem_int.S index d25b93ce3f..71da7b81db 100644 --- a/runtime/interpreter/mterp/x86/op_rem_int.S +++ b/runtime/interpreter/mterp/x86/op_rem_int.S @@ -1 +1,2 @@ -%include "x86/bindiv.S" {"result":"rIBASE","special":"$0","rem":"1"} +%def op_rem_int(): +% bindiv(result="rIBASE", special="$0", rem="1") diff --git a/runtime/interpreter/mterp/x86/op_rem_int_2addr.S b/runtime/interpreter/mterp/x86/op_rem_int_2addr.S index c788e0eed0..f58f4ac73f 100644 --- a/runtime/interpreter/mterp/x86/op_rem_int_2addr.S +++ b/runtime/interpreter/mterp/x86/op_rem_int_2addr.S @@ -1 +1,2 @@ -%include "x86/bindiv2addr.S" {"result":"rIBASE","special":"$0"} +%def op_rem_int_2addr(): +% bindiv2addr(result="rIBASE", special="$0") diff --git a/runtime/interpreter/mterp/x86/op_rem_int_lit16.S b/runtime/interpreter/mterp/x86/op_rem_int_lit16.S index 3df9d3911d..8915740c04 100644 --- a/runtime/interpreter/mterp/x86/op_rem_int_lit16.S +++ b/runtime/interpreter/mterp/x86/op_rem_int_lit16.S @@ -1 +1,2 @@ -%include "x86/bindivLit16.S" {"result":"rIBASE","special":"$0"} +%def op_rem_int_lit16(): +% bindivLit16(result="rIBASE", special="$0") diff --git a/runtime/interpreter/mterp/x86/op_rem_int_lit8.S b/runtime/interpreter/mterp/x86/op_rem_int_lit8.S index 56e19c6b17..88369def7f 100644 --- a/runtime/interpreter/mterp/x86/op_rem_int_lit8.S +++ b/runtime/interpreter/mterp/x86/op_rem_int_lit8.S @@ -1 +1,2 @@ -%include "x86/bindivLit8.S" {"result":"rIBASE","special":"$0"} +%def op_rem_int_lit8(): +% bindivLit8(result="rIBASE", special="$0") diff --git a/runtime/interpreter/mterp/x86/op_rem_long.S b/runtime/interpreter/mterp/x86/op_rem_long.S index 0ffe1f668c..ef23c05ed8 100644 --- a/runtime/interpreter/mterp/x86/op_rem_long.S +++ b/runtime/interpreter/mterp/x86/op_rem_long.S @@ -1 +1,2 @@ -%include "x86/op_div_long.S" {"routine":"art_quick_lmod"} +%def op_rem_long(): +% op_div_long(routine="art_quick_lmod") diff --git a/runtime/interpreter/mterp/x86/op_rem_long_2addr.S b/runtime/interpreter/mterp/x86/op_rem_long_2addr.S index 4b977352a1..f6a8ec36a2 100644 --- a/runtime/interpreter/mterp/x86/op_rem_long_2addr.S +++ b/runtime/interpreter/mterp/x86/op_rem_long_2addr.S @@ -1 +1,2 @@ -%include "x86/op_div_long_2addr.S" {"routine":"art_quick_lmod"} +%def op_rem_long_2addr(): +% op_div_long_2addr(routine="art_quick_lmod") diff --git a/runtime/interpreter/mterp/x86/op_return.S b/runtime/interpreter/mterp/x86/op_return.S index a8ebbed64e..0fdd6f51c8 100644 --- a/runtime/interpreter/mterp/x86/op_return.S +++ b/runtime/interpreter/mterp/x86/op_return.S @@ -1,3 +1,4 @@ +%def op_return(): /* * Return a 32-bit value. * diff --git a/runtime/interpreter/mterp/x86/op_return_object.S b/runtime/interpreter/mterp/x86/op_return_object.S index 12c84b32a2..2eeec0b948 100644 --- a/runtime/interpreter/mterp/x86/op_return_object.S +++ b/runtime/interpreter/mterp/x86/op_return_object.S @@ -1 +1,2 @@ -%include "x86/op_return.S" +%def op_return_object(): +% op_return() diff --git a/runtime/interpreter/mterp/x86/op_return_void.S b/runtime/interpreter/mterp/x86/op_return_void.S index d9eddf39f2..3eb5b6602e 100644 --- a/runtime/interpreter/mterp/x86/op_return_void.S +++ b/runtime/interpreter/mterp/x86/op_return_void.S @@ -1,3 +1,4 @@ +%def op_return_void(): .extern MterpThreadFenceForConstructor call SYMBOL(MterpThreadFenceForConstructor) movl rSELF, %eax diff --git a/runtime/interpreter/mterp/x86/op_return_void_no_barrier.S b/runtime/interpreter/mterp/x86/op_return_void_no_barrier.S index 2fbda6bfe9..eadd522299 100644 --- a/runtime/interpreter/mterp/x86/op_return_void_no_barrier.S +++ b/runtime/interpreter/mterp/x86/op_return_void_no_barrier.S @@ -1,3 +1,4 @@ +%def op_return_void_no_barrier(): movl rSELF, %eax testl $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(%eax) jz 1f diff --git a/runtime/interpreter/mterp/x86/op_return_wide.S b/runtime/interpreter/mterp/x86/op_return_wide.S index 5fff626200..67a103dac6 100644 --- a/runtime/interpreter/mterp/x86/op_return_wide.S +++ b/runtime/interpreter/mterp/x86/op_return_wide.S @@ -1,3 +1,4 @@ +%def op_return_wide(): /* * Return a 64-bit value. */ diff --git a/runtime/interpreter/mterp/x86/op_rsub_int.S b/runtime/interpreter/mterp/x86/op_rsub_int.S index d6449c6c47..05ba130f2f 100644 --- a/runtime/interpreter/mterp/x86/op_rsub_int.S +++ b/runtime/interpreter/mterp/x86/op_rsub_int.S @@ -1,2 +1,3 @@ +%def op_rsub_int(): /* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ -%include "x86/binopLit16.S" {"instr":"subl %eax, %ecx","result":"%ecx"} +% binopLit16(instr="subl %eax, %ecx", result="%ecx") diff --git a/runtime/interpreter/mterp/x86/op_rsub_int_lit8.S b/runtime/interpreter/mterp/x86/op_rsub_int_lit8.S index 15d0e359bf..d0230476d7 100644 --- a/runtime/interpreter/mterp/x86/op_rsub_int_lit8.S +++ b/runtime/interpreter/mterp/x86/op_rsub_int_lit8.S @@ -1 +1,2 @@ -%include "x86/binopLit8.S" {"instr":"subl %eax, %ecx" , "result":"%ecx"} +%def op_rsub_int_lit8(): +% binopLit8(instr="subl %eax, %ecx", result="%ecx") diff --git a/runtime/interpreter/mterp/x86/op_sget.S b/runtime/interpreter/mterp/x86/op_sget.S index ada4e0e26a..8a6a66ab60 100644 --- a/runtime/interpreter/mterp/x86/op_sget.S +++ b/runtime/interpreter/mterp/x86/op_sget.S @@ -1,2 +1,2 @@ -%default { "is_object":"0", "helper":"MterpSGetU32" } -%include "x86/field.S" { } +%def op_sget(is_object="0", helper="MterpSGetU32"): +% field(helper=helper) diff --git a/runtime/interpreter/mterp/x86/op_sget_boolean.S b/runtime/interpreter/mterp/x86/op_sget_boolean.S index 3936eeae45..d9c12c9b28 100644 --- a/runtime/interpreter/mterp/x86/op_sget_boolean.S +++ b/runtime/interpreter/mterp/x86/op_sget_boolean.S @@ -1 +1,2 @@ -%include "x86/op_sget.S" {"helper":"MterpSGetU8"} +%def op_sget_boolean(): +% op_sget(helper="MterpSGetU8") diff --git a/runtime/interpreter/mterp/x86/op_sget_byte.S b/runtime/interpreter/mterp/x86/op_sget_byte.S index 967586d944..37c6879cd4 100644 --- a/runtime/interpreter/mterp/x86/op_sget_byte.S +++ b/runtime/interpreter/mterp/x86/op_sget_byte.S @@ -1 +1,2 @@ -%include "x86/op_sget.S" {"helper":"MterpSGetI8"} +%def op_sget_byte(): +% op_sget(helper="MterpSGetI8") diff --git a/runtime/interpreter/mterp/x86/op_sget_char.S b/runtime/interpreter/mterp/x86/op_sget_char.S index b706f18638..003bcd1683 100644 --- a/runtime/interpreter/mterp/x86/op_sget_char.S +++ b/runtime/interpreter/mterp/x86/op_sget_char.S @@ -1 +1,2 @@ -%include "x86/op_sget.S" {"helper":"MterpSGetU16"} +%def op_sget_char(): +% op_sget(helper="MterpSGetU16") diff --git a/runtime/interpreter/mterp/x86/op_sget_object.S b/runtime/interpreter/mterp/x86/op_sget_object.S index eac8836534..7cf3597f44 100644 --- a/runtime/interpreter/mterp/x86/op_sget_object.S +++ b/runtime/interpreter/mterp/x86/op_sget_object.S @@ -1 +1,2 @@ -%include "x86/op_sget.S" {"is_object":"1", "helper":"MterpSGetObj"} +%def op_sget_object(): +% op_sget(is_object="1", helper="MterpSGetObj") diff --git a/runtime/interpreter/mterp/x86/op_sget_short.S b/runtime/interpreter/mterp/x86/op_sget_short.S index ee058a6016..afacb578d9 100644 --- a/runtime/interpreter/mterp/x86/op_sget_short.S +++ b/runtime/interpreter/mterp/x86/op_sget_short.S @@ -1 +1,2 @@ -%include "x86/op_sget.S" {"helper":"MterpSGetI16"} +%def op_sget_short(): +% op_sget(helper="MterpSGetI16") diff --git a/runtime/interpreter/mterp/x86/op_sget_wide.S b/runtime/interpreter/mterp/x86/op_sget_wide.S index 59232749a2..fff2be6945 100644 --- a/runtime/interpreter/mterp/x86/op_sget_wide.S +++ b/runtime/interpreter/mterp/x86/op_sget_wide.S @@ -1 +1,2 @@ -%include "x86/op_sget.S" {"helper":"MterpSGetU64"} +%def op_sget_wide(): +% op_sget(helper="MterpSGetU64") diff --git a/runtime/interpreter/mterp/x86/op_shl_int.S b/runtime/interpreter/mterp/x86/op_shl_int.S index 6a41d1c70b..a98b256120 100644 --- a/runtime/interpreter/mterp/x86/op_shl_int.S +++ b/runtime/interpreter/mterp/x86/op_shl_int.S @@ -1 +1,2 @@ -%include "x86/binop1.S" {"instr":"sall %cl, %eax"} +%def op_shl_int(): +% binop1(instr="sall %cl, %eax") diff --git a/runtime/interpreter/mterp/x86/op_shl_int_2addr.S b/runtime/interpreter/mterp/x86/op_shl_int_2addr.S index 72abb8ebe0..987c7d1e28 100644 --- a/runtime/interpreter/mterp/x86/op_shl_int_2addr.S +++ b/runtime/interpreter/mterp/x86/op_shl_int_2addr.S @@ -1 +1,2 @@ -%include "x86/shop2addr.S" {"instr":"sall %cl, %eax"} +%def op_shl_int_2addr(): +% shop2addr(instr="sall %cl, %eax") diff --git a/runtime/interpreter/mterp/x86/op_shl_int_lit8.S b/runtime/interpreter/mterp/x86/op_shl_int_lit8.S index b8d6069177..ee1a15e696 100644 --- a/runtime/interpreter/mterp/x86/op_shl_int_lit8.S +++ b/runtime/interpreter/mterp/x86/op_shl_int_lit8.S @@ -1 +1,2 @@ -%include "x86/binopLit8.S" {"instr":"sall %cl, %eax"} +%def op_shl_int_lit8(): +% binopLit8(instr="sall %cl, %eax") diff --git a/runtime/interpreter/mterp/x86/op_shl_long.S b/runtime/interpreter/mterp/x86/op_shl_long.S index aa58a93f9c..d45705a6ad 100644 --- a/runtime/interpreter/mterp/x86/op_shl_long.S +++ b/runtime/interpreter/mterp/x86/op_shl_long.S @@ -1,3 +1,4 @@ +%def op_shl_long(): /* * Long integer shift. This is different from the generic 32/64-bit * binary operations because vAA/vBB are 64-bit but vCC (the shift diff --git a/runtime/interpreter/mterp/x86/op_shl_long_2addr.S b/runtime/interpreter/mterp/x86/op_shl_long_2addr.S index 6bbf49ca69..7d40f56cc0 100644 --- a/runtime/interpreter/mterp/x86/op_shl_long_2addr.S +++ b/runtime/interpreter/mterp/x86/op_shl_long_2addr.S @@ -1,3 +1,4 @@ +%def op_shl_long_2addr(): /* * Long integer shift, 2addr version. vA is 64-bit value/result, vB is * 32-bit shift distance. diff --git a/runtime/interpreter/mterp/x86/op_shr_int.S b/runtime/interpreter/mterp/x86/op_shr_int.S index 687b2c3b7b..4d4d79cc09 100644 --- a/runtime/interpreter/mterp/x86/op_shr_int.S +++ b/runtime/interpreter/mterp/x86/op_shr_int.S @@ -1 +1,2 @@ -%include "x86/binop1.S" {"instr":"sarl %cl, %eax"} +%def op_shr_int(): +% binop1(instr="sarl %cl, %eax") diff --git a/runtime/interpreter/mterp/x86/op_shr_int_2addr.S b/runtime/interpreter/mterp/x86/op_shr_int_2addr.S index 533b0e95b9..8e4b055e15 100644 --- a/runtime/interpreter/mterp/x86/op_shr_int_2addr.S +++ b/runtime/interpreter/mterp/x86/op_shr_int_2addr.S @@ -1 +1,2 @@ -%include "x86/shop2addr.S" {"instr":"sarl %cl, %eax"} +%def op_shr_int_2addr(): +% shop2addr(instr="sarl %cl, %eax") diff --git a/runtime/interpreter/mterp/x86/op_shr_int_lit8.S b/runtime/interpreter/mterp/x86/op_shr_int_lit8.S index ebd1beafac..a7acf5f384 100644 --- a/runtime/interpreter/mterp/x86/op_shr_int_lit8.S +++ b/runtime/interpreter/mterp/x86/op_shr_int_lit8.S @@ -1 +1,2 @@ -%include "x86/binopLit8.S" {"instr":"sarl %cl, %eax"} +%def op_shr_int_lit8(): +% binopLit8(instr="sarl %cl, %eax") diff --git a/runtime/interpreter/mterp/x86/op_shr_long.S b/runtime/interpreter/mterp/x86/op_shr_long.S index 68aa0ee837..3b859411ae 100644 --- a/runtime/interpreter/mterp/x86/op_shr_long.S +++ b/runtime/interpreter/mterp/x86/op_shr_long.S @@ -1,3 +1,4 @@ +%def op_shr_long(): /* * Long integer shift. This is different from the generic 32/64-bit * binary operations because vAA/vBB are 64-bit but vCC (the shift diff --git a/runtime/interpreter/mterp/x86/op_shr_long_2addr.S b/runtime/interpreter/mterp/x86/op_shr_long_2addr.S index 148bd1b9eb..6427dedbf4 100644 --- a/runtime/interpreter/mterp/x86/op_shr_long_2addr.S +++ b/runtime/interpreter/mterp/x86/op_shr_long_2addr.S @@ -1,3 +1,4 @@ +%def op_shr_long_2addr(): /* * Long integer shift, 2addr version. vA is 64-bit value/result, vB is * 32-bit shift distance. diff --git a/runtime/interpreter/mterp/x86/op_sparse_switch.S b/runtime/interpreter/mterp/x86/op_sparse_switch.S index fdaec4762a..b74d7da816 100644 --- a/runtime/interpreter/mterp/x86/op_sparse_switch.S +++ b/runtime/interpreter/mterp/x86/op_sparse_switch.S @@ -1 +1,2 @@ -%include "x86/op_packed_switch.S" { "func":"MterpDoSparseSwitch" } +%def op_sparse_switch(): +% op_packed_switch(func="MterpDoSparseSwitch") diff --git a/runtime/interpreter/mterp/x86/op_sput.S b/runtime/interpreter/mterp/x86/op_sput.S index 2ad68e7683..cbd6ee96d3 100644 --- a/runtime/interpreter/mterp/x86/op_sput.S +++ b/runtime/interpreter/mterp/x86/op_sput.S @@ -1,2 +1,2 @@ -%default { "is_object":"0", "helper":"MterpSPutU32"} -%include "x86/field.S" { } +%def op_sput(is_object="0", helper="MterpSPutU32"): +% field(helper=helper) diff --git a/runtime/interpreter/mterp/x86/op_sput_boolean.S b/runtime/interpreter/mterp/x86/op_sput_boolean.S index c6aa7c4cd1..36fba8448b 100644 --- a/runtime/interpreter/mterp/x86/op_sput_boolean.S +++ b/runtime/interpreter/mterp/x86/op_sput_boolean.S @@ -1 +1,2 @@ -%include "x86/op_sput.S" {"helper":"MterpSPutU8"} +%def op_sput_boolean(): +% op_sput(helper="MterpSPutU8") diff --git a/runtime/interpreter/mterp/x86/op_sput_byte.S b/runtime/interpreter/mterp/x86/op_sput_byte.S index fd504a8023..84ad4a0ff8 100644 --- a/runtime/interpreter/mterp/x86/op_sput_byte.S +++ b/runtime/interpreter/mterp/x86/op_sput_byte.S @@ -1 +1,2 @@ -%include "x86/op_sput.S" {"helper":"MterpSPutI8"} +%def op_sput_byte(): +% op_sput(helper="MterpSPutI8") diff --git a/runtime/interpreter/mterp/x86/op_sput_char.S b/runtime/interpreter/mterp/x86/op_sput_char.S index b4d0997737..9b8eeba578 100644 --- a/runtime/interpreter/mterp/x86/op_sput_char.S +++ b/runtime/interpreter/mterp/x86/op_sput_char.S @@ -1 +1,2 @@ -%include "x86/op_sput.S" {"helper":"MterpSPutU16"} +%def op_sput_char(): +% op_sput(helper="MterpSPutU16") diff --git a/runtime/interpreter/mterp/x86/op_sput_object.S b/runtime/interpreter/mterp/x86/op_sput_object.S index 4452dba272..081360c40f 100644 --- a/runtime/interpreter/mterp/x86/op_sput_object.S +++ b/runtime/interpreter/mterp/x86/op_sput_object.S @@ -1 +1,2 @@ -%include "x86/op_sput.S" {"is_object":"1", "helper":"MterpSPutObj"} +%def op_sput_object(): +% op_sput(is_object="1", helper="MterpSPutObj") diff --git a/runtime/interpreter/mterp/x86/op_sput_short.S b/runtime/interpreter/mterp/x86/op_sput_short.S index eba01bdfd0..ee16513486 100644 --- a/runtime/interpreter/mterp/x86/op_sput_short.S +++ b/runtime/interpreter/mterp/x86/op_sput_short.S @@ -1 +1,2 @@ -%include "x86/op_sput.S" {"helper":"MterpSPutI16"} +%def op_sput_short(): +% op_sput(helper="MterpSPutI16") diff --git a/runtime/interpreter/mterp/x86/op_sput_wide.S b/runtime/interpreter/mterp/x86/op_sput_wide.S index d79b068f33..44c1a188ed 100644 --- a/runtime/interpreter/mterp/x86/op_sput_wide.S +++ b/runtime/interpreter/mterp/x86/op_sput_wide.S @@ -1 +1,2 @@ -%include "x86/op_sput.S" {"helper":"MterpSPutU64"} +%def op_sput_wide(): +% op_sput(helper="MterpSPutU64") diff --git a/runtime/interpreter/mterp/x86/op_sub_double.S b/runtime/interpreter/mterp/x86/op_sub_double.S index e83afeb215..64a28c376b 100644 --- a/runtime/interpreter/mterp/x86/op_sub_double.S +++ b/runtime/interpreter/mterp/x86/op_sub_double.S @@ -1 +1,2 @@ -%include "x86/sseBinop.S" {"instr":"subs","suff":"d"} +%def op_sub_double(): +% sseBinop(instr="subs", suff="d") diff --git a/runtime/interpreter/mterp/x86/op_sub_double_2addr.S b/runtime/interpreter/mterp/x86/op_sub_double_2addr.S index af9a2ab3f8..753074bd37 100644 --- a/runtime/interpreter/mterp/x86/op_sub_double_2addr.S +++ b/runtime/interpreter/mterp/x86/op_sub_double_2addr.S @@ -1 +1,2 @@ -%include "x86/sseBinop2Addr.S" {"instr":"subs","suff":"d"} +%def op_sub_double_2addr(): +% sseBinop2Addr(instr="subs", suff="d") diff --git a/runtime/interpreter/mterp/x86/op_sub_float.S b/runtime/interpreter/mterp/x86/op_sub_float.S index 423d834069..1a1966dba2 100644 --- a/runtime/interpreter/mterp/x86/op_sub_float.S +++ b/runtime/interpreter/mterp/x86/op_sub_float.S @@ -1 +1,2 @@ -%include "x86/sseBinop.S" {"instr":"subs","suff":"s"} +%def op_sub_float(): +% sseBinop(instr="subs", suff="s") diff --git a/runtime/interpreter/mterp/x86/op_sub_float_2addr.S b/runtime/interpreter/mterp/x86/op_sub_float_2addr.S index 18de000b49..9557907bd2 100644 --- a/runtime/interpreter/mterp/x86/op_sub_float_2addr.S +++ b/runtime/interpreter/mterp/x86/op_sub_float_2addr.S @@ -1 +1,2 @@ -%include "x86/sseBinop2Addr.S" {"instr":"subs","suff":"s"} +%def op_sub_float_2addr(): +% sseBinop2Addr(instr="subs", suff="s") diff --git a/runtime/interpreter/mterp/x86/op_sub_int.S b/runtime/interpreter/mterp/x86/op_sub_int.S index 7fe03fb169..289d241acc 100644 --- a/runtime/interpreter/mterp/x86/op_sub_int.S +++ b/runtime/interpreter/mterp/x86/op_sub_int.S @@ -1 +1,2 @@ -%include "x86/binop.S" {"instr":"subl (rFP,%ecx,4), %eax"} +%def op_sub_int(): +% binop(instr="subl (rFP,%ecx,4), %eax") diff --git a/runtime/interpreter/mterp/x86/op_sub_int_2addr.S b/runtime/interpreter/mterp/x86/op_sub_int_2addr.S index cc9bf60f2e..b55f8874d9 100644 --- a/runtime/interpreter/mterp/x86/op_sub_int_2addr.S +++ b/runtime/interpreter/mterp/x86/op_sub_int_2addr.S @@ -1 +1,2 @@ -%include "x86/binop2addr.S" {"instr":"subl %eax, (rFP,%ecx,4)"} +%def op_sub_int_2addr(): +% binop2addr(instr="subl %eax, (rFP,%ecx,4)") diff --git a/runtime/interpreter/mterp/x86/op_sub_long.S b/runtime/interpreter/mterp/x86/op_sub_long.S index 014591e41e..d45c9a7846 100644 --- a/runtime/interpreter/mterp/x86/op_sub_long.S +++ b/runtime/interpreter/mterp/x86/op_sub_long.S @@ -1 +1,2 @@ -%include "x86/binopWide.S" {"instr1":"subl (rFP,%ecx,4), rIBASE", "instr2":"sbbl 4(rFP,%ecx,4), %eax"} +%def op_sub_long(): +% binopWide(instr1="subl (rFP,%ecx,4), rIBASE", instr2="sbbl 4(rFP,%ecx,4), %eax") diff --git a/runtime/interpreter/mterp/x86/op_sub_long_2addr.S b/runtime/interpreter/mterp/x86/op_sub_long_2addr.S index 7498029ebf..615b535ef4 100644 --- a/runtime/interpreter/mterp/x86/op_sub_long_2addr.S +++ b/runtime/interpreter/mterp/x86/op_sub_long_2addr.S @@ -1 +1,2 @@ -%include "x86/binopWide2addr.S" {"instr1":"subl %eax, (rFP,rINST,4)","instr2":"sbbl %ecx, 4(rFP,rINST,4)"} +%def op_sub_long_2addr(): +% binopWide2addr(instr1="subl %eax, (rFP,rINST,4)", instr2="sbbl %ecx, 4(rFP,rINST,4)") diff --git a/runtime/interpreter/mterp/x86/op_throw.S b/runtime/interpreter/mterp/x86/op_throw.S index a6e6b1ed56..fa4a9d02a7 100644 --- a/runtime/interpreter/mterp/x86/op_throw.S +++ b/runtime/interpreter/mterp/x86/op_throw.S @@ -1,3 +1,4 @@ +%def op_throw(): /* * Throw an exception object in the current thread. */ diff --git a/runtime/interpreter/mterp/x86/op_unused_3e.S b/runtime/interpreter/mterp/x86/op_unused_3e.S index 31d98c1f39..d889f1a5fb 100644 --- a/runtime/interpreter/mterp/x86/op_unused_3e.S +++ b/runtime/interpreter/mterp/x86/op_unused_3e.S @@ -1 +1,2 @@ -%include "x86/unused.S" +%def op_unused_3e(): +% unused() diff --git a/runtime/interpreter/mterp/x86/op_unused_3f.S b/runtime/interpreter/mterp/x86/op_unused_3f.S index 31d98c1f39..b3ebcfaeaa 100644 --- a/runtime/interpreter/mterp/x86/op_unused_3f.S +++ b/runtime/interpreter/mterp/x86/op_unused_3f.S @@ -1 +1,2 @@ -%include "x86/unused.S" +%def op_unused_3f(): +% unused() diff --git a/runtime/interpreter/mterp/x86/op_unused_40.S b/runtime/interpreter/mterp/x86/op_unused_40.S index 31d98c1f39..7920fb350f 100644 --- a/runtime/interpreter/mterp/x86/op_unused_40.S +++ b/runtime/interpreter/mterp/x86/op_unused_40.S @@ -1 +1,2 @@ -%include "x86/unused.S" +%def op_unused_40(): +% unused() diff --git a/runtime/interpreter/mterp/x86/op_unused_41.S b/runtime/interpreter/mterp/x86/op_unused_41.S index 31d98c1f39..5ed03b8506 100644 --- a/runtime/interpreter/mterp/x86/op_unused_41.S +++ b/runtime/interpreter/mterp/x86/op_unused_41.S @@ -1 +1,2 @@ -%include "x86/unused.S" +%def op_unused_41(): +% unused() diff --git a/runtime/interpreter/mterp/x86/op_unused_42.S b/runtime/interpreter/mterp/x86/op_unused_42.S index 31d98c1f39..ac32521add 100644 --- a/runtime/interpreter/mterp/x86/op_unused_42.S +++ b/runtime/interpreter/mterp/x86/op_unused_42.S @@ -1 +1,2 @@ -%include "x86/unused.S" +%def op_unused_42(): +% unused() diff --git a/runtime/interpreter/mterp/x86/op_unused_43.S b/runtime/interpreter/mterp/x86/op_unused_43.S index 31d98c1f39..33e2aa10f8 100644 --- a/runtime/interpreter/mterp/x86/op_unused_43.S +++ b/runtime/interpreter/mterp/x86/op_unused_43.S @@ -1 +1,2 @@ -%include "x86/unused.S" +%def op_unused_43(): +% unused() diff --git a/runtime/interpreter/mterp/x86/op_unused_79.S b/runtime/interpreter/mterp/x86/op_unused_79.S index 31d98c1f39..3c6dafc789 100644 --- a/runtime/interpreter/mterp/x86/op_unused_79.S +++ b/runtime/interpreter/mterp/x86/op_unused_79.S @@ -1 +1,2 @@ -%include "x86/unused.S" +%def op_unused_79(): +% unused() diff --git a/runtime/interpreter/mterp/x86/op_unused_7a.S b/runtime/interpreter/mterp/x86/op_unused_7a.S index 31d98c1f39..9c03cd5535 100644 --- a/runtime/interpreter/mterp/x86/op_unused_7a.S +++ b/runtime/interpreter/mterp/x86/op_unused_7a.S @@ -1 +1,2 @@ -%include "x86/unused.S" +%def op_unused_7a(): +% unused() diff --git a/runtime/interpreter/mterp/x86/op_unused_f3.S b/runtime/interpreter/mterp/x86/op_unused_f3.S index 31d98c1f39..ab10b78be2 100644 --- a/runtime/interpreter/mterp/x86/op_unused_f3.S +++ b/runtime/interpreter/mterp/x86/op_unused_f3.S @@ -1 +1,2 @@ -%include "x86/unused.S" +%def op_unused_f3(): +% unused() diff --git a/runtime/interpreter/mterp/x86/op_unused_f4.S b/runtime/interpreter/mterp/x86/op_unused_f4.S index 31d98c1f39..09229d6d99 100644 --- a/runtime/interpreter/mterp/x86/op_unused_f4.S +++ b/runtime/interpreter/mterp/x86/op_unused_f4.S @@ -1 +1,2 @@ -%include "x86/unused.S" +%def op_unused_f4(): +% unused() diff --git a/runtime/interpreter/mterp/x86/op_unused_f5.S b/runtime/interpreter/mterp/x86/op_unused_f5.S index 31d98c1f39..0d6149b5fd 100644 --- a/runtime/interpreter/mterp/x86/op_unused_f5.S +++ b/runtime/interpreter/mterp/x86/op_unused_f5.S @@ -1 +1,2 @@ -%include "x86/unused.S" +%def op_unused_f5(): +% unused() diff --git a/runtime/interpreter/mterp/x86/op_unused_f6.S b/runtime/interpreter/mterp/x86/op_unused_f6.S index 31d98c1f39..117b03de6d 100644 --- a/runtime/interpreter/mterp/x86/op_unused_f6.S +++ b/runtime/interpreter/mterp/x86/op_unused_f6.S @@ -1 +1,2 @@ -%include "x86/unused.S" +%def op_unused_f6(): +% unused() diff --git a/runtime/interpreter/mterp/x86/op_unused_f7.S b/runtime/interpreter/mterp/x86/op_unused_f7.S index 31d98c1f39..4e3a0f3c9a 100644 --- a/runtime/interpreter/mterp/x86/op_unused_f7.S +++ b/runtime/interpreter/mterp/x86/op_unused_f7.S @@ -1 +1,2 @@ -%include "x86/unused.S" +%def op_unused_f7(): +% unused() diff --git a/runtime/interpreter/mterp/x86/op_unused_f8.S b/runtime/interpreter/mterp/x86/op_unused_f8.S index 31d98c1f39..d1220752d7 100644 --- a/runtime/interpreter/mterp/x86/op_unused_f8.S +++ b/runtime/interpreter/mterp/x86/op_unused_f8.S @@ -1 +1,2 @@ -%include "x86/unused.S" +%def op_unused_f8(): +% unused() diff --git a/runtime/interpreter/mterp/x86/op_unused_f9.S b/runtime/interpreter/mterp/x86/op_unused_f9.S index 31d98c1f39..7d09a0ebcf 100644 --- a/runtime/interpreter/mterp/x86/op_unused_f9.S +++ b/runtime/interpreter/mterp/x86/op_unused_f9.S @@ -1 +1,2 @@ -%include "x86/unused.S" +%def op_unused_f9(): +% unused() diff --git a/runtime/interpreter/mterp/x86/op_unused_fc.S b/runtime/interpreter/mterp/x86/op_unused_fc.S index 31d98c1f39..06978191eb 100644 --- a/runtime/interpreter/mterp/x86/op_unused_fc.S +++ b/runtime/interpreter/mterp/x86/op_unused_fc.S @@ -1 +1,2 @@ -%include "x86/unused.S" +%def op_unused_fc(): +% unused() diff --git a/runtime/interpreter/mterp/x86/op_unused_fd.S b/runtime/interpreter/mterp/x86/op_unused_fd.S index 31d98c1f39..4bc2b4bdb6 100644 --- a/runtime/interpreter/mterp/x86/op_unused_fd.S +++ b/runtime/interpreter/mterp/x86/op_unused_fd.S @@ -1 +1,2 @@ -%include "x86/unused.S" +%def op_unused_fd(): +% unused() diff --git a/runtime/interpreter/mterp/x86/op_ushr_int.S b/runtime/interpreter/mterp/x86/op_ushr_int.S index dfe25ff05d..38c8782ca9 100644 --- a/runtime/interpreter/mterp/x86/op_ushr_int.S +++ b/runtime/interpreter/mterp/x86/op_ushr_int.S @@ -1 +1,2 @@ -%include "x86/binop1.S" {"instr":"shrl %cl, %eax"} +%def op_ushr_int(): +% binop1(instr="shrl %cl, %eax") diff --git a/runtime/interpreter/mterp/x86/op_ushr_int_2addr.S b/runtime/interpreter/mterp/x86/op_ushr_int_2addr.S index c14bc980ba..f1da71a47a 100644 --- a/runtime/interpreter/mterp/x86/op_ushr_int_2addr.S +++ b/runtime/interpreter/mterp/x86/op_ushr_int_2addr.S @@ -1 +1,2 @@ -%include "x86/shop2addr.S" {"instr":"shrl %cl, %eax"} +%def op_ushr_int_2addr(): +% shop2addr(instr="shrl %cl, %eax") diff --git a/runtime/interpreter/mterp/x86/op_ushr_int_lit8.S b/runtime/interpreter/mterp/x86/op_ushr_int_lit8.S index e129f6bbe6..4298d36c3d 100644 --- a/runtime/interpreter/mterp/x86/op_ushr_int_lit8.S +++ b/runtime/interpreter/mterp/x86/op_ushr_int_lit8.S @@ -1 +1,2 @@ -%include "x86/binopLit8.S" {"instr":"shrl %cl, %eax"} +%def op_ushr_int_lit8(): +% binopLit8(instr="shrl %cl, %eax") diff --git a/runtime/interpreter/mterp/x86/op_ushr_long.S b/runtime/interpreter/mterp/x86/op_ushr_long.S index 9527c9c2e4..5837a9a792 100644 --- a/runtime/interpreter/mterp/x86/op_ushr_long.S +++ b/runtime/interpreter/mterp/x86/op_ushr_long.S @@ -1,3 +1,4 @@ +%def op_ushr_long(): /* * Long integer shift. This is different from the generic 32/64-bit * binary operations because vAA/vBB are 64-bit but vCC (the shift diff --git a/runtime/interpreter/mterp/x86/op_ushr_long_2addr.S b/runtime/interpreter/mterp/x86/op_ushr_long_2addr.S index 72fcc36fff..f07318aeb9 100644 --- a/runtime/interpreter/mterp/x86/op_ushr_long_2addr.S +++ b/runtime/interpreter/mterp/x86/op_ushr_long_2addr.S @@ -1,3 +1,4 @@ +%def op_ushr_long_2addr(): /* * Long integer shift, 2addr version. vA is 64-bit value/result, vB is * 32-bit shift distance. diff --git a/runtime/interpreter/mterp/x86/op_xor_int.S b/runtime/interpreter/mterp/x86/op_xor_int.S index 35aca6a821..351d73ae9d 100644 --- a/runtime/interpreter/mterp/x86/op_xor_int.S +++ b/runtime/interpreter/mterp/x86/op_xor_int.S @@ -1 +1,2 @@ -%include "x86/binop.S" {"instr":"xorl (rFP,%ecx,4), %eax"} +%def op_xor_int(): +% binop(instr="xorl (rFP,%ecx,4), %eax") diff --git a/runtime/interpreter/mterp/x86/op_xor_int_2addr.S b/runtime/interpreter/mterp/x86/op_xor_int_2addr.S index d7b70e2ea1..daeebed866 100644 --- a/runtime/interpreter/mterp/x86/op_xor_int_2addr.S +++ b/runtime/interpreter/mterp/x86/op_xor_int_2addr.S @@ -1 +1,2 @@ -%include "x86/binop2addr.S" {"instr":"xorl %eax, (rFP,%ecx,4)"} +%def op_xor_int_2addr(): +% binop2addr(instr="xorl %eax, (rFP,%ecx,4)") diff --git a/runtime/interpreter/mterp/x86/op_xor_int_lit16.S b/runtime/interpreter/mterp/x86/op_xor_int_lit16.S index 115f0a0410..f5dc00e074 100644 --- a/runtime/interpreter/mterp/x86/op_xor_int_lit16.S +++ b/runtime/interpreter/mterp/x86/op_xor_int_lit16.S @@ -1 +1,2 @@ -%include "x86/binopLit16.S" {"instr":"xorl %ecx, %eax"} +%def op_xor_int_lit16(): +% binopLit16(instr="xorl %ecx, %eax") diff --git a/runtime/interpreter/mterp/x86/op_xor_int_lit8.S b/runtime/interpreter/mterp/x86/op_xor_int_lit8.S index 243971c549..98a1a432dd 100644 --- a/runtime/interpreter/mterp/x86/op_xor_int_lit8.S +++ b/runtime/interpreter/mterp/x86/op_xor_int_lit8.S @@ -1 +1,2 @@ -%include "x86/binopLit8.S" {"instr":"xorl %ecx, %eax"} +%def op_xor_int_lit8(): +% binopLit8(instr="xorl %ecx, %eax") diff --git a/runtime/interpreter/mterp/x86/op_xor_long.S b/runtime/interpreter/mterp/x86/op_xor_long.S index 0d3c0f5cac..cc749e66c7 100644 --- a/runtime/interpreter/mterp/x86/op_xor_long.S +++ b/runtime/interpreter/mterp/x86/op_xor_long.S @@ -1 +1,2 @@ -%include "x86/binopWide.S" {"instr1":"xorl (rFP,%ecx,4), rIBASE", "instr2":"xorl 4(rFP,%ecx,4), %eax"} +%def op_xor_long(): +% binopWide(instr1="xorl (rFP,%ecx,4), rIBASE", instr2="xorl 4(rFP,%ecx,4), %eax") diff --git a/runtime/interpreter/mterp/x86/op_xor_long_2addr.S b/runtime/interpreter/mterp/x86/op_xor_long_2addr.S index b5000e4426..3aa92357a9 100644 --- a/runtime/interpreter/mterp/x86/op_xor_long_2addr.S +++ b/runtime/interpreter/mterp/x86/op_xor_long_2addr.S @@ -1 +1,2 @@ -%include "x86/binopWide2addr.S" {"instr1":"xorl %eax, (rFP,rINST,4)","instr2":"xorl %ecx, 4(rFP,rINST,4)"} +%def op_xor_long_2addr(): +% binopWide2addr(instr1="xorl %eax, (rFP,rINST,4)", instr2="xorl %ecx, 4(rFP,rINST,4)") diff --git a/runtime/interpreter/mterp/x86/shop2addr.S b/runtime/interpreter/mterp/x86/shop2addr.S index 96c9954d21..9a57677832 100644 --- a/runtime/interpreter/mterp/x86/shop2addr.S +++ b/runtime/interpreter/mterp/x86/shop2addr.S @@ -1,4 +1,4 @@ -%default {"result":"%eax"} +%def shop2addr(result="%eax", instr=""): /* * Generic 32-bit "shift/2addr" operation. */ diff --git a/runtime/interpreter/mterp/x86/sseBinop.S b/runtime/interpreter/mterp/x86/sseBinop.S index 63a1e21a8f..a20db7cc2b 100644 --- a/runtime/interpreter/mterp/x86/sseBinop.S +++ b/runtime/interpreter/mterp/x86/sseBinop.S @@ -1,4 +1,4 @@ -%default {"instr":"","suff":""} +%def sseBinop(instr="", suff=""): movzbl 2(rPC), %ecx # ecx <- BB movzbl 3(rPC), %eax # eax <- CC movs${suff} VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src diff --git a/runtime/interpreter/mterp/x86/sseBinop2Addr.S b/runtime/interpreter/mterp/x86/sseBinop2Addr.S index d157e67b91..1186fb7c2c 100644 --- a/runtime/interpreter/mterp/x86/sseBinop2Addr.S +++ b/runtime/interpreter/mterp/x86/sseBinop2Addr.S @@ -1,4 +1,4 @@ -%default {"instr":"","suff":""} +%def sseBinop2Addr(instr="", suff=""): movzx rINSTbl, %ecx # ecx <- A+ andl $$0xf, %ecx # ecx <- A movs${suff} VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src diff --git a/runtime/interpreter/mterp/x86/unop.S b/runtime/interpreter/mterp/x86/unop.S index db09fc0487..5594cb9e1b 100644 --- a/runtime/interpreter/mterp/x86/unop.S +++ b/runtime/interpreter/mterp/x86/unop.S @@ -1,4 +1,4 @@ -%default {"instr":""} +%def unop(instr=""): /* * Generic 32-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result = op eax". diff --git a/runtime/interpreter/mterp/x86/unused.S b/runtime/interpreter/mterp/x86/unused.S index c95ef947d3..ef35b6e73f 100644 --- a/runtime/interpreter/mterp/x86/unused.S +++ b/runtime/interpreter/mterp/x86/unused.S @@ -1,3 +1,4 @@ +%def unused(): /* * Bail to reference interpreter to throw. */ diff --git a/runtime/interpreter/mterp/x86/zcmp.S b/runtime/interpreter/mterp/x86/zcmp.S index c1161591c6..120f1ed949 100644 --- a/runtime/interpreter/mterp/x86/zcmp.S +++ b/runtime/interpreter/mterp/x86/zcmp.S @@ -1,3 +1,4 @@ +%def zcmp(revcmp=""): /* * Generic one-operand compare-and-branch operation. Provide a "revcmp" * fragment that specifies the *reverse* comparison to perform, e.g. diff --git a/runtime/interpreter/mterp/x86_64/alt_stub.S b/runtime/interpreter/mterp/x86_64/alt_stub.S index 24cd1a821d..0c71716e22 100644 --- a/runtime/interpreter/mterp/x86_64/alt_stub.S +++ b/runtime/interpreter/mterp/x86_64/alt_stub.S @@ -1,3 +1,4 @@ +%def alt_stub(): /* * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle * any interesting requests and then jump to the real instruction diff --git a/runtime/interpreter/mterp/x86_64/bincmp.S b/runtime/interpreter/mterp/x86_64/bincmp.S index 6601483ebe..64a118c103 100644 --- a/runtime/interpreter/mterp/x86_64/bincmp.S +++ b/runtime/interpreter/mterp/x86_64/bincmp.S @@ -1,3 +1,4 @@ +%def bincmp(revcmp=""): /* * Generic two-operand compare-and-branch operation. Provide a "revcmp" * fragment that specifies the *reverse* comparison to perform, e.g. diff --git a/runtime/interpreter/mterp/x86_64/bindiv.S b/runtime/interpreter/mterp/x86_64/bindiv.S index e10d1dc4b1..d7e5333af6 100644 --- a/runtime/interpreter/mterp/x86_64/bindiv.S +++ b/runtime/interpreter/mterp/x86_64/bindiv.S @@ -1,4 +1,4 @@ -%default {"result":"","second":"","wide":"","suffix":"","rem":"0","ext":"cdq"} +%def bindiv(result="", second="", wide="", suffix="", rem="0", ext="cdq"): /* * 32-bit binary div/rem operation. Handles special case of op1=-1. */ diff --git a/runtime/interpreter/mterp/x86_64/bindiv2addr.S b/runtime/interpreter/mterp/x86_64/bindiv2addr.S index 8b9bc953d2..c55351ecb0 100644 --- a/runtime/interpreter/mterp/x86_64/bindiv2addr.S +++ b/runtime/interpreter/mterp/x86_64/bindiv2addr.S @@ -1,4 +1,4 @@ -%default {"result":"","second":"","wide":"","suffix":"","rem":"0","ext":"cdq"} +%def bindiv2addr(result="", second="", wide="", suffix="", rem="0", ext="cdq"): /* * 32-bit binary div/rem operation. Handles special case of op1=-1. */ diff --git a/runtime/interpreter/mterp/x86_64/bindivLit16.S b/runtime/interpreter/mterp/x86_64/bindivLit16.S index 80dbce2975..dbda834331 100644 --- a/runtime/interpreter/mterp/x86_64/bindivLit16.S +++ b/runtime/interpreter/mterp/x86_64/bindivLit16.S @@ -1,4 +1,4 @@ -%default {"result":"","rem":"0"} +%def bindivLit16(result="", rem="0"): /* * 32-bit binary div/rem operation. Handles special case of op1=-1. */ diff --git a/runtime/interpreter/mterp/x86_64/bindivLit8.S b/runtime/interpreter/mterp/x86_64/bindivLit8.S index ab535f3fb0..a5164b5021 100644 --- a/runtime/interpreter/mterp/x86_64/bindivLit8.S +++ b/runtime/interpreter/mterp/x86_64/bindivLit8.S @@ -1,4 +1,4 @@ -%default {"result":"","rem":"0"} +%def bindivLit8(result="", rem="0"): /* * 32-bit div/rem "lit8" binary operation. Handles special case of * op0=minint & op1=-1 diff --git a/runtime/interpreter/mterp/x86_64/binop.S b/runtime/interpreter/mterp/x86_64/binop.S index 962dd61eea..fddeaa1826 100644 --- a/runtime/interpreter/mterp/x86_64/binop.S +++ b/runtime/interpreter/mterp/x86_64/binop.S @@ -1,4 +1,4 @@ -%default {"result":"%eax"} +%def binop(result="%eax", instr=""): /* * Generic 32-bit binary operation. Provide an "instr" line that * specifies an instruction that performs "result = eax op (rFP,%ecx,4)". diff --git a/runtime/interpreter/mterp/x86_64/binop1.S b/runtime/interpreter/mterp/x86_64/binop1.S index bdd57325aa..9915c32fbf 100644 --- a/runtime/interpreter/mterp/x86_64/binop1.S +++ b/runtime/interpreter/mterp/x86_64/binop1.S @@ -1,4 +1,4 @@ -%default {"wide":"0"} +%def binop1(wide="0", instr=""): /* * Generic 32-bit binary operation in which both operands loaded to * registers (op0 in eax, op1 in ecx). diff --git a/runtime/interpreter/mterp/x86_64/binop2addr.S b/runtime/interpreter/mterp/x86_64/binop2addr.S index 4448a815e9..1cdf7fd401 100644 --- a/runtime/interpreter/mterp/x86_64/binop2addr.S +++ b/runtime/interpreter/mterp/x86_64/binop2addr.S @@ -1,4 +1,4 @@ -%default {"result":"%eax"} +%def binop2addr(result="%eax", instr=""): /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = r0 op r1". diff --git a/runtime/interpreter/mterp/x86_64/binopLit16.S b/runtime/interpreter/mterp/x86_64/binopLit16.S index de43b53d5c..bb882cba75 100644 --- a/runtime/interpreter/mterp/x86_64/binopLit16.S +++ b/runtime/interpreter/mterp/x86_64/binopLit16.S @@ -1,4 +1,4 @@ -%default {"result":"%eax"} +%def binopLit16(result="%eax", instr=""): /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = eax op ecx". diff --git a/runtime/interpreter/mterp/x86_64/binopLit8.S b/runtime/interpreter/mterp/x86_64/binopLit8.S index 995002b7e4..a30d2e8ed2 100644 --- a/runtime/interpreter/mterp/x86_64/binopLit8.S +++ b/runtime/interpreter/mterp/x86_64/binopLit8.S @@ -1,4 +1,4 @@ -%default {"result":"%eax"} +%def binopLit8(result="%eax", instr=""): /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line * that specifies an instruction that performs "result = eax op ecx". diff --git a/runtime/interpreter/mterp/x86_64/binopWide.S b/runtime/interpreter/mterp/x86_64/binopWide.S index f92f18e013..015d9eef41 100644 --- a/runtime/interpreter/mterp/x86_64/binopWide.S +++ b/runtime/interpreter/mterp/x86_64/binopWide.S @@ -1,3 +1,4 @@ +%def binopWide(instr=""): /* * Generic 64-bit binary operation. */ diff --git a/runtime/interpreter/mterp/x86_64/binopWide2addr.S b/runtime/interpreter/mterp/x86_64/binopWide2addr.S index d9e6cfbc9d..e4c1e4da73 100644 --- a/runtime/interpreter/mterp/x86_64/binopWide2addr.S +++ b/runtime/interpreter/mterp/x86_64/binopWide2addr.S @@ -1,3 +1,4 @@ +%def binopWide2addr(instr=""): /* * Generic 64-bit binary operation. */ diff --git a/runtime/interpreter/mterp/x86_64/const.S b/runtime/interpreter/mterp/x86_64/const.S index 1ddf20fdca..fa98637a29 100644 --- a/runtime/interpreter/mterp/x86_64/const.S +++ b/runtime/interpreter/mterp/x86_64/const.S @@ -1,4 +1,4 @@ -%default { "helper":"UndefinedConstHandler" } +%def const(helper="UndefinedConstHandler"): /* const/class vAA, type@BBBB */ /* const/method-handle vAA, method_handle@BBBB */ /* const/method-type vAA, proto@BBBB */ diff --git a/runtime/interpreter/mterp/x86_64/cvtfp_int.S b/runtime/interpreter/mterp/x86_64/cvtfp_int.S index 1472bd26bd..e18986f0db 100644 --- a/runtime/interpreter/mterp/x86_64/cvtfp_int.S +++ b/runtime/interpreter/mterp/x86_64/cvtfp_int.S @@ -1,4 +1,4 @@ -%default {"fp_suffix":"","i_suffix":"","max_const":"","result_reg":"","wide":""} +%def cvtfp_int(fp_suffix="", i_suffix="", max_const="", result_reg="", wide=""): /* On fp to int conversions, Java requires that * if the result > maxint, it should be clamped to maxint. If it is less * than minint, it should be clamped to minint. If it is a nan, the result diff --git a/runtime/interpreter/mterp/x86_64/entry.S b/runtime/interpreter/mterp/x86_64/entry.S index b08419b219..515ffbc3ea 100644 --- a/runtime/interpreter/mterp/x86_64/entry.S +++ b/runtime/interpreter/mterp/x86_64/entry.S @@ -1,3 +1,4 @@ +%def entry(): /* * Copyright (C) 2016 The Android Open Source Project * diff --git a/runtime/interpreter/mterp/x86_64/fallback.S b/runtime/interpreter/mterp/x86_64/fallback.S index 8d61166f63..e3c2e2bd40 100644 --- a/runtime/interpreter/mterp/x86_64/fallback.S +++ b/runtime/interpreter/mterp/x86_64/fallback.S @@ -1,3 +1,4 @@ +%def fallback(): /* Transfer stub to alternate interpreter */ jmp MterpFallback diff --git a/runtime/interpreter/mterp/x86_64/field.S b/runtime/interpreter/mterp/x86_64/field.S index f8b0588e1b..f6c40eb224 100644 --- a/runtime/interpreter/mterp/x86_64/field.S +++ b/runtime/interpreter/mterp/x86_64/field.S @@ -1,4 +1,4 @@ -%default { } +%def field(helper=""): /* * General field read / write (iget-* iput-* sget-* sput-*). */ diff --git a/runtime/interpreter/mterp/x86_64/footer.S b/runtime/interpreter/mterp/x86_64/footer.S index 3cc75321cf..140fbaed49 100644 --- a/runtime/interpreter/mterp/x86_64/footer.S +++ b/runtime/interpreter/mterp/x86_64/footer.S @@ -1,3 +1,4 @@ +%def footer(): /* * =========================================================================== * Common subroutines and data diff --git a/runtime/interpreter/mterp/x86_64/fpcmp.S b/runtime/interpreter/mterp/x86_64/fpcmp.S index 806bc2b1ef..15161c8bf1 100644 --- a/runtime/interpreter/mterp/x86_64/fpcmp.S +++ b/runtime/interpreter/mterp/x86_64/fpcmp.S @@ -1,4 +1,4 @@ -%default {"suff":"d","nanval":"pos"} +%def fpcmp(suff="d", nanval="pos"): /* * Compare two floating-point values. Puts 0, 1, or -1 into the * destination register based on the results of the comparison. diff --git a/runtime/interpreter/mterp/x86_64/fpcvt.S b/runtime/interpreter/mterp/x86_64/fpcvt.S index 657869e0bd..6647ff369c 100644 --- a/runtime/interpreter/mterp/x86_64/fpcvt.S +++ b/runtime/interpreter/mterp/x86_64/fpcvt.S @@ -1,4 +1,4 @@ -%default {"source_suffix":"","dest_suffix":"","wide":""} +%def fpcvt(source_suffix="", dest_suffix="", wide=""): /* * Generic 32-bit FP conversion operation. */ diff --git a/runtime/interpreter/mterp/x86_64/header.S b/runtime/interpreter/mterp/x86_64/header.S index 0332ce272c..44ece2e42c 100644 --- a/runtime/interpreter/mterp/x86_64/header.S +++ b/runtime/interpreter/mterp/x86_64/header.S @@ -1,3 +1,4 @@ +%def header(): /* * Copyright (C) 2016 The Android Open Source Project * diff --git a/runtime/interpreter/mterp/x86_64/instruction_end.S b/runtime/interpreter/mterp/x86_64/instruction_end.S index 94587f83b7..5a24b66dec 100644 --- a/runtime/interpreter/mterp/x86_64/instruction_end.S +++ b/runtime/interpreter/mterp/x86_64/instruction_end.S @@ -1,3 +1,4 @@ +%def instruction_end(): OBJECT_TYPE(artMterpAsmInstructionEnd) ASM_HIDDEN SYMBOL(artMterpAsmInstructionEnd) diff --git a/runtime/interpreter/mterp/x86_64/instruction_end_alt.S b/runtime/interpreter/mterp/x86_64/instruction_end_alt.S index 7757bce9a7..d037db988c 100644 --- a/runtime/interpreter/mterp/x86_64/instruction_end_alt.S +++ b/runtime/interpreter/mterp/x86_64/instruction_end_alt.S @@ -1,3 +1,4 @@ +%def instruction_end_alt(): OBJECT_TYPE(artMterpAsmAltInstructionEnd) ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionEnd) diff --git a/runtime/interpreter/mterp/x86_64/instruction_end_sister.S b/runtime/interpreter/mterp/x86_64/instruction_end_sister.S index 8eb79accdf..7b1ec89d60 100644 --- a/runtime/interpreter/mterp/x86_64/instruction_end_sister.S +++ b/runtime/interpreter/mterp/x86_64/instruction_end_sister.S @@ -1,3 +1,4 @@ +%def instruction_end_sister(): OBJECT_TYPE(artMterpAsmSisterEnd) ASM_HIDDEN SYMBOL(artMterpAsmSisterEnd) diff --git a/runtime/interpreter/mterp/x86_64/instruction_start.S b/runtime/interpreter/mterp/x86_64/instruction_start.S index 5d29a81993..dee581b60f 100644 --- a/runtime/interpreter/mterp/x86_64/instruction_start.S +++ b/runtime/interpreter/mterp/x86_64/instruction_start.S @@ -1,3 +1,4 @@ +%def instruction_start(): OBJECT_TYPE(artMterpAsmInstructionStart) ASM_HIDDEN SYMBOL(artMterpAsmInstructionStart) diff --git a/runtime/interpreter/mterp/x86_64/instruction_start_alt.S b/runtime/interpreter/mterp/x86_64/instruction_start_alt.S index 8dcf5bfaf9..66650e7a6e 100644 --- a/runtime/interpreter/mterp/x86_64/instruction_start_alt.S +++ b/runtime/interpreter/mterp/x86_64/instruction_start_alt.S @@ -1,3 +1,4 @@ +%def instruction_start_alt(): OBJECT_TYPE(artMterpAsmAltInstructionStart) ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionStart) diff --git a/runtime/interpreter/mterp/x86_64/instruction_start_sister.S b/runtime/interpreter/mterp/x86_64/instruction_start_sister.S index 796e98b09a..8c156adf7e 100644 --- a/runtime/interpreter/mterp/x86_64/instruction_start_sister.S +++ b/runtime/interpreter/mterp/x86_64/instruction_start_sister.S @@ -1,3 +1,4 @@ +%def instruction_start_sister(): OBJECT_TYPE(artMterpAsmSisterStart) ASM_HIDDEN SYMBOL(artMterpAsmSisterStart) diff --git a/runtime/interpreter/mterp/x86_64/invoke.S b/runtime/interpreter/mterp/x86_64/invoke.S index f7e6155c16..42b50f269e 100644 --- a/runtime/interpreter/mterp/x86_64/invoke.S +++ b/runtime/interpreter/mterp/x86_64/invoke.S @@ -1,4 +1,4 @@ -%default { "helper":"UndefinedInvokeHandler" } +%def invoke(helper="UndefinedInvokeHandler"): /* * Generic invoke handler wrapper. */ diff --git a/runtime/interpreter/mterp/x86_64/invoke_polymorphic.S b/runtime/interpreter/mterp/x86_64/invoke_polymorphic.S index 5157860b37..18fd5e6125 100644 --- a/runtime/interpreter/mterp/x86_64/invoke_polymorphic.S +++ b/runtime/interpreter/mterp/x86_64/invoke_polymorphic.S @@ -1,4 +1,4 @@ -%default { "helper":"UndefinedInvokeHandler" } +%def invoke_polymorphic(helper="UndefinedInvokeHandler"): /* * invoke-polymorphic handler wrapper. */ diff --git a/runtime/interpreter/mterp/x86_64/op_add_double.S b/runtime/interpreter/mterp/x86_64/op_add_double.S index cb462cb816..a00923928b 100644 --- a/runtime/interpreter/mterp/x86_64/op_add_double.S +++ b/runtime/interpreter/mterp/x86_64/op_add_double.S @@ -1 +1,2 @@ -%include "x86_64/sseBinop.S" {"instr":"adds","suff":"d"} +%def op_add_double(): +% sseBinop(instr="adds", suff="d") diff --git a/runtime/interpreter/mterp/x86_64/op_add_double_2addr.S b/runtime/interpreter/mterp/x86_64/op_add_double_2addr.S index 063bde3fb3..8cb45a9a20 100644 --- a/runtime/interpreter/mterp/x86_64/op_add_double_2addr.S +++ b/runtime/interpreter/mterp/x86_64/op_add_double_2addr.S @@ -1 +1,2 @@ -%include "x86_64/sseBinop2Addr.S" {"instr":"adds","suff":"d"} +%def op_add_double_2addr(): +% sseBinop2Addr(instr="adds", suff="d") diff --git a/runtime/interpreter/mterp/x86_64/op_add_float.S b/runtime/interpreter/mterp/x86_64/op_add_float.S index 7753bf8870..dee28c7b8b 100644 --- a/runtime/interpreter/mterp/x86_64/op_add_float.S +++ b/runtime/interpreter/mterp/x86_64/op_add_float.S @@ -1 +1,2 @@ -%include "x86_64/sseBinop.S" {"instr":"adds","suff":"s"} +%def op_add_float(): +% sseBinop(instr="adds", suff="s") diff --git a/runtime/interpreter/mterp/x86_64/op_add_float_2addr.S b/runtime/interpreter/mterp/x86_64/op_add_float_2addr.S index 6c8005b182..4deb4451ce 100644 --- a/runtime/interpreter/mterp/x86_64/op_add_float_2addr.S +++ b/runtime/interpreter/mterp/x86_64/op_add_float_2addr.S @@ -1 +1,2 @@ -%include "x86_64/sseBinop2Addr.S" {"instr":"adds","suff":"s"} +%def op_add_float_2addr(): +% sseBinop2Addr(instr="adds", suff="s") diff --git a/runtime/interpreter/mterp/x86_64/op_add_int.S b/runtime/interpreter/mterp/x86_64/op_add_int.S index e316be7b9d..aaf0b35b57 100644 --- a/runtime/interpreter/mterp/x86_64/op_add_int.S +++ b/runtime/interpreter/mterp/x86_64/op_add_int.S @@ -1 +1,2 @@ -%include "x86_64/binop.S" {"instr":"addl (rFP,%rcx,4), %eax"} +%def op_add_int(): +% binop(instr="addl (rFP,%rcx,4), %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_add_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_add_int_2addr.S index 2ff82935ae..8ce26f6e71 100644 --- a/runtime/interpreter/mterp/x86_64/op_add_int_2addr.S +++ b/runtime/interpreter/mterp/x86_64/op_add_int_2addr.S @@ -1 +1,2 @@ -%include "x86_64/binop2addr.S" {"instr":"addl %eax, (rFP,%rcx,4)"} +%def op_add_int_2addr(): +% binop2addr(instr="addl %eax, (rFP,%rcx,4)") diff --git a/runtime/interpreter/mterp/x86_64/op_add_int_lit16.S b/runtime/interpreter/mterp/x86_64/op_add_int_lit16.S index bfeb7caabc..a43103019e 100644 --- a/runtime/interpreter/mterp/x86_64/op_add_int_lit16.S +++ b/runtime/interpreter/mterp/x86_64/op_add_int_lit16.S @@ -1 +1,2 @@ -%include "x86_64/binopLit16.S" {"instr":"addl %ecx, %eax"} +%def op_add_int_lit16(): +% binopLit16(instr="addl %ecx, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_add_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_add_int_lit8.S index 8954844eae..3205aee0cb 100644 --- a/runtime/interpreter/mterp/x86_64/op_add_int_lit8.S +++ b/runtime/interpreter/mterp/x86_64/op_add_int_lit8.S @@ -1 +1,2 @@ -%include "x86_64/binopLit8.S" {"instr":"addl %ecx, %eax"} +%def op_add_int_lit8(): +% binopLit8(instr="addl %ecx, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_add_long.S b/runtime/interpreter/mterp/x86_64/op_add_long.S index 89131ffe0e..fac8163f4b 100644 --- a/runtime/interpreter/mterp/x86_64/op_add_long.S +++ b/runtime/interpreter/mterp/x86_64/op_add_long.S @@ -1 +1,2 @@ -%include "x86_64/binopWide.S" {"instr":"addq (rFP,%rcx,4), %rax"} +%def op_add_long(): +% binopWide(instr="addq (rFP,%rcx,4), %rax") diff --git a/runtime/interpreter/mterp/x86_64/op_add_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_add_long_2addr.S index fed98bc3e6..17684e6b2b 100644 --- a/runtime/interpreter/mterp/x86_64/op_add_long_2addr.S +++ b/runtime/interpreter/mterp/x86_64/op_add_long_2addr.S @@ -1 +1,2 @@ -%include "x86_64/binopWide2addr.S" {"instr":"addq %rax, (rFP,%rcx,4)"} +%def op_add_long_2addr(): +% binopWide2addr(instr="addq %rax, (rFP,%rcx,4)") diff --git a/runtime/interpreter/mterp/x86_64/op_aget.S b/runtime/interpreter/mterp/x86_64/op_aget.S index 58d49481cf..b45f43a9ab 100644 --- a/runtime/interpreter/mterp/x86_64/op_aget.S +++ b/runtime/interpreter/mterp/x86_64/op_aget.S @@ -1,4 +1,4 @@ -%default { "load":"movl", "shift":"4", "data_offset":"MIRROR_INT_ARRAY_DATA_OFFSET", "wide":"0" } +%def op_aget(load="movl", shift="4", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET", wide="0"): /* * Array get, 32 bits or less. vAA <- vBB[vCC]. * diff --git a/runtime/interpreter/mterp/x86_64/op_aget_boolean.S b/runtime/interpreter/mterp/x86_64/op_aget_boolean.S index cf7bdb582b..279e6fc739 100644 --- a/runtime/interpreter/mterp/x86_64/op_aget_boolean.S +++ b/runtime/interpreter/mterp/x86_64/op_aget_boolean.S @@ -1 +1,2 @@ -%include "x86_64/op_aget.S" { "load":"movzbl", "shift":"1", "data_offset":"MIRROR_BOOLEAN_ARRAY_DATA_OFFSET" } +%def op_aget_boolean(): +% op_aget(load="movzbl", shift="1", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/x86_64/op_aget_byte.S b/runtime/interpreter/mterp/x86_64/op_aget_byte.S index 1cbb569024..1989450743 100644 --- a/runtime/interpreter/mterp/x86_64/op_aget_byte.S +++ b/runtime/interpreter/mterp/x86_64/op_aget_byte.S @@ -1 +1,2 @@ -%include "x86_64/op_aget.S" { "load":"movsbl", "shift":"1", "data_offset":"MIRROR_BYTE_ARRAY_DATA_OFFSET" } +%def op_aget_byte(): +% op_aget(load="movsbl", shift="1", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/x86_64/op_aget_char.S b/runtime/interpreter/mterp/x86_64/op_aget_char.S index 45c90851fd..a35269bd65 100644 --- a/runtime/interpreter/mterp/x86_64/op_aget_char.S +++ b/runtime/interpreter/mterp/x86_64/op_aget_char.S @@ -1 +1,2 @@ -%include "x86_64/op_aget.S" { "load":"movzwl", "shift":"2", "data_offset":"MIRROR_CHAR_ARRAY_DATA_OFFSET" } +%def op_aget_char(): +% op_aget(load="movzwl", shift="2", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/x86_64/op_aget_object.S b/runtime/interpreter/mterp/x86_64/op_aget_object.S index 5f77a97748..fc099dc3a2 100644 --- a/runtime/interpreter/mterp/x86_64/op_aget_object.S +++ b/runtime/interpreter/mterp/x86_64/op_aget_object.S @@ -1,3 +1,4 @@ +%def op_aget_object(): /* * Array object get. vAA <- vBB[vCC]. * diff --git a/runtime/interpreter/mterp/x86_64/op_aget_short.S b/runtime/interpreter/mterp/x86_64/op_aget_short.S index 82c4a1ddf3..ca51ec8052 100644 --- a/runtime/interpreter/mterp/x86_64/op_aget_short.S +++ b/runtime/interpreter/mterp/x86_64/op_aget_short.S @@ -1 +1,2 @@ -%include "x86_64/op_aget.S" { "load":"movswl", "shift":"2", "data_offset":"MIRROR_SHORT_ARRAY_DATA_OFFSET" } +%def op_aget_short(): +% op_aget(load="movswl", shift="2", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/x86_64/op_aget_wide.S b/runtime/interpreter/mterp/x86_64/op_aget_wide.S index 4f2771b9c4..42513fc19a 100644 --- a/runtime/interpreter/mterp/x86_64/op_aget_wide.S +++ b/runtime/interpreter/mterp/x86_64/op_aget_wide.S @@ -1 +1,2 @@ -%include "x86_64/op_aget.S" { "load":"movq", "shift":"8", "data_offset":"MIRROR_WIDE_ARRAY_DATA_OFFSET", "wide":"1" } +%def op_aget_wide(): +% op_aget(load="movq", shift="8", data_offset="MIRROR_WIDE_ARRAY_DATA_OFFSET", wide="1") diff --git a/runtime/interpreter/mterp/x86_64/op_and_int.S b/runtime/interpreter/mterp/x86_64/op_and_int.S index 446988993d..afe2d67047 100644 --- a/runtime/interpreter/mterp/x86_64/op_and_int.S +++ b/runtime/interpreter/mterp/x86_64/op_and_int.S @@ -1 +1,2 @@ -%include "x86_64/binop.S" {"instr":"andl (rFP,%rcx,4), %eax"} +%def op_and_int(): +% binop(instr="andl (rFP,%rcx,4), %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_and_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_and_int_2addr.S index 16315bba03..ed9fc654b3 100644 --- a/runtime/interpreter/mterp/x86_64/op_and_int_2addr.S +++ b/runtime/interpreter/mterp/x86_64/op_and_int_2addr.S @@ -1 +1,2 @@ -%include "x86_64/binop2addr.S" {"instr":"andl %eax, (rFP,%rcx,4)"} +%def op_and_int_2addr(): +% binop2addr(instr="andl %eax, (rFP,%rcx,4)") diff --git a/runtime/interpreter/mterp/x86_64/op_and_int_lit16.S b/runtime/interpreter/mterp/x86_64/op_and_int_lit16.S index 63e851b449..d7752b1230 100644 --- a/runtime/interpreter/mterp/x86_64/op_and_int_lit16.S +++ b/runtime/interpreter/mterp/x86_64/op_and_int_lit16.S @@ -1 +1,2 @@ -%include "x86_64/binopLit16.S" {"instr":"andl %ecx, %eax"} +%def op_and_int_lit16(): +% binopLit16(instr="andl %ecx, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_and_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_and_int_lit8.S index da7a20fdff..a353178a88 100644 --- a/runtime/interpreter/mterp/x86_64/op_and_int_lit8.S +++ b/runtime/interpreter/mterp/x86_64/op_and_int_lit8.S @@ -1 +1,2 @@ -%include "x86_64/binopLit8.S" {"instr":"andl %ecx, %eax"} +%def op_and_int_lit8(): +% binopLit8(instr="andl %ecx, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_and_long.S b/runtime/interpreter/mterp/x86_64/op_and_long.S index ce1dd264dd..7375154bdc 100644 --- a/runtime/interpreter/mterp/x86_64/op_and_long.S +++ b/runtime/interpreter/mterp/x86_64/op_and_long.S @@ -1 +1,2 @@ -%include "x86_64/binopWide.S" {"instr":"andq (rFP,%rcx,4), %rax"} +%def op_and_long(): +% binopWide(instr="andq (rFP,%rcx,4), %rax") diff --git a/runtime/interpreter/mterp/x86_64/op_and_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_and_long_2addr.S index d17ab8d58b..41938ac4dc 100644 --- a/runtime/interpreter/mterp/x86_64/op_and_long_2addr.S +++ b/runtime/interpreter/mterp/x86_64/op_and_long_2addr.S @@ -1 +1,2 @@ -%include "x86_64/binopWide2addr.S" {"instr":"andq %rax, (rFP,%rcx,4)"} +%def op_and_long_2addr(): +% binopWide2addr(instr="andq %rax, (rFP,%rcx,4)") diff --git a/runtime/interpreter/mterp/x86_64/op_aput.S b/runtime/interpreter/mterp/x86_64/op_aput.S index 11500ad201..bef2e2abe7 100644 --- a/runtime/interpreter/mterp/x86_64/op_aput.S +++ b/runtime/interpreter/mterp/x86_64/op_aput.S @@ -1,4 +1,4 @@ -%default { "reg":"rINST", "store":"movl", "shift":"4", "data_offset":"MIRROR_INT_ARRAY_DATA_OFFSET", "wide":"0" } +%def op_aput(reg="rINST", store="movl", shift="4", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET", wide="0"): /* * Array put, 32 bits or less. vBB[vCC] <- vAA. * diff --git a/runtime/interpreter/mterp/x86_64/op_aput_boolean.S b/runtime/interpreter/mterp/x86_64/op_aput_boolean.S index 7d77a86528..8420b5af8f 100644 --- a/runtime/interpreter/mterp/x86_64/op_aput_boolean.S +++ b/runtime/interpreter/mterp/x86_64/op_aput_boolean.S @@ -1 +1,2 @@ -%include "x86_64/op_aput.S" { "reg":"rINSTbl", "store":"movb", "shift":"1", "data_offset":"MIRROR_BOOLEAN_ARRAY_DATA_OFFSET" } +%def op_aput_boolean(): +% op_aput(reg="rINSTbl", store="movb", shift="1", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/x86_64/op_aput_byte.S b/runtime/interpreter/mterp/x86_64/op_aput_byte.S index 7a1723e0fe..6c181a48d9 100644 --- a/runtime/interpreter/mterp/x86_64/op_aput_byte.S +++ b/runtime/interpreter/mterp/x86_64/op_aput_byte.S @@ -1 +1,2 @@ -%include "x86_64/op_aput.S" { "reg":"rINSTbl", "store":"movb", "shift":"1", "data_offset":"MIRROR_BYTE_ARRAY_DATA_OFFSET" } +%def op_aput_byte(): +% op_aput(reg="rINSTbl", store="movb", shift="1", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/x86_64/op_aput_char.S b/runtime/interpreter/mterp/x86_64/op_aput_char.S index f8f50a3b2e..3f4602a7f4 100644 --- a/runtime/interpreter/mterp/x86_64/op_aput_char.S +++ b/runtime/interpreter/mterp/x86_64/op_aput_char.S @@ -1 +1,2 @@ -%include "x86_64/op_aput.S" { "reg":"rINSTw", "store":"movw", "shift":"2", "data_offset":"MIRROR_CHAR_ARRAY_DATA_OFFSET" } +%def op_aput_char(): +% op_aput(reg="rINSTw", store="movw", shift="2", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/x86_64/op_aput_object.S b/runtime/interpreter/mterp/x86_64/op_aput_object.S index b1bae0f457..cf4bdf1a09 100644 --- a/runtime/interpreter/mterp/x86_64/op_aput_object.S +++ b/runtime/interpreter/mterp/x86_64/op_aput_object.S @@ -1,3 +1,4 @@ +%def op_aput_object(): /* * Store an object into an array. vBB[vCC] <- vAA. */ diff --git a/runtime/interpreter/mterp/x86_64/op_aput_short.S b/runtime/interpreter/mterp/x86_64/op_aput_short.S index 481fd6847b..e76d83368b 100644 --- a/runtime/interpreter/mterp/x86_64/op_aput_short.S +++ b/runtime/interpreter/mterp/x86_64/op_aput_short.S @@ -1 +1,2 @@ -%include "x86_64/op_aput.S" { "reg":"rINSTw", "store":"movw", "shift":"2", "data_offset":"MIRROR_SHORT_ARRAY_DATA_OFFSET" } +%def op_aput_short(): +% op_aput(reg="rINSTw", store="movw", shift="2", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/x86_64/op_aput_wide.S b/runtime/interpreter/mterp/x86_64/op_aput_wide.S index 5bbd39b0b6..c1ca1ef81c 100644 --- a/runtime/interpreter/mterp/x86_64/op_aput_wide.S +++ b/runtime/interpreter/mterp/x86_64/op_aput_wide.S @@ -1 +1,2 @@ -%include "x86_64/op_aput.S" { "reg":"rINSTq", "store":"movq", "shift":"8", "data_offset":"MIRROR_WIDE_ARRAY_DATA_OFFSET", "wide":"1" } +%def op_aput_wide(): +% op_aput(reg="rINSTq", store="movq", shift="8", data_offset="MIRROR_WIDE_ARRAY_DATA_OFFSET", wide="1") diff --git a/runtime/interpreter/mterp/x86_64/op_array_length.S b/runtime/interpreter/mterp/x86_64/op_array_length.S index e80d665160..7e6c5c0b52 100644 --- a/runtime/interpreter/mterp/x86_64/op_array_length.S +++ b/runtime/interpreter/mterp/x86_64/op_array_length.S @@ -1,3 +1,4 @@ +%def op_array_length(): /* * Return the length of an array. */ diff --git a/runtime/interpreter/mterp/x86_64/op_check_cast.S b/runtime/interpreter/mterp/x86_64/op_check_cast.S index f8fa7b2036..ac7051b19b 100644 --- a/runtime/interpreter/mterp/x86_64/op_check_cast.S +++ b/runtime/interpreter/mterp/x86_64/op_check_cast.S @@ -1,3 +1,4 @@ +%def op_check_cast(): /* * Check to see if a cast from one class to another is allowed. */ diff --git a/runtime/interpreter/mterp/x86_64/op_cmp_long.S b/runtime/interpreter/mterp/x86_64/op_cmp_long.S index 23ca3e5e6d..f222813a02 100644 --- a/runtime/interpreter/mterp/x86_64/op_cmp_long.S +++ b/runtime/interpreter/mterp/x86_64/op_cmp_long.S @@ -1,3 +1,4 @@ +%def op_cmp_long(): /* * Compare two 64-bit values. Puts 0, 1, or -1 into the destination * register based on the results of the comparison. diff --git a/runtime/interpreter/mterp/x86_64/op_cmpg_double.S b/runtime/interpreter/mterp/x86_64/op_cmpg_double.S index 7c0aa1bdba..1c04e997f1 100644 --- a/runtime/interpreter/mterp/x86_64/op_cmpg_double.S +++ b/runtime/interpreter/mterp/x86_64/op_cmpg_double.S @@ -1 +1,2 @@ -%include "x86_64/fpcmp.S" {"suff":"d","nanval":"pos"} +%def op_cmpg_double(): +% fpcmp(suff="d", nanval="pos") diff --git a/runtime/interpreter/mterp/x86_64/op_cmpg_float.S b/runtime/interpreter/mterp/x86_64/op_cmpg_float.S index 14e8472672..797c3d52d7 100644 --- a/runtime/interpreter/mterp/x86_64/op_cmpg_float.S +++ b/runtime/interpreter/mterp/x86_64/op_cmpg_float.S @@ -1 +1,2 @@ -%include "x86_64/fpcmp.S" {"suff":"s","nanval":"pos"} +%def op_cmpg_float(): +% fpcmp(suff="s", nanval="pos") diff --git a/runtime/interpreter/mterp/x86_64/op_cmpl_double.S b/runtime/interpreter/mterp/x86_64/op_cmpl_double.S index 1d4c4243ae..cbe8db713b 100644 --- a/runtime/interpreter/mterp/x86_64/op_cmpl_double.S +++ b/runtime/interpreter/mterp/x86_64/op_cmpl_double.S @@ -1 +1,2 @@ -%include "x86_64/fpcmp.S" {"suff":"d","nanval":"neg"} +%def op_cmpl_double(): +% fpcmp(suff="d", nanval="neg") diff --git a/runtime/interpreter/mterp/x86_64/op_cmpl_float.S b/runtime/interpreter/mterp/x86_64/op_cmpl_float.S index 97a12a6a7d..068f4cb5c1 100644 --- a/runtime/interpreter/mterp/x86_64/op_cmpl_float.S +++ b/runtime/interpreter/mterp/x86_64/op_cmpl_float.S @@ -1 +1,2 @@ -%include "x86_64/fpcmp.S" {"suff":"s","nanval":"neg"} +%def op_cmpl_float(): +% fpcmp(suff="s", nanval="neg") diff --git a/runtime/interpreter/mterp/x86_64/op_const.S b/runtime/interpreter/mterp/x86_64/op_const.S index 3cfafdb13b..36220952bc 100644 --- a/runtime/interpreter/mterp/x86_64/op_const.S +++ b/runtime/interpreter/mterp/x86_64/op_const.S @@ -1,3 +1,4 @@ +%def op_const(): /* const vAA, #+BBBBbbbb */ movl 2(rPC), %eax # grab all 32 bits at once SET_VREG %eax, rINSTq # vAA<- eax diff --git a/runtime/interpreter/mterp/x86_64/op_const_16.S b/runtime/interpreter/mterp/x86_64/op_const_16.S index 1a139c683e..fa86060906 100644 --- a/runtime/interpreter/mterp/x86_64/op_const_16.S +++ b/runtime/interpreter/mterp/x86_64/op_const_16.S @@ -1,3 +1,4 @@ +%def op_const_16(): /* const/16 vAA, #+BBBB */ movswl 2(rPC), %ecx # ecx <- ssssBBBB SET_VREG %ecx, rINSTq # vAA <- ssssBBBB diff --git a/runtime/interpreter/mterp/x86_64/op_const_4.S b/runtime/interpreter/mterp/x86_64/op_const_4.S index 23c4816f82..9f39ceec49 100644 --- a/runtime/interpreter/mterp/x86_64/op_const_4.S +++ b/runtime/interpreter/mterp/x86_64/op_const_4.S @@ -1,3 +1,4 @@ +%def op_const_4(): /* const/4 vA, #+B */ movsbl rINSTbl, %eax # eax <-ssssssBx movl $$0xf, rINST diff --git a/runtime/interpreter/mterp/x86_64/op_const_class.S b/runtime/interpreter/mterp/x86_64/op_const_class.S index 0c402e1489..db12ec3141 100644 --- a/runtime/interpreter/mterp/x86_64/op_const_class.S +++ b/runtime/interpreter/mterp/x86_64/op_const_class.S @@ -1 +1,2 @@ -%include "x86_64/const.S" { "helper":"MterpConstClass" } +%def op_const_class(): +% const(helper="MterpConstClass") diff --git a/runtime/interpreter/mterp/x86_64/op_const_high16.S b/runtime/interpreter/mterp/x86_64/op_const_high16.S index 64e633c7a0..e1e61e387a 100644 --- a/runtime/interpreter/mterp/x86_64/op_const_high16.S +++ b/runtime/interpreter/mterp/x86_64/op_const_high16.S @@ -1,3 +1,4 @@ +%def op_const_high16(): /* const/high16 vAA, #+BBBB0000 */ movzwl 2(rPC), %eax # eax <- 0000BBBB sall $$16, %eax # eax <- BBBB0000 diff --git a/runtime/interpreter/mterp/x86_64/op_const_method_handle.S b/runtime/interpreter/mterp/x86_64/op_const_method_handle.S index 2b8b0a258a..2680c17aad 100644 --- a/runtime/interpreter/mterp/x86_64/op_const_method_handle.S +++ b/runtime/interpreter/mterp/x86_64/op_const_method_handle.S @@ -1 +1,2 @@ -%include "x86_64/const.S" { "helper":"MterpConstMethodHandle" } +%def op_const_method_handle(): +% const(helper="MterpConstMethodHandle") diff --git a/runtime/interpreter/mterp/x86_64/op_const_method_type.S b/runtime/interpreter/mterp/x86_64/op_const_method_type.S index 33ce952031..ea814bf648 100644 --- a/runtime/interpreter/mterp/x86_64/op_const_method_type.S +++ b/runtime/interpreter/mterp/x86_64/op_const_method_type.S @@ -1 +1,2 @@ -%include "x86_64/const.S" { "helper":"MterpConstMethodType" } +%def op_const_method_type(): +% const(helper="MterpConstMethodType") diff --git a/runtime/interpreter/mterp/x86_64/op_const_string.S b/runtime/interpreter/mterp/x86_64/op_const_string.S index 5a29bd3dde..41376f8703 100644 --- a/runtime/interpreter/mterp/x86_64/op_const_string.S +++ b/runtime/interpreter/mterp/x86_64/op_const_string.S @@ -1 +1,2 @@ -%include "x86_64/const.S" { "helper":"MterpConstString" } +%def op_const_string(): +% const(helper="MterpConstString") diff --git a/runtime/interpreter/mterp/x86_64/op_const_string_jumbo.S b/runtime/interpreter/mterp/x86_64/op_const_string_jumbo.S index ae03d20f4f..c12abb114f 100644 --- a/runtime/interpreter/mterp/x86_64/op_const_string_jumbo.S +++ b/runtime/interpreter/mterp/x86_64/op_const_string_jumbo.S @@ -1,3 +1,4 @@ +%def op_const_string_jumbo(): /* const/string vAA, String@BBBBBBBB */ EXPORT_PC movl 2(rPC), OUT_32_ARG0 # OUT_32_ARG0 <- BBBB diff --git a/runtime/interpreter/mterp/x86_64/op_const_wide.S b/runtime/interpreter/mterp/x86_64/op_const_wide.S index 5615177175..f7a74c218a 100644 --- a/runtime/interpreter/mterp/x86_64/op_const_wide.S +++ b/runtime/interpreter/mterp/x86_64/op_const_wide.S @@ -1,3 +1,4 @@ +%def op_const_wide(): /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ movq 2(rPC), %rax # rax <- HHHHhhhhBBBBbbbb SET_WIDE_VREG %rax, rINSTq diff --git a/runtime/interpreter/mterp/x86_64/op_const_wide_16.S b/runtime/interpreter/mterp/x86_64/op_const_wide_16.S index 593b62466f..8d1e17c906 100644 --- a/runtime/interpreter/mterp/x86_64/op_const_wide_16.S +++ b/runtime/interpreter/mterp/x86_64/op_const_wide_16.S @@ -1,3 +1,4 @@ +%def op_const_wide_16(): /* const-wide/16 vAA, #+BBBB */ movswq 2(rPC), %rax # rax <- ssssBBBB SET_WIDE_VREG %rax, rINSTq # store diff --git a/runtime/interpreter/mterp/x86_64/op_const_wide_32.S b/runtime/interpreter/mterp/x86_64/op_const_wide_32.S index 5ef3636129..22b807477c 100644 --- a/runtime/interpreter/mterp/x86_64/op_const_wide_32.S +++ b/runtime/interpreter/mterp/x86_64/op_const_wide_32.S @@ -1,3 +1,4 @@ +%def op_const_wide_32(): /* const-wide/32 vAA, #+BBBBbbbb */ movslq 2(rPC), %rax # eax <- ssssssssBBBBbbbb SET_WIDE_VREG %rax, rINSTq # store diff --git a/runtime/interpreter/mterp/x86_64/op_const_wide_high16.S b/runtime/interpreter/mterp/x86_64/op_const_wide_high16.S index b86b4e582b..d41b02a6b4 100644 --- a/runtime/interpreter/mterp/x86_64/op_const_wide_high16.S +++ b/runtime/interpreter/mterp/x86_64/op_const_wide_high16.S @@ -1,3 +1,4 @@ +%def op_const_wide_high16(): /* const-wide/high16 vAA, #+BBBB000000000000 */ movzwq 2(rPC), %rax # eax <- 0000BBBB salq $$48, %rax # eax <- BBBB0000 diff --git a/runtime/interpreter/mterp/x86_64/op_div_double.S b/runtime/interpreter/mterp/x86_64/op_div_double.S index 45c700c066..6b342f89bf 100644 --- a/runtime/interpreter/mterp/x86_64/op_div_double.S +++ b/runtime/interpreter/mterp/x86_64/op_div_double.S @@ -1 +1,2 @@ -%include "x86_64/sseBinop.S" {"instr":"divs","suff":"d"} +%def op_div_double(): +% sseBinop(instr="divs", suff="d") diff --git a/runtime/interpreter/mterp/x86_64/op_div_double_2addr.S b/runtime/interpreter/mterp/x86_64/op_div_double_2addr.S index 83f270e245..212c82547e 100644 --- a/runtime/interpreter/mterp/x86_64/op_div_double_2addr.S +++ b/runtime/interpreter/mterp/x86_64/op_div_double_2addr.S @@ -1 +1,2 @@ -%include "x86_64/sseBinop2Addr.S" {"instr":"divs","suff":"d"} +%def op_div_double_2addr(): +% sseBinop2Addr(instr="divs", suff="d") diff --git a/runtime/interpreter/mterp/x86_64/op_div_float.S b/runtime/interpreter/mterp/x86_64/op_div_float.S index aa90b24698..b6537d9d89 100644 --- a/runtime/interpreter/mterp/x86_64/op_div_float.S +++ b/runtime/interpreter/mterp/x86_64/op_div_float.S @@ -1 +1,2 @@ -%include "x86_64/sseBinop.S" {"instr":"divs","suff":"s"} +%def op_div_float(): +% sseBinop(instr="divs", suff="s") diff --git a/runtime/interpreter/mterp/x86_64/op_div_float_2addr.S b/runtime/interpreter/mterp/x86_64/op_div_float_2addr.S index f0f8f1a6c8..19ae27d61a 100644 --- a/runtime/interpreter/mterp/x86_64/op_div_float_2addr.S +++ b/runtime/interpreter/mterp/x86_64/op_div_float_2addr.S @@ -1 +1,2 @@ -%include "x86_64/sseBinop2Addr.S" {"instr":"divs","suff":"s"} +%def op_div_float_2addr(): +% sseBinop2Addr(instr="divs", suff="s") diff --git a/runtime/interpreter/mterp/x86_64/op_div_int.S b/runtime/interpreter/mterp/x86_64/op_div_int.S index bba5a176a0..cd7f3db914 100644 --- a/runtime/interpreter/mterp/x86_64/op_div_int.S +++ b/runtime/interpreter/mterp/x86_64/op_div_int.S @@ -1 +1,2 @@ -%include "x86_64/bindiv.S" {"result":"%eax","second":"%ecx","wide":"0","suffix":"l"} +%def op_div_int(): +% bindiv(result="%eax", second="%ecx", wide="0", suffix="l") diff --git a/runtime/interpreter/mterp/x86_64/op_div_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_div_int_2addr.S index fa4255ddfa..3a734dbf88 100644 --- a/runtime/interpreter/mterp/x86_64/op_div_int_2addr.S +++ b/runtime/interpreter/mterp/x86_64/op_div_int_2addr.S @@ -1 +1,2 @@ -%include "x86_64/bindiv2addr.S" {"result":"%eax","second":"%ecx","wide":"0","suffix":"l"} +%def op_div_int_2addr(): +% bindiv2addr(result="%eax", second="%ecx", wide="0", suffix="l") diff --git a/runtime/interpreter/mterp/x86_64/op_div_int_lit16.S b/runtime/interpreter/mterp/x86_64/op_div_int_lit16.S index 3fa1e09fd6..cdcee2d774 100644 --- a/runtime/interpreter/mterp/x86_64/op_div_int_lit16.S +++ b/runtime/interpreter/mterp/x86_64/op_div_int_lit16.S @@ -1 +1,2 @@ -%include "x86_64/bindivLit16.S" {"result":"%eax"} +%def op_div_int_lit16(): +% bindivLit16(result="%eax") diff --git a/runtime/interpreter/mterp/x86_64/op_div_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_div_int_lit8.S index 859883e5c7..7d258c80db 100644 --- a/runtime/interpreter/mterp/x86_64/op_div_int_lit8.S +++ b/runtime/interpreter/mterp/x86_64/op_div_int_lit8.S @@ -1 +1,2 @@ -%include "x86_64/bindivLit8.S" {"result":"%eax"} +%def op_div_int_lit8(): +% bindivLit8(result="%eax") diff --git a/runtime/interpreter/mterp/x86_64/op_div_long.S b/runtime/interpreter/mterp/x86_64/op_div_long.S index a061a88b13..59f9073087 100644 --- a/runtime/interpreter/mterp/x86_64/op_div_long.S +++ b/runtime/interpreter/mterp/x86_64/op_div_long.S @@ -1 +1,2 @@ -%include "x86_64/bindiv.S" {"result":"%rax","second":"%rcx","wide":"1","suffix":"q","ext":"cqo"} +%def op_div_long(): +% bindiv(result="%rax", second="%rcx", wide="1", suffix="q", ext="cqo") diff --git a/runtime/interpreter/mterp/x86_64/op_div_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_div_long_2addr.S index 8886e68248..d7a46f540c 100644 --- a/runtime/interpreter/mterp/x86_64/op_div_long_2addr.S +++ b/runtime/interpreter/mterp/x86_64/op_div_long_2addr.S @@ -1 +1,2 @@ -%include "x86_64/bindiv2addr.S" {"result":"%rax","second":"%rcx","wide":"1","suffix":"q","ext":"cqo"} +%def op_div_long_2addr(): +% bindiv2addr(result="%rax", second="%rcx", wide="1", suffix="q", ext="cqo") diff --git a/runtime/interpreter/mterp/x86_64/op_double_to_float.S b/runtime/interpreter/mterp/x86_64/op_double_to_float.S index cea1482038..e62aa4d2a6 100644 --- a/runtime/interpreter/mterp/x86_64/op_double_to_float.S +++ b/runtime/interpreter/mterp/x86_64/op_double_to_float.S @@ -1 +1,2 @@ -%include "x86_64/fpcvt.S" {"source_suffix":"d","dest_suffix":"s","wide":"0"} +%def op_double_to_float(): +% fpcvt(source_suffix="d", dest_suffix="s", wide="0") diff --git a/runtime/interpreter/mterp/x86_64/op_double_to_int.S b/runtime/interpreter/mterp/x86_64/op_double_to_int.S index a9965edcc3..24fca631b7 100644 --- a/runtime/interpreter/mterp/x86_64/op_double_to_int.S +++ b/runtime/interpreter/mterp/x86_64/op_double_to_int.S @@ -1 +1,2 @@ -%include "x86_64/cvtfp_int.S" {"fp_suffix":"d","i_suffix":"l","max_const":"$0x7fffffff","result_reg":"%eax","wide":"0"} +%def op_double_to_int(): +% cvtfp_int(fp_suffix="d", i_suffix="l", max_const="$0x7fffffff", result_reg="%eax", wide="0") diff --git a/runtime/interpreter/mterp/x86_64/op_double_to_long.S b/runtime/interpreter/mterp/x86_64/op_double_to_long.S index 179e6a1605..8f042c0ca1 100644 --- a/runtime/interpreter/mterp/x86_64/op_double_to_long.S +++ b/runtime/interpreter/mterp/x86_64/op_double_to_long.S @@ -1 +1,2 @@ -%include "x86_64/cvtfp_int.S" {"fp_suffix":"d","i_suffix":"q","max_const":"$0x7fffffffffffffff","result_reg":"%rax","wide":"1"} +%def op_double_to_long(): +% cvtfp_int(fp_suffix="d", i_suffix="q", max_const="$0x7fffffffffffffff", result_reg="%rax", wide="1") diff --git a/runtime/interpreter/mterp/x86_64/op_fill_array_data.S b/runtime/interpreter/mterp/x86_64/op_fill_array_data.S index 7ea36a6136..694ee79bf8 100644 --- a/runtime/interpreter/mterp/x86_64/op_fill_array_data.S +++ b/runtime/interpreter/mterp/x86_64/op_fill_array_data.S @@ -1,3 +1,4 @@ +%def op_fill_array_data(): /* fill-array-data vAA, +BBBBBBBB */ EXPORT_PC movslq 2(rPC), %rcx # rcx <- ssssssssBBBBbbbb diff --git a/runtime/interpreter/mterp/x86_64/op_filled_new_array.S b/runtime/interpreter/mterp/x86_64/op_filled_new_array.S index a7f7ddc2a0..0f8b20e6aa 100644 --- a/runtime/interpreter/mterp/x86_64/op_filled_new_array.S +++ b/runtime/interpreter/mterp/x86_64/op_filled_new_array.S @@ -1,4 +1,4 @@ -%default { "helper":"MterpFilledNewArray" } +%def op_filled_new_array(helper="MterpFilledNewArray"): /* * Create a new array with elements filled from registers. * diff --git a/runtime/interpreter/mterp/x86_64/op_filled_new_array_range.S b/runtime/interpreter/mterp/x86_64/op_filled_new_array_range.S index 4ca79a3fe1..1667de149a 100644 --- a/runtime/interpreter/mterp/x86_64/op_filled_new_array_range.S +++ b/runtime/interpreter/mterp/x86_64/op_filled_new_array_range.S @@ -1 +1,2 @@ -%include "x86_64/op_filled_new_array.S" { "helper":"MterpFilledNewArrayRange" } +%def op_filled_new_array_range(): +% op_filled_new_array(helper="MterpFilledNewArrayRange") diff --git a/runtime/interpreter/mterp/x86_64/op_float_to_double.S b/runtime/interpreter/mterp/x86_64/op_float_to_double.S index 7855205575..a7cf8d3345 100644 --- a/runtime/interpreter/mterp/x86_64/op_float_to_double.S +++ b/runtime/interpreter/mterp/x86_64/op_float_to_double.S @@ -1 +1,2 @@ -%include "x86_64/fpcvt.S" {"source_suffix":"s","dest_suffix":"d","wide":"1"} +%def op_float_to_double(): +% fpcvt(source_suffix="s", dest_suffix="d", wide="1") diff --git a/runtime/interpreter/mterp/x86_64/op_float_to_int.S b/runtime/interpreter/mterp/x86_64/op_float_to_int.S index cb90555405..11955868a8 100644 --- a/runtime/interpreter/mterp/x86_64/op_float_to_int.S +++ b/runtime/interpreter/mterp/x86_64/op_float_to_int.S @@ -1 +1,2 @@ -%include "x86_64/cvtfp_int.S" {"fp_suffix":"s","i_suffix":"l","max_const":"$0x7fffffff","result_reg":"%eax","wide":"0"} +%def op_float_to_int(): +% cvtfp_int(fp_suffix="s", i_suffix="l", max_const="$0x7fffffff", result_reg="%eax", wide="0") diff --git a/runtime/interpreter/mterp/x86_64/op_float_to_long.S b/runtime/interpreter/mterp/x86_64/op_float_to_long.S index 96bb4eee6f..4548d6a47f 100644 --- a/runtime/interpreter/mterp/x86_64/op_float_to_long.S +++ b/runtime/interpreter/mterp/x86_64/op_float_to_long.S @@ -1 +1,2 @@ -%include "x86_64/cvtfp_int.S" {"fp_suffix":"s","i_suffix":"q","max_const":"$0x7fffffffffffffff","result_reg":"%rax","wide":"1"} +%def op_float_to_long(): +% cvtfp_int(fp_suffix="s", i_suffix="q", max_const="$0x7fffffffffffffff", result_reg="%rax", wide="1") diff --git a/runtime/interpreter/mterp/x86_64/op_goto.S b/runtime/interpreter/mterp/x86_64/op_goto.S index 9749901f5a..0659bbc0e6 100644 --- a/runtime/interpreter/mterp/x86_64/op_goto.S +++ b/runtime/interpreter/mterp/x86_64/op_goto.S @@ -1,3 +1,4 @@ +%def op_goto(): /* * Unconditional branch, 8-bit offset. * diff --git a/runtime/interpreter/mterp/x86_64/op_goto_16.S b/runtime/interpreter/mterp/x86_64/op_goto_16.S index 77688e05e4..1193f70aec 100644 --- a/runtime/interpreter/mterp/x86_64/op_goto_16.S +++ b/runtime/interpreter/mterp/x86_64/op_goto_16.S @@ -1,3 +1,4 @@ +%def op_goto_16(): /* * Unconditional branch, 16-bit offset. * diff --git a/runtime/interpreter/mterp/x86_64/op_goto_32.S b/runtime/interpreter/mterp/x86_64/op_goto_32.S index 29d777b5a6..cd0b522274 100644 --- a/runtime/interpreter/mterp/x86_64/op_goto_32.S +++ b/runtime/interpreter/mterp/x86_64/op_goto_32.S @@ -1,3 +1,4 @@ +%def op_goto_32(): /* * Unconditional branch, 32-bit offset. * diff --git a/runtime/interpreter/mterp/x86_64/op_if_eq.S b/runtime/interpreter/mterp/x86_64/op_if_eq.S index d56ce72461..4d1f6a54d2 100644 --- a/runtime/interpreter/mterp/x86_64/op_if_eq.S +++ b/runtime/interpreter/mterp/x86_64/op_if_eq.S @@ -1 +1,2 @@ -%include "x86_64/bincmp.S" { "revcmp":"ne" } +%def op_if_eq(): +% bincmp(revcmp="ne") diff --git a/runtime/interpreter/mterp/x86_64/op_if_eqz.S b/runtime/interpreter/mterp/x86_64/op_if_eqz.S index a0fc4448a3..12de558550 100644 --- a/runtime/interpreter/mterp/x86_64/op_if_eqz.S +++ b/runtime/interpreter/mterp/x86_64/op_if_eqz.S @@ -1 +1,2 @@ -%include "x86_64/zcmp.S" { "revcmp":"ne" } +%def op_if_eqz(): +% zcmp(revcmp="ne") diff --git a/runtime/interpreter/mterp/x86_64/op_if_ge.S b/runtime/interpreter/mterp/x86_64/op_if_ge.S index a7832efb68..684902776f 100644 --- a/runtime/interpreter/mterp/x86_64/op_if_ge.S +++ b/runtime/interpreter/mterp/x86_64/op_if_ge.S @@ -1 +1,2 @@ -%include "x86_64/bincmp.S" { "revcmp":"l" } +%def op_if_ge(): +% bincmp(revcmp="l") diff --git a/runtime/interpreter/mterp/x86_64/op_if_gez.S b/runtime/interpreter/mterp/x86_64/op_if_gez.S index f9af5db933..87bdcbfa32 100644 --- a/runtime/interpreter/mterp/x86_64/op_if_gez.S +++ b/runtime/interpreter/mterp/x86_64/op_if_gez.S @@ -1 +1,2 @@ -%include "x86_64/zcmp.S" { "revcmp":"l" } +%def op_if_gez(): +% zcmp(revcmp="l") diff --git a/runtime/interpreter/mterp/x86_64/op_if_gt.S b/runtime/interpreter/mterp/x86_64/op_if_gt.S index 70f2b9e12f..4a521006b3 100644 --- a/runtime/interpreter/mterp/x86_64/op_if_gt.S +++ b/runtime/interpreter/mterp/x86_64/op_if_gt.S @@ -1 +1,2 @@ -%include "x86_64/bincmp.S" { "revcmp":"le" } +%def op_if_gt(): +% bincmp(revcmp="le") diff --git a/runtime/interpreter/mterp/x86_64/op_if_gtz.S b/runtime/interpreter/mterp/x86_64/op_if_gtz.S index 2fb0d50937..a0b2e3a35b 100644 --- a/runtime/interpreter/mterp/x86_64/op_if_gtz.S +++ b/runtime/interpreter/mterp/x86_64/op_if_gtz.S @@ -1 +1,2 @@ -%include "x86_64/zcmp.S" { "revcmp":"le" } +%def op_if_gtz(): +% zcmp(revcmp="le") diff --git a/runtime/interpreter/mterp/x86_64/op_if_le.S b/runtime/interpreter/mterp/x86_64/op_if_le.S index 321962a040..69e94db79f 100644 --- a/runtime/interpreter/mterp/x86_64/op_if_le.S +++ b/runtime/interpreter/mterp/x86_64/op_if_le.S @@ -1 +1,2 @@ -%include "x86_64/bincmp.S" { "revcmp":"g" } +%def op_if_le(): +% bincmp(revcmp="g") diff --git a/runtime/interpreter/mterp/x86_64/op_if_lez.S b/runtime/interpreter/mterp/x86_64/op_if_lez.S index d3dc334f7b..42e69d969a 100644 --- a/runtime/interpreter/mterp/x86_64/op_if_lez.S +++ b/runtime/interpreter/mterp/x86_64/op_if_lez.S @@ -1 +1,2 @@ -%include "x86_64/zcmp.S" { "revcmp":"g" } +%def op_if_lez(): +% zcmp(revcmp="g") diff --git a/runtime/interpreter/mterp/x86_64/op_if_lt.S b/runtime/interpreter/mterp/x86_64/op_if_lt.S index f028005844..052aabe1e7 100644 --- a/runtime/interpreter/mterp/x86_64/op_if_lt.S +++ b/runtime/interpreter/mterp/x86_64/op_if_lt.S @@ -1 +1,2 @@ -%include "x86_64/bincmp.S" { "revcmp":"ge" } +%def op_if_lt(): +% bincmp(revcmp="ge") diff --git a/runtime/interpreter/mterp/x86_64/op_if_ltz.S b/runtime/interpreter/mterp/x86_64/op_if_ltz.S index 383d73aa7a..8e13e48c2a 100644 --- a/runtime/interpreter/mterp/x86_64/op_if_ltz.S +++ b/runtime/interpreter/mterp/x86_64/op_if_ltz.S @@ -1 +1,2 @@ -%include "x86_64/zcmp.S" { "revcmp":"ge" } +%def op_if_ltz(): +% zcmp(revcmp="ge") diff --git a/runtime/interpreter/mterp/x86_64/op_if_ne.S b/runtime/interpreter/mterp/x86_64/op_if_ne.S index ac6e063cd1..2cfd8a9a1e 100644 --- a/runtime/interpreter/mterp/x86_64/op_if_ne.S +++ b/runtime/interpreter/mterp/x86_64/op_if_ne.S @@ -1 +1,2 @@ -%include "x86_64/bincmp.S" { "revcmp":"e" } +%def op_if_ne(): +% bincmp(revcmp="e") diff --git a/runtime/interpreter/mterp/x86_64/op_if_nez.S b/runtime/interpreter/mterp/x86_64/op_if_nez.S index c96e4f3d16..261a173a38 100644 --- a/runtime/interpreter/mterp/x86_64/op_if_nez.S +++ b/runtime/interpreter/mterp/x86_64/op_if_nez.S @@ -1 +1,2 @@ -%include "x86_64/zcmp.S" { "revcmp":"e" } +%def op_if_nez(): +% zcmp(revcmp="e") diff --git a/runtime/interpreter/mterp/x86_64/op_iget.S b/runtime/interpreter/mterp/x86_64/op_iget.S index 4ab7c27c51..d09edc0a17 100644 --- a/runtime/interpreter/mterp/x86_64/op_iget.S +++ b/runtime/interpreter/mterp/x86_64/op_iget.S @@ -1,2 +1,2 @@ -%default { "is_object":"0", "helper":"MterpIGetU32"} -%include "x86_64/field.S" { } +%def op_iget(is_object="0", helper="MterpIGetU32"): +% field(helper=helper) diff --git a/runtime/interpreter/mterp/x86_64/op_iget_boolean.S b/runtime/interpreter/mterp/x86_64/op_iget_boolean.S index 18e9264926..cb8edeec77 100644 --- a/runtime/interpreter/mterp/x86_64/op_iget_boolean.S +++ b/runtime/interpreter/mterp/x86_64/op_iget_boolean.S @@ -1 +1,2 @@ -%include "x86_64/op_iget.S" { "helper":"MterpIGetU8" } +%def op_iget_boolean(): +% op_iget(helper="MterpIGetU8") diff --git a/runtime/interpreter/mterp/x86_64/op_iget_boolean_quick.S b/runtime/interpreter/mterp/x86_64/op_iget_boolean_quick.S index 07139c75ee..4e1676844b 100644 --- a/runtime/interpreter/mterp/x86_64/op_iget_boolean_quick.S +++ b/runtime/interpreter/mterp/x86_64/op_iget_boolean_quick.S @@ -1 +1,2 @@ -%include "x86_64/op_iget_quick.S" { "load":"movsbl" } +%def op_iget_boolean_quick(): +% op_iget_quick(load="movsbl") diff --git a/runtime/interpreter/mterp/x86_64/op_iget_byte.S b/runtime/interpreter/mterp/x86_64/op_iget_byte.S index bec0ad526c..2b87fb16b5 100644 --- a/runtime/interpreter/mterp/x86_64/op_iget_byte.S +++ b/runtime/interpreter/mterp/x86_64/op_iget_byte.S @@ -1 +1,2 @@ -%include "x86_64/op_iget.S" { "helper":"MterpIGetI8" } +%def op_iget_byte(): +% op_iget(helper="MterpIGetI8") diff --git a/runtime/interpreter/mterp/x86_64/op_iget_byte_quick.S b/runtime/interpreter/mterp/x86_64/op_iget_byte_quick.S index 07139c75ee..b92936c28d 100644 --- a/runtime/interpreter/mterp/x86_64/op_iget_byte_quick.S +++ b/runtime/interpreter/mterp/x86_64/op_iget_byte_quick.S @@ -1 +1,2 @@ -%include "x86_64/op_iget_quick.S" { "load":"movsbl" } +%def op_iget_byte_quick(): +% op_iget_quick(load="movsbl") diff --git a/runtime/interpreter/mterp/x86_64/op_iget_char.S b/runtime/interpreter/mterp/x86_64/op_iget_char.S index 5e22b88129..001bd03e2b 100644 --- a/runtime/interpreter/mterp/x86_64/op_iget_char.S +++ b/runtime/interpreter/mterp/x86_64/op_iget_char.S @@ -1 +1,2 @@ -%include "x86_64/op_iget.S" { "helper":"MterpIGetU16" } +%def op_iget_char(): +% op_iget(helper="MterpIGetU16") diff --git a/runtime/interpreter/mterp/x86_64/op_iget_char_quick.S b/runtime/interpreter/mterp/x86_64/op_iget_char_quick.S index 8cb3be3b65..d6f836b28e 100644 --- a/runtime/interpreter/mterp/x86_64/op_iget_char_quick.S +++ b/runtime/interpreter/mterp/x86_64/op_iget_char_quick.S @@ -1 +1,2 @@ -%include "x86_64/op_iget_quick.S" { "load":"movzwl" } +%def op_iget_char_quick(): +% op_iget_quick(load="movzwl") diff --git a/runtime/interpreter/mterp/x86_64/op_iget_object.S b/runtime/interpreter/mterp/x86_64/op_iget_object.S index bcef1d2c25..4e5f769547 100644 --- a/runtime/interpreter/mterp/x86_64/op_iget_object.S +++ b/runtime/interpreter/mterp/x86_64/op_iget_object.S @@ -1 +1,2 @@ -%include "x86_64/op_iget.S" { "is_object":"1", "helper":"MterpIGetObj" } +%def op_iget_object(): +% op_iget(is_object="1", helper="MterpIGetObj") diff --git a/runtime/interpreter/mterp/x86_64/op_iget_object_quick.S b/runtime/interpreter/mterp/x86_64/op_iget_object_quick.S index 176c9544ef..1969a25a0d 100644 --- a/runtime/interpreter/mterp/x86_64/op_iget_object_quick.S +++ b/runtime/interpreter/mterp/x86_64/op_iget_object_quick.S @@ -1,3 +1,4 @@ +%def op_iget_object_quick(): /* For: iget-object-quick */ /* op vA, vB, offset@CCCC */ .extern artIGetObjectFromMterp diff --git a/runtime/interpreter/mterp/x86_64/op_iget_quick.S b/runtime/interpreter/mterp/x86_64/op_iget_quick.S index bfb7530167..ba9e8e40e7 100644 --- a/runtime/interpreter/mterp/x86_64/op_iget_quick.S +++ b/runtime/interpreter/mterp/x86_64/op_iget_quick.S @@ -1,4 +1,4 @@ -%default { "load":"movl", "wide":"0"} +%def op_iget_quick(load="movl", wide="0"): /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick, iget-wide-quick */ /* op vA, vB, offset@CCCC */ movl rINST, %ecx # rcx <- BA diff --git a/runtime/interpreter/mterp/x86_64/op_iget_short.S b/runtime/interpreter/mterp/x86_64/op_iget_short.S index 14c49f7711..a62c4d998f 100644 --- a/runtime/interpreter/mterp/x86_64/op_iget_short.S +++ b/runtime/interpreter/mterp/x86_64/op_iget_short.S @@ -1 +1,2 @@ -%include "x86_64/op_iget.S" { "helper":"MterpIGetI16" } +%def op_iget_short(): +% op_iget(helper="MterpIGetI16") diff --git a/runtime/interpreter/mterp/x86_64/op_iget_short_quick.S b/runtime/interpreter/mterp/x86_64/op_iget_short_quick.S index 56ca858e74..f5e48d621a 100644 --- a/runtime/interpreter/mterp/x86_64/op_iget_short_quick.S +++ b/runtime/interpreter/mterp/x86_64/op_iget_short_quick.S @@ -1 +1,2 @@ -%include "x86_64/op_iget_quick.S" { "load":"movswl" } +%def op_iget_short_quick(): +% op_iget_quick(load="movswl") diff --git a/runtime/interpreter/mterp/x86_64/op_iget_wide.S b/runtime/interpreter/mterp/x86_64/op_iget_wide.S index a85a474845..9643cc3403 100644 --- a/runtime/interpreter/mterp/x86_64/op_iget_wide.S +++ b/runtime/interpreter/mterp/x86_64/op_iget_wide.S @@ -1 +1,2 @@ -%include "x86_64/op_iget.S" { "helper":"MterpIGetU64" } +%def op_iget_wide(): +% op_iget(helper="MterpIGetU64") diff --git a/runtime/interpreter/mterp/x86_64/op_iget_wide_quick.S b/runtime/interpreter/mterp/x86_64/op_iget_wide_quick.S index 169d625529..263ea8cff8 100644 --- a/runtime/interpreter/mterp/x86_64/op_iget_wide_quick.S +++ b/runtime/interpreter/mterp/x86_64/op_iget_wide_quick.S @@ -1 +1,2 @@ -%include "x86_64/op_iget_quick.S" { "load":"movswl", "wide":"1" } +%def op_iget_wide_quick(): +% op_iget_quick(load="movswl", wide="1") diff --git a/runtime/interpreter/mterp/x86_64/op_instance_of.S b/runtime/interpreter/mterp/x86_64/op_instance_of.S index 4819833658..237dd39868 100644 --- a/runtime/interpreter/mterp/x86_64/op_instance_of.S +++ b/runtime/interpreter/mterp/x86_64/op_instance_of.S @@ -1,3 +1,4 @@ +%def op_instance_of(): /* * Check to see if an object reference is an instance of a class. * diff --git a/runtime/interpreter/mterp/x86_64/op_int_to_byte.S b/runtime/interpreter/mterp/x86_64/op_int_to_byte.S index f4e578f868..80e4d5c310 100644 --- a/runtime/interpreter/mterp/x86_64/op_int_to_byte.S +++ b/runtime/interpreter/mterp/x86_64/op_int_to_byte.S @@ -1 +1,2 @@ -%include "x86_64/unop.S" {"instr":"movsbl %al, %eax"} +%def op_int_to_byte(): +% unop(instr="movsbl %al, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_int_to_char.S b/runtime/interpreter/mterp/x86_64/op_int_to_char.S index c1bf17f271..83e9868ef3 100644 --- a/runtime/interpreter/mterp/x86_64/op_int_to_char.S +++ b/runtime/interpreter/mterp/x86_64/op_int_to_char.S @@ -1 +1,2 @@ -%include "x86_64/unop.S" {"instr":"movzwl %ax,%eax"} +%def op_int_to_char(): +% unop(instr="movzwl %ax,%eax") diff --git a/runtime/interpreter/mterp/x86_64/op_int_to_double.S b/runtime/interpreter/mterp/x86_64/op_int_to_double.S index 27ebf42dbb..74e91ecebf 100644 --- a/runtime/interpreter/mterp/x86_64/op_int_to_double.S +++ b/runtime/interpreter/mterp/x86_64/op_int_to_double.S @@ -1 +1,2 @@ -%include "x86_64/fpcvt.S" {"source_suffix":"i","dest_suffix":"dl","wide":"1"} +%def op_int_to_double(): +% fpcvt(source_suffix="i", dest_suffix="dl", wide="1") diff --git a/runtime/interpreter/mterp/x86_64/op_int_to_float.S b/runtime/interpreter/mterp/x86_64/op_int_to_float.S index 5a98d44337..b57fc84d0d 100644 --- a/runtime/interpreter/mterp/x86_64/op_int_to_float.S +++ b/runtime/interpreter/mterp/x86_64/op_int_to_float.S @@ -1 +1,2 @@ -%include "x86_64/fpcvt.S" {"source_suffix":"i","dest_suffix":"sl","wide":"0"} +%def op_int_to_float(): +% fpcvt(source_suffix="i", dest_suffix="sl", wide="0") diff --git a/runtime/interpreter/mterp/x86_64/op_int_to_long.S b/runtime/interpreter/mterp/x86_64/op_int_to_long.S index 9281137a54..473d6a2ab7 100644 --- a/runtime/interpreter/mterp/x86_64/op_int_to_long.S +++ b/runtime/interpreter/mterp/x86_64/op_int_to_long.S @@ -1,3 +1,4 @@ +%def op_int_to_long(): /* int to long vA, vB */ movzbq rINSTbl, %rax # rax <- +A sarl $$4, %eax # eax <- B diff --git a/runtime/interpreter/mterp/x86_64/op_int_to_short.S b/runtime/interpreter/mterp/x86_64/op_int_to_short.S index 6ae6b50f34..e4db90b801 100644 --- a/runtime/interpreter/mterp/x86_64/op_int_to_short.S +++ b/runtime/interpreter/mterp/x86_64/op_int_to_short.S @@ -1 +1,2 @@ -%include "x86_64/unop.S" {"instr":"movswl %ax, %eax"} +%def op_int_to_short(): +% unop(instr="movswl %ax, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_custom.S b/runtime/interpreter/mterp/x86_64/op_invoke_custom.S index f4011f6d86..4bba9ee524 100644 --- a/runtime/interpreter/mterp/x86_64/op_invoke_custom.S +++ b/runtime/interpreter/mterp/x86_64/op_invoke_custom.S @@ -1 +1,2 @@ -%include "x86_64/invoke.S" { "helper":"MterpInvokeCustom" } +%def op_invoke_custom(): +% invoke(helper="MterpInvokeCustom") diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_custom_range.S b/runtime/interpreter/mterp/x86_64/op_invoke_custom_range.S index 94612c47d5..57e61af1fa 100644 --- a/runtime/interpreter/mterp/x86_64/op_invoke_custom_range.S +++ b/runtime/interpreter/mterp/x86_64/op_invoke_custom_range.S @@ -1 +1,2 @@ -%include "x86_64/invoke.S" { "helper":"MterpInvokeCustomRange" } +%def op_invoke_custom_range(): +% invoke(helper="MterpInvokeCustomRange") diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_direct.S b/runtime/interpreter/mterp/x86_64/op_invoke_direct.S index 9628589b03..d3139cf39b 100644 --- a/runtime/interpreter/mterp/x86_64/op_invoke_direct.S +++ b/runtime/interpreter/mterp/x86_64/op_invoke_direct.S @@ -1 +1,2 @@ -%include "x86_64/invoke.S" { "helper":"MterpInvokeDirect" } +%def op_invoke_direct(): +% invoke(helper="MterpInvokeDirect") diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_direct_range.S b/runtime/interpreter/mterp/x86_64/op_invoke_direct_range.S index 09ac8812fc..b4a161f48b 100644 --- a/runtime/interpreter/mterp/x86_64/op_invoke_direct_range.S +++ b/runtime/interpreter/mterp/x86_64/op_invoke_direct_range.S @@ -1 +1,2 @@ -%include "x86_64/invoke.S" { "helper":"MterpInvokeDirectRange" } +%def op_invoke_direct_range(): +% invoke(helper="MterpInvokeDirectRange") diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_interface.S b/runtime/interpreter/mterp/x86_64/op_invoke_interface.S index 76d9cd426f..559b9768d9 100644 --- a/runtime/interpreter/mterp/x86_64/op_invoke_interface.S +++ b/runtime/interpreter/mterp/x86_64/op_invoke_interface.S @@ -1,4 +1,5 @@ -%include "x86_64/invoke.S" { "helper":"MterpInvokeInterface" } +%def op_invoke_interface(): +% invoke(helper="MterpInvokeInterface") /* * Handle an interface method call. * diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_interface_range.S b/runtime/interpreter/mterp/x86_64/op_invoke_interface_range.S index 785b43c1a8..2989115377 100644 --- a/runtime/interpreter/mterp/x86_64/op_invoke_interface_range.S +++ b/runtime/interpreter/mterp/x86_64/op_invoke_interface_range.S @@ -1 +1,2 @@ -%include "x86_64/invoke.S" { "helper":"MterpInvokeInterfaceRange" } +%def op_invoke_interface_range(): +% invoke(helper="MterpInvokeInterfaceRange") diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_polymorphic.S b/runtime/interpreter/mterp/x86_64/op_invoke_polymorphic.S index 452944536d..ce61f5aa0e 100644 --- a/runtime/interpreter/mterp/x86_64/op_invoke_polymorphic.S +++ b/runtime/interpreter/mterp/x86_64/op_invoke_polymorphic.S @@ -1 +1,2 @@ -%include "x86_64/invoke_polymorphic.S" { "helper":"MterpInvokePolymorphic" } +%def op_invoke_polymorphic(): +% invoke_polymorphic(helper="MterpInvokePolymorphic") diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_polymorphic_range.S b/runtime/interpreter/mterp/x86_64/op_invoke_polymorphic_range.S index 01981c1b49..16731bdb40 100644 --- a/runtime/interpreter/mterp/x86_64/op_invoke_polymorphic_range.S +++ b/runtime/interpreter/mterp/x86_64/op_invoke_polymorphic_range.S @@ -1 +1,2 @@ -%include "x86_64/invoke_polymorphic.S" { "helper":"MterpInvokePolymorphicRange" } +%def op_invoke_polymorphic_range(): +% invoke_polymorphic(helper="MterpInvokePolymorphicRange") diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_static.S b/runtime/interpreter/mterp/x86_64/op_invoke_static.S index dd8027d58c..3e38d36a27 100644 --- a/runtime/interpreter/mterp/x86_64/op_invoke_static.S +++ b/runtime/interpreter/mterp/x86_64/op_invoke_static.S @@ -1,2 +1,3 @@ -%include "x86_64/invoke.S" { "helper":"MterpInvokeStatic" } +%def op_invoke_static(): +% invoke(helper="MterpInvokeStatic") diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_static_range.S b/runtime/interpreter/mterp/x86_64/op_invoke_static_range.S index ee26074f92..e0a546c92b 100644 --- a/runtime/interpreter/mterp/x86_64/op_invoke_static_range.S +++ b/runtime/interpreter/mterp/x86_64/op_invoke_static_range.S @@ -1 +1,2 @@ -%include "x86_64/invoke.S" { "helper":"MterpInvokeStaticRange" } +%def op_invoke_static_range(): +% invoke(helper="MterpInvokeStaticRange") diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_super.S b/runtime/interpreter/mterp/x86_64/op_invoke_super.S index d07f8d555b..5b2055010e 100644 --- a/runtime/interpreter/mterp/x86_64/op_invoke_super.S +++ b/runtime/interpreter/mterp/x86_64/op_invoke_super.S @@ -1,4 +1,5 @@ -%include "x86_64/invoke.S" { "helper":"MterpInvokeSuper" } +%def op_invoke_super(): +% invoke(helper="MterpInvokeSuper") /* * Handle a "super" method call. * diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_super_range.S b/runtime/interpreter/mterp/x86_64/op_invoke_super_range.S index 7245cfd405..caeafaa13c 100644 --- a/runtime/interpreter/mterp/x86_64/op_invoke_super_range.S +++ b/runtime/interpreter/mterp/x86_64/op_invoke_super_range.S @@ -1 +1,2 @@ -%include "x86_64/invoke.S" { "helper":"MterpInvokeSuperRange" } +%def op_invoke_super_range(): +% invoke(helper="MterpInvokeSuperRange") diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_virtual.S b/runtime/interpreter/mterp/x86_64/op_invoke_virtual.S index 19c708bd2a..e27eeedacc 100644 --- a/runtime/interpreter/mterp/x86_64/op_invoke_virtual.S +++ b/runtime/interpreter/mterp/x86_64/op_invoke_virtual.S @@ -1,4 +1,5 @@ -%include "x86_64/invoke.S" { "helper":"MterpInvokeVirtual" } +%def op_invoke_virtual(): +% invoke(helper="MterpInvokeVirtual") /* * Handle a virtual method call. * diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_virtual_quick.S b/runtime/interpreter/mterp/x86_64/op_invoke_virtual_quick.S index 313bd058b1..ea72c171ec 100644 --- a/runtime/interpreter/mterp/x86_64/op_invoke_virtual_quick.S +++ b/runtime/interpreter/mterp/x86_64/op_invoke_virtual_quick.S @@ -1 +1,2 @@ -%include "x86_64/invoke.S" { "helper":"MterpInvokeVirtualQuick" } +%def op_invoke_virtual_quick(): +% invoke(helper="MterpInvokeVirtualQuick") diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_virtual_range.S b/runtime/interpreter/mterp/x86_64/op_invoke_virtual_range.S index 424ad321a3..baa0779593 100644 --- a/runtime/interpreter/mterp/x86_64/op_invoke_virtual_range.S +++ b/runtime/interpreter/mterp/x86_64/op_invoke_virtual_range.S @@ -1 +1,2 @@ -%include "x86_64/invoke.S" { "helper":"MterpInvokeVirtualRange" } +%def op_invoke_virtual_range(): +% invoke(helper="MterpInvokeVirtualRange") diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_virtual_range_quick.S b/runtime/interpreter/mterp/x86_64/op_invoke_virtual_range_quick.S index 556f718ffb..1d961a0781 100644 --- a/runtime/interpreter/mterp/x86_64/op_invoke_virtual_range_quick.S +++ b/runtime/interpreter/mterp/x86_64/op_invoke_virtual_range_quick.S @@ -1 +1,2 @@ -%include "x86_64/invoke.S" { "helper":"MterpInvokeVirtualQuickRange" } +%def op_invoke_virtual_range_quick(): +% invoke(helper="MterpInvokeVirtualQuickRange") diff --git a/runtime/interpreter/mterp/x86_64/op_iput.S b/runtime/interpreter/mterp/x86_64/op_iput.S index dad5af664b..e5351baf55 100644 --- a/runtime/interpreter/mterp/x86_64/op_iput.S +++ b/runtime/interpreter/mterp/x86_64/op_iput.S @@ -1,2 +1,2 @@ -%default { "is_object":"0", "helper":"MterpIPutU32" } -%include "x86_64/field.S" { } +%def op_iput(is_object="0", helper="MterpIPutU32"): +% field(helper=helper) diff --git a/runtime/interpreter/mterp/x86_64/op_iput_boolean.S b/runtime/interpreter/mterp/x86_64/op_iput_boolean.S index 06bbd704d7..9eb849877b 100644 --- a/runtime/interpreter/mterp/x86_64/op_iput_boolean.S +++ b/runtime/interpreter/mterp/x86_64/op_iput_boolean.S @@ -1 +1,2 @@ -%include "x86_64/op_iput.S" { "helper":"MterpIPutU8" } +%def op_iput_boolean(): +% op_iput(helper="MterpIPutU8") diff --git a/runtime/interpreter/mterp/x86_64/op_iput_boolean_quick.S b/runtime/interpreter/mterp/x86_64/op_iput_boolean_quick.S index 6bd060e4f3..c304c76b51 100644 --- a/runtime/interpreter/mterp/x86_64/op_iput_boolean_quick.S +++ b/runtime/interpreter/mterp/x86_64/op_iput_boolean_quick.S @@ -1 +1,2 @@ -%include "x86_64/op_iput_quick.S" { "reg":"rINSTbl", "store":"movb" } +%def op_iput_boolean_quick(): +% op_iput_quick(reg="rINSTbl", store="movb") diff --git a/runtime/interpreter/mterp/x86_64/op_iput_byte.S b/runtime/interpreter/mterp/x86_64/op_iput_byte.S index 53f9008eb5..4b74f9fb0e 100644 --- a/runtime/interpreter/mterp/x86_64/op_iput_byte.S +++ b/runtime/interpreter/mterp/x86_64/op_iput_byte.S @@ -1 +1,2 @@ -%include "x86_64/op_iput.S" { "helper":"MterpIPutI8" } +%def op_iput_byte(): +% op_iput(helper="MterpIPutI8") diff --git a/runtime/interpreter/mterp/x86_64/op_iput_byte_quick.S b/runtime/interpreter/mterp/x86_64/op_iput_byte_quick.S index 6bd060e4f3..dac18e63cc 100644 --- a/runtime/interpreter/mterp/x86_64/op_iput_byte_quick.S +++ b/runtime/interpreter/mterp/x86_64/op_iput_byte_quick.S @@ -1 +1,2 @@ -%include "x86_64/op_iput_quick.S" { "reg":"rINSTbl", "store":"movb" } +%def op_iput_byte_quick(): +% op_iput_quick(reg="rINSTbl", store="movb") diff --git a/runtime/interpreter/mterp/x86_64/op_iput_char.S b/runtime/interpreter/mterp/x86_64/op_iput_char.S index 4736f5e9d4..64a249fc12 100644 --- a/runtime/interpreter/mterp/x86_64/op_iput_char.S +++ b/runtime/interpreter/mterp/x86_64/op_iput_char.S @@ -1 +1,2 @@ -%include "x86_64/op_iput.S" { "helper":"MterpIPutU16" } +%def op_iput_char(): +% op_iput(helper="MterpIPutU16") diff --git a/runtime/interpreter/mterp/x86_64/op_iput_char_quick.S b/runtime/interpreter/mterp/x86_64/op_iput_char_quick.S index 3da96d53af..21a25812b1 100644 --- a/runtime/interpreter/mterp/x86_64/op_iput_char_quick.S +++ b/runtime/interpreter/mterp/x86_64/op_iput_char_quick.S @@ -1 +1,2 @@ -%include "x86_64/op_iput_quick.S" { "reg":"rINSTw", "store":"movw" } +%def op_iput_char_quick(): +% op_iput_quick(reg="rINSTw", store="movw") diff --git a/runtime/interpreter/mterp/x86_64/op_iput_object.S b/runtime/interpreter/mterp/x86_64/op_iput_object.S index 202e33fa76..131edd5dbd 100644 --- a/runtime/interpreter/mterp/x86_64/op_iput_object.S +++ b/runtime/interpreter/mterp/x86_64/op_iput_object.S @@ -1 +1,2 @@ -%include "x86_64/op_iput.S" { "is_object":"1", "helper":"MterpIPutObj" } +%def op_iput_object(): +% op_iput(is_object="1", helper="MterpIPutObj") diff --git a/runtime/interpreter/mterp/x86_64/op_iput_object_quick.S b/runtime/interpreter/mterp/x86_64/op_iput_object_quick.S index b5b128ab7f..e41540d5b7 100644 --- a/runtime/interpreter/mterp/x86_64/op_iput_object_quick.S +++ b/runtime/interpreter/mterp/x86_64/op_iput_object_quick.S @@ -1,3 +1,4 @@ +%def op_iput_object_quick(): EXPORT_PC leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG0 movq rPC, OUT_ARG1 diff --git a/runtime/interpreter/mterp/x86_64/op_iput_quick.S b/runtime/interpreter/mterp/x86_64/op_iput_quick.S index ecaf98e415..3cbb7e99c3 100644 --- a/runtime/interpreter/mterp/x86_64/op_iput_quick.S +++ b/runtime/interpreter/mterp/x86_64/op_iput_quick.S @@ -1,4 +1,4 @@ -%default { "reg":"rINST", "store":"movl" } +%def op_iput_quick(reg="rINST", store="movl"): /* For: iput-quick, iput-object-quick */ /* op vA, vB, offset@CCCC */ movzbq rINSTbl, %rcx # rcx <- BA diff --git a/runtime/interpreter/mterp/x86_64/op_iput_short.S b/runtime/interpreter/mterp/x86_64/op_iput_short.S index dca5735963..e631a3b259 100644 --- a/runtime/interpreter/mterp/x86_64/op_iput_short.S +++ b/runtime/interpreter/mterp/x86_64/op_iput_short.S @@ -1 +1,2 @@ -%include "x86_64/op_iput.S" { "helper":"MterpIPutI16" } +%def op_iput_short(): +% op_iput(helper="MterpIPutI16") diff --git a/runtime/interpreter/mterp/x86_64/op_iput_short_quick.S b/runtime/interpreter/mterp/x86_64/op_iput_short_quick.S index 3da96d53af..5eb28d6922 100644 --- a/runtime/interpreter/mterp/x86_64/op_iput_short_quick.S +++ b/runtime/interpreter/mterp/x86_64/op_iput_short_quick.S @@ -1 +1,2 @@ -%include "x86_64/op_iput_quick.S" { "reg":"rINSTw", "store":"movw" } +%def op_iput_short_quick(): +% op_iput_quick(reg="rINSTw", store="movw") diff --git a/runtime/interpreter/mterp/x86_64/op_iput_wide.S b/runtime/interpreter/mterp/x86_64/op_iput_wide.S index db520167d2..2f34fd39f9 100644 --- a/runtime/interpreter/mterp/x86_64/op_iput_wide.S +++ b/runtime/interpreter/mterp/x86_64/op_iput_wide.S @@ -1 +1,2 @@ -%include "x86_64/op_iput.S" { "helper":"MterpIPutU64" } +%def op_iput_wide(): +% op_iput(helper="MterpIPutU64") diff --git a/runtime/interpreter/mterp/x86_64/op_iput_wide_quick.S b/runtime/interpreter/mterp/x86_64/op_iput_wide_quick.S index 473189d007..a13a6340ef 100644 --- a/runtime/interpreter/mterp/x86_64/op_iput_wide_quick.S +++ b/runtime/interpreter/mterp/x86_64/op_iput_wide_quick.S @@ -1,3 +1,4 @@ +%def op_iput_wide_quick(): /* iput-wide-quick vA, vB, offset@CCCC */ movzbq rINSTbl, %rcx # rcx<- BA sarl $$4, %ecx # ecx<- B diff --git a/runtime/interpreter/mterp/x86_64/op_long_to_double.S b/runtime/interpreter/mterp/x86_64/op_long_to_double.S index 7cdae32373..6b2d7bf574 100644 --- a/runtime/interpreter/mterp/x86_64/op_long_to_double.S +++ b/runtime/interpreter/mterp/x86_64/op_long_to_double.S @@ -1 +1,2 @@ -%include "x86_64/fpcvt.S" {"source_suffix":"i","dest_suffix":"dq","wide":"1"} +%def op_long_to_double(): +% fpcvt(source_suffix="i", dest_suffix="dq", wide="1") diff --git a/runtime/interpreter/mterp/x86_64/op_long_to_float.S b/runtime/interpreter/mterp/x86_64/op_long_to_float.S index 7553348633..7c2edfd613 100644 --- a/runtime/interpreter/mterp/x86_64/op_long_to_float.S +++ b/runtime/interpreter/mterp/x86_64/op_long_to_float.S @@ -1 +1,2 @@ -%include "x86_64/fpcvt.S" {"source_suffix":"i","dest_suffix":"sq","wide":"0"} +%def op_long_to_float(): +% fpcvt(source_suffix="i", dest_suffix="sq", wide="0") diff --git a/runtime/interpreter/mterp/x86_64/op_long_to_int.S b/runtime/interpreter/mterp/x86_64/op_long_to_int.S index 7b50c8e0b3..eacb8f59ec 100644 --- a/runtime/interpreter/mterp/x86_64/op_long_to_int.S +++ b/runtime/interpreter/mterp/x86_64/op_long_to_int.S @@ -1,2 +1,3 @@ +%def op_long_to_int(): /* we ignore the high word, making this equivalent to a 32-bit reg move */ -%include "x86_64/op_move.S" +% op_move() diff --git a/runtime/interpreter/mterp/x86_64/op_monitor_enter.S b/runtime/interpreter/mterp/x86_64/op_monitor_enter.S index 411091f23e..7865156c25 100644 --- a/runtime/interpreter/mterp/x86_64/op_monitor_enter.S +++ b/runtime/interpreter/mterp/x86_64/op_monitor_enter.S @@ -1,3 +1,4 @@ +%def op_monitor_enter(): /* * Synchronize on an object. */ diff --git a/runtime/interpreter/mterp/x86_64/op_monitor_exit.S b/runtime/interpreter/mterp/x86_64/op_monitor_exit.S index 72d9a23a87..6422bc8759 100644 --- a/runtime/interpreter/mterp/x86_64/op_monitor_exit.S +++ b/runtime/interpreter/mterp/x86_64/op_monitor_exit.S @@ -1,3 +1,4 @@ +%def op_monitor_exit(): /* * Unlock an object. * diff --git a/runtime/interpreter/mterp/x86_64/op_move.S b/runtime/interpreter/mterp/x86_64/op_move.S index ccaac2caa8..0ccf228ee8 100644 --- a/runtime/interpreter/mterp/x86_64/op_move.S +++ b/runtime/interpreter/mterp/x86_64/op_move.S @@ -1,4 +1,4 @@ -%default { "is_object":"0" } +%def op_move(is_object="0"): /* for move, move-object, long-to-int */ /* op vA, vB */ movl rINST, %eax # eax <- BA diff --git a/runtime/interpreter/mterp/x86_64/op_move_16.S b/runtime/interpreter/mterp/x86_64/op_move_16.S index 6a813eb5ce..238f089bef 100644 --- a/runtime/interpreter/mterp/x86_64/op_move_16.S +++ b/runtime/interpreter/mterp/x86_64/op_move_16.S @@ -1,4 +1,4 @@ -%default { "is_object":"0" } +%def op_move_16(is_object="0"): /* for: move/16, move-object/16 */ /* op vAAAA, vBBBB */ movzwq 4(rPC), %rcx # ecx <- BBBB diff --git a/runtime/interpreter/mterp/x86_64/op_move_exception.S b/runtime/interpreter/mterp/x86_64/op_move_exception.S index 33db878236..9d87f7c8f7 100644 --- a/runtime/interpreter/mterp/x86_64/op_move_exception.S +++ b/runtime/interpreter/mterp/x86_64/op_move_exception.S @@ -1,3 +1,4 @@ +%def op_move_exception(): /* move-exception vAA */ movq rSELF, %rcx movl THREAD_EXCEPTION_OFFSET(%rcx), %eax diff --git a/runtime/interpreter/mterp/x86_64/op_move_from16.S b/runtime/interpreter/mterp/x86_64/op_move_from16.S index 150e9c2f2c..6163e6d37d 100644 --- a/runtime/interpreter/mterp/x86_64/op_move_from16.S +++ b/runtime/interpreter/mterp/x86_64/op_move_from16.S @@ -1,4 +1,4 @@ -%default { "is_object":"0" } +%def op_move_from16(is_object="0"): /* for: move/from16, move-object/from16 */ /* op vAA, vBBBB */ movzwq 2(rPC), %rax # eax <- BBBB diff --git a/runtime/interpreter/mterp/x86_64/op_move_object.S b/runtime/interpreter/mterp/x86_64/op_move_object.S index 0d866496e8..dbb4d59710 100644 --- a/runtime/interpreter/mterp/x86_64/op_move_object.S +++ b/runtime/interpreter/mterp/x86_64/op_move_object.S @@ -1 +1,2 @@ -%include "x86_64/op_move.S" {"is_object":"1"} +%def op_move_object(): +% op_move(is_object="1") diff --git a/runtime/interpreter/mterp/x86_64/op_move_object_16.S b/runtime/interpreter/mterp/x86_64/op_move_object_16.S index 32541ff2bf..40120379d5 100644 --- a/runtime/interpreter/mterp/x86_64/op_move_object_16.S +++ b/runtime/interpreter/mterp/x86_64/op_move_object_16.S @@ -1 +1,2 @@ -%include "x86_64/op_move_16.S" {"is_object":"1"} +%def op_move_object_16(): +% op_move_16(is_object="1") diff --git a/runtime/interpreter/mterp/x86_64/op_move_object_from16.S b/runtime/interpreter/mterp/x86_64/op_move_object_from16.S index 983e4abae5..c82698e81e 100644 --- a/runtime/interpreter/mterp/x86_64/op_move_object_from16.S +++ b/runtime/interpreter/mterp/x86_64/op_move_object_from16.S @@ -1 +1,2 @@ -%include "x86_64/op_move_from16.S" {"is_object":"1"} +%def op_move_object_from16(): +% op_move_from16(is_object="1") diff --git a/runtime/interpreter/mterp/x86_64/op_move_result.S b/runtime/interpreter/mterp/x86_64/op_move_result.S index 8268344bce..a089623bca 100644 --- a/runtime/interpreter/mterp/x86_64/op_move_result.S +++ b/runtime/interpreter/mterp/x86_64/op_move_result.S @@ -1,4 +1,4 @@ -%default { "is_object":"0" } +%def op_move_result(is_object="0"): /* for: move-result, move-result-object */ /* op vAA */ movq OFF_FP_RESULT_REGISTER(rFP), %rax # get pointer to result JType. diff --git a/runtime/interpreter/mterp/x86_64/op_move_result_object.S b/runtime/interpreter/mterp/x86_64/op_move_result_object.S index c5aac17f41..87aea2646a 100644 --- a/runtime/interpreter/mterp/x86_64/op_move_result_object.S +++ b/runtime/interpreter/mterp/x86_64/op_move_result_object.S @@ -1 +1,2 @@ -%include "x86_64/op_move_result.S" {"is_object":"1"} +%def op_move_result_object(): +% op_move_result(is_object="1") diff --git a/runtime/interpreter/mterp/x86_64/op_move_result_wide.S b/runtime/interpreter/mterp/x86_64/op_move_result_wide.S index 03de783627..80f49aaa15 100644 --- a/runtime/interpreter/mterp/x86_64/op_move_result_wide.S +++ b/runtime/interpreter/mterp/x86_64/op_move_result_wide.S @@ -1,3 +1,4 @@ +%def op_move_result_wide(): /* move-result-wide vAA */ movq OFF_FP_RESULT_REGISTER(rFP), %rax # get pointer to result JType. movq (%rax), %rdx # Get wide diff --git a/runtime/interpreter/mterp/x86_64/op_move_wide.S b/runtime/interpreter/mterp/x86_64/op_move_wide.S index 508f8cc152..afb67efd10 100644 --- a/runtime/interpreter/mterp/x86_64/op_move_wide.S +++ b/runtime/interpreter/mterp/x86_64/op_move_wide.S @@ -1,3 +1,4 @@ +%def op_move_wide(): /* move-wide vA, vB */ /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ movl rINST, %ecx # ecx <- BA diff --git a/runtime/interpreter/mterp/x86_64/op_move_wide_16.S b/runtime/interpreter/mterp/x86_64/op_move_wide_16.S index ce371a920e..b4de5206fd 100644 --- a/runtime/interpreter/mterp/x86_64/op_move_wide_16.S +++ b/runtime/interpreter/mterp/x86_64/op_move_wide_16.S @@ -1,3 +1,4 @@ +%def op_move_wide_16(): /* move-wide/16 vAAAA, vBBBB */ /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ movzwq 4(rPC), %rcx # ecx<- BBBB diff --git a/runtime/interpreter/mterp/x86_64/op_move_wide_from16.S b/runtime/interpreter/mterp/x86_64/op_move_wide_from16.S index 0d6971a674..c4389a4873 100644 --- a/runtime/interpreter/mterp/x86_64/op_move_wide_from16.S +++ b/runtime/interpreter/mterp/x86_64/op_move_wide_from16.S @@ -1,3 +1,4 @@ +%def op_move_wide_from16(): /* move-wide/from16 vAA, vBBBB */ /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ movzwl 2(rPC), %ecx # ecx <- BBBB diff --git a/runtime/interpreter/mterp/x86_64/op_mul_double.S b/runtime/interpreter/mterp/x86_64/op_mul_double.S index 1f4bcb3d00..5353028798 100644 --- a/runtime/interpreter/mterp/x86_64/op_mul_double.S +++ b/runtime/interpreter/mterp/x86_64/op_mul_double.S @@ -1 +1,2 @@ -%include "x86_64/sseBinop.S" {"instr":"muls","suff":"d"} +%def op_mul_double(): +% sseBinop(instr="muls", suff="d") diff --git a/runtime/interpreter/mterp/x86_64/op_mul_double_2addr.S b/runtime/interpreter/mterp/x86_64/op_mul_double_2addr.S index 9850a28995..7a6dcd0cb8 100644 --- a/runtime/interpreter/mterp/x86_64/op_mul_double_2addr.S +++ b/runtime/interpreter/mterp/x86_64/op_mul_double_2addr.S @@ -1 +1,2 @@ -%include "x86_64/sseBinop2Addr.S" {"instr":"muls","suff":"d"} +%def op_mul_double_2addr(): +% sseBinop2Addr(instr="muls", suff="d") diff --git a/runtime/interpreter/mterp/x86_64/op_mul_float.S b/runtime/interpreter/mterp/x86_64/op_mul_float.S index 85960e9dec..b9eeeeeb69 100644 --- a/runtime/interpreter/mterp/x86_64/op_mul_float.S +++ b/runtime/interpreter/mterp/x86_64/op_mul_float.S @@ -1 +1,2 @@ -%include "x86_64/sseBinop.S" {"instr":"muls","suff":"s"} +%def op_mul_float(): +% sseBinop(instr="muls", suff="s") diff --git a/runtime/interpreter/mterp/x86_64/op_mul_float_2addr.S b/runtime/interpreter/mterp/x86_64/op_mul_float_2addr.S index 6d36b6a178..949af7b254 100644 --- a/runtime/interpreter/mterp/x86_64/op_mul_float_2addr.S +++ b/runtime/interpreter/mterp/x86_64/op_mul_float_2addr.S @@ -1 +1,2 @@ -%include "x86_64/sseBinop2Addr.S" {"instr":"muls","suff":"s"} +%def op_mul_float_2addr(): +% sseBinop2Addr(instr="muls", suff="s") diff --git a/runtime/interpreter/mterp/x86_64/op_mul_int.S b/runtime/interpreter/mterp/x86_64/op_mul_int.S index 5f3923a20e..51abae6294 100644 --- a/runtime/interpreter/mterp/x86_64/op_mul_int.S +++ b/runtime/interpreter/mterp/x86_64/op_mul_int.S @@ -1 +1,2 @@ -%include "x86_64/binop.S" {"instr":"imull (rFP,%rcx,4), %eax"} +%def op_mul_int(): +% binop(instr="imull (rFP,%rcx,4), %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_mul_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_mul_int_2addr.S index 0b5af8a927..fb2ec89245 100644 --- a/runtime/interpreter/mterp/x86_64/op_mul_int_2addr.S +++ b/runtime/interpreter/mterp/x86_64/op_mul_int_2addr.S @@ -1,3 +1,4 @@ +%def op_mul_int_2addr(): /* mul vA, vB */ movl rINST, %ecx # rcx <- A+ sarl $$4, rINST # rINST <- B diff --git a/runtime/interpreter/mterp/x86_64/op_mul_int_lit16.S b/runtime/interpreter/mterp/x86_64/op_mul_int_lit16.S index a4cfdbce3e..a0b1e714c6 100644 --- a/runtime/interpreter/mterp/x86_64/op_mul_int_lit16.S +++ b/runtime/interpreter/mterp/x86_64/op_mul_int_lit16.S @@ -1 +1,2 @@ -%include "x86_64/binopLit16.S" {"instr":"imull %ecx, %eax"} +%def op_mul_int_lit16(): +% binopLit16(instr="imull %ecx, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_mul_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_mul_int_lit8.S index 89e9acb77d..e68e7f7e2f 100644 --- a/runtime/interpreter/mterp/x86_64/op_mul_int_lit8.S +++ b/runtime/interpreter/mterp/x86_64/op_mul_int_lit8.S @@ -1 +1,2 @@ -%include "x86_64/binopLit8.S" {"instr":"imull %ecx, %eax"} +%def op_mul_int_lit8(): +% binopLit8(instr="imull %ecx, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_mul_long.S b/runtime/interpreter/mterp/x86_64/op_mul_long.S index 2b853705cf..e5bffa4035 100644 --- a/runtime/interpreter/mterp/x86_64/op_mul_long.S +++ b/runtime/interpreter/mterp/x86_64/op_mul_long.S @@ -1 +1,2 @@ -%include "x86_64/binopWide.S" {"instr":"imulq (rFP,%rcx,4), %rax"} +%def op_mul_long(): +% binopWide(instr="imulq (rFP,%rcx,4), %rax") diff --git a/runtime/interpreter/mterp/x86_64/op_mul_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_mul_long_2addr.S index 167128b4d1..25ffc148a5 100644 --- a/runtime/interpreter/mterp/x86_64/op_mul_long_2addr.S +++ b/runtime/interpreter/mterp/x86_64/op_mul_long_2addr.S @@ -1,3 +1,4 @@ +%def op_mul_long_2addr(): /* mul vA, vB */ movl rINST, %ecx # rcx <- A+ sarl $$4, rINST # rINST <- B diff --git a/runtime/interpreter/mterp/x86_64/op_neg_double.S b/runtime/interpreter/mterp/x86_64/op_neg_double.S index 2c14b091cb..56e38041b1 100644 --- a/runtime/interpreter/mterp/x86_64/op_neg_double.S +++ b/runtime/interpreter/mterp/x86_64/op_neg_double.S @@ -1 +1,2 @@ -%include "x86_64/unop.S" {"preinstr":" movq $0x8000000000000000, %rsi", "instr":" xorq %rsi, %rax", "wide":"1"} +%def op_neg_double(): +% unop(preinstr=" movq $0x8000000000000000, %rsi", instr=" xorq %rsi, %rax", wide="1") diff --git a/runtime/interpreter/mterp/x86_64/op_neg_float.S b/runtime/interpreter/mterp/x86_64/op_neg_float.S index 148b21ec9a..6a39444963 100644 --- a/runtime/interpreter/mterp/x86_64/op_neg_float.S +++ b/runtime/interpreter/mterp/x86_64/op_neg_float.S @@ -1 +1,2 @@ -%include "x86_64/unop.S" {"instr":" xorl $0x80000000, %eax"} +%def op_neg_float(): +% unop(instr=" xorl $0x80000000, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_neg_int.S b/runtime/interpreter/mterp/x86_64/op_neg_int.S index f90a937a8b..44790edd51 100644 --- a/runtime/interpreter/mterp/x86_64/op_neg_int.S +++ b/runtime/interpreter/mterp/x86_64/op_neg_int.S @@ -1 +1,2 @@ -%include "x86_64/unop.S" {"instr":" negl %eax"} +%def op_neg_int(): +% unop(instr=" negl %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_neg_long.S b/runtime/interpreter/mterp/x86_64/op_neg_long.S index 18fc3ccece..2d296ee19d 100644 --- a/runtime/interpreter/mterp/x86_64/op_neg_long.S +++ b/runtime/interpreter/mterp/x86_64/op_neg_long.S @@ -1 +1,2 @@ -%include "x86_64/unop.S" {"instr":" negq %rax", "wide":"1"} +%def op_neg_long(): +% unop(instr=" negq %rax", wide="1") diff --git a/runtime/interpreter/mterp/x86_64/op_new_array.S b/runtime/interpreter/mterp/x86_64/op_new_array.S index 9831a0b888..de1b0016d2 100644 --- a/runtime/interpreter/mterp/x86_64/op_new_array.S +++ b/runtime/interpreter/mterp/x86_64/op_new_array.S @@ -1,3 +1,4 @@ +%def op_new_array(): /* * Allocate an array of objects, specified with the array class * and a count. diff --git a/runtime/interpreter/mterp/x86_64/op_new_instance.S b/runtime/interpreter/mterp/x86_64/op_new_instance.S index fc8c8cd98c..cc3f31cb5e 100644 --- a/runtime/interpreter/mterp/x86_64/op_new_instance.S +++ b/runtime/interpreter/mterp/x86_64/op_new_instance.S @@ -1,3 +1,4 @@ +%def op_new_instance(): /* * Create a new instance of a class. */ diff --git a/runtime/interpreter/mterp/x86_64/op_nop.S b/runtime/interpreter/mterp/x86_64/op_nop.S index 4cb68e392e..aa4a843ab5 100644 --- a/runtime/interpreter/mterp/x86_64/op_nop.S +++ b/runtime/interpreter/mterp/x86_64/op_nop.S @@ -1 +1,2 @@ +%def op_nop(): ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86_64/op_not_int.S b/runtime/interpreter/mterp/x86_64/op_not_int.S index 463d080de9..55ac8a7ff3 100644 --- a/runtime/interpreter/mterp/x86_64/op_not_int.S +++ b/runtime/interpreter/mterp/x86_64/op_not_int.S @@ -1 +1,2 @@ -%include "x86_64/unop.S" {"instr":" notl %eax"} +%def op_not_int(): +% unop(instr=" notl %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_not_long.S b/runtime/interpreter/mterp/x86_64/op_not_long.S index c97bb9ea1a..c6c0f859c3 100644 --- a/runtime/interpreter/mterp/x86_64/op_not_long.S +++ b/runtime/interpreter/mterp/x86_64/op_not_long.S @@ -1 +1,2 @@ -%include "x86_64/unop.S" {"instr":" notq %rax", "wide":"1"} +%def op_not_long(): +% unop(instr=" notq %rax", wide="1") diff --git a/runtime/interpreter/mterp/x86_64/op_or_int.S b/runtime/interpreter/mterp/x86_64/op_or_int.S index 730310f6af..0e6dd67c27 100644 --- a/runtime/interpreter/mterp/x86_64/op_or_int.S +++ b/runtime/interpreter/mterp/x86_64/op_or_int.S @@ -1 +1,2 @@ -%include "x86_64/binop.S" {"instr":"orl (rFP,%rcx,4), %eax"} +%def op_or_int(): +% binop(instr="orl (rFP,%rcx,4), %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_or_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_or_int_2addr.S index f722e4dd9c..c722938c82 100644 --- a/runtime/interpreter/mterp/x86_64/op_or_int_2addr.S +++ b/runtime/interpreter/mterp/x86_64/op_or_int_2addr.S @@ -1 +1,2 @@ -%include "x86_64/binop2addr.S" {"instr":"orl %eax, (rFP,%rcx,4)"} +%def op_or_int_2addr(): +% binop2addr(instr="orl %eax, (rFP,%rcx,4)") diff --git a/runtime/interpreter/mterp/x86_64/op_or_int_lit16.S b/runtime/interpreter/mterp/x86_64/op_or_int_lit16.S index fee86c7c62..ba9b6bff18 100644 --- a/runtime/interpreter/mterp/x86_64/op_or_int_lit16.S +++ b/runtime/interpreter/mterp/x86_64/op_or_int_lit16.S @@ -1 +1,2 @@ -%include "x86_64/binopLit16.S" {"instr":"orl %ecx, %eax"} +%def op_or_int_lit16(): +% binopLit16(instr="orl %ecx, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_or_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_or_int_lit8.S index 81104c7e56..758109bc05 100644 --- a/runtime/interpreter/mterp/x86_64/op_or_int_lit8.S +++ b/runtime/interpreter/mterp/x86_64/op_or_int_lit8.S @@ -1 +1,2 @@ -%include "x86_64/binopLit8.S" {"instr":"orl %ecx, %eax"} +%def op_or_int_lit8(): +% binopLit8(instr="orl %ecx, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_or_long.S b/runtime/interpreter/mterp/x86_64/op_or_long.S index 6c70a2001e..b9c9321b2e 100644 --- a/runtime/interpreter/mterp/x86_64/op_or_long.S +++ b/runtime/interpreter/mterp/x86_64/op_or_long.S @@ -1 +1,2 @@ -%include "x86_64/binopWide.S" {"instr":"orq (rFP,%rcx,4), %rax"} +%def op_or_long(): +% binopWide(instr="orq (rFP,%rcx,4), %rax") diff --git a/runtime/interpreter/mterp/x86_64/op_or_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_or_long_2addr.S index 546da1de2d..616288e315 100644 --- a/runtime/interpreter/mterp/x86_64/op_or_long_2addr.S +++ b/runtime/interpreter/mterp/x86_64/op_or_long_2addr.S @@ -1 +1,2 @@ -%include "x86_64/binopWide2addr.S" {"instr":"orq %rax, (rFP,%rcx,4)"} +%def op_or_long_2addr(): +% binopWide2addr(instr="orq %rax, (rFP,%rcx,4)") diff --git a/runtime/interpreter/mterp/x86_64/op_packed_switch.S b/runtime/interpreter/mterp/x86_64/op_packed_switch.S index 148552f77e..8b2b18b8cd 100644 --- a/runtime/interpreter/mterp/x86_64/op_packed_switch.S +++ b/runtime/interpreter/mterp/x86_64/op_packed_switch.S @@ -1,4 +1,4 @@ -%default { "func":"MterpDoPackedSwitch" } +%def op_packed_switch(func="MterpDoPackedSwitch"): /* * Handle a packed-switch or sparse-switch instruction. In both cases * we decode it and hand it off to a helper function. diff --git a/runtime/interpreter/mterp/x86_64/op_rem_double.S b/runtime/interpreter/mterp/x86_64/op_rem_double.S index 00aed787cb..9b1c0b4bdc 100644 --- a/runtime/interpreter/mterp/x86_64/op_rem_double.S +++ b/runtime/interpreter/mterp/x86_64/op_rem_double.S @@ -1,3 +1,4 @@ +%def op_rem_double(): /* rem_double vAA, vBB, vCC */ movzbq 3(rPC), %rcx # ecx <- BB movzbq 2(rPC), %rax # eax <- CC diff --git a/runtime/interpreter/mterp/x86_64/op_rem_double_2addr.S b/runtime/interpreter/mterp/x86_64/op_rem_double_2addr.S index 9768266e21..0600e90dfb 100644 --- a/runtime/interpreter/mterp/x86_64/op_rem_double_2addr.S +++ b/runtime/interpreter/mterp/x86_64/op_rem_double_2addr.S @@ -1,3 +1,4 @@ +%def op_rem_double_2addr(): /* rem_double/2addr vA, vB */ movzbq rINSTbl, %rcx # ecx <- A+ sarl $$4, rINST # rINST <- B diff --git a/runtime/interpreter/mterp/x86_64/op_rem_float.S b/runtime/interpreter/mterp/x86_64/op_rem_float.S index 5af28accec..28c1328e7c 100644 --- a/runtime/interpreter/mterp/x86_64/op_rem_float.S +++ b/runtime/interpreter/mterp/x86_64/op_rem_float.S @@ -1,3 +1,4 @@ +%def op_rem_float(): /* rem_float vAA, vBB, vCC */ movzbq 3(rPC), %rcx # ecx <- BB movzbq 2(rPC), %rax # eax <- CC diff --git a/runtime/interpreter/mterp/x86_64/op_rem_float_2addr.S b/runtime/interpreter/mterp/x86_64/op_rem_float_2addr.S index e9282a8de9..8cfdca080a 100644 --- a/runtime/interpreter/mterp/x86_64/op_rem_float_2addr.S +++ b/runtime/interpreter/mterp/x86_64/op_rem_float_2addr.S @@ -1,3 +1,4 @@ +%def op_rem_float_2addr(): /* rem_float/2addr vA, vB */ movzbq rINSTbl, %rcx # ecx <- A+ sarl $$4, rINST # rINST <- B diff --git a/runtime/interpreter/mterp/x86_64/op_rem_int.S b/runtime/interpreter/mterp/x86_64/op_rem_int.S index fd77d7cdfe..1530f5f944 100644 --- a/runtime/interpreter/mterp/x86_64/op_rem_int.S +++ b/runtime/interpreter/mterp/x86_64/op_rem_int.S @@ -1 +1,2 @@ -%include "x86_64/bindiv.S" {"result":"%edx","second":"%ecx","wide":"0","suffix":"l","rem":"1"} +%def op_rem_int(): +% bindiv(result="%edx", second="%ecx", wide="0", suffix="l", rem="1") diff --git a/runtime/interpreter/mterp/x86_64/op_rem_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_rem_int_2addr.S index 25ffbf713b..742213a468 100644 --- a/runtime/interpreter/mterp/x86_64/op_rem_int_2addr.S +++ b/runtime/interpreter/mterp/x86_64/op_rem_int_2addr.S @@ -1 +1,2 @@ -%include "x86_64/bindiv2addr.S" {"result":"%edx","second":"%ecx","wide":"0","suffix":"l","rem":"1"} +%def op_rem_int_2addr(): +% bindiv2addr(result="%edx", second="%ecx", wide="0", suffix="l", rem="1") diff --git a/runtime/interpreter/mterp/x86_64/op_rem_int_lit16.S b/runtime/interpreter/mterp/x86_64/op_rem_int_lit16.S index 21cc37087d..eaa44a4608 100644 --- a/runtime/interpreter/mterp/x86_64/op_rem_int_lit16.S +++ b/runtime/interpreter/mterp/x86_64/op_rem_int_lit16.S @@ -1 +1,2 @@ -%include "x86_64/bindivLit16.S" {"result":"%edx","rem":"1"} +%def op_rem_int_lit16(): +% bindivLit16(result="%edx", rem="1") diff --git a/runtime/interpreter/mterp/x86_64/op_rem_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_rem_int_lit8.S index 2eb0150f63..3fef144d1f 100644 --- a/runtime/interpreter/mterp/x86_64/op_rem_int_lit8.S +++ b/runtime/interpreter/mterp/x86_64/op_rem_int_lit8.S @@ -1 +1,2 @@ -%include "x86_64/bindivLit8.S" {"result":"%edx","rem":"1"} +%def op_rem_int_lit8(): +% bindivLit8(result="%edx", rem="1") diff --git a/runtime/interpreter/mterp/x86_64/op_rem_long.S b/runtime/interpreter/mterp/x86_64/op_rem_long.S index efa721520d..60bfd3d9df 100644 --- a/runtime/interpreter/mterp/x86_64/op_rem_long.S +++ b/runtime/interpreter/mterp/x86_64/op_rem_long.S @@ -1 +1,2 @@ -%include "x86_64/bindiv.S" {"result":"%rdx","second":"%rcx","wide":"1","suffix":"q","ext":"cqo","rem":"1"} +%def op_rem_long(): +% bindiv(result="%rdx", second="%rcx", wide="1", suffix="q", ext="cqo", rem="1") diff --git a/runtime/interpreter/mterp/x86_64/op_rem_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_rem_long_2addr.S index ce0dd86539..fc5a2d0cb9 100644 --- a/runtime/interpreter/mterp/x86_64/op_rem_long_2addr.S +++ b/runtime/interpreter/mterp/x86_64/op_rem_long_2addr.S @@ -1 +1,2 @@ -%include "x86_64/bindiv2addr.S" {"result":"%rdx","second":"%rcx","wide":"1","suffix":"q","rem":"1","ext":"cqo"} +%def op_rem_long_2addr(): +% bindiv2addr(result="%rdx", second="%rcx", wide="1", suffix="q", rem="1", ext="cqo") diff --git a/runtime/interpreter/mterp/x86_64/op_return.S b/runtime/interpreter/mterp/x86_64/op_return.S index 8cb6cbaee1..b838f18b7c 100644 --- a/runtime/interpreter/mterp/x86_64/op_return.S +++ b/runtime/interpreter/mterp/x86_64/op_return.S @@ -1,3 +1,4 @@ +%def op_return(): /* * Return a 32-bit value. * diff --git a/runtime/interpreter/mterp/x86_64/op_return_object.S b/runtime/interpreter/mterp/x86_64/op_return_object.S index 1ae69a501c..2eeec0b948 100644 --- a/runtime/interpreter/mterp/x86_64/op_return_object.S +++ b/runtime/interpreter/mterp/x86_64/op_return_object.S @@ -1 +1,2 @@ -%include "x86_64/op_return.S" +%def op_return_object(): +% op_return() diff --git a/runtime/interpreter/mterp/x86_64/op_return_void.S b/runtime/interpreter/mterp/x86_64/op_return_void.S index ba68e7e444..301dc92822 100644 --- a/runtime/interpreter/mterp/x86_64/op_return_void.S +++ b/runtime/interpreter/mterp/x86_64/op_return_void.S @@ -1,3 +1,4 @@ +%def op_return_void(): .extern MterpThreadFenceForConstructor call SYMBOL(MterpThreadFenceForConstructor) movq rSELF, OUT_ARG0 diff --git a/runtime/interpreter/mterp/x86_64/op_return_void_no_barrier.S b/runtime/interpreter/mterp/x86_64/op_return_void_no_barrier.S index 6799da1dbd..cec739c381 100644 --- a/runtime/interpreter/mterp/x86_64/op_return_void_no_barrier.S +++ b/runtime/interpreter/mterp/x86_64/op_return_void_no_barrier.S @@ -1,3 +1,4 @@ +%def op_return_void_no_barrier(): movq rSELF, OUT_ARG0 testl $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(OUT_ARG0) jz 1f diff --git a/runtime/interpreter/mterp/x86_64/op_return_wide.S b/runtime/interpreter/mterp/x86_64/op_return_wide.S index d6d6d1bf5e..90e0a42d62 100644 --- a/runtime/interpreter/mterp/x86_64/op_return_wide.S +++ b/runtime/interpreter/mterp/x86_64/op_return_wide.S @@ -1,3 +1,4 @@ +%def op_return_wide(): /* * Return a 64-bit value. */ diff --git a/runtime/interpreter/mterp/x86_64/op_rsub_int.S b/runtime/interpreter/mterp/x86_64/op_rsub_int.S index 2dd20026df..05ba130f2f 100644 --- a/runtime/interpreter/mterp/x86_64/op_rsub_int.S +++ b/runtime/interpreter/mterp/x86_64/op_rsub_int.S @@ -1,2 +1,3 @@ +%def op_rsub_int(): /* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ -%include "x86_64/binopLit16.S" {"instr":"subl %eax, %ecx","result":"%ecx"} +% binopLit16(instr="subl %eax, %ecx", result="%ecx") diff --git a/runtime/interpreter/mterp/x86_64/op_rsub_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_rsub_int_lit8.S index 64d0d8a704..d0230476d7 100644 --- a/runtime/interpreter/mterp/x86_64/op_rsub_int_lit8.S +++ b/runtime/interpreter/mterp/x86_64/op_rsub_int_lit8.S @@ -1 +1,2 @@ -%include "x86_64/binopLit8.S" {"instr":"subl %eax, %ecx" , "result":"%ecx"} +%def op_rsub_int_lit8(): +% binopLit8(instr="subl %eax, %ecx", result="%ecx") diff --git a/runtime/interpreter/mterp/x86_64/op_sget.S b/runtime/interpreter/mterp/x86_64/op_sget.S index 21e8e64b8b..8a6a66ab60 100644 --- a/runtime/interpreter/mterp/x86_64/op_sget.S +++ b/runtime/interpreter/mterp/x86_64/op_sget.S @@ -1,2 +1,2 @@ -%default { "is_object":"0", "helper":"MterpSGetU32" } -%include "x86_64/field.S" { } +%def op_sget(is_object="0", helper="MterpSGetU32"): +% field(helper=helper) diff --git a/runtime/interpreter/mterp/x86_64/op_sget_boolean.S b/runtime/interpreter/mterp/x86_64/op_sget_boolean.S index e5a4e41995..d9c12c9b28 100644 --- a/runtime/interpreter/mterp/x86_64/op_sget_boolean.S +++ b/runtime/interpreter/mterp/x86_64/op_sget_boolean.S @@ -1 +1,2 @@ -%include "x86_64/op_sget.S" {"helper":"MterpSGetU8"} +%def op_sget_boolean(): +% op_sget(helper="MterpSGetU8") diff --git a/runtime/interpreter/mterp/x86_64/op_sget_byte.S b/runtime/interpreter/mterp/x86_64/op_sget_byte.S index 4602f7da53..37c6879cd4 100644 --- a/runtime/interpreter/mterp/x86_64/op_sget_byte.S +++ b/runtime/interpreter/mterp/x86_64/op_sget_byte.S @@ -1 +1,2 @@ -%include "x86_64/op_sget.S" {"helper":"MterpSGetI8"} +%def op_sget_byte(): +% op_sget(helper="MterpSGetI8") diff --git a/runtime/interpreter/mterp/x86_64/op_sget_char.S b/runtime/interpreter/mterp/x86_64/op_sget_char.S index a094a542de..003bcd1683 100644 --- a/runtime/interpreter/mterp/x86_64/op_sget_char.S +++ b/runtime/interpreter/mterp/x86_64/op_sget_char.S @@ -1 +1,2 @@ -%include "x86_64/op_sget.S" {"helper":"MterpSGetU16"} +%def op_sget_char(): +% op_sget(helper="MterpSGetU16") diff --git a/runtime/interpreter/mterp/x86_64/op_sget_object.S b/runtime/interpreter/mterp/x86_64/op_sget_object.S index 94597b187c..7cf3597f44 100644 --- a/runtime/interpreter/mterp/x86_64/op_sget_object.S +++ b/runtime/interpreter/mterp/x86_64/op_sget_object.S @@ -1 +1,2 @@ -%include "x86_64/op_sget.S" {"is_object":"1", "helper":"MterpSGetObj"} +%def op_sget_object(): +% op_sget(is_object="1", helper="MterpSGetObj") diff --git a/runtime/interpreter/mterp/x86_64/op_sget_short.S b/runtime/interpreter/mterp/x86_64/op_sget_short.S index dee5c247b9..afacb578d9 100644 --- a/runtime/interpreter/mterp/x86_64/op_sget_short.S +++ b/runtime/interpreter/mterp/x86_64/op_sget_short.S @@ -1 +1,2 @@ -%include "x86_64/op_sget.S" {"helper":"MterpSGetI16"} +%def op_sget_short(): +% op_sget(helper="MterpSGetI16") diff --git a/runtime/interpreter/mterp/x86_64/op_sget_wide.S b/runtime/interpreter/mterp/x86_64/op_sget_wide.S index c53c0773a5..fff2be6945 100644 --- a/runtime/interpreter/mterp/x86_64/op_sget_wide.S +++ b/runtime/interpreter/mterp/x86_64/op_sget_wide.S @@ -1 +1,2 @@ -%include "x86_64/op_sget.S" {"helper":"MterpSGetU64"} +%def op_sget_wide(): +% op_sget(helper="MterpSGetU64") diff --git a/runtime/interpreter/mterp/x86_64/op_shl_int.S b/runtime/interpreter/mterp/x86_64/op_shl_int.S index fa1edb7555..a98b256120 100644 --- a/runtime/interpreter/mterp/x86_64/op_shl_int.S +++ b/runtime/interpreter/mterp/x86_64/op_shl_int.S @@ -1 +1,2 @@ -%include "x86_64/binop1.S" {"instr":"sall %cl, %eax"} +%def op_shl_int(): +% binop1(instr="sall %cl, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_shl_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_shl_int_2addr.S index dd962792c9..987c7d1e28 100644 --- a/runtime/interpreter/mterp/x86_64/op_shl_int_2addr.S +++ b/runtime/interpreter/mterp/x86_64/op_shl_int_2addr.S @@ -1 +1,2 @@ -%include "x86_64/shop2addr.S" {"instr":"sall %cl, %eax"} +%def op_shl_int_2addr(): +% shop2addr(instr="sall %cl, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_shl_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_shl_int_lit8.S index 39b23ae1fb..ee1a15e696 100644 --- a/runtime/interpreter/mterp/x86_64/op_shl_int_lit8.S +++ b/runtime/interpreter/mterp/x86_64/op_shl_int_lit8.S @@ -1 +1,2 @@ -%include "x86_64/binopLit8.S" {"instr":"sall %cl, %eax"} +%def op_shl_int_lit8(): +% binopLit8(instr="sall %cl, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_shl_long.S b/runtime/interpreter/mterp/x86_64/op_shl_long.S index fdc7cb64de..c288b36352 100644 --- a/runtime/interpreter/mterp/x86_64/op_shl_long.S +++ b/runtime/interpreter/mterp/x86_64/op_shl_long.S @@ -1 +1,2 @@ -%include "x86_64/binop1.S" {"instr":"salq %cl, %rax","wide":"1"} +%def op_shl_long(): +% binop1(instr="salq %cl, %rax", wide="1") diff --git a/runtime/interpreter/mterp/x86_64/op_shl_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_shl_long_2addr.S index 546633f7d5..820e703975 100644 --- a/runtime/interpreter/mterp/x86_64/op_shl_long_2addr.S +++ b/runtime/interpreter/mterp/x86_64/op_shl_long_2addr.S @@ -1 +1,2 @@ -%include "x86_64/shop2addr.S" {"instr":"salq %cl, %rax","wide":"1"} +%def op_shl_long_2addr(): +% shop2addr(instr="salq %cl, %rax", wide="1") diff --git a/runtime/interpreter/mterp/x86_64/op_shr_int.S b/runtime/interpreter/mterp/x86_64/op_shr_int.S index fc289f4638..4d4d79cc09 100644 --- a/runtime/interpreter/mterp/x86_64/op_shr_int.S +++ b/runtime/interpreter/mterp/x86_64/op_shr_int.S @@ -1 +1,2 @@ -%include "x86_64/binop1.S" {"instr":"sarl %cl, %eax"} +%def op_shr_int(): +% binop1(instr="sarl %cl, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_shr_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_shr_int_2addr.S index 0e5bca7057..8e4b055e15 100644 --- a/runtime/interpreter/mterp/x86_64/op_shr_int_2addr.S +++ b/runtime/interpreter/mterp/x86_64/op_shr_int_2addr.S @@ -1 +1,2 @@ -%include "x86_64/shop2addr.S" {"instr":"sarl %cl, %eax"} +%def op_shr_int_2addr(): +% shop2addr(instr="sarl %cl, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_shr_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_shr_int_lit8.S index 3cc9307569..a7acf5f384 100644 --- a/runtime/interpreter/mterp/x86_64/op_shr_int_lit8.S +++ b/runtime/interpreter/mterp/x86_64/op_shr_int_lit8.S @@ -1 +1,2 @@ -%include "x86_64/binopLit8.S" {"instr":"sarl %cl, %eax"} +%def op_shr_int_lit8(): +% binopLit8(instr="sarl %cl, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_shr_long.S b/runtime/interpreter/mterp/x86_64/op_shr_long.S index 25028d3560..ed3e504a55 100644 --- a/runtime/interpreter/mterp/x86_64/op_shr_long.S +++ b/runtime/interpreter/mterp/x86_64/op_shr_long.S @@ -1 +1,2 @@ -%include "x86_64/binop1.S" {"instr":"sarq %cl, %rax","wide":"1"} +%def op_shr_long(): +% binop1(instr="sarq %cl, %rax", wide="1") diff --git a/runtime/interpreter/mterp/x86_64/op_shr_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_shr_long_2addr.S index 373841322d..be6898d5a6 100644 --- a/runtime/interpreter/mterp/x86_64/op_shr_long_2addr.S +++ b/runtime/interpreter/mterp/x86_64/op_shr_long_2addr.S @@ -1 +1,2 @@ -%include "x86_64/shop2addr.S" {"instr":"sarq %cl, %rax","wide":"1"} +%def op_shr_long_2addr(): +% shop2addr(instr="sarq %cl, %rax", wide="1") diff --git a/runtime/interpreter/mterp/x86_64/op_sparse_switch.S b/runtime/interpreter/mterp/x86_64/op_sparse_switch.S index 0eaa514813..b74d7da816 100644 --- a/runtime/interpreter/mterp/x86_64/op_sparse_switch.S +++ b/runtime/interpreter/mterp/x86_64/op_sparse_switch.S @@ -1 +1,2 @@ -%include "x86_64/op_packed_switch.S" { "func":"MterpDoSparseSwitch" } +%def op_sparse_switch(): +% op_packed_switch(func="MterpDoSparseSwitch") diff --git a/runtime/interpreter/mterp/x86_64/op_sput.S b/runtime/interpreter/mterp/x86_64/op_sput.S index 7dd24985ff..cbd6ee96d3 100644 --- a/runtime/interpreter/mterp/x86_64/op_sput.S +++ b/runtime/interpreter/mterp/x86_64/op_sput.S @@ -1,2 +1,2 @@ -%default { "is_object":"0", "helper":"MterpSPutU32"} -%include "x86_64/field.S" { } +%def op_sput(is_object="0", helper="MterpSPutU32"): +% field(helper=helper) diff --git a/runtime/interpreter/mterp/x86_64/op_sput_boolean.S b/runtime/interpreter/mterp/x86_64/op_sput_boolean.S index ea9acbfdc7..36fba8448b 100644 --- a/runtime/interpreter/mterp/x86_64/op_sput_boolean.S +++ b/runtime/interpreter/mterp/x86_64/op_sput_boolean.S @@ -1 +1,2 @@ -%include "x86_64/op_sput.S" {"helper":"MterpSPutU8"} +%def op_sput_boolean(): +% op_sput(helper="MterpSPutU8") diff --git a/runtime/interpreter/mterp/x86_64/op_sput_byte.S b/runtime/interpreter/mterp/x86_64/op_sput_byte.S index 62c9e205a1..84ad4a0ff8 100644 --- a/runtime/interpreter/mterp/x86_64/op_sput_byte.S +++ b/runtime/interpreter/mterp/x86_64/op_sput_byte.S @@ -1 +1,2 @@ -%include "x86_64/op_sput.S" {"helper":"MterpSPutI8"} +%def op_sput_byte(): +% op_sput(helper="MterpSPutI8") diff --git a/runtime/interpreter/mterp/x86_64/op_sput_char.S b/runtime/interpreter/mterp/x86_64/op_sput_char.S index ab0196e027..9b8eeba578 100644 --- a/runtime/interpreter/mterp/x86_64/op_sput_char.S +++ b/runtime/interpreter/mterp/x86_64/op_sput_char.S @@ -1 +1,2 @@ -%include "x86_64/op_sput.S" {"helper":"MterpSPutU16"} +%def op_sput_char(): +% op_sput(helper="MterpSPutU16") diff --git a/runtime/interpreter/mterp/x86_64/op_sput_object.S b/runtime/interpreter/mterp/x86_64/op_sput_object.S index c2bd07bcc8..081360c40f 100644 --- a/runtime/interpreter/mterp/x86_64/op_sput_object.S +++ b/runtime/interpreter/mterp/x86_64/op_sput_object.S @@ -1 +1,2 @@ -%include "x86_64/op_sput.S" {"is_object":"1", "helper":"MterpSPutObj"} +%def op_sput_object(): +% op_sput(is_object="1", helper="MterpSPutObj") diff --git a/runtime/interpreter/mterp/x86_64/op_sput_short.S b/runtime/interpreter/mterp/x86_64/op_sput_short.S index f73a3fc69e..ee16513486 100644 --- a/runtime/interpreter/mterp/x86_64/op_sput_short.S +++ b/runtime/interpreter/mterp/x86_64/op_sput_short.S @@ -1 +1,2 @@ -%include "x86_64/op_sput.S" {"helper":"MterpSPutI16"} +%def op_sput_short(): +% op_sput(helper="MterpSPutI16") diff --git a/runtime/interpreter/mterp/x86_64/op_sput_wide.S b/runtime/interpreter/mterp/x86_64/op_sput_wide.S index 7e77072dce..44c1a188ed 100644 --- a/runtime/interpreter/mterp/x86_64/op_sput_wide.S +++ b/runtime/interpreter/mterp/x86_64/op_sput_wide.S @@ -1 +1,2 @@ -%include "x86_64/op_sput.S" {"helper":"MterpSPutU64"} +%def op_sput_wide(): +% op_sput(helper="MterpSPutU64") diff --git a/runtime/interpreter/mterp/x86_64/op_sub_double.S b/runtime/interpreter/mterp/x86_64/op_sub_double.S index 952667e831..64a28c376b 100644 --- a/runtime/interpreter/mterp/x86_64/op_sub_double.S +++ b/runtime/interpreter/mterp/x86_64/op_sub_double.S @@ -1 +1,2 @@ -%include "x86_64/sseBinop.S" {"instr":"subs","suff":"d"} +%def op_sub_double(): +% sseBinop(instr="subs", suff="d") diff --git a/runtime/interpreter/mterp/x86_64/op_sub_double_2addr.S b/runtime/interpreter/mterp/x86_64/op_sub_double_2addr.S index 0bd5dbb8ff..753074bd37 100644 --- a/runtime/interpreter/mterp/x86_64/op_sub_double_2addr.S +++ b/runtime/interpreter/mterp/x86_64/op_sub_double_2addr.S @@ -1 +1,2 @@ -%include "x86_64/sseBinop2Addr.S" {"instr":"subs","suff":"d"} +%def op_sub_double_2addr(): +% sseBinop2Addr(instr="subs", suff="d") diff --git a/runtime/interpreter/mterp/x86_64/op_sub_float.S b/runtime/interpreter/mterp/x86_64/op_sub_float.S index ea0ae14f5b..1a1966dba2 100644 --- a/runtime/interpreter/mterp/x86_64/op_sub_float.S +++ b/runtime/interpreter/mterp/x86_64/op_sub_float.S @@ -1 +1,2 @@ -%include "x86_64/sseBinop.S" {"instr":"subs","suff":"s"} +%def op_sub_float(): +% sseBinop(instr="subs", suff="s") diff --git a/runtime/interpreter/mterp/x86_64/op_sub_float_2addr.S b/runtime/interpreter/mterp/x86_64/op_sub_float_2addr.S index 9dd17805c8..9557907bd2 100644 --- a/runtime/interpreter/mterp/x86_64/op_sub_float_2addr.S +++ b/runtime/interpreter/mterp/x86_64/op_sub_float_2addr.S @@ -1 +1,2 @@ -%include "x86_64/sseBinop2Addr.S" {"instr":"subs","suff":"s"} +%def op_sub_float_2addr(): +% sseBinop2Addr(instr="subs", suff="s") diff --git a/runtime/interpreter/mterp/x86_64/op_sub_int.S b/runtime/interpreter/mterp/x86_64/op_sub_int.S index 560394f43f..ecab19d72b 100644 --- a/runtime/interpreter/mterp/x86_64/op_sub_int.S +++ b/runtime/interpreter/mterp/x86_64/op_sub_int.S @@ -1 +1,2 @@ -%include "x86_64/binop.S" {"instr":"subl (rFP,%rcx,4), %eax"} +%def op_sub_int(): +% binop(instr="subl (rFP,%rcx,4), %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_sub_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_sub_int_2addr.S index 6f50f78f41..61fc7a7b15 100644 --- a/runtime/interpreter/mterp/x86_64/op_sub_int_2addr.S +++ b/runtime/interpreter/mterp/x86_64/op_sub_int_2addr.S @@ -1 +1,2 @@ -%include "x86_64/binop2addr.S" {"instr":"subl %eax, (rFP,%rcx,4)"} +%def op_sub_int_2addr(): +% binop2addr(instr="subl %eax, (rFP,%rcx,4)") diff --git a/runtime/interpreter/mterp/x86_64/op_sub_long.S b/runtime/interpreter/mterp/x86_64/op_sub_long.S index 7fa54e7a11..9c38f88951 100644 --- a/runtime/interpreter/mterp/x86_64/op_sub_long.S +++ b/runtime/interpreter/mterp/x86_64/op_sub_long.S @@ -1 +1,2 @@ -%include "x86_64/binopWide.S" {"instr":"subq (rFP,%rcx,4), %rax"} +%def op_sub_long(): +% binopWide(instr="subq (rFP,%rcx,4), %rax") diff --git a/runtime/interpreter/mterp/x86_64/op_sub_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_sub_long_2addr.S index c18be10919..ab31aaff8f 100644 --- a/runtime/interpreter/mterp/x86_64/op_sub_long_2addr.S +++ b/runtime/interpreter/mterp/x86_64/op_sub_long_2addr.S @@ -1 +1,2 @@ -%include "x86_64/binopWide2addr.S" {"instr":"subq %rax, (rFP,%rcx,4)"} +%def op_sub_long_2addr(): +% binopWide2addr(instr="subq %rax, (rFP,%rcx,4)") diff --git a/runtime/interpreter/mterp/x86_64/op_throw.S b/runtime/interpreter/mterp/x86_64/op_throw.S index 8095c25b08..09fc1ec6b8 100644 --- a/runtime/interpreter/mterp/x86_64/op_throw.S +++ b/runtime/interpreter/mterp/x86_64/op_throw.S @@ -1,3 +1,4 @@ +%def op_throw(): /* * Throw an exception object in the current thread. */ diff --git a/runtime/interpreter/mterp/x86_64/op_unused_3e.S b/runtime/interpreter/mterp/x86_64/op_unused_3e.S index 280615f08b..d889f1a5fb 100644 --- a/runtime/interpreter/mterp/x86_64/op_unused_3e.S +++ b/runtime/interpreter/mterp/x86_64/op_unused_3e.S @@ -1 +1,2 @@ -%include "x86_64/unused.S" +%def op_unused_3e(): +% unused() diff --git a/runtime/interpreter/mterp/x86_64/op_unused_3f.S b/runtime/interpreter/mterp/x86_64/op_unused_3f.S index 280615f08b..b3ebcfaeaa 100644 --- a/runtime/interpreter/mterp/x86_64/op_unused_3f.S +++ b/runtime/interpreter/mterp/x86_64/op_unused_3f.S @@ -1 +1,2 @@ -%include "x86_64/unused.S" +%def op_unused_3f(): +% unused() diff --git a/runtime/interpreter/mterp/x86_64/op_unused_40.S b/runtime/interpreter/mterp/x86_64/op_unused_40.S index 280615f08b..7920fb350f 100644 --- a/runtime/interpreter/mterp/x86_64/op_unused_40.S +++ b/runtime/interpreter/mterp/x86_64/op_unused_40.S @@ -1 +1,2 @@ -%include "x86_64/unused.S" +%def op_unused_40(): +% unused() diff --git a/runtime/interpreter/mterp/x86_64/op_unused_41.S b/runtime/interpreter/mterp/x86_64/op_unused_41.S index 280615f08b..5ed03b8506 100644 --- a/runtime/interpreter/mterp/x86_64/op_unused_41.S +++ b/runtime/interpreter/mterp/x86_64/op_unused_41.S @@ -1 +1,2 @@ -%include "x86_64/unused.S" +%def op_unused_41(): +% unused() diff --git a/runtime/interpreter/mterp/x86_64/op_unused_42.S b/runtime/interpreter/mterp/x86_64/op_unused_42.S index 280615f08b..ac32521add 100644 --- a/runtime/interpreter/mterp/x86_64/op_unused_42.S +++ b/runtime/interpreter/mterp/x86_64/op_unused_42.S @@ -1 +1,2 @@ -%include "x86_64/unused.S" +%def op_unused_42(): +% unused() diff --git a/runtime/interpreter/mterp/x86_64/op_unused_43.S b/runtime/interpreter/mterp/x86_64/op_unused_43.S index 280615f08b..33e2aa10f8 100644 --- a/runtime/interpreter/mterp/x86_64/op_unused_43.S +++ b/runtime/interpreter/mterp/x86_64/op_unused_43.S @@ -1 +1,2 @@ -%include "x86_64/unused.S" +%def op_unused_43(): +% unused() diff --git a/runtime/interpreter/mterp/x86_64/op_unused_79.S b/runtime/interpreter/mterp/x86_64/op_unused_79.S index 280615f08b..3c6dafc789 100644 --- a/runtime/interpreter/mterp/x86_64/op_unused_79.S +++ b/runtime/interpreter/mterp/x86_64/op_unused_79.S @@ -1 +1,2 @@ -%include "x86_64/unused.S" +%def op_unused_79(): +% unused() diff --git a/runtime/interpreter/mterp/x86_64/op_unused_7a.S b/runtime/interpreter/mterp/x86_64/op_unused_7a.S index 280615f08b..9c03cd5535 100644 --- a/runtime/interpreter/mterp/x86_64/op_unused_7a.S +++ b/runtime/interpreter/mterp/x86_64/op_unused_7a.S @@ -1 +1,2 @@ -%include "x86_64/unused.S" +%def op_unused_7a(): +% unused() diff --git a/runtime/interpreter/mterp/x86_64/op_unused_f3.S b/runtime/interpreter/mterp/x86_64/op_unused_f3.S index 280615f08b..ab10b78be2 100644 --- a/runtime/interpreter/mterp/x86_64/op_unused_f3.S +++ b/runtime/interpreter/mterp/x86_64/op_unused_f3.S @@ -1 +1,2 @@ -%include "x86_64/unused.S" +%def op_unused_f3(): +% unused() diff --git a/runtime/interpreter/mterp/x86_64/op_unused_f4.S b/runtime/interpreter/mterp/x86_64/op_unused_f4.S index 280615f08b..09229d6d99 100644 --- a/runtime/interpreter/mterp/x86_64/op_unused_f4.S +++ b/runtime/interpreter/mterp/x86_64/op_unused_f4.S @@ -1 +1,2 @@ -%include "x86_64/unused.S" +%def op_unused_f4(): +% unused() diff --git a/runtime/interpreter/mterp/x86_64/op_unused_f5.S b/runtime/interpreter/mterp/x86_64/op_unused_f5.S index 280615f08b..0d6149b5fd 100644 --- a/runtime/interpreter/mterp/x86_64/op_unused_f5.S +++ b/runtime/interpreter/mterp/x86_64/op_unused_f5.S @@ -1 +1,2 @@ -%include "x86_64/unused.S" +%def op_unused_f5(): +% unused() diff --git a/runtime/interpreter/mterp/x86_64/op_unused_f6.S b/runtime/interpreter/mterp/x86_64/op_unused_f6.S index 280615f08b..117b03de6d 100644 --- a/runtime/interpreter/mterp/x86_64/op_unused_f6.S +++ b/runtime/interpreter/mterp/x86_64/op_unused_f6.S @@ -1 +1,2 @@ -%include "x86_64/unused.S" +%def op_unused_f6(): +% unused() diff --git a/runtime/interpreter/mterp/x86_64/op_unused_f7.S b/runtime/interpreter/mterp/x86_64/op_unused_f7.S index 280615f08b..4e3a0f3c9a 100644 --- a/runtime/interpreter/mterp/x86_64/op_unused_f7.S +++ b/runtime/interpreter/mterp/x86_64/op_unused_f7.S @@ -1 +1,2 @@ -%include "x86_64/unused.S" +%def op_unused_f7(): +% unused() diff --git a/runtime/interpreter/mterp/x86_64/op_unused_f8.S b/runtime/interpreter/mterp/x86_64/op_unused_f8.S index 280615f08b..d1220752d7 100644 --- a/runtime/interpreter/mterp/x86_64/op_unused_f8.S +++ b/runtime/interpreter/mterp/x86_64/op_unused_f8.S @@ -1 +1,2 @@ -%include "x86_64/unused.S" +%def op_unused_f8(): +% unused() diff --git a/runtime/interpreter/mterp/x86_64/op_unused_f9.S b/runtime/interpreter/mterp/x86_64/op_unused_f9.S index 280615f08b..7d09a0ebcf 100644 --- a/runtime/interpreter/mterp/x86_64/op_unused_f9.S +++ b/runtime/interpreter/mterp/x86_64/op_unused_f9.S @@ -1 +1,2 @@ -%include "x86_64/unused.S" +%def op_unused_f9(): +% unused() diff --git a/runtime/interpreter/mterp/x86_64/op_unused_fc.S b/runtime/interpreter/mterp/x86_64/op_unused_fc.S index 280615f08b..06978191eb 100644 --- a/runtime/interpreter/mterp/x86_64/op_unused_fc.S +++ b/runtime/interpreter/mterp/x86_64/op_unused_fc.S @@ -1 +1,2 @@ -%include "x86_64/unused.S" +%def op_unused_fc(): +% unused() diff --git a/runtime/interpreter/mterp/x86_64/op_unused_fd.S b/runtime/interpreter/mterp/x86_64/op_unused_fd.S index 280615f08b..4bc2b4bdb6 100644 --- a/runtime/interpreter/mterp/x86_64/op_unused_fd.S +++ b/runtime/interpreter/mterp/x86_64/op_unused_fd.S @@ -1 +1,2 @@ -%include "x86_64/unused.S" +%def op_unused_fd(): +% unused() diff --git a/runtime/interpreter/mterp/x86_64/op_ushr_int.S b/runtime/interpreter/mterp/x86_64/op_ushr_int.S index dd91086371..38c8782ca9 100644 --- a/runtime/interpreter/mterp/x86_64/op_ushr_int.S +++ b/runtime/interpreter/mterp/x86_64/op_ushr_int.S @@ -1 +1,2 @@ -%include "x86_64/binop1.S" {"instr":"shrl %cl, %eax"} +%def op_ushr_int(): +% binop1(instr="shrl %cl, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_ushr_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_ushr_int_2addr.S index d38aedd234..f1da71a47a 100644 --- a/runtime/interpreter/mterp/x86_64/op_ushr_int_2addr.S +++ b/runtime/interpreter/mterp/x86_64/op_ushr_int_2addr.S @@ -1 +1,2 @@ -%include "x86_64/shop2addr.S" {"instr":"shrl %cl, %eax"} +%def op_ushr_int_2addr(): +% shop2addr(instr="shrl %cl, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_ushr_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_ushr_int_lit8.S index f7ff8abc86..4298d36c3d 100644 --- a/runtime/interpreter/mterp/x86_64/op_ushr_int_lit8.S +++ b/runtime/interpreter/mterp/x86_64/op_ushr_int_lit8.S @@ -1 +1,2 @@ -%include "x86_64/binopLit8.S" {"instr":"shrl %cl, %eax"} +%def op_ushr_int_lit8(): +% binopLit8(instr="shrl %cl, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_ushr_long.S b/runtime/interpreter/mterp/x86_64/op_ushr_long.S index 7c6daca05d..a0b4daf14d 100644 --- a/runtime/interpreter/mterp/x86_64/op_ushr_long.S +++ b/runtime/interpreter/mterp/x86_64/op_ushr_long.S @@ -1 +1,2 @@ -%include "x86_64/binop1.S" {"instr":"shrq %cl, %rax","wide":"1"} +%def op_ushr_long(): +% binop1(instr="shrq %cl, %rax", wide="1") diff --git a/runtime/interpreter/mterp/x86_64/op_ushr_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_ushr_long_2addr.S index cd6a22c6fa..2213cf3865 100644 --- a/runtime/interpreter/mterp/x86_64/op_ushr_long_2addr.S +++ b/runtime/interpreter/mterp/x86_64/op_ushr_long_2addr.S @@ -1 +1,2 @@ -%include "x86_64/shop2addr.S" {"instr":"shrq %cl, %rax","wide":"1"} +%def op_ushr_long_2addr(): +% shop2addr(instr="shrq %cl, %rax", wide="1") diff --git a/runtime/interpreter/mterp/x86_64/op_xor_int.S b/runtime/interpreter/mterp/x86_64/op_xor_int.S index b295d74de0..5dc2603735 100644 --- a/runtime/interpreter/mterp/x86_64/op_xor_int.S +++ b/runtime/interpreter/mterp/x86_64/op_xor_int.S @@ -1 +1,2 @@ -%include "x86_64/binop.S" {"instr":"xorl (rFP,%rcx,4), %eax"} +%def op_xor_int(): +% binop(instr="xorl (rFP,%rcx,4), %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_xor_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_xor_int_2addr.S index 879bfc05dc..2c847028c5 100644 --- a/runtime/interpreter/mterp/x86_64/op_xor_int_2addr.S +++ b/runtime/interpreter/mterp/x86_64/op_xor_int_2addr.S @@ -1 +1,2 @@ -%include "x86_64/binop2addr.S" {"instr":"xorl %eax, (rFP,%rcx,4)"} +%def op_xor_int_2addr(): +% binop2addr(instr="xorl %eax, (rFP,%rcx,4)") diff --git a/runtime/interpreter/mterp/x86_64/op_xor_int_lit16.S b/runtime/interpreter/mterp/x86_64/op_xor_int_lit16.S index 5d375a1cf6..f5dc00e074 100644 --- a/runtime/interpreter/mterp/x86_64/op_xor_int_lit16.S +++ b/runtime/interpreter/mterp/x86_64/op_xor_int_lit16.S @@ -1 +1,2 @@ -%include "x86_64/binopLit16.S" {"instr":"xorl %ecx, %eax"} +%def op_xor_int_lit16(): +% binopLit16(instr="xorl %ecx, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_xor_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_xor_int_lit8.S index 54cce9c18e..98a1a432dd 100644 --- a/runtime/interpreter/mterp/x86_64/op_xor_int_lit8.S +++ b/runtime/interpreter/mterp/x86_64/op_xor_int_lit8.S @@ -1 +1,2 @@ -%include "x86_64/binopLit8.S" {"instr":"xorl %ecx, %eax"} +%def op_xor_int_lit8(): +% binopLit8(instr="xorl %ecx, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_xor_long.S b/runtime/interpreter/mterp/x86_64/op_xor_long.S index 52b44e29c1..1c267930d4 100644 --- a/runtime/interpreter/mterp/x86_64/op_xor_long.S +++ b/runtime/interpreter/mterp/x86_64/op_xor_long.S @@ -1 +1,2 @@ -%include "x86_64/binopWide.S" {"instr":"xorq (rFP,%rcx,4), %rax"} +%def op_xor_long(): +% binopWide(instr="xorq (rFP,%rcx,4), %rax") diff --git a/runtime/interpreter/mterp/x86_64/op_xor_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_xor_long_2addr.S index d75c4ba6ce..c6496517f7 100644 --- a/runtime/interpreter/mterp/x86_64/op_xor_long_2addr.S +++ b/runtime/interpreter/mterp/x86_64/op_xor_long_2addr.S @@ -1 +1,2 @@ -%include "x86_64/binopWide2addr.S" {"instr":"xorq %rax, (rFP,%rcx,4)"} +%def op_xor_long_2addr(): +% binopWide2addr(instr="xorq %rax, (rFP,%rcx,4)") diff --git a/runtime/interpreter/mterp/x86_64/shop2addr.S b/runtime/interpreter/mterp/x86_64/shop2addr.S index 6b06d002fc..d0d838b880 100644 --- a/runtime/interpreter/mterp/x86_64/shop2addr.S +++ b/runtime/interpreter/mterp/x86_64/shop2addr.S @@ -1,4 +1,4 @@ -%default {"wide":"0"} +%def shop2addr(wide="0", instr=""): /* * Generic 32-bit "shift/2addr" operation. */ diff --git a/runtime/interpreter/mterp/x86_64/sseBinop.S b/runtime/interpreter/mterp/x86_64/sseBinop.S index 09d3364de7..638ea8ef56 100644 --- a/runtime/interpreter/mterp/x86_64/sseBinop.S +++ b/runtime/interpreter/mterp/x86_64/sseBinop.S @@ -1,4 +1,4 @@ -%default {"instr":"","suff":""} +%def sseBinop(instr="", suff=""): movzbq 2(rPC), %rcx # ecx <- BB movzbq 3(rPC), %rax # eax <- CC movs${suff} VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src diff --git a/runtime/interpreter/mterp/x86_64/sseBinop2Addr.S b/runtime/interpreter/mterp/x86_64/sseBinop2Addr.S index 084166b95d..1292a36de3 100644 --- a/runtime/interpreter/mterp/x86_64/sseBinop2Addr.S +++ b/runtime/interpreter/mterp/x86_64/sseBinop2Addr.S @@ -1,4 +1,4 @@ -%default {"instr":"","suff":""} +%def sseBinop2Addr(instr="", suff=""): movl rINST, %ecx # ecx <- A+ andl $$0xf, %ecx # ecx <- A movs${suff} VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src diff --git a/runtime/interpreter/mterp/x86_64/unop.S b/runtime/interpreter/mterp/x86_64/unop.S index 1777123f36..1dd12a31a1 100644 --- a/runtime/interpreter/mterp/x86_64/unop.S +++ b/runtime/interpreter/mterp/x86_64/unop.S @@ -1,4 +1,4 @@ -%default {"preinstr":"", "instr":"", "wide":"0"} +%def unop(preinstr="", instr="", wide="0"): /* * Generic 32/64-bit unary operation. Provide an "instr" line that * specifies an instruction that performs "result = op eax". diff --git a/runtime/interpreter/mterp/x86_64/unused.S b/runtime/interpreter/mterp/x86_64/unused.S index c95ef947d3..ef35b6e73f 100644 --- a/runtime/interpreter/mterp/x86_64/unused.S +++ b/runtime/interpreter/mterp/x86_64/unused.S @@ -1,3 +1,4 @@ +%def unused(): /* * Bail to reference interpreter to throw. */ diff --git a/runtime/interpreter/mterp/x86_64/zcmp.S b/runtime/interpreter/mterp/x86_64/zcmp.S index fb8ae6af6e..e794fb0e5b 100644 --- a/runtime/interpreter/mterp/x86_64/zcmp.S +++ b/runtime/interpreter/mterp/x86_64/zcmp.S @@ -1,3 +1,4 @@ +%def zcmp(revcmp=""): /* * Generic one-operand compare-and-branch operation. Provide a "revcmp" * fragment that specifies the *reverse* comparison to perform, e.g. -- GitLab From b2b52a55c3ff44e6b20dc76c48e2dcf58bc34468 Mon Sep 17 00:00:00 2001 From: David Srbecky Date: Thu, 6 Sep 2018 16:41:23 +0100 Subject: [PATCH 2/4] Group mterp files Group hundreds of tiny files into larger files (but still less than 1000 lines of code each). This should make editing and reviews simpler. This CL is just simple file concatenation. The filenames don't have any meaning any more. The generated assembly output is still the same. Test: test-art-host-gtest Change-Id: Iee493f334999c2e06a72e19d3c065d19c67323f1 --- runtime/interpreter/mterp/arm/alt_stub.S | 14 - runtime/interpreter/mterp/arm/arithmetic.S | 975 ++++++++++++++++++ runtime/interpreter/mterp/arm/array.S | 250 +++++ runtime/interpreter/mterp/arm/bincmp.S | 20 - runtime/interpreter/mterp/arm/binop.S | 35 - runtime/interpreter/mterp/arm/binop2addr.S | 32 - runtime/interpreter/mterp/arm/binopLit16.S | 29 - runtime/interpreter/mterp/arm/binopLit8.S | 35 - runtime/interpreter/mterp/arm/binopWide.S | 38 - .../interpreter/mterp/arm/binopWide2addr.S | 34 - runtime/interpreter/mterp/arm/const.S | 18 - runtime/interpreter/mterp/arm/control_flow.S | 209 ++++ runtime/interpreter/mterp/arm/entry.S | 77 -- runtime/interpreter/mterp/arm/fallback.S | 4 - runtime/interpreter/mterp/arm/fbinop.S | 24 - runtime/interpreter/mterp/arm/fbinop2addr.S | 20 - runtime/interpreter/mterp/arm/fbinopWide.S | 24 - .../interpreter/mterp/arm/fbinopWide2addr.S | 22 - runtime/interpreter/mterp/arm/field.S | 16 - .../interpreter/mterp/arm/floating_point.S | 482 +++++++++ runtime/interpreter/mterp/arm/footer.S | 298 ------ runtime/interpreter/mterp/arm/funop.S | 18 - runtime/interpreter/mterp/arm/funopNarrower.S | 18 - runtime/interpreter/mterp/arm/funopWider.S | 19 - runtime/interpreter/mterp/arm/header.S | 313 ------ .../interpreter/mterp/arm/instruction_end.S | 6 - .../mterp/arm/instruction_end_alt.S | 6 - .../mterp/arm/instruction_end_sister.S | 6 - .../interpreter/mterp/arm/instruction_start.S | 7 - .../mterp/arm/instruction_start_alt.S | 7 - .../mterp/arm/instruction_start_sister.S | 8 - runtime/interpreter/mterp/arm/invoke.S | 99 ++ .../mterp/arm/invoke_polymorphic.S | 21 - runtime/interpreter/mterp/arm/main.S | 756 ++++++++++++++ runtime/interpreter/mterp/arm/object.S | 275 +++++ runtime/interpreter/mterp/arm/op_add_double.S | 2 - .../mterp/arm/op_add_double_2addr.S | 2 - runtime/interpreter/mterp/arm/op_add_float.S | 2 - .../mterp/arm/op_add_float_2addr.S | 2 - runtime/interpreter/mterp/arm/op_add_int.S | 2 - .../interpreter/mterp/arm/op_add_int_2addr.S | 2 - .../interpreter/mterp/arm/op_add_int_lit16.S | 2 - .../interpreter/mterp/arm/op_add_int_lit8.S | 2 - runtime/interpreter/mterp/arm/op_add_long.S | 2 - .../interpreter/mterp/arm/op_add_long_2addr.S | 2 - runtime/interpreter/mterp/arm/op_aget.S | 29 - .../interpreter/mterp/arm/op_aget_boolean.S | 2 - runtime/interpreter/mterp/arm/op_aget_byte.S | 2 - runtime/interpreter/mterp/arm/op_aget_char.S | 2 - .../interpreter/mterp/arm/op_aget_object.S | 22 - runtime/interpreter/mterp/arm/op_aget_short.S | 2 - runtime/interpreter/mterp/arm/op_aget_wide.S | 26 - runtime/interpreter/mterp/arm/op_and_int.S | 2 - .../interpreter/mterp/arm/op_and_int_2addr.S | 2 - .../interpreter/mterp/arm/op_and_int_lit16.S | 2 - .../interpreter/mterp/arm/op_and_int_lit8.S | 2 - runtime/interpreter/mterp/arm/op_and_long.S | 2 - .../interpreter/mterp/arm/op_and_long_2addr.S | 2 - runtime/interpreter/mterp/arm/op_aput.S | 29 - .../interpreter/mterp/arm/op_aput_boolean.S | 2 - runtime/interpreter/mterp/arm/op_aput_byte.S | 2 - runtime/interpreter/mterp/arm/op_aput_char.S | 2 - .../interpreter/mterp/arm/op_aput_object.S | 15 - runtime/interpreter/mterp/arm/op_aput_short.S | 2 - runtime/interpreter/mterp/arm/op_aput_wide.S | 25 - .../interpreter/mterp/arm/op_array_length.S | 14 - runtime/interpreter/mterp/arm/op_check_cast.S | 18 - runtime/interpreter/mterp/arm/op_cmp_long.S | 24 - .../interpreter/mterp/arm/op_cmpg_double.S | 35 - runtime/interpreter/mterp/arm/op_cmpg_float.S | 35 - .../interpreter/mterp/arm/op_cmpl_double.S | 35 - runtime/interpreter/mterp/arm/op_cmpl_float.S | 35 - runtime/interpreter/mterp/arm/op_const.S | 10 - runtime/interpreter/mterp/arm/op_const_16.S | 8 - runtime/interpreter/mterp/arm/op_const_4.S | 8 - .../interpreter/mterp/arm/op_const_class.S | 2 - .../interpreter/mterp/arm/op_const_high16.S | 9 - .../mterp/arm/op_const_method_handle.S | 2 - .../mterp/arm/op_const_method_type.S | 2 - .../interpreter/mterp/arm/op_const_string.S | 2 - .../mterp/arm/op_const_string_jumbo.S | 16 - runtime/interpreter/mterp/arm/op_const_wide.S | 15 - .../interpreter/mterp/arm/op_const_wide_16.S | 11 - .../interpreter/mterp/arm/op_const_wide_32.S | 13 - .../mterp/arm/op_const_wide_high16.S | 12 - runtime/interpreter/mterp/arm/op_div_double.S | 2 - .../mterp/arm/op_div_double_2addr.S | 2 - runtime/interpreter/mterp/arm/op_div_float.S | 2 - .../mterp/arm/op_div_float_2addr.S | 2 - runtime/interpreter/mterp/arm/op_div_int.S | 30 - .../interpreter/mterp/arm/op_div_int_2addr.S | 29 - .../interpreter/mterp/arm/op_div_int_lit16.S | 28 - .../interpreter/mterp/arm/op_div_int_lit8.S | 29 - runtime/interpreter/mterp/arm/op_div_long.S | 2 - .../interpreter/mterp/arm/op_div_long_2addr.S | 2 - .../mterp/arm/op_double_to_float.S | 2 - .../interpreter/mterp/arm/op_double_to_int.S | 2 - .../interpreter/mterp/arm/op_double_to_long.S | 34 - .../mterp/arm/op_fill_array_data.S | 15 - .../mterp/arm/op_filled_new_array.S | 19 - .../mterp/arm/op_filled_new_array_range.S | 2 - .../mterp/arm/op_float_to_double.S | 2 - .../interpreter/mterp/arm/op_float_to_int.S | 2 - .../interpreter/mterp/arm/op_float_to_long.S | 32 - runtime/interpreter/mterp/arm/op_goto.S | 10 - runtime/interpreter/mterp/arm/op_goto_16.S | 10 - runtime/interpreter/mterp/arm/op_goto_32.S | 17 - runtime/interpreter/mterp/arm/op_if_eq.S | 2 - runtime/interpreter/mterp/arm/op_if_eqz.S | 2 - runtime/interpreter/mterp/arm/op_if_ge.S | 2 - runtime/interpreter/mterp/arm/op_if_gez.S | 2 - runtime/interpreter/mterp/arm/op_if_gt.S | 2 - runtime/interpreter/mterp/arm/op_if_gtz.S | 2 - runtime/interpreter/mterp/arm/op_if_le.S | 2 - runtime/interpreter/mterp/arm/op_if_lez.S | 2 - runtime/interpreter/mterp/arm/op_if_lt.S | 2 - runtime/interpreter/mterp/arm/op_if_ltz.S | 2 - runtime/interpreter/mterp/arm/op_if_ne.S | 2 - runtime/interpreter/mterp/arm/op_if_nez.S | 2 - runtime/interpreter/mterp/arm/op_iget.S | 2 - .../interpreter/mterp/arm/op_iget_boolean.S | 2 - .../mterp/arm/op_iget_boolean_quick.S | 2 - runtime/interpreter/mterp/arm/op_iget_byte.S | 2 - .../mterp/arm/op_iget_byte_quick.S | 2 - runtime/interpreter/mterp/arm/op_iget_char.S | 2 - .../mterp/arm/op_iget_char_quick.S | 2 - .../interpreter/mterp/arm/op_iget_object.S | 2 - .../mterp/arm/op_iget_object_quick.S | 17 - runtime/interpreter/mterp/arm/op_iget_quick.S | 14 - runtime/interpreter/mterp/arm/op_iget_short.S | 2 - .../mterp/arm/op_iget_short_quick.S | 2 - runtime/interpreter/mterp/arm/op_iget_wide.S | 2 - .../mterp/arm/op_iget_wide_quick.S | 15 - .../interpreter/mterp/arm/op_instance_of.S | 24 - .../interpreter/mterp/arm/op_int_to_byte.S | 2 - .../interpreter/mterp/arm/op_int_to_char.S | 2 - .../interpreter/mterp/arm/op_int_to_double.S | 2 - .../interpreter/mterp/arm/op_int_to_float.S | 2 - .../interpreter/mterp/arm/op_int_to_long.S | 2 - .../interpreter/mterp/arm/op_int_to_short.S | 2 - .../interpreter/mterp/arm/op_invoke_custom.S | 9 - .../mterp/arm/op_invoke_custom_range.S | 2 - .../interpreter/mterp/arm/op_invoke_direct.S | 2 - .../mterp/arm/op_invoke_direct_range.S | 2 - .../mterp/arm/op_invoke_interface.S | 9 - .../mterp/arm/op_invoke_interface_range.S | 2 - .../mterp/arm/op_invoke_polymorphic.S | 2 - .../mterp/arm/op_invoke_polymorphic_range.S | 2 - .../interpreter/mterp/arm/op_invoke_static.S | 3 - .../mterp/arm/op_invoke_static_range.S | 2 - .../interpreter/mterp/arm/op_invoke_super.S | 9 - .../mterp/arm/op_invoke_super_range.S | 2 - .../interpreter/mterp/arm/op_invoke_virtual.S | 9 - .../mterp/arm/op_invoke_virtual_quick.S | 2 - .../mterp/arm/op_invoke_virtual_range.S | 2 - .../mterp/arm/op_invoke_virtual_range_quick.S | 2 - runtime/interpreter/mterp/arm/op_iput.S | 2 - .../interpreter/mterp/arm/op_iput_boolean.S | 2 - .../mterp/arm/op_iput_boolean_quick.S | 2 - runtime/interpreter/mterp/arm/op_iput_byte.S | 2 - .../mterp/arm/op_iput_byte_quick.S | 2 - runtime/interpreter/mterp/arm/op_iput_char.S | 2 - .../mterp/arm/op_iput_char_quick.S | 2 - .../interpreter/mterp/arm/op_iput_object.S | 2 - .../mterp/arm/op_iput_object_quick.S | 11 - runtime/interpreter/mterp/arm/op_iput_quick.S | 14 - runtime/interpreter/mterp/arm/op_iput_short.S | 2 - .../mterp/arm/op_iput_short_quick.S | 2 - runtime/interpreter/mterp/arm/op_iput_wide.S | 2 - .../mterp/arm/op_iput_wide_quick.S | 14 - .../interpreter/mterp/arm/op_long_to_double.S | 27 - .../interpreter/mterp/arm/op_long_to_float.S | 2 - .../interpreter/mterp/arm/op_long_to_int.S | 3 - .../interpreter/mterp/arm/op_monitor_enter.S | 15 - .../interpreter/mterp/arm/op_monitor_exit.S | 19 - runtime/interpreter/mterp/arm/op_move.S | 14 - runtime/interpreter/mterp/arm/op_move_16.S | 14 - .../interpreter/mterp/arm/op_move_exception.S | 10 - .../interpreter/mterp/arm/op_move_from16.S | 14 - .../interpreter/mterp/arm/op_move_object.S | 2 - .../interpreter/mterp/arm/op_move_object_16.S | 2 - .../mterp/arm/op_move_object_from16.S | 2 - .../interpreter/mterp/arm/op_move_result.S | 14 - .../mterp/arm/op_move_result_object.S | 2 - .../mterp/arm/op_move_result_wide.S | 11 - runtime/interpreter/mterp/arm/op_move_wide.S | 13 - .../interpreter/mterp/arm/op_move_wide_16.S | 13 - .../mterp/arm/op_move_wide_from16.S | 13 - runtime/interpreter/mterp/arm/op_mul_double.S | 2 - .../mterp/arm/op_mul_double_2addr.S | 2 - runtime/interpreter/mterp/arm/op_mul_float.S | 2 - .../mterp/arm/op_mul_float_2addr.S | 2 - runtime/interpreter/mterp/arm/op_mul_int.S | 3 - .../interpreter/mterp/arm/op_mul_int_2addr.S | 3 - .../interpreter/mterp/arm/op_mul_int_lit16.S | 3 - .../interpreter/mterp/arm/op_mul_int_lit8.S | 3 - runtime/interpreter/mterp/arm/op_mul_long.S | 38 - .../interpreter/mterp/arm/op_mul_long_2addr.S | 25 - runtime/interpreter/mterp/arm/op_neg_double.S | 2 - runtime/interpreter/mterp/arm/op_neg_float.S | 2 - runtime/interpreter/mterp/arm/op_neg_int.S | 2 - runtime/interpreter/mterp/arm/op_neg_long.S | 2 - runtime/interpreter/mterp/arm/op_new_array.S | 20 - .../interpreter/mterp/arm/op_new_instance.S | 15 - runtime/interpreter/mterp/arm/op_nop.S | 4 - runtime/interpreter/mterp/arm/op_not_int.S | 2 - runtime/interpreter/mterp/arm/op_not_long.S | 2 - runtime/interpreter/mterp/arm/op_or_int.S | 2 - .../interpreter/mterp/arm/op_or_int_2addr.S | 2 - .../interpreter/mterp/arm/op_or_int_lit16.S | 2 - .../interpreter/mterp/arm/op_or_int_lit8.S | 2 - runtime/interpreter/mterp/arm/op_or_long.S | 2 - .../interpreter/mterp/arm/op_or_long_2addr.S | 2 - .../interpreter/mterp/arm/op_packed_switch.S | 20 - runtime/interpreter/mterp/arm/op_rem_double.S | 3 - .../mterp/arm/op_rem_double_2addr.S | 3 - runtime/interpreter/mterp/arm/op_rem_float.S | 3 - .../mterp/arm/op_rem_float_2addr.S | 3 - runtime/interpreter/mterp/arm/op_rem_int.S | 33 - .../interpreter/mterp/arm/op_rem_int_2addr.S | 32 - .../interpreter/mterp/arm/op_rem_int_lit16.S | 31 - .../interpreter/mterp/arm/op_rem_int_lit8.S | 32 - runtime/interpreter/mterp/arm/op_rem_long.S | 3 - .../interpreter/mterp/arm/op_rem_long_2addr.S | 3 - runtime/interpreter/mterp/arm/op_return.S | 17 - .../interpreter/mterp/arm/op_return_object.S | 2 - .../interpreter/mterp/arm/op_return_void.S | 10 - .../mterp/arm/op_return_void_no_barrier.S | 8 - .../interpreter/mterp/arm/op_return_wide.S | 15 - runtime/interpreter/mterp/arm/op_rsub_int.S | 3 - .../interpreter/mterp/arm/op_rsub_int_lit8.S | 2 - runtime/interpreter/mterp/arm/op_sget.S | 2 - .../interpreter/mterp/arm/op_sget_boolean.S | 2 - runtime/interpreter/mterp/arm/op_sget_byte.S | 2 - runtime/interpreter/mterp/arm/op_sget_char.S | 2 - .../interpreter/mterp/arm/op_sget_object.S | 2 - runtime/interpreter/mterp/arm/op_sget_short.S | 2 - runtime/interpreter/mterp/arm/op_sget_wide.S | 2 - runtime/interpreter/mterp/arm/op_shl_int.S | 2 - .../interpreter/mterp/arm/op_shl_int_2addr.S | 2 - .../interpreter/mterp/arm/op_shl_int_lit8.S | 2 - runtime/interpreter/mterp/arm/op_shl_long.S | 28 - .../interpreter/mterp/arm/op_shl_long_2addr.S | 23 - runtime/interpreter/mterp/arm/op_shr_int.S | 2 - .../interpreter/mterp/arm/op_shr_int_2addr.S | 2 - .../interpreter/mterp/arm/op_shr_int_lit8.S | 2 - runtime/interpreter/mterp/arm/op_shr_long.S | 28 - .../interpreter/mterp/arm/op_shr_long_2addr.S | 23 - .../interpreter/mterp/arm/op_sparse_switch.S | 2 - runtime/interpreter/mterp/arm/op_sput.S | 2 - .../interpreter/mterp/arm/op_sput_boolean.S | 2 - runtime/interpreter/mterp/arm/op_sput_byte.S | 2 - runtime/interpreter/mterp/arm/op_sput_char.S | 2 - .../interpreter/mterp/arm/op_sput_object.S | 2 - runtime/interpreter/mterp/arm/op_sput_short.S | 2 - runtime/interpreter/mterp/arm/op_sput_wide.S | 2 - runtime/interpreter/mterp/arm/op_sub_double.S | 2 - .../mterp/arm/op_sub_double_2addr.S | 2 - runtime/interpreter/mterp/arm/op_sub_float.S | 2 - .../mterp/arm/op_sub_float_2addr.S | 2 - runtime/interpreter/mterp/arm/op_sub_int.S | 2 - .../interpreter/mterp/arm/op_sub_int_2addr.S | 2 - runtime/interpreter/mterp/arm/op_sub_long.S | 2 - .../interpreter/mterp/arm/op_sub_long_2addr.S | 2 - runtime/interpreter/mterp/arm/op_throw.S | 12 - runtime/interpreter/mterp/arm/op_unused_3e.S | 2 - runtime/interpreter/mterp/arm/op_unused_3f.S | 2 - runtime/interpreter/mterp/arm/op_unused_40.S | 2 - runtime/interpreter/mterp/arm/op_unused_41.S | 2 - runtime/interpreter/mterp/arm/op_unused_42.S | 2 - runtime/interpreter/mterp/arm/op_unused_43.S | 2 - runtime/interpreter/mterp/arm/op_unused_73.S | 2 - runtime/interpreter/mterp/arm/op_unused_79.S | 2 - runtime/interpreter/mterp/arm/op_unused_7a.S | 2 - runtime/interpreter/mterp/arm/op_unused_f3.S | 2 - runtime/interpreter/mterp/arm/op_unused_f4.S | 2 - runtime/interpreter/mterp/arm/op_unused_f5.S | 2 - runtime/interpreter/mterp/arm/op_unused_f6.S | 2 - runtime/interpreter/mterp/arm/op_unused_f7.S | 2 - runtime/interpreter/mterp/arm/op_unused_f8.S | 2 - runtime/interpreter/mterp/arm/op_unused_f9.S | 2 - runtime/interpreter/mterp/arm/op_unused_fc.S | 2 - runtime/interpreter/mterp/arm/op_unused_fd.S | 2 - runtime/interpreter/mterp/arm/op_ushr_int.S | 2 - .../interpreter/mterp/arm/op_ushr_int_2addr.S | 2 - .../interpreter/mterp/arm/op_ushr_int_lit8.S | 2 - runtime/interpreter/mterp/arm/op_ushr_long.S | 28 - .../mterp/arm/op_ushr_long_2addr.S | 23 - runtime/interpreter/mterp/arm/op_xor_int.S | 2 - .../interpreter/mterp/arm/op_xor_int_2addr.S | 2 - .../interpreter/mterp/arm/op_xor_int_lit16.S | 2 - .../interpreter/mterp/arm/op_xor_int_lit8.S | 2 - runtime/interpreter/mterp/arm/op_xor_long.S | 2 - .../interpreter/mterp/arm/op_xor_long_2addr.S | 2 - runtime/interpreter/mterp/arm/other.S | 379 +++++++ runtime/interpreter/mterp/arm/unop.S | 20 - runtime/interpreter/mterp/arm/unopNarrower.S | 23 - runtime/interpreter/mterp/arm/unopWide.S | 22 - runtime/interpreter/mterp/arm/unopWider.S | 21 - runtime/interpreter/mterp/arm/unused.S | 5 - runtime/interpreter/mterp/arm/zcmp.S | 18 - runtime/interpreter/mterp/arm64/alt_stub.S | 13 - runtime/interpreter/mterp/arm64/arithmetic.S | 507 +++++++++ runtime/interpreter/mterp/arm64/array.S | 235 +++++ runtime/interpreter/mterp/arm64/bincmp.S | 20 - runtime/interpreter/mterp/arm64/binop.S | 33 - runtime/interpreter/mterp/arm64/binop2addr.S | 30 - runtime/interpreter/mterp/arm64/binopLit16.S | 28 - runtime/interpreter/mterp/arm64/binopLit8.S | 34 - runtime/interpreter/mterp/arm64/binopWide.S | 30 - .../interpreter/mterp/arm64/binopWide2addr.S | 29 - runtime/interpreter/mterp/arm64/close_cfi.S | 5 - runtime/interpreter/mterp/arm64/const.S | 17 - .../interpreter/mterp/arm64/control_flow.S | 223 ++++ runtime/interpreter/mterp/arm64/entry.S | 67 -- runtime/interpreter/mterp/arm64/fallback.S | 4 - runtime/interpreter/mterp/arm64/fbinop.S | 19 - runtime/interpreter/mterp/arm64/fbinop2addr.S | 18 - runtime/interpreter/mterp/arm64/fcmp.S | 19 - runtime/interpreter/mterp/arm64/field.S | 15 - .../interpreter/mterp/arm64/floating_point.S | 269 +++++ runtime/interpreter/mterp/arm64/footer.S | 305 ------ runtime/interpreter/mterp/arm64/funopNarrow.S | 17 - .../interpreter/mterp/arm64/funopNarrower.S | 16 - runtime/interpreter/mterp/arm64/funopWide.S | 16 - runtime/interpreter/mterp/arm64/funopWider.S | 16 - runtime/interpreter/mterp/arm64/header.S | 354 ------- .../interpreter/mterp/arm64/instruction_end.S | 6 - .../mterp/arm64/instruction_end_alt.S | 6 - .../mterp/arm64/instruction_end_sister.S | 6 - .../mterp/arm64/instruction_start.S | 7 - .../mterp/arm64/instruction_start_alt.S | 7 - .../mterp/arm64/instruction_start_sister.S | 8 - runtime/interpreter/mterp/arm64/invoke.S | 90 ++ .../mterp/arm64/invoke_polymorphic.S | 19 - runtime/interpreter/mterp/arm64/main.S | 799 ++++++++++++++ runtime/interpreter/mterp/arm64/object.S | 263 +++++ .../interpreter/mterp/arm64/op_add_double.S | 2 - .../mterp/arm64/op_add_double_2addr.S | 2 - .../interpreter/mterp/arm64/op_add_float.S | 2 - .../mterp/arm64/op_add_float_2addr.S | 2 - runtime/interpreter/mterp/arm64/op_add_int.S | 2 - .../mterp/arm64/op_add_int_2addr.S | 2 - .../mterp/arm64/op_add_int_lit16.S | 2 - .../interpreter/mterp/arm64/op_add_int_lit8.S | 2 - runtime/interpreter/mterp/arm64/op_add_long.S | 2 - .../mterp/arm64/op_add_long_2addr.S | 2 - runtime/interpreter/mterp/arm64/op_aget.S | 28 - .../interpreter/mterp/arm64/op_aget_boolean.S | 2 - .../interpreter/mterp/arm64/op_aget_byte.S | 2 - .../interpreter/mterp/arm64/op_aget_char.S | 2 - .../interpreter/mterp/arm64/op_aget_object.S | 21 - .../interpreter/mterp/arm64/op_aget_short.S | 2 - .../interpreter/mterp/arm64/op_aget_wide.S | 22 - runtime/interpreter/mterp/arm64/op_and_int.S | 2 - .../mterp/arm64/op_and_int_2addr.S | 2 - .../mterp/arm64/op_and_int_lit16.S | 2 - .../interpreter/mterp/arm64/op_and_int_lit8.S | 2 - runtime/interpreter/mterp/arm64/op_and_long.S | 2 - .../mterp/arm64/op_and_long_2addr.S | 2 - runtime/interpreter/mterp/arm64/op_aput.S | 28 - .../interpreter/mterp/arm64/op_aput_boolean.S | 2 - .../interpreter/mterp/arm64/op_aput_byte.S | 2 - .../interpreter/mterp/arm64/op_aput_char.S | 2 - .../interpreter/mterp/arm64/op_aput_object.S | 14 - .../interpreter/mterp/arm64/op_aput_short.S | 2 - .../interpreter/mterp/arm64/op_aput_wide.S | 22 - .../interpreter/mterp/arm64/op_array_length.S | 13 - .../interpreter/mterp/arm64/op_check_cast.S | 17 - runtime/interpreter/mterp/arm64/op_cmp_long.S | 14 - .../interpreter/mterp/arm64/op_cmpg_double.S | 2 - .../interpreter/mterp/arm64/op_cmpg_float.S | 2 - .../interpreter/mterp/arm64/op_cmpl_double.S | 2 - .../interpreter/mterp/arm64/op_cmpl_float.S | 2 - runtime/interpreter/mterp/arm64/op_const.S | 10 - runtime/interpreter/mterp/arm64/op_const_16.S | 8 - runtime/interpreter/mterp/arm64/op_const_4.S | 8 - .../interpreter/mterp/arm64/op_const_class.S | 2 - .../interpreter/mterp/arm64/op_const_high16.S | 9 - .../mterp/arm64/op_const_method_handle.S | 2 - .../mterp/arm64/op_const_method_type.S | 2 - .../interpreter/mterp/arm64/op_const_string.S | 2 - .../mterp/arm64/op_const_string_jumbo.S | 15 - .../interpreter/mterp/arm64/op_const_wide.S | 14 - .../mterp/arm64/op_const_wide_16.S | 8 - .../mterp/arm64/op_const_wide_32.S | 10 - .../mterp/arm64/op_const_wide_high16.S | 9 - .../interpreter/mterp/arm64/op_div_double.S | 2 - .../mterp/arm64/op_div_double_2addr.S | 2 - .../interpreter/mterp/arm64/op_div_float.S | 2 - .../mterp/arm64/op_div_float_2addr.S | 2 - runtime/interpreter/mterp/arm64/op_div_int.S | 2 - .../mterp/arm64/op_div_int_2addr.S | 2 - .../mterp/arm64/op_div_int_lit16.S | 2 - .../interpreter/mterp/arm64/op_div_int_lit8.S | 2 - runtime/interpreter/mterp/arm64/op_div_long.S | 2 - .../mterp/arm64/op_div_long_2addr.S | 2 - .../mterp/arm64/op_double_to_float.S | 2 - .../mterp/arm64/op_double_to_int.S | 2 - .../mterp/arm64/op_double_to_long.S | 2 - .../mterp/arm64/op_fill_array_data.S | 14 - .../mterp/arm64/op_filled_new_array.S | 18 - .../mterp/arm64/op_filled_new_array_range.S | 2 - .../mterp/arm64/op_float_to_double.S | 2 - .../interpreter/mterp/arm64/op_float_to_int.S | 2 - .../mterp/arm64/op_float_to_long.S | 2 - runtime/interpreter/mterp/arm64/op_goto.S | 10 - runtime/interpreter/mterp/arm64/op_goto_16.S | 10 - runtime/interpreter/mterp/arm64/op_goto_32.S | 17 - runtime/interpreter/mterp/arm64/op_if_eq.S | 2 - runtime/interpreter/mterp/arm64/op_if_eqz.S | 2 - runtime/interpreter/mterp/arm64/op_if_ge.S | 2 - runtime/interpreter/mterp/arm64/op_if_gez.S | 2 - runtime/interpreter/mterp/arm64/op_if_gt.S | 2 - runtime/interpreter/mterp/arm64/op_if_gtz.S | 2 - runtime/interpreter/mterp/arm64/op_if_le.S | 2 - runtime/interpreter/mterp/arm64/op_if_lez.S | 2 - runtime/interpreter/mterp/arm64/op_if_lt.S | 2 - runtime/interpreter/mterp/arm64/op_if_ltz.S | 2 - runtime/interpreter/mterp/arm64/op_if_ne.S | 2 - runtime/interpreter/mterp/arm64/op_if_nez.S | 2 - runtime/interpreter/mterp/arm64/op_iget.S | 2 - .../interpreter/mterp/arm64/op_iget_boolean.S | 2 - .../mterp/arm64/op_iget_boolean_quick.S | 2 - .../interpreter/mterp/arm64/op_iget_byte.S | 2 - .../mterp/arm64/op_iget_byte_quick.S | 2 - .../interpreter/mterp/arm64/op_iget_char.S | 2 - .../mterp/arm64/op_iget_char_quick.S | 2 - .../interpreter/mterp/arm64/op_iget_object.S | 2 - .../mterp/arm64/op_iget_object_quick.S | 16 - .../interpreter/mterp/arm64/op_iget_quick.S | 14 - .../interpreter/mterp/arm64/op_iget_short.S | 2 - .../mterp/arm64/op_iget_short_quick.S | 2 - .../interpreter/mterp/arm64/op_iget_wide.S | 2 - .../mterp/arm64/op_iget_wide_quick.S | 12 - .../interpreter/mterp/arm64/op_instance_of.S | 23 - .../interpreter/mterp/arm64/op_int_to_byte.S | 2 - .../interpreter/mterp/arm64/op_int_to_char.S | 2 - .../mterp/arm64/op_int_to_double.S | 2 - .../interpreter/mterp/arm64/op_int_to_float.S | 2 - .../interpreter/mterp/arm64/op_int_to_long.S | 9 - .../interpreter/mterp/arm64/op_int_to_short.S | 2 - .../mterp/arm64/op_invoke_custom.S | 2 - .../mterp/arm64/op_invoke_custom_range.S | 2 - .../mterp/arm64/op_invoke_direct.S | 2 - .../mterp/arm64/op_invoke_direct_range.S | 2 - .../mterp/arm64/op_invoke_interface.S | 9 - .../mterp/arm64/op_invoke_interface_range.S | 2 - .../mterp/arm64/op_invoke_polymorphic.S | 2 - .../mterp/arm64/op_invoke_polymorphic_range.S | 2 - .../mterp/arm64/op_invoke_static.S | 3 - .../mterp/arm64/op_invoke_static_range.S | 2 - .../interpreter/mterp/arm64/op_invoke_super.S | 9 - .../mterp/arm64/op_invoke_super_range.S | 2 - .../mterp/arm64/op_invoke_virtual.S | 9 - .../mterp/arm64/op_invoke_virtual_quick.S | 2 - .../mterp/arm64/op_invoke_virtual_range.S | 2 - .../arm64/op_invoke_virtual_range_quick.S | 2 - runtime/interpreter/mterp/arm64/op_iput.S | 2 - .../interpreter/mterp/arm64/op_iput_boolean.S | 2 - .../mterp/arm64/op_iput_boolean_quick.S | 2 - .../interpreter/mterp/arm64/op_iput_byte.S | 2 - .../mterp/arm64/op_iput_byte_quick.S | 2 - .../interpreter/mterp/arm64/op_iput_char.S | 2 - .../mterp/arm64/op_iput_char_quick.S | 2 - .../interpreter/mterp/arm64/op_iput_object.S | 2 - .../mterp/arm64/op_iput_object_quick.S | 10 - .../interpreter/mterp/arm64/op_iput_quick.S | 13 - .../interpreter/mterp/arm64/op_iput_short.S | 2 - .../mterp/arm64/op_iput_short_quick.S | 2 - .../interpreter/mterp/arm64/op_iput_wide.S | 2 - .../mterp/arm64/op_iput_wide_quick.S | 12 - .../mterp/arm64/op_long_to_double.S | 2 - .../mterp/arm64/op_long_to_float.S | 2 - .../interpreter/mterp/arm64/op_long_to_int.S | 3 - .../mterp/arm64/op_monitor_enter.S | 14 - .../interpreter/mterp/arm64/op_monitor_exit.S | 18 - runtime/interpreter/mterp/arm64/op_move.S | 14 - runtime/interpreter/mterp/arm64/op_move_16.S | 14 - .../mterp/arm64/op_move_exception.S | 10 - .../interpreter/mterp/arm64/op_move_from16.S | 14 - .../interpreter/mterp/arm64/op_move_object.S | 2 - .../mterp/arm64/op_move_object_16.S | 2 - .../mterp/arm64/op_move_object_from16.S | 2 - .../interpreter/mterp/arm64/op_move_result.S | 14 - .../mterp/arm64/op_move_result_object.S | 2 - .../mterp/arm64/op_move_result_wide.S | 10 - .../interpreter/mterp/arm64/op_move_wide.S | 10 - .../interpreter/mterp/arm64/op_move_wide_16.S | 10 - .../mterp/arm64/op_move_wide_from16.S | 10 - .../interpreter/mterp/arm64/op_mul_double.S | 2 - .../mterp/arm64/op_mul_double_2addr.S | 2 - .../interpreter/mterp/arm64/op_mul_float.S | 2 - .../mterp/arm64/op_mul_float_2addr.S | 2 - runtime/interpreter/mterp/arm64/op_mul_int.S | 3 - .../mterp/arm64/op_mul_int_2addr.S | 3 - .../mterp/arm64/op_mul_int_lit16.S | 3 - .../interpreter/mterp/arm64/op_mul_int_lit8.S | 3 - runtime/interpreter/mterp/arm64/op_mul_long.S | 2 - .../mterp/arm64/op_mul_long_2addr.S | 2 - .../interpreter/mterp/arm64/op_neg_double.S | 2 - .../interpreter/mterp/arm64/op_neg_float.S | 2 - runtime/interpreter/mterp/arm64/op_neg_int.S | 2 - runtime/interpreter/mterp/arm64/op_neg_long.S | 2 - .../interpreter/mterp/arm64/op_new_array.S | 19 - .../interpreter/mterp/arm64/op_new_instance.S | 14 - runtime/interpreter/mterp/arm64/op_nop.S | 4 - runtime/interpreter/mterp/arm64/op_not_int.S | 2 - runtime/interpreter/mterp/arm64/op_not_long.S | 2 - runtime/interpreter/mterp/arm64/op_or_int.S | 2 - .../interpreter/mterp/arm64/op_or_int_2addr.S | 2 - .../interpreter/mterp/arm64/op_or_int_lit16.S | 2 - .../interpreter/mterp/arm64/op_or_int_lit8.S | 2 - runtime/interpreter/mterp/arm64/op_or_long.S | 2 - .../mterp/arm64/op_or_long_2addr.S | 2 - .../mterp/arm64/op_packed_switch.S | 20 - .../interpreter/mterp/arm64/op_rem_double.S | 14 - .../mterp/arm64/op_rem_double_2addr.S | 13 - .../interpreter/mterp/arm64/op_rem_float.S | 3 - .../mterp/arm64/op_rem_float_2addr.S | 12 - runtime/interpreter/mterp/arm64/op_rem_int.S | 2 - .../mterp/arm64/op_rem_int_2addr.S | 2 - .../mterp/arm64/op_rem_int_lit16.S | 2 - .../interpreter/mterp/arm64/op_rem_int_lit8.S | 2 - runtime/interpreter/mterp/arm64/op_rem_long.S | 2 - .../mterp/arm64/op_rem_long_2addr.S | 2 - runtime/interpreter/mterp/arm64/op_return.S | 20 - .../mterp/arm64/op_return_object.S | 2 - .../interpreter/mterp/arm64/op_return_void.S | 13 - .../mterp/arm64/op_return_void_no_barrier.S | 11 - .../interpreter/mterp/arm64/op_return_wide.S | 19 - runtime/interpreter/mterp/arm64/op_rsub_int.S | 3 - .../mterp/arm64/op_rsub_int_lit8.S | 2 - runtime/interpreter/mterp/arm64/op_sget.S | 2 - .../interpreter/mterp/arm64/op_sget_boolean.S | 2 - .../interpreter/mterp/arm64/op_sget_byte.S | 2 - .../interpreter/mterp/arm64/op_sget_char.S | 2 - .../interpreter/mterp/arm64/op_sget_object.S | 2 - .../interpreter/mterp/arm64/op_sget_short.S | 2 - .../interpreter/mterp/arm64/op_sget_wide.S | 2 - runtime/interpreter/mterp/arm64/op_shl_int.S | 2 - .../mterp/arm64/op_shl_int_2addr.S | 2 - .../interpreter/mterp/arm64/op_shl_int_lit8.S | 2 - runtime/interpreter/mterp/arm64/op_shl_long.S | 2 - .../mterp/arm64/op_shl_long_2addr.S | 2 - runtime/interpreter/mterp/arm64/op_shr_int.S | 2 - .../mterp/arm64/op_shr_int_2addr.S | 2 - .../interpreter/mterp/arm64/op_shr_int_lit8.S | 2 - runtime/interpreter/mterp/arm64/op_shr_long.S | 2 - .../mterp/arm64/op_shr_long_2addr.S | 2 - .../mterp/arm64/op_sparse_switch.S | 2 - runtime/interpreter/mterp/arm64/op_sput.S | 2 - .../interpreter/mterp/arm64/op_sput_boolean.S | 2 - .../interpreter/mterp/arm64/op_sput_byte.S | 2 - .../interpreter/mterp/arm64/op_sput_char.S | 2 - .../interpreter/mterp/arm64/op_sput_object.S | 2 - .../interpreter/mterp/arm64/op_sput_short.S | 2 - .../interpreter/mterp/arm64/op_sput_wide.S | 2 - .../interpreter/mterp/arm64/op_sub_double.S | 2 - .../mterp/arm64/op_sub_double_2addr.S | 2 - .../interpreter/mterp/arm64/op_sub_float.S | 2 - .../mterp/arm64/op_sub_float_2addr.S | 2 - runtime/interpreter/mterp/arm64/op_sub_int.S | 2 - .../mterp/arm64/op_sub_int_2addr.S | 2 - runtime/interpreter/mterp/arm64/op_sub_long.S | 2 - .../mterp/arm64/op_sub_long_2addr.S | 2 - runtime/interpreter/mterp/arm64/op_throw.S | 11 - .../interpreter/mterp/arm64/op_unused_3e.S | 2 - .../interpreter/mterp/arm64/op_unused_3f.S | 2 - .../interpreter/mterp/arm64/op_unused_40.S | 2 - .../interpreter/mterp/arm64/op_unused_41.S | 2 - .../interpreter/mterp/arm64/op_unused_42.S | 2 - .../interpreter/mterp/arm64/op_unused_43.S | 2 - .../interpreter/mterp/arm64/op_unused_73.S | 2 - .../interpreter/mterp/arm64/op_unused_79.S | 2 - .../interpreter/mterp/arm64/op_unused_7a.S | 2 - .../interpreter/mterp/arm64/op_unused_f3.S | 2 - .../interpreter/mterp/arm64/op_unused_f4.S | 2 - .../interpreter/mterp/arm64/op_unused_f5.S | 2 - .../interpreter/mterp/arm64/op_unused_f6.S | 2 - .../interpreter/mterp/arm64/op_unused_f7.S | 2 - .../interpreter/mterp/arm64/op_unused_f8.S | 2 - .../interpreter/mterp/arm64/op_unused_f9.S | 2 - .../interpreter/mterp/arm64/op_unused_fc.S | 2 - .../interpreter/mterp/arm64/op_unused_fd.S | 2 - runtime/interpreter/mterp/arm64/op_ushr_int.S | 2 - .../mterp/arm64/op_ushr_int_2addr.S | 2 - .../mterp/arm64/op_ushr_int_lit8.S | 2 - .../interpreter/mterp/arm64/op_ushr_long.S | 2 - .../mterp/arm64/op_ushr_long_2addr.S | 2 - runtime/interpreter/mterp/arm64/op_xor_int.S | 2 - .../mterp/arm64/op_xor_int_2addr.S | 2 - .../mterp/arm64/op_xor_int_lit16.S | 2 - .../interpreter/mterp/arm64/op_xor_int_lit8.S | 2 - runtime/interpreter/mterp/arm64/op_xor_long.S | 2 - .../mterp/arm64/op_xor_long_2addr.S | 2 - runtime/interpreter/mterp/arm64/other.S | 355 +++++++ runtime/interpreter/mterp/arm64/shiftWide.S | 19 - .../interpreter/mterp/arm64/shiftWide2addr.S | 15 - runtime/interpreter/mterp/arm64/unop.S | 19 - runtime/interpreter/mterp/arm64/unopWide.S | 17 - runtime/interpreter/mterp/arm64/unused.S | 5 - runtime/interpreter/mterp/arm64/zcmp.S | 20 - runtime/interpreter/mterp/mips/alt_stub.S | 14 - runtime/interpreter/mterp/mips/arithmetic.S | 803 +++++++++++++++ runtime/interpreter/mterp/mips/array.S | 239 +++++ runtime/interpreter/mterp/mips/bincmp.S | 19 - runtime/interpreter/mterp/mips/binop.S | 32 - runtime/interpreter/mterp/mips/binop2addr.S | 28 - runtime/interpreter/mterp/mips/binopLit16.S | 28 - runtime/interpreter/mterp/mips/binopLit8.S | 30 - runtime/interpreter/mterp/mips/binopWide.S | 34 - .../interpreter/mterp/mips/binopWide2addr.S | 30 - runtime/interpreter/mterp/mips/const.S | 17 - runtime/interpreter/mterp/mips/control_flow.S | 214 ++++ runtime/interpreter/mterp/mips/entry.S | 76 -- runtime/interpreter/mterp/mips/fallback.S | 3 - runtime/interpreter/mterp/mips/fbinop.S | 19 - runtime/interpreter/mterp/mips/fbinop2addr.S | 19 - runtime/interpreter/mterp/mips/fbinopWide.S | 24 - .../interpreter/mterp/mips/fbinopWide2addr.S | 22 - runtime/interpreter/mterp/mips/field.S | 2 - .../interpreter/mterp/mips/floating_point.S | 518 ++++++++++ runtime/interpreter/mterp/mips/footer.S | 289 ------ runtime/interpreter/mterp/mips/funop.S | 16 - runtime/interpreter/mterp/mips/funopWider.S | 15 - .../interpreter/mterp/mips/instruction_end.S | 4 - .../mterp/mips/instruction_end_alt.S | 4 - .../mterp/mips/instruction_end_sister.S | 4 - .../mterp/mips/instruction_start.S | 5 - .../mterp/mips/instruction_start_alt.S | 5 - .../mterp/mips/instruction_start_sister.S | 6 - runtime/interpreter/mterp/mips/invoke.S | 68 ++ .../mterp/mips/invoke_polymorphic.S | 19 - .../mterp/mips/{header.S => main.S} | 420 ++++++++ runtime/interpreter/mterp/mips/object.S | 257 +++++ .../interpreter/mterp/mips/op_add_double.S | 2 - .../mterp/mips/op_add_double_2addr.S | 2 - runtime/interpreter/mterp/mips/op_add_float.S | 2 - .../mterp/mips/op_add_float_2addr.S | 2 - runtime/interpreter/mterp/mips/op_add_int.S | 2 - .../interpreter/mterp/mips/op_add_int_2addr.S | 2 - .../interpreter/mterp/mips/op_add_int_lit16.S | 2 - .../interpreter/mterp/mips/op_add_int_lit8.S | 2 - runtime/interpreter/mterp/mips/op_add_long.S | 10 - .../mterp/mips/op_add_long_2addr.S | 5 - runtime/interpreter/mterp/mips/op_aget.S | 28 - .../interpreter/mterp/mips/op_aget_boolean.S | 2 - runtime/interpreter/mterp/mips/op_aget_byte.S | 2 - runtime/interpreter/mterp/mips/op_aget_char.S | 2 - .../interpreter/mterp/mips/op_aget_object.S | 20 - .../interpreter/mterp/mips/op_aget_short.S | 2 - runtime/interpreter/mterp/mips/op_aget_wide.S | 23 - runtime/interpreter/mterp/mips/op_and_int.S | 2 - .../interpreter/mterp/mips/op_and_int_2addr.S | 2 - .../interpreter/mterp/mips/op_and_int_lit16.S | 2 - .../interpreter/mterp/mips/op_and_int_lit8.S | 2 - runtime/interpreter/mterp/mips/op_and_long.S | 2 - .../mterp/mips/op_and_long_2addr.S | 2 - runtime/interpreter/mterp/mips/op_aput.S | 27 - .../interpreter/mterp/mips/op_aput_boolean.S | 2 - runtime/interpreter/mterp/mips/op_aput_byte.S | 2 - runtime/interpreter/mterp/mips/op_aput_char.S | 2 - .../interpreter/mterp/mips/op_aput_object.S | 15 - .../interpreter/mterp/mips/op_aput_short.S | 2 - runtime/interpreter/mterp/mips/op_aput_wide.S | 25 - .../interpreter/mterp/mips/op_array_length.S | 14 - .../interpreter/mterp/mips/op_check_cast.S | 17 - runtime/interpreter/mterp/mips/op_cmp_long.S | 35 - .../interpreter/mterp/mips/op_cmpg_double.S | 2 - .../interpreter/mterp/mips/op_cmpg_float.S | 2 - .../interpreter/mterp/mips/op_cmpl_double.S | 52 - .../interpreter/mterp/mips/op_cmpl_float.S | 50 - runtime/interpreter/mterp/mips/op_const.S | 9 - runtime/interpreter/mterp/mips/op_const_16.S | 7 - runtime/interpreter/mterp/mips/op_const_4.S | 9 - .../interpreter/mterp/mips/op_const_class.S | 2 - .../interpreter/mterp/mips/op_const_high16.S | 8 - .../mterp/mips/op_const_method_handle.S | 2 - .../mterp/mips/op_const_method_type.S | 2 - .../interpreter/mterp/mips/op_const_string.S | 2 - .../mterp/mips/op_const_string_jumbo.S | 15 - .../interpreter/mterp/mips/op_const_wide.S | 12 - .../interpreter/mterp/mips/op_const_wide_16.S | 8 - .../interpreter/mterp/mips/op_const_wide_32.S | 10 - .../mterp/mips/op_const_wide_high16.S | 9 - .../interpreter/mterp/mips/op_div_double.S | 2 - .../mterp/mips/op_div_double_2addr.S | 2 - runtime/interpreter/mterp/mips/op_div_float.S | 2 - .../mterp/mips/op_div_float_2addr.S | 2 - runtime/interpreter/mterp/mips/op_div_int.S | 6 - .../interpreter/mterp/mips/op_div_int_2addr.S | 6 - .../interpreter/mterp/mips/op_div_int_lit16.S | 6 - .../interpreter/mterp/mips/op_div_int_lit8.S | 6 - runtime/interpreter/mterp/mips/op_div_long.S | 2 - .../mterp/mips/op_div_long_2addr.S | 2 - .../mterp/mips/op_double_to_float.S | 2 - .../interpreter/mterp/mips/op_double_to_int.S | 32 - .../mterp/mips/op_double_to_long.S | 51 - .../mterp/mips/op_fill_array_data.S | 14 - .../mterp/mips/op_filled_new_array.S | 18 - .../mterp/mips/op_filled_new_array_range.S | 2 - .../mterp/mips/op_float_to_double.S | 2 - .../interpreter/mterp/mips/op_float_to_int.S | 30 - .../interpreter/mterp/mips/op_float_to_long.S | 49 - runtime/interpreter/mterp/mips/op_goto.S | 11 - runtime/interpreter/mterp/mips/op_goto_16.S | 10 - runtime/interpreter/mterp/mips/op_goto_32.S | 15 - runtime/interpreter/mterp/mips/op_if_eq.S | 2 - runtime/interpreter/mterp/mips/op_if_eqz.S | 2 - runtime/interpreter/mterp/mips/op_if_ge.S | 2 - runtime/interpreter/mterp/mips/op_if_gez.S | 2 - runtime/interpreter/mterp/mips/op_if_gt.S | 2 - runtime/interpreter/mterp/mips/op_if_gtz.S | 2 - runtime/interpreter/mterp/mips/op_if_le.S | 2 - runtime/interpreter/mterp/mips/op_if_lez.S | 2 - runtime/interpreter/mterp/mips/op_if_lt.S | 2 - runtime/interpreter/mterp/mips/op_if_ltz.S | 2 - runtime/interpreter/mterp/mips/op_if_ne.S | 2 - runtime/interpreter/mterp/mips/op_if_nez.S | 2 - runtime/interpreter/mterp/mips/op_iget.S | 2 - .../interpreter/mterp/mips/op_iget_boolean.S | 2 - .../mterp/mips/op_iget_boolean_quick.S | 2 - runtime/interpreter/mterp/mips/op_iget_byte.S | 2 - .../mterp/mips/op_iget_byte_quick.S | 2 - runtime/interpreter/mterp/mips/op_iget_char.S | 2 - .../mterp/mips/op_iget_char_quick.S | 2 - .../interpreter/mterp/mips/op_iget_object.S | 2 - .../mterp/mips/op_iget_object_quick.S | 15 - .../interpreter/mterp/mips/op_iget_quick.S | 14 - .../interpreter/mterp/mips/op_iget_short.S | 2 - .../mterp/mips/op_iget_short_quick.S | 2 - runtime/interpreter/mterp/mips/op_iget_wide.S | 2 - .../mterp/mips/op_iget_wide_quick.S | 13 - .../interpreter/mterp/mips/op_instance_of.S | 22 - .../interpreter/mterp/mips/op_int_to_byte.S | 2 - .../interpreter/mterp/mips/op_int_to_char.S | 2 - .../interpreter/mterp/mips/op_int_to_double.S | 2 - .../interpreter/mterp/mips/op_int_to_float.S | 2 - .../interpreter/mterp/mips/op_int_to_long.S | 2 - .../interpreter/mterp/mips/op_int_to_short.S | 2 - .../interpreter/mterp/mips/op_invoke_custom.S | 2 - .../mterp/mips/op_invoke_custom_range.S | 2 - .../interpreter/mterp/mips/op_invoke_direct.S | 2 - .../mterp/mips/op_invoke_direct_range.S | 2 - .../mterp/mips/op_invoke_interface.S | 2 - .../mterp/mips/op_invoke_interface_range.S | 2 - .../mterp/mips/op_invoke_polymorphic.S | 2 - .../mterp/mips/op_invoke_polymorphic_range.S | 2 - .../interpreter/mterp/mips/op_invoke_static.S | 2 - .../mterp/mips/op_invoke_static_range.S | 2 - .../interpreter/mterp/mips/op_invoke_super.S | 2 - .../mterp/mips/op_invoke_super_range.S | 2 - .../mterp/mips/op_invoke_virtual.S | 2 - .../mterp/mips/op_invoke_virtual_quick.S | 2 - .../mterp/mips/op_invoke_virtual_range.S | 2 - .../mips/op_invoke_virtual_range_quick.S | 2 - runtime/interpreter/mterp/mips/op_iput.S | 2 - .../interpreter/mterp/mips/op_iput_boolean.S | 2 - .../mterp/mips/op_iput_boolean_quick.S | 2 - runtime/interpreter/mterp/mips/op_iput_byte.S | 2 - .../mterp/mips/op_iput_byte_quick.S | 2 - runtime/interpreter/mterp/mips/op_iput_char.S | 2 - .../mterp/mips/op_iput_char_quick.S | 2 - .../interpreter/mterp/mips/op_iput_object.S | 2 - .../mterp/mips/op_iput_object_quick.S | 12 - .../interpreter/mterp/mips/op_iput_quick.S | 15 - .../interpreter/mterp/mips/op_iput_short.S | 2 - .../mterp/mips/op_iput_short_quick.S | 2 - runtime/interpreter/mterp/mips/op_iput_wide.S | 2 - .../mterp/mips/op_iput_wide_quick.S | 16 - .../mterp/mips/op_long_to_double.S | 21 - .../interpreter/mterp/mips/op_long_to_float.S | 21 - .../interpreter/mterp/mips/op_long_to_int.S | 3 - .../interpreter/mterp/mips/op_monitor_enter.S | 14 - .../interpreter/mterp/mips/op_monitor_exit.S | 18 - runtime/interpreter/mterp/mips/op_move.S | 13 - runtime/interpreter/mterp/mips/op_move_16.S | 13 - .../mterp/mips/op_move_exception.S | 10 - .../interpreter/mterp/mips/op_move_from16.S | 13 - .../interpreter/mterp/mips/op_move_object.S | 2 - .../mterp/mips/op_move_object_16.S | 2 - .../mterp/mips/op_move_object_from16.S | 2 - .../interpreter/mterp/mips/op_move_result.S | 13 - .../mterp/mips/op_move_result_object.S | 2 - .../mterp/mips/op_move_result_wide.S | 8 - runtime/interpreter/mterp/mips/op_move_wide.S | 10 - .../interpreter/mterp/mips/op_move_wide_16.S | 10 - .../mterp/mips/op_move_wide_from16.S | 10 - .../interpreter/mterp/mips/op_mul_double.S | 2 - .../mterp/mips/op_mul_double_2addr.S | 2 - runtime/interpreter/mterp/mips/op_mul_float.S | 2 - .../mterp/mips/op_mul_float_2addr.S | 2 - runtime/interpreter/mterp/mips/op_mul_int.S | 2 - .../interpreter/mterp/mips/op_mul_int_2addr.S | 2 - .../interpreter/mterp/mips/op_mul_int_lit16.S | 2 - .../interpreter/mterp/mips/op_mul_int_lit8.S | 2 - runtime/interpreter/mterp/mips/op_mul_long.S | 43 - .../mterp/mips/op_mul_long_2addr.S | 30 - .../interpreter/mterp/mips/op_neg_double.S | 2 - runtime/interpreter/mterp/mips/op_neg_float.S | 2 - runtime/interpreter/mterp/mips/op_neg_int.S | 2 - runtime/interpreter/mterp/mips/op_neg_long.S | 2 - runtime/interpreter/mterp/mips/op_new_array.S | 19 - .../interpreter/mterp/mips/op_new_instance.S | 14 - runtime/interpreter/mterp/mips/op_nop.S | 4 - runtime/interpreter/mterp/mips/op_not_int.S | 2 - runtime/interpreter/mterp/mips/op_not_long.S | 2 - runtime/interpreter/mterp/mips/op_or_int.S | 2 - .../interpreter/mterp/mips/op_or_int_2addr.S | 2 - .../interpreter/mterp/mips/op_or_int_lit16.S | 2 - .../interpreter/mterp/mips/op_or_int_lit8.S | 2 - runtime/interpreter/mterp/mips/op_or_long.S | 2 - .../interpreter/mterp/mips/op_or_long_2addr.S | 2 - .../interpreter/mterp/mips/op_packed_switch.S | 20 - .../interpreter/mterp/mips/op_rem_double.S | 2 - .../mterp/mips/op_rem_double_2addr.S | 2 - runtime/interpreter/mterp/mips/op_rem_float.S | 2 - .../mterp/mips/op_rem_float_2addr.S | 2 - runtime/interpreter/mterp/mips/op_rem_int.S | 6 - .../interpreter/mterp/mips/op_rem_int_2addr.S | 6 - .../interpreter/mterp/mips/op_rem_int_lit16.S | 6 - .../interpreter/mterp/mips/op_rem_int_lit8.S | 6 - runtime/interpreter/mterp/mips/op_rem_long.S | 2 - .../mterp/mips/op_rem_long_2addr.S | 2 - runtime/interpreter/mterp/mips/op_return.S | 19 - .../interpreter/mterp/mips/op_return_object.S | 2 - .../interpreter/mterp/mips/op_return_void.S | 12 - .../mterp/mips/op_return_void_no_barrier.S | 10 - .../interpreter/mterp/mips/op_return_wide.S | 17 - runtime/interpreter/mterp/mips/op_rsub_int.S | 3 - .../interpreter/mterp/mips/op_rsub_int_lit8.S | 2 - runtime/interpreter/mterp/mips/op_sget.S | 2 - .../interpreter/mterp/mips/op_sget_boolean.S | 2 - runtime/interpreter/mterp/mips/op_sget_byte.S | 2 - runtime/interpreter/mterp/mips/op_sget_char.S | 2 - .../interpreter/mterp/mips/op_sget_object.S | 2 - .../interpreter/mterp/mips/op_sget_short.S | 2 - runtime/interpreter/mterp/mips/op_sget_wide.S | 2 - runtime/interpreter/mterp/mips/op_shl_int.S | 2 - .../interpreter/mterp/mips/op_shl_int_2addr.S | 2 - .../interpreter/mterp/mips/op_shl_int_lit8.S | 2 - runtime/interpreter/mterp/mips/op_shl_long.S | 32 - .../mterp/mips/op_shl_long_2addr.S | 28 - runtime/interpreter/mterp/mips/op_shr_int.S | 2 - .../interpreter/mterp/mips/op_shr_int_2addr.S | 2 - .../interpreter/mterp/mips/op_shr_int_lit8.S | 2 - runtime/interpreter/mterp/mips/op_shr_long.S | 32 - .../mterp/mips/op_shr_long_2addr.S | 28 - .../interpreter/mterp/mips/op_sparse_switch.S | 2 - runtime/interpreter/mterp/mips/op_sput.S | 2 - .../interpreter/mterp/mips/op_sput_boolean.S | 2 - runtime/interpreter/mterp/mips/op_sput_byte.S | 2 - runtime/interpreter/mterp/mips/op_sput_char.S | 2 - .../interpreter/mterp/mips/op_sput_object.S | 2 - .../interpreter/mterp/mips/op_sput_short.S | 2 - runtime/interpreter/mterp/mips/op_sput_wide.S | 2 - .../interpreter/mterp/mips/op_sub_double.S | 2 - .../mterp/mips/op_sub_double_2addr.S | 2 - runtime/interpreter/mterp/mips/op_sub_float.S | 2 - .../mterp/mips/op_sub_float_2addr.S | 2 - runtime/interpreter/mterp/mips/op_sub_int.S | 2 - .../interpreter/mterp/mips/op_sub_int_2addr.S | 2 - runtime/interpreter/mterp/mips/op_sub_long.S | 9 - .../mterp/mips/op_sub_long_2addr.S | 5 - runtime/interpreter/mterp/mips/op_throw.S | 12 - runtime/interpreter/mterp/mips/op_unused_3e.S | 2 - runtime/interpreter/mterp/mips/op_unused_3f.S | 2 - runtime/interpreter/mterp/mips/op_unused_40.S | 2 - runtime/interpreter/mterp/mips/op_unused_41.S | 2 - runtime/interpreter/mterp/mips/op_unused_42.S | 2 - runtime/interpreter/mterp/mips/op_unused_43.S | 2 - runtime/interpreter/mterp/mips/op_unused_73.S | 2 - runtime/interpreter/mterp/mips/op_unused_79.S | 2 - runtime/interpreter/mterp/mips/op_unused_7a.S | 2 - runtime/interpreter/mterp/mips/op_unused_f3.S | 2 - runtime/interpreter/mterp/mips/op_unused_f4.S | 2 - runtime/interpreter/mterp/mips/op_unused_f5.S | 2 - runtime/interpreter/mterp/mips/op_unused_f6.S | 2 - runtime/interpreter/mterp/mips/op_unused_f7.S | 2 - runtime/interpreter/mterp/mips/op_unused_f8.S | 2 - runtime/interpreter/mterp/mips/op_unused_f9.S | 2 - runtime/interpreter/mterp/mips/op_unused_fc.S | 2 - runtime/interpreter/mterp/mips/op_unused_fd.S | 2 - runtime/interpreter/mterp/mips/op_ushr_int.S | 2 - .../mterp/mips/op_ushr_int_2addr.S | 2 - .../interpreter/mterp/mips/op_ushr_int_lit8.S | 2 - runtime/interpreter/mterp/mips/op_ushr_long.S | 32 - .../mterp/mips/op_ushr_long_2addr.S | 28 - runtime/interpreter/mterp/mips/op_xor_int.S | 2 - .../interpreter/mterp/mips/op_xor_int_2addr.S | 2 - .../interpreter/mterp/mips/op_xor_int_lit16.S | 2 - .../interpreter/mterp/mips/op_xor_int_lit8.S | 2 - runtime/interpreter/mterp/mips/op_xor_long.S | 2 - .../mterp/mips/op_xor_long_2addr.S | 2 - runtime/interpreter/mterp/mips/other.S | 345 +++++++ runtime/interpreter/mterp/mips/unop.S | 18 - runtime/interpreter/mterp/mips/unopNarrower.S | 16 - runtime/interpreter/mterp/mips/unopWide.S | 18 - runtime/interpreter/mterp/mips/unopWider.S | 16 - runtime/interpreter/mterp/mips/unused.S | 5 - runtime/interpreter/mterp/mips/zcmp.S | 17 - runtime/interpreter/mterp/mips64/alt_stub.S | 15 - runtime/interpreter/mterp/mips64/arithmetic.S | 458 ++++++++ runtime/interpreter/mterp/mips64/array.S | 241 +++++ runtime/interpreter/mterp/mips64/bincmp.S | 20 - runtime/interpreter/mterp/mips64/binop.S | 30 - runtime/interpreter/mterp/mips64/binop2addr.S | 30 - runtime/interpreter/mterp/mips64/binopLit16.S | 28 - runtime/interpreter/mterp/mips64/binopLit8.S | 29 - runtime/interpreter/mterp/mips64/binopWide.S | 30 - .../interpreter/mterp/mips64/binopWide2addr.S | 30 - runtime/interpreter/mterp/mips64/const.S | 17 - .../interpreter/mterp/mips64/control_flow.S | 217 ++++ runtime/interpreter/mterp/mips64/entry.S | 95 -- runtime/interpreter/mterp/mips64/fallback.S | 3 - runtime/interpreter/mterp/mips64/fbinop.S | 18 - .../interpreter/mterp/mips64/fbinop2addr.S | 17 - runtime/interpreter/mterp/mips64/fbinopWide.S | 18 - .../mterp/mips64/fbinopWide2addr.S | 17 - runtime/interpreter/mterp/mips64/fcmp.S | 32 - runtime/interpreter/mterp/mips64/fcmpWide.S | 32 - runtime/interpreter/mterp/mips64/fcvtFooter.S | 19 - runtime/interpreter/mterp/mips64/fcvtHeader.S | 16 - runtime/interpreter/mterp/mips64/field.S | 2 - .../interpreter/mterp/mips64/floating_point.S | 382 +++++++ runtime/interpreter/mterp/mips64/footer.S | 277 ----- runtime/interpreter/mterp/mips64/header.S | 329 ------ .../mterp/mips64/instruction_end.S | 4 - .../mterp/mips64/instruction_end_alt.S | 4 - .../mterp/mips64/instruction_end_sister.S | 4 - .../mterp/mips64/instruction_start.S | 5 - .../mterp/mips64/instruction_start_alt.S | 5 - .../mterp/mips64/instruction_start_sister.S | 6 - runtime/interpreter/mterp/mips64/invoke.S | 90 ++ .../mterp/mips64/invoke_polymorphic.S | 20 - runtime/interpreter/mterp/mips64/main.S | 757 ++++++++++++++ runtime/interpreter/mterp/mips64/object.S | 262 +++++ .../interpreter/mterp/mips64/op_add_double.S | 2 - .../mterp/mips64/op_add_double_2addr.S | 2 - .../interpreter/mterp/mips64/op_add_float.S | 2 - .../mterp/mips64/op_add_float_2addr.S | 2 - runtime/interpreter/mterp/mips64/op_add_int.S | 2 - .../mterp/mips64/op_add_int_2addr.S | 2 - .../mterp/mips64/op_add_int_lit16.S | 2 - .../mterp/mips64/op_add_int_lit8.S | 2 - .../interpreter/mterp/mips64/op_add_long.S | 2 - .../mterp/mips64/op_add_long_2addr.S | 2 - runtime/interpreter/mterp/mips64/op_aget.S | 29 - .../mterp/mips64/op_aget_boolean.S | 2 - .../interpreter/mterp/mips64/op_aget_byte.S | 2 - .../interpreter/mterp/mips64/op_aget_char.S | 2 - .../interpreter/mterp/mips64/op_aget_object.S | 22 - .../interpreter/mterp/mips64/op_aget_short.S | 2 - .../interpreter/mterp/mips64/op_aget_wide.S | 22 - runtime/interpreter/mterp/mips64/op_and_int.S | 2 - .../mterp/mips64/op_and_int_2addr.S | 2 - .../mterp/mips64/op_and_int_lit16.S | 2 - .../mterp/mips64/op_and_int_lit8.S | 2 - .../interpreter/mterp/mips64/op_and_long.S | 2 - .../mterp/mips64/op_and_long_2addr.S | 2 - runtime/interpreter/mterp/mips64/op_aput.S | 29 - .../mterp/mips64/op_aput_boolean.S | 2 - .../interpreter/mterp/mips64/op_aput_byte.S | 2 - .../interpreter/mterp/mips64/op_aput_char.S | 2 - .../interpreter/mterp/mips64/op_aput_object.S | 15 - .../interpreter/mterp/mips64/op_aput_short.S | 2 - .../interpreter/mterp/mips64/op_aput_wide.S | 22 - .../mterp/mips64/op_array_length.S | 13 - .../interpreter/mterp/mips64/op_check_cast.S | 18 - .../interpreter/mterp/mips64/op_cmp_long.S | 14 - .../interpreter/mterp/mips64/op_cmpg_double.S | 2 - .../interpreter/mterp/mips64/op_cmpg_float.S | 2 - .../interpreter/mterp/mips64/op_cmpl_double.S | 2 - .../interpreter/mterp/mips64/op_cmpl_float.S | 2 - runtime/interpreter/mterp/mips64/op_const.S | 10 - .../interpreter/mterp/mips64/op_const_16.S | 8 - runtime/interpreter/mterp/mips64/op_const_4.S | 9 - .../interpreter/mterp/mips64/op_const_class.S | 2 - .../mterp/mips64/op_const_high16.S | 9 - .../mterp/mips64/op_const_method_handle.S | 2 - .../mterp/mips64/op_const_method_type.S | 2 - .../mterp/mips64/op_const_string.S | 2 - .../mterp/mips64/op_const_string_jumbo.S | 16 - .../interpreter/mterp/mips64/op_const_wide.S | 14 - .../mterp/mips64/op_const_wide_16.S | 8 - .../mterp/mips64/op_const_wide_32.S | 10 - .../mterp/mips64/op_const_wide_high16.S | 9 - .../interpreter/mterp/mips64/op_div_double.S | 2 - .../mterp/mips64/op_div_double_2addr.S | 2 - .../interpreter/mterp/mips64/op_div_float.S | 2 - .../mterp/mips64/op_div_float_2addr.S | 2 - runtime/interpreter/mterp/mips64/op_div_int.S | 2 - .../mterp/mips64/op_div_int_2addr.S | 2 - .../mterp/mips64/op_div_int_lit16.S | 2 - .../mterp/mips64/op_div_int_lit8.S | 2 - .../interpreter/mterp/mips64/op_div_long.S | 2 - .../mterp/mips64/op_div_long_2addr.S | 2 - .../mterp/mips64/op_double_to_float.S | 9 - .../mterp/mips64/op_double_to_int.S | 4 - .../mterp/mips64/op_double_to_long.S | 4 - .../mterp/mips64/op_fill_array_data.S | 15 - .../mterp/mips64/op_filled_new_array.S | 18 - .../mterp/mips64/op_filled_new_array_range.S | 2 - .../mterp/mips64/op_float_to_double.S | 9 - .../mterp/mips64/op_float_to_int.S | 4 - .../mterp/mips64/op_float_to_long.S | 4 - runtime/interpreter/mterp/mips64/op_goto.S | 11 - runtime/interpreter/mterp/mips64/op_goto_16.S | 10 - runtime/interpreter/mterp/mips64/op_goto_32.S | 15 - runtime/interpreter/mterp/mips64/op_if_eq.S | 2 - runtime/interpreter/mterp/mips64/op_if_eqz.S | 2 - runtime/interpreter/mterp/mips64/op_if_ge.S | 2 - runtime/interpreter/mterp/mips64/op_if_gez.S | 2 - runtime/interpreter/mterp/mips64/op_if_gt.S | 2 - runtime/interpreter/mterp/mips64/op_if_gtz.S | 2 - runtime/interpreter/mterp/mips64/op_if_le.S | 2 - runtime/interpreter/mterp/mips64/op_if_lez.S | 2 - runtime/interpreter/mterp/mips64/op_if_lt.S | 2 - runtime/interpreter/mterp/mips64/op_if_ltz.S | 2 - runtime/interpreter/mterp/mips64/op_if_ne.S | 2 - runtime/interpreter/mterp/mips64/op_if_nez.S | 2 - runtime/interpreter/mterp/mips64/op_iget.S | 2 - .../mterp/mips64/op_iget_boolean.S | 2 - .../mterp/mips64/op_iget_boolean_quick.S | 2 - .../interpreter/mterp/mips64/op_iget_byte.S | 2 - .../mterp/mips64/op_iget_byte_quick.S | 2 - .../interpreter/mterp/mips64/op_iget_char.S | 2 - .../mterp/mips64/op_iget_char_quick.S | 2 - .../interpreter/mterp/mips64/op_iget_object.S | 2 - .../mterp/mips64/op_iget_object_quick.S | 17 - .../interpreter/mterp/mips64/op_iget_quick.S | 14 - .../interpreter/mterp/mips64/op_iget_short.S | 2 - .../mterp/mips64/op_iget_short_quick.S | 2 - .../interpreter/mterp/mips64/op_iget_wide.S | 2 - .../mterp/mips64/op_iget_wide_quick.S | 15 - .../interpreter/mterp/mips64/op_instance_of.S | 24 - .../interpreter/mterp/mips64/op_int_to_byte.S | 2 - .../interpreter/mterp/mips64/op_int_to_char.S | 2 - .../mterp/mips64/op_int_to_double.S | 9 - .../mterp/mips64/op_int_to_float.S | 9 - .../interpreter/mterp/mips64/op_int_to_long.S | 9 - .../mterp/mips64/op_int_to_short.S | 2 - .../mterp/mips64/op_invoke_custom.S | 2 - .../mterp/mips64/op_invoke_custom_range.S | 2 - .../mterp/mips64/op_invoke_direct.S | 2 - .../mterp/mips64/op_invoke_direct_range.S | 2 - .../mterp/mips64/op_invoke_interface.S | 9 - .../mterp/mips64/op_invoke_interface_range.S | 2 - .../mterp/mips64/op_invoke_polymorphic.S | 2 - .../mips64/op_invoke_polymorphic_range.S | 2 - .../mterp/mips64/op_invoke_static.S | 2 - .../mterp/mips64/op_invoke_static_range.S | 2 - .../mterp/mips64/op_invoke_super.S | 9 - .../mterp/mips64/op_invoke_super_range.S | 2 - .../mterp/mips64/op_invoke_virtual.S | 9 - .../mterp/mips64/op_invoke_virtual_quick.S | 2 - .../mterp/mips64/op_invoke_virtual_range.S | 2 - .../mips64/op_invoke_virtual_range_quick.S | 2 - runtime/interpreter/mterp/mips64/op_iput.S | 2 - .../mterp/mips64/op_iput_boolean.S | 2 - .../mterp/mips64/op_iput_boolean_quick.S | 2 - .../interpreter/mterp/mips64/op_iput_byte.S | 2 - .../mterp/mips64/op_iput_byte_quick.S | 2 - .../interpreter/mterp/mips64/op_iput_char.S | 2 - .../mterp/mips64/op_iput_char_quick.S | 2 - .../interpreter/mterp/mips64/op_iput_object.S | 2 - .../mterp/mips64/op_iput_object_quick.S | 11 - .../interpreter/mterp/mips64/op_iput_quick.S | 14 - .../interpreter/mterp/mips64/op_iput_short.S | 2 - .../mterp/mips64/op_iput_short_quick.S | 2 - .../interpreter/mterp/mips64/op_iput_wide.S | 2 - .../mterp/mips64/op_iput_wide_quick.S | 15 - .../mterp/mips64/op_long_to_double.S | 9 - .../mterp/mips64/op_long_to_float.S | 9 - .../interpreter/mterp/mips64/op_long_to_int.S | 3 - .../mterp/mips64/op_monitor_enter.S | 15 - .../mterp/mips64/op_monitor_exit.S | 19 - runtime/interpreter/mterp/mips64/op_move.S | 14 - runtime/interpreter/mterp/mips64/op_move_16.S | 14 - .../mterp/mips64/op_move_exception.S | 9 - .../interpreter/mterp/mips64/op_move_from16.S | 14 - .../interpreter/mterp/mips64/op_move_object.S | 2 - .../mterp/mips64/op_move_object_16.S | 2 - .../mterp/mips64/op_move_object_from16.S | 2 - .../interpreter/mterp/mips64/op_move_result.S | 14 - .../mterp/mips64/op_move_result_object.S | 2 - .../mterp/mips64/op_move_result_wide.S | 10 - .../interpreter/mterp/mips64/op_move_wide.S | 10 - .../mterp/mips64/op_move_wide_16.S | 10 - .../mterp/mips64/op_move_wide_from16.S | 10 - .../interpreter/mterp/mips64/op_mul_double.S | 2 - .../mterp/mips64/op_mul_double_2addr.S | 2 - .../interpreter/mterp/mips64/op_mul_float.S | 2 - .../mterp/mips64/op_mul_float_2addr.S | 2 - runtime/interpreter/mterp/mips64/op_mul_int.S | 2 - .../mterp/mips64/op_mul_int_2addr.S | 2 - .../mterp/mips64/op_mul_int_lit16.S | 2 - .../mterp/mips64/op_mul_int_lit8.S | 2 - .../interpreter/mterp/mips64/op_mul_long.S | 2 - .../mterp/mips64/op_mul_long_2addr.S | 2 - .../interpreter/mterp/mips64/op_neg_double.S | 4 - .../interpreter/mterp/mips64/op_neg_float.S | 4 - runtime/interpreter/mterp/mips64/op_neg_int.S | 2 - .../interpreter/mterp/mips64/op_neg_long.S | 2 - .../interpreter/mterp/mips64/op_new_array.S | 20 - .../mterp/mips64/op_new_instance.S | 15 - runtime/interpreter/mterp/mips64/op_nop.S | 4 - runtime/interpreter/mterp/mips64/op_not_int.S | 2 - .../interpreter/mterp/mips64/op_not_long.S | 2 - runtime/interpreter/mterp/mips64/op_or_int.S | 2 - .../mterp/mips64/op_or_int_2addr.S | 2 - .../mterp/mips64/op_or_int_lit16.S | 2 - .../interpreter/mterp/mips64/op_or_int_lit8.S | 2 - runtime/interpreter/mterp/mips64/op_or_long.S | 2 - .../mterp/mips64/op_or_long_2addr.S | 2 - .../mterp/mips64/op_packed_switch.S | 21 - .../interpreter/mterp/mips64/op_rem_double.S | 13 - .../mterp/mips64/op_rem_double_2addr.S | 13 - .../interpreter/mterp/mips64/op_rem_float.S | 13 - .../mterp/mips64/op_rem_float_2addr.S | 13 - runtime/interpreter/mterp/mips64/op_rem_int.S | 2 - .../mterp/mips64/op_rem_int_2addr.S | 2 - .../mterp/mips64/op_rem_int_lit16.S | 2 - .../mterp/mips64/op_rem_int_lit8.S | 2 - .../interpreter/mterp/mips64/op_rem_long.S | 2 - .../mterp/mips64/op_rem_long_2addr.S | 2 - runtime/interpreter/mterp/mips64/op_return.S | 19 - .../mterp/mips64/op_return_object.S | 2 - .../interpreter/mterp/mips64/op_return_void.S | 12 - .../mterp/mips64/op_return_void_no_barrier.S | 10 - .../interpreter/mterp/mips64/op_return_wide.S | 18 - .../interpreter/mterp/mips64/op_rsub_int.S | 2 - .../mterp/mips64/op_rsub_int_lit8.S | 2 - runtime/interpreter/mterp/mips64/op_sget.S | 2 - .../mterp/mips64/op_sget_boolean.S | 2 - .../interpreter/mterp/mips64/op_sget_byte.S | 2 - .../interpreter/mterp/mips64/op_sget_char.S | 2 - .../interpreter/mterp/mips64/op_sget_object.S | 2 - .../interpreter/mterp/mips64/op_sget_short.S | 2 - .../interpreter/mterp/mips64/op_sget_wide.S | 2 - runtime/interpreter/mterp/mips64/op_shl_int.S | 2 - .../mterp/mips64/op_shl_int_2addr.S | 2 - .../mterp/mips64/op_shl_int_lit8.S | 2 - .../interpreter/mterp/mips64/op_shl_long.S | 2 - .../mterp/mips64/op_shl_long_2addr.S | 2 - runtime/interpreter/mterp/mips64/op_shr_int.S | 2 - .../mterp/mips64/op_shr_int_2addr.S | 2 - .../mterp/mips64/op_shr_int_lit8.S | 2 - .../interpreter/mterp/mips64/op_shr_long.S | 2 - .../mterp/mips64/op_shr_long_2addr.S | 2 - .../mterp/mips64/op_sparse_switch.S | 2 - runtime/interpreter/mterp/mips64/op_sput.S | 2 - .../mterp/mips64/op_sput_boolean.S | 2 - .../interpreter/mterp/mips64/op_sput_byte.S | 2 - .../interpreter/mterp/mips64/op_sput_char.S | 2 - .../interpreter/mterp/mips64/op_sput_object.S | 2 - .../interpreter/mterp/mips64/op_sput_short.S | 2 - .../interpreter/mterp/mips64/op_sput_wide.S | 2 - .../interpreter/mterp/mips64/op_sub_double.S | 2 - .../mterp/mips64/op_sub_double_2addr.S | 2 - .../interpreter/mterp/mips64/op_sub_float.S | 2 - .../mterp/mips64/op_sub_float_2addr.S | 2 - runtime/interpreter/mterp/mips64/op_sub_int.S | 2 - .../mterp/mips64/op_sub_int_2addr.S | 2 - .../interpreter/mterp/mips64/op_sub_long.S | 2 - .../mterp/mips64/op_sub_long_2addr.S | 2 - runtime/interpreter/mterp/mips64/op_throw.S | 11 - .../interpreter/mterp/mips64/op_unused_3e.S | 2 - .../interpreter/mterp/mips64/op_unused_3f.S | 2 - .../interpreter/mterp/mips64/op_unused_40.S | 2 - .../interpreter/mterp/mips64/op_unused_41.S | 2 - .../interpreter/mterp/mips64/op_unused_42.S | 2 - .../interpreter/mterp/mips64/op_unused_43.S | 2 - .../interpreter/mterp/mips64/op_unused_79.S | 2 - .../interpreter/mterp/mips64/op_unused_7a.S | 2 - .../interpreter/mterp/mips64/op_unused_f3.S | 2 - .../interpreter/mterp/mips64/op_unused_f4.S | 2 - .../interpreter/mterp/mips64/op_unused_f5.S | 2 - .../interpreter/mterp/mips64/op_unused_f6.S | 2 - .../interpreter/mterp/mips64/op_unused_f7.S | 2 - .../interpreter/mterp/mips64/op_unused_f8.S | 2 - .../interpreter/mterp/mips64/op_unused_f9.S | 2 - .../interpreter/mterp/mips64/op_unused_fc.S | 2 - .../interpreter/mterp/mips64/op_unused_fd.S | 2 - .../interpreter/mterp/mips64/op_ushr_int.S | 2 - .../mterp/mips64/op_ushr_int_2addr.S | 2 - .../mterp/mips64/op_ushr_int_lit8.S | 2 - .../interpreter/mterp/mips64/op_ushr_long.S | 2 - .../mterp/mips64/op_ushr_long_2addr.S | 2 - runtime/interpreter/mterp/mips64/op_xor_int.S | 2 - .../mterp/mips64/op_xor_int_2addr.S | 2 - .../mterp/mips64/op_xor_int_lit16.S | 2 - .../mterp/mips64/op_xor_int_lit8.S | 2 - .../interpreter/mterp/mips64/op_xor_long.S | 2 - .../mterp/mips64/op_xor_long_2addr.S | 2 - runtime/interpreter/mterp/mips64/other.S | 355 +++++++ runtime/interpreter/mterp/mips64/unop.S | 18 - runtime/interpreter/mterp/mips64/unopWide.S | 17 - runtime/interpreter/mterp/mips64/unused.S | 5 - runtime/interpreter/mterp/mips64/zcmp.S | 18 - runtime/interpreter/mterp/out/mterp_arm.S | 5 + runtime/interpreter/mterp/out/mterp_arm64.S | 5 + runtime/interpreter/mterp/out/mterp_mips.S | 21 + runtime/interpreter/mterp/out/mterp_mips64.S | 20 + runtime/interpreter/mterp/out/mterp_x86.S | 8 + runtime/interpreter/mterp/out/mterp_x86_64.S | 8 + runtime/interpreter/mterp/x86/alt_stub.S | 20 - runtime/interpreter/mterp/x86/arithmetic.S | 936 +++++++++++++++++ runtime/interpreter/mterp/x86/array.S | 215 ++++ runtime/interpreter/mterp/x86/bincmp.S | 22 - runtime/interpreter/mterp/x86/bindiv.S | 48 - runtime/interpreter/mterp/x86/bindiv2addr.S | 29 - runtime/interpreter/mterp/x86/bindivLit16.S | 29 - runtime/interpreter/mterp/x86/bindivLit8.S | 26 - runtime/interpreter/mterp/x86/binop.S | 17 - runtime/interpreter/mterp/x86/binop1.S | 13 - runtime/interpreter/mterp/x86/binop2addr.S | 19 - runtime/interpreter/mterp/x86/binopLit16.S | 19 - runtime/interpreter/mterp/x86/binopLit8.S | 18 - runtime/interpreter/mterp/x86/binopWide.S | 16 - .../interpreter/mterp/x86/binopWide2addr.S | 14 - runtime/interpreter/mterp/x86/const.S | 19 - runtime/interpreter/mterp/x86/control_flow.S | 219 ++++ runtime/interpreter/mterp/x86/cvtfp_int.S | 61 -- runtime/interpreter/mterp/x86/entry.S | 84 -- runtime/interpreter/mterp/x86/fallback.S | 4 - runtime/interpreter/mterp/x86/field.S | 17 - .../interpreter/mterp/x86/floating_point.S | 236 +++++ runtime/interpreter/mterp/x86/footer.S | 326 ------ runtime/interpreter/mterp/x86/fpcmp.S | 35 - runtime/interpreter/mterp/x86/fpcvt.S | 17 - runtime/interpreter/mterp/x86/header.S | 317 ------ .../interpreter/mterp/x86/instruction_end.S | 6 - .../mterp/x86/instruction_end_alt.S | 6 - .../mterp/x86/instruction_end_sister.S | 6 - .../interpreter/mterp/x86/instruction_start.S | 7 - .../mterp/x86/instruction_start_alt.S | 7 - .../mterp/x86/instruction_start_sister.S | 8 - runtime/interpreter/mterp/x86/invoke.S | 96 ++ .../mterp/x86/invoke_polymorphic.S | 25 - runtime/interpreter/mterp/x86/main.S | 801 ++++++++++++++ runtime/interpreter/mterp/x86/object.S | 278 +++++ runtime/interpreter/mterp/x86/op_add_double.S | 2 - .../mterp/x86/op_add_double_2addr.S | 2 - runtime/interpreter/mterp/x86/op_add_float.S | 2 - .../mterp/x86/op_add_float_2addr.S | 2 - runtime/interpreter/mterp/x86/op_add_int.S | 2 - .../interpreter/mterp/x86/op_add_int_2addr.S | 2 - .../interpreter/mterp/x86/op_add_int_lit16.S | 2 - .../interpreter/mterp/x86/op_add_int_lit8.S | 2 - runtime/interpreter/mterp/x86/op_add_long.S | 2 - .../interpreter/mterp/x86/op_add_long_2addr.S | 2 - runtime/interpreter/mterp/x86/op_aget.S | 19 - .../interpreter/mterp/x86/op_aget_boolean.S | 2 - runtime/interpreter/mterp/x86/op_aget_byte.S | 2 - runtime/interpreter/mterp/x86/op_aget_char.S | 2 - .../interpreter/mterp/x86/op_aget_object.S | 21 - runtime/interpreter/mterp/x86/op_aget_short.S | 2 - runtime/interpreter/mterp/x86/op_aget_wide.S | 17 - runtime/interpreter/mterp/x86/op_and_int.S | 2 - .../interpreter/mterp/x86/op_and_int_2addr.S | 2 - .../interpreter/mterp/x86/op_and_int_lit16.S | 2 - .../interpreter/mterp/x86/op_and_int_lit8.S | 2 - runtime/interpreter/mterp/x86/op_and_long.S | 2 - .../interpreter/mterp/x86/op_and_long_2addr.S | 2 - runtime/interpreter/mterp/x86/op_aput.S | 20 - .../interpreter/mterp/x86/op_aput_boolean.S | 2 - runtime/interpreter/mterp/x86/op_aput_byte.S | 2 - runtime/interpreter/mterp/x86/op_aput_char.S | 2 - .../interpreter/mterp/x86/op_aput_object.S | 16 - runtime/interpreter/mterp/x86/op_aput_short.S | 2 - runtime/interpreter/mterp/x86/op_aput_wide.S | 18 - .../interpreter/mterp/x86/op_array_length.S | 13 - runtime/interpreter/mterp/x86/op_check_cast.S | 19 - runtime/interpreter/mterp/x86/op_cmp_long.S | 28 - .../interpreter/mterp/x86/op_cmpg_double.S | 2 - runtime/interpreter/mterp/x86/op_cmpg_float.S | 2 - .../interpreter/mterp/x86/op_cmpl_double.S | 2 - runtime/interpreter/mterp/x86/op_cmpl_float.S | 2 - runtime/interpreter/mterp/x86/op_const.S | 5 - runtime/interpreter/mterp/x86/op_const_16.S | 5 - runtime/interpreter/mterp/x86/op_const_4.S | 8 - .../interpreter/mterp/x86/op_const_class.S | 2 - .../interpreter/mterp/x86/op_const_high16.S | 6 - .../mterp/x86/op_const_method_handle.S | 2 - .../mterp/x86/op_const_method_type.S | 2 - .../interpreter/mterp/x86/op_const_string.S | 2 - .../mterp/x86/op_const_string_jumbo.S | 15 - runtime/interpreter/mterp/x86/op_const_wide.S | 8 - .../interpreter/mterp/x86/op_const_wide_16.S | 9 - .../interpreter/mterp/x86/op_const_wide_32.S | 9 - .../mterp/x86/op_const_wide_high16.S | 8 - runtime/interpreter/mterp/x86/op_div_double.S | 2 - .../mterp/x86/op_div_double_2addr.S | 2 - runtime/interpreter/mterp/x86/op_div_float.S | 2 - .../mterp/x86/op_div_float_2addr.S | 2 - runtime/interpreter/mterp/x86/op_div_int.S | 2 - .../interpreter/mterp/x86/op_div_int_2addr.S | 2 - .../interpreter/mterp/x86/op_div_int_lit16.S | 2 - .../interpreter/mterp/x86/op_div_int_lit8.S | 2 - runtime/interpreter/mterp/x86/op_div_long.S | 23 - .../interpreter/mterp/x86/op_div_long_2addr.S | 25 - .../mterp/x86/op_double_to_float.S | 2 - .../interpreter/mterp/x86/op_double_to_int.S | 2 - .../interpreter/mterp/x86/op_double_to_long.S | 2 - .../mterp/x86/op_fill_array_data.S | 13 - .../mterp/x86/op_filled_new_array.S | 20 - .../mterp/x86/op_filled_new_array_range.S | 2 - .../mterp/x86/op_float_to_double.S | 2 - .../interpreter/mterp/x86/op_float_to_int.S | 2 - .../interpreter/mterp/x86/op_float_to_long.S | 2 - runtime/interpreter/mterp/x86/op_goto.S | 11 - runtime/interpreter/mterp/x86/op_goto_16.S | 11 - runtime/interpreter/mterp/x86/op_goto_32.S | 16 - runtime/interpreter/mterp/x86/op_if_eq.S | 2 - runtime/interpreter/mterp/x86/op_if_eqz.S | 2 - runtime/interpreter/mterp/x86/op_if_ge.S | 2 - runtime/interpreter/mterp/x86/op_if_gez.S | 2 - runtime/interpreter/mterp/x86/op_if_gt.S | 2 - runtime/interpreter/mterp/x86/op_if_gtz.S | 2 - runtime/interpreter/mterp/x86/op_if_le.S | 2 - runtime/interpreter/mterp/x86/op_if_lez.S | 2 - runtime/interpreter/mterp/x86/op_if_lt.S | 2 - runtime/interpreter/mterp/x86/op_if_ltz.S | 2 - runtime/interpreter/mterp/x86/op_if_ne.S | 2 - runtime/interpreter/mterp/x86/op_if_nez.S | 2 - runtime/interpreter/mterp/x86/op_iget.S | 2 - .../interpreter/mterp/x86/op_iget_boolean.S | 2 - .../mterp/x86/op_iget_boolean_quick.S | 2 - runtime/interpreter/mterp/x86/op_iget_byte.S | 2 - .../mterp/x86/op_iget_byte_quick.S | 2 - runtime/interpreter/mterp/x86/op_iget_char.S | 2 - .../mterp/x86/op_iget_char_quick.S | 2 - .../interpreter/mterp/x86/op_iget_object.S | 2 - .../mterp/x86/op_iget_object_quick.S | 18 - runtime/interpreter/mterp/x86/op_iget_quick.S | 13 - runtime/interpreter/mterp/x86/op_iget_short.S | 2 - .../mterp/x86/op_iget_short_quick.S | 2 - runtime/interpreter/mterp/x86/op_iget_wide.S | 2 - .../mterp/x86/op_iget_wide_quick.S | 12 - .../interpreter/mterp/x86/op_instance_of.S | 27 - .../interpreter/mterp/x86/op_int_to_byte.S | 2 - .../interpreter/mterp/x86/op_int_to_char.S | 2 - .../interpreter/mterp/x86/op_int_to_double.S | 2 - .../interpreter/mterp/x86/op_int_to_float.S | 2 - .../interpreter/mterp/x86/op_int_to_long.S | 13 - .../interpreter/mterp/x86/op_int_to_short.S | 2 - .../interpreter/mterp/x86/op_invoke_custom.S | 2 - .../mterp/x86/op_invoke_custom_range.S | 2 - .../interpreter/mterp/x86/op_invoke_direct.S | 2 - .../mterp/x86/op_invoke_direct_range.S | 2 - .../mterp/x86/op_invoke_interface.S | 9 - .../mterp/x86/op_invoke_interface_range.S | 2 - .../mterp/x86/op_invoke_polymorphic.S | 2 - .../mterp/x86/op_invoke_polymorphic_range.S | 2 - .../interpreter/mterp/x86/op_invoke_static.S | 3 - .../mterp/x86/op_invoke_static_range.S | 2 - .../interpreter/mterp/x86/op_invoke_super.S | 9 - .../mterp/x86/op_invoke_super_range.S | 2 - .../interpreter/mterp/x86/op_invoke_virtual.S | 9 - .../mterp/x86/op_invoke_virtual_quick.S | 2 - .../mterp/x86/op_invoke_virtual_range.S | 2 - .../mterp/x86/op_invoke_virtual_range_quick.S | 2 - runtime/interpreter/mterp/x86/op_iput.S | 2 - .../interpreter/mterp/x86/op_iput_boolean.S | 2 - .../mterp/x86/op_iput_boolean_quick.S | 2 - runtime/interpreter/mterp/x86/op_iput_byte.S | 2 - .../mterp/x86/op_iput_byte_quick.S | 2 - runtime/interpreter/mterp/x86/op_iput_char.S | 2 - .../mterp/x86/op_iput_char_quick.S | 2 - .../interpreter/mterp/x86/op_iput_object.S | 2 - .../mterp/x86/op_iput_object_quick.S | 12 - runtime/interpreter/mterp/x86/op_iput_quick.S | 13 - runtime/interpreter/mterp/x86/op_iput_short.S | 2 - .../mterp/x86/op_iput_short_quick.S | 2 - runtime/interpreter/mterp/x86/op_iput_wide.S | 2 - .../mterp/x86/op_iput_wide_quick.S | 13 - .../interpreter/mterp/x86/op_long_to_double.S | 2 - .../interpreter/mterp/x86/op_long_to_float.S | 2 - .../interpreter/mterp/x86/op_long_to_int.S | 3 - .../interpreter/mterp/x86/op_monitor_enter.S | 15 - .../interpreter/mterp/x86/op_monitor_exit.S | 19 - runtime/interpreter/mterp/x86/op_move.S | 13 - runtime/interpreter/mterp/x86/op_move_16.S | 12 - .../interpreter/mterp/x86/op_move_exception.S | 7 - .../interpreter/mterp/x86/op_move_from16.S | 12 - .../interpreter/mterp/x86/op_move_object.S | 2 - .../interpreter/mterp/x86/op_move_object_16.S | 2 - .../mterp/x86/op_move_object_from16.S | 2 - .../interpreter/mterp/x86/op_move_result.S | 11 - .../mterp/x86/op_move_result_object.S | 2 - .../mterp/x86/op_move_result_wide.S | 8 - runtime/interpreter/mterp/x86/op_move_wide.S | 9 - .../interpreter/mterp/x86/op_move_wide_16.S | 8 - .../mterp/x86/op_move_wide_from16.S | 8 - runtime/interpreter/mterp/x86/op_mul_double.S | 2 - .../mterp/x86/op_mul_double_2addr.S | 2 - runtime/interpreter/mterp/x86/op_mul_float.S | 2 - .../mterp/x86/op_mul_float_2addr.S | 2 - runtime/interpreter/mterp/x86/op_mul_int.S | 13 - .../interpreter/mterp/x86/op_mul_int_2addr.S | 11 - .../interpreter/mterp/x86/op_mul_int_lit16.S | 13 - .../interpreter/mterp/x86/op_mul_int_lit8.S | 10 - runtime/interpreter/mterp/x86/op_mul_long.S | 34 - .../interpreter/mterp/x86/op_mul_long_2addr.S | 36 - runtime/interpreter/mterp/x86/op_neg_double.S | 2 - runtime/interpreter/mterp/x86/op_neg_float.S | 2 - runtime/interpreter/mterp/x86/op_neg_int.S | 2 - runtime/interpreter/mterp/x86/op_neg_long.S | 14 - runtime/interpreter/mterp/x86/op_new_array.S | 22 - .../interpreter/mterp/x86/op_new_instance.S | 17 - runtime/interpreter/mterp/x86/op_nop.S | 2 - runtime/interpreter/mterp/x86/op_not_int.S | 2 - runtime/interpreter/mterp/x86/op_not_long.S | 12 - runtime/interpreter/mterp/x86/op_or_int.S | 2 - .../interpreter/mterp/x86/op_or_int_2addr.S | 2 - .../interpreter/mterp/x86/op_or_int_lit16.S | 2 - .../interpreter/mterp/x86/op_or_int_lit8.S | 2 - runtime/interpreter/mterp/x86/op_or_long.S | 2 - .../interpreter/mterp/x86/op_or_long_2addr.S | 2 - .../interpreter/mterp/x86/op_packed_switch.S | 21 - runtime/interpreter/mterp/x86/op_rem_double.S | 15 - .../mterp/x86/op_rem_double_2addr.S | 16 - runtime/interpreter/mterp/x86/op_rem_float.S | 15 - .../mterp/x86/op_rem_float_2addr.S | 16 - runtime/interpreter/mterp/x86/op_rem_int.S | 2 - .../interpreter/mterp/x86/op_rem_int_2addr.S | 2 - .../interpreter/mterp/x86/op_rem_int_lit16.S | 2 - .../interpreter/mterp/x86/op_rem_int_lit8.S | 2 - runtime/interpreter/mterp/x86/op_rem_long.S | 2 - .../interpreter/mterp/x86/op_rem_long_2addr.S | 2 - runtime/interpreter/mterp/x86/op_return.S | 18 - .../interpreter/mterp/x86/op_return_object.S | 2 - .../interpreter/mterp/x86/op_return_void.S | 12 - .../mterp/x86/op_return_void_no_barrier.S | 10 - .../interpreter/mterp/x86/op_return_wide.S | 16 - runtime/interpreter/mterp/x86/op_rsub_int.S | 3 - .../interpreter/mterp/x86/op_rsub_int_lit8.S | 2 - runtime/interpreter/mterp/x86/op_sget.S | 2 - .../interpreter/mterp/x86/op_sget_boolean.S | 2 - runtime/interpreter/mterp/x86/op_sget_byte.S | 2 - runtime/interpreter/mterp/x86/op_sget_char.S | 2 - .../interpreter/mterp/x86/op_sget_object.S | 2 - runtime/interpreter/mterp/x86/op_sget_short.S | 2 - runtime/interpreter/mterp/x86/op_sget_wide.S | 2 - runtime/interpreter/mterp/x86/op_shl_int.S | 2 - .../interpreter/mterp/x86/op_shl_int_2addr.S | 2 - .../interpreter/mterp/x86/op_shl_int_lit8.S | 2 - runtime/interpreter/mterp/x86/op_shl_long.S | 30 - .../interpreter/mterp/x86/op_shl_long_2addr.S | 27 - runtime/interpreter/mterp/x86/op_shr_int.S | 2 - .../interpreter/mterp/x86/op_shr_int_2addr.S | 2 - .../interpreter/mterp/x86/op_shr_int_lit8.S | 2 - runtime/interpreter/mterp/x86/op_shr_long.S | 30 - .../interpreter/mterp/x86/op_shr_long_2addr.S | 27 - .../interpreter/mterp/x86/op_sparse_switch.S | 2 - runtime/interpreter/mterp/x86/op_sput.S | 2 - .../interpreter/mterp/x86/op_sput_boolean.S | 2 - runtime/interpreter/mterp/x86/op_sput_byte.S | 2 - runtime/interpreter/mterp/x86/op_sput_char.S | 2 - .../interpreter/mterp/x86/op_sput_object.S | 2 - runtime/interpreter/mterp/x86/op_sput_short.S | 2 - runtime/interpreter/mterp/x86/op_sput_wide.S | 2 - runtime/interpreter/mterp/x86/op_sub_double.S | 2 - .../mterp/x86/op_sub_double_2addr.S | 2 - runtime/interpreter/mterp/x86/op_sub_float.S | 2 - .../mterp/x86/op_sub_float_2addr.S | 2 - runtime/interpreter/mterp/x86/op_sub_int.S | 2 - .../interpreter/mterp/x86/op_sub_int_2addr.S | 2 - runtime/interpreter/mterp/x86/op_sub_long.S | 2 - .../interpreter/mterp/x86/op_sub_long_2addr.S | 2 - runtime/interpreter/mterp/x86/op_throw.S | 12 - runtime/interpreter/mterp/x86/op_unused_3e.S | 2 - runtime/interpreter/mterp/x86/op_unused_3f.S | 2 - runtime/interpreter/mterp/x86/op_unused_40.S | 2 - runtime/interpreter/mterp/x86/op_unused_41.S | 2 - runtime/interpreter/mterp/x86/op_unused_42.S | 2 - runtime/interpreter/mterp/x86/op_unused_43.S | 2 - runtime/interpreter/mterp/x86/op_unused_79.S | 2 - runtime/interpreter/mterp/x86/op_unused_7a.S | 2 - runtime/interpreter/mterp/x86/op_unused_f3.S | 2 - runtime/interpreter/mterp/x86/op_unused_f4.S | 2 - runtime/interpreter/mterp/x86/op_unused_f5.S | 2 - runtime/interpreter/mterp/x86/op_unused_f6.S | 2 - runtime/interpreter/mterp/x86/op_unused_f7.S | 2 - runtime/interpreter/mterp/x86/op_unused_f8.S | 2 - runtime/interpreter/mterp/x86/op_unused_f9.S | 2 - runtime/interpreter/mterp/x86/op_unused_fc.S | 2 - runtime/interpreter/mterp/x86/op_unused_fd.S | 2 - runtime/interpreter/mterp/x86/op_ushr_int.S | 2 - .../interpreter/mterp/x86/op_ushr_int_2addr.S | 2 - .../interpreter/mterp/x86/op_ushr_int_lit8.S | 2 - runtime/interpreter/mterp/x86/op_ushr_long.S | 30 - .../mterp/x86/op_ushr_long_2addr.S | 27 - runtime/interpreter/mterp/x86/op_xor_int.S | 2 - .../interpreter/mterp/x86/op_xor_int_2addr.S | 2 - .../interpreter/mterp/x86/op_xor_int_lit16.S | 2 - .../interpreter/mterp/x86/op_xor_int_lit8.S | 2 - runtime/interpreter/mterp/x86/op_xor_long.S | 2 - .../interpreter/mterp/x86/op_xor_long_2addr.S | 2 - runtime/interpreter/mterp/x86/other.S | 318 ++++++ runtime/interpreter/mterp/x86/shop2addr.S | 13 - runtime/interpreter/mterp/x86/sseBinop.S | 9 - runtime/interpreter/mterp/x86/sseBinop2Addr.S | 10 - runtime/interpreter/mterp/x86/unop.S | 13 - runtime/interpreter/mterp/x86/unused.S | 5 - runtime/interpreter/mterp/x86/zcmp.S | 18 - runtime/interpreter/mterp/x86_64/alt_stub.S | 18 - runtime/interpreter/mterp/x86_64/arithmetic.S | 575 +++++++++++ runtime/interpreter/mterp/x86_64/array.S | 178 ++++ runtime/interpreter/mterp/x86_64/bincmp.S | 22 - runtime/interpreter/mterp/x86_64/bindiv.S | 34 - .../interpreter/mterp/x86_64/bindiv2addr.S | 35 - .../interpreter/mterp/x86_64/bindivLit16.S | 27 - runtime/interpreter/mterp/x86_64/bindivLit8.S | 25 - runtime/interpreter/mterp/x86_64/binop.S | 17 - runtime/interpreter/mterp/x86_64/binop1.S | 19 - runtime/interpreter/mterp/x86_64/binop2addr.S | 19 - runtime/interpreter/mterp/x86_64/binopLit16.S | 19 - runtime/interpreter/mterp/x86_64/binopLit8.S | 18 - runtime/interpreter/mterp/x86_64/binopWide.S | 11 - .../interpreter/mterp/x86_64/binopWide2addr.S | 12 - runtime/interpreter/mterp/x86_64/const.S | 15 - .../interpreter/mterp/x86_64/control_flow.S | 206 ++++ runtime/interpreter/mterp/x86_64/cvtfp_int.S | 27 - runtime/interpreter/mterp/x86_64/entry.S | 80 -- runtime/interpreter/mterp/x86_64/fallback.S | 4 - runtime/interpreter/mterp/x86_64/field.S | 14 - .../interpreter/mterp/x86_64/floating_point.S | 236 +++++ runtime/interpreter/mterp/x86_64/footer.S | 298 ------ runtime/interpreter/mterp/x86_64/fpcmp.S | 35 - runtime/interpreter/mterp/x86_64/fpcvt.S | 17 - runtime/interpreter/mterp/x86_64/header.S | 303 ------ .../mterp/x86_64/instruction_end.S | 6 - .../mterp/x86_64/instruction_end_alt.S | 6 - .../mterp/x86_64/instruction_end_sister.S | 6 - .../mterp/x86_64/instruction_start.S | 7 - .../mterp/x86_64/instruction_start_alt.S | 7 - .../mterp/x86_64/instruction_start_sister.S | 8 - runtime/interpreter/mterp/x86_64/invoke.S | 93 ++ .../mterp/x86_64/invoke_polymorphic.S | 22 - runtime/interpreter/mterp/x86_64/main.S | 753 ++++++++++++++ runtime/interpreter/mterp/x86_64/object.S | 254 +++++ .../interpreter/mterp/x86_64/op_add_double.S | 2 - .../mterp/x86_64/op_add_double_2addr.S | 2 - .../interpreter/mterp/x86_64/op_add_float.S | 2 - .../mterp/x86_64/op_add_float_2addr.S | 2 - runtime/interpreter/mterp/x86_64/op_add_int.S | 2 - .../mterp/x86_64/op_add_int_2addr.S | 2 - .../mterp/x86_64/op_add_int_lit16.S | 2 - .../mterp/x86_64/op_add_int_lit8.S | 2 - .../interpreter/mterp/x86_64/op_add_long.S | 2 - .../mterp/x86_64/op_add_long_2addr.S | 2 - runtime/interpreter/mterp/x86_64/op_aget.S | 24 - .../mterp/x86_64/op_aget_boolean.S | 2 - .../interpreter/mterp/x86_64/op_aget_byte.S | 2 - .../interpreter/mterp/x86_64/op_aget_char.S | 2 - .../interpreter/mterp/x86_64/op_aget_object.S | 18 - .../interpreter/mterp/x86_64/op_aget_short.S | 2 - .../interpreter/mterp/x86_64/op_aget_wide.S | 2 - runtime/interpreter/mterp/x86_64/op_and_int.S | 2 - .../mterp/x86_64/op_and_int_2addr.S | 2 - .../mterp/x86_64/op_and_int_lit16.S | 2 - .../mterp/x86_64/op_and_int_lit8.S | 2 - .../interpreter/mterp/x86_64/op_and_long.S | 2 - .../mterp/x86_64/op_and_long_2addr.S | 2 - runtime/interpreter/mterp/x86_64/op_aput.S | 23 - .../mterp/x86_64/op_aput_boolean.S | 2 - .../interpreter/mterp/x86_64/op_aput_byte.S | 2 - .../interpreter/mterp/x86_64/op_aput_char.S | 2 - .../interpreter/mterp/x86_64/op_aput_object.S | 14 - .../interpreter/mterp/x86_64/op_aput_short.S | 2 - .../interpreter/mterp/x86_64/op_aput_wide.S | 2 - .../mterp/x86_64/op_array_length.S | 13 - .../interpreter/mterp/x86_64/op_check_cast.S | 14 - .../interpreter/mterp/x86_64/op_cmp_long.S | 18 - .../interpreter/mterp/x86_64/op_cmpg_double.S | 2 - .../interpreter/mterp/x86_64/op_cmpg_float.S | 2 - .../interpreter/mterp/x86_64/op_cmpl_double.S | 2 - .../interpreter/mterp/x86_64/op_cmpl_float.S | 2 - runtime/interpreter/mterp/x86_64/op_const.S | 5 - .../interpreter/mterp/x86_64/op_const_16.S | 5 - runtime/interpreter/mterp/x86_64/op_const_4.S | 8 - .../interpreter/mterp/x86_64/op_const_class.S | 2 - .../mterp/x86_64/op_const_high16.S | 6 - .../mterp/x86_64/op_const_method_handle.S | 2 - .../mterp/x86_64/op_const_method_type.S | 2 - .../mterp/x86_64/op_const_string.S | 2 - .../mterp/x86_64/op_const_string_jumbo.S | 11 - .../interpreter/mterp/x86_64/op_const_wide.S | 5 - .../mterp/x86_64/op_const_wide_16.S | 5 - .../mterp/x86_64/op_const_wide_32.S | 5 - .../mterp/x86_64/op_const_wide_high16.S | 6 - .../interpreter/mterp/x86_64/op_div_double.S | 2 - .../mterp/x86_64/op_div_double_2addr.S | 2 - .../interpreter/mterp/x86_64/op_div_float.S | 2 - .../mterp/x86_64/op_div_float_2addr.S | 2 - runtime/interpreter/mterp/x86_64/op_div_int.S | 2 - .../mterp/x86_64/op_div_int_2addr.S | 2 - .../mterp/x86_64/op_div_int_lit16.S | 2 - .../mterp/x86_64/op_div_int_lit8.S | 2 - .../interpreter/mterp/x86_64/op_div_long.S | 2 - .../mterp/x86_64/op_div_long_2addr.S | 2 - .../mterp/x86_64/op_double_to_float.S | 2 - .../mterp/x86_64/op_double_to_int.S | 2 - .../mterp/x86_64/op_double_to_long.S | 2 - .../mterp/x86_64/op_fill_array_data.S | 10 - .../mterp/x86_64/op_filled_new_array.S | 17 - .../mterp/x86_64/op_filled_new_array_range.S | 2 - .../mterp/x86_64/op_float_to_double.S | 2 - .../mterp/x86_64/op_float_to_int.S | 2 - .../mterp/x86_64/op_float_to_long.S | 2 - runtime/interpreter/mterp/x86_64/op_goto.S | 11 - runtime/interpreter/mterp/x86_64/op_goto_16.S | 11 - runtime/interpreter/mterp/x86_64/op_goto_32.S | 14 - runtime/interpreter/mterp/x86_64/op_if_eq.S | 2 - runtime/interpreter/mterp/x86_64/op_if_eqz.S | 2 - runtime/interpreter/mterp/x86_64/op_if_ge.S | 2 - runtime/interpreter/mterp/x86_64/op_if_gez.S | 2 - runtime/interpreter/mterp/x86_64/op_if_gt.S | 2 - runtime/interpreter/mterp/x86_64/op_if_gtz.S | 2 - runtime/interpreter/mterp/x86_64/op_if_le.S | 2 - runtime/interpreter/mterp/x86_64/op_if_lez.S | 2 - runtime/interpreter/mterp/x86_64/op_if_lt.S | 2 - runtime/interpreter/mterp/x86_64/op_if_ltz.S | 2 - runtime/interpreter/mterp/x86_64/op_if_ne.S | 2 - runtime/interpreter/mterp/x86_64/op_if_nez.S | 2 - runtime/interpreter/mterp/x86_64/op_iget.S | 2 - .../mterp/x86_64/op_iget_boolean.S | 2 - .../mterp/x86_64/op_iget_boolean_quick.S | 2 - .../interpreter/mterp/x86_64/op_iget_byte.S | 2 - .../mterp/x86_64/op_iget_byte_quick.S | 2 - .../interpreter/mterp/x86_64/op_iget_char.S | 2 - .../mterp/x86_64/op_iget_char_quick.S | 2 - .../interpreter/mterp/x86_64/op_iget_object.S | 2 - .../mterp/x86_64/op_iget_object_quick.S | 16 - .../interpreter/mterp/x86_64/op_iget_quick.S | 18 - .../interpreter/mterp/x86_64/op_iget_short.S | 2 - .../mterp/x86_64/op_iget_short_quick.S | 2 - .../interpreter/mterp/x86_64/op_iget_wide.S | 2 - .../mterp/x86_64/op_iget_wide_quick.S | 2 - .../interpreter/mterp/x86_64/op_instance_of.S | 23 - .../interpreter/mterp/x86_64/op_int_to_byte.S | 2 - .../interpreter/mterp/x86_64/op_int_to_char.S | 2 - .../mterp/x86_64/op_int_to_double.S | 2 - .../mterp/x86_64/op_int_to_float.S | 2 - .../interpreter/mterp/x86_64/op_int_to_long.S | 9 - .../mterp/x86_64/op_int_to_short.S | 2 - .../mterp/x86_64/op_invoke_custom.S | 2 - .../mterp/x86_64/op_invoke_custom_range.S | 2 - .../mterp/x86_64/op_invoke_direct.S | 2 - .../mterp/x86_64/op_invoke_direct_range.S | 2 - .../mterp/x86_64/op_invoke_interface.S | 9 - .../mterp/x86_64/op_invoke_interface_range.S | 2 - .../mterp/x86_64/op_invoke_polymorphic.S | 2 - .../x86_64/op_invoke_polymorphic_range.S | 2 - .../mterp/x86_64/op_invoke_static.S | 3 - .../mterp/x86_64/op_invoke_static_range.S | 2 - .../mterp/x86_64/op_invoke_super.S | 9 - .../mterp/x86_64/op_invoke_super_range.S | 2 - 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deleted file mode 100644 index 9e6f91ecf7..0000000000 --- a/runtime/interpreter/mterp/arm/alt_stub.S +++ /dev/null @@ -1,14 +0,0 @@ -%def alt_stub(): -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_${opcode} - sub lr, lr, #(.L_ALT_${opcode} - .L_${opcode}) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. diff --git a/runtime/interpreter/mterp/arm/arithmetic.S b/runtime/interpreter/mterp/arm/arithmetic.S new file mode 100644 index 0000000000..6413b63627 --- /dev/null +++ b/runtime/interpreter/mterp/arm/arithmetic.S @@ -0,0 +1,975 @@ +%def binop(preinstr="", result="r0", chkzero="0", instr=""): + /* + * Generic 32-bit binary operation. Provide an "instr" line that + * specifies an instruction that performs "result = r0 op r1". + * This could be an ARM instruction or a function call. (If the result + * comes back in a register other than r0, you can override "result".) + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vCC (r1). Useful for integer division and modulus. Note that we + * *don't* check for (INT_MIN / -1) here, because the ARM math lib + * handles it correctly. + * + * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, + * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, + * mul-float, div-float, rem-float + */ + /* binop vAA, vBB, vCC */ + FETCH r0, 1 @ r0<- CCBB + mov r9, rINST, lsr #8 @ r9<- AA + mov r3, r0, lsr #8 @ r3<- CC + and r2, r0, #255 @ r2<- BB + GET_VREG r1, r3 @ r1<- vCC + GET_VREG r0, r2 @ r0<- vBB + .if $chkzero + cmp r1, #0 @ is second operand zero? + beq common_errDivideByZero + .endif + + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + $preinstr @ optional op; may set condition codes + $instr @ $result<- op, r0-r3 changed + GET_INST_OPCODE ip @ extract opcode from rINST + SET_VREG $result, r9 @ vAA<- $result + GOTO_OPCODE ip @ jump to next instruction + /* 11-14 instructions */ + +%def binop2addr(preinstr="", result="r0", chkzero="0", instr=""): + /* + * Generic 32-bit "/2addr" binary operation. Provide an "instr" line + * that specifies an instruction that performs "result = r0 op r1". + * This could be an ARM instruction or a function call. (If the result + * comes back in a register other than r0, you can override "result".) + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vCC (r1). Useful for integer division and modulus. + * + * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, + * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, + * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, + * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr + */ + /* binop/2addr vA, vB */ + mov r3, rINST, lsr #12 @ r3<- B + ubfx r9, rINST, #8, #4 @ r9<- A + GET_VREG r1, r3 @ r1<- vB + GET_VREG r0, r9 @ r0<- vA + .if $chkzero + cmp r1, #0 @ is second operand zero? + beq common_errDivideByZero + .endif + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + + $preinstr @ optional op; may set condition codes + $instr @ $result<- op, r0-r3 changed + GET_INST_OPCODE ip @ extract opcode from rINST + SET_VREG $result, r9 @ vAA<- $result + GOTO_OPCODE ip @ jump to next instruction + /* 10-13 instructions */ + +%def binopLit16(result="r0", chkzero="0", instr=""): + /* + * Generic 32-bit "lit16" binary operation. Provide an "instr" line + * that specifies an instruction that performs "result = r0 op r1". + * This could be an ARM instruction or a function call. (If the result + * comes back in a register other than r0, you can override "result".) + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vCC (r1). Useful for integer division and modulus. + * + * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, + * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 + */ + /* binop/lit16 vA, vB, #+CCCC */ + FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) + mov r2, rINST, lsr #12 @ r2<- B + ubfx r9, rINST, #8, #4 @ r9<- A + GET_VREG r0, r2 @ r0<- vB + .if $chkzero + cmp r1, #0 @ is second operand zero? + beq common_errDivideByZero + .endif + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + + $instr @ $result<- op, r0-r3 changed + GET_INST_OPCODE ip @ extract opcode from rINST + SET_VREG $result, r9 @ vAA<- $result + GOTO_OPCODE ip @ jump to next instruction + /* 10-13 instructions */ + +%def binopLit8(extract="asr r1, r3, #8", result="r0", chkzero="0", instr=""): + /* + * Generic 32-bit "lit8" binary operation. Provide an "instr" line + * that specifies an instruction that performs "result = r0 op r1". + * This could be an ARM instruction or a function call. (If the result + * comes back in a register other than r0, you can override "result".) + * + * You can override "extract" if the extraction of the literal value + * from r3 to r1 is not the default "asr r1, r3, #8". The extraction + * can be omitted completely if the shift is embedded in "instr". + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vCC (r1). Useful for integer division and modulus. + * + * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, + * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, + * shl-int/lit8, shr-int/lit8, ushr-int/lit8 + */ + /* binop/lit8 vAA, vBB, #+CC */ + FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) + mov r9, rINST, lsr #8 @ r9<- AA + and r2, r3, #255 @ r2<- BB + GET_VREG r0, r2 @ r0<- vBB + $extract @ optional; typically r1<- ssssssCC (sign extended) + .if $chkzero + @cmp r1, #0 @ is second operand zero? + beq common_errDivideByZero + .endif + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + + $instr @ $result<- op, r0-r3 changed + GET_INST_OPCODE ip @ extract opcode from rINST + SET_VREG $result, r9 @ vAA<- $result + GOTO_OPCODE ip @ jump to next instruction + /* 10-12 instructions */ + +%def binopWide(preinstr="", result0="r0", result1="r1", chkzero="0", instr=""): + /* + * Generic 64-bit binary operation. Provide an "instr" line that + * specifies an instruction that performs "result = r0-r1 op r2-r3". + * This could be an ARM instruction or a function call. (If the result + * comes back in a register other than r0, you can override "result".) + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vCC (r1). Useful for integer division and modulus. + * + * for: add-long, sub-long, div-long, rem-long, and-long, or-long, + * xor-long, add-double, sub-double, mul-double, div-double, + * rem-double + * + * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. + */ + /* binop vAA, vBB, vCC */ + FETCH r0, 1 @ r0<- CCBB + mov rINST, rINST, lsr #8 @ rINST<- AA + and r2, r0, #255 @ r2<- BB + mov r3, r0, lsr #8 @ r3<- CC + VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[AA] + VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] + ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 + ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 + .if $chkzero + orrs ip, r2, r3 @ second arg (r2-r3) is zero? + beq common_errDivideByZero + .endif + CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + $preinstr @ optional op; may set condition codes + $instr @ result<- op, r0-r3 changed + GET_INST_OPCODE ip @ extract opcode from rINST + stmia r9, {$result0,$result1} @ vAA/vAA+1<- $result0/$result1 + GOTO_OPCODE ip @ jump to next instruction + /* 14-17 instructions */ + +%def binopWide2addr(preinstr="", result0="r0", result1="r1", chkzero="0", instr=""): + /* + * Generic 64-bit "/2addr" binary operation. Provide an "instr" line + * that specifies an instruction that performs "result = r0-r1 op r2-r3". + * This could be an ARM instruction or a function call. (If the result + * comes back in a register other than r0, you can override "result".) + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vCC (r1). Useful for integer division and modulus. + * + * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, + * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, + * sub-double/2addr, mul-double/2addr, div-double/2addr, + * rem-double/2addr + */ + /* binop/2addr vA, vB */ + mov r1, rINST, lsr #12 @ r1<- B + ubfx rINST, rINST, #8, #4 @ rINST<- A + VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] + VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] + ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 + ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 + .if $chkzero + orrs ip, r2, r3 @ second arg (r2-r3) is zero? + beq common_errDivideByZero + .endif + CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + $preinstr @ optional op; may set condition codes + $instr @ result<- op, r0-r3 changed + GET_INST_OPCODE ip @ extract opcode from rINST + stmia r9, {$result0,$result1} @ vAA/vAA+1<- $result0/$result1 + GOTO_OPCODE ip @ jump to next instruction + /* 12-15 instructions */ + +%def unop(preinstr="", instr=""): + /* + * Generic 32-bit unary operation. Provide an "instr" line that + * specifies an instruction that performs "result = op r0". + * This could be an ARM instruction or a function call. + * + * for: neg-int, not-int, neg-float, int-to-float, float-to-int, + * int-to-byte, int-to-char, int-to-short + */ + /* unop vA, vB */ + mov r3, rINST, lsr #12 @ r3<- B + ubfx r9, rINST, #8, #4 @ r9<- A + GET_VREG r0, r3 @ r0<- vB + $preinstr @ optional op; may set condition codes + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + $instr @ r0<- op, r0-r3 changed + GET_INST_OPCODE ip @ extract opcode from rINST + SET_VREG r0, r9 @ vAA<- r0 + GOTO_OPCODE ip @ jump to next instruction + /* 8-9 instructions */ + +%def unopNarrower(preinstr="", instr=""): + /* + * Generic 64bit-to-32bit unary operation. Provide an "instr" line + * that specifies an instruction that performs "result = op r0/r1", where + * "result" is a 32-bit quantity in r0. + * + * For: long-to-float, double-to-int, double-to-float + * + * (This would work for long-to-int, but that instruction is actually + * an exact match for op_move.) + */ + /* unop vA, vB */ + mov r3, rINST, lsr #12 @ r3<- B + ubfx r9, rINST, #8, #4 @ r9<- A + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] + ldmia r3, {r0-r1} @ r0/r1<- vB/vB+1 + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + $preinstr @ optional op; may set condition codes + $instr @ r0<- op, r0-r3 changed + GET_INST_OPCODE ip @ extract opcode from rINST + SET_VREG r0, r9 @ vA<- r0 + GOTO_OPCODE ip @ jump to next instruction + /* 9-10 instructions */ + +%def unopWide(preinstr="", instr=""): + /* + * Generic 64-bit unary operation. Provide an "instr" line that + * specifies an instruction that performs "result = op r0/r1". + * This could be an ARM instruction or a function call. + * + * For: neg-long, not-long, neg-double, long-to-double, double-to-long + */ + /* unop vA, vB */ + mov r3, rINST, lsr #12 @ r3<- B + ubfx rINST, rINST, #8, #4 @ rINST<- A + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] + VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] + ldmia r3, {r0-r1} @ r0/r1<- vAA + CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + $preinstr @ optional op; may set condition codes + $instr @ r0/r1<- op, r2-r3 changed + GET_INST_OPCODE ip @ extract opcode from rINST + stmia r9, {r0-r1} @ vAA<- r0/r1 + GOTO_OPCODE ip @ jump to next instruction + /* 10-11 instructions */ + +%def unopWider(preinstr="", instr=""): + /* + * Generic 32bit-to-64bit unary operation. Provide an "instr" line + * that specifies an instruction that performs "result = op r0", where + * "result" is a 64-bit quantity in r0/r1. + * + * For: int-to-long, int-to-double, float-to-long, float-to-double + */ + /* unop vA, vB */ + mov r3, rINST, lsr #12 @ r3<- B + ubfx rINST, rINST, #8, #4 @ rINST<- A + GET_VREG r0, r3 @ r0<- vB + VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] + $preinstr @ optional op; may set condition codes + CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + $instr @ r0<- op, r0-r3 changed + GET_INST_OPCODE ip @ extract opcode from rINST + stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 + GOTO_OPCODE ip @ jump to next instruction + /* 9-10 instructions */ + +%def op_add_int(): +% binop(instr="add r0, r0, r1") + +%def op_add_int_2addr(): +% binop2addr(instr="add r0, r0, r1") + +%def op_add_int_lit16(): +% binopLit16(instr="add r0, r0, r1") + +%def op_add_int_lit8(): +% binopLit8(extract="", instr="add r0, r0, r3, asr #8") + +%def op_add_long(): +% binopWide(preinstr="adds r0, r0, r2", instr="adc r1, r1, r3") + +%def op_add_long_2addr(): +% binopWide2addr(preinstr="adds r0, r0, r2", instr="adc r1, r1, r3") + +%def op_and_int(): +% binop(instr="and r0, r0, r1") + +%def op_and_int_2addr(): +% binop2addr(instr="and r0, r0, r1") + +%def op_and_int_lit16(): +% binopLit16(instr="and r0, r0, r1") + +%def op_and_int_lit8(): +% binopLit8(extract="", instr="and r0, r0, r3, asr #8") + +%def op_and_long(): +% binopWide(preinstr="and r0, r0, r2", instr="and r1, r1, r3") + +%def op_and_long_2addr(): +% binopWide2addr(preinstr="and r0, r0, r2", instr="and r1, r1, r3") + +%def op_cmp_long(): + /* + * Compare two 64-bit values. Puts 0, 1, or -1 into the destination + * register based on the results of the comparison. + */ + /* cmp-long vAA, vBB, vCC */ + FETCH r0, 1 @ r0<- CCBB + mov r9, rINST, lsr #8 @ r9<- AA + and r2, r0, #255 @ r2<- BB + mov r3, r0, lsr #8 @ r3<- CC + VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] + ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 + ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 + cmp r0, r2 + sbcs ip, r1, r3 @ Sets correct CCs for checking LT (but not EQ/NE) + mov ip, #0 + mvnlt ip, #0 @ -1 + cmpeq r0, r2 @ For correct EQ/NE, we may need to repeat the first CMP + orrne ip, #1 + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + SET_VREG ip, r9 @ vAA<- ip + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def op_div_int(): + /* + * Specialized 32-bit binary operation + * + * Performs "r0 = r0 div r1". The selection between sdiv or the gcc helper + * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for + * ARMv7 CPUs that have hardware division support). + * + * div-int + * + */ + FETCH r0, 1 @ r0<- CCBB + mov r9, rINST, lsr #8 @ r9<- AA + mov r3, r0, lsr #8 @ r3<- CC + and r2, r0, #255 @ r2<- BB + GET_VREG r1, r3 @ r1<- vCC + GET_VREG r0, r2 @ r0<- vBB + cmp r1, #0 @ is second operand zero? + beq common_errDivideByZero + + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST +#ifdef __ARM_ARCH_EXT_IDIV__ + sdiv r0, r0, r1 @ r0<- op +#else + bl __aeabi_idiv @ r0<- op, r0-r3 changed +#endif + GET_INST_OPCODE ip @ extract opcode from rINST + SET_VREG r0, r9 @ vAA<- r0 + GOTO_OPCODE ip @ jump to next instruction + /* 11-14 instructions */ + +%def op_div_int_2addr(): + /* + * Specialized 32-bit binary operation + * + * Performs "r0 = r0 div r1". The selection between sdiv or the gcc helper + * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for + * ARMv7 CPUs that have hardware division support). + * + * div-int/2addr + * + */ + mov r3, rINST, lsr #12 @ r3<- B + ubfx r9, rINST, #8, #4 @ r9<- A + GET_VREG r1, r3 @ r1<- vB + GET_VREG r0, r9 @ r0<- vA + cmp r1, #0 @ is second operand zero? + beq common_errDivideByZero + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + +#ifdef __ARM_ARCH_EXT_IDIV__ + sdiv r0, r0, r1 @ r0<- op +#else + bl __aeabi_idiv @ r0<- op, r0-r3 changed +#endif + GET_INST_OPCODE ip @ extract opcode from rINST + SET_VREG r0, r9 @ vAA<- r0 + GOTO_OPCODE ip @ jump to next instruction + /* 10-13 instructions */ + + +%def op_div_int_lit16(): + /* + * Specialized 32-bit binary operation + * + * Performs "r0 = r0 div r1". The selection between sdiv or the gcc helper + * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for + * ARMv7 CPUs that have hardware division support). + * + * div-int/lit16 + * + */ + FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) + mov r2, rINST, lsr #12 @ r2<- B + ubfx r9, rINST, #8, #4 @ r9<- A + GET_VREG r0, r2 @ r0<- vB + cmp r1, #0 @ is second operand zero? + beq common_errDivideByZero + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + +#ifdef __ARM_ARCH_EXT_IDIV__ + sdiv r0, r0, r1 @ r0<- op +#else + bl __aeabi_idiv @ r0<- op, r0-r3 changed +#endif + GET_INST_OPCODE ip @ extract opcode from rINST + SET_VREG r0, r9 @ vAA<- r0 + GOTO_OPCODE ip @ jump to next instruction + /* 10-13 instructions */ + +%def op_div_int_lit8(): + /* + * Specialized 32-bit binary operation + * + * Performs "r0 = r0 div r1". The selection between sdiv or the gcc helper + * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for + * ARMv7 CPUs that have hardware division support). + * + * div-int/lit8 + * + */ + FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC + mov r9, rINST, lsr #8 @ r9<- AA + and r2, r3, #255 @ r2<- BB + GET_VREG r0, r2 @ r0<- vBB + movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) + @cmp r1, #0 @ is second operand zero? + beq common_errDivideByZero + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + +#ifdef __ARM_ARCH_EXT_IDIV__ + sdiv r0, r0, r1 @ r0<- op +#else + bl __aeabi_idiv @ r0<- op, r0-r3 changed +#endif + GET_INST_OPCODE ip @ extract opcode from rINST + SET_VREG r0, r9 @ vAA<- r0 + GOTO_OPCODE ip @ jump to next instruction + /* 10-12 instructions */ + +%def op_div_long(): +% binopWide(instr="bl __aeabi_ldivmod", chkzero="1") + +%def op_div_long_2addr(): +% binopWide2addr(instr="bl __aeabi_ldivmod", chkzero="1") + +%def op_int_to_byte(): +% unop(instr="sxtb r0, r0") + +%def op_int_to_char(): +% unop(instr="uxth r0, r0") + +%def op_int_to_long(): +% unopWider(instr="mov r1, r0, asr #31") + +%def op_int_to_short(): +% unop(instr="sxth r0, r0") + +%def op_long_to_int(): +/* we ignore the high word, making this equivalent to a 32-bit reg move */ +% op_move() + +%def op_mul_int(): +/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ +% binop(instr="mul r0, r1, r0") + +%def op_mul_int_2addr(): +/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ +% binop2addr(instr="mul r0, r1, r0") + +%def op_mul_int_lit16(): +/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ +% binopLit16(instr="mul r0, r1, r0") + +%def op_mul_int_lit8(): +/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ +% binopLit8(instr="mul r0, r1, r0") + +%def op_mul_long(): + /* + * Signed 64-bit integer multiply. + * + * Consider WXxYZ (r1r0 x r3r2) with a long multiply: + * WX + * x YZ + * -------- + * ZW ZX + * YW YX + * + * The low word of the result holds ZX, the high word holds + * (ZW+YX) + (the high overflow from ZX). YW doesn't matter because + * it doesn't fit in the low 64 bits. + * + * Unlike most ARM math operations, multiply instructions have + * restrictions on using the same register more than once (Rd and Rm + * cannot be the same). + */ + /* mul-long vAA, vBB, vCC */ + FETCH r0, 1 @ r0<- CCBB + and r2, r0, #255 @ r2<- BB + mov r3, r0, lsr #8 @ r3<- CC + VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] + ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 + ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 + mul ip, r2, r1 @ ip<- ZxW + umull r1, lr, r2, r0 @ r1/lr <- ZxX + mla r2, r0, r3, ip @ r2<- YxX + (ZxW) + mov r0, rINST, lsr #8 @ r0<- AA + add r2, r2, lr @ r2<- lr + low(ZxW + (YxX)) + CLEAR_SHADOW_PAIR r0, lr, ip @ Zero out the shadow regs + VREG_INDEX_TO_ADDR r0, r0 @ r0<- &fp[AA] + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + GET_INST_OPCODE ip @ extract opcode from rINST + stmia r0, {r1-r2 } @ vAA/vAA+1<- r1/r2 + GOTO_OPCODE ip @ jump to next instruction + +%def op_mul_long_2addr(): + /* + * Signed 64-bit integer multiply, "/2addr" version. + * + * See op_mul_long for an explanation. + * + * We get a little tight on registers, so to avoid looking up &fp[A] + * again we stuff it into rINST. + */ + /* mul-long/2addr vA, vB */ + mov r1, rINST, lsr #12 @ r1<- B + ubfx r9, rINST, #8, #4 @ r9<- A + VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] + VREG_INDEX_TO_ADDR rINST, r9 @ rINST<- &fp[A] + ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 + ldmia rINST, {r0-r1} @ r0/r1<- vAA/vAA+1 + mul ip, r2, r1 @ ip<- ZxW + umull r1, lr, r2, r0 @ r1/lr <- ZxX + mla r2, r0, r3, ip @ r2<- YxX + (ZxW) + mov r0, rINST @ r0<- &fp[A] (free up rINST) + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + add r2, r2, lr @ r2<- r2 + low(ZxW + (YxX)) + GET_INST_OPCODE ip @ extract opcode from rINST + stmia r0, {r1-r2} @ vAA/vAA+1<- r1/r2 + GOTO_OPCODE ip @ jump to next instruction + +%def op_neg_int(): +% unop(instr="rsb r0, r0, #0") + +%def op_neg_long(): +% unopWide(preinstr="rsbs r0, r0, #0", instr="rsc r1, r1, #0") + +%def op_not_int(): +% unop(instr="mvn r0, r0") + +%def op_not_long(): +% unopWide(preinstr="mvn r0, r0", instr="mvn r1, r1") + +%def op_or_int(): +% binop(instr="orr r0, r0, r1") + +%def op_or_int_2addr(): +% binop2addr(instr="orr r0, r0, r1") + +%def op_or_int_lit16(): +% binopLit16(instr="orr r0, r0, r1") + +%def op_or_int_lit8(): +% binopLit8(extract="", instr="orr r0, r0, r3, asr #8") + +%def op_or_long(): +% binopWide(preinstr="orr r0, r0, r2", instr="orr r1, r1, r3") + +%def op_or_long_2addr(): +% binopWide2addr(preinstr="orr r0, r0, r2", instr="orr r1, r1, r3") + +%def op_rem_int(): + /* + * Specialized 32-bit binary operation + * + * Performs "r1 = r0 rem r1". The selection between sdiv block or the gcc helper + * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for + * ARMv7 CPUs that have hardware division support). + * + * NOTE: idivmod returns quotient in r0 and remainder in r1 + * + * rem-int + * + */ + FETCH r0, 1 @ r0<- CCBB + mov r9, rINST, lsr #8 @ r9<- AA + mov r3, r0, lsr #8 @ r3<- CC + and r2, r0, #255 @ r2<- BB + GET_VREG r1, r3 @ r1<- vCC + GET_VREG r0, r2 @ r0<- vBB + cmp r1, #0 @ is second operand zero? + beq common_errDivideByZero + + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST +#ifdef __ARM_ARCH_EXT_IDIV__ + sdiv r2, r0, r1 + mls r1, r1, r2, r0 @ r1<- op, r0-r2 changed +#else + bl __aeabi_idivmod @ r1<- op, r0-r3 changed +#endif + GET_INST_OPCODE ip @ extract opcode from rINST + SET_VREG r1, r9 @ vAA<- r1 + GOTO_OPCODE ip @ jump to next instruction + /* 11-14 instructions */ + +%def op_rem_int_2addr(): + /* + * Specialized 32-bit binary operation + * + * Performs "r1 = r0 rem r1". The selection between sdiv block or the gcc helper + * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for + * ARMv7 CPUs that have hardware division support). + * + * NOTE: idivmod returns quotient in r0 and remainder in r1 + * + * rem-int/2addr + * + */ + mov r3, rINST, lsr #12 @ r3<- B + ubfx r9, rINST, #8, #4 @ r9<- A + GET_VREG r1, r3 @ r1<- vB + GET_VREG r0, r9 @ r0<- vA + cmp r1, #0 @ is second operand zero? + beq common_errDivideByZero + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + +#ifdef __ARM_ARCH_EXT_IDIV__ + sdiv r2, r0, r1 + mls r1, r1, r2, r0 @ r1<- op +#else + bl __aeabi_idivmod @ r1<- op, r0-r3 changed +#endif + GET_INST_OPCODE ip @ extract opcode from rINST + SET_VREG r1, r9 @ vAA<- r1 + GOTO_OPCODE ip @ jump to next instruction + /* 10-13 instructions */ + + +%def op_rem_int_lit16(): + /* + * Specialized 32-bit binary operation + * + * Performs "r1 = r0 rem r1". The selection between sdiv block or the gcc helper + * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for + * ARMv7 CPUs that have hardware division support). + * + * NOTE: idivmod returns quotient in r0 and remainder in r1 + * + * rem-int/lit16 + * + */ + FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) + mov r2, rINST, lsr #12 @ r2<- B + ubfx r9, rINST, #8, #4 @ r9<- A + GET_VREG r0, r2 @ r0<- vB + cmp r1, #0 @ is second operand zero? + beq common_errDivideByZero + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + +#ifdef __ARM_ARCH_EXT_IDIV__ + sdiv r2, r0, r1 + mls r1, r1, r2, r0 @ r1<- op +#else + bl __aeabi_idivmod @ r1<- op, r0-r3 changed +#endif + GET_INST_OPCODE ip @ extract opcode from rINST + SET_VREG r1, r9 @ vAA<- r1 + GOTO_OPCODE ip @ jump to next instruction + /* 10-13 instructions */ + +%def op_rem_int_lit8(): + /* + * Specialized 32-bit binary operation + * + * Performs "r1 = r0 rem r1". The selection between sdiv block or the gcc helper + * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for + * ARMv7 CPUs that have hardware division support). + * + * NOTE: idivmod returns quotient in r0 and remainder in r1 + * + * rem-int/lit8 + * + */ + FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) + mov r9, rINST, lsr #8 @ r9<- AA + and r2, r3, #255 @ r2<- BB + GET_VREG r0, r2 @ r0<- vBB + movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) + @cmp r1, #0 @ is second operand zero? + beq common_errDivideByZero + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + +#ifdef __ARM_ARCH_EXT_IDIV__ + sdiv r2, r0, r1 + mls r1, r1, r2, r0 @ r1<- op +#else + bl __aeabi_idivmod @ r1<- op, r0-r3 changed +#endif + GET_INST_OPCODE ip @ extract opcode from rINST + SET_VREG r1, r9 @ vAA<- r1 + GOTO_OPCODE ip @ jump to next instruction + /* 10-12 instructions */ + +%def op_rem_long(): +/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ +% binopWide(instr="bl __aeabi_ldivmod", result0="r2", result1="r3", chkzero="1") + +%def op_rem_long_2addr(): +/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ +% binopWide2addr(instr="bl __aeabi_ldivmod", result0="r2", result1="r3", chkzero="1") + +%def op_rsub_int(): +/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ +% binopLit16(instr="rsb r0, r0, r1") + +%def op_rsub_int_lit8(): +% binopLit8(extract="", instr="rsb r0, r0, r3, asr #8") + +%def op_shl_int(): +% binop(preinstr="and r1, r1, #31", instr="mov r0, r0, asl r1") + +%def op_shl_int_2addr(): +% binop2addr(preinstr="and r1, r1, #31", instr="mov r0, r0, asl r1") + +%def op_shl_int_lit8(): +% binopLit8(extract="ubfx r1, r3, #8, #5", instr="mov r0, r0, asl r1") + +%def op_shl_long(): + /* + * Long integer shift. This is different from the generic 32/64-bit + * binary operations because vAA/vBB are 64-bit but vCC (the shift + * distance) is 32-bit. Also, Dalvik requires us to mask off the low + * 6 bits of the shift distance. + */ + /* shl-long vAA, vBB, vCC */ + FETCH r0, 1 @ r0<- CCBB + mov r9, rINST, lsr #8 @ r9<- AA + and r3, r0, #255 @ r3<- BB + mov r0, r0, lsr #8 @ r0<- CC + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[BB] + GET_VREG r2, r0 @ r2<- vCC + ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 + CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs + and r2, r2, #63 @ r2<- r2 & 0x3f + VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] + mov r1, r1, asl r2 @ r1<- r1 << r2 + rsb r3, r2, #32 @ r3<- 32 - r2 + orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) + subs ip, r2, #32 @ ip<- r2 - 32 + movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + mov r0, r0, asl r2 @ r0<- r0 << r2 + GET_INST_OPCODE ip @ extract opcode from rINST + stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 + GOTO_OPCODE ip @ jump to next instruction + +%def op_shl_long_2addr(): + /* + * Long integer shift, 2addr version. vA is 64-bit value/result, vB is + * 32-bit shift distance. + */ + /* shl-long/2addr vA, vB */ + mov r3, rINST, lsr #12 @ r3<- B + ubfx r9, rINST, #8, #4 @ r9<- A + GET_VREG r2, r3 @ r2<- vB + CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs + VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[A] + and r2, r2, #63 @ r2<- r2 & 0x3f + ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 + mov r1, r1, asl r2 @ r1<- r1 << r2 + rsb r3, r2, #32 @ r3<- 32 - r2 + orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) + subs ip, r2, #32 @ ip<- r2 - 32 + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) + mov r0, r0, asl r2 @ r0<- r0 << r2 + GET_INST_OPCODE ip @ extract opcode from rINST + stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 + GOTO_OPCODE ip @ jump to next instruction + +%def op_shr_int(): +% binop(preinstr="and r1, r1, #31", instr="mov r0, r0, asr r1") + +%def op_shr_int_2addr(): +% binop2addr(preinstr="and r1, r1, #31", instr="mov r0, r0, asr r1") + +%def op_shr_int_lit8(): +% binopLit8(extract="ubfx r1, r3, #8, #5", instr="mov r0, r0, asr r1") + +%def op_shr_long(): + /* + * Long integer shift. This is different from the generic 32/64-bit + * binary operations because vAA/vBB are 64-bit but vCC (the shift + * distance) is 32-bit. Also, Dalvik requires us to mask off the low + * 6 bits of the shift distance. + */ + /* shr-long vAA, vBB, vCC */ + FETCH r0, 1 @ r0<- CCBB + mov r9, rINST, lsr #8 @ r9<- AA + and r3, r0, #255 @ r3<- BB + mov r0, r0, lsr #8 @ r0<- CC + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[BB] + GET_VREG r2, r0 @ r2<- vCC + ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 + CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs + and r2, r2, #63 @ r0<- r0 & 0x3f + VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] + mov r0, r0, lsr r2 @ r0<- r2 >> r2 + rsb r3, r2, #32 @ r3<- 32 - r2 + orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) + subs ip, r2, #32 @ ip<- r2 - 32 + movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + mov r1, r1, asr r2 @ r1<- r1 >> r2 + GET_INST_OPCODE ip @ extract opcode from rINST + stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 + GOTO_OPCODE ip @ jump to next instruction + +%def op_shr_long_2addr(): + /* + * Long integer shift, 2addr version. vA is 64-bit value/result, vB is + * 32-bit shift distance. + */ + /* shr-long/2addr vA, vB */ + mov r3, rINST, lsr #12 @ r3<- B + ubfx r9, rINST, #8, #4 @ r9<- A + GET_VREG r2, r3 @ r2<- vB + CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs + VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[A] + and r2, r2, #63 @ r2<- r2 & 0x3f + ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 + mov r0, r0, lsr r2 @ r0<- r2 >> r2 + rsb r3, r2, #32 @ r3<- 32 - r2 + orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) + subs ip, r2, #32 @ ip<- r2 - 32 + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) + mov r1, r1, asr r2 @ r1<- r1 >> r2 + GET_INST_OPCODE ip @ extract opcode from rINST + stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 + GOTO_OPCODE ip @ jump to next instruction + +%def op_sub_int(): +% binop(instr="sub r0, r0, r1") + +%def op_sub_int_2addr(): +% binop2addr(instr="sub r0, r0, r1") + +%def op_sub_long(): +% binopWide(preinstr="subs r0, r0, r2", instr="sbc r1, r1, r3") + +%def op_sub_long_2addr(): +% binopWide2addr(preinstr="subs r0, r0, r2", instr="sbc r1, r1, r3") + +%def op_ushr_int(): +% binop(preinstr="and r1, r1, #31", instr="mov r0, r0, lsr r1") + +%def op_ushr_int_2addr(): +% binop2addr(preinstr="and r1, r1, #31", instr="mov r0, r0, lsr r1") + +%def op_ushr_int_lit8(): +% binopLit8(extract="ubfx r1, r3, #8, #5", instr="mov r0, r0, lsr r1") + +%def op_ushr_long(): + /* + * Long integer shift. This is different from the generic 32/64-bit + * binary operations because vAA/vBB are 64-bit but vCC (the shift + * distance) is 32-bit. Also, Dalvik requires us to mask off the low + * 6 bits of the shift distance. + */ + /* ushr-long vAA, vBB, vCC */ + FETCH r0, 1 @ r0<- CCBB + mov r9, rINST, lsr #8 @ r9<- AA + and r3, r0, #255 @ r3<- BB + mov r0, r0, lsr #8 @ r0<- CC + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[BB] + GET_VREG r2, r0 @ r2<- vCC + ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 + CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs + and r2, r2, #63 @ r0<- r0 & 0x3f + VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] + mov r0, r0, lsr r2 @ r0<- r2 >> r2 + rsb r3, r2, #32 @ r3<- 32 - r2 + orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) + subs ip, r2, #32 @ ip<- r2 - 32 + movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + mov r1, r1, lsr r2 @ r1<- r1 >>> r2 + GET_INST_OPCODE ip @ extract opcode from rINST + stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 + GOTO_OPCODE ip @ jump to next instruction + +%def op_ushr_long_2addr(): + /* + * Long integer shift, 2addr version. vA is 64-bit value/result, vB is + * 32-bit shift distance. + */ + /* ushr-long/2addr vA, vB */ + mov r3, rINST, lsr #12 @ r3<- B + ubfx r9, rINST, #8, #4 @ r9<- A + GET_VREG r2, r3 @ r2<- vB + CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs + VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[A] + and r2, r2, #63 @ r2<- r2 & 0x3f + ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 + mov r0, r0, lsr r2 @ r0<- r2 >> r2 + rsb r3, r2, #32 @ r3<- 32 - r2 + orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) + subs ip, r2, #32 @ ip<- r2 - 32 + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) + mov r1, r1, lsr r2 @ r1<- r1 >>> r2 + GET_INST_OPCODE ip @ extract opcode from rINST + stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 + GOTO_OPCODE ip @ jump to next instruction + +%def op_xor_int(): +% binop(instr="eor r0, r0, r1") + +%def op_xor_int_2addr(): +% binop2addr(instr="eor r0, r0, r1") + +%def op_xor_int_lit16(): +% binopLit16(instr="eor r0, r0, r1") + +%def op_xor_int_lit8(): +% binopLit8(extract="", instr="eor r0, r0, r3, asr #8") + +%def op_xor_long(): +% binopWide(preinstr="eor r0, r0, r2", instr="eor r1, r1, r3") + +%def op_xor_long_2addr(): +% binopWide2addr(preinstr="eor r0, r0, r2", instr="eor r1, r1, r3") diff --git a/runtime/interpreter/mterp/arm/array.S b/runtime/interpreter/mterp/arm/array.S new file mode 100644 index 0000000000..88d89c53a2 --- /dev/null +++ b/runtime/interpreter/mterp/arm/array.S @@ -0,0 +1,250 @@ +%def op_aget(load="ldr", shift="2", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"): + /* + * Array get, 32 bits or less. vAA <- vBB[vCC]. + * + * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 + * instructions. We use a pair of FETCH_Bs instead. + * + * for: aget, aget-boolean, aget-byte, aget-char, aget-short + * + * NOTE: assumes data offset for arrays is the same for all non-wide types. + * If this changes, specialize. + */ + /* op vAA, vBB, vCC */ + FETCH_B r2, 1, 0 @ r2<- BB + mov r9, rINST, lsr #8 @ r9<- AA + FETCH_B r3, 1, 1 @ r3<- CC + GET_VREG r0, r2 @ r0<- vBB (array object) + GET_VREG r1, r3 @ r1<- vCC (requested index) + cmp r0, #0 @ null array object? + beq common_errNullObject @ yes, bail + ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length + add r0, r0, r1, lsl #$shift @ r0<- arrayObj + index*width + cmp r1, r3 @ compare unsigned index, length + bcs common_errArrayIndex @ index >= length, bail + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + $load r2, [r0, #$data_offset] @ r2<- vBB[vCC] + GET_INST_OPCODE ip @ extract opcode from rINST + SET_VREG r2, r9 @ vAA<- r2 + GOTO_OPCODE ip @ jump to next instruction + +%def op_aget_boolean(): +% op_aget(load="ldrb", shift="0", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") + +%def op_aget_byte(): +% op_aget(load="ldrsb", shift="0", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") + +%def op_aget_char(): +% op_aget(load="ldrh", shift="1", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") + +%def op_aget_object(): + /* + * Array object get. vAA <- vBB[vCC]. + * + * for: aget-object + */ + /* op vAA, vBB, vCC */ + FETCH_B r2, 1, 0 @ r2<- BB + mov r9, rINST, lsr #8 @ r9<- AA + FETCH_B r3, 1, 1 @ r3<- CC + EXPORT_PC + GET_VREG r0, r2 @ r0<- vBB (array object) + GET_VREG r1, r3 @ r1<- vCC (requested index) + bl artAGetObjectFromMterp @ (array, index) + ldr r1, [rSELF, #THREAD_EXCEPTION_OFFSET] + PREFETCH_INST 2 + cmp r1, #0 + bne MterpException + SET_VREG_OBJECT r0, r9 + ADVANCE 2 + GET_INST_OPCODE ip + GOTO_OPCODE ip @ jump to next instruction + +%def op_aget_short(): +% op_aget(load="ldrsh", shift="1", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") + +%def op_aget_wide(): + /* + * Array get, 64 bits. vAA <- vBB[vCC]. + * + * Arrays of long/double are 64-bit aligned, so it's okay to use LDRD. + */ + /* aget-wide vAA, vBB, vCC */ + FETCH r0, 1 @ r0<- CCBB + mov r9, rINST, lsr #8 @ r9<- AA + and r2, r0, #255 @ r2<- BB + mov r3, r0, lsr #8 @ r3<- CC + GET_VREG r0, r2 @ r0<- vBB (array object) + GET_VREG r1, r3 @ r1<- vCC (requested index) + cmp r0, #0 @ null array object? + beq common_errNullObject @ yes, bail + ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length + add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width + cmp r1, r3 @ compare unsigned index, length + bcs common_errArrayIndex @ index >= length, bail + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs + ldrd r2, [r0, #MIRROR_WIDE_ARRAY_DATA_OFFSET] @ r2/r3<- vBB[vCC] + VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] + GET_INST_OPCODE ip @ extract opcode from rINST + stmia r9, {r2-r3} @ vAA/vAA+1<- r2/r3 + GOTO_OPCODE ip @ jump to next instruction + +%def op_aput(store="str", shift="2", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"): + /* + * Array put, 32 bits or less. vBB[vCC] <- vAA. + * + * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 + * instructions. We use a pair of FETCH_Bs instead. + * + * for: aput, aput-boolean, aput-byte, aput-char, aput-short + * + * NOTE: this assumes data offset for arrays is the same for all non-wide types. + * If this changes, specialize. + */ + /* op vAA, vBB, vCC */ + FETCH_B r2, 1, 0 @ r2<- BB + mov r9, rINST, lsr #8 @ r9<- AA + FETCH_B r3, 1, 1 @ r3<- CC + GET_VREG r0, r2 @ r0<- vBB (array object) + GET_VREG r1, r3 @ r1<- vCC (requested index) + cmp r0, #0 @ null array object? + beq common_errNullObject @ yes, bail + ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length + add r0, r0, r1, lsl #$shift @ r0<- arrayObj + index*width + cmp r1, r3 @ compare unsigned index, length + bcs common_errArrayIndex @ index >= length, bail + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + GET_VREG r2, r9 @ r2<- vAA + GET_INST_OPCODE ip @ extract opcode from rINST + $store r2, [r0, #$data_offset] @ vBB[vCC]<- r2 + GOTO_OPCODE ip @ jump to next instruction + +%def op_aput_boolean(): +% op_aput(store="strb", shift="0", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") + +%def op_aput_byte(): +% op_aput(store="strb", shift="0", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") + +%def op_aput_char(): +% op_aput(store="strh", shift="1", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") + +%def op_aput_object(): + /* + * Store an object into an array. vBB[vCC] <- vAA. + */ + /* op vAA, vBB, vCC */ + EXPORT_PC + add r0, rFP, #OFF_FP_SHADOWFRAME + mov r1, rPC + mov r2, rINST + bl MterpAputObject + cmp r0, #0 + beq MterpPossibleException + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def op_aput_short(): +% op_aput(store="strh", shift="1", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") + +%def op_aput_wide(): + /* + * Array put, 64 bits. vBB[vCC] <- vAA. + * + * Arrays of long/double are 64-bit aligned, so it's okay to use STRD. + */ + /* aput-wide vAA, vBB, vCC */ + FETCH r0, 1 @ r0<- CCBB + mov r9, rINST, lsr #8 @ r9<- AA + and r2, r0, #255 @ r2<- BB + mov r3, r0, lsr #8 @ r3<- CC + GET_VREG r0, r2 @ r0<- vBB (array object) + GET_VREG r1, r3 @ r1<- vCC (requested index) + cmp r0, #0 @ null array object? + beq common_errNullObject @ yes, bail + ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length + add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width + cmp r1, r3 @ compare unsigned index, length + VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] + bcs common_errArrayIndex @ index >= length, bail + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + ldmia r9, {r2-r3} @ r2/r3<- vAA/vAA+1 + GET_INST_OPCODE ip @ extract opcode from rINST + strd r2, [r0, #MIRROR_WIDE_ARRAY_DATA_OFFSET] @ r2/r3<- vBB[vCC] + GOTO_OPCODE ip @ jump to next instruction + +%def op_array_length(): + /* + * Return the length of an array. + */ + mov r1, rINST, lsr #12 @ r1<- B + ubfx r2, rINST, #8, #4 @ r2<- A + GET_VREG r0, r1 @ r0<- vB (object ref) + cmp r0, #0 @ is object null? + beq common_errNullObject @ yup, fail + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- array length + GET_INST_OPCODE ip @ extract opcode from rINST + SET_VREG r3, r2 @ vB<- length + GOTO_OPCODE ip @ jump to next instruction + +%def op_fill_array_data(): + /* fill-array-data vAA, +BBBBBBBB */ + EXPORT_PC + FETCH r0, 1 @ r0<- bbbb (lo) + FETCH r1, 2 @ r1<- BBBB (hi) + mov r3, rINST, lsr #8 @ r3<- AA + orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb + GET_VREG r0, r3 @ r0<- vAA (array object) + add r1, rPC, r1, lsl #1 @ r1<- PC + BBBBbbbb*2 (array data off.) + bl MterpFillArrayData @ (obj, payload) + cmp r0, #0 @ 0 means an exception is thrown + beq MterpPossibleException @ exception? + FETCH_ADVANCE_INST 3 @ advance rPC, load rINST + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def op_filled_new_array(helper="MterpFilledNewArray"): + /* + * Create a new array with elements filled from registers. + * + * for: filled-new-array, filled-new-array/range + */ + /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ + /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ + .extern $helper + EXPORT_PC + add r0, rFP, #OFF_FP_SHADOWFRAME + mov r1, rPC + mov r2, rSELF + bl $helper + cmp r0, #0 + beq MterpPossibleException + FETCH_ADVANCE_INST 3 @ advance rPC, load rINST + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def op_filled_new_array_range(): +% op_filled_new_array(helper="MterpFilledNewArrayRange") + +%def op_new_array(): + /* + * Allocate an array of objects, specified with the array class + * and a count. + * + * The verifier guarantees that this is an array class, so we don't + * check for it here. + */ + /* new-array vA, vB, class@CCCC */ + EXPORT_PC + add r0, rFP, #OFF_FP_SHADOWFRAME + mov r1, rPC + mov r2, rINST + mov r3, rSELF + bl MterpNewArray + cmp r0, #0 + beq MterpPossibleException + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/bincmp.S b/runtime/interpreter/mterp/arm/bincmp.S deleted file mode 100644 index 368c2d6971..0000000000 --- a/runtime/interpreter/mterp/arm/bincmp.S +++ /dev/null @@ -1,20 +0,0 @@ -%def bincmp(condition=""): - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - mov r1, rINST, lsr #12 @ r1<- B - ubfx r0, rINST, #8, #4 @ r0<- A - GET_VREG r3, r1 @ r3<- vB - GET_VREG r0, r0 @ r0<- vA - FETCH_S rINST, 1 @ rINST<- branch offset, in code units - cmp r0, r3 @ compare (vA, vB) - b${condition} MterpCommonTakenBranchNoFlags - cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? - beq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/binop.S b/runtime/interpreter/mterp/arm/binop.S deleted file mode 100644 index 72ae9f4b38..0000000000 --- a/runtime/interpreter/mterp/arm/binop.S +++ /dev/null @@ -1,35 +0,0 @@ -%def binop(preinstr="", result="r0", chkzero="0", instr=""): - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - GET_VREG r1, r3 @ r1<- vCC - GET_VREG r0, r2 @ r0<- vBB - .if $chkzero - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - $preinstr @ optional op; may set condition codes - $instr @ $result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG $result, r9 @ vAA<- $result - GOTO_OPCODE ip @ jump to next instruction - /* 11-14 instructions */ diff --git a/runtime/interpreter/mterp/arm/binop2addr.S b/runtime/interpreter/mterp/arm/binop2addr.S deleted file mode 100644 index 6f7f23c2aa..0000000000 --- a/runtime/interpreter/mterp/arm/binop2addr.S +++ /dev/null @@ -1,32 +0,0 @@ -%def binop2addr(preinstr="", result="r0", chkzero="0", instr=""): - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r1, r3 @ r1<- vB - GET_VREG r0, r9 @ r0<- vA - .if $chkzero - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - - $preinstr @ optional op; may set condition codes - $instr @ $result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG $result, r9 @ vAA<- $result - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ diff --git a/runtime/interpreter/mterp/arm/binopLit16.S b/runtime/interpreter/mterp/arm/binopLit16.S deleted file mode 100644 index 86291b5655..0000000000 --- a/runtime/interpreter/mterp/arm/binopLit16.S +++ /dev/null @@ -1,29 +0,0 @@ -%def binopLit16(result="r0", chkzero="0", instr=""): - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) - mov r2, rINST, lsr #12 @ r2<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r0, r2 @ r0<- vB - .if $chkzero - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - - $instr @ $result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG $result, r9 @ vAA<- $result - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ diff --git a/runtime/interpreter/mterp/arm/binopLit8.S b/runtime/interpreter/mterp/arm/binopLit8.S deleted file mode 100644 index b850e496e7..0000000000 --- a/runtime/interpreter/mterp/arm/binopLit8.S +++ /dev/null @@ -1,35 +0,0 @@ -%def binopLit8(extract="asr r1, r3, #8", result="r0", chkzero="0", instr=""): - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from r3 to r1 is not the default "asr r1, r3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r3, #255 @ r2<- BB - GET_VREG r0, r2 @ r0<- vBB - $extract @ optional; typically r1<- ssssssCC (sign extended) - .if $chkzero - @cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - - $instr @ $result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG $result, r9 @ vAA<- $result - GOTO_OPCODE ip @ jump to next instruction - /* 10-12 instructions */ diff --git a/runtime/interpreter/mterp/arm/binopWide.S b/runtime/interpreter/mterp/arm/binopWide.S deleted file mode 100644 index b708627f97..0000000000 --- a/runtime/interpreter/mterp/arm/binopWide.S +++ /dev/null @@ -1,38 +0,0 @@ -%def binopWide(preinstr="", result0="r0", result1="r1", chkzero="0", instr=""): - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = r0-r1 op r2-r3". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * for: add-long, sub-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, - * rem-double - * - * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. - */ - /* binop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov rINST, rINST, lsr #8 @ rINST<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[AA] - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] - ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 - ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 - .if $chkzero - orrs ip, r2, r3 @ second arg (r2-r3) is zero? - beq common_errDivideByZero - .endif - CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - $preinstr @ optional op; may set condition codes - $instr @ result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {$result0,$result1} @ vAA/vAA+1<- $result0/$result1 - GOTO_OPCODE ip @ jump to next instruction - /* 14-17 instructions */ diff --git a/runtime/interpreter/mterp/arm/binopWide2addr.S b/runtime/interpreter/mterp/arm/binopWide2addr.S deleted file mode 100644 index 2ce513088b..0000000000 --- a/runtime/interpreter/mterp/arm/binopWide2addr.S +++ /dev/null @@ -1,34 +0,0 @@ -%def binopWide2addr(preinstr="", result0="r0", result1="r1", chkzero="0", instr=""): - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0-r1 op r2-r3". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, - * rem-double/2addr - */ - /* binop/2addr vA, vB */ - mov r1, rINST, lsr #12 @ r1<- B - ubfx rINST, rINST, #8, #4 @ rINST<- A - VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] - ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 - ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 - .if $chkzero - orrs ip, r2, r3 @ second arg (r2-r3) is zero? - beq common_errDivideByZero - .endif - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - $preinstr @ optional op; may set condition codes - $instr @ result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {$result0,$result1} @ vAA/vAA+1<- $result0/$result1 - GOTO_OPCODE ip @ jump to next instruction - /* 12-15 instructions */ diff --git a/runtime/interpreter/mterp/arm/const.S b/runtime/interpreter/mterp/arm/const.S deleted file mode 100644 index a22f366c97..0000000000 --- a/runtime/interpreter/mterp/arm/const.S +++ /dev/null @@ -1,18 +0,0 @@ -%def const(helper="UndefinedConstHandler"): - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern $helper - EXPORT_PC - FETCH r0, 1 @ r0<- BBBB - mov r1, rINST, lsr #8 @ r1<- AA - add r2, rFP, #OFF_FP_SHADOWFRAME - mov r3, rSELF - bl $helper @ (index, tgt_reg, shadow_frame, self) - PREFETCH_INST 2 @ load rINST - cmp r0, #0 @ fail? - bne MterpPossibleException @ let reference interpreter deal with it. - ADVANCE 2 @ advance rPC - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/control_flow.S b/runtime/interpreter/mterp/arm/control_flow.S new file mode 100644 index 0000000000..51832e10b5 --- /dev/null +++ b/runtime/interpreter/mterp/arm/control_flow.S @@ -0,0 +1,209 @@ +%def bincmp(condition=""): + /* + * Generic two-operand compare-and-branch operation. Provide a "condition" + * fragment that specifies the comparison to perform. + * + * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le + */ + /* if-cmp vA, vB, +CCCC */ + mov r1, rINST, lsr #12 @ r1<- B + ubfx r0, rINST, #8, #4 @ r0<- A + GET_VREG r3, r1 @ r3<- vB + GET_VREG r0, r0 @ r0<- vA + FETCH_S rINST, 1 @ rINST<- branch offset, in code units + cmp r0, r3 @ compare (vA, vB) + b${condition} MterpCommonTakenBranchNoFlags + cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? + beq .L_check_not_taken_osr + FETCH_ADVANCE_INST 2 + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def zcmp(condition=""): + /* + * Generic one-operand compare-and-branch operation. Provide a "condition" + * fragment that specifies the comparison to perform. + * + * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez + */ + /* if-cmp vAA, +BBBB */ + mov r0, rINST, lsr #8 @ r0<- AA + GET_VREG r0, r0 @ r0<- vAA + FETCH_S rINST, 1 @ rINST<- branch offset, in code units + cmp r0, #0 @ compare (vA, 0) + b${condition} MterpCommonTakenBranchNoFlags + cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? + beq .L_check_not_taken_osr + FETCH_ADVANCE_INST 2 + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def op_goto(): + /* + * Unconditional branch, 8-bit offset. + * + * The branch distance is a signed code-unit offset, which we need to + * double to get a byte offset. + */ + /* goto +AA */ + sbfx rINST, rINST, #8, #8 @ rINST<- ssssssAA (sign-extended) + b MterpCommonTakenBranchNoFlags + +%def op_goto_16(): + /* + * Unconditional branch, 16-bit offset. + * + * The branch distance is a signed code-unit offset, which we need to + * double to get a byte offset. + */ + /* goto/16 +AAAA */ + FETCH_S rINST, 1 @ rINST<- ssssAAAA (sign-extended) + b MterpCommonTakenBranchNoFlags + +%def op_goto_32(): + /* + * Unconditional branch, 32-bit offset. + * + * The branch distance is a signed code-unit offset, which we need to + * double to get a byte offset. + * + * Unlike most opcodes, this one is allowed to branch to itself, so + * our "backward branch" test must be "<=0" instead of "<0". Because + * we need the V bit set, we'll use an adds to convert from Dalvik + * offset to byte offset. + */ + /* goto/32 +AAAAAAAA */ + FETCH r0, 1 @ r0<- aaaa (lo) + FETCH r3, 2 @ r1<- AAAA (hi) + orrs rINST, r0, r3, lsl #16 @ rINST<- AAAAaaaa + b MterpCommonTakenBranch + +%def op_if_eq(): +% bincmp(condition="eq") + +%def op_if_eqz(): +% zcmp(condition="eq") + +%def op_if_ge(): +% bincmp(condition="ge") + +%def op_if_gez(): +% zcmp(condition="ge") + +%def op_if_gt(): +% bincmp(condition="gt") + +%def op_if_gtz(): +% zcmp(condition="gt") + +%def op_if_le(): +% bincmp(condition="le") + +%def op_if_lez(): +% zcmp(condition="le") + +%def op_if_lt(): +% bincmp(condition="lt") + +%def op_if_ltz(): +% zcmp(condition="lt") + +%def op_if_ne(): +% bincmp(condition="ne") + +%def op_if_nez(): +% zcmp(condition="ne") + +%def op_packed_switch(func="MterpDoPackedSwitch"): + /* + * Handle a packed-switch or sparse-switch instruction. In both cases + * we decode it and hand it off to a helper function. + * + * We don't really expect backward branches in a switch statement, but + * they're perfectly legal, so we check for them here. + * + * for: packed-switch, sparse-switch + */ + /* op vAA, +BBBB */ + FETCH r0, 1 @ r0<- bbbb (lo) + FETCH r1, 2 @ r1<- BBBB (hi) + mov r3, rINST, lsr #8 @ r3<- AA + orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb + GET_VREG r1, r3 @ r1<- vAA + add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 + bl $func @ r0<- code-unit branch offset + movs rINST, r0 + b MterpCommonTakenBranch + +%def op_return(): + /* + * Return a 32-bit value. + * + * for: return, return-object + */ + /* op vAA */ + .extern MterpThreadFenceForConstructor + bl MterpThreadFenceForConstructor + ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] + mov r0, rSELF + ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST + blne MterpSuspendCheck @ (self) + mov r2, rINST, lsr #8 @ r2<- AA + GET_VREG r0, r2 @ r0<- vAA + mov r1, #0 + b MterpReturn + +%def op_return_object(): +% op_return() + +%def op_return_void(): + .extern MterpThreadFenceForConstructor + bl MterpThreadFenceForConstructor + ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] + mov r0, rSELF + ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST + blne MterpSuspendCheck @ (self) + mov r0, #0 + mov r1, #0 + b MterpReturn + +%def op_return_void_no_barrier(): + ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] + mov r0, rSELF + ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST + blne MterpSuspendCheck @ (self) + mov r0, #0 + mov r1, #0 + b MterpReturn + +%def op_return_wide(): + /* + * Return a 64-bit value. + */ + /* return-wide vAA */ + .extern MterpThreadFenceForConstructor + bl MterpThreadFenceForConstructor + ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] + mov r0, rSELF + ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST + blne MterpSuspendCheck @ (self) + mov r2, rINST, lsr #8 @ r2<- AA + VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[AA] + ldmia r2, {r0-r1} @ r0/r1 <- vAA/vAA+1 + b MterpReturn + +%def op_sparse_switch(): +% op_packed_switch(func="MterpDoSparseSwitch") + +%def op_throw(): + /* + * Throw an exception object in the current thread. + */ + /* throw vAA */ + EXPORT_PC + mov r2, rINST, lsr #8 @ r2<- AA + GET_VREG r1, r2 @ r1<- vAA (exception object) + cmp r1, #0 @ null object? + beq common_errNullObject @ yes, throw an NPE instead + str r1, [rSELF, #THREAD_EXCEPTION_OFFSET] @ thread->exception<- obj + b MterpException diff --git a/runtime/interpreter/mterp/arm/entry.S b/runtime/interpreter/mterp/arm/entry.S deleted file mode 100644 index d17802b705..0000000000 --- a/runtime/interpreter/mterp/arm/entry.S +++ /dev/null @@ -1,77 +0,0 @@ -%def entry(): -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -/* - * Interpreter entry point. - */ - - .text - .align 2 - -/* - * On entry: - * r0 Thread* self/ - * r1 insns_ - * r2 ShadowFrame - * r3 JValue* result_register - * - */ - -ENTRY ExecuteMterpImpl - stmfd sp!, {r3-r10,fp,lr} @ save 10 regs, (r3 just to align 64) - .cfi_adjust_cfa_offset 40 - .cfi_rel_offset r3, 0 - .cfi_rel_offset r4, 4 - .cfi_rel_offset r5, 8 - .cfi_rel_offset r6, 12 - .cfi_rel_offset r7, 16 - .cfi_rel_offset r8, 20 - .cfi_rel_offset r9, 24 - .cfi_rel_offset r10, 28 - .cfi_rel_offset fp, 32 - .cfi_rel_offset lr, 36 - - /* Remember the return register */ - str r3, [r2, #SHADOWFRAME_RESULT_REGISTER_OFFSET] - - /* Remember the dex instruction pointer */ - str r1, [r2, #SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET] - - /* set up "named" registers */ - mov rSELF, r0 - ldr r0, [r2, #SHADOWFRAME_NUMBER_OF_VREGS_OFFSET] - add rFP, r2, #SHADOWFRAME_VREGS_OFFSET @ point to vregs. - VREG_INDEX_TO_ADDR rREFS, r0 @ point to reference array in shadow frame - ldr r0, [r2, #SHADOWFRAME_DEX_PC_OFFSET] @ Get starting dex_pc. - add rPC, r1, r0, lsl #1 @ Create direct pointer to 1st dex opcode - CFI_DEFINE_DEX_PC_WITH_OFFSET(CFI_TMP, CFI_DEX, 0) - EXPORT_PC - - /* Starting ibase */ - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] - - /* Set up for backwards branches & osr profiling */ - ldr r0, [rFP, #OFF_FP_METHOD] - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rSELF - bl MterpSetUpHotnessCountdown - mov rPROFILE, r0 @ Starting hotness countdown to rPROFILE - - /* start executing the instruction at rPC */ - FETCH_INST @ load rINST from rPC - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - /* NOTE: no fallthrough */ diff --git a/runtime/interpreter/mterp/arm/fallback.S b/runtime/interpreter/mterp/arm/fallback.S deleted file mode 100644 index 3685700dec..0000000000 --- a/runtime/interpreter/mterp/arm/fallback.S +++ /dev/null @@ -1,4 +0,0 @@ -%def fallback(): -/* Transfer stub to alternate interpreter */ - b MterpFallback - diff --git a/runtime/interpreter/mterp/arm/fbinop.S b/runtime/interpreter/mterp/arm/fbinop.S deleted file mode 100644 index 0f75f89cbb..0000000000 --- a/runtime/interpreter/mterp/arm/fbinop.S +++ /dev/null @@ -1,24 +0,0 @@ -%def fbinop(instr=""): - /* - * Generic 32-bit floating-point operation. Provide an "instr" line that - * specifies an instruction that performs "s2 = s0 op s1". Because we - * use the "softfp" ABI, this must be an instruction, not a function call. - * - * For: add-float, sub-float, mul-float, div-float - */ - /* floatop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB - flds s1, [r3] @ s1<- vCC - flds s0, [r2] @ s0<- vBB - - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - $instr @ s2<- op - GET_INST_OPCODE ip @ extract opcode from rINST - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA - fsts s2, [r9] @ vAA<- s2 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/fbinop2addr.S b/runtime/interpreter/mterp/arm/fbinop2addr.S deleted file mode 100644 index a5162a13b2..0000000000 --- a/runtime/interpreter/mterp/arm/fbinop2addr.S +++ /dev/null @@ -1,20 +0,0 @@ -%def fbinop2addr(instr=""): - /* - * Generic 32-bit floating point "/2addr" binary operation. Provide - * an "instr" line that specifies an instruction that performs - * "s2 = s0 op s1". - * - * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr - */ - /* binop/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA - flds s1, [r3] @ s1<- vB - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - flds s0, [r9] @ s0<- vA - $instr @ s2<- op - GET_INST_OPCODE ip @ extract opcode from rINST - fsts s2, [r9] @ vAA<- s2 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/fbinopWide.S b/runtime/interpreter/mterp/arm/fbinopWide.S deleted file mode 100644 index e283feedd8..0000000000 --- a/runtime/interpreter/mterp/arm/fbinopWide.S +++ /dev/null @@ -1,24 +0,0 @@ -%def fbinopWide(instr=""): - /* - * Generic 64-bit double-precision floating point binary operation. - * Provide an "instr" line that specifies an instruction that performs - * "d2 = d0 op d1". - * - * for: add-double, sub-double, mul-double, div-double - */ - /* doubleop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB - fldd d1, [r3] @ d1<- vCC - fldd d0, [r2] @ d0<- vBB - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - $instr @ s2<- op - CLEAR_SHADOW_PAIR r9, ip, lr @ Zero shadow regs - GET_INST_OPCODE ip @ extract opcode from rINST - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA - fstd d2, [r9] @ vAA<- d2 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/fbinopWide2addr.S b/runtime/interpreter/mterp/arm/fbinopWide2addr.S deleted file mode 100644 index 639a7834f9..0000000000 --- a/runtime/interpreter/mterp/arm/fbinopWide2addr.S +++ /dev/null @@ -1,22 +0,0 @@ -%def fbinopWide2addr(instr=""): - /* - * Generic 64-bit floating point "/2addr" binary operation. Provide - * an "instr" line that specifies an instruction that performs - * "d2 = d0 op d1". - * - * For: add-double/2addr, sub-double/2addr, mul-double/2addr, - * div-double/2addr - */ - /* binop/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB - CLEAR_SHADOW_PAIR r9, ip, r0 @ Zero out shadow regs - fldd d1, [r3] @ d1<- vB - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - fldd d0, [r9] @ d0<- vA - $instr @ d2<- op - GET_INST_OPCODE ip @ extract opcode from rINST - fstd d2, [r9] @ vAA<- d2 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/field.S b/runtime/interpreter/mterp/arm/field.S deleted file mode 100644 index 82e1638fcd..0000000000 --- a/runtime/interpreter/mterp/arm/field.S +++ /dev/null @@ -1,16 +0,0 @@ -%def field(helper=""): - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern $helper - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl $helper - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/floating_point.S b/runtime/interpreter/mterp/arm/floating_point.S new file mode 100644 index 0000000000..583010acc1 --- /dev/null +++ b/runtime/interpreter/mterp/arm/floating_point.S @@ -0,0 +1,482 @@ +%def fbinop(instr=""): + /* + * Generic 32-bit floating-point operation. Provide an "instr" line that + * specifies an instruction that performs "s2 = s0 op s1". Because we + * use the "softfp" ABI, this must be an instruction, not a function call. + * + * For: add-float, sub-float, mul-float, div-float + */ + /* floatop vAA, vBB, vCC */ + FETCH r0, 1 @ r0<- CCBB + mov r9, rINST, lsr #8 @ r9<- AA + mov r3, r0, lsr #8 @ r3<- CC + and r2, r0, #255 @ r2<- BB + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC + VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB + flds s1, [r3] @ s1<- vCC + flds s0, [r2] @ s0<- vBB + + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + $instr @ s2<- op + GET_INST_OPCODE ip @ extract opcode from rINST + VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA + fsts s2, [r9] @ vAA<- s2 + GOTO_OPCODE ip @ jump to next instruction + +%def fbinop2addr(instr=""): + /* + * Generic 32-bit floating point "/2addr" binary operation. Provide + * an "instr" line that specifies an instruction that performs + * "s2 = s0 op s1". + * + * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr + */ + /* binop/2addr vA, vB */ + mov r3, rINST, lsr #12 @ r3<- B + ubfx r9, rINST, #8, #4 @ r9<- A + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB + VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA + flds s1, [r3] @ s1<- vB + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + flds s0, [r9] @ s0<- vA + $instr @ s2<- op + GET_INST_OPCODE ip @ extract opcode from rINST + fsts s2, [r9] @ vAA<- s2 + GOTO_OPCODE ip @ jump to next instruction + +%def fbinopWide(instr=""): + /* + * Generic 64-bit double-precision floating point binary operation. + * Provide an "instr" line that specifies an instruction that performs + * "d2 = d0 op d1". + * + * for: add-double, sub-double, mul-double, div-double + */ + /* doubleop vAA, vBB, vCC */ + FETCH r0, 1 @ r0<- CCBB + mov r9, rINST, lsr #8 @ r9<- AA + mov r3, r0, lsr #8 @ r3<- CC + and r2, r0, #255 @ r2<- BB + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC + VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB + fldd d1, [r3] @ d1<- vCC + fldd d0, [r2] @ d0<- vBB + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + $instr @ s2<- op + CLEAR_SHADOW_PAIR r9, ip, lr @ Zero shadow regs + GET_INST_OPCODE ip @ extract opcode from rINST + VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA + fstd d2, [r9] @ vAA<- d2 + GOTO_OPCODE ip @ jump to next instruction + +%def fbinopWide2addr(instr=""): + /* + * Generic 64-bit floating point "/2addr" binary operation. Provide + * an "instr" line that specifies an instruction that performs + * "d2 = d0 op d1". + * + * For: add-double/2addr, sub-double/2addr, mul-double/2addr, + * div-double/2addr + */ + /* binop/2addr vA, vB */ + mov r3, rINST, lsr #12 @ r3<- B + ubfx r9, rINST, #8, #4 @ r9<- A + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB + CLEAR_SHADOW_PAIR r9, ip, r0 @ Zero out shadow regs + fldd d1, [r3] @ d1<- vB + VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + fldd d0, [r9] @ d0<- vA + $instr @ d2<- op + GET_INST_OPCODE ip @ extract opcode from rINST + fstd d2, [r9] @ vAA<- d2 + GOTO_OPCODE ip @ jump to next instruction + +%def funop(instr=""): + /* + * Generic 32-bit unary floating-point operation. Provide an "instr" + * line that specifies an instruction that performs "s1 = op s0". + * + * for: int-to-float, float-to-int + */ + /* unop vA, vB */ + mov r3, rINST, lsr #12 @ r3<- B + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB + flds s0, [r3] @ s0<- vB + ubfx r9, rINST, #8, #4 @ r9<- A + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + $instr @ s1<- op + GET_INST_OPCODE ip @ extract opcode from rINST + VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA + fsts s1, [r9] @ vA<- s1 + GOTO_OPCODE ip @ jump to next instruction + +%def funopNarrower(instr=""): + /* + * Generic 64bit-to-32bit unary floating point operation. Provide an + * "instr" line that specifies an instruction that performs "s0 = op d0". + * + * For: double-to-int, double-to-float + */ + /* unop vA, vB */ + mov r3, rINST, lsr #12 @ r3<- B + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB + fldd d0, [r3] @ d0<- vB + ubfx r9, rINST, #8, #4 @ r9<- A + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + $instr @ s0<- op + GET_INST_OPCODE ip @ extract opcode from rINST + VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA + fsts s0, [r9] @ vA<- s0 + GOTO_OPCODE ip @ jump to next instruction + +%def funopWider(instr=""): + /* + * Generic 32bit-to-64bit floating point unary operation. Provide an + * "instr" line that specifies an instruction that performs "d0 = op s0". + * + * For: int-to-double, float-to-double + */ + /* unop vA, vB */ + mov r3, rINST, lsr #12 @ r3<- B + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB + flds s0, [r3] @ s0<- vB + ubfx r9, rINST, #8, #4 @ r9<- A + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + $instr @ d0<- op + CLEAR_SHADOW_PAIR r9, ip, lr @ Zero shadow regs + GET_INST_OPCODE ip @ extract opcode from rINST + VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA + fstd d0, [r9] @ vA<- d0 + GOTO_OPCODE ip @ jump to next instruction + +%def op_add_double(): +% fbinopWide(instr="faddd d2, d0, d1") + +%def op_add_double_2addr(): +% fbinopWide2addr(instr="faddd d2, d0, d1") + +%def op_add_float(): +% fbinop(instr="fadds s2, s0, s1") + +%def op_add_float_2addr(): +% fbinop2addr(instr="fadds s2, s0, s1") + +%def op_cmpg_double(): + /* + * Compare two floating-point values. Puts 0, 1, or -1 into the + * destination register based on the results of the comparison. + * + * int compare(x, y) { + * if (x == y) { + * return 0; + * } else if (x < y) { + * return -1; + * } else if (x > y) { + * return 1; + * } else { + * return 1; + * } + * } + */ + /* op vAA, vBB, vCC */ + FETCH r0, 1 @ r0<- CCBB + mov r9, rINST, lsr #8 @ r9<- AA + and r2, r0, #255 @ r2<- BB + mov r3, r0, lsr #8 @ r3<- CC + VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC + fldd d0, [r2] @ d0<- vBB + fldd d1, [r3] @ d1<- vCC + vcmpe.f64 d0, d1 @ compare (vBB, vCC) + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + mov r0, #1 @ r0<- 1 (default) + GET_INST_OPCODE ip @ extract opcode from rINST + fmstat @ export status flags + mvnmi r0, #0 @ (less than) r1<- -1 + moveq r0, #0 @ (equal) r1<- 0 + SET_VREG r0, r9 @ vAA<- r0 + GOTO_OPCODE ip @ jump to next instruction + +%def op_cmpg_float(): + /* + * Compare two floating-point values. Puts 0, 1, or -1 into the + * destination register based on the results of the comparison. + * + * int compare(x, y) { + * if (x == y) { + * return 0; + * } else if (x < y) { + * return -1; + * } else if (x > y) { + * return 1; + * } else { + * return 1; + * } + * } + */ + /* op vAA, vBB, vCC */ + FETCH r0, 1 @ r0<- CCBB + mov r9, rINST, lsr #8 @ r9<- AA + and r2, r0, #255 @ r2<- BB + mov r3, r0, lsr #8 @ r3<- CC + VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC + flds s0, [r2] @ s0<- vBB + flds s1, [r3] @ s1<- vCC + vcmpe.f32 s0, s1 @ compare (vBB, vCC) + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + mov r0, #1 @ r0<- 1 (default) + GET_INST_OPCODE ip @ extract opcode from rINST + fmstat @ export status flags + mvnmi r0, #0 @ (less than) r1<- -1 + moveq r0, #0 @ (equal) r1<- 0 + SET_VREG r0, r9 @ vAA<- r0 + GOTO_OPCODE ip @ jump to next instruction + +%def op_cmpl_double(): + /* + * Compare two floating-point values. Puts 0, 1, or -1 into the + * destination register based on the results of the comparison. + * + * int compare(x, y) { + * if (x == y) { + * return 0; + * } else if (x > y) { + * return 1; + * } else if (x < y) { + * return -1; + * } else { + * return -1; + * } + * } + */ + /* op vAA, vBB, vCC */ + FETCH r0, 1 @ r0<- CCBB + mov r9, rINST, lsr #8 @ r9<- AA + and r2, r0, #255 @ r2<- BB + mov r3, r0, lsr #8 @ r3<- CC + VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC + fldd d0, [r2] @ d0<- vBB + fldd d1, [r3] @ d1<- vCC + vcmpe.f64 d0, d1 @ compare (vBB, vCC) + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + mvn r0, #0 @ r0<- -1 (default) + GET_INST_OPCODE ip @ extract opcode from rINST + fmstat @ export status flags + movgt r0, #1 @ (greater than) r1<- 1 + moveq r0, #0 @ (equal) r1<- 0 + SET_VREG r0, r9 @ vAA<- r0 + GOTO_OPCODE ip @ jump to next instruction + +%def op_cmpl_float(): + /* + * Compare two floating-point values. Puts 0, 1, or -1 into the + * destination register based on the results of the comparison. + * + * int compare(x, y) { + * if (x == y) { + * return 0; + * } else if (x > y) { + * return 1; + * } else if (x < y) { + * return -1; + * } else { + * return -1; + * } + * } + */ + /* op vAA, vBB, vCC */ + FETCH r0, 1 @ r0<- CCBB + mov r9, rINST, lsr #8 @ r9<- AA + and r2, r0, #255 @ r2<- BB + mov r3, r0, lsr #8 @ r3<- CC + VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC + flds s0, [r2] @ s0<- vBB + flds s1, [r3] @ s1<- vCC + vcmpe.f32 s0, s1 @ compare (vBB, vCC) + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + mvn r0, #0 @ r0<- -1 (default) + GET_INST_OPCODE ip @ extract opcode from rINST + fmstat @ export status flags + movgt r0, #1 @ (greater than) r1<- 1 + moveq r0, #0 @ (equal) r1<- 0 + SET_VREG r0, r9 @ vAA<- r0 + GOTO_OPCODE ip @ jump to next instruction + +%def op_div_double(): +% fbinopWide(instr="fdivd d2, d0, d1") + +%def op_div_double_2addr(): +% fbinopWide2addr(instr="fdivd d2, d0, d1") + +%def op_div_float(): +% fbinop(instr="fdivs s2, s0, s1") + +%def op_div_float_2addr(): +% fbinop2addr(instr="fdivs s2, s0, s1") + +%def op_double_to_float(): +% funopNarrower(instr="vcvt.f32.f64 s0, d0") + +%def op_double_to_int(): +% funopNarrower(instr="ftosizd s0, d0") + +%def op_double_to_long(): +% unopWide(instr="bl d2l_doconv") + +%def op_double_to_long_sister_code(): +/* + * Convert the double in r0/r1 to a long in r0/r1. + * + * We have to clip values to long min/max per the specification. The + * expected common case is a "reasonable" value that converts directly + * to modest integer. The EABI convert function isn't doing this for us. + */ +d2l_doconv: + ubfx r2, r1, #20, #11 @ grab the exponent + movw r3, #0x43e + cmp r2, r3 @ MINLONG < x > MAXLONG? + bhs d2l_special_cases + b __aeabi_d2lz @ tail call to convert double to long +d2l_special_cases: + movw r3, #0x7ff + cmp r2, r3 + beq d2l_maybeNaN @ NaN? +d2l_notNaN: + adds r1, r1, r1 @ sign bit to carry + mov r0, #0xffffffff @ assume maxlong for lsw + mov r1, #0x7fffffff @ assume maxlong for msw + adc r0, r0, #0 + adc r1, r1, #0 @ convert maxlong to minlong if exp negative + bx lr @ return +d2l_maybeNaN: + orrs r3, r0, r1, lsl #12 + beq d2l_notNaN @ if fraction is non-zero, it's a NaN + mov r0, #0 + mov r1, #0 + bx lr @ return 0 for NaN + +%def op_float_to_double(): +% funopWider(instr="vcvt.f64.f32 d0, s0") + +%def op_float_to_int(): +% funop(instr="ftosizs s1, s0") + +%def op_float_to_long(): +% unopWider(instr="bl f2l_doconv") + +%def op_float_to_long_sister_code(): +/* + * Convert the float in r0 to a long in r0/r1. + * + * We have to clip values to long min/max per the specification. The + * expected common case is a "reasonable" value that converts directly + * to modest integer. The EABI convert function isn't doing this for us. + */ +f2l_doconv: + ubfx r2, r0, #23, #8 @ grab the exponent + cmp r2, #0xbe @ MININT < x > MAXINT? + bhs f2l_special_cases + b __aeabi_f2lz @ tail call to convert float to long +f2l_special_cases: + cmp r2, #0xff @ NaN or infinity? + beq f2l_maybeNaN +f2l_notNaN: + adds r0, r0, r0 @ sign bit to carry + mov r0, #0xffffffff @ assume maxlong for lsw + mov r1, #0x7fffffff @ assume maxlong for msw + adc r0, r0, #0 + adc r1, r1, #0 @ convert maxlong to minlong if exp negative + bx lr @ return +f2l_maybeNaN: + lsls r3, r0, #9 + beq f2l_notNaN @ if fraction is non-zero, it's a NaN + mov r0, #0 + mov r1, #0 + bx lr @ return 0 for NaN + +%def op_int_to_double(): +% funopWider(instr="fsitod d0, s0") + +%def op_int_to_float(): +% funop(instr="fsitos s1, s0") + +%def op_long_to_double(): + /* + * Specialised 64-bit floating point operation. + * + * Note: The result will be returned in d2. + * + * For: long-to-double + */ + mov r3, rINST, lsr #12 @ r3<- B + ubfx r9, rINST, #8, #4 @ r9<- A + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] + VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[A] + vldr d0, [r3] @ d0<- vAA + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + + vcvt.f64.s32 d1, s1 @ d1<- (double)(vAAh) + vcvt.f64.u32 d2, s0 @ d2<- (double)(vAAl) + vldr d3, constval$opcode + vmla.f64 d2, d1, d3 @ d2<- vAAh*2^32 + vAAl + + GET_INST_OPCODE ip @ extract opcode from rINST + vstr.64 d2, [r9] @ vAA<- d2 + GOTO_OPCODE ip @ jump to next instruction + + /* literal pool helper */ +constval${opcode}: + .8byte 0x41f0000000000000 + +%def op_long_to_float(): +% unopNarrower(instr="bl __aeabi_l2f") + +%def op_mul_double(): +% fbinopWide(instr="fmuld d2, d0, d1") + +%def op_mul_double_2addr(): +% fbinopWide2addr(instr="fmuld d2, d0, d1") + +%def op_mul_float(): +% fbinop(instr="fmuls s2, s0, s1") + +%def op_mul_float_2addr(): +% fbinop2addr(instr="fmuls s2, s0, s1") + +%def op_neg_double(): +% unopWide(instr="add r1, r1, #0x80000000") + +%def op_neg_float(): +% unop(instr="add r0, r0, #0x80000000") + +%def op_rem_double(): +/* EABI doesn't define a double remainder function, but libm does */ +% binopWide(instr="bl fmod") + +%def op_rem_double_2addr(): +/* EABI doesn't define a double remainder function, but libm does */ +% binopWide2addr(instr="bl fmod") + +%def op_rem_float(): +/* EABI doesn't define a float remainder function, but libm does */ +% binop(instr="bl fmodf") + +%def op_rem_float_2addr(): +/* EABI doesn't define a float remainder function, but libm does */ +% binop2addr(instr="bl fmodf") + +%def op_sub_double(): +% fbinopWide(instr="fsubd d2, d0, d1") + +%def op_sub_double_2addr(): +% fbinopWide2addr(instr="fsubd d2, d0, d1") + +%def op_sub_float(): +% fbinop(instr="fsubs s2, s0, s1") + +%def op_sub_float_2addr(): +% fbinop2addr(instr="fsubs s2, s0, s1") diff --git a/runtime/interpreter/mterp/arm/footer.S b/runtime/interpreter/mterp/arm/footer.S deleted file mode 100644 index 275584e4ea..0000000000 --- a/runtime/interpreter/mterp/arm/footer.S +++ /dev/null @@ -1,298 +0,0 @@ -%def footer(): -/* - * =========================================================================== - * Common subroutines and data - * =========================================================================== - */ - - .text - .align 2 - -/* - * We've detected a condition that will result in an exception, but the exception - * has not yet been thrown. Just bail out to the reference interpreter to deal with it. - * TUNING: for consistency, we may want to just go ahead and handle these here. - */ -common_errDivideByZero: - EXPORT_PC -#if MTERP_LOGGING - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - bl MterpLogDivideByZeroException -#endif - b MterpCommonFallback - -common_errArrayIndex: - EXPORT_PC -#if MTERP_LOGGING - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - bl MterpLogArrayIndexException -#endif - b MterpCommonFallback - -common_errNegativeArraySize: - EXPORT_PC -#if MTERP_LOGGING - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - bl MterpLogNegativeArraySizeException -#endif - b MterpCommonFallback - -common_errNoSuchMethod: - EXPORT_PC -#if MTERP_LOGGING - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - bl MterpLogNoSuchMethodException -#endif - b MterpCommonFallback - -common_errNullObject: - EXPORT_PC -#if MTERP_LOGGING - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - bl MterpLogNullObjectException -#endif - b MterpCommonFallback - -common_exceptionThrown: - EXPORT_PC -#if MTERP_LOGGING - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - bl MterpLogExceptionThrownException -#endif - b MterpCommonFallback - -MterpSuspendFallback: - EXPORT_PC -#if MTERP_LOGGING - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - ldr r2, [rSELF, #THREAD_FLAGS_OFFSET] - bl MterpLogSuspendFallback -#endif - b MterpCommonFallback - -/* - * If we're here, something is out of the ordinary. If there is a pending - * exception, handle it. Otherwise, roll back and retry with the reference - * interpreter. - */ -MterpPossibleException: - ldr r0, [rSELF, #THREAD_EXCEPTION_OFFSET] - cmp r0, #0 @ Exception pending? - beq MterpFallback @ If not, fall back to reference interpreter. - /* intentional fallthrough - handle pending exception. */ -/* - * On return from a runtime helper routine, we've found a pending exception. - * Can we handle it here - or need to bail out to caller? - * - */ -MterpException: - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - bl MterpHandleException @ (self, shadow_frame) - cmp r0, #0 - beq MterpExceptionReturn @ no local catch, back to caller. - ldr r0, [rFP, #OFF_FP_DEX_INSTRUCTIONS] - ldr r1, [rFP, #OFF_FP_DEX_PC] - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] - add rPC, r0, r1, lsl #1 @ generate new dex_pc_ptr - /* Do we need to switch interpreters? */ - bl MterpShouldSwitchInterpreters - cmp r0, #0 - bne MterpFallback - /* resume execution at catch block */ - EXPORT_PC - FETCH_INST - GET_INST_OPCODE ip - GOTO_OPCODE ip - /* NOTE: no fallthrough */ - -/* - * Common handling for branches with support for Jit profiling. - * On entry: - * rINST <= signed offset - * rPROFILE <= signed hotness countdown (expanded to 32 bits) - * condition bits <= set to establish sign of offset (use "NoFlags" entry if not) - * - * We have quite a few different cases for branch profiling, OSR detection and - * suspend check support here. - * - * Taken backward branches: - * If profiling active, do hotness countdown and report if we hit zero. - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * Is there a pending suspend request? If so, suspend. - * - * Taken forward branches and not-taken backward branches: - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * - * Our most common case is expected to be a taken backward branch with active jit profiling, - * but no full OSR check and no pending suspend request. - * Next most common case is not-taken branch with no full OSR check. - * - */ -MterpCommonTakenBranchNoFlags: - cmp rINST, #0 -MterpCommonTakenBranch: - bgt .L_forward_branch @ don't add forward branches to hotness -/* - * We need to subtract 1 from positive values and we should not see 0 here, - * so we may use the result of the comparison with -1. - */ -#if JIT_CHECK_OSR != -1 -# error "JIT_CHECK_OSR must be -1." -#endif - cmp rPROFILE, #JIT_CHECK_OSR - beq .L_osr_check - subsgt rPROFILE, #1 - beq .L_add_batch @ counted down to zero - report -.L_resume_backward_branch: - ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] - REFRESH_IBASE - add r2, rINST, rINST @ r2<- byte offset - FETCH_ADVANCE_INST_RB r2 @ update rPC, load rINST - ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - bne .L_suspend_request_pending - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -.L_suspend_request_pending: - EXPORT_PC - mov r0, rSELF - bl MterpSuspendCheck @ (self) - cmp r0, #0 - bne MterpFallback - REFRESH_IBASE @ might have changed during suspend - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -.L_no_count_backwards: - cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? - bne .L_resume_backward_branch -.L_osr_check: - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rINST - EXPORT_PC - bl MterpMaybeDoOnStackReplacement @ (self, shadow_frame, offset) - cmp r0, #0 - bne MterpOnStackReplacement - b .L_resume_backward_branch - -.L_forward_branch: - cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? - beq .L_check_osr_forward -.L_resume_forward_branch: - add r2, rINST, rINST @ r2<- byte offset - FETCH_ADVANCE_INST_RB r2 @ update rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -.L_check_osr_forward: - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rINST - EXPORT_PC - bl MterpMaybeDoOnStackReplacement @ (self, shadow_frame, offset) - cmp r0, #0 - bne MterpOnStackReplacement - b .L_resume_forward_branch - -.L_add_batch: - add r1, rFP, #OFF_FP_SHADOWFRAME - strh rPROFILE, [r1, #SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET] - ldr r0, [rFP, #OFF_FP_METHOD] - mov r2, rSELF - bl MterpAddHotnessBatch @ (method, shadow_frame, self) - mov rPROFILE, r0 @ restore new hotness countdown to rPROFILE - b .L_no_count_backwards - -/* - * Entered from the conditional branch handlers when OSR check request active on - * not-taken path. All Dalvik not-taken conditional branch offsets are 2. - */ -.L_check_not_taken_osr: - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, #2 - EXPORT_PC - bl MterpMaybeDoOnStackReplacement @ (self, shadow_frame, offset) - cmp r0, #0 - bne MterpOnStackReplacement - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* - * On-stack replacement has happened, and now we've returned from the compiled method. - */ -MterpOnStackReplacement: -#if MTERP_LOGGING - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rINST - bl MterpLogOSR -#endif - mov r0, #1 @ Signal normal return - b MterpDone - -/* - * Bail out to reference interpreter. - */ -MterpFallback: - EXPORT_PC -#if MTERP_LOGGING - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - bl MterpLogFallback -#endif -MterpCommonFallback: - mov r0, #0 @ signal retry with reference interpreter. - b MterpDone - -/* - * We pushed some registers on the stack in ExecuteMterpImpl, then saved - * SP and LR. Here we restore SP, restore the registers, and then restore - * LR to PC. - * - * On entry: - * uint32_t* rFP (should still be live, pointer to base of vregs) - */ -MterpExceptionReturn: - mov r0, #1 @ signal return to caller. - b MterpDone -MterpReturn: - ldr r2, [rFP, #OFF_FP_RESULT_REGISTER] - str r0, [r2] - str r1, [r2, #4] - mov r0, #1 @ signal return to caller. -MterpDone: -/* - * At this point, we expect rPROFILE to be non-zero. If negative, hotness is disabled or we're - * checking for OSR. If greater than zero, we might have unreported hotness to register - * (the difference between the ending rPROFILE and the cached hotness counter). rPROFILE - * should only reach zero immediately after a hotness decrement, and is then reset to either - * a negative special state or the new non-zero countdown value. - */ - cmp rPROFILE, #0 - bgt MterpProfileActive @ if > 0, we may have some counts to report. - ldmfd sp!, {r3-r10,fp,pc} @ restore 10 regs and return - -MterpProfileActive: - mov rINST, r0 @ stash return value - /* Report cached hotness counts */ - ldr r0, [rFP, #OFF_FP_METHOD] - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rSELF - strh rPROFILE, [r1, #SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET] - bl MterpAddHotnessBatch @ (method, shadow_frame, self) - mov r0, rINST @ restore return value - ldmfd sp!, {r3-r10,fp,pc} @ restore 10 regs and return - - END ExecuteMterpImpl - diff --git a/runtime/interpreter/mterp/arm/funop.S b/runtime/interpreter/mterp/arm/funop.S deleted file mode 100644 index c4f2231938..0000000000 --- a/runtime/interpreter/mterp/arm/funop.S +++ /dev/null @@ -1,18 +0,0 @@ -%def funop(instr=""): - /* - * Generic 32-bit unary floating-point operation. Provide an "instr" - * line that specifies an instruction that performs "s1 = op s0". - * - * for: int-to-float, float-to-int - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB - flds s0, [r3] @ s0<- vB - ubfx r9, rINST, #8, #4 @ r9<- A - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - $instr @ s1<- op - GET_INST_OPCODE ip @ extract opcode from rINST - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA - fsts s1, [r9] @ vA<- s1 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/funopNarrower.S b/runtime/interpreter/mterp/arm/funopNarrower.S deleted file mode 100644 index ce5e82ca89..0000000000 --- a/runtime/interpreter/mterp/arm/funopNarrower.S +++ /dev/null @@ -1,18 +0,0 @@ -%def funopNarrower(instr=""): - /* - * Generic 64bit-to-32bit unary floating point operation. Provide an - * "instr" line that specifies an instruction that performs "s0 = op d0". - * - * For: double-to-int, double-to-float - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB - fldd d0, [r3] @ d0<- vB - ubfx r9, rINST, #8, #4 @ r9<- A - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - $instr @ s0<- op - GET_INST_OPCODE ip @ extract opcode from rINST - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA - fsts s0, [r9] @ vA<- s0 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/funopWider.S b/runtime/interpreter/mterp/arm/funopWider.S deleted file mode 100644 index 8df362f250..0000000000 --- a/runtime/interpreter/mterp/arm/funopWider.S +++ /dev/null @@ -1,19 +0,0 @@ -%def funopWider(instr=""): - /* - * Generic 32bit-to-64bit floating point unary operation. Provide an - * "instr" line that specifies an instruction that performs "d0 = op s0". - * - * For: int-to-double, float-to-double - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB - flds s0, [r3] @ s0<- vB - ubfx r9, rINST, #8, #4 @ r9<- A - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - $instr @ d0<- op - CLEAR_SHADOW_PAIR r9, ip, lr @ Zero shadow regs - GET_INST_OPCODE ip @ extract opcode from rINST - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA - fstd d0, [r9] @ vA<- d0 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/header.S b/runtime/interpreter/mterp/arm/header.S deleted file mode 100644 index 03f330a4e9..0000000000 --- a/runtime/interpreter/mterp/arm/header.S +++ /dev/null @@ -1,313 +0,0 @@ -%def header(): -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - Art assembly interpreter notes: - - First validate assembly code by implementing ExecuteXXXImpl() style body (doesn't - handle invoke, allows higher-level code to create frame & shadow frame. - - Once that's working, support direct entry code & eliminate shadow frame (and - excess locals allocation. - - Some (hopefully) temporary ugliness. We'll treat rFP as pointing to the - base of the vreg array within the shadow frame. Access the other fields, - dex_pc_, method_ and number_of_vregs_ via negative offsets. For now, we'll continue - the shadow frame mechanism of double-storing object references - via rFP & - number_of_vregs_. - - */ - -/* -ARM EABI general notes: - -r0-r3 hold first 4 args to a method; they are not preserved across method calls -r4-r8 are available for general use -r9 is given special treatment in some situations, but not for us -r10 (sl) seems to be generally available -r11 (fp) is used by gcc (unless -fomit-frame-pointer is set) -r12 (ip) is scratch -- not preserved across method calls -r13 (sp) should be managed carefully in case a signal arrives -r14 (lr) must be preserved -r15 (pc) can be tinkered with directly - -r0 holds returns of <= 4 bytes -r0-r1 hold returns of 8 bytes, low word in r0 - -Callee must save/restore r4+ (except r12) if it modifies them. If VFP -is present, registers s16-s31 (a/k/a d8-d15, a/k/a q4-q7) must be preserved, -s0-s15 (d0-d7, q0-a3) do not need to be. - -Stack is "full descending". Only the arguments that don't fit in the first 4 -registers are placed on the stack. "sp" points at the first stacked argument -(i.e. the 5th arg). - -VFP: single-precision results in s0, double-precision results in d0. - -In the EABI, "sp" must be 64-bit aligned on entry to a function, and any -64-bit quantities (long long, double) must be 64-bit aligned. -*/ - -/* -Mterp and ARM notes: - -The following registers have fixed assignments: - - reg nick purpose - r4 rPC interpreted program counter, used for fetching instructions - r5 rFP interpreted frame pointer, used for accessing locals and args - r6 rSELF self (Thread) pointer - r7 rINST first 16-bit code unit of current instruction - r8 rIBASE interpreted instruction base pointer, used for computed goto - r10 rPROFILE branch profiling countdown - r11 rREFS base of object references in shadow frame (ideally, we'll get rid of this later). - -Macros are provided for common operations. Each macro MUST emit only -one instruction to make instruction-counting easier. They MUST NOT alter -unspecified registers or condition codes. -*/ - -/* - * This is a #include, not a %include, because we want the C pre-processor - * to expand the macros into assembler assignment statements. - */ -#include "asm_support.h" -#include "interpreter/cfi_asm_support.h" - -#define MTERP_PROFILE_BRANCHES 1 -#define MTERP_LOGGING 0 - -/* During bringup, we'll use the shadow frame model instead of rFP */ -/* single-purpose registers, given names for clarity */ -#define rPC r4 -#define CFI_DEX 4 // DWARF register number of the register holding dex-pc (xPC). -#define CFI_TMP 0 // DWARF register number of the first argument register (r0). -#define rFP r5 -#define rSELF r6 -#define rINST r7 -#define rIBASE r8 -#define rPROFILE r10 -#define rREFS r11 - -/* - * Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs. So, - * to access other shadow frame fields, we need to use a backwards offset. Define those here. - */ -#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) -#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) -#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) -#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) -#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) -#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) -#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) -#define OFF_FP_DEX_INSTRUCTIONS OFF_FP(SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET) -#define OFF_FP_SHADOWFRAME OFF_FP(0) - -/* - * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must - * be done *before* something throws. - * - * It's okay to do this more than once. - * - * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped - * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction - * offset into the code_items_[] array. For effiency, we will "export" the - * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC - * to convert to a dex pc when needed. - */ -.macro EXPORT_PC - str rPC, [rFP, #OFF_FP_DEX_PC_PTR] -.endm - -.macro EXPORT_DEX_PC tmp - ldr \tmp, [rFP, #OFF_FP_DEX_INSTRUCTIONS] - str rPC, [rFP, #OFF_FP_DEX_PC_PTR] - sub \tmp, rPC, \tmp - asr \tmp, #1 - str \tmp, [rFP, #OFF_FP_DEX_PC] -.endm - -/* - * Fetch the next instruction from rPC into rINST. Does not advance rPC. - */ -.macro FETCH_INST - ldrh rINST, [rPC] -.endm - -/* - * Fetch the next instruction from the specified offset. Advances rPC - * to point to the next instruction. "_count" is in 16-bit code units. - * - * Because of the limited size of immediate constants on ARM, this is only - * suitable for small forward movements (i.e. don't try to implement "goto" - * with this). - * - * This must come AFTER anything that can throw an exception, or the - * exception catch may miss. (This also implies that it must come after - * EXPORT_PC.) - */ -.macro FETCH_ADVANCE_INST count - ldrh rINST, [rPC, #((\count)*2)]! -.endm - -/* - * The operation performed here is similar to FETCH_ADVANCE_INST, except the - * src and dest registers are parameterized (not hard-wired to rPC and rINST). - */ -.macro PREFETCH_ADVANCE_INST dreg, sreg, count - ldrh \dreg, [\sreg, #((\count)*2)]! -.endm - -/* - * Similar to FETCH_ADVANCE_INST, but does not update rPC. Used to load - * rINST ahead of possible exception point. Be sure to manually advance rPC - * later. - */ -.macro PREFETCH_INST count - ldrh rINST, [rPC, #((\count)*2)] -.endm - -/* Advance rPC by some number of code units. */ -.macro ADVANCE count - add rPC, #((\count)*2) -.endm - -/* - * Fetch the next instruction from an offset specified by _reg. Updates - * rPC to point to the next instruction. "_reg" must specify the distance - * in bytes, *not* 16-bit code units, and may be a signed value. - * - * We want to write "ldrh rINST, [rPC, _reg, lsl #1]!", but some of the - * bits that hold the shift distance are used for the half/byte/sign flags. - * In some cases we can pre-double _reg for free, so we require a byte offset - * here. - */ -.macro FETCH_ADVANCE_INST_RB reg - ldrh rINST, [rPC, \reg]! -.endm - -/* - * Fetch a half-word code unit from an offset past the current PC. The - * "_count" value is in 16-bit code units. Does not advance rPC. - * - * The "_S" variant works the same but treats the value as signed. - */ -.macro FETCH reg, count - ldrh \reg, [rPC, #((\count)*2)] -.endm - -.macro FETCH_S reg, count - ldrsh \reg, [rPC, #((\count)*2)] -.endm - -/* - * Fetch one byte from an offset past the current PC. Pass in the same - * "_count" as you would for FETCH, and an additional 0/1 indicating which - * byte of the halfword you want (lo/hi). - */ -.macro FETCH_B reg, count, byte - ldrb \reg, [rPC, #((\count)*2+(\byte))] -.endm - -/* - * Put the instruction's opcode field into the specified register. - */ -.macro GET_INST_OPCODE reg - and \reg, rINST, #255 -.endm - -/* - * Put the prefetched instruction's opcode field into the specified register. - */ -.macro GET_PREFETCHED_OPCODE oreg, ireg - and \oreg, \ireg, #255 -.endm - -/* - * Begin executing the opcode in _reg. Because this only jumps within the - * interpreter, we don't have to worry about pre-ARMv5 THUMB interwork. - */ -.macro GOTO_OPCODE reg - add pc, rIBASE, \reg, lsl #${handler_size_bits} -.endm -.macro GOTO_OPCODE_BASE base,reg - add pc, \base, \reg, lsl #${handler_size_bits} -.endm - -/* - * Get/set the 32-bit value from a Dalvik register. - */ -.macro GET_VREG reg, vreg - ldr \reg, [rFP, \vreg, lsl #2] -.endm -.macro SET_VREG reg, vreg - str \reg, [rFP, \vreg, lsl #2] - mov \reg, #0 - str \reg, [rREFS, \vreg, lsl #2] -.endm -.macro SET_VREG_OBJECT reg, vreg, tmpreg - str \reg, [rFP, \vreg, lsl #2] - str \reg, [rREFS, \vreg, lsl #2] -.endm -.macro SET_VREG_SHADOW reg, vreg - str \reg, [rREFS, \vreg, lsl #2] -.endm - -/* - * Clear the corresponding shadow regs for a vreg pair - */ -.macro CLEAR_SHADOW_PAIR vreg, tmp1, tmp2 - mov \tmp1, #0 - add \tmp2, \vreg, #1 - SET_VREG_SHADOW \tmp1, \vreg - SET_VREG_SHADOW \tmp1, \tmp2 -.endm - -/* - * Convert a virtual register index into an address. - */ -.macro VREG_INDEX_TO_ADDR reg, vreg - add \reg, rFP, \vreg, lsl #2 /* WARNING/FIXME: handle shadow frame vreg zero if store */ -.endm - -/* - * Refresh handler table. - */ -.macro REFRESH_IBASE - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] -.endm - -/* - * cfi support macros. - */ -.macro ENTRY name - .arm - .type \name, #function - .hidden \name // Hide this as a global symbol, so we do not incur plt calls. - .global \name - /* Cache alignment for function entry */ - .balign 16 -\name: - .cfi_startproc - .fnstart -.endm - -.macro END name - .fnend - .cfi_endproc - .size \name, .-\name -.endm diff --git a/runtime/interpreter/mterp/arm/instruction_end.S b/runtime/interpreter/mterp/arm/instruction_end.S deleted file mode 100644 index cf30a9b0b0..0000000000 --- a/runtime/interpreter/mterp/arm/instruction_end.S +++ /dev/null @@ -1,6 +0,0 @@ -%def instruction_end(): - - .type artMterpAsmInstructionEnd, #object - .hidden artMterpAsmInstructionEnd - .global artMterpAsmInstructionEnd -artMterpAsmInstructionEnd: diff --git a/runtime/interpreter/mterp/arm/instruction_end_alt.S b/runtime/interpreter/mterp/arm/instruction_end_alt.S deleted file mode 100644 index 9509a63b6a..0000000000 --- a/runtime/interpreter/mterp/arm/instruction_end_alt.S +++ /dev/null @@ -1,6 +0,0 @@ -%def instruction_end_alt(): - - .type artMterpAsmAltInstructionEnd, #object - .hidden artMterpAsmAltInstructionEnd - .global artMterpAsmAltInstructionEnd -artMterpAsmAltInstructionEnd: diff --git a/runtime/interpreter/mterp/arm/instruction_end_sister.S b/runtime/interpreter/mterp/arm/instruction_end_sister.S deleted file mode 100644 index 18f1dbb38d..0000000000 --- a/runtime/interpreter/mterp/arm/instruction_end_sister.S +++ /dev/null @@ -1,6 +0,0 @@ -%def instruction_end_sister(): - - .type artMterpAsmSisterEnd, #object - .hidden artMterpAsmSisterEnd - .global artMterpAsmSisterEnd -artMterpAsmSisterEnd: diff --git a/runtime/interpreter/mterp/arm/instruction_start.S b/runtime/interpreter/mterp/arm/instruction_start.S deleted file mode 100644 index 457dcf9617..0000000000 --- a/runtime/interpreter/mterp/arm/instruction_start.S +++ /dev/null @@ -1,7 +0,0 @@ -%def instruction_start(): - - .type artMterpAsmInstructionStart, #object - .hidden artMterpAsmInstructionStart - .global artMterpAsmInstructionStart -artMterpAsmInstructionStart = .L_op_nop - .text diff --git a/runtime/interpreter/mterp/arm/instruction_start_alt.S b/runtime/interpreter/mterp/arm/instruction_start_alt.S deleted file mode 100644 index 40d2bf5dbe..0000000000 --- a/runtime/interpreter/mterp/arm/instruction_start_alt.S +++ /dev/null @@ -1,7 +0,0 @@ -%def instruction_start_alt(): - - .type artMterpAsmAltInstructionStart, #object - .hidden artMterpAsmAltInstructionStart - .global artMterpAsmAltInstructionStart -artMterpAsmAltInstructionStart = .L_ALT_op_nop - .text diff --git a/runtime/interpreter/mterp/arm/instruction_start_sister.S b/runtime/interpreter/mterp/arm/instruction_start_sister.S deleted file mode 100644 index 2bf24636ea..0000000000 --- a/runtime/interpreter/mterp/arm/instruction_start_sister.S +++ /dev/null @@ -1,8 +0,0 @@ -%def instruction_start_sister(): - - .type artMterpAsmSisterStart, #object - .hidden artMterpAsmSisterStart - .global artMterpAsmSisterStart - .text - .balign 4 -artMterpAsmSisterStart: diff --git a/runtime/interpreter/mterp/arm/invoke.S b/runtime/interpreter/mterp/arm/invoke.S index 812852ef57..8693d3b8ca 100644 --- a/runtime/interpreter/mterp/arm/invoke.S +++ b/runtime/interpreter/mterp/arm/invoke.S @@ -20,3 +20,102 @@ GET_INST_OPCODE ip GOTO_OPCODE ip + +%def invoke_polymorphic(helper="UndefinedInvokeHandler"): + /* + * invoke-polymorphic handler wrapper. + */ + /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ + /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ + .extern $helper + EXPORT_PC + mov r0, rSELF + add r1, rFP, #OFF_FP_SHADOWFRAME + mov r2, rPC + mov r3, rINST + bl $helper + cmp r0, #0 + beq MterpException + FETCH_ADVANCE_INST 4 + bl MterpShouldSwitchInterpreters + cmp r0, #0 + bne MterpFallback + GET_INST_OPCODE ip + GOTO_OPCODE ip + +%def op_invoke_custom(): +% invoke(helper="MterpInvokeCustom") + /* + * Handle an invoke-custom invocation. + * + * for: invoke-custom, invoke-custom/range + */ + /* op vB, {vD, vE, vF, vG, vA}, call_site@BBBB */ + /* op vAA, {vCCCC..v(CCCC+AA-1)}, call_site@BBBB */ + +%def op_invoke_custom_range(): +% invoke(helper="MterpInvokeCustomRange") + +%def op_invoke_direct(): +% invoke(helper="MterpInvokeDirect") + +%def op_invoke_direct_range(): +% invoke(helper="MterpInvokeDirectRange") + +%def op_invoke_interface(): +% invoke(helper="MterpInvokeInterface") + /* + * Handle an interface method call. + * + * for: invoke-interface, invoke-interface/range + */ + /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ + /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ + +%def op_invoke_interface_range(): +% invoke(helper="MterpInvokeInterfaceRange") + +%def op_invoke_polymorphic(): +% invoke_polymorphic(helper="MterpInvokePolymorphic") + +%def op_invoke_polymorphic_range(): +% invoke_polymorphic(helper="MterpInvokePolymorphicRange") + +%def op_invoke_static(): +% invoke(helper="MterpInvokeStatic") + + +%def op_invoke_static_range(): +% invoke(helper="MterpInvokeStaticRange") + +%def op_invoke_super(): +% invoke(helper="MterpInvokeSuper") + /* + * Handle a "super" method call. + * + * for: invoke-super, invoke-super/range + */ + /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ + /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ + +%def op_invoke_super_range(): +% invoke(helper="MterpInvokeSuperRange") + +%def op_invoke_virtual(): +% invoke(helper="MterpInvokeVirtual") + /* + * Handle a virtual method call. + * + * for: invoke-virtual, invoke-virtual/range + */ + /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ + /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ + +%def op_invoke_virtual_quick(): +% invoke(helper="MterpInvokeVirtualQuick") + +%def op_invoke_virtual_range(): +% invoke(helper="MterpInvokeVirtualRange") + +%def op_invoke_virtual_range_quick(): +% invoke(helper="MterpInvokeVirtualQuickRange") diff --git a/runtime/interpreter/mterp/arm/invoke_polymorphic.S b/runtime/interpreter/mterp/arm/invoke_polymorphic.S deleted file mode 100644 index b473616ad2..0000000000 --- a/runtime/interpreter/mterp/arm/invoke_polymorphic.S +++ /dev/null @@ -1,21 +0,0 @@ -%def invoke_polymorphic(helper="UndefinedInvokeHandler"): - /* - * invoke-polymorphic handler wrapper. - */ - /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ - .extern $helper - EXPORT_PC - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - mov r3, rINST - bl $helper - cmp r0, #0 - beq MterpException - FETCH_ADVANCE_INST 4 - bl MterpShouldSwitchInterpreters - cmp r0, #0 - bne MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip diff --git a/runtime/interpreter/mterp/arm/main.S b/runtime/interpreter/mterp/arm/main.S new file mode 100644 index 0000000000..73d45c0cbf --- /dev/null +++ b/runtime/interpreter/mterp/arm/main.S @@ -0,0 +1,756 @@ +%def header(): +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + Art assembly interpreter notes: + + First validate assembly code by implementing ExecuteXXXImpl() style body (doesn't + handle invoke, allows higher-level code to create frame & shadow frame. + + Once that's working, support direct entry code & eliminate shadow frame (and + excess locals allocation. + + Some (hopefully) temporary ugliness. We'll treat rFP as pointing to the + base of the vreg array within the shadow frame. Access the other fields, + dex_pc_, method_ and number_of_vregs_ via negative offsets. For now, we'll continue + the shadow frame mechanism of double-storing object references - via rFP & + number_of_vregs_. + + */ + +/* +ARM EABI general notes: + +r0-r3 hold first 4 args to a method; they are not preserved across method calls +r4-r8 are available for general use +r9 is given special treatment in some situations, but not for us +r10 (sl) seems to be generally available +r11 (fp) is used by gcc (unless -fomit-frame-pointer is set) +r12 (ip) is scratch -- not preserved across method calls +r13 (sp) should be managed carefully in case a signal arrives +r14 (lr) must be preserved +r15 (pc) can be tinkered with directly + +r0 holds returns of <= 4 bytes +r0-r1 hold returns of 8 bytes, low word in r0 + +Callee must save/restore r4+ (except r12) if it modifies them. If VFP +is present, registers s16-s31 (a/k/a d8-d15, a/k/a q4-q7) must be preserved, +s0-s15 (d0-d7, q0-a3) do not need to be. + +Stack is "full descending". Only the arguments that don't fit in the first 4 +registers are placed on the stack. "sp" points at the first stacked argument +(i.e. the 5th arg). + +VFP: single-precision results in s0, double-precision results in d0. + +In the EABI, "sp" must be 64-bit aligned on entry to a function, and any +64-bit quantities (long long, double) must be 64-bit aligned. +*/ + +/* +Mterp and ARM notes: + +The following registers have fixed assignments: + + reg nick purpose + r4 rPC interpreted program counter, used for fetching instructions + r5 rFP interpreted frame pointer, used for accessing locals and args + r6 rSELF self (Thread) pointer + r7 rINST first 16-bit code unit of current instruction + r8 rIBASE interpreted instruction base pointer, used for computed goto + r10 rPROFILE branch profiling countdown + r11 rREFS base of object references in shadow frame (ideally, we'll get rid of this later). + +Macros are provided for common operations. Each macro MUST emit only +one instruction to make instruction-counting easier. They MUST NOT alter +unspecified registers or condition codes. +*/ + +/* + * This is a #include, not a %include, because we want the C pre-processor + * to expand the macros into assembler assignment statements. + */ +#include "asm_support.h" +#include "interpreter/cfi_asm_support.h" + +#define MTERP_PROFILE_BRANCHES 1 +#define MTERP_LOGGING 0 + +/* During bringup, we'll use the shadow frame model instead of rFP */ +/* single-purpose registers, given names for clarity */ +#define rPC r4 +#define CFI_DEX 4 // DWARF register number of the register holding dex-pc (xPC). +#define CFI_TMP 0 // DWARF register number of the first argument register (r0). +#define rFP r5 +#define rSELF r6 +#define rINST r7 +#define rIBASE r8 +#define rPROFILE r10 +#define rREFS r11 + +/* + * Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs. So, + * to access other shadow frame fields, we need to use a backwards offset. Define those here. + */ +#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) +#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) +#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) +#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) +#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) +#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) +#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) +#define OFF_FP_DEX_INSTRUCTIONS OFF_FP(SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET) +#define OFF_FP_SHADOWFRAME OFF_FP(0) + +/* + * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must + * be done *before* something throws. + * + * It's okay to do this more than once. + * + * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped + * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction + * offset into the code_items_[] array. For effiency, we will "export" the + * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC + * to convert to a dex pc when needed. + */ +.macro EXPORT_PC + str rPC, [rFP, #OFF_FP_DEX_PC_PTR] +.endm + +.macro EXPORT_DEX_PC tmp + ldr \tmp, [rFP, #OFF_FP_DEX_INSTRUCTIONS] + str rPC, [rFP, #OFF_FP_DEX_PC_PTR] + sub \tmp, rPC, \tmp + asr \tmp, #1 + str \tmp, [rFP, #OFF_FP_DEX_PC] +.endm + +/* + * Fetch the next instruction from rPC into rINST. Does not advance rPC. + */ +.macro FETCH_INST + ldrh rINST, [rPC] +.endm + +/* + * Fetch the next instruction from the specified offset. Advances rPC + * to point to the next instruction. "_count" is in 16-bit code units. + * + * Because of the limited size of immediate constants on ARM, this is only + * suitable for small forward movements (i.e. don't try to implement "goto" + * with this). + * + * This must come AFTER anything that can throw an exception, or the + * exception catch may miss. (This also implies that it must come after + * EXPORT_PC.) + */ +.macro FETCH_ADVANCE_INST count + ldrh rINST, [rPC, #((\count)*2)]! +.endm + +/* + * The operation performed here is similar to FETCH_ADVANCE_INST, except the + * src and dest registers are parameterized (not hard-wired to rPC and rINST). + */ +.macro PREFETCH_ADVANCE_INST dreg, sreg, count + ldrh \dreg, [\sreg, #((\count)*2)]! +.endm + +/* + * Similar to FETCH_ADVANCE_INST, but does not update rPC. Used to load + * rINST ahead of possible exception point. Be sure to manually advance rPC + * later. + */ +.macro PREFETCH_INST count + ldrh rINST, [rPC, #((\count)*2)] +.endm + +/* Advance rPC by some number of code units. */ +.macro ADVANCE count + add rPC, #((\count)*2) +.endm + +/* + * Fetch the next instruction from an offset specified by _reg. Updates + * rPC to point to the next instruction. "_reg" must specify the distance + * in bytes, *not* 16-bit code units, and may be a signed value. + * + * We want to write "ldrh rINST, [rPC, _reg, lsl #1]!", but some of the + * bits that hold the shift distance are used for the half/byte/sign flags. + * In some cases we can pre-double _reg for free, so we require a byte offset + * here. + */ +.macro FETCH_ADVANCE_INST_RB reg + ldrh rINST, [rPC, \reg]! +.endm + +/* + * Fetch a half-word code unit from an offset past the current PC. The + * "_count" value is in 16-bit code units. Does not advance rPC. + * + * The "_S" variant works the same but treats the value as signed. + */ +.macro FETCH reg, count + ldrh \reg, [rPC, #((\count)*2)] +.endm + +.macro FETCH_S reg, count + ldrsh \reg, [rPC, #((\count)*2)] +.endm + +/* + * Fetch one byte from an offset past the current PC. Pass in the same + * "_count" as you would for FETCH, and an additional 0/1 indicating which + * byte of the halfword you want (lo/hi). + */ +.macro FETCH_B reg, count, byte + ldrb \reg, [rPC, #((\count)*2+(\byte))] +.endm + +/* + * Put the instruction's opcode field into the specified register. + */ +.macro GET_INST_OPCODE reg + and \reg, rINST, #255 +.endm + +/* + * Put the prefetched instruction's opcode field into the specified register. + */ +.macro GET_PREFETCHED_OPCODE oreg, ireg + and \oreg, \ireg, #255 +.endm + +/* + * Begin executing the opcode in _reg. Because this only jumps within the + * interpreter, we don't have to worry about pre-ARMv5 THUMB interwork. + */ +.macro GOTO_OPCODE reg + add pc, rIBASE, \reg, lsl #${handler_size_bits} +.endm +.macro GOTO_OPCODE_BASE base,reg + add pc, \base, \reg, lsl #${handler_size_bits} +.endm + +/* + * Get/set the 32-bit value from a Dalvik register. + */ +.macro GET_VREG reg, vreg + ldr \reg, [rFP, \vreg, lsl #2] +.endm +.macro SET_VREG reg, vreg + str \reg, [rFP, \vreg, lsl #2] + mov \reg, #0 + str \reg, [rREFS, \vreg, lsl #2] +.endm +.macro SET_VREG_OBJECT reg, vreg, tmpreg + str \reg, [rFP, \vreg, lsl #2] + str \reg, [rREFS, \vreg, lsl #2] +.endm +.macro SET_VREG_SHADOW reg, vreg + str \reg, [rREFS, \vreg, lsl #2] +.endm + +/* + * Clear the corresponding shadow regs for a vreg pair + */ +.macro CLEAR_SHADOW_PAIR vreg, tmp1, tmp2 + mov \tmp1, #0 + add \tmp2, \vreg, #1 + SET_VREG_SHADOW \tmp1, \vreg + SET_VREG_SHADOW \tmp1, \tmp2 +.endm + +/* + * Convert a virtual register index into an address. + */ +.macro VREG_INDEX_TO_ADDR reg, vreg + add \reg, rFP, \vreg, lsl #2 /* WARNING/FIXME: handle shadow frame vreg zero if store */ +.endm + +/* + * Refresh handler table. + */ +.macro REFRESH_IBASE + ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] +.endm + +/* + * cfi support macros. + */ +.macro ENTRY name + .arm + .type \name, #function + .hidden \name // Hide this as a global symbol, so we do not incur plt calls. + .global \name + /* Cache alignment for function entry */ + .balign 16 +\name: + .cfi_startproc + .fnstart +.endm + +.macro END name + .fnend + .cfi_endproc + .size \name, .-\name +.endm + +%def entry(): +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* + * Interpreter entry point. + */ + + .text + .align 2 + +/* + * On entry: + * r0 Thread* self/ + * r1 insns_ + * r2 ShadowFrame + * r3 JValue* result_register + * + */ + +ENTRY ExecuteMterpImpl + stmfd sp!, {r3-r10,fp,lr} @ save 10 regs, (r3 just to align 64) + .cfi_adjust_cfa_offset 40 + .cfi_rel_offset r3, 0 + .cfi_rel_offset r4, 4 + .cfi_rel_offset r5, 8 + .cfi_rel_offset r6, 12 + .cfi_rel_offset r7, 16 + .cfi_rel_offset r8, 20 + .cfi_rel_offset r9, 24 + .cfi_rel_offset r10, 28 + .cfi_rel_offset fp, 32 + .cfi_rel_offset lr, 36 + + /* Remember the return register */ + str r3, [r2, #SHADOWFRAME_RESULT_REGISTER_OFFSET] + + /* Remember the dex instruction pointer */ + str r1, [r2, #SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET] + + /* set up "named" registers */ + mov rSELF, r0 + ldr r0, [r2, #SHADOWFRAME_NUMBER_OF_VREGS_OFFSET] + add rFP, r2, #SHADOWFRAME_VREGS_OFFSET @ point to vregs. + VREG_INDEX_TO_ADDR rREFS, r0 @ point to reference array in shadow frame + ldr r0, [r2, #SHADOWFRAME_DEX_PC_OFFSET] @ Get starting dex_pc. + add rPC, r1, r0, lsl #1 @ Create direct pointer to 1st dex opcode + CFI_DEFINE_DEX_PC_WITH_OFFSET(CFI_TMP, CFI_DEX, 0) + EXPORT_PC + + /* Starting ibase */ + ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] + + /* Set up for backwards branches & osr profiling */ + ldr r0, [rFP, #OFF_FP_METHOD] + add r1, rFP, #OFF_FP_SHADOWFRAME + mov r2, rSELF + bl MterpSetUpHotnessCountdown + mov rPROFILE, r0 @ Starting hotness countdown to rPROFILE + + /* start executing the instruction at rPC */ + FETCH_INST @ load rINST from rPC + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + /* NOTE: no fallthrough */ + +%def alt_stub(): +/* + * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle + * any interesting requests and then jump to the real instruction + * handler. Note that the call to MterpCheckBefore is done as a tail call. + */ + .extern MterpCheckBefore + ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. + adr lr, .L_ALT_${opcode} + sub lr, lr, #(.L_ALT_${opcode} - .L_${opcode}) @ Addr of primary handler. + mov r0, rSELF + add r1, rFP, #OFF_FP_SHADOWFRAME + mov r2, rPC + b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. + +%def fallback(): +/* Transfer stub to alternate interpreter */ + b MterpFallback + + +%def footer(): +/* + * =========================================================================== + * Common subroutines and data + * =========================================================================== + */ + + .text + .align 2 + +/* + * We've detected a condition that will result in an exception, but the exception + * has not yet been thrown. Just bail out to the reference interpreter to deal with it. + * TUNING: for consistency, we may want to just go ahead and handle these here. + */ +common_errDivideByZero: + EXPORT_PC +#if MTERP_LOGGING + mov r0, rSELF + add r1, rFP, #OFF_FP_SHADOWFRAME + bl MterpLogDivideByZeroException +#endif + b MterpCommonFallback + +common_errArrayIndex: + EXPORT_PC +#if MTERP_LOGGING + mov r0, rSELF + add r1, rFP, #OFF_FP_SHADOWFRAME + bl MterpLogArrayIndexException +#endif + b MterpCommonFallback + +common_errNegativeArraySize: + EXPORT_PC +#if MTERP_LOGGING + mov r0, rSELF + add r1, rFP, #OFF_FP_SHADOWFRAME + bl MterpLogNegativeArraySizeException +#endif + b MterpCommonFallback + +common_errNoSuchMethod: + EXPORT_PC +#if MTERP_LOGGING + mov r0, rSELF + add r1, rFP, #OFF_FP_SHADOWFRAME + bl MterpLogNoSuchMethodException +#endif + b MterpCommonFallback + +common_errNullObject: + EXPORT_PC +#if MTERP_LOGGING + mov r0, rSELF + add r1, rFP, #OFF_FP_SHADOWFRAME + bl MterpLogNullObjectException +#endif + b MterpCommonFallback + +common_exceptionThrown: + EXPORT_PC +#if MTERP_LOGGING + mov r0, rSELF + add r1, rFP, #OFF_FP_SHADOWFRAME + bl MterpLogExceptionThrownException +#endif + b MterpCommonFallback + +MterpSuspendFallback: + EXPORT_PC +#if MTERP_LOGGING + mov r0, rSELF + add r1, rFP, #OFF_FP_SHADOWFRAME + ldr r2, [rSELF, #THREAD_FLAGS_OFFSET] + bl MterpLogSuspendFallback +#endif + b MterpCommonFallback + +/* + * If we're here, something is out of the ordinary. If there is a pending + * exception, handle it. Otherwise, roll back and retry with the reference + * interpreter. + */ +MterpPossibleException: + ldr r0, [rSELF, #THREAD_EXCEPTION_OFFSET] + cmp r0, #0 @ Exception pending? + beq MterpFallback @ If not, fall back to reference interpreter. + /* intentional fallthrough - handle pending exception. */ +/* + * On return from a runtime helper routine, we've found a pending exception. + * Can we handle it here - or need to bail out to caller? + * + */ +MterpException: + mov r0, rSELF + add r1, rFP, #OFF_FP_SHADOWFRAME + bl MterpHandleException @ (self, shadow_frame) + cmp r0, #0 + beq MterpExceptionReturn @ no local catch, back to caller. + ldr r0, [rFP, #OFF_FP_DEX_INSTRUCTIONS] + ldr r1, [rFP, #OFF_FP_DEX_PC] + ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] + add rPC, r0, r1, lsl #1 @ generate new dex_pc_ptr + /* Do we need to switch interpreters? */ + bl MterpShouldSwitchInterpreters + cmp r0, #0 + bne MterpFallback + /* resume execution at catch block */ + EXPORT_PC + FETCH_INST + GET_INST_OPCODE ip + GOTO_OPCODE ip + /* NOTE: no fallthrough */ + +/* + * Common handling for branches with support for Jit profiling. + * On entry: + * rINST <= signed offset + * rPROFILE <= signed hotness countdown (expanded to 32 bits) + * condition bits <= set to establish sign of offset (use "NoFlags" entry if not) + * + * We have quite a few different cases for branch profiling, OSR detection and + * suspend check support here. + * + * Taken backward branches: + * If profiling active, do hotness countdown and report if we hit zero. + * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. + * Is there a pending suspend request? If so, suspend. + * + * Taken forward branches and not-taken backward branches: + * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. + * + * Our most common case is expected to be a taken backward branch with active jit profiling, + * but no full OSR check and no pending suspend request. + * Next most common case is not-taken branch with no full OSR check. + * + */ +MterpCommonTakenBranchNoFlags: + cmp rINST, #0 +MterpCommonTakenBranch: + bgt .L_forward_branch @ don't add forward branches to hotness +/* + * We need to subtract 1 from positive values and we should not see 0 here, + * so we may use the result of the comparison with -1. + */ +#if JIT_CHECK_OSR != -1 +# error "JIT_CHECK_OSR must be -1." +#endif + cmp rPROFILE, #JIT_CHECK_OSR + beq .L_osr_check + subsgt rPROFILE, #1 + beq .L_add_batch @ counted down to zero - report +.L_resume_backward_branch: + ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] + REFRESH_IBASE + add r2, rINST, rINST @ r2<- byte offset + FETCH_ADVANCE_INST_RB r2 @ update rPC, load rINST + ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST + bne .L_suspend_request_pending + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +.L_suspend_request_pending: + EXPORT_PC + mov r0, rSELF + bl MterpSuspendCheck @ (self) + cmp r0, #0 + bne MterpFallback + REFRESH_IBASE @ might have changed during suspend + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +.L_no_count_backwards: + cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? + bne .L_resume_backward_branch +.L_osr_check: + mov r0, rSELF + add r1, rFP, #OFF_FP_SHADOWFRAME + mov r2, rINST + EXPORT_PC + bl MterpMaybeDoOnStackReplacement @ (self, shadow_frame, offset) + cmp r0, #0 + bne MterpOnStackReplacement + b .L_resume_backward_branch + +.L_forward_branch: + cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? + beq .L_check_osr_forward +.L_resume_forward_branch: + add r2, rINST, rINST @ r2<- byte offset + FETCH_ADVANCE_INST_RB r2 @ update rPC, load rINST + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +.L_check_osr_forward: + mov r0, rSELF + add r1, rFP, #OFF_FP_SHADOWFRAME + mov r2, rINST + EXPORT_PC + bl MterpMaybeDoOnStackReplacement @ (self, shadow_frame, offset) + cmp r0, #0 + bne MterpOnStackReplacement + b .L_resume_forward_branch + +.L_add_batch: + add r1, rFP, #OFF_FP_SHADOWFRAME + strh rPROFILE, [r1, #SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET] + ldr r0, [rFP, #OFF_FP_METHOD] + mov r2, rSELF + bl MterpAddHotnessBatch @ (method, shadow_frame, self) + mov rPROFILE, r0 @ restore new hotness countdown to rPROFILE + b .L_no_count_backwards + +/* + * Entered from the conditional branch handlers when OSR check request active on + * not-taken path. All Dalvik not-taken conditional branch offsets are 2. + */ +.L_check_not_taken_osr: + mov r0, rSELF + add r1, rFP, #OFF_FP_SHADOWFRAME + mov r2, #2 + EXPORT_PC + bl MterpMaybeDoOnStackReplacement @ (self, shadow_frame, offset) + cmp r0, #0 + bne MterpOnStackReplacement + FETCH_ADVANCE_INST 2 + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +/* + * On-stack replacement has happened, and now we've returned from the compiled method. + */ +MterpOnStackReplacement: +#if MTERP_LOGGING + mov r0, rSELF + add r1, rFP, #OFF_FP_SHADOWFRAME + mov r2, rINST + bl MterpLogOSR +#endif + mov r0, #1 @ Signal normal return + b MterpDone + +/* + * Bail out to reference interpreter. + */ +MterpFallback: + EXPORT_PC +#if MTERP_LOGGING + mov r0, rSELF + add r1, rFP, #OFF_FP_SHADOWFRAME + bl MterpLogFallback +#endif +MterpCommonFallback: + mov r0, #0 @ signal retry with reference interpreter. + b MterpDone + +/* + * We pushed some registers on the stack in ExecuteMterpImpl, then saved + * SP and LR. Here we restore SP, restore the registers, and then restore + * LR to PC. + * + * On entry: + * uint32_t* rFP (should still be live, pointer to base of vregs) + */ +MterpExceptionReturn: + mov r0, #1 @ signal return to caller. + b MterpDone +MterpReturn: + ldr r2, [rFP, #OFF_FP_RESULT_REGISTER] + str r0, [r2] + str r1, [r2, #4] + mov r0, #1 @ signal return to caller. +MterpDone: +/* + * At this point, we expect rPROFILE to be non-zero. If negative, hotness is disabled or we're + * checking for OSR. If greater than zero, we might have unreported hotness to register + * (the difference between the ending rPROFILE and the cached hotness counter). rPROFILE + * should only reach zero immediately after a hotness decrement, and is then reset to either + * a negative special state or the new non-zero countdown value. + */ + cmp rPROFILE, #0 + bgt MterpProfileActive @ if > 0, we may have some counts to report. + ldmfd sp!, {r3-r10,fp,pc} @ restore 10 regs and return + +MterpProfileActive: + mov rINST, r0 @ stash return value + /* Report cached hotness counts */ + ldr r0, [rFP, #OFF_FP_METHOD] + add r1, rFP, #OFF_FP_SHADOWFRAME + mov r2, rSELF + strh rPROFILE, [r1, #SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET] + bl MterpAddHotnessBatch @ (method, shadow_frame, self) + mov r0, rINST @ restore return value + ldmfd sp!, {r3-r10,fp,pc} @ restore 10 regs and return + + END ExecuteMterpImpl + + +%def instruction_end(): + + .type artMterpAsmInstructionEnd, #object + .hidden artMterpAsmInstructionEnd + .global artMterpAsmInstructionEnd +artMterpAsmInstructionEnd: + +%def instruction_end_alt(): + + .type artMterpAsmAltInstructionEnd, #object + .hidden artMterpAsmAltInstructionEnd + .global artMterpAsmAltInstructionEnd +artMterpAsmAltInstructionEnd: + +%def instruction_end_sister(): + + .type artMterpAsmSisterEnd, #object + .hidden artMterpAsmSisterEnd + .global artMterpAsmSisterEnd +artMterpAsmSisterEnd: + +%def instruction_start(): + + .type artMterpAsmInstructionStart, #object + .hidden artMterpAsmInstructionStart + .global artMterpAsmInstructionStart +artMterpAsmInstructionStart = .L_op_nop + .text + +%def instruction_start_alt(): + + .type artMterpAsmAltInstructionStart, #object + .hidden artMterpAsmAltInstructionStart + .global artMterpAsmAltInstructionStart +artMterpAsmAltInstructionStart = .L_ALT_op_nop + .text + +%def instruction_start_sister(): + + .type artMterpAsmSisterStart, #object + .hidden artMterpAsmSisterStart + .global artMterpAsmSisterStart + .text + .balign 4 +artMterpAsmSisterStart: diff --git a/runtime/interpreter/mterp/arm/object.S b/runtime/interpreter/mterp/arm/object.S new file mode 100644 index 0000000000..af1ece2ec2 --- /dev/null +++ b/runtime/interpreter/mterp/arm/object.S @@ -0,0 +1,275 @@ +%def field(helper=""): + /* + * General field read / write (iget-* iput-* sget-* sput-*). + */ + .extern $helper + mov r0, rPC @ arg0: Instruction* inst + mov r1, rINST @ arg1: uint16_t inst_data + add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf + mov r3, rSELF @ arg3: Thread* self + PREFETCH_INST 2 @ prefetch next opcode + bl $helper + cmp r0, #0 + beq MterpPossibleException + ADVANCE 2 + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def op_check_cast(): + /* + * Check to see if a cast from one class to another is allowed. + */ + /* check-cast vAA, class@BBBB */ + EXPORT_PC + FETCH r0, 1 @ r0<- BBBB + mov r1, rINST, lsr #8 @ r1<- AA + VREG_INDEX_TO_ADDR r1, r1 @ r1<- &object + ldr r2, [rFP, #OFF_FP_METHOD] @ r2<- method + mov r3, rSELF @ r3<- self + bl MterpCheckCast @ (index, &obj, method, self) + PREFETCH_INST 2 + cmp r0, #0 + bne MterpPossibleException + ADVANCE 2 + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def op_iget(is_object="0", helper="MterpIGetU32"): +% field(helper=helper) + +%def op_iget_boolean(): +% op_iget(helper="MterpIGetU8") + +%def op_iget_boolean_quick(): +% op_iget_quick(load="ldrb") + +%def op_iget_byte(): +% op_iget(helper="MterpIGetI8") + +%def op_iget_byte_quick(): +% op_iget_quick(load="ldrsb") + +%def op_iget_char(): +% op_iget(helper="MterpIGetU16") + +%def op_iget_char_quick(): +% op_iget_quick(load="ldrh") + +%def op_iget_object(): +% op_iget(is_object="1", helper="MterpIGetObj") + +%def op_iget_object_quick(): + /* For: iget-object-quick */ + /* op vA, vB, offset@CCCC */ + mov r2, rINST, lsr #12 @ r2<- B + FETCH r1, 1 @ r1<- field byte offset + EXPORT_PC + GET_VREG r0, r2 @ r0<- object we're operating on + bl artIGetObjectFromMterp @ (obj, offset) + ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] + ubfx r2, rINST, #8, #4 @ r2<- A + PREFETCH_INST 2 + cmp r3, #0 + bne MterpPossibleException @ bail out + SET_VREG_OBJECT r0, r2 @ fp[A]<- r0 + ADVANCE 2 @ advance rPC + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def op_iget_quick(load="ldr"): + /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ + /* op vA, vB, offset@CCCC */ + mov r2, rINST, lsr #12 @ r2<- B + FETCH r1, 1 @ r1<- field byte offset + GET_VREG r3, r2 @ r3<- object we're operating on + ubfx r2, rINST, #8, #4 @ r2<- A + cmp r3, #0 @ check object for null + beq common_errNullObject @ object was null + $load r0, [r3, r1] @ r0<- obj.field + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + SET_VREG r0, r2 @ fp[A]<- r0 + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def op_iget_short(): +% op_iget(helper="MterpIGetI16") + +%def op_iget_short_quick(): +% op_iget_quick(load="ldrsh") + +%def op_iget_wide(): +% op_iget(helper="MterpIGetU64") + +%def op_iget_wide_quick(): + /* iget-wide-quick vA, vB, offset@CCCC */ + mov r2, rINST, lsr #12 @ r2<- B + FETCH ip, 1 @ ip<- field byte offset + GET_VREG r3, r2 @ r3<- object we're operating on + ubfx r2, rINST, #8, #4 @ r2<- A + cmp r3, #0 @ check object for null + beq common_errNullObject @ object was null + ldrd r0, [r3, ip] @ r0<- obj.field (64 bits, aligned) + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + VREG_INDEX_TO_ADDR r3, r2 @ r3<- &fp[A] + CLEAR_SHADOW_PAIR r2, ip, lr @ Zero out the shadow regs + GET_INST_OPCODE ip @ extract opcode from rINST + stmia r3, {r0-r1} @ fp[A]<- r0/r1 + GOTO_OPCODE ip @ jump to next instruction + +%def op_instance_of(): + /* + * Check to see if an object reference is an instance of a class. + * + * Most common situation is a non-null object, being compared against + * an already-resolved class. + */ + /* instance-of vA, vB, class@CCCC */ + EXPORT_PC + FETCH r0, 1 @ r0<- CCCC + mov r1, rINST, lsr #12 @ r1<- B + VREG_INDEX_TO_ADDR r1, r1 @ r1<- &object + ldr r2, [rFP, #OFF_FP_METHOD] @ r2<- method + mov r3, rSELF @ r3<- self + bl MterpInstanceOf @ (index, &obj, method, self) + ldr r1, [rSELF, #THREAD_EXCEPTION_OFFSET] + ubfx r9, rINST, #8, #4 @ r9<- A + PREFETCH_INST 2 + cmp r1, #0 @ exception pending? + bne MterpException + ADVANCE 2 @ advance rPC + SET_VREG r0, r9 @ vA<- r0 + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def op_iput(is_object="0", helper="MterpIPutU32"): +% field(helper=helper) + +%def op_iput_boolean(): +% op_iput(helper="MterpIPutU8") + +%def op_iput_boolean_quick(): +% op_iput_quick(store="strb") + +%def op_iput_byte(): +% op_iput(helper="MterpIPutI8") + +%def op_iput_byte_quick(): +% op_iput_quick(store="strb") + +%def op_iput_char(): +% op_iput(helper="MterpIPutU16") + +%def op_iput_char_quick(): +% op_iput_quick(store="strh") + +%def op_iput_object(): +% op_iput(is_object="1", helper="MterpIPutObj") + +%def op_iput_object_quick(): + EXPORT_PC + add r0, rFP, #OFF_FP_SHADOWFRAME + mov r1, rPC + mov r2, rINST + bl MterpIputObjectQuick + cmp r0, #0 + beq MterpException + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def op_iput_quick(store="str"): + /* For: iput-quick, iput-object-quick */ + /* op vA, vB, offset@CCCC */ + mov r2, rINST, lsr #12 @ r2<- B + FETCH r1, 1 @ r1<- field byte offset + GET_VREG r3, r2 @ r3<- fp[B], the object pointer + ubfx r2, rINST, #8, #4 @ r2<- A + cmp r3, #0 @ check object for null + beq common_errNullObject @ object was null + GET_VREG r0, r2 @ r0<- fp[A] + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + $store r0, [r3, r1] @ obj.field<- r0 + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def op_iput_short(): +% op_iput(helper="MterpIPutI16") + +%def op_iput_short_quick(): +% op_iput_quick(store="strh") + +%def op_iput_wide(): +% op_iput(helper="MterpIPutU64") + +%def op_iput_wide_quick(): + /* iput-wide-quick vA, vB, offset@CCCC */ + mov r2, rINST, lsr #12 @ r2<- B + FETCH r3, 1 @ r3<- field byte offset + GET_VREG r2, r2 @ r2<- fp[B], the object pointer + ubfx r0, rINST, #8, #4 @ r0<- A + cmp r2, #0 @ check object for null + beq common_errNullObject @ object was null + VREG_INDEX_TO_ADDR r0, r0 @ r0<- &fp[A] + ldmia r0, {r0-r1} @ r0/r1<- fp[A]/fp[A+1] + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + strd r0, [r2, r3] @ obj.field<- r0/r1 + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def op_new_instance(): + /* + * Create a new instance of a class. + */ + /* new-instance vAA, class@BBBB */ + EXPORT_PC + add r0, rFP, #OFF_FP_SHADOWFRAME + mov r1, rSELF + mov r2, rINST + bl MterpNewInstance @ (shadow_frame, self, inst_data) + cmp r0, #0 + beq MterpPossibleException + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def op_sget(is_object="0", helper="MterpSGetU32"): +% field(helper=helper) + +%def op_sget_boolean(): +% op_sget(helper="MterpSGetU8") + +%def op_sget_byte(): +% op_sget(helper="MterpSGetI8") + +%def op_sget_char(): +% op_sget(helper="MterpSGetU16") + +%def op_sget_object(): +% op_sget(is_object="1", helper="MterpSGetObj") + +%def op_sget_short(): +% op_sget(helper="MterpSGetI16") + +%def op_sget_wide(): +% op_sget(helper="MterpSGetU64") + +%def op_sput(is_object="0", helper="MterpSPutU32"): +% field(helper=helper) + +%def op_sput_boolean(): +% op_sput(helper="MterpSPutU8") + +%def op_sput_byte(): +% op_sput(helper="MterpSPutI8") + +%def op_sput_char(): +% op_sput(helper="MterpSPutU16") + +%def op_sput_object(): +% op_sput(is_object="1", helper="MterpSPutObj") + +%def op_sput_short(): +% op_sput(helper="MterpSPutI16") + +%def op_sput_wide(): +% op_sput(helper="MterpSPutU64") diff --git a/runtime/interpreter/mterp/arm/op_add_double.S b/runtime/interpreter/mterp/arm/op_add_double.S deleted file mode 100644 index 17aabcd817..0000000000 --- a/runtime/interpreter/mterp/arm/op_add_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_double(): -% fbinopWide(instr="faddd d2, d0, d1") diff --git a/runtime/interpreter/mterp/arm/op_add_double_2addr.S b/runtime/interpreter/mterp/arm/op_add_double_2addr.S deleted file mode 100644 index 97d1757468..0000000000 --- a/runtime/interpreter/mterp/arm/op_add_double_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_double_2addr(): -% fbinopWide2addr(instr="faddd d2, d0, d1") diff --git a/runtime/interpreter/mterp/arm/op_add_float.S b/runtime/interpreter/mterp/arm/op_add_float.S deleted file mode 100644 index 9ca8cadc34..0000000000 --- a/runtime/interpreter/mterp/arm/op_add_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_float(): -% fbinop(instr="fadds s2, s0, s1") diff --git a/runtime/interpreter/mterp/arm/op_add_float_2addr.S b/runtime/interpreter/mterp/arm/op_add_float_2addr.S deleted file mode 100644 index abe1989778..0000000000 --- a/runtime/interpreter/mterp/arm/op_add_float_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_float_2addr(): -% fbinop2addr(instr="fadds s2, s0, s1") diff --git a/runtime/interpreter/mterp/arm/op_add_int.S b/runtime/interpreter/mterp/arm/op_add_int.S deleted file mode 100644 index e18601c71b..0000000000 --- a/runtime/interpreter/mterp/arm/op_add_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_int(): -% binop(instr="add r0, r0, r1") diff --git a/runtime/interpreter/mterp/arm/op_add_int_2addr.S b/runtime/interpreter/mterp/arm/op_add_int_2addr.S deleted file mode 100644 index 10ea943583..0000000000 --- a/runtime/interpreter/mterp/arm/op_add_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_int_2addr(): -% binop2addr(instr="add r0, r0, r1") diff --git a/runtime/interpreter/mterp/arm/op_add_int_lit16.S b/runtime/interpreter/mterp/arm/op_add_int_lit16.S deleted file mode 100644 index 63febf20da..0000000000 --- a/runtime/interpreter/mterp/arm/op_add_int_lit16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_int_lit16(): -% binopLit16(instr="add r0, r0, r1") diff --git a/runtime/interpreter/mterp/arm/op_add_int_lit8.S b/runtime/interpreter/mterp/arm/op_add_int_lit8.S deleted file mode 100644 index 4393e66861..0000000000 --- a/runtime/interpreter/mterp/arm/op_add_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_int_lit8(): -% binopLit8(extract="", instr="add r0, r0, r3, asr #8") diff --git a/runtime/interpreter/mterp/arm/op_add_long.S b/runtime/interpreter/mterp/arm/op_add_long.S deleted file mode 100644 index 88994d40e5..0000000000 --- a/runtime/interpreter/mterp/arm/op_add_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_long(): -% binopWide(preinstr="adds r0, r0, r2", instr="adc r1, r1, r3") diff --git a/runtime/interpreter/mterp/arm/op_add_long_2addr.S b/runtime/interpreter/mterp/arm/op_add_long_2addr.S deleted file mode 100644 index bfe7447c92..0000000000 --- a/runtime/interpreter/mterp/arm/op_add_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_long_2addr(): -% binopWide2addr(preinstr="adds r0, r0, r2", instr="adc r1, r1, r3") diff --git a/runtime/interpreter/mterp/arm/op_aget.S b/runtime/interpreter/mterp/arm/op_aget.S deleted file mode 100644 index bf265b4819..0000000000 --- a/runtime/interpreter/mterp/arm/op_aget.S +++ /dev/null @@ -1,29 +0,0 @@ -%def op_aget(load="ldr", shift="2", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"): - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B r2, 1, 0 @ r2<- BB - mov r9, rINST, lsr #8 @ r9<- AA - FETCH_B r3, 1, 1 @ r3<- CC - GET_VREG r0, r2 @ r0<- vBB (array object) - GET_VREG r1, r3 @ r1<- vCC (requested index) - cmp r0, #0 @ null array object? - beq common_errNullObject @ yes, bail - ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length - add r0, r0, r1, lsl #$shift @ r0<- arrayObj + index*width - cmp r1, r3 @ compare unsigned index, length - bcs common_errArrayIndex @ index >= length, bail - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - $load r2, [r0, #$data_offset] @ r2<- vBB[vCC] - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r2, r9 @ vAA<- r2 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_aget_boolean.S b/runtime/interpreter/mterp/arm/op_aget_boolean.S deleted file mode 100644 index d6e0a1bbd9..0000000000 --- a/runtime/interpreter/mterp/arm/op_aget_boolean.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aget_boolean(): -% op_aget(load="ldrb", shift="0", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/arm/op_aget_byte.S b/runtime/interpreter/mterp/arm/op_aget_byte.S deleted file mode 100644 index 6c9f1b78fa..0000000000 --- a/runtime/interpreter/mterp/arm/op_aget_byte.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aget_byte(): -% op_aget(load="ldrsb", shift="0", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/arm/op_aget_char.S b/runtime/interpreter/mterp/arm/op_aget_char.S deleted file mode 100644 index c5812e3aff..0000000000 --- a/runtime/interpreter/mterp/arm/op_aget_char.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aget_char(): -% op_aget(load="ldrh", shift="1", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/arm/op_aget_object.S b/runtime/interpreter/mterp/arm/op_aget_object.S deleted file mode 100644 index 3b25086dce..0000000000 --- a/runtime/interpreter/mterp/arm/op_aget_object.S +++ /dev/null @@ -1,22 +0,0 @@ -%def op_aget_object(): - /* - * Array object get. vAA <- vBB[vCC]. - * - * for: aget-object - */ - /* op vAA, vBB, vCC */ - FETCH_B r2, 1, 0 @ r2<- BB - mov r9, rINST, lsr #8 @ r9<- AA - FETCH_B r3, 1, 1 @ r3<- CC - EXPORT_PC - GET_VREG r0, r2 @ r0<- vBB (array object) - GET_VREG r1, r3 @ r1<- vCC (requested index) - bl artAGetObjectFromMterp @ (array, index) - ldr r1, [rSELF, #THREAD_EXCEPTION_OFFSET] - PREFETCH_INST 2 - cmp r1, #0 - bne MterpException - SET_VREG_OBJECT r0, r9 - ADVANCE 2 - GET_INST_OPCODE ip - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_aget_short.S b/runtime/interpreter/mterp/arm/op_aget_short.S deleted file mode 100644 index 9727560fe4..0000000000 --- a/runtime/interpreter/mterp/arm/op_aget_short.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aget_short(): -% op_aget(load="ldrsh", shift="1", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/arm/op_aget_wide.S b/runtime/interpreter/mterp/arm/op_aget_wide.S deleted file mode 100644 index 28437e71f2..0000000000 --- a/runtime/interpreter/mterp/arm/op_aget_wide.S +++ /dev/null @@ -1,26 +0,0 @@ -%def op_aget_wide(): - /* - * Array get, 64 bits. vAA <- vBB[vCC]. - * - * Arrays of long/double are 64-bit aligned, so it's okay to use LDRD. - */ - /* aget-wide vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - GET_VREG r0, r2 @ r0<- vBB (array object) - GET_VREG r1, r3 @ r1<- vCC (requested index) - cmp r0, #0 @ null array object? - beq common_errNullObject @ yes, bail - ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length - add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width - cmp r1, r3 @ compare unsigned index, length - bcs common_errArrayIndex @ index >= length, bail - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs - ldrd r2, [r0, #MIRROR_WIDE_ARRAY_DATA_OFFSET] @ r2/r3<- vBB[vCC] - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r2-r3} @ vAA/vAA+1<- r2/r3 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_and_int.S b/runtime/interpreter/mterp/arm/op_and_int.S deleted file mode 100644 index ac0ae6670d..0000000000 --- a/runtime/interpreter/mterp/arm/op_and_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_and_int(): -% binop(instr="and r0, r0, r1") diff --git a/runtime/interpreter/mterp/arm/op_and_int_2addr.S b/runtime/interpreter/mterp/arm/op_and_int_2addr.S deleted file mode 100644 index 28a668a1a0..0000000000 --- a/runtime/interpreter/mterp/arm/op_and_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_and_int_2addr(): -% binop2addr(instr="and r0, r0, r1") diff --git a/runtime/interpreter/mterp/arm/op_and_int_lit16.S b/runtime/interpreter/mterp/arm/op_and_int_lit16.S deleted file mode 100644 index 4b9a4c947a..0000000000 --- a/runtime/interpreter/mterp/arm/op_and_int_lit16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_and_int_lit16(): -% binopLit16(instr="and r0, r0, r1") diff --git a/runtime/interpreter/mterp/arm/op_and_int_lit8.S b/runtime/interpreter/mterp/arm/op_and_int_lit8.S deleted file mode 100644 index b26bfe4227..0000000000 --- a/runtime/interpreter/mterp/arm/op_and_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_and_int_lit8(): -% binopLit8(extract="", instr="and r0, r0, r3, asr #8") diff --git a/runtime/interpreter/mterp/arm/op_and_long.S b/runtime/interpreter/mterp/arm/op_and_long.S deleted file mode 100644 index 3af7897fb2..0000000000 --- a/runtime/interpreter/mterp/arm/op_and_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_and_long(): -% binopWide(preinstr="and r0, r0, r2", instr="and r1, r1, r3") diff --git a/runtime/interpreter/mterp/arm/op_and_long_2addr.S b/runtime/interpreter/mterp/arm/op_and_long_2addr.S deleted file mode 100644 index 78e5d88162..0000000000 --- a/runtime/interpreter/mterp/arm/op_and_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_and_long_2addr(): -% binopWide2addr(preinstr="and r0, r0, r2", instr="and r1, r1, r3") diff --git a/runtime/interpreter/mterp/arm/op_aput.S b/runtime/interpreter/mterp/arm/op_aput.S deleted file mode 100644 index 7b5da541f6..0000000000 --- a/runtime/interpreter/mterp/arm/op_aput.S +++ /dev/null @@ -1,29 +0,0 @@ -%def op_aput(store="str", shift="2", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"): - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B r2, 1, 0 @ r2<- BB - mov r9, rINST, lsr #8 @ r9<- AA - FETCH_B r3, 1, 1 @ r3<- CC - GET_VREG r0, r2 @ r0<- vBB (array object) - GET_VREG r1, r3 @ r1<- vCC (requested index) - cmp r0, #0 @ null array object? - beq common_errNullObject @ yes, bail - ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length - add r0, r0, r1, lsl #$shift @ r0<- arrayObj + index*width - cmp r1, r3 @ compare unsigned index, length - bcs common_errArrayIndex @ index >= length, bail - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - GET_VREG r2, r9 @ r2<- vAA - GET_INST_OPCODE ip @ extract opcode from rINST - $store r2, [r0, #$data_offset] @ vBB[vCC]<- r2 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_aput_boolean.S b/runtime/interpreter/mterp/arm/op_aput_boolean.S deleted file mode 100644 index 467cc4bf20..0000000000 --- a/runtime/interpreter/mterp/arm/op_aput_boolean.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aput_boolean(): -% op_aput(store="strb", shift="0", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/arm/op_aput_byte.S b/runtime/interpreter/mterp/arm/op_aput_byte.S deleted file mode 100644 index 2b4c0ba389..0000000000 --- a/runtime/interpreter/mterp/arm/op_aput_byte.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aput_byte(): -% op_aput(store="strb", shift="0", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/arm/op_aput_char.S b/runtime/interpreter/mterp/arm/op_aput_char.S deleted file mode 100644 index cb7dcbad4d..0000000000 --- a/runtime/interpreter/mterp/arm/op_aput_char.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aput_char(): -% op_aput(store="strh", shift="1", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/arm/op_aput_object.S b/runtime/interpreter/mterp/arm/op_aput_object.S deleted file mode 100644 index 83b7e5a2fb..0000000000 --- a/runtime/interpreter/mterp/arm/op_aput_object.S +++ /dev/null @@ -1,15 +0,0 @@ -%def op_aput_object(): - /* - * Store an object into an array. vBB[vCC] <- vAA. - */ - /* op vAA, vBB, vCC */ - EXPORT_PC - add r0, rFP, #OFF_FP_SHADOWFRAME - mov r1, rPC - mov r2, rINST - bl MterpAputObject - cmp r0, #0 - beq MterpPossibleException - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_aput_short.S b/runtime/interpreter/mterp/arm/op_aput_short.S deleted file mode 100644 index f624163087..0000000000 --- a/runtime/interpreter/mterp/arm/op_aput_short.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aput_short(): -% op_aput(store="strh", shift="1", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/arm/op_aput_wide.S b/runtime/interpreter/mterp/arm/op_aput_wide.S deleted file mode 100644 index 769522a5ec..0000000000 --- a/runtime/interpreter/mterp/arm/op_aput_wide.S +++ /dev/null @@ -1,25 +0,0 @@ -%def op_aput_wide(): - /* - * Array put, 64 bits. vBB[vCC] <- vAA. - * - * Arrays of long/double are 64-bit aligned, so it's okay to use STRD. - */ - /* aput-wide vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - GET_VREG r0, r2 @ r0<- vBB (array object) - GET_VREG r1, r3 @ r1<- vCC (requested index) - cmp r0, #0 @ null array object? - beq common_errNullObject @ yes, bail - ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length - add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width - cmp r1, r3 @ compare unsigned index, length - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] - bcs common_errArrayIndex @ index >= length, bail - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - ldmia r9, {r2-r3} @ r2/r3<- vAA/vAA+1 - GET_INST_OPCODE ip @ extract opcode from rINST - strd r2, [r0, #MIRROR_WIDE_ARRAY_DATA_OFFSET] @ r2/r3<- vBB[vCC] - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_array_length.S b/runtime/interpreter/mterp/arm/op_array_length.S deleted file mode 100644 index 3ec24b8a3b..0000000000 --- a/runtime/interpreter/mterp/arm/op_array_length.S +++ /dev/null @@ -1,14 +0,0 @@ -%def op_array_length(): - /* - * Return the length of an array. - */ - mov r1, rINST, lsr #12 @ r1<- B - ubfx r2, rINST, #8, #4 @ r2<- A - GET_VREG r0, r1 @ r0<- vB (object ref) - cmp r0, #0 @ is object null? - beq common_errNullObject @ yup, fail - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- array length - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r3, r2 @ vB<- length - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_check_cast.S b/runtime/interpreter/mterp/arm/op_check_cast.S deleted file mode 100644 index a56451b5df..0000000000 --- a/runtime/interpreter/mterp/arm/op_check_cast.S +++ /dev/null @@ -1,18 +0,0 @@ -%def op_check_cast(): - /* - * Check to see if a cast from one class to another is allowed. - */ - /* check-cast vAA, class@BBBB */ - EXPORT_PC - FETCH r0, 1 @ r0<- BBBB - mov r1, rINST, lsr #8 @ r1<- AA - VREG_INDEX_TO_ADDR r1, r1 @ r1<- &object - ldr r2, [rFP, #OFF_FP_METHOD] @ r2<- method - mov r3, rSELF @ r3<- self - bl MterpCheckCast @ (index, &obj, method, self) - PREFETCH_INST 2 - cmp r0, #0 - bne MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_cmp_long.S b/runtime/interpreter/mterp/arm/op_cmp_long.S deleted file mode 100644 index 2f87716df7..0000000000 --- a/runtime/interpreter/mterp/arm/op_cmp_long.S +++ /dev/null @@ -1,24 +0,0 @@ -%def op_cmp_long(): - /* - * Compare two 64-bit values. Puts 0, 1, or -1 into the destination - * register based on the results of the comparison. - */ - /* cmp-long vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] - ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 - ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 - cmp r0, r2 - sbcs ip, r1, r3 @ Sets correct CCs for checking LT (but not EQ/NE) - mov ip, #0 - mvnlt ip, #0 @ -1 - cmpeq r0, r2 @ For correct EQ/NE, we may need to repeat the first CMP - orrne ip, #1 - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - SET_VREG ip, r9 @ vAA<- ip - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_cmpg_double.S b/runtime/interpreter/mterp/arm/op_cmpg_double.S deleted file mode 100644 index a166d16256..0000000000 --- a/runtime/interpreter/mterp/arm/op_cmpg_double.S +++ /dev/null @@ -1,35 +0,0 @@ -%def op_cmpg_double(): - /* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * int compare(x, y) { - * if (x == y) { - * return 0; - * } else if (x < y) { - * return -1; - * } else if (x > y) { - * return 1; - * } else { - * return 1; - * } - * } - */ - /* op vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC - fldd d0, [r2] @ d0<- vBB - fldd d1, [r3] @ d1<- vCC - vcmpe.f64 d0, d1 @ compare (vBB, vCC) - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - mov r0, #1 @ r0<- 1 (default) - GET_INST_OPCODE ip @ extract opcode from rINST - fmstat @ export status flags - mvnmi r0, #0 @ (less than) r1<- -1 - moveq r0, #0 @ (equal) r1<- 0 - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_cmpg_float.S b/runtime/interpreter/mterp/arm/op_cmpg_float.S deleted file mode 100644 index e14f4ec1a2..0000000000 --- a/runtime/interpreter/mterp/arm/op_cmpg_float.S +++ /dev/null @@ -1,35 +0,0 @@ -%def op_cmpg_float(): - /* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * int compare(x, y) { - * if (x == y) { - * return 0; - * } else if (x < y) { - * return -1; - * } else if (x > y) { - * return 1; - * } else { - * return 1; - * } - * } - */ - /* op vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC - flds s0, [r2] @ s0<- vBB - flds s1, [r3] @ s1<- vCC - vcmpe.f32 s0, s1 @ compare (vBB, vCC) - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - mov r0, #1 @ r0<- 1 (default) - GET_INST_OPCODE ip @ extract opcode from rINST - fmstat @ export status flags - mvnmi r0, #0 @ (less than) r1<- -1 - moveq r0, #0 @ (equal) r1<- 0 - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_cmpl_double.S b/runtime/interpreter/mterp/arm/op_cmpl_double.S deleted file mode 100644 index 44c827a9a3..0000000000 --- a/runtime/interpreter/mterp/arm/op_cmpl_double.S +++ /dev/null @@ -1,35 +0,0 @@ -%def op_cmpl_double(): - /* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * int compare(x, y) { - * if (x == y) { - * return 0; - * } else if (x > y) { - * return 1; - * } else if (x < y) { - * return -1; - * } else { - * return -1; - * } - * } - */ - /* op vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC - fldd d0, [r2] @ d0<- vBB - fldd d1, [r3] @ d1<- vCC - vcmpe.f64 d0, d1 @ compare (vBB, vCC) - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - mvn r0, #0 @ r0<- -1 (default) - GET_INST_OPCODE ip @ extract opcode from rINST - fmstat @ export status flags - movgt r0, #1 @ (greater than) r1<- 1 - moveq r0, #0 @ (equal) r1<- 0 - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_cmpl_float.S b/runtime/interpreter/mterp/arm/op_cmpl_float.S deleted file mode 100644 index c2026634e2..0000000000 --- a/runtime/interpreter/mterp/arm/op_cmpl_float.S +++ /dev/null @@ -1,35 +0,0 @@ -%def op_cmpl_float(): - /* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * int compare(x, y) { - * if (x == y) { - * return 0; - * } else if (x > y) { - * return 1; - * } else if (x < y) { - * return -1; - * } else { - * return -1; - * } - * } - */ - /* op vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC - flds s0, [r2] @ s0<- vBB - flds s1, [r3] @ s1<- vCC - vcmpe.f32 s0, s1 @ compare (vBB, vCC) - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - mvn r0, #0 @ r0<- -1 (default) - GET_INST_OPCODE ip @ extract opcode from rINST - fmstat @ export status flags - movgt r0, #1 @ (greater than) r1<- 1 - moveq r0, #0 @ (equal) r1<- 0 - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_const.S b/runtime/interpreter/mterp/arm/op_const.S deleted file mode 100644 index e5ef50e912..0000000000 --- a/runtime/interpreter/mterp/arm/op_const.S +++ /dev/null @@ -1,10 +0,0 @@ -%def op_const(): - /* const vAA, #+BBBBbbbb */ - mov r3, rINST, lsr #8 @ r3<- AA - FETCH r0, 1 @ r0<- bbbb (low) - FETCH r1, 2 @ r1<- BBBB (high) - FETCH_ADVANCE_INST 3 @ advance rPC, load rINST - orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r3 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_const_16.S b/runtime/interpreter/mterp/arm/op_const_16.S deleted file mode 100644 index 3bb89d08ad..0000000000 --- a/runtime/interpreter/mterp/arm/op_const_16.S +++ /dev/null @@ -1,8 +0,0 @@ -%def op_const_16(): - /* const/16 vAA, #+BBBB */ - FETCH_S r0, 1 @ r0<- ssssBBBB (sign-extended) - mov r3, rINST, lsr #8 @ r3<- AA - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - SET_VREG r0, r3 @ vAA<- r0 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_const_4.S b/runtime/interpreter/mterp/arm/op_const_4.S deleted file mode 100644 index bfb4246b0b..0000000000 --- a/runtime/interpreter/mterp/arm/op_const_4.S +++ /dev/null @@ -1,8 +0,0 @@ -%def op_const_4(): - /* const/4 vA, #+B */ - sbfx r1, rINST, #12, #4 @ r1<- sssssssB (sign-extended) - ubfx r0, rINST, #8, #4 @ r0<- A - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - GET_INST_OPCODE ip @ ip<- opcode from rINST - SET_VREG r1, r0 @ fp[A]<- r1 - GOTO_OPCODE ip @ execute next instruction diff --git a/runtime/interpreter/mterp/arm/op_const_class.S b/runtime/interpreter/mterp/arm/op_const_class.S deleted file mode 100644 index db12ec3141..0000000000 --- a/runtime/interpreter/mterp/arm/op_const_class.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_const_class(): -% const(helper="MterpConstClass") diff --git a/runtime/interpreter/mterp/arm/op_const_high16.S b/runtime/interpreter/mterp/arm/op_const_high16.S deleted file mode 100644 index 7f20e11f4c..0000000000 --- a/runtime/interpreter/mterp/arm/op_const_high16.S +++ /dev/null @@ -1,9 +0,0 @@ -%def op_const_high16(): - /* const/high16 vAA, #+BBBB0000 */ - FETCH r0, 1 @ r0<- 0000BBBB (zero-extended) - mov r3, rINST, lsr #8 @ r3<- AA - mov r0, r0, lsl #16 @ r0<- BBBB0000 - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - SET_VREG r0, r3 @ vAA<- r0 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_const_method_handle.S b/runtime/interpreter/mterp/arm/op_const_method_handle.S deleted file mode 100644 index 2680c17aad..0000000000 --- a/runtime/interpreter/mterp/arm/op_const_method_handle.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_const_method_handle(): -% const(helper="MterpConstMethodHandle") diff --git a/runtime/interpreter/mterp/arm/op_const_method_type.S b/runtime/interpreter/mterp/arm/op_const_method_type.S deleted file mode 100644 index ea814bf648..0000000000 --- a/runtime/interpreter/mterp/arm/op_const_method_type.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_const_method_type(): -% const(helper="MterpConstMethodType") diff --git a/runtime/interpreter/mterp/arm/op_const_string.S b/runtime/interpreter/mterp/arm/op_const_string.S deleted file mode 100644 index 41376f8703..0000000000 --- a/runtime/interpreter/mterp/arm/op_const_string.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_const_string(): -% const(helper="MterpConstString") diff --git a/runtime/interpreter/mterp/arm/op_const_string_jumbo.S b/runtime/interpreter/mterp/arm/op_const_string_jumbo.S deleted file mode 100644 index 29c9854f44..0000000000 --- a/runtime/interpreter/mterp/arm/op_const_string_jumbo.S +++ /dev/null @@ -1,16 +0,0 @@ -%def op_const_string_jumbo(): - /* const/string vAA, String@BBBBBBBB */ - EXPORT_PC - FETCH r0, 1 @ r0<- bbbb (low) - FETCH r2, 2 @ r2<- BBBB (high) - mov r1, rINST, lsr #8 @ r1<- AA - orr r0, r0, r2, lsl #16 @ r1<- BBBBbbbb - add r2, rFP, #OFF_FP_SHADOWFRAME - mov r3, rSELF - bl MterpConstString @ (index, tgt_reg, shadow_frame, self) - PREFETCH_INST 3 @ advance rPC - cmp r0, #0 @ fail? - bne MterpPossibleException @ let reference interpreter deal with it. - ADVANCE 3 @ advance rPC - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_const_wide.S b/runtime/interpreter/mterp/arm/op_const_wide.S deleted file mode 100644 index 40bac6d72b..0000000000 --- a/runtime/interpreter/mterp/arm/op_const_wide.S +++ /dev/null @@ -1,15 +0,0 @@ -%def op_const_wide(): - /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ - FETCH r0, 1 @ r0<- bbbb (low) - FETCH r1, 2 @ r1<- BBBB (low middle) - FETCH r2, 3 @ r2<- hhhh (high middle) - orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb (low word) - FETCH r3, 4 @ r3<- HHHH (high) - mov r9, rINST, lsr #8 @ r9<- AA - orr r1, r2, r3, lsl #16 @ r1<- HHHHhhhh (high word) - CLEAR_SHADOW_PAIR r9, r2, r3 @ Zero out the shadow regs - FETCH_ADVANCE_INST 5 @ advance rPC, load rINST - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vAA<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_const_wide_16.S b/runtime/interpreter/mterp/arm/op_const_wide_16.S deleted file mode 100644 index 7d334c997f..0000000000 --- a/runtime/interpreter/mterp/arm/op_const_wide_16.S +++ /dev/null @@ -1,11 +0,0 @@ -%def op_const_wide_16(): - /* const-wide/16 vAA, #+BBBB */ - FETCH_S r0, 1 @ r0<- ssssBBBB (sign-extended) - mov r3, rINST, lsr #8 @ r3<- AA - mov r1, r0, asr #31 @ r1<- ssssssss - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - CLEAR_SHADOW_PAIR r3, r2, lr @ Zero out the shadow regs - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[AA] - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r3, {r0-r1} @ vAA<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_const_wide_32.S b/runtime/interpreter/mterp/arm/op_const_wide_32.S deleted file mode 100644 index eeb5fa510e..0000000000 --- a/runtime/interpreter/mterp/arm/op_const_wide_32.S +++ /dev/null @@ -1,13 +0,0 @@ -%def op_const_wide_32(): - /* const-wide/32 vAA, #+BBBBbbbb */ - FETCH r0, 1 @ r0<- 0000bbbb (low) - mov r3, rINST, lsr #8 @ r3<- AA - FETCH_S r2, 2 @ r2<- ssssBBBB (high) - FETCH_ADVANCE_INST 3 @ advance rPC, load rINST - orr r0, r0, r2, lsl #16 @ r0<- BBBBbbbb - CLEAR_SHADOW_PAIR r3, r2, lr @ Zero out the shadow regs - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[AA] - mov r1, r0, asr #31 @ r1<- ssssssss - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r3, {r0-r1} @ vAA<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_const_wide_high16.S b/runtime/interpreter/mterp/arm/op_const_wide_high16.S deleted file mode 100644 index 57ce0242a1..0000000000 --- a/runtime/interpreter/mterp/arm/op_const_wide_high16.S +++ /dev/null @@ -1,12 +0,0 @@ -%def op_const_wide_high16(): - /* const-wide/high16 vAA, #+BBBB000000000000 */ - FETCH r1, 1 @ r1<- 0000BBBB (zero-extended) - mov r3, rINST, lsr #8 @ r3<- AA - mov r0, #0 @ r0<- 00000000 - mov r1, r1, lsl #16 @ r1<- BBBB0000 - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - CLEAR_SHADOW_PAIR r3, r0, r2 @ Zero shadow regs - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[AA] - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r3, {r0-r1} @ vAA<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_div_double.S b/runtime/interpreter/mterp/arm/op_div_double.S deleted file mode 100644 index d90969495d..0000000000 --- a/runtime/interpreter/mterp/arm/op_div_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_double(): -% fbinopWide(instr="fdivd d2, d0, d1") diff --git a/runtime/interpreter/mterp/arm/op_div_double_2addr.S b/runtime/interpreter/mterp/arm/op_div_double_2addr.S deleted file mode 100644 index 499c87b1e6..0000000000 --- a/runtime/interpreter/mterp/arm/op_div_double_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_double_2addr(): -% fbinopWide2addr(instr="fdivd d2, d0, d1") diff --git a/runtime/interpreter/mterp/arm/op_div_float.S b/runtime/interpreter/mterp/arm/op_div_float.S deleted file mode 100644 index 11369095be..0000000000 --- a/runtime/interpreter/mterp/arm/op_div_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_float(): -% fbinop(instr="fdivs s2, s0, s1") diff --git a/runtime/interpreter/mterp/arm/op_div_float_2addr.S b/runtime/interpreter/mterp/arm/op_div_float_2addr.S deleted file mode 100644 index 5198bc778f..0000000000 --- a/runtime/interpreter/mterp/arm/op_div_float_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_float_2addr(): -% fbinop2addr(instr="fdivs s2, s0, s1") diff --git a/runtime/interpreter/mterp/arm/op_div_int.S b/runtime/interpreter/mterp/arm/op_div_int.S deleted file mode 100644 index 211ac77296..0000000000 --- a/runtime/interpreter/mterp/arm/op_div_int.S +++ /dev/null @@ -1,30 +0,0 @@ -%def op_div_int(): - /* - * Specialized 32-bit binary operation - * - * Performs "r0 = r0 div r1". The selection between sdiv or the gcc helper - * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for - * ARMv7 CPUs that have hardware division support). - * - * div-int - * - */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - GET_VREG r1, r3 @ r1<- vCC - GET_VREG r0, r2 @ r0<- vBB - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST -#ifdef __ARM_ARCH_EXT_IDIV__ - sdiv r0, r0, r1 @ r0<- op -#else - bl __aeabi_idiv @ r0<- op, r0-r3 changed -#endif - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 11-14 instructions */ diff --git a/runtime/interpreter/mterp/arm/op_div_int_2addr.S b/runtime/interpreter/mterp/arm/op_div_int_2addr.S deleted file mode 100644 index 968a4991fa..0000000000 --- a/runtime/interpreter/mterp/arm/op_div_int_2addr.S +++ /dev/null @@ -1,29 +0,0 @@ -%def op_div_int_2addr(): - /* - * Specialized 32-bit binary operation - * - * Performs "r0 = r0 div r1". The selection between sdiv or the gcc helper - * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for - * ARMv7 CPUs that have hardware division support). - * - * div-int/2addr - * - */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r1, r3 @ r1<- vB - GET_VREG r0, r9 @ r0<- vA - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - -#ifdef __ARM_ARCH_EXT_IDIV__ - sdiv r0, r0, r1 @ r0<- op -#else - bl __aeabi_idiv @ r0<- op, r0-r3 changed -#endif - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - diff --git a/runtime/interpreter/mterp/arm/op_div_int_lit16.S b/runtime/interpreter/mterp/arm/op_div_int_lit16.S deleted file mode 100644 index f1e21269c7..0000000000 --- a/runtime/interpreter/mterp/arm/op_div_int_lit16.S +++ /dev/null @@ -1,28 +0,0 @@ -%def op_div_int_lit16(): - /* - * Specialized 32-bit binary operation - * - * Performs "r0 = r0 div r1". The selection between sdiv or the gcc helper - * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for - * ARMv7 CPUs that have hardware division support). - * - * div-int/lit16 - * - */ - FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) - mov r2, rINST, lsr #12 @ r2<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r0, r2 @ r0<- vB - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - -#ifdef __ARM_ARCH_EXT_IDIV__ - sdiv r0, r0, r1 @ r0<- op -#else - bl __aeabi_idiv @ r0<- op, r0-r3 changed -#endif - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ diff --git a/runtime/interpreter/mterp/arm/op_div_int_lit8.S b/runtime/interpreter/mterp/arm/op_div_int_lit8.S deleted file mode 100644 index e0d88f80df..0000000000 --- a/runtime/interpreter/mterp/arm/op_div_int_lit8.S +++ /dev/null @@ -1,29 +0,0 @@ -%def op_div_int_lit8(): - /* - * Specialized 32-bit binary operation - * - * Performs "r0 = r0 div r1". The selection between sdiv or the gcc helper - * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for - * ARMv7 CPUs that have hardware division support). - * - * div-int/lit8 - * - */ - FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r3, #255 @ r2<- BB - GET_VREG r0, r2 @ r0<- vBB - movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) - @cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - -#ifdef __ARM_ARCH_EXT_IDIV__ - sdiv r0, r0, r1 @ r0<- op -#else - bl __aeabi_idiv @ r0<- op, r0-r3 changed -#endif - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-12 instructions */ diff --git a/runtime/interpreter/mterp/arm/op_div_long.S b/runtime/interpreter/mterp/arm/op_div_long.S deleted file mode 100644 index 7423f5bfa8..0000000000 --- a/runtime/interpreter/mterp/arm/op_div_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_long(): -% binopWide(instr="bl __aeabi_ldivmod", chkzero="1") diff --git a/runtime/interpreter/mterp/arm/op_div_long_2addr.S b/runtime/interpreter/mterp/arm/op_div_long_2addr.S deleted file mode 100644 index fed8b8f3d7..0000000000 --- a/runtime/interpreter/mterp/arm/op_div_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_long_2addr(): -% binopWide2addr(instr="bl __aeabi_ldivmod", chkzero="1") diff --git a/runtime/interpreter/mterp/arm/op_double_to_float.S b/runtime/interpreter/mterp/arm/op_double_to_float.S deleted file mode 100644 index dcd575e3f1..0000000000 --- a/runtime/interpreter/mterp/arm/op_double_to_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_double_to_float(): -% funopNarrower(instr="vcvt.f32.f64 s0, d0") diff --git a/runtime/interpreter/mterp/arm/op_double_to_int.S b/runtime/interpreter/mterp/arm/op_double_to_int.S deleted file mode 100644 index e11daad495..0000000000 --- a/runtime/interpreter/mterp/arm/op_double_to_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_double_to_int(): -% funopNarrower(instr="ftosizd s0, d0") diff --git a/runtime/interpreter/mterp/arm/op_double_to_long.S b/runtime/interpreter/mterp/arm/op_double_to_long.S deleted file mode 100644 index c47570430e..0000000000 --- a/runtime/interpreter/mterp/arm/op_double_to_long.S +++ /dev/null @@ -1,34 +0,0 @@ -%def op_double_to_long(): -% unopWide(instr="bl d2l_doconv") - -%def op_double_to_long_sister_code(): -/* - * Convert the double in r0/r1 to a long in r0/r1. - * - * We have to clip values to long min/max per the specification. The - * expected common case is a "reasonable" value that converts directly - * to modest integer. The EABI convert function isn't doing this for us. - */ -d2l_doconv: - ubfx r2, r1, #20, #11 @ grab the exponent - movw r3, #0x43e - cmp r2, r3 @ MINLONG < x > MAXLONG? - bhs d2l_special_cases - b __aeabi_d2lz @ tail call to convert double to long -d2l_special_cases: - movw r3, #0x7ff - cmp r2, r3 - beq d2l_maybeNaN @ NaN? -d2l_notNaN: - adds r1, r1, r1 @ sign bit to carry - mov r0, #0xffffffff @ assume maxlong for lsw - mov r1, #0x7fffffff @ assume maxlong for msw - adc r0, r0, #0 - adc r1, r1, #0 @ convert maxlong to minlong if exp negative - bx lr @ return -d2l_maybeNaN: - orrs r3, r0, r1, lsl #12 - beq d2l_notNaN @ if fraction is non-zero, it's a NaN - mov r0, #0 - mov r1, #0 - bx lr @ return 0 for NaN diff --git a/runtime/interpreter/mterp/arm/op_fill_array_data.S b/runtime/interpreter/mterp/arm/op_fill_array_data.S deleted file mode 100644 index ea0d39724d..0000000000 --- a/runtime/interpreter/mterp/arm/op_fill_array_data.S +++ /dev/null @@ -1,15 +0,0 @@ -%def op_fill_array_data(): - /* fill-array-data vAA, +BBBBBBBB */ - EXPORT_PC - FETCH r0, 1 @ r0<- bbbb (lo) - FETCH r1, 2 @ r1<- BBBB (hi) - mov r3, rINST, lsr #8 @ r3<- AA - orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb - GET_VREG r0, r3 @ r0<- vAA (array object) - add r1, rPC, r1, lsl #1 @ r1<- PC + BBBBbbbb*2 (array data off.) - bl MterpFillArrayData @ (obj, payload) - cmp r0, #0 @ 0 means an exception is thrown - beq MterpPossibleException @ exception? - FETCH_ADVANCE_INST 3 @ advance rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_filled_new_array.S b/runtime/interpreter/mterp/arm/op_filled_new_array.S deleted file mode 100644 index fb1c3c5dc3..0000000000 --- a/runtime/interpreter/mterp/arm/op_filled_new_array.S +++ /dev/null @@ -1,19 +0,0 @@ -%def op_filled_new_array(helper="MterpFilledNewArray"): - /* - * Create a new array with elements filled from registers. - * - * for: filled-new-array, filled-new-array/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ - .extern $helper - EXPORT_PC - add r0, rFP, #OFF_FP_SHADOWFRAME - mov r1, rPC - mov r2, rSELF - bl $helper - cmp r0, #0 - beq MterpPossibleException - FETCH_ADVANCE_INST 3 @ advance rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_filled_new_array_range.S b/runtime/interpreter/mterp/arm/op_filled_new_array_range.S deleted file mode 100644 index 1667de149a..0000000000 --- a/runtime/interpreter/mterp/arm/op_filled_new_array_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_filled_new_array_range(): -% op_filled_new_array(helper="MterpFilledNewArrayRange") diff --git a/runtime/interpreter/mterp/arm/op_float_to_double.S b/runtime/interpreter/mterp/arm/op_float_to_double.S deleted file mode 100644 index 760466eec9..0000000000 --- a/runtime/interpreter/mterp/arm/op_float_to_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_float_to_double(): -% funopWider(instr="vcvt.f64.f32 d0, s0") diff --git a/runtime/interpreter/mterp/arm/op_float_to_int.S b/runtime/interpreter/mterp/arm/op_float_to_int.S deleted file mode 100644 index 77837ba3d5..0000000000 --- a/runtime/interpreter/mterp/arm/op_float_to_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_float_to_int(): -% funop(instr="ftosizs s1, s0") diff --git a/runtime/interpreter/mterp/arm/op_float_to_long.S b/runtime/interpreter/mterp/arm/op_float_to_long.S deleted file mode 100644 index 482b18e69f..0000000000 --- a/runtime/interpreter/mterp/arm/op_float_to_long.S +++ /dev/null @@ -1,32 +0,0 @@ -%def op_float_to_long(): -% unopWider(instr="bl f2l_doconv") - -%def op_float_to_long_sister_code(): -/* - * Convert the float in r0 to a long in r0/r1. - * - * We have to clip values to long min/max per the specification. The - * expected common case is a "reasonable" value that converts directly - * to modest integer. The EABI convert function isn't doing this for us. - */ -f2l_doconv: - ubfx r2, r0, #23, #8 @ grab the exponent - cmp r2, #0xbe @ MININT < x > MAXINT? - bhs f2l_special_cases - b __aeabi_f2lz @ tail call to convert float to long -f2l_special_cases: - cmp r2, #0xff @ NaN or infinity? - beq f2l_maybeNaN -f2l_notNaN: - adds r0, r0, r0 @ sign bit to carry - mov r0, #0xffffffff @ assume maxlong for lsw - mov r1, #0x7fffffff @ assume maxlong for msw - adc r0, r0, #0 - adc r1, r1, #0 @ convert maxlong to minlong if exp negative - bx lr @ return -f2l_maybeNaN: - lsls r3, r0, #9 - beq f2l_notNaN @ if fraction is non-zero, it's a NaN - mov r0, #0 - mov r1, #0 - bx lr @ return 0 for NaN diff --git a/runtime/interpreter/mterp/arm/op_goto.S b/runtime/interpreter/mterp/arm/op_goto.S deleted file mode 100644 index 832a989339..0000000000 --- a/runtime/interpreter/mterp/arm/op_goto.S +++ /dev/null @@ -1,10 +0,0 @@ -%def op_goto(): - /* - * Unconditional branch, 8-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto +AA */ - sbfx rINST, rINST, #8, #8 @ rINST<- ssssssAA (sign-extended) - b MterpCommonTakenBranchNoFlags diff --git a/runtime/interpreter/mterp/arm/op_goto_16.S b/runtime/interpreter/mterp/arm/op_goto_16.S deleted file mode 100644 index 4324a8d666..0000000000 --- a/runtime/interpreter/mterp/arm/op_goto_16.S +++ /dev/null @@ -1,10 +0,0 @@ -%def op_goto_16(): - /* - * Unconditional branch, 16-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto/16 +AAAA */ - FETCH_S rINST, 1 @ rINST<- ssssAAAA (sign-extended) - b MterpCommonTakenBranchNoFlags diff --git a/runtime/interpreter/mterp/arm/op_goto_32.S b/runtime/interpreter/mterp/arm/op_goto_32.S deleted file mode 100644 index b01d2fa719..0000000000 --- a/runtime/interpreter/mterp/arm/op_goto_32.S +++ /dev/null @@ -1,17 +0,0 @@ -%def op_goto_32(): - /* - * Unconditional branch, 32-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - * - * Unlike most opcodes, this one is allowed to branch to itself, so - * our "backward branch" test must be "<=0" instead of "<0". Because - * we need the V bit set, we'll use an adds to convert from Dalvik - * offset to byte offset. - */ - /* goto/32 +AAAAAAAA */ - FETCH r0, 1 @ r0<- aaaa (lo) - FETCH r3, 2 @ r1<- AAAA (hi) - orrs rINST, r0, r3, lsl #16 @ rINST<- AAAAaaaa - b MterpCommonTakenBranch diff --git a/runtime/interpreter/mterp/arm/op_if_eq.S b/runtime/interpreter/mterp/arm/op_if_eq.S deleted file mode 100644 index da58674fd4..0000000000 --- a/runtime/interpreter/mterp/arm/op_if_eq.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_eq(): -% bincmp(condition="eq") diff --git a/runtime/interpreter/mterp/arm/op_if_eqz.S b/runtime/interpreter/mterp/arm/op_if_eqz.S deleted file mode 100644 index 0639664d47..0000000000 --- a/runtime/interpreter/mterp/arm/op_if_eqz.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_eqz(): -% zcmp(condition="eq") diff --git a/runtime/interpreter/mterp/arm/op_if_ge.S b/runtime/interpreter/mterp/arm/op_if_ge.S deleted file mode 100644 index 5b6ed2f994..0000000000 --- a/runtime/interpreter/mterp/arm/op_if_ge.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_ge(): -% bincmp(condition="ge") diff --git a/runtime/interpreter/mterp/arm/op_if_gez.S b/runtime/interpreter/mterp/arm/op_if_gez.S deleted file mode 100644 index ea6cda71fb..0000000000 --- a/runtime/interpreter/mterp/arm/op_if_gez.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_gez(): -% zcmp(condition="ge") diff --git a/runtime/interpreter/mterp/arm/op_if_gt.S b/runtime/interpreter/mterp/arm/op_if_gt.S deleted file mode 100644 index 201decff1a..0000000000 --- a/runtime/interpreter/mterp/arm/op_if_gt.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_gt(): -% bincmp(condition="gt") diff --git a/runtime/interpreter/mterp/arm/op_if_gtz.S b/runtime/interpreter/mterp/arm/op_if_gtz.S deleted file mode 100644 index 1fdbb6e8d2..0000000000 --- a/runtime/interpreter/mterp/arm/op_if_gtz.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_gtz(): -% zcmp(condition="gt") diff --git a/runtime/interpreter/mterp/arm/op_if_le.S b/runtime/interpreter/mterp/arm/op_if_le.S deleted file mode 100644 index e6024f2b3e..0000000000 --- a/runtime/interpreter/mterp/arm/op_if_le.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_le(): -% bincmp(condition="le") diff --git a/runtime/interpreter/mterp/arm/op_if_lez.S b/runtime/interpreter/mterp/arm/op_if_lez.S deleted file mode 100644 index 62c0d2cd39..0000000000 --- a/runtime/interpreter/mterp/arm/op_if_lez.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_lez(): -% zcmp(condition="le") diff --git a/runtime/interpreter/mterp/arm/op_if_lt.S b/runtime/interpreter/mterp/arm/op_if_lt.S deleted file mode 100644 index 4ef22fd798..0000000000 --- a/runtime/interpreter/mterp/arm/op_if_lt.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_lt(): -% bincmp(condition="lt") diff --git a/runtime/interpreter/mterp/arm/op_if_ltz.S b/runtime/interpreter/mterp/arm/op_if_ltz.S deleted file mode 100644 index 84b2d0b53a..0000000000 --- a/runtime/interpreter/mterp/arm/op_if_ltz.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_ltz(): -% zcmp(condition="lt") diff --git a/runtime/interpreter/mterp/arm/op_if_ne.S b/runtime/interpreter/mterp/arm/op_if_ne.S deleted file mode 100644 index ec3a688b29..0000000000 --- a/runtime/interpreter/mterp/arm/op_if_ne.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_ne(): -% bincmp(condition="ne") diff --git a/runtime/interpreter/mterp/arm/op_if_nez.S b/runtime/interpreter/mterp/arm/op_if_nez.S deleted file mode 100644 index 7009c3acaa..0000000000 --- a/runtime/interpreter/mterp/arm/op_if_nez.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_nez(): -% zcmp(condition="ne") diff --git a/runtime/interpreter/mterp/arm/op_iget.S b/runtime/interpreter/mterp/arm/op_iget.S deleted file mode 100644 index d09edc0a17..0000000000 --- a/runtime/interpreter/mterp/arm/op_iget.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget(is_object="0", helper="MterpIGetU32"): -% field(helper=helper) diff --git a/runtime/interpreter/mterp/arm/op_iget_boolean.S b/runtime/interpreter/mterp/arm/op_iget_boolean.S deleted file mode 100644 index cb8edeec77..0000000000 --- a/runtime/interpreter/mterp/arm/op_iget_boolean.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_boolean(): -% op_iget(helper="MterpIGetU8") diff --git a/runtime/interpreter/mterp/arm/op_iget_boolean_quick.S b/runtime/interpreter/mterp/arm/op_iget_boolean_quick.S deleted file mode 100644 index 7ac9fce535..0000000000 --- a/runtime/interpreter/mterp/arm/op_iget_boolean_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_boolean_quick(): -% op_iget_quick(load="ldrb") diff --git a/runtime/interpreter/mterp/arm/op_iget_byte.S b/runtime/interpreter/mterp/arm/op_iget_byte.S deleted file mode 100644 index 2b87fb16b5..0000000000 --- a/runtime/interpreter/mterp/arm/op_iget_byte.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_byte(): -% op_iget(helper="MterpIGetI8") diff --git a/runtime/interpreter/mterp/arm/op_iget_byte_quick.S b/runtime/interpreter/mterp/arm/op_iget_byte_quick.S deleted file mode 100644 index bbccaffe94..0000000000 --- a/runtime/interpreter/mterp/arm/op_iget_byte_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_byte_quick(): -% op_iget_quick(load="ldrsb") diff --git a/runtime/interpreter/mterp/arm/op_iget_char.S b/runtime/interpreter/mterp/arm/op_iget_char.S deleted file mode 100644 index 001bd03e2b..0000000000 --- a/runtime/interpreter/mterp/arm/op_iget_char.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_char(): -% op_iget(helper="MterpIGetU16") diff --git a/runtime/interpreter/mterp/arm/op_iget_char_quick.S b/runtime/interpreter/mterp/arm/op_iget_char_quick.S deleted file mode 100644 index 71a9276a81..0000000000 --- a/runtime/interpreter/mterp/arm/op_iget_char_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_char_quick(): -% op_iget_quick(load="ldrh") diff --git a/runtime/interpreter/mterp/arm/op_iget_object.S b/runtime/interpreter/mterp/arm/op_iget_object.S deleted file mode 100644 index 4e5f769547..0000000000 --- a/runtime/interpreter/mterp/arm/op_iget_object.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_object(): -% op_iget(is_object="1", helper="MterpIGetObj") diff --git a/runtime/interpreter/mterp/arm/op_iget_object_quick.S b/runtime/interpreter/mterp/arm/op_iget_object_quick.S deleted file mode 100644 index 72b04b8bb0..0000000000 --- a/runtime/interpreter/mterp/arm/op_iget_object_quick.S +++ /dev/null @@ -1,17 +0,0 @@ -%def op_iget_object_quick(): - /* For: iget-object-quick */ - /* op vA, vB, offset@CCCC */ - mov r2, rINST, lsr #12 @ r2<- B - FETCH r1, 1 @ r1<- field byte offset - EXPORT_PC - GET_VREG r0, r2 @ r0<- object we're operating on - bl artIGetObjectFromMterp @ (obj, offset) - ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] - ubfx r2, rINST, #8, #4 @ r2<- A - PREFETCH_INST 2 - cmp r3, #0 - bne MterpPossibleException @ bail out - SET_VREG_OBJECT r0, r2 @ fp[A]<- r0 - ADVANCE 2 @ advance rPC - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_iget_quick.S b/runtime/interpreter/mterp/arm/op_iget_quick.S deleted file mode 100644 index 989449867d..0000000000 --- a/runtime/interpreter/mterp/arm/op_iget_quick.S +++ /dev/null @@ -1,14 +0,0 @@ -%def op_iget_quick(load="ldr"): - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset@CCCC */ - mov r2, rINST, lsr #12 @ r2<- B - FETCH r1, 1 @ r1<- field byte offset - GET_VREG r3, r2 @ r3<- object we're operating on - ubfx r2, rINST, #8, #4 @ r2<- A - cmp r3, #0 @ check object for null - beq common_errNullObject @ object was null - $load r0, [r3, r1] @ r0<- obj.field - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - SET_VREG r0, r2 @ fp[A]<- r0 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_iget_short.S b/runtime/interpreter/mterp/arm/op_iget_short.S deleted file mode 100644 index a62c4d998f..0000000000 --- a/runtime/interpreter/mterp/arm/op_iget_short.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_short(): -% op_iget(helper="MterpIGetI16") diff --git a/runtime/interpreter/mterp/arm/op_iget_short_quick.S b/runtime/interpreter/mterp/arm/op_iget_short_quick.S deleted file mode 100644 index 5dbdc4fa22..0000000000 --- a/runtime/interpreter/mterp/arm/op_iget_short_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_short_quick(): -% op_iget_quick(load="ldrsh") diff --git a/runtime/interpreter/mterp/arm/op_iget_wide.S b/runtime/interpreter/mterp/arm/op_iget_wide.S deleted file mode 100644 index 9643cc3403..0000000000 --- a/runtime/interpreter/mterp/arm/op_iget_wide.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_wide(): -% op_iget(helper="MterpIGetU64") diff --git a/runtime/interpreter/mterp/arm/op_iget_wide_quick.S b/runtime/interpreter/mterp/arm/op_iget_wide_quick.S deleted file mode 100644 index e247fb2640..0000000000 --- a/runtime/interpreter/mterp/arm/op_iget_wide_quick.S +++ /dev/null @@ -1,15 +0,0 @@ -%def op_iget_wide_quick(): - /* iget-wide-quick vA, vB, offset@CCCC */ - mov r2, rINST, lsr #12 @ r2<- B - FETCH ip, 1 @ ip<- field byte offset - GET_VREG r3, r2 @ r3<- object we're operating on - ubfx r2, rINST, #8, #4 @ r2<- A - cmp r3, #0 @ check object for null - beq common_errNullObject @ object was null - ldrd r0, [r3, ip] @ r0<- obj.field (64 bits, aligned) - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - VREG_INDEX_TO_ADDR r3, r2 @ r3<- &fp[A] - CLEAR_SHADOW_PAIR r2, ip, lr @ Zero out the shadow regs - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r3, {r0-r1} @ fp[A]<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_instance_of.S b/runtime/interpreter/mterp/arm/op_instance_of.S deleted file mode 100644 index 020b4c5fea..0000000000 --- a/runtime/interpreter/mterp/arm/op_instance_of.S +++ /dev/null @@ -1,24 +0,0 @@ -%def op_instance_of(): - /* - * Check to see if an object reference is an instance of a class. - * - * Most common situation is a non-null object, being compared against - * an already-resolved class. - */ - /* instance-of vA, vB, class@CCCC */ - EXPORT_PC - FETCH r0, 1 @ r0<- CCCC - mov r1, rINST, lsr #12 @ r1<- B - VREG_INDEX_TO_ADDR r1, r1 @ r1<- &object - ldr r2, [rFP, #OFF_FP_METHOD] @ r2<- method - mov r3, rSELF @ r3<- self - bl MterpInstanceOf @ (index, &obj, method, self) - ldr r1, [rSELF, #THREAD_EXCEPTION_OFFSET] - ubfx r9, rINST, #8, #4 @ r9<- A - PREFETCH_INST 2 - cmp r1, #0 @ exception pending? - bne MterpException - ADVANCE 2 @ advance rPC - SET_VREG r0, r9 @ vA<- r0 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_int_to_byte.S b/runtime/interpreter/mterp/arm/op_int_to_byte.S deleted file mode 100644 index 3229b5ecf7..0000000000 --- a/runtime/interpreter/mterp/arm/op_int_to_byte.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_int_to_byte(): -% unop(instr="sxtb r0, r0") diff --git a/runtime/interpreter/mterp/arm/op_int_to_char.S b/runtime/interpreter/mterp/arm/op_int_to_char.S deleted file mode 100644 index 9ce13b8b6e..0000000000 --- a/runtime/interpreter/mterp/arm/op_int_to_char.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_int_to_char(): -% unop(instr="uxth r0, r0") diff --git a/runtime/interpreter/mterp/arm/op_int_to_double.S b/runtime/interpreter/mterp/arm/op_int_to_double.S deleted file mode 100644 index cc8065a9bc..0000000000 --- a/runtime/interpreter/mterp/arm/op_int_to_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_int_to_double(): -% funopWider(instr="fsitod d0, s0") diff --git a/runtime/interpreter/mterp/arm/op_int_to_float.S b/runtime/interpreter/mterp/arm/op_int_to_float.S deleted file mode 100644 index b19f3f3164..0000000000 --- a/runtime/interpreter/mterp/arm/op_int_to_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_int_to_float(): -% funop(instr="fsitos s1, s0") diff --git a/runtime/interpreter/mterp/arm/op_int_to_long.S b/runtime/interpreter/mterp/arm/op_int_to_long.S deleted file mode 100644 index 8d678991a4..0000000000 --- a/runtime/interpreter/mterp/arm/op_int_to_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_int_to_long(): -% unopWider(instr="mov r1, r0, asr #31") diff --git a/runtime/interpreter/mterp/arm/op_int_to_short.S b/runtime/interpreter/mterp/arm/op_int_to_short.S deleted file mode 100644 index 2332460e07..0000000000 --- a/runtime/interpreter/mterp/arm/op_int_to_short.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_int_to_short(): -% unop(instr="sxth r0, r0") diff --git a/runtime/interpreter/mterp/arm/op_invoke_custom.S b/runtime/interpreter/mterp/arm/op_invoke_custom.S deleted file mode 100644 index 0bd29b453a..0000000000 --- a/runtime/interpreter/mterp/arm/op_invoke_custom.S +++ /dev/null @@ -1,9 +0,0 @@ -%def op_invoke_custom(): -% invoke(helper="MterpInvokeCustom") - /* - * Handle an invoke-custom invocation. - * - * for: invoke-custom, invoke-custom/range - */ - /* op vB, {vD, vE, vF, vG, vA}, call_site@BBBB */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, call_site@BBBB */ diff --git a/runtime/interpreter/mterp/arm/op_invoke_custom_range.S b/runtime/interpreter/mterp/arm/op_invoke_custom_range.S deleted file mode 100644 index 57e61af1fa..0000000000 --- a/runtime/interpreter/mterp/arm/op_invoke_custom_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_custom_range(): -% invoke(helper="MterpInvokeCustomRange") diff --git a/runtime/interpreter/mterp/arm/op_invoke_direct.S b/runtime/interpreter/mterp/arm/op_invoke_direct.S deleted file mode 100644 index d3139cf39b..0000000000 --- a/runtime/interpreter/mterp/arm/op_invoke_direct.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_direct(): -% invoke(helper="MterpInvokeDirect") diff --git a/runtime/interpreter/mterp/arm/op_invoke_direct_range.S b/runtime/interpreter/mterp/arm/op_invoke_direct_range.S deleted file mode 100644 index b4a161f48b..0000000000 --- a/runtime/interpreter/mterp/arm/op_invoke_direct_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_direct_range(): -% invoke(helper="MterpInvokeDirectRange") diff --git a/runtime/interpreter/mterp/arm/op_invoke_interface.S b/runtime/interpreter/mterp/arm/op_invoke_interface.S deleted file mode 100644 index b064126253..0000000000 --- a/runtime/interpreter/mterp/arm/op_invoke_interface.S +++ /dev/null @@ -1,9 +0,0 @@ -%def op_invoke_interface(): -% invoke(helper="MterpInvokeInterface") - /* - * Handle an interface method call. - * - * for: invoke-interface, invoke-interface/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ diff --git a/runtime/interpreter/mterp/arm/op_invoke_interface_range.S b/runtime/interpreter/mterp/arm/op_invoke_interface_range.S deleted file mode 100644 index 2989115377..0000000000 --- a/runtime/interpreter/mterp/arm/op_invoke_interface_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_interface_range(): -% invoke(helper="MterpInvokeInterfaceRange") diff --git a/runtime/interpreter/mterp/arm/op_invoke_polymorphic.S b/runtime/interpreter/mterp/arm/op_invoke_polymorphic.S deleted file mode 100644 index ce61f5aa0e..0000000000 --- a/runtime/interpreter/mterp/arm/op_invoke_polymorphic.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_polymorphic(): -% invoke_polymorphic(helper="MterpInvokePolymorphic") diff --git a/runtime/interpreter/mterp/arm/op_invoke_polymorphic_range.S b/runtime/interpreter/mterp/arm/op_invoke_polymorphic_range.S deleted file mode 100644 index 16731bdb40..0000000000 --- a/runtime/interpreter/mterp/arm/op_invoke_polymorphic_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_polymorphic_range(): -% invoke_polymorphic(helper="MterpInvokePolymorphicRange") diff --git a/runtime/interpreter/mterp/arm/op_invoke_static.S b/runtime/interpreter/mterp/arm/op_invoke_static.S deleted file mode 100644 index 3e38d36a27..0000000000 --- a/runtime/interpreter/mterp/arm/op_invoke_static.S +++ /dev/null @@ -1,3 +0,0 @@ -%def op_invoke_static(): -% invoke(helper="MterpInvokeStatic") - diff --git a/runtime/interpreter/mterp/arm/op_invoke_static_range.S b/runtime/interpreter/mterp/arm/op_invoke_static_range.S deleted file mode 100644 index e0a546c92b..0000000000 --- a/runtime/interpreter/mterp/arm/op_invoke_static_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_static_range(): -% invoke(helper="MterpInvokeStaticRange") diff --git a/runtime/interpreter/mterp/arm/op_invoke_super.S b/runtime/interpreter/mterp/arm/op_invoke_super.S deleted file mode 100644 index 3c34c9942e..0000000000 --- a/runtime/interpreter/mterp/arm/op_invoke_super.S +++ /dev/null @@ -1,9 +0,0 @@ -%def op_invoke_super(): -% invoke(helper="MterpInvokeSuper") - /* - * Handle a "super" method call. - * - * for: invoke-super, invoke-super/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ diff --git a/runtime/interpreter/mterp/arm/op_invoke_super_range.S b/runtime/interpreter/mterp/arm/op_invoke_super_range.S deleted file mode 100644 index caeafaa13c..0000000000 --- a/runtime/interpreter/mterp/arm/op_invoke_super_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_super_range(): -% invoke(helper="MterpInvokeSuperRange") diff --git a/runtime/interpreter/mterp/arm/op_invoke_virtual.S b/runtime/interpreter/mterp/arm/op_invoke_virtual.S deleted file mode 100644 index 249177b813..0000000000 --- a/runtime/interpreter/mterp/arm/op_invoke_virtual.S +++ /dev/null @@ -1,9 +0,0 @@ -%def op_invoke_virtual(): -% invoke(helper="MterpInvokeVirtual") - /* - * Handle a virtual method call. - * - * for: invoke-virtual, invoke-virtual/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ diff --git a/runtime/interpreter/mterp/arm/op_invoke_virtual_quick.S b/runtime/interpreter/mterp/arm/op_invoke_virtual_quick.S deleted file mode 100644 index ea72c171ec..0000000000 --- a/runtime/interpreter/mterp/arm/op_invoke_virtual_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_virtual_quick(): -% invoke(helper="MterpInvokeVirtualQuick") diff --git a/runtime/interpreter/mterp/arm/op_invoke_virtual_range.S b/runtime/interpreter/mterp/arm/op_invoke_virtual_range.S deleted file mode 100644 index baa0779593..0000000000 --- a/runtime/interpreter/mterp/arm/op_invoke_virtual_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_virtual_range(): -% invoke(helper="MterpInvokeVirtualRange") diff --git a/runtime/interpreter/mterp/arm/op_invoke_virtual_range_quick.S b/runtime/interpreter/mterp/arm/op_invoke_virtual_range_quick.S deleted file mode 100644 index 1d961a0781..0000000000 --- a/runtime/interpreter/mterp/arm/op_invoke_virtual_range_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_virtual_range_quick(): -% invoke(helper="MterpInvokeVirtualQuickRange") diff --git a/runtime/interpreter/mterp/arm/op_iput.S b/runtime/interpreter/mterp/arm/op_iput.S deleted file mode 100644 index e5351baf55..0000000000 --- a/runtime/interpreter/mterp/arm/op_iput.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput(is_object="0", helper="MterpIPutU32"): -% field(helper=helper) diff --git a/runtime/interpreter/mterp/arm/op_iput_boolean.S b/runtime/interpreter/mterp/arm/op_iput_boolean.S deleted file mode 100644 index 9eb849877b..0000000000 --- a/runtime/interpreter/mterp/arm/op_iput_boolean.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_boolean(): -% op_iput(helper="MterpIPutU8") diff --git a/runtime/interpreter/mterp/arm/op_iput_boolean_quick.S b/runtime/interpreter/mterp/arm/op_iput_boolean_quick.S deleted file mode 100644 index fd077a7792..0000000000 --- a/runtime/interpreter/mterp/arm/op_iput_boolean_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_boolean_quick(): -% op_iput_quick(store="strb") diff --git a/runtime/interpreter/mterp/arm/op_iput_byte.S b/runtime/interpreter/mterp/arm/op_iput_byte.S deleted file mode 100644 index 4b74f9fb0e..0000000000 --- a/runtime/interpreter/mterp/arm/op_iput_byte.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_byte(): -% op_iput(helper="MterpIPutI8") diff --git a/runtime/interpreter/mterp/arm/op_iput_byte_quick.S b/runtime/interpreter/mterp/arm/op_iput_byte_quick.S deleted file mode 100644 index 30238cf354..0000000000 --- a/runtime/interpreter/mterp/arm/op_iput_byte_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_byte_quick(): -% op_iput_quick(store="strb") diff --git a/runtime/interpreter/mterp/arm/op_iput_char.S b/runtime/interpreter/mterp/arm/op_iput_char.S deleted file mode 100644 index 64a249fc12..0000000000 --- a/runtime/interpreter/mterp/arm/op_iput_char.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_char(): -% op_iput(helper="MterpIPutU16") diff --git a/runtime/interpreter/mterp/arm/op_iput_char_quick.S b/runtime/interpreter/mterp/arm/op_iput_char_quick.S deleted file mode 100644 index 0deff56503..0000000000 --- a/runtime/interpreter/mterp/arm/op_iput_char_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_char_quick(): -% op_iput_quick(store="strh") diff --git a/runtime/interpreter/mterp/arm/op_iput_object.S b/runtime/interpreter/mterp/arm/op_iput_object.S deleted file mode 100644 index 131edd5dbd..0000000000 --- a/runtime/interpreter/mterp/arm/op_iput_object.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_object(): -% op_iput(is_object="1", helper="MterpIPutObj") diff --git a/runtime/interpreter/mterp/arm/op_iput_object_quick.S b/runtime/interpreter/mterp/arm/op_iput_object_quick.S deleted file mode 100644 index be90b840e6..0000000000 --- a/runtime/interpreter/mterp/arm/op_iput_object_quick.S +++ /dev/null @@ -1,11 +0,0 @@ -%def op_iput_object_quick(): - EXPORT_PC - add r0, rFP, #OFF_FP_SHADOWFRAME - mov r1, rPC - mov r2, rINST - bl MterpIputObjectQuick - cmp r0, #0 - beq MterpException - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_iput_quick.S b/runtime/interpreter/mterp/arm/op_iput_quick.S deleted file mode 100644 index f84c0982f3..0000000000 --- a/runtime/interpreter/mterp/arm/op_iput_quick.S +++ /dev/null @@ -1,14 +0,0 @@ -%def op_iput_quick(store="str"): - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - mov r2, rINST, lsr #12 @ r2<- B - FETCH r1, 1 @ r1<- field byte offset - GET_VREG r3, r2 @ r3<- fp[B], the object pointer - ubfx r2, rINST, #8, #4 @ r2<- A - cmp r3, #0 @ check object for null - beq common_errNullObject @ object was null - GET_VREG r0, r2 @ r0<- fp[A] - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - $store r0, [r3, r1] @ obj.field<- r0 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_iput_short.S b/runtime/interpreter/mterp/arm/op_iput_short.S deleted file mode 100644 index e631a3b259..0000000000 --- a/runtime/interpreter/mterp/arm/op_iput_short.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_short(): -% op_iput(helper="MterpIPutI16") diff --git a/runtime/interpreter/mterp/arm/op_iput_short_quick.S b/runtime/interpreter/mterp/arm/op_iput_short_quick.S deleted file mode 100644 index 6a1b65194e..0000000000 --- a/runtime/interpreter/mterp/arm/op_iput_short_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_short_quick(): -% op_iput_quick(store="strh") diff --git a/runtime/interpreter/mterp/arm/op_iput_wide.S b/runtime/interpreter/mterp/arm/op_iput_wide.S deleted file mode 100644 index 2f34fd39f9..0000000000 --- a/runtime/interpreter/mterp/arm/op_iput_wide.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_wide(): -% op_iput(helper="MterpIPutU64") diff --git a/runtime/interpreter/mterp/arm/op_iput_wide_quick.S b/runtime/interpreter/mterp/arm/op_iput_wide_quick.S deleted file mode 100644 index 8408f0a924..0000000000 --- a/runtime/interpreter/mterp/arm/op_iput_wide_quick.S +++ /dev/null @@ -1,14 +0,0 @@ -%def op_iput_wide_quick(): - /* iput-wide-quick vA, vB, offset@CCCC */ - mov r2, rINST, lsr #12 @ r2<- B - FETCH r3, 1 @ r3<- field byte offset - GET_VREG r2, r2 @ r2<- fp[B], the object pointer - ubfx r0, rINST, #8, #4 @ r0<- A - cmp r2, #0 @ check object for null - beq common_errNullObject @ object was null - VREG_INDEX_TO_ADDR r0, r0 @ r0<- &fp[A] - ldmia r0, {r0-r1} @ r0/r1<- fp[A]/fp[A+1] - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - strd r0, [r2, r3] @ obj.field<- r0/r1 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_long_to_double.S b/runtime/interpreter/mterp/arm/op_long_to_double.S deleted file mode 100644 index 3228c70929..0000000000 --- a/runtime/interpreter/mterp/arm/op_long_to_double.S +++ /dev/null @@ -1,27 +0,0 @@ -%def op_long_to_double(): - /* - * Specialised 64-bit floating point operation. - * - * Note: The result will be returned in d2. - * - * For: long-to-double - */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[A] - vldr d0, [r3] @ d0<- vAA - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - - vcvt.f64.s32 d1, s1 @ d1<- (double)(vAAh) - vcvt.f64.u32 d2, s0 @ d2<- (double)(vAAl) - vldr d3, constval$opcode - vmla.f64 d2, d1, d3 @ d2<- vAAh*2^32 + vAAl - - GET_INST_OPCODE ip @ extract opcode from rINST - vstr.64 d2, [r9] @ vAA<- d2 - GOTO_OPCODE ip @ jump to next instruction - - /* literal pool helper */ -constval${opcode}: - .8byte 0x41f0000000000000 diff --git a/runtime/interpreter/mterp/arm/op_long_to_float.S b/runtime/interpreter/mterp/arm/op_long_to_float.S deleted file mode 100644 index c021975445..0000000000 --- a/runtime/interpreter/mterp/arm/op_long_to_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_long_to_float(): -% unopNarrower(instr="bl __aeabi_l2f") diff --git a/runtime/interpreter/mterp/arm/op_long_to_int.S b/runtime/interpreter/mterp/arm/op_long_to_int.S deleted file mode 100644 index eacb8f59ec..0000000000 --- a/runtime/interpreter/mterp/arm/op_long_to_int.S +++ /dev/null @@ -1,3 +0,0 @@ -%def op_long_to_int(): -/* we ignore the high word, making this equivalent to a 32-bit reg move */ -% op_move() diff --git a/runtime/interpreter/mterp/arm/op_monitor_enter.S b/runtime/interpreter/mterp/arm/op_monitor_enter.S deleted file mode 100644 index afe293cb1b..0000000000 --- a/runtime/interpreter/mterp/arm/op_monitor_enter.S +++ /dev/null @@ -1,15 +0,0 @@ -%def op_monitor_enter(): - /* - * Synchronize on an object. - */ - /* monitor-enter vAA */ - EXPORT_PC - mov r2, rINST, lsr #8 @ r2<- AA - GET_VREG r0, r2 @ r0<- vAA (object) - mov r1, rSELF @ r1<- self - bl artLockObjectFromCode - cmp r0, #0 - bne MterpException - FETCH_ADVANCE_INST 1 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_monitor_exit.S b/runtime/interpreter/mterp/arm/op_monitor_exit.S deleted file mode 100644 index ddfa7744ef..0000000000 --- a/runtime/interpreter/mterp/arm/op_monitor_exit.S +++ /dev/null @@ -1,19 +0,0 @@ -%def op_monitor_exit(): - /* - * Unlock an object. - * - * Exceptions that occur when unlocking a monitor need to appear as - * if they happened at the following instruction. See the Dalvik - * instruction spec. - */ - /* monitor-exit vAA */ - EXPORT_PC - mov r2, rINST, lsr #8 @ r2<- AA - GET_VREG r0, r2 @ r0<- vAA (object) - mov r1, rSELF @ r0<- self - bl artUnlockObjectFromCode @ r0<- success for unlock(self, obj) - cmp r0, #0 @ failed? - bne MterpException - FETCH_ADVANCE_INST 1 @ before throw: advance rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_move.S b/runtime/interpreter/mterp/arm/op_move.S deleted file mode 100644 index 7dd893fa66..0000000000 --- a/runtime/interpreter/mterp/arm/op_move.S +++ /dev/null @@ -1,14 +0,0 @@ -%def op_move(is_object="0"): - /* for move, move-object, long-to-int */ - /* op vA, vB */ - mov r1, rINST, lsr #12 @ r1<- B from 15:12 - ubfx r0, rINST, #8, #4 @ r0<- A from 11:8 - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - GET_VREG r2, r1 @ r2<- fp[B] - GET_INST_OPCODE ip @ ip<- opcode from rINST - .if $is_object - SET_VREG_OBJECT r2, r0 @ fp[A]<- r2 - .else - SET_VREG r2, r0 @ fp[A]<- r2 - .endif - GOTO_OPCODE ip @ execute next instruction diff --git a/runtime/interpreter/mterp/arm/op_move_16.S b/runtime/interpreter/mterp/arm/op_move_16.S deleted file mode 100644 index 86601aa28b..0000000000 --- a/runtime/interpreter/mterp/arm/op_move_16.S +++ /dev/null @@ -1,14 +0,0 @@ -%def op_move_16(is_object="0"): - /* for: move/16, move-object/16 */ - /* op vAAAA, vBBBB */ - FETCH r1, 2 @ r1<- BBBB - FETCH r0, 1 @ r0<- AAAA - FETCH_ADVANCE_INST 3 @ advance rPC, load rINST - GET_VREG r2, r1 @ r2<- fp[BBBB] - GET_INST_OPCODE ip @ extract opcode from rINST - .if $is_object - SET_VREG_OBJECT r2, r0 @ fp[AAAA]<- r2 - .else - SET_VREG r2, r0 @ fp[AAAA]<- r2 - .endif - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_move_exception.S b/runtime/interpreter/mterp/arm/op_move_exception.S deleted file mode 100644 index 9136228521..0000000000 --- a/runtime/interpreter/mterp/arm/op_move_exception.S +++ /dev/null @@ -1,10 +0,0 @@ -%def op_move_exception(): - /* move-exception vAA */ - mov r2, rINST, lsr #8 @ r2<- AA - ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] - mov r1, #0 @ r1<- 0 - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - SET_VREG_OBJECT r3, r2 @ fp[AA]<- exception obj - GET_INST_OPCODE ip @ extract opcode from rINST - str r1, [rSELF, #THREAD_EXCEPTION_OFFSET] @ clear exception - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_move_from16.S b/runtime/interpreter/mterp/arm/op_move_from16.S deleted file mode 100644 index 113909c9f7..0000000000 --- a/runtime/interpreter/mterp/arm/op_move_from16.S +++ /dev/null @@ -1,14 +0,0 @@ -%def op_move_from16(is_object="0"): - /* for: move/from16, move-object/from16 */ - /* op vAA, vBBBB */ - FETCH r1, 1 @ r1<- BBBB - mov r0, rINST, lsr #8 @ r0<- AA - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - GET_VREG r2, r1 @ r2<- fp[BBBB] - GET_INST_OPCODE ip @ extract opcode from rINST - .if $is_object - SET_VREG_OBJECT r2, r0 @ fp[AA]<- r2 - .else - SET_VREG r2, r0 @ fp[AA]<- r2 - .endif - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_move_object.S b/runtime/interpreter/mterp/arm/op_move_object.S deleted file mode 100644 index dbb4d59710..0000000000 --- a/runtime/interpreter/mterp/arm/op_move_object.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_move_object(): -% op_move(is_object="1") diff --git a/runtime/interpreter/mterp/arm/op_move_object_16.S b/runtime/interpreter/mterp/arm/op_move_object_16.S deleted file mode 100644 index 40120379d5..0000000000 --- a/runtime/interpreter/mterp/arm/op_move_object_16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_move_object_16(): -% op_move_16(is_object="1") diff --git a/runtime/interpreter/mterp/arm/op_move_object_from16.S b/runtime/interpreter/mterp/arm/op_move_object_from16.S deleted file mode 100644 index c82698e81e..0000000000 --- a/runtime/interpreter/mterp/arm/op_move_object_from16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_move_object_from16(): -% op_move_from16(is_object="1") diff --git a/runtime/interpreter/mterp/arm/op_move_result.S b/runtime/interpreter/mterp/arm/op_move_result.S deleted file mode 100644 index eee23f6e25..0000000000 --- a/runtime/interpreter/mterp/arm/op_move_result.S +++ /dev/null @@ -1,14 +0,0 @@ -%def op_move_result(is_object="0"): - /* for: move-result, move-result-object */ - /* op vAA */ - mov r2, rINST, lsr #8 @ r2<- AA - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - ldr r0, [rFP, #OFF_FP_RESULT_REGISTER] @ get pointer to result JType. - ldr r0, [r0] @ r0 <- result.i. - GET_INST_OPCODE ip @ extract opcode from rINST - .if $is_object - SET_VREG_OBJECT r0, r2, r1 @ fp[AA]<- r0 - .else - SET_VREG r0, r2 @ fp[AA]<- r0 - .endif - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_move_result_object.S b/runtime/interpreter/mterp/arm/op_move_result_object.S deleted file mode 100644 index 87aea2646a..0000000000 --- a/runtime/interpreter/mterp/arm/op_move_result_object.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_move_result_object(): -% op_move_result(is_object="1") diff --git a/runtime/interpreter/mterp/arm/op_move_result_wide.S b/runtime/interpreter/mterp/arm/op_move_result_wide.S deleted file mode 100644 index 8b4e98034a..0000000000 --- a/runtime/interpreter/mterp/arm/op_move_result_wide.S +++ /dev/null @@ -1,11 +0,0 @@ -%def op_move_result_wide(): - /* move-result-wide vAA */ - mov rINST, rINST, lsr #8 @ rINST<- AA - ldr r3, [rFP, #OFF_FP_RESULT_REGISTER] - VREG_INDEX_TO_ADDR r2, rINST @ r2<- &fp[AA] - ldmia r3, {r0-r1} @ r0/r1<- retval.j - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - stmia r2, {r0-r1} @ fp[AA]<- r0/r1 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_move_wide.S b/runtime/interpreter/mterp/arm/op_move_wide.S deleted file mode 100644 index 800f7f6faa..0000000000 --- a/runtime/interpreter/mterp/arm/op_move_wide.S +++ /dev/null @@ -1,13 +0,0 @@ -%def op_move_wide(): - /* move-wide vA, vB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx rINST, rINST, #8, #4 @ rINST<- A - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] - VREG_INDEX_TO_ADDR r2, rINST @ r2<- &fp[A] - ldmia r3, {r0-r1} @ r0/r1<- fp[B] - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r2, {r0-r1} @ fp[A]<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_move_wide_16.S b/runtime/interpreter/mterp/arm/op_move_wide_16.S deleted file mode 100644 index ef4f0a8f59..0000000000 --- a/runtime/interpreter/mterp/arm/op_move_wide_16.S +++ /dev/null @@ -1,13 +0,0 @@ -%def op_move_wide_16(): - /* move-wide/16 vAAAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - FETCH r3, 2 @ r3<- BBBB - FETCH r2, 1 @ r2<- AAAA - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[BBBB] - VREG_INDEX_TO_ADDR lr, r2 @ r2<- &fp[AAAA] - ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] - FETCH_ADVANCE_INST 3 @ advance rPC, load rINST - CLEAR_SHADOW_PAIR r2, r3, ip @ Zero out the shadow regs - stmia lr, {r0-r1} @ fp[AAAA]<- r0/r1 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_move_wide_from16.S b/runtime/interpreter/mterp/arm/op_move_wide_from16.S deleted file mode 100644 index aae5aa323c..0000000000 --- a/runtime/interpreter/mterp/arm/op_move_wide_from16.S +++ /dev/null @@ -1,13 +0,0 @@ -%def op_move_wide_from16(): - /* move-wide/from16 vAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - FETCH r3, 1 @ r3<- BBBB - mov rINST, rINST, lsr #8 @ rINST<- AA - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[BBBB] - VREG_INDEX_TO_ADDR r2, rINST @ r2<- &fp[AA] - ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r2, {r0-r1} @ fp[AA]<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_mul_double.S b/runtime/interpreter/mterp/arm/op_mul_double.S deleted file mode 100644 index 72948c22b8..0000000000 --- a/runtime/interpreter/mterp/arm/op_mul_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_mul_double(): -% fbinopWide(instr="fmuld d2, d0, d1") diff --git a/runtime/interpreter/mterp/arm/op_mul_double_2addr.S b/runtime/interpreter/mterp/arm/op_mul_double_2addr.S deleted file mode 100644 index afa7fcf6cb..0000000000 --- a/runtime/interpreter/mterp/arm/op_mul_double_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_mul_double_2addr(): -% fbinopWide2addr(instr="fmuld d2, d0, d1") diff --git a/runtime/interpreter/mterp/arm/op_mul_float.S b/runtime/interpreter/mterp/arm/op_mul_float.S deleted file mode 100644 index ecb3717b0d..0000000000 --- a/runtime/interpreter/mterp/arm/op_mul_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_mul_float(): -% fbinop(instr="fmuls s2, s0, s1") diff --git a/runtime/interpreter/mterp/arm/op_mul_float_2addr.S b/runtime/interpreter/mterp/arm/op_mul_float_2addr.S deleted file mode 100644 index d084b1171b..0000000000 --- a/runtime/interpreter/mterp/arm/op_mul_float_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_mul_float_2addr(): -% fbinop2addr(instr="fmuls s2, s0, s1") diff --git a/runtime/interpreter/mterp/arm/op_mul_int.S b/runtime/interpreter/mterp/arm/op_mul_int.S deleted file mode 100644 index 8a7daf2c35..0000000000 --- a/runtime/interpreter/mterp/arm/op_mul_int.S +++ /dev/null @@ -1,3 +0,0 @@ -%def op_mul_int(): -/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ -% binop(instr="mul r0, r1, r0") diff --git a/runtime/interpreter/mterp/arm/op_mul_int_2addr.S b/runtime/interpreter/mterp/arm/op_mul_int_2addr.S deleted file mode 100644 index 98bfb7a9d9..0000000000 --- a/runtime/interpreter/mterp/arm/op_mul_int_2addr.S +++ /dev/null @@ -1,3 +0,0 @@ -%def op_mul_int_2addr(): -/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ -% binop2addr(instr="mul r0, r1, r0") diff --git a/runtime/interpreter/mterp/arm/op_mul_int_lit16.S b/runtime/interpreter/mterp/arm/op_mul_int_lit16.S deleted file mode 100644 index ab3f36122c..0000000000 --- a/runtime/interpreter/mterp/arm/op_mul_int_lit16.S +++ /dev/null @@ -1,3 +0,0 @@ -%def op_mul_int_lit16(): -/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ -% binopLit16(instr="mul r0, r1, r0") diff --git a/runtime/interpreter/mterp/arm/op_mul_int_lit8.S b/runtime/interpreter/mterp/arm/op_mul_int_lit8.S deleted file mode 100644 index 6cc5b89652..0000000000 --- a/runtime/interpreter/mterp/arm/op_mul_int_lit8.S +++ /dev/null @@ -1,3 +0,0 @@ -%def op_mul_int_lit8(): -/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ -% binopLit8(instr="mul r0, r1, r0") diff --git a/runtime/interpreter/mterp/arm/op_mul_long.S b/runtime/interpreter/mterp/arm/op_mul_long.S deleted file mode 100644 index c9f2e67323..0000000000 --- a/runtime/interpreter/mterp/arm/op_mul_long.S +++ /dev/null @@ -1,38 +0,0 @@ -%def op_mul_long(): - /* - * Signed 64-bit integer multiply. - * - * Consider WXxYZ (r1r0 x r3r2) with a long multiply: - * WX - * x YZ - * -------- - * ZW ZX - * YW YX - * - * The low word of the result holds ZX, the high word holds - * (ZW+YX) + (the high overflow from ZX). YW doesn't matter because - * it doesn't fit in the low 64 bits. - * - * Unlike most ARM math operations, multiply instructions have - * restrictions on using the same register more than once (Rd and Rm - * cannot be the same). - */ - /* mul-long vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] - ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 - ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 - mul ip, r2, r1 @ ip<- ZxW - umull r1, lr, r2, r0 @ r1/lr <- ZxX - mla r2, r0, r3, ip @ r2<- YxX + (ZxW) - mov r0, rINST, lsr #8 @ r0<- AA - add r2, r2, lr @ r2<- lr + low(ZxW + (YxX)) - CLEAR_SHADOW_PAIR r0, lr, ip @ Zero out the shadow regs - VREG_INDEX_TO_ADDR r0, r0 @ r0<- &fp[AA] - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r0, {r1-r2 } @ vAA/vAA+1<- r1/r2 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_mul_long_2addr.S b/runtime/interpreter/mterp/arm/op_mul_long_2addr.S deleted file mode 100644 index 2fd9f5c34b..0000000000 --- a/runtime/interpreter/mterp/arm/op_mul_long_2addr.S +++ /dev/null @@ -1,25 +0,0 @@ -%def op_mul_long_2addr(): - /* - * Signed 64-bit integer multiply, "/2addr" version. - * - * See op_mul_long for an explanation. - * - * We get a little tight on registers, so to avoid looking up &fp[A] - * again we stuff it into rINST. - */ - /* mul-long/2addr vA, vB */ - mov r1, rINST, lsr #12 @ r1<- B - ubfx r9, rINST, #8, #4 @ r9<- A - VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] - VREG_INDEX_TO_ADDR rINST, r9 @ rINST<- &fp[A] - ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 - ldmia rINST, {r0-r1} @ r0/r1<- vAA/vAA+1 - mul ip, r2, r1 @ ip<- ZxW - umull r1, lr, r2, r0 @ r1/lr <- ZxX - mla r2, r0, r3, ip @ r2<- YxX + (ZxW) - mov r0, rINST @ r0<- &fp[A] (free up rINST) - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - add r2, r2, lr @ r2<- r2 + low(ZxW + (YxX)) - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r0, {r1-r2} @ vAA/vAA+1<- r1/r2 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_neg_double.S b/runtime/interpreter/mterp/arm/op_neg_double.S deleted file mode 100644 index df73341b5c..0000000000 --- a/runtime/interpreter/mterp/arm/op_neg_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_neg_double(): -% unopWide(instr="add r1, r1, #0x80000000") diff --git a/runtime/interpreter/mterp/arm/op_neg_float.S b/runtime/interpreter/mterp/arm/op_neg_float.S deleted file mode 100644 index 4ed178fb29..0000000000 --- a/runtime/interpreter/mterp/arm/op_neg_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_neg_float(): -% unop(instr="add r0, r0, #0x80000000") diff --git a/runtime/interpreter/mterp/arm/op_neg_int.S b/runtime/interpreter/mterp/arm/op_neg_int.S deleted file mode 100644 index 08b72a168c..0000000000 --- a/runtime/interpreter/mterp/arm/op_neg_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_neg_int(): -% unop(instr="rsb r0, r0, #0") diff --git a/runtime/interpreter/mterp/arm/op_neg_long.S b/runtime/interpreter/mterp/arm/op_neg_long.S deleted file mode 100644 index 716c6dc643..0000000000 --- a/runtime/interpreter/mterp/arm/op_neg_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_neg_long(): -% unopWide(preinstr="rsbs r0, r0, #0", instr="rsc r1, r1, #0") diff --git a/runtime/interpreter/mterp/arm/op_new_array.S b/runtime/interpreter/mterp/arm/op_new_array.S deleted file mode 100644 index 04b5fa4b11..0000000000 --- a/runtime/interpreter/mterp/arm/op_new_array.S +++ /dev/null @@ -1,20 +0,0 @@ -%def op_new_array(): - /* - * Allocate an array of objects, specified with the array class - * and a count. - * - * The verifier guarantees that this is an array class, so we don't - * check for it here. - */ - /* new-array vA, vB, class@CCCC */ - EXPORT_PC - add r0, rFP, #OFF_FP_SHADOWFRAME - mov r1, rPC - mov r2, rINST - mov r3, rSELF - bl MterpNewArray - cmp r0, #0 - beq MterpPossibleException - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_new_instance.S b/runtime/interpreter/mterp/arm/op_new_instance.S deleted file mode 100644 index 447a6cfc0f..0000000000 --- a/runtime/interpreter/mterp/arm/op_new_instance.S +++ /dev/null @@ -1,15 +0,0 @@ -%def op_new_instance(): - /* - * Create a new instance of a class. - */ - /* new-instance vAA, class@BBBB */ - EXPORT_PC - add r0, rFP, #OFF_FP_SHADOWFRAME - mov r1, rSELF - mov r2, rINST - bl MterpNewInstance @ (shadow_frame, self, inst_data) - cmp r0, #0 - beq MterpPossibleException - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_nop.S b/runtime/interpreter/mterp/arm/op_nop.S deleted file mode 100644 index 8bfd1a3557..0000000000 --- a/runtime/interpreter/mterp/arm/op_nop.S +++ /dev/null @@ -1,4 +0,0 @@ -%def op_nop(): - FETCH_ADVANCE_INST 1 @ advance to next instr, load rINST - GET_INST_OPCODE ip @ ip<- opcode from rINST - GOTO_OPCODE ip @ execute it diff --git a/runtime/interpreter/mterp/arm/op_not_int.S b/runtime/interpreter/mterp/arm/op_not_int.S deleted file mode 100644 index 90c4eed34b..0000000000 --- a/runtime/interpreter/mterp/arm/op_not_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_not_int(): -% unop(instr="mvn r0, r0") diff --git a/runtime/interpreter/mterp/arm/op_not_long.S b/runtime/interpreter/mterp/arm/op_not_long.S deleted file mode 100644 index 29104f2ff7..0000000000 --- a/runtime/interpreter/mterp/arm/op_not_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_not_long(): -% unopWide(preinstr="mvn r0, r0", instr="mvn r1, r1") diff --git a/runtime/interpreter/mterp/arm/op_or_int.S b/runtime/interpreter/mterp/arm/op_or_int.S deleted file mode 100644 index 6992d2ac3d..0000000000 --- a/runtime/interpreter/mterp/arm/op_or_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_or_int(): -% binop(instr="orr r0, r0, r1") diff --git a/runtime/interpreter/mterp/arm/op_or_int_2addr.S b/runtime/interpreter/mterp/arm/op_or_int_2addr.S deleted file mode 100644 index 805ca09169..0000000000 --- a/runtime/interpreter/mterp/arm/op_or_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_or_int_2addr(): -% binop2addr(instr="orr r0, r0, r1") diff --git a/runtime/interpreter/mterp/arm/op_or_int_lit16.S b/runtime/interpreter/mterp/arm/op_or_int_lit16.S deleted file mode 100644 index 03bf4edc54..0000000000 --- a/runtime/interpreter/mterp/arm/op_or_int_lit16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_or_int_lit16(): -% binopLit16(instr="orr r0, r0, r1") diff --git a/runtime/interpreter/mterp/arm/op_or_int_lit8.S b/runtime/interpreter/mterp/arm/op_or_int_lit8.S deleted file mode 100644 index a29d73f322..0000000000 --- a/runtime/interpreter/mterp/arm/op_or_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_or_int_lit8(): -% binopLit8(extract="", instr="orr r0, r0, r3, asr #8") diff --git a/runtime/interpreter/mterp/arm/op_or_long.S b/runtime/interpreter/mterp/arm/op_or_long.S deleted file mode 100644 index 3278700375..0000000000 --- a/runtime/interpreter/mterp/arm/op_or_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_or_long(): -% binopWide(preinstr="orr r0, r0, r2", instr="orr r1, r1, r3") diff --git a/runtime/interpreter/mterp/arm/op_or_long_2addr.S b/runtime/interpreter/mterp/arm/op_or_long_2addr.S deleted file mode 100644 index 56ce5e628e..0000000000 --- a/runtime/interpreter/mterp/arm/op_or_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_or_long_2addr(): -% binopWide2addr(preinstr="orr r0, r0, r2", instr="orr r1, r1, r3") diff --git a/runtime/interpreter/mterp/arm/op_packed_switch.S b/runtime/interpreter/mterp/arm/op_packed_switch.S deleted file mode 100644 index 26af19db22..0000000000 --- a/runtime/interpreter/mterp/arm/op_packed_switch.S +++ /dev/null @@ -1,20 +0,0 @@ -%def op_packed_switch(func="MterpDoPackedSwitch"): - /* - * Handle a packed-switch or sparse-switch instruction. In both cases - * we decode it and hand it off to a helper function. - * - * We don't really expect backward branches in a switch statement, but - * they're perfectly legal, so we check for them here. - * - * for: packed-switch, sparse-switch - */ - /* op vAA, +BBBB */ - FETCH r0, 1 @ r0<- bbbb (lo) - FETCH r1, 2 @ r1<- BBBB (hi) - mov r3, rINST, lsr #8 @ r3<- AA - orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb - GET_VREG r1, r3 @ r1<- vAA - add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 - bl $func @ r0<- code-unit branch offset - movs rINST, r0 - b MterpCommonTakenBranch diff --git a/runtime/interpreter/mterp/arm/op_rem_double.S b/runtime/interpreter/mterp/arm/op_rem_double.S deleted file mode 100644 index 1e1e680d5f..0000000000 --- a/runtime/interpreter/mterp/arm/op_rem_double.S +++ /dev/null @@ -1,3 +0,0 @@ -%def op_rem_double(): -/* EABI doesn't define a double remainder function, but libm does */ -% binopWide(instr="bl fmod") diff --git a/runtime/interpreter/mterp/arm/op_rem_double_2addr.S b/runtime/interpreter/mterp/arm/op_rem_double_2addr.S deleted file mode 100644 index 8db1cdecbd..0000000000 --- a/runtime/interpreter/mterp/arm/op_rem_double_2addr.S +++ /dev/null @@ -1,3 +0,0 @@ -%def op_rem_double_2addr(): -/* EABI doesn't define a double remainder function, but libm does */ -% binopWide2addr(instr="bl fmod") diff --git a/runtime/interpreter/mterp/arm/op_rem_float.S b/runtime/interpreter/mterp/arm/op_rem_float.S deleted file mode 100644 index 5362e0a5f2..0000000000 --- a/runtime/interpreter/mterp/arm/op_rem_float.S +++ /dev/null @@ -1,3 +0,0 @@ -%def op_rem_float(): -/* EABI doesn't define a float remainder function, but libm does */ -% binop(instr="bl fmodf") diff --git a/runtime/interpreter/mterp/arm/op_rem_float_2addr.S b/runtime/interpreter/mterp/arm/op_rem_float_2addr.S deleted file mode 100644 index 90ff391990..0000000000 --- a/runtime/interpreter/mterp/arm/op_rem_float_2addr.S +++ /dev/null @@ -1,3 +0,0 @@ -%def op_rem_float_2addr(): -/* EABI doesn't define a float remainder function, but libm does */ -% binop2addr(instr="bl fmodf") diff --git a/runtime/interpreter/mterp/arm/op_rem_int.S b/runtime/interpreter/mterp/arm/op_rem_int.S deleted file mode 100644 index 068870e02c..0000000000 --- a/runtime/interpreter/mterp/arm/op_rem_int.S +++ /dev/null @@ -1,33 +0,0 @@ -%def op_rem_int(): - /* - * Specialized 32-bit binary operation - * - * Performs "r1 = r0 rem r1". The selection between sdiv block or the gcc helper - * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for - * ARMv7 CPUs that have hardware division support). - * - * NOTE: idivmod returns quotient in r0 and remainder in r1 - * - * rem-int - * - */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - GET_VREG r1, r3 @ r1<- vCC - GET_VREG r0, r2 @ r0<- vBB - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST -#ifdef __ARM_ARCH_EXT_IDIV__ - sdiv r2, r0, r1 - mls r1, r1, r2, r0 @ r1<- op, r0-r2 changed -#else - bl __aeabi_idivmod @ r1<- op, r0-r3 changed -#endif - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r1, r9 @ vAA<- r1 - GOTO_OPCODE ip @ jump to next instruction - /* 11-14 instructions */ diff --git a/runtime/interpreter/mterp/arm/op_rem_int_2addr.S b/runtime/interpreter/mterp/arm/op_rem_int_2addr.S deleted file mode 100644 index 22ade95135..0000000000 --- a/runtime/interpreter/mterp/arm/op_rem_int_2addr.S +++ /dev/null @@ -1,32 +0,0 @@ -%def op_rem_int_2addr(): - /* - * Specialized 32-bit binary operation - * - * Performs "r1 = r0 rem r1". The selection between sdiv block or the gcc helper - * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for - * ARMv7 CPUs that have hardware division support). - * - * NOTE: idivmod returns quotient in r0 and remainder in r1 - * - * rem-int/2addr - * - */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r1, r3 @ r1<- vB - GET_VREG r0, r9 @ r0<- vA - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - -#ifdef __ARM_ARCH_EXT_IDIV__ - sdiv r2, r0, r1 - mls r1, r1, r2, r0 @ r1<- op -#else - bl __aeabi_idivmod @ r1<- op, r0-r3 changed -#endif - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r1, r9 @ vAA<- r1 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - diff --git a/runtime/interpreter/mterp/arm/op_rem_int_lit16.S b/runtime/interpreter/mterp/arm/op_rem_int_lit16.S deleted file mode 100644 index 0605663ce2..0000000000 --- a/runtime/interpreter/mterp/arm/op_rem_int_lit16.S +++ /dev/null @@ -1,31 +0,0 @@ -%def op_rem_int_lit16(): - /* - * Specialized 32-bit binary operation - * - * Performs "r1 = r0 rem r1". The selection between sdiv block or the gcc helper - * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for - * ARMv7 CPUs that have hardware division support). - * - * NOTE: idivmod returns quotient in r0 and remainder in r1 - * - * rem-int/lit16 - * - */ - FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) - mov r2, rINST, lsr #12 @ r2<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r0, r2 @ r0<- vB - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - -#ifdef __ARM_ARCH_EXT_IDIV__ - sdiv r2, r0, r1 - mls r1, r1, r2, r0 @ r1<- op -#else - bl __aeabi_idivmod @ r1<- op, r0-r3 changed -#endif - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r1, r9 @ vAA<- r1 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ diff --git a/runtime/interpreter/mterp/arm/op_rem_int_lit8.S b/runtime/interpreter/mterp/arm/op_rem_int_lit8.S deleted file mode 100644 index 9b6867bac3..0000000000 --- a/runtime/interpreter/mterp/arm/op_rem_int_lit8.S +++ /dev/null @@ -1,32 +0,0 @@ -%def op_rem_int_lit8(): - /* - * Specialized 32-bit binary operation - * - * Performs "r1 = r0 rem r1". The selection between sdiv block or the gcc helper - * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for - * ARMv7 CPUs that have hardware division support). - * - * NOTE: idivmod returns quotient in r0 and remainder in r1 - * - * rem-int/lit8 - * - */ - FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r3, #255 @ r2<- BB - GET_VREG r0, r2 @ r0<- vBB - movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) - @cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - -#ifdef __ARM_ARCH_EXT_IDIV__ - sdiv r2, r0, r1 - mls r1, r1, r2, r0 @ r1<- op -#else - bl __aeabi_idivmod @ r1<- op, r0-r3 changed -#endif - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r1, r9 @ vAA<- r1 - GOTO_OPCODE ip @ jump to next instruction - /* 10-12 instructions */ diff --git a/runtime/interpreter/mterp/arm/op_rem_long.S b/runtime/interpreter/mterp/arm/op_rem_long.S deleted file mode 100644 index a44827f8a1..0000000000 --- a/runtime/interpreter/mterp/arm/op_rem_long.S +++ /dev/null @@ -1,3 +0,0 @@ -%def op_rem_long(): -/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ -% binopWide(instr="bl __aeabi_ldivmod", result0="r2", result1="r3", chkzero="1") diff --git a/runtime/interpreter/mterp/arm/op_rem_long_2addr.S b/runtime/interpreter/mterp/arm/op_rem_long_2addr.S deleted file mode 100644 index cf34964667..0000000000 --- a/runtime/interpreter/mterp/arm/op_rem_long_2addr.S +++ /dev/null @@ -1,3 +0,0 @@ -%def op_rem_long_2addr(): -/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ -% binopWide2addr(instr="bl __aeabi_ldivmod", result0="r2", result1="r3", chkzero="1") diff --git a/runtime/interpreter/mterp/arm/op_return.S b/runtime/interpreter/mterp/arm/op_return.S deleted file mode 100644 index fe35ec9035..0000000000 --- a/runtime/interpreter/mterp/arm/op_return.S +++ /dev/null @@ -1,17 +0,0 @@ -%def op_return(): - /* - * Return a 32-bit value. - * - * for: return, return-object - */ - /* op vAA */ - .extern MterpThreadFenceForConstructor - bl MterpThreadFenceForConstructor - ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] - mov r0, rSELF - ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - blne MterpSuspendCheck @ (self) - mov r2, rINST, lsr #8 @ r2<- AA - GET_VREG r0, r2 @ r0<- vAA - mov r1, #0 - b MterpReturn diff --git a/runtime/interpreter/mterp/arm/op_return_object.S b/runtime/interpreter/mterp/arm/op_return_object.S deleted file mode 100644 index 2eeec0b948..0000000000 --- a/runtime/interpreter/mterp/arm/op_return_object.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_return_object(): -% op_return() diff --git a/runtime/interpreter/mterp/arm/op_return_void.S b/runtime/interpreter/mterp/arm/op_return_void.S deleted file mode 100644 index 2418c6a1f7..0000000000 --- a/runtime/interpreter/mterp/arm/op_return_void.S +++ /dev/null @@ -1,10 +0,0 @@ -%def op_return_void(): - .extern MterpThreadFenceForConstructor - bl MterpThreadFenceForConstructor - ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] - mov r0, rSELF - ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - blne MterpSuspendCheck @ (self) - mov r0, #0 - mov r1, #0 - b MterpReturn diff --git a/runtime/interpreter/mterp/arm/op_return_void_no_barrier.S b/runtime/interpreter/mterp/arm/op_return_void_no_barrier.S deleted file mode 100644 index fa4cc0abee..0000000000 --- a/runtime/interpreter/mterp/arm/op_return_void_no_barrier.S +++ /dev/null @@ -1,8 +0,0 @@ -%def op_return_void_no_barrier(): - ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] - mov r0, rSELF - ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - blne MterpSuspendCheck @ (self) - mov r0, #0 - mov r1, #0 - b MterpReturn diff --git a/runtime/interpreter/mterp/arm/op_return_wide.S b/runtime/interpreter/mterp/arm/op_return_wide.S deleted file mode 100644 index a2a3be41ef..0000000000 --- a/runtime/interpreter/mterp/arm/op_return_wide.S +++ /dev/null @@ -1,15 +0,0 @@ -%def op_return_wide(): - /* - * Return a 64-bit value. - */ - /* return-wide vAA */ - .extern MterpThreadFenceForConstructor - bl MterpThreadFenceForConstructor - ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] - mov r0, rSELF - ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - blne MterpSuspendCheck @ (self) - mov r2, rINST, lsr #8 @ r2<- AA - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[AA] - ldmia r2, {r0-r1} @ r0/r1 <- vAA/vAA+1 - b MterpReturn diff --git a/runtime/interpreter/mterp/arm/op_rsub_int.S b/runtime/interpreter/mterp/arm/op_rsub_int.S deleted file mode 100644 index 5d41f6d63b..0000000000 --- a/runtime/interpreter/mterp/arm/op_rsub_int.S +++ /dev/null @@ -1,3 +0,0 @@ -%def op_rsub_int(): -/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ -% binopLit16(instr="rsb r0, r0, r1") diff --git a/runtime/interpreter/mterp/arm/op_rsub_int_lit8.S b/runtime/interpreter/mterp/arm/op_rsub_int_lit8.S deleted file mode 100644 index 5ce759de4d..0000000000 --- a/runtime/interpreter/mterp/arm/op_rsub_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_rsub_int_lit8(): -% binopLit8(extract="", instr="rsb r0, r0, r3, asr #8") diff --git a/runtime/interpreter/mterp/arm/op_sget.S b/runtime/interpreter/mterp/arm/op_sget.S deleted file mode 100644 index 8a6a66ab60..0000000000 --- a/runtime/interpreter/mterp/arm/op_sget.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sget(is_object="0", helper="MterpSGetU32"): -% field(helper=helper) diff --git a/runtime/interpreter/mterp/arm/op_sget_boolean.S b/runtime/interpreter/mterp/arm/op_sget_boolean.S deleted file mode 100644 index d9c12c9b28..0000000000 --- a/runtime/interpreter/mterp/arm/op_sget_boolean.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sget_boolean(): -% op_sget(helper="MterpSGetU8") diff --git a/runtime/interpreter/mterp/arm/op_sget_byte.S b/runtime/interpreter/mterp/arm/op_sget_byte.S deleted file mode 100644 index 37c6879cd4..0000000000 --- a/runtime/interpreter/mterp/arm/op_sget_byte.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sget_byte(): -% op_sget(helper="MterpSGetI8") diff --git a/runtime/interpreter/mterp/arm/op_sget_char.S b/runtime/interpreter/mterp/arm/op_sget_char.S deleted file mode 100644 index 003bcd1683..0000000000 --- a/runtime/interpreter/mterp/arm/op_sget_char.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sget_char(): -% op_sget(helper="MterpSGetU16") diff --git a/runtime/interpreter/mterp/arm/op_sget_object.S b/runtime/interpreter/mterp/arm/op_sget_object.S deleted file mode 100644 index 7cf3597f44..0000000000 --- a/runtime/interpreter/mterp/arm/op_sget_object.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sget_object(): -% op_sget(is_object="1", helper="MterpSGetObj") diff --git a/runtime/interpreter/mterp/arm/op_sget_short.S b/runtime/interpreter/mterp/arm/op_sget_short.S deleted file mode 100644 index afacb578d9..0000000000 --- a/runtime/interpreter/mterp/arm/op_sget_short.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sget_short(): -% op_sget(helper="MterpSGetI16") diff --git a/runtime/interpreter/mterp/arm/op_sget_wide.S b/runtime/interpreter/mterp/arm/op_sget_wide.S deleted file mode 100644 index fff2be6945..0000000000 --- a/runtime/interpreter/mterp/arm/op_sget_wide.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sget_wide(): -% op_sget(helper="MterpSGetU64") diff --git a/runtime/interpreter/mterp/arm/op_shl_int.S b/runtime/interpreter/mterp/arm/op_shl_int.S deleted file mode 100644 index 948a520e8e..0000000000 --- a/runtime/interpreter/mterp/arm/op_shl_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shl_int(): -% binop(preinstr="and r1, r1, #31", instr="mov r0, r0, asl r1") diff --git a/runtime/interpreter/mterp/arm/op_shl_int_2addr.S b/runtime/interpreter/mterp/arm/op_shl_int_2addr.S deleted file mode 100644 index 89b16da224..0000000000 --- a/runtime/interpreter/mterp/arm/op_shl_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shl_int_2addr(): -% binop2addr(preinstr="and r1, r1, #31", instr="mov r0, r0, asl r1") diff --git a/runtime/interpreter/mterp/arm/op_shl_int_lit8.S b/runtime/interpreter/mterp/arm/op_shl_int_lit8.S deleted file mode 100644 index d6f81e779a..0000000000 --- a/runtime/interpreter/mterp/arm/op_shl_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shl_int_lit8(): -% binopLit8(extract="ubfx r1, r3, #8, #5", instr="mov r0, r0, asl r1") diff --git a/runtime/interpreter/mterp/arm/op_shl_long.S b/runtime/interpreter/mterp/arm/op_shl_long.S deleted file mode 100644 index d11fee24f4..0000000000 --- a/runtime/interpreter/mterp/arm/op_shl_long.S +++ /dev/null @@ -1,28 +0,0 @@ -%def op_shl_long(): - /* - * Long integer shift. This is different from the generic 32/64-bit - * binary operations because vAA/vBB are 64-bit but vCC (the shift - * distance) is 32-bit. Also, Dalvik requires us to mask off the low - * 6 bits of the shift distance. - */ - /* shl-long vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - and r3, r0, #255 @ r3<- BB - mov r0, r0, lsr #8 @ r0<- CC - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[BB] - GET_VREG r2, r0 @ r2<- vCC - ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 - CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs - and r2, r2, #63 @ r2<- r2 & 0x3f - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] - mov r1, r1, asl r2 @ r1<- r1 << r2 - rsb r3, r2, #32 @ r3<- 32 - r2 - orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) - subs ip, r2, #32 @ ip<- r2 - 32 - movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - mov r0, r0, asl r2 @ r0<- r0 << r2 - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_shl_long_2addr.S b/runtime/interpreter/mterp/arm/op_shl_long_2addr.S deleted file mode 100644 index e636d2e330..0000000000 --- a/runtime/interpreter/mterp/arm/op_shl_long_2addr.S +++ /dev/null @@ -1,23 +0,0 @@ -%def op_shl_long_2addr(): - /* - * Long integer shift, 2addr version. vA is 64-bit value/result, vB is - * 32-bit shift distance. - */ - /* shl-long/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r2, r3 @ r2<- vB - CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[A] - and r2, r2, #63 @ r2<- r2 & 0x3f - ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 - mov r1, r1, asl r2 @ r1<- r1 << r2 - rsb r3, r2, #32 @ r3<- 32 - r2 - orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) - subs ip, r2, #32 @ ip<- r2 - 32 - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) - mov r0, r0, asl r2 @ r0<- r0 << r2 - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_shr_int.S b/runtime/interpreter/mterp/arm/op_shr_int.S deleted file mode 100644 index 4d94d1f550..0000000000 --- a/runtime/interpreter/mterp/arm/op_shr_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shr_int(): -% binop(preinstr="and r1, r1, #31", instr="mov r0, r0, asr r1") diff --git a/runtime/interpreter/mterp/arm/op_shr_int_2addr.S b/runtime/interpreter/mterp/arm/op_shr_int_2addr.S deleted file mode 100644 index 786b409921..0000000000 --- a/runtime/interpreter/mterp/arm/op_shr_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shr_int_2addr(): -% binop2addr(preinstr="and r1, r1, #31", instr="mov r0, r0, asr r1") diff --git a/runtime/interpreter/mterp/arm/op_shr_int_lit8.S b/runtime/interpreter/mterp/arm/op_shr_int_lit8.S deleted file mode 100644 index f5550b1d4b..0000000000 --- a/runtime/interpreter/mterp/arm/op_shr_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shr_int_lit8(): -% binopLit8(extract="ubfx r1, r3, #8, #5", instr="mov r0, r0, asr r1") diff --git a/runtime/interpreter/mterp/arm/op_shr_long.S b/runtime/interpreter/mterp/arm/op_shr_long.S deleted file mode 100644 index eec8d32c8c..0000000000 --- a/runtime/interpreter/mterp/arm/op_shr_long.S +++ /dev/null @@ -1,28 +0,0 @@ -%def op_shr_long(): - /* - * Long integer shift. This is different from the generic 32/64-bit - * binary operations because vAA/vBB are 64-bit but vCC (the shift - * distance) is 32-bit. Also, Dalvik requires us to mask off the low - * 6 bits of the shift distance. - */ - /* shr-long vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - and r3, r0, #255 @ r3<- BB - mov r0, r0, lsr #8 @ r0<- CC - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[BB] - GET_VREG r2, r0 @ r2<- vCC - ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 - CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs - and r2, r2, #63 @ r0<- r0 & 0x3f - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] - mov r0, r0, lsr r2 @ r0<- r2 >> r2 - rsb r3, r2, #32 @ r3<- 32 - r2 - orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) - subs ip, r2, #32 @ ip<- r2 - 32 - movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - mov r1, r1, asr r2 @ r1<- r1 >> r2 - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_shr_long_2addr.S b/runtime/interpreter/mterp/arm/op_shr_long_2addr.S deleted file mode 100644 index ac40d36327..0000000000 --- a/runtime/interpreter/mterp/arm/op_shr_long_2addr.S +++ /dev/null @@ -1,23 +0,0 @@ -%def op_shr_long_2addr(): - /* - * Long integer shift, 2addr version. vA is 64-bit value/result, vB is - * 32-bit shift distance. - */ - /* shr-long/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r2, r3 @ r2<- vB - CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[A] - and r2, r2, #63 @ r2<- r2 & 0x3f - ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 - mov r0, r0, lsr r2 @ r0<- r2 >> r2 - rsb r3, r2, #32 @ r3<- 32 - r2 - orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) - subs ip, r2, #32 @ ip<- r2 - 32 - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) - mov r1, r1, asr r2 @ r1<- r1 >> r2 - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_sparse_switch.S b/runtime/interpreter/mterp/arm/op_sparse_switch.S deleted file mode 100644 index b74d7da816..0000000000 --- a/runtime/interpreter/mterp/arm/op_sparse_switch.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sparse_switch(): -% op_packed_switch(func="MterpDoSparseSwitch") diff --git a/runtime/interpreter/mterp/arm/op_sput.S b/runtime/interpreter/mterp/arm/op_sput.S deleted file mode 100644 index cbd6ee96d3..0000000000 --- a/runtime/interpreter/mterp/arm/op_sput.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sput(is_object="0", helper="MterpSPutU32"): -% field(helper=helper) diff --git a/runtime/interpreter/mterp/arm/op_sput_boolean.S b/runtime/interpreter/mterp/arm/op_sput_boolean.S deleted file mode 100644 index 36fba8448b..0000000000 --- a/runtime/interpreter/mterp/arm/op_sput_boolean.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sput_boolean(): -% op_sput(helper="MterpSPutU8") diff --git a/runtime/interpreter/mterp/arm/op_sput_byte.S b/runtime/interpreter/mterp/arm/op_sput_byte.S deleted file mode 100644 index 84ad4a0ff8..0000000000 --- a/runtime/interpreter/mterp/arm/op_sput_byte.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sput_byte(): -% op_sput(helper="MterpSPutI8") diff --git a/runtime/interpreter/mterp/arm/op_sput_char.S b/runtime/interpreter/mterp/arm/op_sput_char.S deleted file mode 100644 index 9b8eeba578..0000000000 --- a/runtime/interpreter/mterp/arm/op_sput_char.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sput_char(): -% op_sput(helper="MterpSPutU16") diff --git a/runtime/interpreter/mterp/arm/op_sput_object.S b/runtime/interpreter/mterp/arm/op_sput_object.S deleted file mode 100644 index 081360c40f..0000000000 --- a/runtime/interpreter/mterp/arm/op_sput_object.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sput_object(): -% op_sput(is_object="1", helper="MterpSPutObj") diff --git a/runtime/interpreter/mterp/arm/op_sput_short.S b/runtime/interpreter/mterp/arm/op_sput_short.S deleted file mode 100644 index ee16513486..0000000000 --- a/runtime/interpreter/mterp/arm/op_sput_short.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sput_short(): -% op_sput(helper="MterpSPutI16") diff --git a/runtime/interpreter/mterp/arm/op_sput_wide.S b/runtime/interpreter/mterp/arm/op_sput_wide.S deleted file mode 100644 index 44c1a188ed..0000000000 --- a/runtime/interpreter/mterp/arm/op_sput_wide.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sput_wide(): -% op_sput(helper="MterpSPutU64") diff --git a/runtime/interpreter/mterp/arm/op_sub_double.S b/runtime/interpreter/mterp/arm/op_sub_double.S deleted file mode 100644 index 418f93098a..0000000000 --- a/runtime/interpreter/mterp/arm/op_sub_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_double(): -% fbinopWide(instr="fsubd d2, d0, d1") diff --git a/runtime/interpreter/mterp/arm/op_sub_double_2addr.S b/runtime/interpreter/mterp/arm/op_sub_double_2addr.S deleted file mode 100644 index 2bd03703f5..0000000000 --- a/runtime/interpreter/mterp/arm/op_sub_double_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_double_2addr(): -% fbinopWide2addr(instr="fsubd d2, d0, d1") diff --git a/runtime/interpreter/mterp/arm/op_sub_float.S b/runtime/interpreter/mterp/arm/op_sub_float.S deleted file mode 100644 index c0b09ff093..0000000000 --- a/runtime/interpreter/mterp/arm/op_sub_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_float(): -% fbinop(instr="fsubs s2, s0, s1") diff --git a/runtime/interpreter/mterp/arm/op_sub_float_2addr.S b/runtime/interpreter/mterp/arm/op_sub_float_2addr.S deleted file mode 100644 index c5ffec7be4..0000000000 --- a/runtime/interpreter/mterp/arm/op_sub_float_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_float_2addr(): -% fbinop2addr(instr="fsubs s2, s0, s1") diff --git a/runtime/interpreter/mterp/arm/op_sub_int.S b/runtime/interpreter/mterp/arm/op_sub_int.S deleted file mode 100644 index 0932989efc..0000000000 --- a/runtime/interpreter/mterp/arm/op_sub_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_int(): -% binop(instr="sub r0, r0, r1") diff --git a/runtime/interpreter/mterp/arm/op_sub_int_2addr.S b/runtime/interpreter/mterp/arm/op_sub_int_2addr.S deleted file mode 100644 index c6fa2e46b3..0000000000 --- a/runtime/interpreter/mterp/arm/op_sub_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_int_2addr(): -% binop2addr(instr="sub r0, r0, r1") diff --git a/runtime/interpreter/mterp/arm/op_sub_long.S b/runtime/interpreter/mterp/arm/op_sub_long.S deleted file mode 100644 index 85d9a9f528..0000000000 --- a/runtime/interpreter/mterp/arm/op_sub_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_long(): -% binopWide(preinstr="subs r0, r0, r2", instr="sbc r1, r1, r3") diff --git a/runtime/interpreter/mterp/arm/op_sub_long_2addr.S b/runtime/interpreter/mterp/arm/op_sub_long_2addr.S deleted file mode 100644 index 8a782aa5bf..0000000000 --- a/runtime/interpreter/mterp/arm/op_sub_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_long_2addr(): -% binopWide2addr(preinstr="subs r0, r0, r2", instr="sbc r1, r1, r3") diff --git a/runtime/interpreter/mterp/arm/op_throw.S b/runtime/interpreter/mterp/arm/op_throw.S deleted file mode 100644 index 0d3fe37934..0000000000 --- a/runtime/interpreter/mterp/arm/op_throw.S +++ /dev/null @@ -1,12 +0,0 @@ -%def op_throw(): - /* - * Throw an exception object in the current thread. - */ - /* throw vAA */ - EXPORT_PC - mov r2, rINST, lsr #8 @ r2<- AA - GET_VREG r1, r2 @ r1<- vAA (exception object) - cmp r1, #0 @ null object? - beq common_errNullObject @ yes, throw an NPE instead - str r1, [rSELF, #THREAD_EXCEPTION_OFFSET] @ thread->exception<- obj - b MterpException diff --git a/runtime/interpreter/mterp/arm/op_unused_3e.S b/runtime/interpreter/mterp/arm/op_unused_3e.S deleted file mode 100644 index d889f1a5fb..0000000000 --- a/runtime/interpreter/mterp/arm/op_unused_3e.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_3e(): -% unused() diff --git a/runtime/interpreter/mterp/arm/op_unused_3f.S b/runtime/interpreter/mterp/arm/op_unused_3f.S deleted file mode 100644 index b3ebcfaeaa..0000000000 --- a/runtime/interpreter/mterp/arm/op_unused_3f.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_3f(): -% unused() diff --git a/runtime/interpreter/mterp/arm/op_unused_40.S b/runtime/interpreter/mterp/arm/op_unused_40.S deleted file mode 100644 index 7920fb350f..0000000000 --- a/runtime/interpreter/mterp/arm/op_unused_40.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_40(): -% unused() diff --git a/runtime/interpreter/mterp/arm/op_unused_41.S b/runtime/interpreter/mterp/arm/op_unused_41.S deleted file mode 100644 index 5ed03b8506..0000000000 --- a/runtime/interpreter/mterp/arm/op_unused_41.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_41(): -% unused() diff --git a/runtime/interpreter/mterp/arm/op_unused_42.S b/runtime/interpreter/mterp/arm/op_unused_42.S deleted file mode 100644 index ac32521add..0000000000 --- a/runtime/interpreter/mterp/arm/op_unused_42.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_42(): -% unused() diff --git a/runtime/interpreter/mterp/arm/op_unused_43.S b/runtime/interpreter/mterp/arm/op_unused_43.S deleted file mode 100644 index 33e2aa10f8..0000000000 --- a/runtime/interpreter/mterp/arm/op_unused_43.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_43(): -% unused() diff --git a/runtime/interpreter/mterp/arm/op_unused_73.S b/runtime/interpreter/mterp/arm/op_unused_73.S deleted file mode 100644 index e3267a30a1..0000000000 --- a/runtime/interpreter/mterp/arm/op_unused_73.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_73(): -% unused() diff --git a/runtime/interpreter/mterp/arm/op_unused_79.S b/runtime/interpreter/mterp/arm/op_unused_79.S deleted file mode 100644 index 3c6dafc789..0000000000 --- a/runtime/interpreter/mterp/arm/op_unused_79.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_79(): -% unused() diff --git a/runtime/interpreter/mterp/arm/op_unused_7a.S b/runtime/interpreter/mterp/arm/op_unused_7a.S deleted file mode 100644 index 9c03cd5535..0000000000 --- a/runtime/interpreter/mterp/arm/op_unused_7a.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_7a(): -% unused() diff --git a/runtime/interpreter/mterp/arm/op_unused_f3.S b/runtime/interpreter/mterp/arm/op_unused_f3.S deleted file mode 100644 index ab10b78be2..0000000000 --- a/runtime/interpreter/mterp/arm/op_unused_f3.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_f3(): -% unused() diff --git a/runtime/interpreter/mterp/arm/op_unused_f4.S b/runtime/interpreter/mterp/arm/op_unused_f4.S deleted file mode 100644 index 09229d6d99..0000000000 --- a/runtime/interpreter/mterp/arm/op_unused_f4.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_f4(): -% unused() diff --git a/runtime/interpreter/mterp/arm/op_unused_f5.S b/runtime/interpreter/mterp/arm/op_unused_f5.S deleted file mode 100644 index 0d6149b5fd..0000000000 --- a/runtime/interpreter/mterp/arm/op_unused_f5.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_f5(): -% unused() diff --git a/runtime/interpreter/mterp/arm/op_unused_f6.S b/runtime/interpreter/mterp/arm/op_unused_f6.S deleted file mode 100644 index 117b03de6d..0000000000 --- a/runtime/interpreter/mterp/arm/op_unused_f6.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_f6(): -% unused() diff --git a/runtime/interpreter/mterp/arm/op_unused_f7.S b/runtime/interpreter/mterp/arm/op_unused_f7.S deleted file mode 100644 index 4e3a0f3c9a..0000000000 --- a/runtime/interpreter/mterp/arm/op_unused_f7.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_f7(): -% unused() diff --git a/runtime/interpreter/mterp/arm/op_unused_f8.S b/runtime/interpreter/mterp/arm/op_unused_f8.S deleted file mode 100644 index d1220752d7..0000000000 --- a/runtime/interpreter/mterp/arm/op_unused_f8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_f8(): -% unused() diff --git a/runtime/interpreter/mterp/arm/op_unused_f9.S b/runtime/interpreter/mterp/arm/op_unused_f9.S deleted file mode 100644 index 7d09a0ebcf..0000000000 --- a/runtime/interpreter/mterp/arm/op_unused_f9.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_f9(): -% unused() diff --git a/runtime/interpreter/mterp/arm/op_unused_fc.S b/runtime/interpreter/mterp/arm/op_unused_fc.S deleted file mode 100644 index 06978191eb..0000000000 --- a/runtime/interpreter/mterp/arm/op_unused_fc.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_fc(): -% unused() diff --git a/runtime/interpreter/mterp/arm/op_unused_fd.S b/runtime/interpreter/mterp/arm/op_unused_fd.S deleted file mode 100644 index 4bc2b4bdb6..0000000000 --- a/runtime/interpreter/mterp/arm/op_unused_fd.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_fd(): -% unused() diff --git a/runtime/interpreter/mterp/arm/op_ushr_int.S b/runtime/interpreter/mterp/arm/op_ushr_int.S deleted file mode 100644 index 7716bebcbb..0000000000 --- a/runtime/interpreter/mterp/arm/op_ushr_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_ushr_int(): -% binop(preinstr="and r1, r1, #31", instr="mov r0, r0, lsr r1") diff --git a/runtime/interpreter/mterp/arm/op_ushr_int_2addr.S b/runtime/interpreter/mterp/arm/op_ushr_int_2addr.S deleted file mode 100644 index 8e435a738c..0000000000 --- a/runtime/interpreter/mterp/arm/op_ushr_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_ushr_int_2addr(): -% binop2addr(preinstr="and r1, r1, #31", instr="mov r0, r0, lsr r1") diff --git a/runtime/interpreter/mterp/arm/op_ushr_int_lit8.S b/runtime/interpreter/mterp/arm/op_ushr_int_lit8.S deleted file mode 100644 index 40783de326..0000000000 --- a/runtime/interpreter/mterp/arm/op_ushr_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_ushr_int_lit8(): -% binopLit8(extract="ubfx r1, r3, #8, #5", instr="mov r0, r0, lsr r1") diff --git a/runtime/interpreter/mterp/arm/op_ushr_long.S b/runtime/interpreter/mterp/arm/op_ushr_long.S deleted file mode 100644 index 2ab31ff216..0000000000 --- a/runtime/interpreter/mterp/arm/op_ushr_long.S +++ /dev/null @@ -1,28 +0,0 @@ -%def op_ushr_long(): - /* - * Long integer shift. This is different from the generic 32/64-bit - * binary operations because vAA/vBB are 64-bit but vCC (the shift - * distance) is 32-bit. Also, Dalvik requires us to mask off the low - * 6 bits of the shift distance. - */ - /* ushr-long vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - and r3, r0, #255 @ r3<- BB - mov r0, r0, lsr #8 @ r0<- CC - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[BB] - GET_VREG r2, r0 @ r2<- vCC - ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 - CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs - and r2, r2, #63 @ r0<- r0 & 0x3f - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] - mov r0, r0, lsr r2 @ r0<- r2 >> r2 - rsb r3, r2, #32 @ r3<- 32 - r2 - orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) - subs ip, r2, #32 @ ip<- r2 - 32 - movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - mov r1, r1, lsr r2 @ r1<- r1 >>> r2 - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_ushr_long_2addr.S b/runtime/interpreter/mterp/arm/op_ushr_long_2addr.S deleted file mode 100644 index e86161b0f5..0000000000 --- a/runtime/interpreter/mterp/arm/op_ushr_long_2addr.S +++ /dev/null @@ -1,23 +0,0 @@ -%def op_ushr_long_2addr(): - /* - * Long integer shift, 2addr version. vA is 64-bit value/result, vB is - * 32-bit shift distance. - */ - /* ushr-long/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r2, r3 @ r2<- vB - CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[A] - and r2, r2, #63 @ r2<- r2 & 0x3f - ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 - mov r0, r0, lsr r2 @ r0<- r2 >> r2 - rsb r3, r2, #32 @ r3<- 32 - r2 - orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) - subs ip, r2, #32 @ ip<- r2 - 32 - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) - mov r1, r1, lsr r2 @ r1<- r1 >>> r2 - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_xor_int.S b/runtime/interpreter/mterp/arm/op_xor_int.S deleted file mode 100644 index 89a6450b01..0000000000 --- a/runtime/interpreter/mterp/arm/op_xor_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_xor_int(): -% binop(instr="eor r0, r0, r1") diff --git a/runtime/interpreter/mterp/arm/op_xor_int_2addr.S b/runtime/interpreter/mterp/arm/op_xor_int_2addr.S deleted file mode 100644 index af7e85ede6..0000000000 --- a/runtime/interpreter/mterp/arm/op_xor_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_xor_int_2addr(): -% binop2addr(instr="eor r0, r0, r1") diff --git a/runtime/interpreter/mterp/arm/op_xor_int_lit16.S b/runtime/interpreter/mterp/arm/op_xor_int_lit16.S deleted file mode 100644 index a970e01357..0000000000 --- a/runtime/interpreter/mterp/arm/op_xor_int_lit16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_xor_int_lit16(): -% binopLit16(instr="eor r0, r0, r1") diff --git a/runtime/interpreter/mterp/arm/op_xor_int_lit8.S b/runtime/interpreter/mterp/arm/op_xor_int_lit8.S deleted file mode 100644 index 2241f3176b..0000000000 --- a/runtime/interpreter/mterp/arm/op_xor_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_xor_int_lit8(): -% binopLit8(extract="", instr="eor r0, r0, r3, asr #8") diff --git a/runtime/interpreter/mterp/arm/op_xor_long.S b/runtime/interpreter/mterp/arm/op_xor_long.S deleted file mode 100644 index 3700a4a308..0000000000 --- a/runtime/interpreter/mterp/arm/op_xor_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_xor_long(): -% binopWide(preinstr="eor r0, r0, r2", instr="eor r1, r1, r3") diff --git a/runtime/interpreter/mterp/arm/op_xor_long_2addr.S b/runtime/interpreter/mterp/arm/op_xor_long_2addr.S deleted file mode 100644 index 6558a4eb39..0000000000 --- a/runtime/interpreter/mterp/arm/op_xor_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_xor_long_2addr(): -% binopWide2addr(preinstr="eor r0, r0, r2", instr="eor r1, r1, r3") diff --git a/runtime/interpreter/mterp/arm/other.S b/runtime/interpreter/mterp/arm/other.S new file mode 100644 index 0000000000..340038c83e --- /dev/null +++ b/runtime/interpreter/mterp/arm/other.S @@ -0,0 +1,379 @@ +%def const(helper="UndefinedConstHandler"): + /* const/class vAA, type@BBBB */ + /* const/method-handle vAA, method_handle@BBBB */ + /* const/method-type vAA, proto@BBBB */ + /* const/string vAA, string@@BBBB */ + .extern $helper + EXPORT_PC + FETCH r0, 1 @ r0<- BBBB + mov r1, rINST, lsr #8 @ r1<- AA + add r2, rFP, #OFF_FP_SHADOWFRAME + mov r3, rSELF + bl $helper @ (index, tgt_reg, shadow_frame, self) + PREFETCH_INST 2 @ load rINST + cmp r0, #0 @ fail? + bne MterpPossibleException @ let reference interpreter deal with it. + ADVANCE 2 @ advance rPC + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def unused(): +/* + * Bail to reference interpreter to throw. + */ + b MterpFallback + +%def op_const(): + /* const vAA, #+BBBBbbbb */ + mov r3, rINST, lsr #8 @ r3<- AA + FETCH r0, 1 @ r0<- bbbb (low) + FETCH r1, 2 @ r1<- BBBB (high) + FETCH_ADVANCE_INST 3 @ advance rPC, load rINST + orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb + GET_INST_OPCODE ip @ extract opcode from rINST + SET_VREG r0, r3 @ vAA<- r0 + GOTO_OPCODE ip @ jump to next instruction + +%def op_const_16(): + /* const/16 vAA, #+BBBB */ + FETCH_S r0, 1 @ r0<- ssssBBBB (sign-extended) + mov r3, rINST, lsr #8 @ r3<- AA + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + SET_VREG r0, r3 @ vAA<- r0 + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def op_const_4(): + /* const/4 vA, #+B */ + sbfx r1, rINST, #12, #4 @ r1<- sssssssB (sign-extended) + ubfx r0, rINST, #8, #4 @ r0<- A + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + GET_INST_OPCODE ip @ ip<- opcode from rINST + SET_VREG r1, r0 @ fp[A]<- r1 + GOTO_OPCODE ip @ execute next instruction + +%def op_const_class(): +% const(helper="MterpConstClass") + +%def op_const_high16(): + /* const/high16 vAA, #+BBBB0000 */ + FETCH r0, 1 @ r0<- 0000BBBB (zero-extended) + mov r3, rINST, lsr #8 @ r3<- AA + mov r0, r0, lsl #16 @ r0<- BBBB0000 + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + SET_VREG r0, r3 @ vAA<- r0 + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def op_const_method_handle(): +% const(helper="MterpConstMethodHandle") + +%def op_const_method_type(): +% const(helper="MterpConstMethodType") + +%def op_const_string(): +% const(helper="MterpConstString") + +%def op_const_string_jumbo(): + /* const/string vAA, String@BBBBBBBB */ + EXPORT_PC + FETCH r0, 1 @ r0<- bbbb (low) + FETCH r2, 2 @ r2<- BBBB (high) + mov r1, rINST, lsr #8 @ r1<- AA + orr r0, r0, r2, lsl #16 @ r1<- BBBBbbbb + add r2, rFP, #OFF_FP_SHADOWFRAME + mov r3, rSELF + bl MterpConstString @ (index, tgt_reg, shadow_frame, self) + PREFETCH_INST 3 @ advance rPC + cmp r0, #0 @ fail? + bne MterpPossibleException @ let reference interpreter deal with it. + ADVANCE 3 @ advance rPC + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def op_const_wide(): + /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ + FETCH r0, 1 @ r0<- bbbb (low) + FETCH r1, 2 @ r1<- BBBB (low middle) + FETCH r2, 3 @ r2<- hhhh (high middle) + orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb (low word) + FETCH r3, 4 @ r3<- HHHH (high) + mov r9, rINST, lsr #8 @ r9<- AA + orr r1, r2, r3, lsl #16 @ r1<- HHHHhhhh (high word) + CLEAR_SHADOW_PAIR r9, r2, r3 @ Zero out the shadow regs + FETCH_ADVANCE_INST 5 @ advance rPC, load rINST + VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] + GET_INST_OPCODE ip @ extract opcode from rINST + stmia r9, {r0-r1} @ vAA<- r0/r1 + GOTO_OPCODE ip @ jump to next instruction + +%def op_const_wide_16(): + /* const-wide/16 vAA, #+BBBB */ + FETCH_S r0, 1 @ r0<- ssssBBBB (sign-extended) + mov r3, rINST, lsr #8 @ r3<- AA + mov r1, r0, asr #31 @ r1<- ssssssss + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + CLEAR_SHADOW_PAIR r3, r2, lr @ Zero out the shadow regs + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[AA] + GET_INST_OPCODE ip @ extract opcode from rINST + stmia r3, {r0-r1} @ vAA<- r0/r1 + GOTO_OPCODE ip @ jump to next instruction + +%def op_const_wide_32(): + /* const-wide/32 vAA, #+BBBBbbbb */ + FETCH r0, 1 @ r0<- 0000bbbb (low) + mov r3, rINST, lsr #8 @ r3<- AA + FETCH_S r2, 2 @ r2<- ssssBBBB (high) + FETCH_ADVANCE_INST 3 @ advance rPC, load rINST + orr r0, r0, r2, lsl #16 @ r0<- BBBBbbbb + CLEAR_SHADOW_PAIR r3, r2, lr @ Zero out the shadow regs + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[AA] + mov r1, r0, asr #31 @ r1<- ssssssss + GET_INST_OPCODE ip @ extract opcode from rINST + stmia r3, {r0-r1} @ vAA<- r0/r1 + GOTO_OPCODE ip @ jump to next instruction + +%def op_const_wide_high16(): + /* const-wide/high16 vAA, #+BBBB000000000000 */ + FETCH r1, 1 @ r1<- 0000BBBB (zero-extended) + mov r3, rINST, lsr #8 @ r3<- AA + mov r0, #0 @ r0<- 00000000 + mov r1, r1, lsl #16 @ r1<- BBBB0000 + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + CLEAR_SHADOW_PAIR r3, r0, r2 @ Zero shadow regs + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[AA] + GET_INST_OPCODE ip @ extract opcode from rINST + stmia r3, {r0-r1} @ vAA<- r0/r1 + GOTO_OPCODE ip @ jump to next instruction + +%def op_monitor_enter(): + /* + * Synchronize on an object. + */ + /* monitor-enter vAA */ + EXPORT_PC + mov r2, rINST, lsr #8 @ r2<- AA + GET_VREG r0, r2 @ r0<- vAA (object) + mov r1, rSELF @ r1<- self + bl artLockObjectFromCode + cmp r0, #0 + bne MterpException + FETCH_ADVANCE_INST 1 + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def op_monitor_exit(): + /* + * Unlock an object. + * + * Exceptions that occur when unlocking a monitor need to appear as + * if they happened at the following instruction. See the Dalvik + * instruction spec. + */ + /* monitor-exit vAA */ + EXPORT_PC + mov r2, rINST, lsr #8 @ r2<- AA + GET_VREG r0, r2 @ r0<- vAA (object) + mov r1, rSELF @ r0<- self + bl artUnlockObjectFromCode @ r0<- success for unlock(self, obj) + cmp r0, #0 @ failed? + bne MterpException + FETCH_ADVANCE_INST 1 @ before throw: advance rPC, load rINST + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def op_move(is_object="0"): + /* for move, move-object, long-to-int */ + /* op vA, vB */ + mov r1, rINST, lsr #12 @ r1<- B from 15:12 + ubfx r0, rINST, #8, #4 @ r0<- A from 11:8 + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + GET_VREG r2, r1 @ r2<- fp[B] + GET_INST_OPCODE ip @ ip<- opcode from rINST + .if $is_object + SET_VREG_OBJECT r2, r0 @ fp[A]<- r2 + .else + SET_VREG r2, r0 @ fp[A]<- r2 + .endif + GOTO_OPCODE ip @ execute next instruction + +%def op_move_16(is_object="0"): + /* for: move/16, move-object/16 */ + /* op vAAAA, vBBBB */ + FETCH r1, 2 @ r1<- BBBB + FETCH r0, 1 @ r0<- AAAA + FETCH_ADVANCE_INST 3 @ advance rPC, load rINST + GET_VREG r2, r1 @ r2<- fp[BBBB] + GET_INST_OPCODE ip @ extract opcode from rINST + .if $is_object + SET_VREG_OBJECT r2, r0 @ fp[AAAA]<- r2 + .else + SET_VREG r2, r0 @ fp[AAAA]<- r2 + .endif + GOTO_OPCODE ip @ jump to next instruction + +%def op_move_exception(): + /* move-exception vAA */ + mov r2, rINST, lsr #8 @ r2<- AA + ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] + mov r1, #0 @ r1<- 0 + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + SET_VREG_OBJECT r3, r2 @ fp[AA]<- exception obj + GET_INST_OPCODE ip @ extract opcode from rINST + str r1, [rSELF, #THREAD_EXCEPTION_OFFSET] @ clear exception + GOTO_OPCODE ip @ jump to next instruction + +%def op_move_from16(is_object="0"): + /* for: move/from16, move-object/from16 */ + /* op vAA, vBBBB */ + FETCH r1, 1 @ r1<- BBBB + mov r0, rINST, lsr #8 @ r0<- AA + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + GET_VREG r2, r1 @ r2<- fp[BBBB] + GET_INST_OPCODE ip @ extract opcode from rINST + .if $is_object + SET_VREG_OBJECT r2, r0 @ fp[AA]<- r2 + .else + SET_VREG r2, r0 @ fp[AA]<- r2 + .endif + GOTO_OPCODE ip @ jump to next instruction + +%def op_move_object(): +% op_move(is_object="1") + +%def op_move_object_16(): +% op_move_16(is_object="1") + +%def op_move_object_from16(): +% op_move_from16(is_object="1") + +%def op_move_result(is_object="0"): + /* for: move-result, move-result-object */ + /* op vAA */ + mov r2, rINST, lsr #8 @ r2<- AA + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + ldr r0, [rFP, #OFF_FP_RESULT_REGISTER] @ get pointer to result JType. + ldr r0, [r0] @ r0 <- result.i. + GET_INST_OPCODE ip @ extract opcode from rINST + .if $is_object + SET_VREG_OBJECT r0, r2, r1 @ fp[AA]<- r0 + .else + SET_VREG r0, r2 @ fp[AA]<- r0 + .endif + GOTO_OPCODE ip @ jump to next instruction + +%def op_move_result_object(): +% op_move_result(is_object="1") + +%def op_move_result_wide(): + /* move-result-wide vAA */ + mov rINST, rINST, lsr #8 @ rINST<- AA + ldr r3, [rFP, #OFF_FP_RESULT_REGISTER] + VREG_INDEX_TO_ADDR r2, rINST @ r2<- &fp[AA] + ldmia r3, {r0-r1} @ r0/r1<- retval.j + CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + stmia r2, {r0-r1} @ fp[AA]<- r0/r1 + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def op_move_wide(): + /* move-wide vA, vB */ + /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ + mov r3, rINST, lsr #12 @ r3<- B + ubfx rINST, rINST, #8, #4 @ rINST<- A + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] + VREG_INDEX_TO_ADDR r2, rINST @ r2<- &fp[A] + ldmia r3, {r0-r1} @ r0/r1<- fp[B] + CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + GET_INST_OPCODE ip @ extract opcode from rINST + stmia r2, {r0-r1} @ fp[A]<- r0/r1 + GOTO_OPCODE ip @ jump to next instruction + +%def op_move_wide_16(): + /* move-wide/16 vAAAA, vBBBB */ + /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ + FETCH r3, 2 @ r3<- BBBB + FETCH r2, 1 @ r2<- AAAA + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[BBBB] + VREG_INDEX_TO_ADDR lr, r2 @ r2<- &fp[AAAA] + ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] + FETCH_ADVANCE_INST 3 @ advance rPC, load rINST + CLEAR_SHADOW_PAIR r2, r3, ip @ Zero out the shadow regs + stmia lr, {r0-r1} @ fp[AAAA]<- r0/r1 + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def op_move_wide_from16(): + /* move-wide/from16 vAA, vBBBB */ + /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ + FETCH r3, 1 @ r3<- BBBB + mov rINST, rINST, lsr #8 @ rINST<- AA + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[BBBB] + VREG_INDEX_TO_ADDR r2, rINST @ r2<- &fp[AA] + ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] + CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + GET_INST_OPCODE ip @ extract opcode from rINST + stmia r2, {r0-r1} @ fp[AA]<- r0/r1 + GOTO_OPCODE ip @ jump to next instruction + +%def op_nop(): + FETCH_ADVANCE_INST 1 @ advance to next instr, load rINST + GET_INST_OPCODE ip @ ip<- opcode from rINST + GOTO_OPCODE ip @ execute it + +%def op_unused_3e(): +% unused() + +%def op_unused_3f(): +% unused() + +%def op_unused_40(): +% unused() + +%def op_unused_41(): +% unused() + +%def op_unused_42(): +% unused() + +%def op_unused_43(): +% unused() + +%def op_unused_73(): +% unused() + +%def op_unused_79(): +% unused() + +%def op_unused_7a(): +% unused() + +%def op_unused_f3(): +% unused() + +%def op_unused_f4(): +% unused() + +%def op_unused_f5(): +% unused() + +%def op_unused_f6(): +% unused() + +%def op_unused_f7(): +% unused() + +%def op_unused_f8(): +% unused() + +%def op_unused_f9(): +% unused() + +%def op_unused_fc(): +% unused() + +%def op_unused_fd(): +% unused() diff --git a/runtime/interpreter/mterp/arm/unop.S b/runtime/interpreter/mterp/arm/unop.S deleted file mode 100644 index a0b095411e..0000000000 --- a/runtime/interpreter/mterp/arm/unop.S +++ /dev/null @@ -1,20 +0,0 @@ -%def unop(preinstr="", instr=""): - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op r0". - * This could be an ARM instruction or a function call. - * - * for: neg-int, not-int, neg-float, int-to-float, float-to-int, - * int-to-byte, int-to-char, int-to-short - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r0, r3 @ r0<- vB - $preinstr @ optional op; may set condition codes - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - $instr @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 8-9 instructions */ diff --git a/runtime/interpreter/mterp/arm/unopNarrower.S b/runtime/interpreter/mterp/arm/unopNarrower.S deleted file mode 100644 index 4d1bdb90a6..0000000000 --- a/runtime/interpreter/mterp/arm/unopNarrower.S +++ /dev/null @@ -1,23 +0,0 @@ -%def unopNarrower(preinstr="", instr=""): - /* - * Generic 64bit-to-32bit unary operation. Provide an "instr" line - * that specifies an instruction that performs "result = op r0/r1", where - * "result" is a 32-bit quantity in r0. - * - * For: long-to-float, double-to-int, double-to-float - * - * (This would work for long-to-int, but that instruction is actually - * an exact match for op_move.) - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] - ldmia r3, {r0-r1} @ r0/r1<- vB/vB+1 - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - $preinstr @ optional op; may set condition codes - $instr @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 9-10 instructions */ diff --git a/runtime/interpreter/mterp/arm/unopWide.S b/runtime/interpreter/mterp/arm/unopWide.S deleted file mode 100644 index 658c2073d9..0000000000 --- a/runtime/interpreter/mterp/arm/unopWide.S +++ /dev/null @@ -1,22 +0,0 @@ -%def unopWide(preinstr="", instr=""): - /* - * Generic 64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op r0/r1". - * This could be an ARM instruction or a function call. - * - * For: neg-long, not-long, neg-double, long-to-double, double-to-long - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx rINST, rINST, #8, #4 @ rINST<- A - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] - ldmia r3, {r0-r1} @ r0/r1<- vAA - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - $preinstr @ optional op; may set condition codes - $instr @ r0/r1<- op, r2-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vAA<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 10-11 instructions */ diff --git a/runtime/interpreter/mterp/arm/unopWider.S b/runtime/interpreter/mterp/arm/unopWider.S deleted file mode 100644 index 8b3292719d..0000000000 --- a/runtime/interpreter/mterp/arm/unopWider.S +++ /dev/null @@ -1,21 +0,0 @@ -%def unopWider(preinstr="", instr=""): - /* - * Generic 32bit-to-64bit unary operation. Provide an "instr" line - * that specifies an instruction that performs "result = op r0", where - * "result" is a 64-bit quantity in r0/r1. - * - * For: int-to-long, int-to-double, float-to-long, float-to-double - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx rINST, rINST, #8, #4 @ rINST<- A - GET_VREG r0, r3 @ r0<- vB - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] - $preinstr @ optional op; may set condition codes - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - $instr @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 9-10 instructions */ diff --git a/runtime/interpreter/mterp/arm/unused.S b/runtime/interpreter/mterp/arm/unused.S deleted file mode 100644 index 3f37e74bb4..0000000000 --- a/runtime/interpreter/mterp/arm/unused.S +++ /dev/null @@ -1,5 +0,0 @@ -%def unused(): -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback diff --git a/runtime/interpreter/mterp/arm/zcmp.S b/runtime/interpreter/mterp/arm/zcmp.S deleted file mode 100644 index 6905a32499..0000000000 --- a/runtime/interpreter/mterp/arm/zcmp.S +++ /dev/null @@ -1,18 +0,0 @@ -%def zcmp(condition=""): - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - mov r0, rINST, lsr #8 @ r0<- AA - GET_VREG r0, r0 @ r0<- vAA - FETCH_S rINST, 1 @ rINST<- branch offset, in code units - cmp r0, #0 @ compare (vA, 0) - b${condition} MterpCommonTakenBranchNoFlags - cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? - beq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/alt_stub.S b/runtime/interpreter/mterp/arm64/alt_stub.S deleted file mode 100644 index 33434633cf..0000000000 --- a/runtime/interpreter/mterp/arm64/alt_stub.S +++ /dev/null @@ -1,13 +0,0 @@ -%def alt_stub(): -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (${opnum} * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. diff --git a/runtime/interpreter/mterp/arm64/arithmetic.S b/runtime/interpreter/mterp/arm64/arithmetic.S new file mode 100644 index 0000000000..cf9dd869d0 --- /dev/null +++ b/runtime/interpreter/mterp/arm64/arithmetic.S @@ -0,0 +1,507 @@ +%def binop(preinstr="", result="w0", chkzero="0", instr=""): + /* + * Generic 32-bit binary operation. Provide an "instr" line that + * specifies an instruction that performs "result = w0 op w1". + * This could be an ARM instruction or a function call. (If the result + * comes back in a register other than w0, you can override "result".) + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vCC (w1). Useful for integer division and modulus. Note that we + * *don't* check for (INT_MIN / -1) here, because the ARM math lib + * handles it correctly. + * + * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, + * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, + * mul-float, div-float, rem-float + */ + /* binop vAA, vBB, vCC */ + FETCH w0, 1 // w0<- CCBB + lsr w9, wINST, #8 // w9<- AA + lsr w3, w0, #8 // w3<- CC + and w2, w0, #255 // w2<- BB + GET_VREG w1, w3 // w1<- vCC + GET_VREG w0, w2 // w0<- vBB + .if $chkzero + cbz w1, common_errDivideByZero // is second operand zero? + .endif + FETCH_ADVANCE_INST 2 // advance rPC, load rINST + $preinstr // optional op; may set condition codes + $instr // $result<- op, w0-w3 changed + GET_INST_OPCODE ip // extract opcode from rINST + SET_VREG $result, w9 // vAA<- $result + GOTO_OPCODE ip // jump to next instruction + /* 11-14 instructions */ + +%def binop2addr(preinstr="", result="w0", chkzero="0", instr=""): + /* + * Generic 32-bit "/2addr" binary operation. Provide an "instr" line + * that specifies an instruction that performs "result = w0 op w1". + * This could be an ARM instruction or a function call. (If the result + * comes back in a register other than w0, you can override "result".) + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vCC (w1). Useful for integer division and modulus. + * + * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, + * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, + * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, + * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr + */ + /* binop/2addr vA, vB */ + lsr w3, wINST, #12 // w3<- B + ubfx w9, wINST, #8, #4 // w9<- A + GET_VREG w1, w3 // w1<- vB + GET_VREG w0, w9 // w0<- vA + .if $chkzero + cbz w1, common_errDivideByZero + .endif + FETCH_ADVANCE_INST 1 // advance rPC, load rINST + $preinstr // optional op; may set condition codes + $instr // $result<- op, w0-w3 changed + GET_INST_OPCODE ip // extract opcode from rINST + SET_VREG $result, w9 // vAA<- $result + GOTO_OPCODE ip // jump to next instruction + /* 10-13 instructions */ + +%def binopLit16(preinstr="", result="w0", chkzero="0", instr=""): + /* + * Generic 32-bit "lit16" binary operation. Provide an "instr" line + * that specifies an instruction that performs "result = w0 op w1". + * This could be an ARM instruction or a function call. (If the result + * comes back in a register other than w0, you can override "result".) + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vCC (w1). Useful for integer division and modulus. + * + * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, + * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 + */ + /* binop/lit16 vA, vB, #+CCCC */ + FETCH_S w1, 1 // w1<- ssssCCCC (sign-extended) + lsr w2, wINST, #12 // w2<- B + ubfx w9, wINST, #8, #4 // w9<- A + GET_VREG w0, w2 // w0<- vB + .if $chkzero + cbz w1, common_errDivideByZero + .endif + FETCH_ADVANCE_INST 2 // advance rPC, load rINST + $preinstr + $instr // $result<- op, w0-w3 changed + GET_INST_OPCODE ip // extract opcode from rINST + SET_VREG $result, w9 // vAA<- $result + GOTO_OPCODE ip // jump to next instruction + /* 10-13 instructions */ + +%def binopLit8(extract="asr w1, w3, #8", preinstr="", result="w0", chkzero="0", instr=""): + /* + * Generic 32-bit "lit8" binary operation. Provide an "instr" line + * that specifies an instruction that performs "result = w0 op w1". + * This could be an ARM instruction or a function call. (If the result + * comes back in a register other than w0, you can override "result".) + * + * You can override "extract" if the extraction of the literal value + * from w3 to w1 is not the default "asr w1, w3, #8". The extraction + * can be omitted completely if the shift is embedded in "instr". + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vCC (w1). Useful for integer division and modulus. + * + * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, + * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, + * shl-int/lit8, shr-int/lit8, ushr-int/lit8 + */ + /* binop/lit8 vAA, vBB, #+CC */ + FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC) + lsr w9, wINST, #8 // w9<- AA + and w2, w3, #255 // w2<- BB + GET_VREG w0, w2 // w0<- vBB + $extract // optional; typically w1<- ssssssCC (sign extended) + .if $chkzero + cbz w1, common_errDivideByZero + .endif + FETCH_ADVANCE_INST 2 // advance rPC, load rINST + $preinstr // optional op; may set condition codes + $instr // $result<- op, w0-w3 changed + GET_INST_OPCODE ip // extract opcode from rINST + SET_VREG $result, w9 // vAA<- $result + GOTO_OPCODE ip // jump to next instruction + /* 10-12 instructions */ + +%def binopWide(preinstr="", instr="add x0, x1, x2", result="x0", r1="x1", r2="x2", chkzero="0"): + /* + * Generic 64-bit binary operation. Provide an "instr" line that + * specifies an instruction that performs "result = x1 op x2". + * This could be an ARM instruction or a function call. (If the result + * comes back in a register other than x0, you can override "result".) + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vCC (w1). Useful for integer division and modulus. + * + * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, + * xor-long, add-double, sub-double, mul-double, div-double, rem-double + */ + /* binop vAA, vBB, vCC */ + FETCH w0, 1 // w0<- CCBB + lsr w4, wINST, #8 // w4<- AA + lsr w2, w0, #8 // w2<- CC + and w1, w0, #255 // w1<- BB + GET_VREG_WIDE $r2, w2 // w2<- vCC + GET_VREG_WIDE $r1, w1 // w1<- vBB + .if $chkzero + cbz $r2, common_errDivideByZero // is second operand zero? + .endif + FETCH_ADVANCE_INST 2 // advance rPC, load rINST + $preinstr + $instr // $result<- op, w0-w4 changed + GET_INST_OPCODE ip // extract opcode from rINST + SET_VREG_WIDE $result, w4 // vAA<- $result + GOTO_OPCODE ip // jump to next instruction + /* 11-14 instructions */ + +%def binopWide2addr(preinstr="", instr="add x0, x0, x1", r0="x0", r1="x1", chkzero="0"): + /* + * Generic 64-bit "/2addr" binary operation. Provide an "instr" line + * that specifies an instruction that performs "x0 = x0 op x1". + * This must not be a function call, as we keep w2 live across it. + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vCC (w1). Useful for integer division and modulus. + * + * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, + * and-long/2addr, or-long/2addr, xor-long/2addr, + * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, + * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr + */ + /* binop/2addr vA, vB */ + lsr w1, wINST, #12 // w1<- B + ubfx w2, wINST, #8, #4 // w2<- A + GET_VREG_WIDE $r1, w1 // x1<- vB + GET_VREG_WIDE $r0, w2 // x0<- vA + .if $chkzero + cbz $r1, common_errDivideByZero + .endif + FETCH_ADVANCE_INST 1 // advance rPC, load rINST + $preinstr + $instr // result<- op + GET_INST_OPCODE ip // extract opcode from rINST + SET_VREG_WIDE $r0, w2 // vAA<- result + GOTO_OPCODE ip // jump to next instruction + /* 10-13 instructions */ + +%def shiftWide(opcode="shl"): + /* + * 64-bit shift operation. + * + * For: shl-long, shr-long, ushr-long + */ + /* binop vAA, vBB, vCC */ + FETCH w0, 1 // w0<- CCBB + lsr w3, wINST, #8 // w3<- AA + lsr w2, w0, #8 // w2<- CC + GET_VREG w2, w2 // w2<- vCC (shift count) + and w1, w0, #255 // w1<- BB + GET_VREG_WIDE x1, w1 // x1<- vBB + FETCH_ADVANCE_INST 2 // advance rPC, load rINST + $opcode x0, x1, x2 // Do the shift. Only low 6 bits of x2 are used. + GET_INST_OPCODE ip // extract opcode from rINST + SET_VREG_WIDE x0, w3 // vAA<- x0 + GOTO_OPCODE ip // jump to next instruction + /* 11-14 instructions */ + +%def shiftWide2addr(opcode="lsl"): + /* + * Generic 64-bit shift operation. + */ + /* binop/2addr vA, vB */ + lsr w1, wINST, #12 // w1<- B + ubfx w2, wINST, #8, #4 // w2<- A + GET_VREG w1, w1 // x1<- vB + GET_VREG_WIDE x0, w2 // x0<- vA + FETCH_ADVANCE_INST 1 // advance rPC, load rINST + $opcode x0, x0, x1 // Do the shift. Only low 6 bits of x1 are used. + GET_INST_OPCODE ip // extract opcode from rINST + SET_VREG_WIDE x0, w2 // vAA<- result + GOTO_OPCODE ip // jump to next instruction + /* 10-13 instructions */ + +%def unop(instr=""): + /* + * Generic 32-bit unary operation. Provide an "instr" line that + * specifies an instruction that performs "result = op w0". + * This could be an ARM instruction or a function call. + * + * for: neg-int, not-int, neg-float, int-to-float, float-to-int, + * int-to-byte, int-to-char, int-to-short + */ + /* unop vA, vB */ + lsr w3, wINST, #12 // w3<- B + GET_VREG w0, w3 // w0<- vB + ubfx w9, wINST, #8, #4 // w9<- A + FETCH_ADVANCE_INST 1 // advance rPC, load rINST + $instr // w0<- op, w0-w3 changed + GET_INST_OPCODE ip // extract opcode from rINST + SET_VREG w0, w9 // vAA<- w0 + GOTO_OPCODE ip // jump to next instruction + /* 8-9 instructions */ + +%def unopWide(instr="sub x0, xzr, x0"): + /* + * Generic 64-bit unary operation. Provide an "instr" line that + * specifies an instruction that performs "result = op x0". + * + * For: neg-long, not-long + */ + /* unop vA, vB */ + lsr w3, wINST, #12 // w3<- B + ubfx w4, wINST, #8, #4 // w4<- A + GET_VREG_WIDE x0, w3 + FETCH_ADVANCE_INST 1 // advance rPC, load wINST + $instr + GET_INST_OPCODE ip // extract opcode from wINST + SET_VREG_WIDE x0, w4 + GOTO_OPCODE ip // jump to next instruction + /* 10-11 instructions */ + +%def op_add_int(): +% binop(instr="add w0, w0, w1") + +%def op_add_int_2addr(): +% binop2addr(instr="add w0, w0, w1") + +%def op_add_int_lit16(): +% binopLit16(instr="add w0, w0, w1") + +%def op_add_int_lit8(): +% binopLit8(extract="", instr="add w0, w0, w3, asr #8") + +%def op_add_long(): +% binopWide(instr="add x0, x1, x2") + +%def op_add_long_2addr(): +% binopWide2addr(instr="add x0, x0, x1") + +%def op_and_int(): +% binop(instr="and w0, w0, w1") + +%def op_and_int_2addr(): +% binop2addr(instr="and w0, w0, w1") + +%def op_and_int_lit16(): +% binopLit16(instr="and w0, w0, w1") + +%def op_and_int_lit8(): +% binopLit8(extract="", instr="and w0, w0, w3, asr #8") + +%def op_and_long(): +% binopWide(instr="and x0, x1, x2") + +%def op_and_long_2addr(): +% binopWide2addr(instr="and x0, x0, x1") + +%def op_cmp_long(): + FETCH w0, 1 // w0<- CCBB + lsr w4, wINST, #8 // w4<- AA + and w2, w0, #255 // w2<- BB + lsr w3, w0, #8 // w3<- CC + GET_VREG_WIDE x1, w2 + GET_VREG_WIDE x2, w3 + cmp x1, x2 + cset w0, ne + cneg w0, w0, lt + FETCH_ADVANCE_INST 2 // advance rPC, load wINST + SET_VREG w0, w4 + GET_INST_OPCODE ip // extract opcode from wINST + GOTO_OPCODE ip // jump to next instruction + +%def op_div_int(): +% binop(instr="sdiv w0, w0, w1", chkzero="1") + +%def op_div_int_2addr(): +% binop2addr(instr="sdiv w0, w0, w1", chkzero="1") + +%def op_div_int_lit16(): +% binopLit16(instr="sdiv w0, w0, w1", chkzero="1") + +%def op_div_int_lit8(): +% binopLit8(instr="sdiv w0, w0, w1", chkzero="1") + +%def op_div_long(): +% binopWide(instr="sdiv x0, x1, x2", chkzero="1") + +%def op_div_long_2addr(): +% binopWide2addr(instr="sdiv x0, x0, x1", chkzero="1") + +%def op_int_to_byte(): +% unop(instr="sxtb w0, w0") + +%def op_int_to_char(): +% unop(instr="uxth w0, w0") + +%def op_int_to_long(): + /* int-to-long vA, vB */ + lsr w3, wINST, #12 // w3<- B + ubfx w4, wINST, #8, #4 // w4<- A + GET_VREG_S x0, w3 // x0<- sign_extend(fp[B]) + FETCH_ADVANCE_INST 1 // advance rPC, load wINST + GET_INST_OPCODE ip // extract opcode from wINST + SET_VREG_WIDE x0, w4 // fp[A]<- x0 + GOTO_OPCODE ip // jump to next instruction + +%def op_int_to_short(): +% unop(instr="sxth w0, w0") + +%def op_long_to_int(): +/* we ignore the high word, making this equivalent to a 32-bit reg move */ +% op_move() + +%def op_mul_int(): +/* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */ +% binop(instr="mul w0, w1, w0") + +%def op_mul_int_2addr(): +/* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */ +% binop2addr(instr="mul w0, w1, w0") + +%def op_mul_int_lit16(): +/* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */ +% binopLit16(instr="mul w0, w1, w0") + +%def op_mul_int_lit8(): +/* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */ +% binopLit8(instr="mul w0, w1, w0") + +%def op_mul_long(): +% binopWide(instr="mul x0, x1, x2") + +%def op_mul_long_2addr(): +% binopWide2addr(instr="mul x0, x0, x1") + +%def op_neg_int(): +% unop(instr="sub w0, wzr, w0") + +%def op_neg_long(): +% unopWide(instr="sub x0, xzr, x0") + +%def op_not_int(): +% unop(instr="mvn w0, w0") + +%def op_not_long(): +% unopWide(instr="mvn x0, x0") + +%def op_or_int(): +% binop(instr="orr w0, w0, w1") + +%def op_or_int_2addr(): +% binop2addr(instr="orr w0, w0, w1") + +%def op_or_int_lit16(): +% binopLit16(instr="orr w0, w0, w1") + +%def op_or_int_lit8(): +% binopLit8(extract="", instr="orr w0, w0, w3, asr #8") + +%def op_or_long(): +% binopWide(instr="orr x0, x1, x2") + +%def op_or_long_2addr(): +% binopWide2addr(instr="orr x0, x0, x1") + +%def op_rem_int(): +% binop(preinstr="sdiv w2, w0, w1", instr="msub w0, w2, w1, w0", chkzero="1") + +%def op_rem_int_2addr(): +% binop2addr(preinstr="sdiv w2, w0, w1", instr="msub w0, w2, w1, w0", chkzero="1") + +%def op_rem_int_lit16(): +% binopLit16(preinstr="sdiv w3, w0, w1", instr="msub w0, w3, w1, w0", chkzero="1") + +%def op_rem_int_lit8(): +% binopLit8(preinstr="sdiv w3, w0, w1", instr="msub w0, w3, w1, w0", chkzero="1") + +%def op_rem_long(): +% binopWide(preinstr="sdiv x3, x1, x2", instr="msub x0, x3, x2, x1", chkzero="1") + +%def op_rem_long_2addr(): +% binopWide2addr(preinstr="sdiv x3, x0, x1", instr="msub x0, x3, x1, x0", chkzero="1") + +%def op_rsub_int(): +/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ +% binopLit16(instr="sub w0, w1, w0") + +%def op_rsub_int_lit8(): +% binopLit8(instr="sub w0, w1, w0") + +%def op_shl_int(): +% binop(instr="lsl w0, w0, w1") + +%def op_shl_int_2addr(): +% binop2addr(instr="lsl w0, w0, w1") + +%def op_shl_int_lit8(): +% binopLit8(extract="ubfx w1, w3, #8, #5", instr="lsl w0, w0, w1") + +%def op_shl_long(): +% shiftWide(opcode="lsl") + +%def op_shl_long_2addr(): +% shiftWide2addr(opcode="lsl") + +%def op_shr_int(): +% binop(instr="asr w0, w0, w1") + +%def op_shr_int_2addr(): +% binop2addr(instr="asr w0, w0, w1") + +%def op_shr_int_lit8(): +% binopLit8(extract="ubfx w1, w3, #8, #5", instr="asr w0, w0, w1") + +%def op_shr_long(): +% shiftWide(opcode="asr") + +%def op_shr_long_2addr(): +% shiftWide2addr(opcode="asr") + +%def op_sub_int(): +% binop(instr="sub w0, w0, w1") + +%def op_sub_int_2addr(): +% binop2addr(instr="sub w0, w0, w1") + +%def op_sub_long(): +% binopWide(instr="sub x0, x1, x2") + +%def op_sub_long_2addr(): +% binopWide2addr(instr="sub x0, x0, x1") + +%def op_ushr_int(): +% binop(instr="lsr w0, w0, w1") + +%def op_ushr_int_2addr(): +% binop2addr(instr="lsr w0, w0, w1") + +%def op_ushr_int_lit8(): +% binopLit8(extract="ubfx w1, w3, #8, #5", instr="lsr w0, w0, w1") + +%def op_ushr_long(): +% shiftWide(opcode="lsr") + +%def op_ushr_long_2addr(): +% shiftWide2addr(opcode="lsr") + +%def op_xor_int(): +% binop(instr="eor w0, w0, w1") + +%def op_xor_int_2addr(): +% binop2addr(instr="eor w0, w0, w1") + +%def op_xor_int_lit16(): +% binopLit16(instr="eor w0, w0, w1") + +%def op_xor_int_lit8(): +% binopLit8(extract="", instr="eor w0, w0, w3, asr #8") + +%def op_xor_long(): +% binopWide(instr="eor x0, x1, x2") + +%def op_xor_long_2addr(): +% binopWide2addr(instr="eor x0, x0, x1") diff --git a/runtime/interpreter/mterp/arm64/array.S b/runtime/interpreter/mterp/arm64/array.S new file mode 100644 index 0000000000..a023d22ff5 --- /dev/null +++ b/runtime/interpreter/mterp/arm64/array.S @@ -0,0 +1,235 @@ +%def op_aget(load="ldr", shift="2", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"): + /* + * Array get, 32 bits or less. vAA <- vBB[vCC]. + * + * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 + * instructions. We use a pair of FETCH_Bs instead. + * + * for: aget, aget-boolean, aget-byte, aget-char, aget-short + * + * NOTE: assumes data offset for arrays is the same for all non-wide types. + * If this changes, specialize. + */ + /* op vAA, vBB, vCC */ + FETCH_B w2, 1, 0 // w2<- BB + lsr w9, wINST, #8 // w9<- AA + FETCH_B w3, 1, 1 // w3<- CC + GET_VREG w0, w2 // w0<- vBB (array object) + GET_VREG w1, w3 // w1<- vCC (requested index) + cbz x0, common_errNullObject // bail if null array object. + ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length + add x0, x0, w1, uxtw #$shift // w0<- arrayObj + index*width + cmp w1, w3 // compare unsigned index, length + bcs common_errArrayIndex // index >= length, bail + FETCH_ADVANCE_INST 2 // advance rPC, load rINST + $load w2, [x0, #$data_offset] // w2<- vBB[vCC] + GET_INST_OPCODE ip // extract opcode from rINST + SET_VREG w2, w9 // vAA<- w2 + GOTO_OPCODE ip // jump to next instruction + +%def op_aget_boolean(): +% op_aget(load="ldrb", shift="0", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") + +%def op_aget_byte(): +% op_aget(load="ldrsb", shift="0", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") + +%def op_aget_char(): +% op_aget(load="ldrh", shift="1", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") + +%def op_aget_object(): + /* + * Array object get. vAA <- vBB[vCC]. + * + * for: aget-object + */ + /* op vAA, vBB, vCC */ + FETCH_B w2, 1, 0 // w2<- BB + FETCH_B w3, 1, 1 // w3<- CC + EXPORT_PC + GET_VREG w0, w2 // w0<- vBB (array object) + GET_VREG w1, w3 // w1<- vCC (requested index) + bl artAGetObjectFromMterp // (array, index) + ldr x1, [xSELF, #THREAD_EXCEPTION_OFFSET] + lsr w2, wINST, #8 // w9<- AA + PREFETCH_INST 2 + cbnz w1, MterpException + SET_VREG_OBJECT w0, w2 + ADVANCE 2 + GET_INST_OPCODE ip + GOTO_OPCODE ip // jump to next instruction + +%def op_aget_short(): +% op_aget(load="ldrsh", shift="1", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") + +%def op_aget_wide(): + /* + * Array get, 64 bits. vAA <- vBB[vCC]. + * + */ + /* aget-wide vAA, vBB, vCC */ + FETCH w0, 1 // w0<- CCBB + lsr w4, wINST, #8 // w4<- AA + and w2, w0, #255 // w2<- BB + lsr w3, w0, #8 // w3<- CC + GET_VREG w0, w2 // w0<- vBB (array object) + GET_VREG w1, w3 // w1<- vCC (requested index) + cbz w0, common_errNullObject // yes, bail + ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length + add x0, x0, w1, lsl #3 // w0<- arrayObj + index*width + cmp w1, w3 // compare unsigned index, length + bcs common_errArrayIndex // index >= length, bail + FETCH_ADVANCE_INST 2 // advance rPC, load wINST + ldr x2, [x0, #MIRROR_WIDE_ARRAY_DATA_OFFSET] // x2<- vBB[vCC] + GET_INST_OPCODE ip // extract opcode from wINST + SET_VREG_WIDE x2, w4 + GOTO_OPCODE ip // jump to next instruction + +%def op_aput(store="str", shift="2", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"): + /* + * Array put, 32 bits or less. vBB[vCC] <- vAA. + * + * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 + * instructions. We use a pair of FETCH_Bs instead. + * + * for: aput, aput-boolean, aput-byte, aput-char, aput-short + * + * NOTE: this assumes data offset for arrays is the same for all non-wide types. + * If this changes, specialize. + */ + /* op vAA, vBB, vCC */ + FETCH_B w2, 1, 0 // w2<- BB + lsr w9, wINST, #8 // w9<- AA + FETCH_B w3, 1, 1 // w3<- CC + GET_VREG w0, w2 // w0<- vBB (array object) + GET_VREG w1, w3 // w1<- vCC (requested index) + cbz w0, common_errNullObject // bail if null + ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length + add x0, x0, w1, lsl #$shift // w0<- arrayObj + index*width + cmp w1, w3 // compare unsigned index, length + bcs common_errArrayIndex // index >= length, bail + FETCH_ADVANCE_INST 2 // advance rPC, load rINST + GET_VREG w2, w9 // w2<- vAA + GET_INST_OPCODE ip // extract opcode from rINST + $store w2, [x0, #$data_offset] // vBB[vCC]<- w2 + GOTO_OPCODE ip // jump to next instruction + +%def op_aput_boolean(): +% op_aput(store="strb", shift="0", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") + +%def op_aput_byte(): +% op_aput(store="strb", shift="0", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") + +%def op_aput_char(): +% op_aput(store="strh", shift="1", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") + +%def op_aput_object(): + /* + * Store an object into an array. vBB[vCC] <- vAA. + */ + /* op vAA, vBB, vCC */ + EXPORT_PC + add x0, xFP, #OFF_FP_SHADOWFRAME + mov x1, xPC + mov w2, wINST + bl MterpAputObject + cbz w0, MterpPossibleException + FETCH_ADVANCE_INST 2 // advance rPC, load rINST + GET_INST_OPCODE ip // extract opcode from rINST + GOTO_OPCODE ip // jump to next instruction + +%def op_aput_short(): +% op_aput(store="strh", shift="1", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") + +%def op_aput_wide(): + /* + * Array put, 64 bits. vBB[vCC] <- vAA. + * + */ + /* aput-wide vAA, vBB, vCC */ + FETCH w0, 1 // w0<- CCBB + lsr w4, wINST, #8 // w4<- AA + and w2, w0, #255 // w2<- BB + lsr w3, w0, #8 // w3<- CC + GET_VREG w0, w2 // w0<- vBB (array object) + GET_VREG w1, w3 // w1<- vCC (requested index) + cbz w0, common_errNullObject // bail if null + ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length + add x0, x0, w1, lsl #3 // w0<- arrayObj + index*width + cmp w1, w3 // compare unsigned index, length + bcs common_errArrayIndex // index >= length, bail + GET_VREG_WIDE x1, w4 + FETCH_ADVANCE_INST 2 // advance rPC, load wINST + GET_INST_OPCODE ip // extract opcode from wINST + str x1, [x0, #MIRROR_WIDE_ARRAY_DATA_OFFSET] + GOTO_OPCODE ip // jump to next instruction + +%def op_array_length(): + /* + * Return the length of an array. + */ + lsr w1, wINST, #12 // w1<- B + ubfx w2, wINST, #8, #4 // w2<- A + GET_VREG w0, w1 // w0<- vB (object ref) + cbz w0, common_errNullObject // yup, fail + FETCH_ADVANCE_INST 1 // advance rPC, load rINST + ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- array length + GET_INST_OPCODE ip // extract opcode from rINST + SET_VREG w3, w2 // vB<- length + GOTO_OPCODE ip // jump to next instruction + +%def op_fill_array_data(): + /* fill-array-data vAA, +BBBBBBBB */ + EXPORT_PC + FETCH w0, 1 // x0<- 000000000000bbbb (lo) + FETCH_S x1, 2 // x1<- ssssssssssssBBBB (hi) + lsr w3, wINST, #8 // w3<- AA + orr x1, x0, x1, lsl #16 // x1<- ssssssssBBBBbbbb + GET_VREG w0, w3 // w0<- vAA (array object) + add x1, xPC, x1, lsl #1 // x1<- PC + ssssssssBBBBbbbb*2 (array data off.) + bl MterpFillArrayData // (obj, payload) + cbz w0, MterpPossibleException // exception? + FETCH_ADVANCE_INST 3 // advance rPC, load rINST + GET_INST_OPCODE ip // extract opcode from rINST + GOTO_OPCODE ip // jump to next instruction + +%def op_filled_new_array(helper="MterpFilledNewArray"): + /* + * Create a new array with elements filled from registers. + * + * for: filled-new-array, filled-new-array/range + */ + /* op vB, {vD, vE, vF, vG, vA}, class//CCCC */ + /* op {vCCCC..v(CCCC+AA-1)}, type//BBBB */ + .extern $helper + EXPORT_PC + add x0, xFP, #OFF_FP_SHADOWFRAME + mov x1, xPC + mov x2, xSELF + bl $helper + cbz w0, MterpPossibleException + FETCH_ADVANCE_INST 3 // advance rPC, load rINST + GET_INST_OPCODE ip // extract opcode from rINST + GOTO_OPCODE ip // jump to next instruction + +%def op_filled_new_array_range(): +% op_filled_new_array(helper="MterpFilledNewArrayRange") + +%def op_new_array(): + /* + * Allocate an array of objects, specified with the array class + * and a count. + * + * The verifier guarantees that this is an array class, so we don't + * check for it here. + */ + /* new-array vA, vB, class//CCCC */ + EXPORT_PC + add x0, xFP, #OFF_FP_SHADOWFRAME + mov x1, xPC + mov w2, wINST + mov x3, xSELF + bl MterpNewArray + cbz w0, MterpPossibleException + FETCH_ADVANCE_INST 2 // advance rPC, load rINST + GET_INST_OPCODE ip // extract opcode from rINST + GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/bincmp.S b/runtime/interpreter/mterp/arm64/bincmp.S deleted file mode 100644 index 80ffbc5f3b..0000000000 --- a/runtime/interpreter/mterp/arm64/bincmp.S +++ /dev/null @@ -1,20 +0,0 @@ -%def bincmp(condition=""): - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - lsr w1, wINST, #12 // w1<- B - ubfx w0, wINST, #8, #4 // w0<- A - GET_VREG w3, w1 // w3<- vB - GET_VREG w2, w0 // w2<- vA - FETCH_S wINST, 1 // wINST<- branch offset, in code units - cmp w2, w3 // compare (vA, vB) - b.${condition} MterpCommonTakenBranchNoFlags - cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? - b.eq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/binop.S b/runtime/interpreter/mterp/arm64/binop.S deleted file mode 100644 index be4db17515..0000000000 --- a/runtime/interpreter/mterp/arm64/binop.S +++ /dev/null @@ -1,33 +0,0 @@ -%def binop(preinstr="", result="w0", chkzero="0", instr=""): - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w9, wINST, #8 // w9<- AA - lsr w3, w0, #8 // w3<- CC - and w2, w0, #255 // w2<- BB - GET_VREG w1, w3 // w1<- vCC - GET_VREG w0, w2 // w0<- vBB - .if $chkzero - cbz w1, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - $preinstr // optional op; may set condition codes - $instr // $result<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG $result, w9 // vAA<- $result - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ diff --git a/runtime/interpreter/mterp/arm64/binop2addr.S b/runtime/interpreter/mterp/arm64/binop2addr.S deleted file mode 100644 index 5b46b12157..0000000000 --- a/runtime/interpreter/mterp/arm64/binop2addr.S +++ /dev/null @@ -1,30 +0,0 @@ -%def binop2addr(preinstr="", result="w0", chkzero="0", instr=""): - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG w1, w3 // w1<- vB - GET_VREG w0, w9 // w0<- vA - .if $chkzero - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - $preinstr // optional op; may set condition codes - $instr // $result<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG $result, w9 // vAA<- $result - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ diff --git a/runtime/interpreter/mterp/arm64/binopLit16.S b/runtime/interpreter/mterp/arm64/binopLit16.S deleted file mode 100644 index b8af7d18fc..0000000000 --- a/runtime/interpreter/mterp/arm64/binopLit16.S +++ /dev/null @@ -1,28 +0,0 @@ -%def binopLit16(preinstr="", result="w0", chkzero="0", instr=""): - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - FETCH_S w1, 1 // w1<- ssssCCCC (sign-extended) - lsr w2, wINST, #12 // w2<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG w0, w2 // w0<- vB - .if $chkzero - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - $preinstr - $instr // $result<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG $result, w9 // vAA<- $result - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ diff --git a/runtime/interpreter/mterp/arm64/binopLit8.S b/runtime/interpreter/mterp/arm64/binopLit8.S deleted file mode 100644 index e7161a7d4b..0000000000 --- a/runtime/interpreter/mterp/arm64/binopLit8.S +++ /dev/null @@ -1,34 +0,0 @@ -%def binopLit8(extract="asr w1, w3, #8", preinstr="", result="w0", chkzero="0", instr=""): - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from w3 to w1 is not the default "asr w1, w3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC) - lsr w9, wINST, #8 // w9<- AA - and w2, w3, #255 // w2<- BB - GET_VREG w0, w2 // w0<- vBB - $extract // optional; typically w1<- ssssssCC (sign extended) - .if $chkzero - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - $preinstr // optional op; may set condition codes - $instr // $result<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG $result, w9 // vAA<- $result - GOTO_OPCODE ip // jump to next instruction - /* 10-12 instructions */ diff --git a/runtime/interpreter/mterp/arm64/binopWide.S b/runtime/interpreter/mterp/arm64/binopWide.S deleted file mode 100644 index 829b53067f..0000000000 --- a/runtime/interpreter/mterp/arm64/binopWide.S +++ /dev/null @@ -1,30 +0,0 @@ -%def binopWide(preinstr="", instr="add x0, x1, x2", result="x0", r1="x1", r2="x2", chkzero="0"): - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = x1 op x2". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than x0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, rem-double - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - lsr w2, w0, #8 // w2<- CC - and w1, w0, #255 // w1<- BB - GET_VREG_WIDE $r2, w2 // w2<- vCC - GET_VREG_WIDE $r1, w1 // w1<- vBB - .if $chkzero - cbz $r2, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - $preinstr - $instr // $result<- op, w0-w4 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE $result, w4 // vAA<- $result - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ diff --git a/runtime/interpreter/mterp/arm64/binopWide2addr.S b/runtime/interpreter/mterp/arm64/binopWide2addr.S deleted file mode 100644 index dbd6b3b853..0000000000 --- a/runtime/interpreter/mterp/arm64/binopWide2addr.S +++ /dev/null @@ -1,29 +0,0 @@ -%def binopWide2addr(preinstr="", instr="add x0, x0, x1", r0="x0", r1="x1", chkzero="0"): - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "x0 = x0 op x1". - * This must not be a function call, as we keep w2 live across it. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr - */ - /* binop/2addr vA, vB */ - lsr w1, wINST, #12 // w1<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG_WIDE $r1, w1 // x1<- vB - GET_VREG_WIDE $r0, w2 // x0<- vA - .if $chkzero - cbz $r1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - $preinstr - $instr // result<- op - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE $r0, w2 // vAA<- result - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ diff --git a/runtime/interpreter/mterp/arm64/close_cfi.S b/runtime/interpreter/mterp/arm64/close_cfi.S deleted file mode 100644 index 8f651b18f0..0000000000 --- a/runtime/interpreter/mterp/arm64/close_cfi.S +++ /dev/null @@ -1,5 +0,0 @@ -%def close_cfi(): -// Close out the cfi info. We're treating mterp as a single function. - -END ExecuteMterpImpl - diff --git a/runtime/interpreter/mterp/arm64/const.S b/runtime/interpreter/mterp/arm64/const.S deleted file mode 100644 index f8477a8b12..0000000000 --- a/runtime/interpreter/mterp/arm64/const.S +++ /dev/null @@ -1,17 +0,0 @@ -%def const(helper="UndefinedConstHandler"): - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern $helper - EXPORT_PC - FETCH w0, 1 // w0<- BBBB - lsr w1, wINST, #8 // w1<- AA - add x2, xFP, #OFF_FP_SHADOWFRAME - mov x3, xSELF - bl $helper // (index, tgt_reg, shadow_frame, self) - PREFETCH_INST 2 // load rINST - cbnz w0, MterpPossibleException // let reference interpreter deal with it. - ADVANCE 2 // advance rPC - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/control_flow.S b/runtime/interpreter/mterp/arm64/control_flow.S new file mode 100644 index 0000000000..b634c9812c --- /dev/null +++ b/runtime/interpreter/mterp/arm64/control_flow.S @@ -0,0 +1,223 @@ +%def bincmp(condition=""): + /* + * Generic two-operand compare-and-branch operation. Provide a "condition" + * fragment that specifies the comparison to perform. + * + * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le + */ + /* if-cmp vA, vB, +CCCC */ + lsr w1, wINST, #12 // w1<- B + ubfx w0, wINST, #8, #4 // w0<- A + GET_VREG w3, w1 // w3<- vB + GET_VREG w2, w0 // w2<- vA + FETCH_S wINST, 1 // wINST<- branch offset, in code units + cmp w2, w3 // compare (vA, vB) + b.${condition} MterpCommonTakenBranchNoFlags + cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? + b.eq .L_check_not_taken_osr + FETCH_ADVANCE_INST 2 + GET_INST_OPCODE ip // extract opcode from wINST + GOTO_OPCODE ip // jump to next instruction + +%def zcmp(compare="1", branch=""): + /* + * Generic one-operand compare-and-branch operation. Provide a "condition" + * fragment that specifies the comparison to perform. + * + * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez + */ + /* if-cmp vAA, +BBBB */ + lsr w0, wINST, #8 // w0<- AA + GET_VREG w2, w0 // w2<- vAA + FETCH_S wINST, 1 // w1<- branch offset, in code units + .if ${compare} + cmp w2, #0 // compare (vA, 0) + .endif + ${branch} MterpCommonTakenBranchNoFlags + cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? + b.eq .L_check_not_taken_osr + FETCH_ADVANCE_INST 2 + GET_INST_OPCODE ip // extract opcode from wINST + GOTO_OPCODE ip // jump to next instruction + +%def op_goto(): + /* + * Unconditional branch, 8-bit offset. + * + * The branch distance is a signed code-unit offset, which we need to + * double to get a byte offset. + */ + /* goto +AA */ + sbfx wINST, wINST, #8, #8 // wINST<- ssssssAA (sign-extended) + b MterpCommonTakenBranchNoFlags + +%def op_goto_16(): + /* + * Unconditional branch, 16-bit offset. + * + * The branch distance is a signed code-unit offset, which we need to + * double to get a byte offset. + */ + /* goto/16 +AAAA */ + FETCH_S wINST, 1 // wINST<- ssssAAAA (sign-extended) + b MterpCommonTakenBranchNoFlags + +%def op_goto_32(): + /* + * Unconditional branch, 32-bit offset. + * + * The branch distance is a signed code-unit offset, which we need to + * double to get a byte offset. + * + * Unlike most opcodes, this one is allowed to branch to itself, so + * our "backward branch" test must be "<=0" instead of "<0". Because + * we need the V bit set, we'll use an adds to convert from Dalvik + * offset to byte offset. + */ + /* goto/32 +AAAAAAAA */ + FETCH w0, 1 // w0<- aaaa (lo) + FETCH w1, 2 // w1<- AAAA (hi) + orr wINST, w0, w1, lsl #16 // wINST<- AAAAaaaa + b MterpCommonTakenBranchNoFlags + +%def op_if_eq(): +% bincmp(condition="eq") + +%def op_if_eqz(): +% zcmp(compare="0", branch="cbz w2,") + +%def op_if_ge(): +% bincmp(condition="ge") + +%def op_if_gez(): +% zcmp(compare="0", branch="tbz w2, #31,") + +%def op_if_gt(): +% bincmp(condition="gt") + +%def op_if_gtz(): +% zcmp(branch="b.gt") + +%def op_if_le(): +% bincmp(condition="le") + +%def op_if_lez(): +% zcmp(branch="b.le") + +%def op_if_lt(): +% bincmp(condition="lt") + +%def op_if_ltz(): +% zcmp(compare="0", branch="tbnz w2, #31,") + +%def op_if_ne(): +% bincmp(condition="ne") + +%def op_if_nez(): +% zcmp(compare="0", branch="cbnz w2,") + +%def op_packed_switch(func="MterpDoPackedSwitch"): + /* + * Handle a packed-switch or sparse-switch instruction. In both cases + * we decode it and hand it off to a helper function. + * + * We don't really expect backward branches in a switch statement, but + * they're perfectly legal, so we check for them here. + * + * for: packed-switch, sparse-switch + */ + /* op vAA, +BBBB */ + FETCH w0, 1 // x0<- 000000000000bbbb (lo) + FETCH_S x1, 2 // x1<- ssssssssssssBBBB (hi) + lsr w3, wINST, #8 // w3<- AA + orr x0, x0, x1, lsl #16 // x0<- ssssssssBBBBbbbb + GET_VREG w1, w3 // w1<- vAA + add x0, xPC, x0, lsl #1 // x0<- PC + ssssssssBBBBbbbb*2 + bl $func // w0<- code-unit branch offset + sxtw xINST, w0 + b MterpCommonTakenBranchNoFlags + +%def op_return(): + /* + * Return a 32-bit value. + * + * for: return, return-object + */ + /* op vAA */ + .extern MterpThreadFenceForConstructor + bl MterpThreadFenceForConstructor + ldr w7, [xSELF, #THREAD_FLAGS_OFFSET] + mov x0, xSELF + ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST + b.ne .L${opcode}_check +.L${opcode}_return: + lsr w2, wINST, #8 // r2<- AA + GET_VREG w0, w2 // r0<- vAA + b MterpReturn +.L${opcode}_check: + bl MterpSuspendCheck // (self) + b .L${opcode}_return + +%def op_return_object(): +% op_return() + +%def op_return_void(): + .extern MterpThreadFenceForConstructor + bl MterpThreadFenceForConstructor + ldr w7, [xSELF, #THREAD_FLAGS_OFFSET] + mov x0, xSELF + ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST + b.ne .L${opcode}_check +.L${opcode}_return: + mov x0, #0 + b MterpReturn +.L${opcode}_check: + bl MterpSuspendCheck // (self) + b .L${opcode}_return + +%def op_return_void_no_barrier(): + ldr w7, [xSELF, #THREAD_FLAGS_OFFSET] + mov x0, xSELF + ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST + b.ne .L${opcode}_check +.L${opcode}_return: + mov x0, #0 + b MterpReturn +.L${opcode}_check: + bl MterpSuspendCheck // (self) + b .L${opcode}_return + +%def op_return_wide(): + /* + * Return a 64-bit value. + */ + /* return-wide vAA */ + /* op vAA */ + .extern MterpThreadFenceForConstructor + bl MterpThreadFenceForConstructor + ldr w7, [xSELF, #THREAD_FLAGS_OFFSET] + mov x0, xSELF + ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST + b.ne .L${opcode}_check +.L${opcode}_return: + lsr w2, wINST, #8 // w2<- AA + GET_VREG_WIDE x0, w2 // x0<- vAA + b MterpReturn +.L${opcode}_check: + bl MterpSuspendCheck // (self) + b .L${opcode}_return + +%def op_sparse_switch(): +% op_packed_switch(func="MterpDoSparseSwitch") + +%def op_throw(): + /* + * Throw an exception object in the current thread. + */ + /* throw vAA */ + EXPORT_PC + lsr w2, wINST, #8 // r2<- AA + GET_VREG w1, w2 // r1<- vAA (exception object) + cbz w1, common_errNullObject + str x1, [xSELF, #THREAD_EXCEPTION_OFFSET] // thread->exception<- obj + b MterpException diff --git a/runtime/interpreter/mterp/arm64/entry.S b/runtime/interpreter/mterp/arm64/entry.S deleted file mode 100644 index baf8afce6e..0000000000 --- a/runtime/interpreter/mterp/arm64/entry.S +++ /dev/null @@ -1,67 +0,0 @@ -%def entry(): -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - .text - -/* - * Interpreter entry point. - * On entry: - * x0 Thread* self/ - * x1 insns_ - * x2 ShadowFrame - * x3 JValue* result_register - * - */ -ENTRY ExecuteMterpImpl - SAVE_TWO_REGS_INCREASE_FRAME xPROFILE, x27, 80 - SAVE_TWO_REGS xIBASE, xREFS, 16 - SAVE_TWO_REGS xSELF, xINST, 32 - SAVE_TWO_REGS xPC, xFP, 48 - SAVE_TWO_REGS fp, lr, 64 - add fp, sp, #64 - - /* Remember the return register */ - str x3, [x2, #SHADOWFRAME_RESULT_REGISTER_OFFSET] - - /* Remember the dex instruction pointer */ - str x1, [x2, #SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET] - - /* set up "named" registers */ - mov xSELF, x0 - ldr w0, [x2, #SHADOWFRAME_NUMBER_OF_VREGS_OFFSET] - add xFP, x2, #SHADOWFRAME_VREGS_OFFSET // point to vregs. - add xREFS, xFP, w0, lsl #2 // point to reference array in shadow frame - ldr w0, [x2, #SHADOWFRAME_DEX_PC_OFFSET] // Get starting dex_pc. - add xPC, x1, w0, lsl #1 // Create direct pointer to 1st dex opcode - CFI_DEFINE_DEX_PC_WITH_OFFSET(CFI_TMP, CFI_DEX, 0) - EXPORT_PC - - /* Starting ibase */ - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] - - /* Set up for backwards branches & osr profiling */ - ldr x0, [xFP, #OFF_FP_METHOD] - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xSELF - bl MterpSetUpHotnessCountdown - mov wPROFILE, w0 // Starting hotness countdown to xPROFILE - - /* start executing the instruction at rPC */ - FETCH_INST // load wINST from rPC - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - /* NOTE: no fallthrough */ diff --git a/runtime/interpreter/mterp/arm64/fallback.S b/runtime/interpreter/mterp/arm64/fallback.S deleted file mode 100644 index 3685700dec..0000000000 --- a/runtime/interpreter/mterp/arm64/fallback.S +++ /dev/null @@ -1,4 +0,0 @@ -%def fallback(): -/* Transfer stub to alternate interpreter */ - b MterpFallback - diff --git a/runtime/interpreter/mterp/arm64/fbinop.S b/runtime/interpreter/mterp/arm64/fbinop.S deleted file mode 100644 index e3fb25a8da..0000000000 --- a/runtime/interpreter/mterp/arm64/fbinop.S +++ /dev/null @@ -1,19 +0,0 @@ -%def fbinop(instr=""): - /*: - * Generic 32-bit floating-point operation. - * - * For: add-float, sub-float, mul-float, div-float - * form: s0, s0, s1 - */ - /* floatop vAA, vBB, vCC */ - FETCH w0, 1 // r0<- CCBB - lsr w1, w0, #8 // r2<- CC - and w0, w0, #255 // r1<- BB - GET_VREG s1, w1 - GET_VREG s0, w0 - $instr // s0<- op - lsr w1, wINST, #8 // r1<- AA - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG s0, w1 - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/fbinop2addr.S b/runtime/interpreter/mterp/arm64/fbinop2addr.S deleted file mode 100644 index 9f235d94b6..0000000000 --- a/runtime/interpreter/mterp/arm64/fbinop2addr.S +++ /dev/null @@ -1,18 +0,0 @@ -%def fbinop2addr(instr=""): - /* - * Generic 32-bit floating point "/2addr" binary operation. Provide - * an "instr" line that specifies an instruction that performs - * "s2 = s0 op s1". - * - * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr - */ - /* binop/2addr vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG s1, w3 - GET_VREG s0, w9 - $instr // s2<- op - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG s2, w9 - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/fcmp.S b/runtime/interpreter/mterp/arm64/fcmp.S deleted file mode 100644 index c0cc33afcd..0000000000 --- a/runtime/interpreter/mterp/arm64/fcmp.S +++ /dev/null @@ -1,19 +0,0 @@ -%def fcmp(wide="", r1="s1", r2="s2", cond="lt"): - /* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - */ - /* op vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - and w2, w0, #255 // w2<- BB - lsr w3, w0, #8 // w3<- CC - GET_VREG$wide $r1, w2 - GET_VREG$wide $r2, w3 - fcmp $r1, $r2 - cset w0, ne - cneg w0, w0, $cond - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w4 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/field.S b/runtime/interpreter/mterp/arm64/field.S deleted file mode 100644 index 8a66992724..0000000000 --- a/runtime/interpreter/mterp/arm64/field.S +++ /dev/null @@ -1,15 +0,0 @@ -%def field(helper=""): - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern $helper - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl $helper - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/floating_point.S b/runtime/interpreter/mterp/arm64/floating_point.S new file mode 100644 index 0000000000..04ca6949ff --- /dev/null +++ b/runtime/interpreter/mterp/arm64/floating_point.S @@ -0,0 +1,269 @@ +%def fbinop(instr=""): + /*: + * Generic 32-bit floating-point operation. + * + * For: add-float, sub-float, mul-float, div-float + * form: s0, s0, s1 + */ + /* floatop vAA, vBB, vCC */ + FETCH w0, 1 // r0<- CCBB + lsr w1, w0, #8 // r2<- CC + and w0, w0, #255 // r1<- BB + GET_VREG s1, w1 + GET_VREG s0, w0 + $instr // s0<- op + lsr w1, wINST, #8 // r1<- AA + FETCH_ADVANCE_INST 2 // advance rPC, load rINST + GET_INST_OPCODE ip // extract opcode from rINST + SET_VREG s0, w1 + GOTO_OPCODE ip // jump to next instruction + +%def fbinop2addr(instr=""): + /* + * Generic 32-bit floating point "/2addr" binary operation. Provide + * an "instr" line that specifies an instruction that performs + * "s2 = s0 op s1". + * + * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr + */ + /* binop/2addr vA, vB */ + lsr w3, wINST, #12 // w3<- B + ubfx w9, wINST, #8, #4 // w9<- A + GET_VREG s1, w3 + GET_VREG s0, w9 + $instr // s2<- op + FETCH_ADVANCE_INST 1 // advance rPC, load rINST + GET_INST_OPCODE ip // extract opcode from rINST + SET_VREG s2, w9 + GOTO_OPCODE ip // jump to next instruction + +%def fcmp(wide="", r1="s1", r2="s2", cond="lt"): + /* + * Compare two floating-point values. Puts 0, 1, or -1 into the + * destination register based on the results of the comparison. + */ + /* op vAA, vBB, vCC */ + FETCH w0, 1 // w0<- CCBB + lsr w4, wINST, #8 // w4<- AA + and w2, w0, #255 // w2<- BB + lsr w3, w0, #8 // w3<- CC + GET_VREG$wide $r1, w2 + GET_VREG$wide $r2, w3 + fcmp $r1, $r2 + cset w0, ne + cneg w0, w0, $cond + FETCH_ADVANCE_INST 2 // advance rPC, load rINST + GET_INST_OPCODE ip // extract opcode from rINST + SET_VREG w0, w4 // vAA<- w0 + GOTO_OPCODE ip // jump to next instruction + +%def funopNarrow(srcreg="s0", tgtreg="d0", instr=""): + /* + * Generic 32bit-to-32bit floating point unary operation. Provide an + * "instr" line that specifies an instruction that performs "$tgtreg = op $srcreg". + * + * For: int-to-float, float-to-int + * TODO: refactor all of the conversions - parameterize width and use same template. + */ + /* unop vA, vB */ + lsr w3, wINST, #12 // w3<- B + ubfx w4, wINST, #8, #4 // w4<- A + GET_VREG $srcreg, w3 + FETCH_ADVANCE_INST 1 // advance rPC, load wINST + $instr // d0<- op + GET_INST_OPCODE ip // extract opcode from wINST + SET_VREG $tgtreg, w4 // vA<- d0 + GOTO_OPCODE ip // jump to next instruction + +%def funopNarrower(srcreg="s0", tgtreg="d0", instr=""): + /* + * Generic 64bit-to-32bit floating point unary operation. Provide an + * "instr" line that specifies an instruction that performs "$tgtreg = op $srcreg". + * + * For: int-to-double, float-to-double, float-to-long + */ + /* unop vA, vB */ + lsr w3, wINST, #12 // w3<- B + ubfx w4, wINST, #8, #4 // w4<- A + GET_VREG_WIDE $srcreg, w3 + FETCH_ADVANCE_INST 1 // advance rPC, load wINST + $instr // d0<- op + GET_INST_OPCODE ip // extract opcode from wINST + SET_VREG $tgtreg, w4 // vA<- d0 + GOTO_OPCODE ip // jump to next instruction + +%def funopWide(srcreg="s0", tgtreg="d0", instr=""): + /* + * Generic 64bit-to-64bit floating point unary operation. Provide an + * "instr" line that specifies an instruction that performs "$tgtreg = op $srcreg". + * + * For: long-to-double, double-to-long + */ + /* unop vA, vB */ + lsr w3, wINST, #12 // w3<- B + ubfx w4, wINST, #8, #4 // w4<- A + GET_VREG_WIDE $srcreg, w3 + FETCH_ADVANCE_INST 1 // advance rPC, load wINST + $instr // d0<- op + GET_INST_OPCODE ip // extract opcode from wINST + SET_VREG_WIDE $tgtreg, w4 // vA<- d0 + GOTO_OPCODE ip // jump to next instruction + +%def funopWider(srcreg="s0", tgtreg="d0", instr=""): + /* + * Generic 32bit-to-64bit floating point unary operation. Provide an + * "instr" line that specifies an instruction that performs "$tgtreg = op $srcreg". + * + * For: int-to-double, float-to-double, float-to-long + */ + /* unop vA, vB */ + lsr w3, wINST, #12 // w3<- B + ubfx w4, wINST, #8, #4 // w4<- A + GET_VREG $srcreg, w3 + FETCH_ADVANCE_INST 1 // advance rPC, load wINST + $instr // d0<- op + GET_INST_OPCODE ip // extract opcode from wINST + SET_VREG_WIDE $tgtreg, w4 // vA<- d0 + GOTO_OPCODE ip // jump to next instruction + +%def op_add_double(): +% binopWide(instr="fadd d0, d1, d2", result="d0", r1="d1", r2="d2") + +%def op_add_double_2addr(): +% binopWide2addr(instr="fadd d0, d0, d1", r0="d0", r1="d1") + +%def op_add_float(): +% fbinop(instr="fadd s0, s0, s1") + +%def op_add_float_2addr(): +% fbinop2addr(instr="fadd s2, s0, s1") + +%def op_cmpg_double(): +% fcmp(wide="_WIDE", r1="d1", r2="d2", cond="cc") + +%def op_cmpg_float(): +% fcmp(wide="", r1="s1", r2="s2", cond="cc") + +%def op_cmpl_double(): +% fcmp(wide="_WIDE", r1="d1", r2="d2", cond="lt") + +%def op_cmpl_float(): +% fcmp(wide="", r1="s1", r2="s2", cond="lt") + +%def op_div_double(): +% binopWide(instr="fdiv d0, d1, d2", result="d0", r1="d1", r2="d2") + +%def op_div_double_2addr(): +% binopWide2addr(instr="fdiv d0, d0, d1", r0="d0", r1="d1") + +%def op_div_float(): +% fbinop(instr="fdiv s0, s0, s1") + +%def op_div_float_2addr(): +% fbinop2addr(instr="fdiv s2, s0, s1") + +%def op_double_to_float(): +% funopNarrower(instr="fcvt s0, d0", srcreg="d0", tgtreg="s0") + +%def op_double_to_int(): +% funopNarrower(instr="fcvtzs w0, d0", srcreg="d0", tgtreg="w0") + +%def op_double_to_long(): +% funopWide(instr="fcvtzs x0, d0", srcreg="d0", tgtreg="x0") + +%def op_float_to_double(): +% funopWider(instr="fcvt d0, s0", srcreg="s0", tgtreg="d0") + +%def op_float_to_int(): +% funopNarrow(instr="fcvtzs w0, s0", srcreg="s0", tgtreg="w0") + +%def op_float_to_long(): +% funopWider(instr="fcvtzs x0, s0", srcreg="s0", tgtreg="x0") + +%def op_int_to_double(): +% funopWider(instr="scvtf d0, w0", srcreg="w0", tgtreg="d0") + +%def op_int_to_float(): +% funopNarrow(instr="scvtf s0, w0", srcreg="w0", tgtreg="s0") + +%def op_long_to_double(): +% funopWide(instr="scvtf d0, x0", srcreg="x0", tgtreg="d0") + +%def op_long_to_float(): +% funopNarrower(instr="scvtf s0, x0", srcreg="x0", tgtreg="s0") + +%def op_mul_double(): +% binopWide(instr="fmul d0, d1, d2", result="d0", r1="d1", r2="d2") + +%def op_mul_double_2addr(): +% binopWide2addr(instr="fmul d0, d0, d1", r0="d0", r1="d1") + +%def op_mul_float(): +% fbinop(instr="fmul s0, s0, s1") + +%def op_mul_float_2addr(): +% fbinop2addr(instr="fmul s2, s0, s1") + +%def op_neg_double(): +% unopWide(instr="eor x0, x0, #0x8000000000000000") + +%def op_neg_float(): +% unop(instr="eor w0, w0, #0x80000000") + +%def op_rem_double(): + /* rem vAA, vBB, vCC */ + FETCH w0, 1 // w0<- CCBB + lsr w2, w0, #8 // w2<- CC + and w1, w0, #255 // w1<- BB + GET_VREG_WIDE d1, w2 // d1<- vCC + GET_VREG_WIDE d0, w1 // d0<- vBB + bl fmod + lsr w4, wINST, #8 // w4<- AA + FETCH_ADVANCE_INST 2 // advance rPC, load rINST + GET_INST_OPCODE ip // extract opcode from rINST + SET_VREG_WIDE d0, w4 // vAA<- result + GOTO_OPCODE ip // jump to next instruction + /* 11-14 instructions */ + +%def op_rem_double_2addr(): + /* rem vA, vB */ + lsr w1, wINST, #12 // w1<- B + ubfx w2, wINST, #8, #4 // w2<- A + GET_VREG_WIDE d1, w1 // d1<- vB + GET_VREG_WIDE d0, w2 // d0<- vA + bl fmod + ubfx w2, wINST, #8, #4 // w2<- A (need to reload - killed across call) + FETCH_ADVANCE_INST 1 // advance rPC, load rINST + GET_INST_OPCODE ip // extract opcode from rINST + SET_VREG_WIDE d0, w2 // vAA<- result + GOTO_OPCODE ip // jump to next instruction + /* 10-13 instructions */ + +%def op_rem_float(): +/* EABI doesn't define a float remainder function, but libm does */ +% fbinop(instr="bl fmodf") + +%def op_rem_float_2addr(): + /* rem vA, vB */ + lsr w3, wINST, #12 // w3<- B + ubfx w9, wINST, #8, #4 // w9<- A + GET_VREG s1, w3 + GET_VREG s0, w9 + bl fmodf + ubfx w9, wINST, #8, #4 // w9<- A + FETCH_ADVANCE_INST 1 // advance rPC, load rINST + GET_INST_OPCODE ip // extract opcode from rINST + SET_VREG s0, w9 + GOTO_OPCODE ip // jump to next instruction + +%def op_sub_double(): +% binopWide(instr="fsub d0, d1, d2", result="d0", r1="d1", r2="d2") + +%def op_sub_double_2addr(): +% binopWide2addr(instr="fsub d0, d0, d1", r0="d0", r1="d1") + +%def op_sub_float(): +% fbinop(instr="fsub s0, s0, s1") + +%def op_sub_float_2addr(): +% fbinop2addr(instr="fsub s2, s0, s1") diff --git a/runtime/interpreter/mterp/arm64/footer.S b/runtime/interpreter/mterp/arm64/footer.S deleted file mode 100644 index ba17f5e897..0000000000 --- a/runtime/interpreter/mterp/arm64/footer.S +++ /dev/null @@ -1,305 +0,0 @@ -%def footer(): -/* - * =========================================================================== - * Common subroutines and data - * =========================================================================== - */ - -/* - * We've detected a condition that will result in an exception, but the exception - * has not yet been thrown. Just bail out to the reference interpreter to deal with it. - * TUNING: for consistency, we may want to just go ahead and handle these here. - */ -common_errDivideByZero: - EXPORT_PC -#if MTERP_LOGGING - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - bl MterpLogDivideByZeroException -#endif - b MterpCommonFallback - -common_errArrayIndex: - EXPORT_PC -#if MTERP_LOGGING - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - bl MterpLogArrayIndexException -#endif - b MterpCommonFallback - -common_errNegativeArraySize: - EXPORT_PC -#if MTERP_LOGGING - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - bl MterpLogNegativeArraySizeException -#endif - b MterpCommonFallback - -common_errNoSuchMethod: - EXPORT_PC -#if MTERP_LOGGING - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - bl MterpLogNoSuchMethodException -#endif - b MterpCommonFallback - -common_errNullObject: - EXPORT_PC -#if MTERP_LOGGING - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - bl MterpLogNullObjectException -#endif - b MterpCommonFallback - -common_exceptionThrown: - EXPORT_PC -#if MTERP_LOGGING - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - bl MterpLogExceptionThrownException -#endif - b MterpCommonFallback - -MterpSuspendFallback: - EXPORT_PC -#if MTERP_LOGGING - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - ldr x2, [xSELF, #THREAD_FLAGS_OFFSET] - bl MterpLogSuspendFallback -#endif - b MterpCommonFallback - -/* - * If we're here, something is out of the ordinary. If there is a pending - * exception, handle it. Otherwise, roll back and retry with the reference - * interpreter. - */ -MterpPossibleException: - ldr x0, [xSELF, #THREAD_EXCEPTION_OFFSET] - cbz x0, MterpFallback // If not, fall back to reference interpreter. - /* intentional fallthrough - handle pending exception. */ -/* - * On return from a runtime helper routine, we've found a pending exception. - * Can we handle it here - or need to bail out to caller? - * - */ -MterpException: - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - bl MterpHandleException // (self, shadow_frame) - cbz w0, MterpExceptionReturn // no local catch, back to caller. - ldr x0, [xFP, #OFF_FP_DEX_INSTRUCTIONS] - ldr w1, [xFP, #OFF_FP_DEX_PC] - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] - add xPC, x0, x1, lsl #1 // generate new dex_pc_ptr - /* Do we need to switch interpreters? */ - bl MterpShouldSwitchInterpreters - cbnz w0, MterpFallback - /* resume execution at catch block */ - EXPORT_PC - FETCH_INST - GET_INST_OPCODE ip - GOTO_OPCODE ip - /* NOTE: no fallthrough */ -/* - * Common handling for branches with support for Jit profiling. - * On entry: - * wINST <= signed offset - * wPROFILE <= signed hotness countdown (expanded to 32 bits) - * condition bits <= set to establish sign of offset (use "NoFlags" entry if not) - * - * We have quite a few different cases for branch profiling, OSR detection and - * suspend check support here. - * - * Taken backward branches: - * If profiling active, do hotness countdown and report if we hit zero. - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * Is there a pending suspend request? If so, suspend. - * - * Taken forward branches and not-taken backward branches: - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * - * Our most common case is expected to be a taken backward branch with active jit profiling, - * but no full OSR check and no pending suspend request. - * Next most common case is not-taken branch with no full OSR check. - * - */ -MterpCommonTakenBranchNoFlags: - cmp wINST, #0 - b.gt .L_forward_branch // don't add forward branches to hotness - tbnz wPROFILE, #31, .L_no_count_backwards // go if negative - subs wPROFILE, wPROFILE, #1 // countdown - b.eq .L_add_batch // counted down to zero - report -.L_resume_backward_branch: - ldr lr, [xSELF, #THREAD_FLAGS_OFFSET] - add w2, wINST, wINST // w2<- byte offset - FETCH_ADVANCE_INST_RB w2 // update rPC, load wINST - REFRESH_IBASE - ands lr, lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - b.ne .L_suspend_request_pending - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - -.L_suspend_request_pending: - EXPORT_PC - mov x0, xSELF - bl MterpSuspendCheck // (self) - cbnz x0, MterpFallback - REFRESH_IBASE // might have changed during suspend - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - -.L_no_count_backwards: - cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? - b.ne .L_resume_backward_branch - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xINST - EXPORT_PC - bl MterpMaybeDoOnStackReplacement // (self, shadow_frame, offset) - cbnz x0, MterpOnStackReplacement - b .L_resume_backward_branch - -.L_forward_branch: - cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? - b.eq .L_check_osr_forward -.L_resume_forward_branch: - add w2, wINST, wINST // w2<- byte offset - FETCH_ADVANCE_INST_RB w2 // update rPC, load wINST - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - -.L_check_osr_forward: - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xINST - EXPORT_PC - bl MterpMaybeDoOnStackReplacement // (self, shadow_frame, offset) - cbnz x0, MterpOnStackReplacement - b .L_resume_forward_branch - -.L_add_batch: - add x1, xFP, #OFF_FP_SHADOWFRAME - strh wPROFILE, [x1, #SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET] - ldr x0, [xFP, #OFF_FP_METHOD] - mov x2, xSELF - bl MterpAddHotnessBatch // (method, shadow_frame, self) - mov wPROFILE, w0 // restore new hotness countdown to wPROFILE - b .L_no_count_backwards - -/* - * Entered from the conditional branch handlers when OSR check request active on - * not-taken path. All Dalvik not-taken conditional branch offsets are 2. - */ -.L_check_not_taken_osr: - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, #2 - EXPORT_PC - bl MterpMaybeDoOnStackReplacement // (self, shadow_frame, offset) - cbnz x0, MterpOnStackReplacement - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - -/* - * Check for suspend check request. Assumes wINST already loaded, xPC advanced and - * still needs to get the opcode and branch to it, and flags are in lr. - */ -MterpCheckSuspendAndContinue: - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh xIBASE - ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - b.ne check1 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction -check1: - EXPORT_PC - mov x0, xSELF - bl MterpSuspendCheck // (self) - cbnz x0, MterpFallback // Something in the environment changed, switch interpreters - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - -/* - * On-stack replacement has happened, and now we've returned from the compiled method. - */ -MterpOnStackReplacement: -#if MTERP_LOGGING - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - sxtw x2, wINST - bl MterpLogOSR -#endif - mov x0, #1 // Signal normal return - b MterpDone - -/* - * Bail out to reference interpreter. - */ -MterpFallback: - EXPORT_PC -#if MTERP_LOGGING - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - bl MterpLogFallback -#endif -MterpCommonFallback: - mov x0, #0 // signal retry with reference interpreter. - b MterpDone - -/* - * We pushed some registers on the stack in ExecuteMterpImpl, then saved - * SP and LR. Here we restore SP, restore the registers, and then restore - * LR to PC. - * - * On entry: - * uint32_t* xFP (should still be live, pointer to base of vregs) - */ -MterpExceptionReturn: - mov x0, #1 // signal return to caller. - b MterpDone -MterpReturn: - ldr x2, [xFP, #OFF_FP_RESULT_REGISTER] - str x0, [x2] - mov x0, #1 // signal return to caller. -MterpDone: -/* - * At this point, we expect wPROFILE to be non-zero. If negative, hotness is disabled or we're - * checking for OSR. If greater than zero, we might have unreported hotness to register - * (the difference between the ending wPROFILE and the cached hotness counter). wPROFILE - * should only reach zero immediately after a hotness decrement, and is then reset to either - * a negative special state or the new non-zero countdown value. - */ - cmp wPROFILE, #0 - bgt MterpProfileActive // if > 0, we may have some counts to report. - .cfi_remember_state - RESTORE_TWO_REGS fp, lr, 64 - RESTORE_TWO_REGS xPC, xFP, 48 - RESTORE_TWO_REGS xSELF, xINST, 32 - RESTORE_TWO_REGS xIBASE, xREFS, 16 - RESTORE_TWO_REGS_DECREASE_FRAME xPROFILE, x27, 80 - ret - .cfi_restore_state // Reset unwind info so following code unwinds. - .cfi_def_cfa_offset 80 // workaround for clang bug: 31975598 - -MterpProfileActive: - mov xINST, x0 // stash return value - /* Report cached hotness counts */ - ldr x0, [xFP, #OFF_FP_METHOD] - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xSELF - strh wPROFILE, [x1, #SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET] - bl MterpAddHotnessBatch // (method, shadow_frame, self) - mov x0, xINST // restore return value - RESTORE_TWO_REGS fp, lr, 64 - RESTORE_TWO_REGS xPC, xFP, 48 - RESTORE_TWO_REGS xSELF, xINST, 32 - RESTORE_TWO_REGS xIBASE, xREFS, 16 - RESTORE_TWO_REGS_DECREASE_FRAME xPROFILE, x27, 80 - ret - diff --git a/runtime/interpreter/mterp/arm64/funopNarrow.S b/runtime/interpreter/mterp/arm64/funopNarrow.S deleted file mode 100644 index f08e87fb3c..0000000000 --- a/runtime/interpreter/mterp/arm64/funopNarrow.S +++ /dev/null @@ -1,17 +0,0 @@ -%def funopNarrow(srcreg="s0", tgtreg="d0", instr=""): - /* - * Generic 32bit-to-32bit floating point unary operation. Provide an - * "instr" line that specifies an instruction that performs "$tgtreg = op $srcreg". - * - * For: int-to-float, float-to-int - * TODO: refactor all of the conversions - parameterize width and use same template. - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w4, wINST, #8, #4 // w4<- A - GET_VREG $srcreg, w3 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - $instr // d0<- op - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG $tgtreg, w4 // vA<- d0 - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/funopNarrower.S b/runtime/interpreter/mterp/arm64/funopNarrower.S deleted file mode 100644 index e1a1214f11..0000000000 --- a/runtime/interpreter/mterp/arm64/funopNarrower.S +++ /dev/null @@ -1,16 +0,0 @@ -%def funopNarrower(srcreg="s0", tgtreg="d0", instr=""): - /* - * Generic 64bit-to-32bit floating point unary operation. Provide an - * "instr" line that specifies an instruction that performs "$tgtreg = op $srcreg". - * - * For: int-to-double, float-to-double, float-to-long - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w4, wINST, #8, #4 // w4<- A - GET_VREG_WIDE $srcreg, w3 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - $instr // d0<- op - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG $tgtreg, w4 // vA<- d0 - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/funopWide.S b/runtime/interpreter/mterp/arm64/funopWide.S deleted file mode 100644 index 83e55be206..0000000000 --- a/runtime/interpreter/mterp/arm64/funopWide.S +++ /dev/null @@ -1,16 +0,0 @@ -%def funopWide(srcreg="s0", tgtreg="d0", instr=""): - /* - * Generic 64bit-to-64bit floating point unary operation. Provide an - * "instr" line that specifies an instruction that performs "$tgtreg = op $srcreg". - * - * For: long-to-double, double-to-long - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w4, wINST, #8, #4 // w4<- A - GET_VREG_WIDE $srcreg, w3 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - $instr // d0<- op - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG_WIDE $tgtreg, w4 // vA<- d0 - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/funopWider.S b/runtime/interpreter/mterp/arm64/funopWider.S deleted file mode 100644 index 825698ebf7..0000000000 --- a/runtime/interpreter/mterp/arm64/funopWider.S +++ /dev/null @@ -1,16 +0,0 @@ -%def funopWider(srcreg="s0", tgtreg="d0", instr=""): - /* - * Generic 32bit-to-64bit floating point unary operation. Provide an - * "instr" line that specifies an instruction that performs "$tgtreg = op $srcreg". - * - * For: int-to-double, float-to-double, float-to-long - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w4, wINST, #8, #4 // w4<- A - GET_VREG $srcreg, w3 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - $instr // d0<- op - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG_WIDE $tgtreg, w4 // vA<- d0 - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/header.S b/runtime/interpreter/mterp/arm64/header.S deleted file mode 100644 index 41029729ca..0000000000 --- a/runtime/interpreter/mterp/arm64/header.S +++ /dev/null @@ -1,354 +0,0 @@ -%def header(): -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - Art assembly interpreter notes: - - First validate assembly code by implementing ExecuteXXXImpl() style body (doesn't - handle invoke, allows higher-level code to create frame & shadow frame. - - Once that's working, support direct entry code & eliminate shadow frame (and - excess locals allocation. - - Some (hopefully) temporary ugliness. We'll treat xFP as pointing to the - base of the vreg array within the shadow frame. Access the other fields, - dex_pc_, method_ and number_of_vregs_ via negative offsets. For now, we'll continue - the shadow frame mechanism of double-storing object references - via xFP & - number_of_vregs_. - - */ - -/* -ARM64 Runtime register usage conventions. - - r0 : w0 is 32-bit return register and x0 is 64-bit. - r0-r7 : Argument registers. - r8-r15 : Caller save registers (used as temporary registers). - r16-r17: Also known as ip0-ip1, respectively. Used as scratch registers by - the linker, by the trampolines and other stubs (the backend uses - these as temporary registers). - r18 : Caller save register (used as temporary register). - r19 : Pointer to thread-local storage. - r20-r29: Callee save registers. - r30 : (lr) is reserved (the link register). - rsp : (sp) is reserved (the stack pointer). - rzr : (zr) is reserved (the zero register). - - Floating-point registers - v0-v31 - - v0 : s0 is return register for singles (32-bit) and d0 for doubles (64-bit). - This is analogous to the C/C++ (hard-float) calling convention. - v0-v7 : Floating-point argument registers in both Dalvik and C/C++ conventions. - Also used as temporary and codegen scratch registers. - - v0-v7 and v16-v31 : trashed across C calls. - v8-v15 : bottom 64-bits preserved across C calls (d8-d15 are preserved). - - v16-v31: Used as codegen temp/scratch. - v8-v15 : Can be used for promotion. - - Must maintain 16-byte stack alignment. - -Mterp notes: - -The following registers have fixed assignments: - - reg nick purpose - x20 xPC interpreted program counter, used for fetching instructions - x21 xFP interpreted frame pointer, used for accessing locals and args - x22 xSELF self (Thread) pointer - x23 xINST first 16-bit code unit of current instruction - x24 xIBASE interpreted instruction base pointer, used for computed goto - x25 xREFS base of object references in shadow frame (ideally, we'll get rid of this later). - x26 wPROFILE jit profile hotness countdown - x16 ip scratch reg - x17 ip2 scratch reg (used by macros) - -Macros are provided for common operations. They MUST NOT alter unspecified registers or condition -codes. -*/ - -/* - * This is a #include, not a %include, because we want the C pre-processor - * to expand the macros into assembler assignment statements. - */ -#include "asm_support.h" -#include "interpreter/cfi_asm_support.h" - -#define MTERP_PROFILE_BRANCHES 1 -#define MTERP_LOGGING 0 - -/* During bringup, we'll use the shadow frame model instead of xFP */ -/* single-purpose registers, given names for clarity */ -#define xPC x20 -#define CFI_DEX 20 // DWARF register number of the register holding dex-pc (xPC). -#define CFI_TMP 0 // DWARF register number of the first argument register (r0). -#define xFP x21 -#define xSELF x22 -#define xINST x23 -#define wINST w23 -#define xIBASE x24 -#define xREFS x25 -#define wPROFILE w26 -#define xPROFILE x26 -#define ip x16 -#define ip2 x17 - -/* - * Instead of holding a pointer to the shadow frame, we keep xFP at the base of the vregs. So, - * to access other shadow frame fields, we need to use a backwards offset. Define those here. - */ -#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) -#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) -#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) -#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) -#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) -#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) -#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) -#define OFF_FP_DEX_INSTRUCTIONS OFF_FP(SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET) -#define OFF_FP_SHADOWFRAME OFF_FP(0) - -/* - * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must - * be done *before* something throws. - * - * It's okay to do this more than once. - * - * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped - * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction - * offset into the code_items_[] array. For effiency, we will "export" the - * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC - * to convert to a dex pc when needed. - */ -.macro EXPORT_PC - str xPC, [xFP, #OFF_FP_DEX_PC_PTR] -.endm - -/* - * Fetch the next instruction from xPC into wINST. Does not advance xPC. - */ -.macro FETCH_INST - ldrh wINST, [xPC] -.endm - -/* - * Fetch the next instruction from the specified offset. Advances xPC - * to point to the next instruction. "_count" is in 16-bit code units. - * - * Because of the limited size of immediate constants on ARM, this is only - * suitable for small forward movements (i.e. don't try to implement "goto" - * with this). - * - * This must come AFTER anything that can throw an exception, or the - * exception catch may miss. (This also implies that it must come after - * EXPORT_PC.) - */ -.macro FETCH_ADVANCE_INST count - ldrh wINST, [xPC, #((\count)*2)]! -.endm - -/* - * The operation performed here is similar to FETCH_ADVANCE_INST, except the - * src and dest registers are parameterized (not hard-wired to xPC and xINST). - */ -.macro PREFETCH_ADVANCE_INST dreg, sreg, count - ldrh \dreg, [\sreg, #((\count)*2)]! -.endm - -/* - * Similar to FETCH_ADVANCE_INST, but does not update xPC. Used to load - * xINST ahead of possible exception point. Be sure to manually advance xPC - * later. - */ -.macro PREFETCH_INST count - ldrh wINST, [xPC, #((\count)*2)] -.endm - -/* Advance xPC by some number of code units. */ -.macro ADVANCE count - add xPC, xPC, #((\count)*2) -.endm - -/* - * Fetch the next instruction from an offset specified by _reg and advance xPC. - * xPC to point to the next instruction. "_reg" must specify the distance - * in bytes, *not* 16-bit code units, and may be a signed value. Must not set flags. - * - */ -.macro FETCH_ADVANCE_INST_RB reg - add xPC, xPC, \reg, sxtw - ldrh wINST, [xPC] -.endm - -/* - * Fetch a half-word code unit from an offset past the current PC. The - * "_count" value is in 16-bit code units. Does not advance xPC. - * - * The "_S" variant works the same but treats the value as signed. - */ -.macro FETCH reg, count - ldrh \reg, [xPC, #((\count)*2)] -.endm - -.macro FETCH_S reg, count - ldrsh \reg, [xPC, #((\count)*2)] -.endm - -/* - * Fetch one byte from an offset past the current PC. Pass in the same - * "_count" as you would for FETCH, and an additional 0/1 indicating which - * byte of the halfword you want (lo/hi). - */ -.macro FETCH_B reg, count, byte - ldrb \reg, [xPC, #((\count)*2+(\byte))] -.endm - -/* - * Put the instruction's opcode field into the specified register. - */ -.macro GET_INST_OPCODE reg - and \reg, xINST, #255 -.endm - -/* - * Put the prefetched instruction's opcode field into the specified register. - */ -.macro GET_PREFETCHED_OPCODE oreg, ireg - and \oreg, \ireg, #255 -.endm - -/* - * Begin executing the opcode in _reg. Clobbers reg - */ - -.macro GOTO_OPCODE reg - add \reg, xIBASE, \reg, lsl #${handler_size_bits} - br \reg -.endm -.macro GOTO_OPCODE_BASE base,reg - add \reg, \base, \reg, lsl #${handler_size_bits} - br \reg -.endm - -/* - * Get/set the 32-bit value from a Dalvik register. - */ -.macro GET_VREG reg, vreg - ldr \reg, [xFP, \vreg, uxtw #2] -.endm -.macro SET_VREG reg, vreg - str \reg, [xFP, \vreg, uxtw #2] - str wzr, [xREFS, \vreg, uxtw #2] -.endm -.macro SET_VREG_OBJECT reg, vreg, tmpreg - str \reg, [xFP, \vreg, uxtw #2] - str \reg, [xREFS, \vreg, uxtw #2] -.endm - -/* - * Get/set the 64-bit value from a Dalvik register. - * TUNING: can we do better here? - */ -.macro GET_VREG_WIDE reg, vreg - add ip2, xFP, \vreg, lsl #2 - ldr \reg, [ip2] -.endm -.macro SET_VREG_WIDE reg, vreg - add ip2, xFP, \vreg, lsl #2 - str \reg, [ip2] - add ip2, xREFS, \vreg, lsl #2 - str xzr, [ip2] -.endm - -/* - * Get the 32-bit value from a Dalvik register and sign-extend to 64-bit. - * Used to avoid an extra instruction in int-to-long. - */ -.macro GET_VREG_S reg, vreg - ldrsw \reg, [xFP, \vreg, uxtw #2] -.endm - -/* - * Convert a virtual register index into an address. - */ -.macro VREG_INDEX_TO_ADDR reg, vreg - add \reg, xFP, \vreg, lsl #2 /* WARNING: handle shadow frame vreg zero if store */ -.endm - -/* - * Refresh handler table. - */ -.macro REFRESH_IBASE - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] -.endm - -/* - * Save two registers to the stack. - */ -.macro SAVE_TWO_REGS reg1, reg2, offset - stp \reg1, \reg2, [sp, #(\offset)] - .cfi_rel_offset \reg1, (\offset) - .cfi_rel_offset \reg2, (\offset) + 8 -.endm - -/* - * Restore two registers from the stack. - */ -.macro RESTORE_TWO_REGS reg1, reg2, offset - ldp \reg1, \reg2, [sp, #(\offset)] - .cfi_restore \reg1 - .cfi_restore \reg2 -.endm - -/* - * Increase frame size and save two registers to the bottom of the stack. - */ -.macro SAVE_TWO_REGS_INCREASE_FRAME reg1, reg2, frame_adjustment - stp \reg1, \reg2, [sp, #-(\frame_adjustment)]! - .cfi_adjust_cfa_offset (\frame_adjustment) - .cfi_rel_offset \reg1, 0 - .cfi_rel_offset \reg2, 8 -.endm - -/* - * Restore two registers from the bottom of the stack and decrease frame size. - */ -.macro RESTORE_TWO_REGS_DECREASE_FRAME reg1, reg2, frame_adjustment - ldp \reg1, \reg2, [sp], #(\frame_adjustment) - .cfi_restore \reg1 - .cfi_restore \reg2 - .cfi_adjust_cfa_offset -(\frame_adjustment) -.endm - -/* - * cfi support macros. - */ -.macro ENTRY name - .type \name, #function - .hidden \name // Hide this as a global symbol, so we do not incur plt calls. - .global \name - /* Cache alignment for function entry */ - .balign 16 -\name: - .cfi_startproc -.endm - -.macro END name - .cfi_endproc - .size \name, .-\name -.endm diff --git a/runtime/interpreter/mterp/arm64/instruction_end.S b/runtime/interpreter/mterp/arm64/instruction_end.S deleted file mode 100644 index cf30a9b0b0..0000000000 --- a/runtime/interpreter/mterp/arm64/instruction_end.S +++ /dev/null @@ -1,6 +0,0 @@ -%def instruction_end(): - - .type artMterpAsmInstructionEnd, #object - .hidden artMterpAsmInstructionEnd - .global artMterpAsmInstructionEnd -artMterpAsmInstructionEnd: diff --git a/runtime/interpreter/mterp/arm64/instruction_end_alt.S b/runtime/interpreter/mterp/arm64/instruction_end_alt.S deleted file mode 100644 index 9509a63b6a..0000000000 --- a/runtime/interpreter/mterp/arm64/instruction_end_alt.S +++ /dev/null @@ -1,6 +0,0 @@ -%def instruction_end_alt(): - - .type artMterpAsmAltInstructionEnd, #object - .hidden artMterpAsmAltInstructionEnd - .global artMterpAsmAltInstructionEnd -artMterpAsmAltInstructionEnd: diff --git a/runtime/interpreter/mterp/arm64/instruction_end_sister.S b/runtime/interpreter/mterp/arm64/instruction_end_sister.S deleted file mode 100644 index 18f1dbb38d..0000000000 --- a/runtime/interpreter/mterp/arm64/instruction_end_sister.S +++ /dev/null @@ -1,6 +0,0 @@ -%def instruction_end_sister(): - - .type artMterpAsmSisterEnd, #object - .hidden artMterpAsmSisterEnd - .global artMterpAsmSisterEnd -artMterpAsmSisterEnd: diff --git a/runtime/interpreter/mterp/arm64/instruction_start.S b/runtime/interpreter/mterp/arm64/instruction_start.S deleted file mode 100644 index 457dcf9617..0000000000 --- a/runtime/interpreter/mterp/arm64/instruction_start.S +++ /dev/null @@ -1,7 +0,0 @@ -%def instruction_start(): - - .type artMterpAsmInstructionStart, #object - .hidden artMterpAsmInstructionStart - .global artMterpAsmInstructionStart -artMterpAsmInstructionStart = .L_op_nop - .text diff --git a/runtime/interpreter/mterp/arm64/instruction_start_alt.S b/runtime/interpreter/mterp/arm64/instruction_start_alt.S deleted file mode 100644 index 40d2bf5dbe..0000000000 --- a/runtime/interpreter/mterp/arm64/instruction_start_alt.S +++ /dev/null @@ -1,7 +0,0 @@ -%def instruction_start_alt(): - - .type artMterpAsmAltInstructionStart, #object - .hidden artMterpAsmAltInstructionStart - .global artMterpAsmAltInstructionStart -artMterpAsmAltInstructionStart = .L_ALT_op_nop - .text diff --git a/runtime/interpreter/mterp/arm64/instruction_start_sister.S b/runtime/interpreter/mterp/arm64/instruction_start_sister.S deleted file mode 100644 index 2bf24636ea..0000000000 --- a/runtime/interpreter/mterp/arm64/instruction_start_sister.S +++ /dev/null @@ -1,8 +0,0 @@ -%def instruction_start_sister(): - - .type artMterpAsmSisterStart, #object - .hidden artMterpAsmSisterStart - .global artMterpAsmSisterStart - .text - .balign 4 -artMterpAsmSisterStart: diff --git a/runtime/interpreter/mterp/arm64/invoke.S b/runtime/interpreter/mterp/arm64/invoke.S index 9e5b5b725a..03ac316392 100644 --- a/runtime/interpreter/mterp/arm64/invoke.S +++ b/runtime/interpreter/mterp/arm64/invoke.S @@ -18,3 +18,93 @@ GET_INST_OPCODE ip GOTO_OPCODE ip + +%def invoke_polymorphic(helper="UndefinedInvokeHandler"): + /* + * invoke-polymorphic handler wrapper. + */ + /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ + /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ + .extern $helper + EXPORT_PC + mov x0, xSELF + add x1, xFP, #OFF_FP_SHADOWFRAME + mov x2, xPC + mov x3, xINST + bl $helper + cbz w0, MterpException + FETCH_ADVANCE_INST 4 + bl MterpShouldSwitchInterpreters + cbnz w0, MterpFallback + GET_INST_OPCODE ip + GOTO_OPCODE ip + +%def op_invoke_custom(): +% invoke(helper="MterpInvokeCustom") + +%def op_invoke_custom_range(): +% invoke(helper="MterpInvokeCustomRange") + +%def op_invoke_direct(): +% invoke(helper="MterpInvokeDirect") + +%def op_invoke_direct_range(): +% invoke(helper="MterpInvokeDirectRange") + +%def op_invoke_interface(): +% invoke(helper="MterpInvokeInterface") + /* + * Handle an interface method call. + * + * for: invoke-interface, invoke-interface/range + */ + /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ + /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ + +%def op_invoke_interface_range(): +% invoke(helper="MterpInvokeInterfaceRange") + +%def op_invoke_polymorphic(): +% invoke_polymorphic(helper="MterpInvokePolymorphic") + +%def op_invoke_polymorphic_range(): +% invoke_polymorphic(helper="MterpInvokePolymorphicRange") + +%def op_invoke_static(): +% invoke(helper="MterpInvokeStatic") + + +%def op_invoke_static_range(): +% invoke(helper="MterpInvokeStaticRange") + +%def op_invoke_super(): +% invoke(helper="MterpInvokeSuper") + /* + * Handle a "super" method call. + * + * for: invoke-super, invoke-super/range + */ + /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ + /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ + +%def op_invoke_super_range(): +% invoke(helper="MterpInvokeSuperRange") + +%def op_invoke_virtual(): +% invoke(helper="MterpInvokeVirtual") + /* + * Handle a virtual method call. + * + * for: invoke-virtual, invoke-virtual/range + */ + /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ + /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ + +%def op_invoke_virtual_quick(): +% invoke(helper="MterpInvokeVirtualQuick") + +%def op_invoke_virtual_range(): +% invoke(helper="MterpInvokeVirtualRange") + +%def op_invoke_virtual_range_quick(): +% invoke(helper="MterpInvokeVirtualQuickRange") diff --git a/runtime/interpreter/mterp/arm64/invoke_polymorphic.S b/runtime/interpreter/mterp/arm64/invoke_polymorphic.S deleted file mode 100644 index 08ffb9cae7..0000000000 --- a/runtime/interpreter/mterp/arm64/invoke_polymorphic.S +++ /dev/null @@ -1,19 +0,0 @@ -%def invoke_polymorphic(helper="UndefinedInvokeHandler"): - /* - * invoke-polymorphic handler wrapper. - */ - /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ - .extern $helper - EXPORT_PC - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - mov x3, xINST - bl $helper - cbz w0, MterpException - FETCH_ADVANCE_INST 4 - bl MterpShouldSwitchInterpreters - cbnz w0, MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip diff --git a/runtime/interpreter/mterp/arm64/main.S b/runtime/interpreter/mterp/arm64/main.S new file mode 100644 index 0000000000..37ed83d60f --- /dev/null +++ b/runtime/interpreter/mterp/arm64/main.S @@ -0,0 +1,799 @@ +%def header(): +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + Art assembly interpreter notes: + + First validate assembly code by implementing ExecuteXXXImpl() style body (doesn't + handle invoke, allows higher-level code to create frame & shadow frame. + + Once that's working, support direct entry code & eliminate shadow frame (and + excess locals allocation. + + Some (hopefully) temporary ugliness. We'll treat xFP as pointing to the + base of the vreg array within the shadow frame. Access the other fields, + dex_pc_, method_ and number_of_vregs_ via negative offsets. For now, we'll continue + the shadow frame mechanism of double-storing object references - via xFP & + number_of_vregs_. + + */ + +/* +ARM64 Runtime register usage conventions. + + r0 : w0 is 32-bit return register and x0 is 64-bit. + r0-r7 : Argument registers. + r8-r15 : Caller save registers (used as temporary registers). + r16-r17: Also known as ip0-ip1, respectively. Used as scratch registers by + the linker, by the trampolines and other stubs (the backend uses + these as temporary registers). + r18 : Caller save register (used as temporary register). + r19 : Pointer to thread-local storage. + r20-r29: Callee save registers. + r30 : (lr) is reserved (the link register). + rsp : (sp) is reserved (the stack pointer). + rzr : (zr) is reserved (the zero register). + + Floating-point registers + v0-v31 + + v0 : s0 is return register for singles (32-bit) and d0 for doubles (64-bit). + This is analogous to the C/C++ (hard-float) calling convention. + v0-v7 : Floating-point argument registers in both Dalvik and C/C++ conventions. + Also used as temporary and codegen scratch registers. + + v0-v7 and v16-v31 : trashed across C calls. + v8-v15 : bottom 64-bits preserved across C calls (d8-d15 are preserved). + + v16-v31: Used as codegen temp/scratch. + v8-v15 : Can be used for promotion. + + Must maintain 16-byte stack alignment. + +Mterp notes: + +The following registers have fixed assignments: + + reg nick purpose + x20 xPC interpreted program counter, used for fetching instructions + x21 xFP interpreted frame pointer, used for accessing locals and args + x22 xSELF self (Thread) pointer + x23 xINST first 16-bit code unit of current instruction + x24 xIBASE interpreted instruction base pointer, used for computed goto + x25 xREFS base of object references in shadow frame (ideally, we'll get rid of this later). + x26 wPROFILE jit profile hotness countdown + x16 ip scratch reg + x17 ip2 scratch reg (used by macros) + +Macros are provided for common operations. They MUST NOT alter unspecified registers or condition +codes. +*/ + +/* + * This is a #include, not a %include, because we want the C pre-processor + * to expand the macros into assembler assignment statements. + */ +#include "asm_support.h" +#include "interpreter/cfi_asm_support.h" + +#define MTERP_PROFILE_BRANCHES 1 +#define MTERP_LOGGING 0 + +/* During bringup, we'll use the shadow frame model instead of xFP */ +/* single-purpose registers, given names for clarity */ +#define xPC x20 +#define CFI_DEX 20 // DWARF register number of the register holding dex-pc (xPC). +#define CFI_TMP 0 // DWARF register number of the first argument register (r0). +#define xFP x21 +#define xSELF x22 +#define xINST x23 +#define wINST w23 +#define xIBASE x24 +#define xREFS x25 +#define wPROFILE w26 +#define xPROFILE x26 +#define ip x16 +#define ip2 x17 + +/* + * Instead of holding a pointer to the shadow frame, we keep xFP at the base of the vregs. So, + * to access other shadow frame fields, we need to use a backwards offset. Define those here. + */ +#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) +#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) +#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) +#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) +#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) +#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) +#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) +#define OFF_FP_DEX_INSTRUCTIONS OFF_FP(SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET) +#define OFF_FP_SHADOWFRAME OFF_FP(0) + +/* + * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must + * be done *before* something throws. + * + * It's okay to do this more than once. + * + * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped + * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction + * offset into the code_items_[] array. For effiency, we will "export" the + * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC + * to convert to a dex pc when needed. + */ +.macro EXPORT_PC + str xPC, [xFP, #OFF_FP_DEX_PC_PTR] +.endm + +/* + * Fetch the next instruction from xPC into wINST. Does not advance xPC. + */ +.macro FETCH_INST + ldrh wINST, [xPC] +.endm + +/* + * Fetch the next instruction from the specified offset. Advances xPC + * to point to the next instruction. "_count" is in 16-bit code units. + * + * Because of the limited size of immediate constants on ARM, this is only + * suitable for small forward movements (i.e. don't try to implement "goto" + * with this). + * + * This must come AFTER anything that can throw an exception, or the + * exception catch may miss. (This also implies that it must come after + * EXPORT_PC.) + */ +.macro FETCH_ADVANCE_INST count + ldrh wINST, [xPC, #((\count)*2)]! +.endm + +/* + * The operation performed here is similar to FETCH_ADVANCE_INST, except the + * src and dest registers are parameterized (not hard-wired to xPC and xINST). + */ +.macro PREFETCH_ADVANCE_INST dreg, sreg, count + ldrh \dreg, [\sreg, #((\count)*2)]! +.endm + +/* + * Similar to FETCH_ADVANCE_INST, but does not update xPC. Used to load + * xINST ahead of possible exception point. Be sure to manually advance xPC + * later. + */ +.macro PREFETCH_INST count + ldrh wINST, [xPC, #((\count)*2)] +.endm + +/* Advance xPC by some number of code units. */ +.macro ADVANCE count + add xPC, xPC, #((\count)*2) +.endm + +/* + * Fetch the next instruction from an offset specified by _reg and advance xPC. + * xPC to point to the next instruction. "_reg" must specify the distance + * in bytes, *not* 16-bit code units, and may be a signed value. Must not set flags. + * + */ +.macro FETCH_ADVANCE_INST_RB reg + add xPC, xPC, \reg, sxtw + ldrh wINST, [xPC] +.endm + +/* + * Fetch a half-word code unit from an offset past the current PC. The + * "_count" value is in 16-bit code units. Does not advance xPC. + * + * The "_S" variant works the same but treats the value as signed. + */ +.macro FETCH reg, count + ldrh \reg, [xPC, #((\count)*2)] +.endm + +.macro FETCH_S reg, count + ldrsh \reg, [xPC, #((\count)*2)] +.endm + +/* + * Fetch one byte from an offset past the current PC. Pass in the same + * "_count" as you would for FETCH, and an additional 0/1 indicating which + * byte of the halfword you want (lo/hi). + */ +.macro FETCH_B reg, count, byte + ldrb \reg, [xPC, #((\count)*2+(\byte))] +.endm + +/* + * Put the instruction's opcode field into the specified register. + */ +.macro GET_INST_OPCODE reg + and \reg, xINST, #255 +.endm + +/* + * Put the prefetched instruction's opcode field into the specified register. + */ +.macro GET_PREFETCHED_OPCODE oreg, ireg + and \oreg, \ireg, #255 +.endm + +/* + * Begin executing the opcode in _reg. Clobbers reg + */ + +.macro GOTO_OPCODE reg + add \reg, xIBASE, \reg, lsl #${handler_size_bits} + br \reg +.endm +.macro GOTO_OPCODE_BASE base,reg + add \reg, \base, \reg, lsl #${handler_size_bits} + br \reg +.endm + +/* + * Get/set the 32-bit value from a Dalvik register. + */ +.macro GET_VREG reg, vreg + ldr \reg, [xFP, \vreg, uxtw #2] +.endm +.macro SET_VREG reg, vreg + str \reg, [xFP, \vreg, uxtw #2] + str wzr, [xREFS, \vreg, uxtw #2] +.endm +.macro SET_VREG_OBJECT reg, vreg, tmpreg + str \reg, [xFP, \vreg, uxtw #2] + str \reg, [xREFS, \vreg, uxtw #2] +.endm + +/* + * Get/set the 64-bit value from a Dalvik register. + * TUNING: can we do better here? + */ +.macro GET_VREG_WIDE reg, vreg + add ip2, xFP, \vreg, lsl #2 + ldr \reg, [ip2] +.endm +.macro SET_VREG_WIDE reg, vreg + add ip2, xFP, \vreg, lsl #2 + str \reg, [ip2] + add ip2, xREFS, \vreg, lsl #2 + str xzr, [ip2] +.endm + +/* + * Get the 32-bit value from a Dalvik register and sign-extend to 64-bit. + * Used to avoid an extra instruction in int-to-long. + */ +.macro GET_VREG_S reg, vreg + ldrsw \reg, [xFP, \vreg, uxtw #2] +.endm + +/* + * Convert a virtual register index into an address. + */ +.macro VREG_INDEX_TO_ADDR reg, vreg + add \reg, xFP, \vreg, lsl #2 /* WARNING: handle shadow frame vreg zero if store */ +.endm + +/* + * Refresh handler table. + */ +.macro REFRESH_IBASE + ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] +.endm + +/* + * Save two registers to the stack. + */ +.macro SAVE_TWO_REGS reg1, reg2, offset + stp \reg1, \reg2, [sp, #(\offset)] + .cfi_rel_offset \reg1, (\offset) + .cfi_rel_offset \reg2, (\offset) + 8 +.endm + +/* + * Restore two registers from the stack. + */ +.macro RESTORE_TWO_REGS reg1, reg2, offset + ldp \reg1, \reg2, [sp, #(\offset)] + .cfi_restore \reg1 + .cfi_restore \reg2 +.endm + +/* + * Increase frame size and save two registers to the bottom of the stack. + */ +.macro SAVE_TWO_REGS_INCREASE_FRAME reg1, reg2, frame_adjustment + stp \reg1, \reg2, [sp, #-(\frame_adjustment)]! + .cfi_adjust_cfa_offset (\frame_adjustment) + .cfi_rel_offset \reg1, 0 + .cfi_rel_offset \reg2, 8 +.endm + +/* + * Restore two registers from the bottom of the stack and decrease frame size. + */ +.macro RESTORE_TWO_REGS_DECREASE_FRAME reg1, reg2, frame_adjustment + ldp \reg1, \reg2, [sp], #(\frame_adjustment) + .cfi_restore \reg1 + .cfi_restore \reg2 + .cfi_adjust_cfa_offset -(\frame_adjustment) +.endm + +/* + * cfi support macros. + */ +.macro ENTRY name + .type \name, #function + .hidden \name // Hide this as a global symbol, so we do not incur plt calls. + .global \name + /* Cache alignment for function entry */ + .balign 16 +\name: + .cfi_startproc +.endm + +.macro END name + .cfi_endproc + .size \name, .-\name +.endm + +%def entry(): +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + .text + +/* + * Interpreter entry point. + * On entry: + * x0 Thread* self/ + * x1 insns_ + * x2 ShadowFrame + * x3 JValue* result_register + * + */ +ENTRY ExecuteMterpImpl + SAVE_TWO_REGS_INCREASE_FRAME xPROFILE, x27, 80 + SAVE_TWO_REGS xIBASE, xREFS, 16 + SAVE_TWO_REGS xSELF, xINST, 32 + SAVE_TWO_REGS xPC, xFP, 48 + SAVE_TWO_REGS fp, lr, 64 + add fp, sp, #64 + + /* Remember the return register */ + str x3, [x2, #SHADOWFRAME_RESULT_REGISTER_OFFSET] + + /* Remember the dex instruction pointer */ + str x1, [x2, #SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET] + + /* set up "named" registers */ + mov xSELF, x0 + ldr w0, [x2, #SHADOWFRAME_NUMBER_OF_VREGS_OFFSET] + add xFP, x2, #SHADOWFRAME_VREGS_OFFSET // point to vregs. + add xREFS, xFP, w0, lsl #2 // point to reference array in shadow frame + ldr w0, [x2, #SHADOWFRAME_DEX_PC_OFFSET] // Get starting dex_pc. + add xPC, x1, w0, lsl #1 // Create direct pointer to 1st dex opcode + CFI_DEFINE_DEX_PC_WITH_OFFSET(CFI_TMP, CFI_DEX, 0) + EXPORT_PC + + /* Starting ibase */ + ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] + + /* Set up for backwards branches & osr profiling */ + ldr x0, [xFP, #OFF_FP_METHOD] + add x1, xFP, #OFF_FP_SHADOWFRAME + mov x2, xSELF + bl MterpSetUpHotnessCountdown + mov wPROFILE, w0 // Starting hotness countdown to xPROFILE + + /* start executing the instruction at rPC */ + FETCH_INST // load wINST from rPC + GET_INST_OPCODE ip // extract opcode from wINST + GOTO_OPCODE ip // jump to next instruction + /* NOTE: no fallthrough */ + +%def alt_stub(): +/* + * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle + * any interesting requests and then jump to the real instruction + * handler. Note that the call to MterpCheckBefore is done as a tail call. + */ + .extern MterpCheckBefore + ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. + adr lr, artMterpAsmInstructionStart + (${opnum} * 128) // Addr of primary handler. + mov x0, xSELF + add x1, xFP, #OFF_FP_SHADOWFRAME + mov x2, xPC + b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. + +%def close_cfi(): +// Close out the cfi info. We're treating mterp as a single function. + +END ExecuteMterpImpl + + +%def fallback(): +/* Transfer stub to alternate interpreter */ + b MterpFallback + + +%def footer(): +/* + * =========================================================================== + * Common subroutines and data + * =========================================================================== + */ + +/* + * We've detected a condition that will result in an exception, but the exception + * has not yet been thrown. Just bail out to the reference interpreter to deal with it. + * TUNING: for consistency, we may want to just go ahead and handle these here. + */ +common_errDivideByZero: + EXPORT_PC +#if MTERP_LOGGING + mov x0, xSELF + add x1, xFP, #OFF_FP_SHADOWFRAME + bl MterpLogDivideByZeroException +#endif + b MterpCommonFallback + +common_errArrayIndex: + EXPORT_PC +#if MTERP_LOGGING + mov x0, xSELF + add x1, xFP, #OFF_FP_SHADOWFRAME + bl MterpLogArrayIndexException +#endif + b MterpCommonFallback + +common_errNegativeArraySize: + EXPORT_PC +#if MTERP_LOGGING + mov x0, xSELF + add x1, xFP, #OFF_FP_SHADOWFRAME + bl MterpLogNegativeArraySizeException +#endif + b MterpCommonFallback + +common_errNoSuchMethod: + EXPORT_PC +#if MTERP_LOGGING + mov x0, xSELF + add x1, xFP, #OFF_FP_SHADOWFRAME + bl MterpLogNoSuchMethodException +#endif + b MterpCommonFallback + +common_errNullObject: + EXPORT_PC +#if MTERP_LOGGING + mov x0, xSELF + add x1, xFP, #OFF_FP_SHADOWFRAME + bl MterpLogNullObjectException +#endif + b MterpCommonFallback + +common_exceptionThrown: + EXPORT_PC +#if MTERP_LOGGING + mov x0, xSELF + add x1, xFP, #OFF_FP_SHADOWFRAME + bl MterpLogExceptionThrownException +#endif + b MterpCommonFallback + +MterpSuspendFallback: + EXPORT_PC +#if MTERP_LOGGING + mov x0, xSELF + add x1, xFP, #OFF_FP_SHADOWFRAME + ldr x2, [xSELF, #THREAD_FLAGS_OFFSET] + bl MterpLogSuspendFallback +#endif + b MterpCommonFallback + +/* + * If we're here, something is out of the ordinary. If there is a pending + * exception, handle it. Otherwise, roll back and retry with the reference + * interpreter. + */ +MterpPossibleException: + ldr x0, [xSELF, #THREAD_EXCEPTION_OFFSET] + cbz x0, MterpFallback // If not, fall back to reference interpreter. + /* intentional fallthrough - handle pending exception. */ +/* + * On return from a runtime helper routine, we've found a pending exception. + * Can we handle it here - or need to bail out to caller? + * + */ +MterpException: + mov x0, xSELF + add x1, xFP, #OFF_FP_SHADOWFRAME + bl MterpHandleException // (self, shadow_frame) + cbz w0, MterpExceptionReturn // no local catch, back to caller. + ldr x0, [xFP, #OFF_FP_DEX_INSTRUCTIONS] + ldr w1, [xFP, #OFF_FP_DEX_PC] + ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] + add xPC, x0, x1, lsl #1 // generate new dex_pc_ptr + /* Do we need to switch interpreters? */ + bl MterpShouldSwitchInterpreters + cbnz w0, MterpFallback + /* resume execution at catch block */ + EXPORT_PC + FETCH_INST + GET_INST_OPCODE ip + GOTO_OPCODE ip + /* NOTE: no fallthrough */ +/* + * Common handling for branches with support for Jit profiling. + * On entry: + * wINST <= signed offset + * wPROFILE <= signed hotness countdown (expanded to 32 bits) + * condition bits <= set to establish sign of offset (use "NoFlags" entry if not) + * + * We have quite a few different cases for branch profiling, OSR detection and + * suspend check support here. + * + * Taken backward branches: + * If profiling active, do hotness countdown and report if we hit zero. + * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. + * Is there a pending suspend request? If so, suspend. + * + * Taken forward branches and not-taken backward branches: + * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. + * + * Our most common case is expected to be a taken backward branch with active jit profiling, + * but no full OSR check and no pending suspend request. + * Next most common case is not-taken branch with no full OSR check. + * + */ +MterpCommonTakenBranchNoFlags: + cmp wINST, #0 + b.gt .L_forward_branch // don't add forward branches to hotness + tbnz wPROFILE, #31, .L_no_count_backwards // go if negative + subs wPROFILE, wPROFILE, #1 // countdown + b.eq .L_add_batch // counted down to zero - report +.L_resume_backward_branch: + ldr lr, [xSELF, #THREAD_FLAGS_OFFSET] + add w2, wINST, wINST // w2<- byte offset + FETCH_ADVANCE_INST_RB w2 // update rPC, load wINST + REFRESH_IBASE + ands lr, lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST + b.ne .L_suspend_request_pending + GET_INST_OPCODE ip // extract opcode from wINST + GOTO_OPCODE ip // jump to next instruction + +.L_suspend_request_pending: + EXPORT_PC + mov x0, xSELF + bl MterpSuspendCheck // (self) + cbnz x0, MterpFallback + REFRESH_IBASE // might have changed during suspend + GET_INST_OPCODE ip // extract opcode from wINST + GOTO_OPCODE ip // jump to next instruction + +.L_no_count_backwards: + cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? + b.ne .L_resume_backward_branch + mov x0, xSELF + add x1, xFP, #OFF_FP_SHADOWFRAME + mov x2, xINST + EXPORT_PC + bl MterpMaybeDoOnStackReplacement // (self, shadow_frame, offset) + cbnz x0, MterpOnStackReplacement + b .L_resume_backward_branch + +.L_forward_branch: + cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? + b.eq .L_check_osr_forward +.L_resume_forward_branch: + add w2, wINST, wINST // w2<- byte offset + FETCH_ADVANCE_INST_RB w2 // update rPC, load wINST + GET_INST_OPCODE ip // extract opcode from wINST + GOTO_OPCODE ip // jump to next instruction + +.L_check_osr_forward: + mov x0, xSELF + add x1, xFP, #OFF_FP_SHADOWFRAME + mov x2, xINST + EXPORT_PC + bl MterpMaybeDoOnStackReplacement // (self, shadow_frame, offset) + cbnz x0, MterpOnStackReplacement + b .L_resume_forward_branch + +.L_add_batch: + add x1, xFP, #OFF_FP_SHADOWFRAME + strh wPROFILE, [x1, #SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET] + ldr x0, [xFP, #OFF_FP_METHOD] + mov x2, xSELF + bl MterpAddHotnessBatch // (method, shadow_frame, self) + mov wPROFILE, w0 // restore new hotness countdown to wPROFILE + b .L_no_count_backwards + +/* + * Entered from the conditional branch handlers when OSR check request active on + * not-taken path. All Dalvik not-taken conditional branch offsets are 2. + */ +.L_check_not_taken_osr: + mov x0, xSELF + add x1, xFP, #OFF_FP_SHADOWFRAME + mov x2, #2 + EXPORT_PC + bl MterpMaybeDoOnStackReplacement // (self, shadow_frame, offset) + cbnz x0, MterpOnStackReplacement + FETCH_ADVANCE_INST 2 + GET_INST_OPCODE ip // extract opcode from wINST + GOTO_OPCODE ip // jump to next instruction + +/* + * Check for suspend check request. Assumes wINST already loaded, xPC advanced and + * still needs to get the opcode and branch to it, and flags are in lr. + */ +MterpCheckSuspendAndContinue: + ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh xIBASE + ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST + b.ne check1 + GET_INST_OPCODE ip // extract opcode from wINST + GOTO_OPCODE ip // jump to next instruction +check1: + EXPORT_PC + mov x0, xSELF + bl MterpSuspendCheck // (self) + cbnz x0, MterpFallback // Something in the environment changed, switch interpreters + GET_INST_OPCODE ip // extract opcode from wINST + GOTO_OPCODE ip // jump to next instruction + +/* + * On-stack replacement has happened, and now we've returned from the compiled method. + */ +MterpOnStackReplacement: +#if MTERP_LOGGING + mov x0, xSELF + add x1, xFP, #OFF_FP_SHADOWFRAME + sxtw x2, wINST + bl MterpLogOSR +#endif + mov x0, #1 // Signal normal return + b MterpDone + +/* + * Bail out to reference interpreter. + */ +MterpFallback: + EXPORT_PC +#if MTERP_LOGGING + mov x0, xSELF + add x1, xFP, #OFF_FP_SHADOWFRAME + bl MterpLogFallback +#endif +MterpCommonFallback: + mov x0, #0 // signal retry with reference interpreter. + b MterpDone + +/* + * We pushed some registers on the stack in ExecuteMterpImpl, then saved + * SP and LR. Here we restore SP, restore the registers, and then restore + * LR to PC. + * + * On entry: + * uint32_t* xFP (should still be live, pointer to base of vregs) + */ +MterpExceptionReturn: + mov x0, #1 // signal return to caller. + b MterpDone +MterpReturn: + ldr x2, [xFP, #OFF_FP_RESULT_REGISTER] + str x0, [x2] + mov x0, #1 // signal return to caller. +MterpDone: +/* + * At this point, we expect wPROFILE to be non-zero. If negative, hotness is disabled or we're + * checking for OSR. If greater than zero, we might have unreported hotness to register + * (the difference between the ending wPROFILE and the cached hotness counter). wPROFILE + * should only reach zero immediately after a hotness decrement, and is then reset to either + * a negative special state or the new non-zero countdown value. + */ + cmp wPROFILE, #0 + bgt MterpProfileActive // if > 0, we may have some counts to report. + .cfi_remember_state + RESTORE_TWO_REGS fp, lr, 64 + RESTORE_TWO_REGS xPC, xFP, 48 + RESTORE_TWO_REGS xSELF, xINST, 32 + RESTORE_TWO_REGS xIBASE, xREFS, 16 + RESTORE_TWO_REGS_DECREASE_FRAME xPROFILE, x27, 80 + ret + .cfi_restore_state // Reset unwind info so following code unwinds. + .cfi_def_cfa_offset 80 // workaround for clang bug: 31975598 + +MterpProfileActive: + mov xINST, x0 // stash return value + /* Report cached hotness counts */ + ldr x0, [xFP, #OFF_FP_METHOD] + add x1, xFP, #OFF_FP_SHADOWFRAME + mov x2, xSELF + strh wPROFILE, [x1, #SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET] + bl MterpAddHotnessBatch // (method, shadow_frame, self) + mov x0, xINST // restore return value + RESTORE_TWO_REGS fp, lr, 64 + RESTORE_TWO_REGS xPC, xFP, 48 + RESTORE_TWO_REGS xSELF, xINST, 32 + RESTORE_TWO_REGS xIBASE, xREFS, 16 + RESTORE_TWO_REGS_DECREASE_FRAME xPROFILE, x27, 80 + ret + + +%def instruction_end(): + + .type artMterpAsmInstructionEnd, #object + .hidden artMterpAsmInstructionEnd + .global artMterpAsmInstructionEnd +artMterpAsmInstructionEnd: + +%def instruction_end_alt(): + + .type artMterpAsmAltInstructionEnd, #object + .hidden artMterpAsmAltInstructionEnd + .global artMterpAsmAltInstructionEnd +artMterpAsmAltInstructionEnd: + +%def instruction_end_sister(): + + .type artMterpAsmSisterEnd, #object + .hidden artMterpAsmSisterEnd + .global artMterpAsmSisterEnd +artMterpAsmSisterEnd: + +%def instruction_start(): + + .type artMterpAsmInstructionStart, #object + .hidden artMterpAsmInstructionStart + .global artMterpAsmInstructionStart +artMterpAsmInstructionStart = .L_op_nop + .text + +%def instruction_start_alt(): + + .type artMterpAsmAltInstructionStart, #object + .hidden artMterpAsmAltInstructionStart + .global artMterpAsmAltInstructionStart +artMterpAsmAltInstructionStart = .L_ALT_op_nop + .text + +%def instruction_start_sister(): + + .type artMterpAsmSisterStart, #object + .hidden artMterpAsmSisterStart + .global artMterpAsmSisterStart + .text + .balign 4 +artMterpAsmSisterStart: diff --git a/runtime/interpreter/mterp/arm64/object.S b/runtime/interpreter/mterp/arm64/object.S new file mode 100644 index 0000000000..388aba57f8 --- /dev/null +++ b/runtime/interpreter/mterp/arm64/object.S @@ -0,0 +1,263 @@ +%def field(helper=""): + /* + * General field read / write (iget-* iput-* sget-* sput-*). + */ + .extern $helper + mov x0, xPC // arg0: Instruction* inst + mov x1, xINST // arg1: uint16_t inst_data + add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf + mov x3, xSELF // arg3: Thread* self + PREFETCH_INST 2 // prefetch next opcode + bl $helper + cbz x0, MterpPossibleException + ADVANCE 2 + GET_INST_OPCODE ip // extract opcode from rINST + GOTO_OPCODE ip // jump to next instruction + +%def op_check_cast(): + /* + * Check to see if a cast from one class to another is allowed. + */ + /* check-cast vAA, class//BBBB */ + EXPORT_PC + FETCH w0, 1 // w0<- BBBB + lsr w1, wINST, #8 // w1<- AA + VREG_INDEX_TO_ADDR x1, w1 // w1<- &object + ldr x2, [xFP, #OFF_FP_METHOD] // w2<- method + mov x3, xSELF // w3<- self + bl MterpCheckCast // (index, &obj, method, self) + PREFETCH_INST 2 + cbnz w0, MterpPossibleException + ADVANCE 2 + GET_INST_OPCODE ip // extract opcode from rINST + GOTO_OPCODE ip // jump to next instruction + +%def op_iget(is_object="0", helper="MterpIGetU32"): +% field(helper=helper) + +%def op_iget_boolean(): +% op_iget(helper="MterpIGetU8") + +%def op_iget_boolean_quick(): +% op_iget_quick(load="ldrb") + +%def op_iget_byte(): +% op_iget(helper="MterpIGetI8") + +%def op_iget_byte_quick(): +% op_iget_quick(load="ldrsb") + +%def op_iget_char(): +% op_iget(helper="MterpIGetU16") + +%def op_iget_char_quick(): +% op_iget_quick(load="ldrh") + +%def op_iget_object(): +% op_iget(is_object="1", helper="MterpIGetObj") + +%def op_iget_object_quick(): + /* For: iget-object-quick */ + /* op vA, vB, offset//CCCC */ + lsr w2, wINST, #12 // w2<- B + FETCH w1, 1 // w1<- field byte offset + EXPORT_PC + GET_VREG w0, w2 // w0<- object we're operating on + bl artIGetObjectFromMterp // (obj, offset) + ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] + ubfx w2, wINST, #8, #4 // w2<- A + PREFETCH_INST 2 + cbnz w3, MterpPossibleException // bail out + SET_VREG_OBJECT w0, w2 // fp[A]<- w0 + ADVANCE 2 // advance rPC + GET_INST_OPCODE ip // extract opcode from wINST + GOTO_OPCODE ip // jump to next instruction + +%def op_iget_quick(load="ldr", extend=""): + /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ + /* op vA, vB, offset//CCCC */ + lsr w2, wINST, #12 // w2<- B + FETCH w1, 1 // w1<- field byte offset + GET_VREG w3, w2 // w3<- object we're operating on + ubfx w2, wINST, #8, #4 // w2<- A + cbz w3, common_errNullObject // object was null + $load w0, [x3, x1] // w0<- obj.field + FETCH_ADVANCE_INST 2 // advance rPC, load rINST + $extend + SET_VREG w0, w2 // fp[A]<- w0 + GET_INST_OPCODE ip // extract opcode from rINST + GOTO_OPCODE ip // jump to next instruction + +%def op_iget_short(): +% op_iget(helper="MterpIGetI16") + +%def op_iget_short_quick(): +% op_iget_quick(load="ldrsh") + +%def op_iget_wide(): +% op_iget(helper="MterpIGetU64") + +%def op_iget_wide_quick(): + /* iget-wide-quick vA, vB, offset//CCCC */ + lsr w2, wINST, #12 // w2<- B + FETCH w4, 1 // w4<- field byte offset + GET_VREG w3, w2 // w3<- object we're operating on + ubfx w2, wINST, #8, #4 // w2<- A + cbz w3, common_errNullObject // object was null + ldr x0, [x3, x4] // x0<- obj.field + FETCH_ADVANCE_INST 2 // advance rPC, load wINST + SET_VREG_WIDE x0, w2 + GET_INST_OPCODE ip // extract opcode from wINST + GOTO_OPCODE ip // jump to next instruction + +%def op_instance_of(): + /* + * Check to see if an object reference is an instance of a class. + * + * Most common situation is a non-null object, being compared against + * an already-resolved class. + */ + /* instance-of vA, vB, class//CCCC */ + EXPORT_PC + FETCH w0, 1 // w0<- CCCC + lsr w1, wINST, #12 // w1<- B + VREG_INDEX_TO_ADDR x1, w1 // w1<- &object + ldr x2, [xFP, #OFF_FP_METHOD] // w2<- method + mov x3, xSELF // w3<- self + bl MterpInstanceOf // (index, &obj, method, self) + ldr x1, [xSELF, #THREAD_EXCEPTION_OFFSET] + ubfx w2, wINST, #8, #4 // w2<- A + PREFETCH_INST 2 + cbnz x1, MterpException + ADVANCE 2 // advance rPC + SET_VREG w0, w2 // vA<- w0 + GET_INST_OPCODE ip // extract opcode from rINST + GOTO_OPCODE ip // jump to next instruction + +%def op_iput(is_object="0", helper="MterpIPutU32"): +% field(helper=helper) + +%def op_iput_boolean(): +% op_iput(helper="MterpIPutU8") + +%def op_iput_boolean_quick(): +% op_iput_quick(store="strb") + +%def op_iput_byte(): +% op_iput(helper="MterpIPutI8") + +%def op_iput_byte_quick(): +% op_iput_quick(store="strb") + +%def op_iput_char(): +% op_iput(helper="MterpIPutU16") + +%def op_iput_char_quick(): +% op_iput_quick(store="strh") + +%def op_iput_object(): +% op_iput(is_object="1", helper="MterpIPutObj") + +%def op_iput_object_quick(): + EXPORT_PC + add x0, xFP, #OFF_FP_SHADOWFRAME + mov x1, xPC + mov w2, wINST + bl MterpIputObjectQuick + cbz w0, MterpException + FETCH_ADVANCE_INST 2 // advance rPC, load rINST + GET_INST_OPCODE ip // extract opcode from rINST + GOTO_OPCODE ip // jump to next instruction + +%def op_iput_quick(store="str"): + /* For: iput-quick, iput-object-quick */ + /* op vA, vB, offset//CCCC */ + lsr w2, wINST, #12 // w2<- B + FETCH w1, 1 // w1<- field byte offset + GET_VREG w3, w2 // w3<- fp[B], the object pointer + ubfx w2, wINST, #8, #4 // w2<- A + cbz w3, common_errNullObject // object was null + GET_VREG w0, w2 // w0<- fp[A] + FETCH_ADVANCE_INST 2 // advance rPC, load rINST + $store w0, [x3, x1] // obj.field<- w0 + GET_INST_OPCODE ip // extract opcode from rINST + GOTO_OPCODE ip // jump to next instruction + +%def op_iput_short(): +% op_iput(helper="MterpIPutI16") + +%def op_iput_short_quick(): +% op_iput_quick(store="strh") + +%def op_iput_wide(): +% op_iput(helper="MterpIPutU64") + +%def op_iput_wide_quick(): + /* iput-wide-quick vA, vB, offset//CCCC */ + lsr w2, wINST, #12 // w2<- B + FETCH w3, 1 // w3<- field byte offset + GET_VREG w2, w2 // w2<- fp[B], the object pointer + ubfx w0, wINST, #8, #4 // w0<- A + cbz w2, common_errNullObject // object was null + GET_VREG_WIDE x0, w0 // x0<- fp[A] + FETCH_ADVANCE_INST 2 // advance rPC, load wINST + str x0, [x2, x3] // obj.field<- x0 + GET_INST_OPCODE ip // extract opcode from wINST + GOTO_OPCODE ip // jump to next instruction + +%def op_new_instance(): + /* + * Create a new instance of a class. + */ + /* new-instance vAA, class//BBBB */ + EXPORT_PC + add x0, xFP, #OFF_FP_SHADOWFRAME + mov x1, xSELF + mov w2, wINST + bl MterpNewInstance // (shadow_frame, self, inst_data) + cbz w0, MterpPossibleException + FETCH_ADVANCE_INST 2 // advance rPC, load rINST + GET_INST_OPCODE ip // extract opcode from rINST + GOTO_OPCODE ip // jump to next instruction + +%def op_sget(is_object="0", helper="MterpSGetU32"): +% field(helper=helper) + +%def op_sget_boolean(): +% op_sget(helper="MterpSGetU8") + +%def op_sget_byte(): +% op_sget(helper="MterpSGetI8") + +%def op_sget_char(): +% op_sget(helper="MterpSGetU16") + +%def op_sget_object(): +% op_sget(is_object="1", helper="MterpSGetObj") + +%def op_sget_short(): +% op_sget(helper="MterpSGetI16") + +%def op_sget_wide(): +% op_sget(helper="MterpSGetU64") + +%def op_sput(is_object="0", helper="MterpSPutU32"): +% field(helper=helper) + +%def op_sput_boolean(): +% op_sput(helper="MterpSPutU8") + +%def op_sput_byte(): +% op_sput(helper="MterpSPutI8") + +%def op_sput_char(): +% op_sput(helper="MterpSPutU16") + +%def op_sput_object(): +% op_sput(is_object="1", helper="MterpSPutObj") + +%def op_sput_short(): +% op_sput(helper="MterpSPutI16") + +%def op_sput_wide(): +% op_sput(helper="MterpSPutU64") diff --git a/runtime/interpreter/mterp/arm64/op_add_double.S b/runtime/interpreter/mterp/arm64/op_add_double.S deleted file mode 100644 index 8d31342b38..0000000000 --- a/runtime/interpreter/mterp/arm64/op_add_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_double(): -% binopWide(instr="fadd d0, d1, d2", result="d0", r1="d1", r2="d2") diff --git a/runtime/interpreter/mterp/arm64/op_add_double_2addr.S b/runtime/interpreter/mterp/arm64/op_add_double_2addr.S deleted file mode 100644 index 88c1d5e0bd..0000000000 --- a/runtime/interpreter/mterp/arm64/op_add_double_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_double_2addr(): -% binopWide2addr(instr="fadd d0, d0, d1", r0="d0", r1="d1") diff --git a/runtime/interpreter/mterp/arm64/op_add_float.S b/runtime/interpreter/mterp/arm64/op_add_float.S deleted file mode 100644 index 388732e34e..0000000000 --- a/runtime/interpreter/mterp/arm64/op_add_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_float(): -% fbinop(instr="fadd s0, s0, s1") diff --git a/runtime/interpreter/mterp/arm64/op_add_float_2addr.S b/runtime/interpreter/mterp/arm64/op_add_float_2addr.S deleted file mode 100644 index 061c9d52ae..0000000000 --- a/runtime/interpreter/mterp/arm64/op_add_float_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_float_2addr(): -% fbinop2addr(instr="fadd s2, s0, s1") diff --git a/runtime/interpreter/mterp/arm64/op_add_int.S b/runtime/interpreter/mterp/arm64/op_add_int.S deleted file mode 100644 index 99953ee837..0000000000 --- a/runtime/interpreter/mterp/arm64/op_add_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_int(): -% binop(instr="add w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_add_int_2addr.S b/runtime/interpreter/mterp/arm64/op_add_int_2addr.S deleted file mode 100644 index d61fcce27d..0000000000 --- a/runtime/interpreter/mterp/arm64/op_add_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_int_2addr(): -% binop2addr(instr="add w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_add_int_lit16.S b/runtime/interpreter/mterp/arm64/op_add_int_lit16.S deleted file mode 100644 index 37bf2e8621..0000000000 --- a/runtime/interpreter/mterp/arm64/op_add_int_lit16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_int_lit16(): -% binopLit16(instr="add w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_add_int_lit8.S b/runtime/interpreter/mterp/arm64/op_add_int_lit8.S deleted file mode 100644 index f4cab96fec..0000000000 --- a/runtime/interpreter/mterp/arm64/op_add_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_int_lit8(): -% binopLit8(extract="", instr="add w0, w0, w3, asr #8") diff --git a/runtime/interpreter/mterp/arm64/op_add_long.S b/runtime/interpreter/mterp/arm64/op_add_long.S deleted file mode 100644 index 0ac32466bc..0000000000 --- a/runtime/interpreter/mterp/arm64/op_add_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_long(): -% binopWide(instr="add x0, x1, x2") diff --git a/runtime/interpreter/mterp/arm64/op_add_long_2addr.S b/runtime/interpreter/mterp/arm64/op_add_long_2addr.S deleted file mode 100644 index 03987eb5c6..0000000000 --- a/runtime/interpreter/mterp/arm64/op_add_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_long_2addr(): -% binopWide2addr(instr="add x0, x0, x1") diff --git a/runtime/interpreter/mterp/arm64/op_aget.S b/runtime/interpreter/mterp/arm64/op_aget.S deleted file mode 100644 index edc62f5cbb..0000000000 --- a/runtime/interpreter/mterp/arm64/op_aget.S +++ /dev/null @@ -1,28 +0,0 @@ -%def op_aget(load="ldr", shift="2", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"): - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B w2, 1, 0 // w2<- BB - lsr w9, wINST, #8 // w9<- AA - FETCH_B w3, 1, 1 // w3<- CC - GET_VREG w0, w2 // w0<- vBB (array object) - GET_VREG w1, w3 // w1<- vCC (requested index) - cbz x0, common_errNullObject // bail if null array object. - ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length - add x0, x0, w1, uxtw #$shift // w0<- arrayObj + index*width - cmp w1, w3 // compare unsigned index, length - bcs common_errArrayIndex // index >= length, bail - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - $load w2, [x0, #$data_offset] // w2<- vBB[vCC] - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w2, w9 // vAA<- w2 - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_aget_boolean.S b/runtime/interpreter/mterp/arm64/op_aget_boolean.S deleted file mode 100644 index d6e0a1bbd9..0000000000 --- a/runtime/interpreter/mterp/arm64/op_aget_boolean.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aget_boolean(): -% op_aget(load="ldrb", shift="0", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/arm64/op_aget_byte.S b/runtime/interpreter/mterp/arm64/op_aget_byte.S deleted file mode 100644 index 6c9f1b78fa..0000000000 --- a/runtime/interpreter/mterp/arm64/op_aget_byte.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aget_byte(): -% op_aget(load="ldrsb", shift="0", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/arm64/op_aget_char.S b/runtime/interpreter/mterp/arm64/op_aget_char.S deleted file mode 100644 index c5812e3aff..0000000000 --- a/runtime/interpreter/mterp/arm64/op_aget_char.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aget_char(): -% op_aget(load="ldrh", shift="1", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/arm64/op_aget_object.S b/runtime/interpreter/mterp/arm64/op_aget_object.S deleted file mode 100644 index 0c5d2c394d..0000000000 --- a/runtime/interpreter/mterp/arm64/op_aget_object.S +++ /dev/null @@ -1,21 +0,0 @@ -%def op_aget_object(): - /* - * Array object get. vAA <- vBB[vCC]. - * - * for: aget-object - */ - /* op vAA, vBB, vCC */ - FETCH_B w2, 1, 0 // w2<- BB - FETCH_B w3, 1, 1 // w3<- CC - EXPORT_PC - GET_VREG w0, w2 // w0<- vBB (array object) - GET_VREG w1, w3 // w1<- vCC (requested index) - bl artAGetObjectFromMterp // (array, index) - ldr x1, [xSELF, #THREAD_EXCEPTION_OFFSET] - lsr w2, wINST, #8 // w9<- AA - PREFETCH_INST 2 - cbnz w1, MterpException - SET_VREG_OBJECT w0, w2 - ADVANCE 2 - GET_INST_OPCODE ip - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_aget_short.S b/runtime/interpreter/mterp/arm64/op_aget_short.S deleted file mode 100644 index 9727560fe4..0000000000 --- a/runtime/interpreter/mterp/arm64/op_aget_short.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aget_short(): -% op_aget(load="ldrsh", shift="1", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/arm64/op_aget_wide.S b/runtime/interpreter/mterp/arm64/op_aget_wide.S deleted file mode 100644 index e9bccd6e4e..0000000000 --- a/runtime/interpreter/mterp/arm64/op_aget_wide.S +++ /dev/null @@ -1,22 +0,0 @@ -%def op_aget_wide(): - /* - * Array get, 64 bits. vAA <- vBB[vCC]. - * - */ - /* aget-wide vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - and w2, w0, #255 // w2<- BB - lsr w3, w0, #8 // w3<- CC - GET_VREG w0, w2 // w0<- vBB (array object) - GET_VREG w1, w3 // w1<- vCC (requested index) - cbz w0, common_errNullObject // yes, bail - ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length - add x0, x0, w1, lsl #3 // w0<- arrayObj + index*width - cmp w1, w3 // compare unsigned index, length - bcs common_errArrayIndex // index >= length, bail - FETCH_ADVANCE_INST 2 // advance rPC, load wINST - ldr x2, [x0, #MIRROR_WIDE_ARRAY_DATA_OFFSET] // x2<- vBB[vCC] - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG_WIDE x2, w4 - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_and_int.S b/runtime/interpreter/mterp/arm64/op_and_int.S deleted file mode 100644 index 364e615843..0000000000 --- a/runtime/interpreter/mterp/arm64/op_and_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_and_int(): -% binop(instr="and w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_and_int_2addr.S b/runtime/interpreter/mterp/arm64/op_and_int_2addr.S deleted file mode 100644 index 98a5c5db3a..0000000000 --- a/runtime/interpreter/mterp/arm64/op_and_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_and_int_2addr(): -% binop2addr(instr="and w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_and_int_lit16.S b/runtime/interpreter/mterp/arm64/op_and_int_lit16.S deleted file mode 100644 index add2ecc83b..0000000000 --- a/runtime/interpreter/mterp/arm64/op_and_int_lit16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_and_int_lit16(): -% binopLit16(instr="and w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_and_int_lit8.S b/runtime/interpreter/mterp/arm64/op_and_int_lit8.S deleted file mode 100644 index bf68c2a5cc..0000000000 --- a/runtime/interpreter/mterp/arm64/op_and_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_and_int_lit8(): -% binopLit8(extract="", instr="and w0, w0, w3, asr #8") diff --git a/runtime/interpreter/mterp/arm64/op_and_long.S b/runtime/interpreter/mterp/arm64/op_and_long.S deleted file mode 100644 index aff5eadd05..0000000000 --- a/runtime/interpreter/mterp/arm64/op_and_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_and_long(): -% binopWide(instr="and x0, x1, x2") diff --git a/runtime/interpreter/mterp/arm64/op_and_long_2addr.S b/runtime/interpreter/mterp/arm64/op_and_long_2addr.S deleted file mode 100644 index ba71e5cec1..0000000000 --- a/runtime/interpreter/mterp/arm64/op_and_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_and_long_2addr(): -% binopWide2addr(instr="and x0, x0, x1") diff --git a/runtime/interpreter/mterp/arm64/op_aput.S b/runtime/interpreter/mterp/arm64/op_aput.S deleted file mode 100644 index 85dd5564a9..0000000000 --- a/runtime/interpreter/mterp/arm64/op_aput.S +++ /dev/null @@ -1,28 +0,0 @@ -%def op_aput(store="str", shift="2", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"): - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B w2, 1, 0 // w2<- BB - lsr w9, wINST, #8 // w9<- AA - FETCH_B w3, 1, 1 // w3<- CC - GET_VREG w0, w2 // w0<- vBB (array object) - GET_VREG w1, w3 // w1<- vCC (requested index) - cbz w0, common_errNullObject // bail if null - ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length - add x0, x0, w1, lsl #$shift // w0<- arrayObj + index*width - cmp w1, w3 // compare unsigned index, length - bcs common_errArrayIndex // index >= length, bail - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_VREG w2, w9 // w2<- vAA - GET_INST_OPCODE ip // extract opcode from rINST - $store w2, [x0, #$data_offset] // vBB[vCC]<- w2 - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_aput_boolean.S b/runtime/interpreter/mterp/arm64/op_aput_boolean.S deleted file mode 100644 index 467cc4bf20..0000000000 --- a/runtime/interpreter/mterp/arm64/op_aput_boolean.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aput_boolean(): -% op_aput(store="strb", shift="0", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/arm64/op_aput_byte.S b/runtime/interpreter/mterp/arm64/op_aput_byte.S deleted file mode 100644 index 2b4c0ba389..0000000000 --- a/runtime/interpreter/mterp/arm64/op_aput_byte.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aput_byte(): -% op_aput(store="strb", shift="0", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/arm64/op_aput_char.S b/runtime/interpreter/mterp/arm64/op_aput_char.S deleted file mode 100644 index cb7dcbad4d..0000000000 --- a/runtime/interpreter/mterp/arm64/op_aput_char.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aput_char(): -% op_aput(store="strh", shift="1", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/arm64/op_aput_object.S b/runtime/interpreter/mterp/arm64/op_aput_object.S deleted file mode 100644 index 4d1ee65f7f..0000000000 --- a/runtime/interpreter/mterp/arm64/op_aput_object.S +++ /dev/null @@ -1,14 +0,0 @@ -%def op_aput_object(): - /* - * Store an object into an array. vBB[vCC] <- vAA. - */ - /* op vAA, vBB, vCC */ - EXPORT_PC - add x0, xFP, #OFF_FP_SHADOWFRAME - mov x1, xPC - mov w2, wINST - bl MterpAputObject - cbz w0, MterpPossibleException - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_aput_short.S b/runtime/interpreter/mterp/arm64/op_aput_short.S deleted file mode 100644 index f624163087..0000000000 --- a/runtime/interpreter/mterp/arm64/op_aput_short.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aput_short(): -% op_aput(store="strh", shift="1", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/arm64/op_aput_wide.S b/runtime/interpreter/mterp/arm64/op_aput_wide.S deleted file mode 100644 index 8498783f81..0000000000 --- a/runtime/interpreter/mterp/arm64/op_aput_wide.S +++ /dev/null @@ -1,22 +0,0 @@ -%def op_aput_wide(): - /* - * Array put, 64 bits. vBB[vCC] <- vAA. - * - */ - /* aput-wide vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - and w2, w0, #255 // w2<- BB - lsr w3, w0, #8 // w3<- CC - GET_VREG w0, w2 // w0<- vBB (array object) - GET_VREG w1, w3 // w1<- vCC (requested index) - cbz w0, common_errNullObject // bail if null - ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length - add x0, x0, w1, lsl #3 // w0<- arrayObj + index*width - cmp w1, w3 // compare unsigned index, length - bcs common_errArrayIndex // index >= length, bail - GET_VREG_WIDE x1, w4 - FETCH_ADVANCE_INST 2 // advance rPC, load wINST - GET_INST_OPCODE ip // extract opcode from wINST - str x1, [x0, #MIRROR_WIDE_ARRAY_DATA_OFFSET] - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_array_length.S b/runtime/interpreter/mterp/arm64/op_array_length.S deleted file mode 100644 index 26979b837f..0000000000 --- a/runtime/interpreter/mterp/arm64/op_array_length.S +++ /dev/null @@ -1,13 +0,0 @@ -%def op_array_length(): - /* - * Return the length of an array. - */ - lsr w1, wINST, #12 // w1<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG w0, w1 // w0<- vB (object ref) - cbz w0, common_errNullObject // yup, fail - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- array length - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w3, w2 // vB<- length - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_check_cast.S b/runtime/interpreter/mterp/arm64/op_check_cast.S deleted file mode 100644 index 359c860e48..0000000000 --- a/runtime/interpreter/mterp/arm64/op_check_cast.S +++ /dev/null @@ -1,17 +0,0 @@ -%def op_check_cast(): - /* - * Check to see if a cast from one class to another is allowed. - */ - /* check-cast vAA, class//BBBB */ - EXPORT_PC - FETCH w0, 1 // w0<- BBBB - lsr w1, wINST, #8 // w1<- AA - VREG_INDEX_TO_ADDR x1, w1 // w1<- &object - ldr x2, [xFP, #OFF_FP_METHOD] // w2<- method - mov x3, xSELF // w3<- self - bl MterpCheckCast // (index, &obj, method, self) - PREFETCH_INST 2 - cbnz w0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_cmp_long.S b/runtime/interpreter/mterp/arm64/op_cmp_long.S deleted file mode 100644 index 636262c2f7..0000000000 --- a/runtime/interpreter/mterp/arm64/op_cmp_long.S +++ /dev/null @@ -1,14 +0,0 @@ -%def op_cmp_long(): - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - and w2, w0, #255 // w2<- BB - lsr w3, w0, #8 // w3<- CC - GET_VREG_WIDE x1, w2 - GET_VREG_WIDE x2, w3 - cmp x1, x2 - cset w0, ne - cneg w0, w0, lt - FETCH_ADVANCE_INST 2 // advance rPC, load wINST - SET_VREG w0, w4 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_cmpg_double.S b/runtime/interpreter/mterp/arm64/op_cmpg_double.S deleted file mode 100644 index 4527873eb1..0000000000 --- a/runtime/interpreter/mterp/arm64/op_cmpg_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_cmpg_double(): -% fcmp(wide="_WIDE", r1="d1", r2="d2", cond="cc") diff --git a/runtime/interpreter/mterp/arm64/op_cmpg_float.S b/runtime/interpreter/mterp/arm64/op_cmpg_float.S deleted file mode 100644 index 395d1862f7..0000000000 --- a/runtime/interpreter/mterp/arm64/op_cmpg_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_cmpg_float(): -% fcmp(wide="", r1="s1", r2="s2", cond="cc") diff --git a/runtime/interpreter/mterp/arm64/op_cmpl_double.S b/runtime/interpreter/mterp/arm64/op_cmpl_double.S deleted file mode 100644 index 67b69c8b65..0000000000 --- a/runtime/interpreter/mterp/arm64/op_cmpl_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_cmpl_double(): -% fcmp(wide="_WIDE", r1="d1", r2="d2", cond="lt") diff --git a/runtime/interpreter/mterp/arm64/op_cmpl_float.S b/runtime/interpreter/mterp/arm64/op_cmpl_float.S deleted file mode 100644 index 7574f4cec7..0000000000 --- a/runtime/interpreter/mterp/arm64/op_cmpl_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_cmpl_float(): -% fcmp(wide="", r1="s1", r2="s2", cond="lt") diff --git a/runtime/interpreter/mterp/arm64/op_const.S b/runtime/interpreter/mterp/arm64/op_const.S deleted file mode 100644 index 493611e473..0000000000 --- a/runtime/interpreter/mterp/arm64/op_const.S +++ /dev/null @@ -1,10 +0,0 @@ -%def op_const(): - /* const vAA, #+BBBBbbbb */ - lsr w3, wINST, #8 // w3<- AA - FETCH w0, 1 // w0<- bbbb (low - FETCH w1, 2 // w1<- BBBB (high - FETCH_ADVANCE_INST 3 // advance rPC, load wINST - orr w0, w0, w1, lsl #16 // w0<- BBBBbbbb - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG w0, w3 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_const_16.S b/runtime/interpreter/mterp/arm64/op_const_16.S deleted file mode 100644 index 75e69364a7..0000000000 --- a/runtime/interpreter/mterp/arm64/op_const_16.S +++ /dev/null @@ -1,8 +0,0 @@ -%def op_const_16(): - /* const/16 vAA, #+BBBB */ - FETCH_S w0, 1 // w0<- ssssBBBB (sign-extended) - lsr w3, wINST, #8 // w3<- AA - FETCH_ADVANCE_INST 2 // advance xPC, load wINST - SET_VREG w0, w3 // vAA<- w0 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_const_4.S b/runtime/interpreter/mterp/arm64/op_const_4.S deleted file mode 100644 index e6281ed82c..0000000000 --- a/runtime/interpreter/mterp/arm64/op_const_4.S +++ /dev/null @@ -1,8 +0,0 @@ -%def op_const_4(): - /* const/4 vA, #+B */ - sbfx w1, wINST, #12, #4 // w1<- sssssssB - ubfx w0, wINST, #8, #4 // w0<- A - FETCH_ADVANCE_INST 1 // advance xPC, load wINST - GET_INST_OPCODE ip // ip<- opcode from xINST - SET_VREG w1, w0 // fp[A]<- w1 - GOTO_OPCODE ip // execute next instruction diff --git a/runtime/interpreter/mterp/arm64/op_const_class.S b/runtime/interpreter/mterp/arm64/op_const_class.S deleted file mode 100644 index db12ec3141..0000000000 --- a/runtime/interpreter/mterp/arm64/op_const_class.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_const_class(): -% const(helper="MterpConstClass") diff --git a/runtime/interpreter/mterp/arm64/op_const_high16.S b/runtime/interpreter/mterp/arm64/op_const_high16.S deleted file mode 100644 index 8a8558f0fc..0000000000 --- a/runtime/interpreter/mterp/arm64/op_const_high16.S +++ /dev/null @@ -1,9 +0,0 @@ -%def op_const_high16(): - /* const/high16 vAA, #+BBBB0000 */ - FETCH w0, 1 // r0<- 0000BBBB (zero-extended) - lsr w3, wINST, #8 // r3<- AA - lsl w0, w0, #16 // r0<- BBBB0000 - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - SET_VREG w0, w3 // vAA<- r0 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_const_method_handle.S b/runtime/interpreter/mterp/arm64/op_const_method_handle.S deleted file mode 100644 index 2680c17aad..0000000000 --- a/runtime/interpreter/mterp/arm64/op_const_method_handle.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_const_method_handle(): -% const(helper="MterpConstMethodHandle") diff --git a/runtime/interpreter/mterp/arm64/op_const_method_type.S b/runtime/interpreter/mterp/arm64/op_const_method_type.S deleted file mode 100644 index ea814bf648..0000000000 --- a/runtime/interpreter/mterp/arm64/op_const_method_type.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_const_method_type(): -% const(helper="MterpConstMethodType") diff --git a/runtime/interpreter/mterp/arm64/op_const_string.S b/runtime/interpreter/mterp/arm64/op_const_string.S deleted file mode 100644 index 41376f8703..0000000000 --- a/runtime/interpreter/mterp/arm64/op_const_string.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_const_string(): -% const(helper="MterpConstString") diff --git a/runtime/interpreter/mterp/arm64/op_const_string_jumbo.S b/runtime/interpreter/mterp/arm64/op_const_string_jumbo.S deleted file mode 100644 index 1a78bcb799..0000000000 --- a/runtime/interpreter/mterp/arm64/op_const_string_jumbo.S +++ /dev/null @@ -1,15 +0,0 @@ -%def op_const_string_jumbo(): - /* const/string vAA, String//BBBBBBBB */ - EXPORT_PC - FETCH w0, 1 // w0<- bbbb (low - FETCH w2, 2 // w2<- BBBB (high - lsr w1, wINST, #8 // w1<- AA - orr w0, w0, w2, lsl #16 // w1<- BBBBbbbb - add x2, xFP, #OFF_FP_SHADOWFRAME - mov x3, xSELF - bl MterpConstString // (index, tgt_reg, shadow_frame, self) - PREFETCH_INST 3 // advance rPC - cbnz w0, MterpPossibleException // let reference interpreter deal with it. - ADVANCE 3 // advance rPC - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_const_wide.S b/runtime/interpreter/mterp/arm64/op_const_wide.S deleted file mode 100644 index 6d3be6b127..0000000000 --- a/runtime/interpreter/mterp/arm64/op_const_wide.S +++ /dev/null @@ -1,14 +0,0 @@ -%def op_const_wide(): - /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ - FETCH w0, 1 // w0<- bbbb (low) - FETCH w1, 2 // w1<- BBBB (low middle) - FETCH w2, 3 // w2<- hhhh (high middle) - FETCH w3, 4 // w3<- HHHH (high) - lsr w4, wINST, #8 // r4<- AA - FETCH_ADVANCE_INST 5 // advance rPC, load wINST - GET_INST_OPCODE ip // extract opcode from wINST - orr w0, w0, w1, lsl #16 // w0<- BBBBbbbb - orr x0, x0, x2, lsl #32 // w0<- hhhhBBBBbbbb - orr x0, x0, x3, lsl #48 // w0<- HHHHhhhhBBBBbbbb - SET_VREG_WIDE x0, w4 - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_const_wide_16.S b/runtime/interpreter/mterp/arm64/op_const_wide_16.S deleted file mode 100644 index 04615e1d4e..0000000000 --- a/runtime/interpreter/mterp/arm64/op_const_wide_16.S +++ /dev/null @@ -1,8 +0,0 @@ -%def op_const_wide_16(): - /* const-wide/16 vAA, #+BBBB */ - FETCH_S x0, 1 // x0<- ssssssssssssBBBB (sign-extended) - lsr w3, wINST, #8 // w3<- AA - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w3 - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_const_wide_32.S b/runtime/interpreter/mterp/arm64/op_const_wide_32.S deleted file mode 100644 index 627ddea3ea..0000000000 --- a/runtime/interpreter/mterp/arm64/op_const_wide_32.S +++ /dev/null @@ -1,10 +0,0 @@ -%def op_const_wide_32(): - /* const-wide/32 vAA, #+BBBBbbbb */ - FETCH w0, 1 // x0<- 000000000000bbbb (low) - lsr w3, wINST, #8 // w3<- AA - FETCH_S x2, 2 // x2<- ssssssssssssBBBB (high) - FETCH_ADVANCE_INST 3 // advance rPC, load wINST - GET_INST_OPCODE ip // extract opcode from wINST - orr x0, x0, x2, lsl #16 // x0<- ssssssssBBBBbbbb - SET_VREG_WIDE x0, w3 - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_const_wide_high16.S b/runtime/interpreter/mterp/arm64/op_const_wide_high16.S deleted file mode 100644 index d51d25f3e1..0000000000 --- a/runtime/interpreter/mterp/arm64/op_const_wide_high16.S +++ /dev/null @@ -1,9 +0,0 @@ -%def op_const_wide_high16(): - /* const-wide/high16 vAA, #+BBBB000000000000 */ - FETCH w0, 1 // w0<- 0000BBBB (zero-extended) - lsr w1, wINST, #8 // w1<- AA - FETCH_ADVANCE_INST 2 // advance rPC, load wINST - lsl x0, x0, #48 - SET_VREG_WIDE x0, w1 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_div_double.S b/runtime/interpreter/mterp/arm64/op_div_double.S deleted file mode 100644 index ec5b1f5bbb..0000000000 --- a/runtime/interpreter/mterp/arm64/op_div_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_double(): -% binopWide(instr="fdiv d0, d1, d2", result="d0", r1="d1", r2="d2") diff --git a/runtime/interpreter/mterp/arm64/op_div_double_2addr.S b/runtime/interpreter/mterp/arm64/op_div_double_2addr.S deleted file mode 100644 index e2781b884f..0000000000 --- a/runtime/interpreter/mterp/arm64/op_div_double_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_double_2addr(): -% binopWide2addr(instr="fdiv d0, d0, d1", r0="d0", r1="d1") diff --git a/runtime/interpreter/mterp/arm64/op_div_float.S b/runtime/interpreter/mterp/arm64/op_div_float.S deleted file mode 100644 index f0e72c43f9..0000000000 --- a/runtime/interpreter/mterp/arm64/op_div_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_float(): -% fbinop(instr="fdiv s0, s0, s1") diff --git a/runtime/interpreter/mterp/arm64/op_div_float_2addr.S b/runtime/interpreter/mterp/arm64/op_div_float_2addr.S deleted file mode 100644 index aa73950ce5..0000000000 --- a/runtime/interpreter/mterp/arm64/op_div_float_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_float_2addr(): -% fbinop2addr(instr="fdiv s2, s0, s1") diff --git a/runtime/interpreter/mterp/arm64/op_div_int.S b/runtime/interpreter/mterp/arm64/op_div_int.S deleted file mode 100644 index 6f4cbf327f..0000000000 --- a/runtime/interpreter/mterp/arm64/op_div_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_int(): -% binop(instr="sdiv w0, w0, w1", chkzero="1") diff --git a/runtime/interpreter/mterp/arm64/op_div_int_2addr.S b/runtime/interpreter/mterp/arm64/op_div_int_2addr.S deleted file mode 100644 index eb01066621..0000000000 --- a/runtime/interpreter/mterp/arm64/op_div_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_int_2addr(): -% binop2addr(instr="sdiv w0, w0, w1", chkzero="1") diff --git a/runtime/interpreter/mterp/arm64/op_div_int_lit16.S b/runtime/interpreter/mterp/arm64/op_div_int_lit16.S deleted file mode 100644 index c5cdb96fcf..0000000000 --- a/runtime/interpreter/mterp/arm64/op_div_int_lit16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_int_lit16(): -% binopLit16(instr="sdiv w0, w0, w1", chkzero="1") diff --git a/runtime/interpreter/mterp/arm64/op_div_int_lit8.S b/runtime/interpreter/mterp/arm64/op_div_int_lit8.S deleted file mode 100644 index 3842cd92b1..0000000000 --- a/runtime/interpreter/mterp/arm64/op_div_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_int_lit8(): -% binopLit8(instr="sdiv w0, w0, w1", chkzero="1") diff --git a/runtime/interpreter/mterp/arm64/op_div_long.S b/runtime/interpreter/mterp/arm64/op_div_long.S deleted file mode 100644 index 696a91f134..0000000000 --- a/runtime/interpreter/mterp/arm64/op_div_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_long(): -% binopWide(instr="sdiv x0, x1, x2", chkzero="1") diff --git a/runtime/interpreter/mterp/arm64/op_div_long_2addr.S b/runtime/interpreter/mterp/arm64/op_div_long_2addr.S deleted file mode 100644 index cac878c41c..0000000000 --- a/runtime/interpreter/mterp/arm64/op_div_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_long_2addr(): -% binopWide2addr(instr="sdiv x0, x0, x1", chkzero="1") diff --git a/runtime/interpreter/mterp/arm64/op_double_to_float.S b/runtime/interpreter/mterp/arm64/op_double_to_float.S deleted file mode 100644 index 292dcc78a6..0000000000 --- a/runtime/interpreter/mterp/arm64/op_double_to_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_double_to_float(): -% funopNarrower(instr="fcvt s0, d0", srcreg="d0", tgtreg="s0") diff --git a/runtime/interpreter/mterp/arm64/op_double_to_int.S b/runtime/interpreter/mterp/arm64/op_double_to_int.S deleted file mode 100644 index 640e6daa81..0000000000 --- a/runtime/interpreter/mterp/arm64/op_double_to_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_double_to_int(): -% funopNarrower(instr="fcvtzs w0, d0", srcreg="d0", tgtreg="w0") diff --git a/runtime/interpreter/mterp/arm64/op_double_to_long.S b/runtime/interpreter/mterp/arm64/op_double_to_long.S deleted file mode 100644 index 99c15eb601..0000000000 --- a/runtime/interpreter/mterp/arm64/op_double_to_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_double_to_long(): -% funopWide(instr="fcvtzs x0, d0", srcreg="d0", tgtreg="x0") diff --git a/runtime/interpreter/mterp/arm64/op_fill_array_data.S b/runtime/interpreter/mterp/arm64/op_fill_array_data.S deleted file mode 100644 index 2ae444cc29..0000000000 --- a/runtime/interpreter/mterp/arm64/op_fill_array_data.S +++ /dev/null @@ -1,14 +0,0 @@ -%def op_fill_array_data(): - /* fill-array-data vAA, +BBBBBBBB */ - EXPORT_PC - FETCH w0, 1 // x0<- 000000000000bbbb (lo) - FETCH_S x1, 2 // x1<- ssssssssssssBBBB (hi) - lsr w3, wINST, #8 // w3<- AA - orr x1, x0, x1, lsl #16 // x1<- ssssssssBBBBbbbb - GET_VREG w0, w3 // w0<- vAA (array object) - add x1, xPC, x1, lsl #1 // x1<- PC + ssssssssBBBBbbbb*2 (array data off.) - bl MterpFillArrayData // (obj, payload) - cbz w0, MterpPossibleException // exception? - FETCH_ADVANCE_INST 3 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_filled_new_array.S b/runtime/interpreter/mterp/arm64/op_filled_new_array.S deleted file mode 100644 index 2be627c3af..0000000000 --- a/runtime/interpreter/mterp/arm64/op_filled_new_array.S +++ /dev/null @@ -1,18 +0,0 @@ -%def op_filled_new_array(helper="MterpFilledNewArray"): - /* - * Create a new array with elements filled from registers. - * - * for: filled-new-array, filled-new-array/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class//CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, type//BBBB */ - .extern $helper - EXPORT_PC - add x0, xFP, #OFF_FP_SHADOWFRAME - mov x1, xPC - mov x2, xSELF - bl $helper - cbz w0, MterpPossibleException - FETCH_ADVANCE_INST 3 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_filled_new_array_range.S b/runtime/interpreter/mterp/arm64/op_filled_new_array_range.S deleted file mode 100644 index 1667de149a..0000000000 --- a/runtime/interpreter/mterp/arm64/op_filled_new_array_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_filled_new_array_range(): -% op_filled_new_array(helper="MterpFilledNewArrayRange") diff --git a/runtime/interpreter/mterp/arm64/op_float_to_double.S b/runtime/interpreter/mterp/arm64/op_float_to_double.S deleted file mode 100644 index c3dff39283..0000000000 --- a/runtime/interpreter/mterp/arm64/op_float_to_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_float_to_double(): -% funopWider(instr="fcvt d0, s0", srcreg="s0", tgtreg="d0") diff --git a/runtime/interpreter/mterp/arm64/op_float_to_int.S b/runtime/interpreter/mterp/arm64/op_float_to_int.S deleted file mode 100644 index ed784e2e14..0000000000 --- a/runtime/interpreter/mterp/arm64/op_float_to_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_float_to_int(): -% funopNarrow(instr="fcvtzs w0, s0", srcreg="s0", tgtreg="w0") diff --git a/runtime/interpreter/mterp/arm64/op_float_to_long.S b/runtime/interpreter/mterp/arm64/op_float_to_long.S deleted file mode 100644 index 14912493b5..0000000000 --- a/runtime/interpreter/mterp/arm64/op_float_to_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_float_to_long(): -% funopWider(instr="fcvtzs x0, s0", srcreg="s0", tgtreg="x0") diff --git a/runtime/interpreter/mterp/arm64/op_goto.S b/runtime/interpreter/mterp/arm64/op_goto.S deleted file mode 100644 index 722eec60a3..0000000000 --- a/runtime/interpreter/mterp/arm64/op_goto.S +++ /dev/null @@ -1,10 +0,0 @@ -%def op_goto(): - /* - * Unconditional branch, 8-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto +AA */ - sbfx wINST, wINST, #8, #8 // wINST<- ssssssAA (sign-extended) - b MterpCommonTakenBranchNoFlags diff --git a/runtime/interpreter/mterp/arm64/op_goto_16.S b/runtime/interpreter/mterp/arm64/op_goto_16.S deleted file mode 100644 index b5cfa71fce..0000000000 --- a/runtime/interpreter/mterp/arm64/op_goto_16.S +++ /dev/null @@ -1,10 +0,0 @@ -%def op_goto_16(): - /* - * Unconditional branch, 16-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto/16 +AAAA */ - FETCH_S wINST, 1 // wINST<- ssssAAAA (sign-extended) - b MterpCommonTakenBranchNoFlags diff --git a/runtime/interpreter/mterp/arm64/op_goto_32.S b/runtime/interpreter/mterp/arm64/op_goto_32.S deleted file mode 100644 index 3843ba2af3..0000000000 --- a/runtime/interpreter/mterp/arm64/op_goto_32.S +++ /dev/null @@ -1,17 +0,0 @@ -%def op_goto_32(): - /* - * Unconditional branch, 32-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - * - * Unlike most opcodes, this one is allowed to branch to itself, so - * our "backward branch" test must be "<=0" instead of "<0". Because - * we need the V bit set, we'll use an adds to convert from Dalvik - * offset to byte offset. - */ - /* goto/32 +AAAAAAAA */ - FETCH w0, 1 // w0<- aaaa (lo) - FETCH w1, 2 // w1<- AAAA (hi) - orr wINST, w0, w1, lsl #16 // wINST<- AAAAaaaa - b MterpCommonTakenBranchNoFlags diff --git a/runtime/interpreter/mterp/arm64/op_if_eq.S b/runtime/interpreter/mterp/arm64/op_if_eq.S deleted file mode 100644 index da58674fd4..0000000000 --- a/runtime/interpreter/mterp/arm64/op_if_eq.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_eq(): -% bincmp(condition="eq") diff --git a/runtime/interpreter/mterp/arm64/op_if_eqz.S b/runtime/interpreter/mterp/arm64/op_if_eqz.S deleted file mode 100644 index 8241db8287..0000000000 --- a/runtime/interpreter/mterp/arm64/op_if_eqz.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_eqz(): -% zcmp(compare="0", branch="cbz w2,") diff --git a/runtime/interpreter/mterp/arm64/op_if_ge.S b/runtime/interpreter/mterp/arm64/op_if_ge.S deleted file mode 100644 index 5b6ed2f994..0000000000 --- a/runtime/interpreter/mterp/arm64/op_if_ge.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_ge(): -% bincmp(condition="ge") diff --git a/runtime/interpreter/mterp/arm64/op_if_gez.S b/runtime/interpreter/mterp/arm64/op_if_gez.S deleted file mode 100644 index f7903b8b1d..0000000000 --- a/runtime/interpreter/mterp/arm64/op_if_gez.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_gez(): -% zcmp(compare="0", branch="tbz w2, #31,") diff --git a/runtime/interpreter/mterp/arm64/op_if_gt.S b/runtime/interpreter/mterp/arm64/op_if_gt.S deleted file mode 100644 index 201decff1a..0000000000 --- a/runtime/interpreter/mterp/arm64/op_if_gt.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_gt(): -% bincmp(condition="gt") diff --git a/runtime/interpreter/mterp/arm64/op_if_gtz.S b/runtime/interpreter/mterp/arm64/op_if_gtz.S deleted file mode 100644 index e0663a0206..0000000000 --- a/runtime/interpreter/mterp/arm64/op_if_gtz.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_gtz(): -% zcmp(branch="b.gt") diff --git a/runtime/interpreter/mterp/arm64/op_if_le.S b/runtime/interpreter/mterp/arm64/op_if_le.S deleted file mode 100644 index e6024f2b3e..0000000000 --- a/runtime/interpreter/mterp/arm64/op_if_le.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_le(): -% bincmp(condition="le") diff --git a/runtime/interpreter/mterp/arm64/op_if_lez.S b/runtime/interpreter/mterp/arm64/op_if_lez.S deleted file mode 100644 index 7ec4a9ee26..0000000000 --- a/runtime/interpreter/mterp/arm64/op_if_lez.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_lez(): -% zcmp(branch="b.le") diff --git a/runtime/interpreter/mterp/arm64/op_if_lt.S b/runtime/interpreter/mterp/arm64/op_if_lt.S deleted file mode 100644 index 4ef22fd798..0000000000 --- a/runtime/interpreter/mterp/arm64/op_if_lt.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_lt(): -% bincmp(condition="lt") diff --git a/runtime/interpreter/mterp/arm64/op_if_ltz.S b/runtime/interpreter/mterp/arm64/op_if_ltz.S deleted file mode 100644 index a9f04ee478..0000000000 --- a/runtime/interpreter/mterp/arm64/op_if_ltz.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_ltz(): -% zcmp(compare="0", branch="tbnz w2, #31,") diff --git a/runtime/interpreter/mterp/arm64/op_if_ne.S b/runtime/interpreter/mterp/arm64/op_if_ne.S deleted file mode 100644 index ec3a688b29..0000000000 --- a/runtime/interpreter/mterp/arm64/op_if_ne.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_ne(): -% bincmp(condition="ne") diff --git a/runtime/interpreter/mterp/arm64/op_if_nez.S b/runtime/interpreter/mterp/arm64/op_if_nez.S deleted file mode 100644 index c4bb3b3bdf..0000000000 --- a/runtime/interpreter/mterp/arm64/op_if_nez.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_nez(): -% zcmp(compare="0", branch="cbnz w2,") diff --git a/runtime/interpreter/mterp/arm64/op_iget.S b/runtime/interpreter/mterp/arm64/op_iget.S deleted file mode 100644 index d09edc0a17..0000000000 --- a/runtime/interpreter/mterp/arm64/op_iget.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget(is_object="0", helper="MterpIGetU32"): -% field(helper=helper) diff --git a/runtime/interpreter/mterp/arm64/op_iget_boolean.S b/runtime/interpreter/mterp/arm64/op_iget_boolean.S deleted file mode 100644 index cb8edeec77..0000000000 --- a/runtime/interpreter/mterp/arm64/op_iget_boolean.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_boolean(): -% op_iget(helper="MterpIGetU8") diff --git a/runtime/interpreter/mterp/arm64/op_iget_boolean_quick.S b/runtime/interpreter/mterp/arm64/op_iget_boolean_quick.S deleted file mode 100644 index 7ac9fce535..0000000000 --- a/runtime/interpreter/mterp/arm64/op_iget_boolean_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_boolean_quick(): -% op_iget_quick(load="ldrb") diff --git a/runtime/interpreter/mterp/arm64/op_iget_byte.S b/runtime/interpreter/mterp/arm64/op_iget_byte.S deleted file mode 100644 index 2b87fb16b5..0000000000 --- a/runtime/interpreter/mterp/arm64/op_iget_byte.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_byte(): -% op_iget(helper="MterpIGetI8") diff --git a/runtime/interpreter/mterp/arm64/op_iget_byte_quick.S b/runtime/interpreter/mterp/arm64/op_iget_byte_quick.S deleted file mode 100644 index bbccaffe94..0000000000 --- a/runtime/interpreter/mterp/arm64/op_iget_byte_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_byte_quick(): -% op_iget_quick(load="ldrsb") diff --git a/runtime/interpreter/mterp/arm64/op_iget_char.S b/runtime/interpreter/mterp/arm64/op_iget_char.S deleted file mode 100644 index 001bd03e2b..0000000000 --- a/runtime/interpreter/mterp/arm64/op_iget_char.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_char(): -% op_iget(helper="MterpIGetU16") diff --git a/runtime/interpreter/mterp/arm64/op_iget_char_quick.S b/runtime/interpreter/mterp/arm64/op_iget_char_quick.S deleted file mode 100644 index 71a9276a81..0000000000 --- a/runtime/interpreter/mterp/arm64/op_iget_char_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_char_quick(): -% op_iget_quick(load="ldrh") diff --git a/runtime/interpreter/mterp/arm64/op_iget_object.S b/runtime/interpreter/mterp/arm64/op_iget_object.S deleted file mode 100644 index 4e5f769547..0000000000 --- a/runtime/interpreter/mterp/arm64/op_iget_object.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_object(): -% op_iget(is_object="1", helper="MterpIGetObj") diff --git a/runtime/interpreter/mterp/arm64/op_iget_object_quick.S b/runtime/interpreter/mterp/arm64/op_iget_object_quick.S deleted file mode 100644 index f55b08f909..0000000000 --- a/runtime/interpreter/mterp/arm64/op_iget_object_quick.S +++ /dev/null @@ -1,16 +0,0 @@ -%def op_iget_object_quick(): - /* For: iget-object-quick */ - /* op vA, vB, offset//CCCC */ - lsr w2, wINST, #12 // w2<- B - FETCH w1, 1 // w1<- field byte offset - EXPORT_PC - GET_VREG w0, w2 // w0<- object we're operating on - bl artIGetObjectFromMterp // (obj, offset) - ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] - ubfx w2, wINST, #8, #4 // w2<- A - PREFETCH_INST 2 - cbnz w3, MterpPossibleException // bail out - SET_VREG_OBJECT w0, w2 // fp[A]<- w0 - ADVANCE 2 // advance rPC - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_iget_quick.S b/runtime/interpreter/mterp/arm64/op_iget_quick.S deleted file mode 100644 index 641bfab7df..0000000000 --- a/runtime/interpreter/mterp/arm64/op_iget_quick.S +++ /dev/null @@ -1,14 +0,0 @@ -%def op_iget_quick(load="ldr", extend=""): - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset//CCCC */ - lsr w2, wINST, #12 // w2<- B - FETCH w1, 1 // w1<- field byte offset - GET_VREG w3, w2 // w3<- object we're operating on - ubfx w2, wINST, #8, #4 // w2<- A - cbz w3, common_errNullObject // object was null - $load w0, [x3, x1] // w0<- obj.field - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - $extend - SET_VREG w0, w2 // fp[A]<- w0 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_iget_short.S b/runtime/interpreter/mterp/arm64/op_iget_short.S deleted file mode 100644 index a62c4d998f..0000000000 --- a/runtime/interpreter/mterp/arm64/op_iget_short.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_short(): -% op_iget(helper="MterpIGetI16") diff --git a/runtime/interpreter/mterp/arm64/op_iget_short_quick.S b/runtime/interpreter/mterp/arm64/op_iget_short_quick.S deleted file mode 100644 index 5dbdc4fa22..0000000000 --- a/runtime/interpreter/mterp/arm64/op_iget_short_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_short_quick(): -% op_iget_quick(load="ldrsh") diff --git a/runtime/interpreter/mterp/arm64/op_iget_wide.S b/runtime/interpreter/mterp/arm64/op_iget_wide.S deleted file mode 100644 index 9643cc3403..0000000000 --- a/runtime/interpreter/mterp/arm64/op_iget_wide.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_wide(): -% op_iget(helper="MterpIGetU64") diff --git a/runtime/interpreter/mterp/arm64/op_iget_wide_quick.S b/runtime/interpreter/mterp/arm64/op_iget_wide_quick.S deleted file mode 100644 index 9f7a61b4b2..0000000000 --- a/runtime/interpreter/mterp/arm64/op_iget_wide_quick.S +++ /dev/null @@ -1,12 +0,0 @@ -%def op_iget_wide_quick(): - /* iget-wide-quick vA, vB, offset//CCCC */ - lsr w2, wINST, #12 // w2<- B - FETCH w4, 1 // w4<- field byte offset - GET_VREG w3, w2 // w3<- object we're operating on - ubfx w2, wINST, #8, #4 // w2<- A - cbz w3, common_errNullObject // object was null - ldr x0, [x3, x4] // x0<- obj.field - FETCH_ADVANCE_INST 2 // advance rPC, load wINST - SET_VREG_WIDE x0, w2 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_instance_of.S b/runtime/interpreter/mterp/arm64/op_instance_of.S deleted file mode 100644 index 9c337d12fe..0000000000 --- a/runtime/interpreter/mterp/arm64/op_instance_of.S +++ /dev/null @@ -1,23 +0,0 @@ -%def op_instance_of(): - /* - * Check to see if an object reference is an instance of a class. - * - * Most common situation is a non-null object, being compared against - * an already-resolved class. - */ - /* instance-of vA, vB, class//CCCC */ - EXPORT_PC - FETCH w0, 1 // w0<- CCCC - lsr w1, wINST, #12 // w1<- B - VREG_INDEX_TO_ADDR x1, w1 // w1<- &object - ldr x2, [xFP, #OFF_FP_METHOD] // w2<- method - mov x3, xSELF // w3<- self - bl MterpInstanceOf // (index, &obj, method, self) - ldr x1, [xSELF, #THREAD_EXCEPTION_OFFSET] - ubfx w2, wINST, #8, #4 // w2<- A - PREFETCH_INST 2 - cbnz x1, MterpException - ADVANCE 2 // advance rPC - SET_VREG w0, w2 // vA<- w0 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_int_to_byte.S b/runtime/interpreter/mterp/arm64/op_int_to_byte.S deleted file mode 100644 index 8174978f48..0000000000 --- a/runtime/interpreter/mterp/arm64/op_int_to_byte.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_int_to_byte(): -% unop(instr="sxtb w0, w0") diff --git a/runtime/interpreter/mterp/arm64/op_int_to_char.S b/runtime/interpreter/mterp/arm64/op_int_to_char.S deleted file mode 100644 index bbf32394b7..0000000000 --- a/runtime/interpreter/mterp/arm64/op_int_to_char.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_int_to_char(): -% unop(instr="uxth w0, w0") diff --git a/runtime/interpreter/mterp/arm64/op_int_to_double.S b/runtime/interpreter/mterp/arm64/op_int_to_double.S deleted file mode 100644 index f2b9dc0c9f..0000000000 --- a/runtime/interpreter/mterp/arm64/op_int_to_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_int_to_double(): -% funopWider(instr="scvtf d0, w0", srcreg="w0", tgtreg="d0") diff --git a/runtime/interpreter/mterp/arm64/op_int_to_float.S b/runtime/interpreter/mterp/arm64/op_int_to_float.S deleted file mode 100644 index ffe873de81..0000000000 --- a/runtime/interpreter/mterp/arm64/op_int_to_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_int_to_float(): -% funopNarrow(instr="scvtf s0, w0", srcreg="w0", tgtreg="s0") diff --git a/runtime/interpreter/mterp/arm64/op_int_to_long.S b/runtime/interpreter/mterp/arm64/op_int_to_long.S deleted file mode 100644 index d7e5b463e6..0000000000 --- a/runtime/interpreter/mterp/arm64/op_int_to_long.S +++ /dev/null @@ -1,9 +0,0 @@ -%def op_int_to_long(): - /* int-to-long vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w4, wINST, #8, #4 // w4<- A - GET_VREG_S x0, w3 // x0<- sign_extend(fp[B]) - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG_WIDE x0, w4 // fp[A]<- x0 - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_int_to_short.S b/runtime/interpreter/mterp/arm64/op_int_to_short.S deleted file mode 100644 index 0c51c76dc5..0000000000 --- a/runtime/interpreter/mterp/arm64/op_int_to_short.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_int_to_short(): -% unop(instr="sxth w0, w0") diff --git a/runtime/interpreter/mterp/arm64/op_invoke_custom.S b/runtime/interpreter/mterp/arm64/op_invoke_custom.S deleted file mode 100644 index 4bba9ee524..0000000000 --- a/runtime/interpreter/mterp/arm64/op_invoke_custom.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_custom(): -% invoke(helper="MterpInvokeCustom") diff --git a/runtime/interpreter/mterp/arm64/op_invoke_custom_range.S b/runtime/interpreter/mterp/arm64/op_invoke_custom_range.S deleted file mode 100644 index 57e61af1fa..0000000000 --- a/runtime/interpreter/mterp/arm64/op_invoke_custom_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_custom_range(): -% invoke(helper="MterpInvokeCustomRange") diff --git a/runtime/interpreter/mterp/arm64/op_invoke_direct.S b/runtime/interpreter/mterp/arm64/op_invoke_direct.S deleted file mode 100644 index d3139cf39b..0000000000 --- a/runtime/interpreter/mterp/arm64/op_invoke_direct.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_direct(): -% invoke(helper="MterpInvokeDirect") diff --git a/runtime/interpreter/mterp/arm64/op_invoke_direct_range.S b/runtime/interpreter/mterp/arm64/op_invoke_direct_range.S deleted file mode 100644 index b4a161f48b..0000000000 --- a/runtime/interpreter/mterp/arm64/op_invoke_direct_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_direct_range(): -% invoke(helper="MterpInvokeDirectRange") diff --git a/runtime/interpreter/mterp/arm64/op_invoke_interface.S b/runtime/interpreter/mterp/arm64/op_invoke_interface.S deleted file mode 100644 index b064126253..0000000000 --- a/runtime/interpreter/mterp/arm64/op_invoke_interface.S +++ /dev/null @@ -1,9 +0,0 @@ -%def op_invoke_interface(): -% invoke(helper="MterpInvokeInterface") - /* - * Handle an interface method call. - * - * for: invoke-interface, invoke-interface/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ diff --git a/runtime/interpreter/mterp/arm64/op_invoke_interface_range.S b/runtime/interpreter/mterp/arm64/op_invoke_interface_range.S deleted file mode 100644 index 2989115377..0000000000 --- a/runtime/interpreter/mterp/arm64/op_invoke_interface_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_interface_range(): -% invoke(helper="MterpInvokeInterfaceRange") diff --git a/runtime/interpreter/mterp/arm64/op_invoke_polymorphic.S b/runtime/interpreter/mterp/arm64/op_invoke_polymorphic.S deleted file mode 100644 index ce61f5aa0e..0000000000 --- a/runtime/interpreter/mterp/arm64/op_invoke_polymorphic.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_polymorphic(): -% invoke_polymorphic(helper="MterpInvokePolymorphic") diff --git a/runtime/interpreter/mterp/arm64/op_invoke_polymorphic_range.S b/runtime/interpreter/mterp/arm64/op_invoke_polymorphic_range.S deleted file mode 100644 index 16731bdb40..0000000000 --- a/runtime/interpreter/mterp/arm64/op_invoke_polymorphic_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_polymorphic_range(): -% invoke_polymorphic(helper="MterpInvokePolymorphicRange") diff --git a/runtime/interpreter/mterp/arm64/op_invoke_static.S b/runtime/interpreter/mterp/arm64/op_invoke_static.S deleted file mode 100644 index 3e38d36a27..0000000000 --- a/runtime/interpreter/mterp/arm64/op_invoke_static.S +++ /dev/null @@ -1,3 +0,0 @@ -%def op_invoke_static(): -% invoke(helper="MterpInvokeStatic") - diff --git a/runtime/interpreter/mterp/arm64/op_invoke_static_range.S b/runtime/interpreter/mterp/arm64/op_invoke_static_range.S deleted file mode 100644 index e0a546c92b..0000000000 --- a/runtime/interpreter/mterp/arm64/op_invoke_static_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_static_range(): -% invoke(helper="MterpInvokeStaticRange") diff --git a/runtime/interpreter/mterp/arm64/op_invoke_super.S b/runtime/interpreter/mterp/arm64/op_invoke_super.S deleted file mode 100644 index 3c34c9942e..0000000000 --- a/runtime/interpreter/mterp/arm64/op_invoke_super.S +++ /dev/null @@ -1,9 +0,0 @@ -%def op_invoke_super(): -% invoke(helper="MterpInvokeSuper") - /* - * Handle a "super" method call. - * - * for: invoke-super, invoke-super/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ diff --git a/runtime/interpreter/mterp/arm64/op_invoke_super_range.S b/runtime/interpreter/mterp/arm64/op_invoke_super_range.S deleted file mode 100644 index caeafaa13c..0000000000 --- a/runtime/interpreter/mterp/arm64/op_invoke_super_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_super_range(): -% invoke(helper="MterpInvokeSuperRange") diff --git a/runtime/interpreter/mterp/arm64/op_invoke_virtual.S b/runtime/interpreter/mterp/arm64/op_invoke_virtual.S deleted file mode 100644 index 249177b813..0000000000 --- a/runtime/interpreter/mterp/arm64/op_invoke_virtual.S +++ /dev/null @@ -1,9 +0,0 @@ -%def op_invoke_virtual(): -% invoke(helper="MterpInvokeVirtual") - /* - * Handle a virtual method call. - * - * for: invoke-virtual, invoke-virtual/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ diff --git a/runtime/interpreter/mterp/arm64/op_invoke_virtual_quick.S b/runtime/interpreter/mterp/arm64/op_invoke_virtual_quick.S deleted file mode 100644 index ea72c171ec..0000000000 --- a/runtime/interpreter/mterp/arm64/op_invoke_virtual_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_virtual_quick(): -% invoke(helper="MterpInvokeVirtualQuick") diff --git a/runtime/interpreter/mterp/arm64/op_invoke_virtual_range.S b/runtime/interpreter/mterp/arm64/op_invoke_virtual_range.S deleted file mode 100644 index baa0779593..0000000000 --- a/runtime/interpreter/mterp/arm64/op_invoke_virtual_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_virtual_range(): -% invoke(helper="MterpInvokeVirtualRange") diff --git a/runtime/interpreter/mterp/arm64/op_invoke_virtual_range_quick.S b/runtime/interpreter/mterp/arm64/op_invoke_virtual_range_quick.S deleted file mode 100644 index 1d961a0781..0000000000 --- a/runtime/interpreter/mterp/arm64/op_invoke_virtual_range_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_virtual_range_quick(): -% invoke(helper="MterpInvokeVirtualQuickRange") diff --git a/runtime/interpreter/mterp/arm64/op_iput.S b/runtime/interpreter/mterp/arm64/op_iput.S deleted file mode 100644 index e5351baf55..0000000000 --- a/runtime/interpreter/mterp/arm64/op_iput.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput(is_object="0", helper="MterpIPutU32"): -% field(helper=helper) diff --git a/runtime/interpreter/mterp/arm64/op_iput_boolean.S b/runtime/interpreter/mterp/arm64/op_iput_boolean.S deleted file mode 100644 index 9eb849877b..0000000000 --- a/runtime/interpreter/mterp/arm64/op_iput_boolean.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_boolean(): -% op_iput(helper="MterpIPutU8") diff --git a/runtime/interpreter/mterp/arm64/op_iput_boolean_quick.S b/runtime/interpreter/mterp/arm64/op_iput_boolean_quick.S deleted file mode 100644 index fd077a7792..0000000000 --- a/runtime/interpreter/mterp/arm64/op_iput_boolean_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_boolean_quick(): -% op_iput_quick(store="strb") diff --git a/runtime/interpreter/mterp/arm64/op_iput_byte.S b/runtime/interpreter/mterp/arm64/op_iput_byte.S deleted file mode 100644 index 4b74f9fb0e..0000000000 --- a/runtime/interpreter/mterp/arm64/op_iput_byte.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_byte(): -% op_iput(helper="MterpIPutI8") diff --git a/runtime/interpreter/mterp/arm64/op_iput_byte_quick.S b/runtime/interpreter/mterp/arm64/op_iput_byte_quick.S deleted file mode 100644 index 30238cf354..0000000000 --- a/runtime/interpreter/mterp/arm64/op_iput_byte_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_byte_quick(): -% op_iput_quick(store="strb") diff --git a/runtime/interpreter/mterp/arm64/op_iput_char.S b/runtime/interpreter/mterp/arm64/op_iput_char.S deleted file mode 100644 index 64a249fc12..0000000000 --- a/runtime/interpreter/mterp/arm64/op_iput_char.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_char(): -% op_iput(helper="MterpIPutU16") diff --git a/runtime/interpreter/mterp/arm64/op_iput_char_quick.S b/runtime/interpreter/mterp/arm64/op_iput_char_quick.S deleted file mode 100644 index 0deff56503..0000000000 --- a/runtime/interpreter/mterp/arm64/op_iput_char_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_char_quick(): -% op_iput_quick(store="strh") diff --git a/runtime/interpreter/mterp/arm64/op_iput_object.S b/runtime/interpreter/mterp/arm64/op_iput_object.S deleted file mode 100644 index 131edd5dbd..0000000000 --- a/runtime/interpreter/mterp/arm64/op_iput_object.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_object(): -% op_iput(is_object="1", helper="MterpIPutObj") diff --git a/runtime/interpreter/mterp/arm64/op_iput_object_quick.S b/runtime/interpreter/mterp/arm64/op_iput_object_quick.S deleted file mode 100644 index 58c1026658..0000000000 --- a/runtime/interpreter/mterp/arm64/op_iput_object_quick.S +++ /dev/null @@ -1,10 +0,0 @@ -%def op_iput_object_quick(): - EXPORT_PC - add x0, xFP, #OFF_FP_SHADOWFRAME - mov x1, xPC - mov w2, wINST - bl MterpIputObjectQuick - cbz w0, MterpException - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_iput_quick.S b/runtime/interpreter/mterp/arm64/op_iput_quick.S deleted file mode 100644 index 1d9910826f..0000000000 --- a/runtime/interpreter/mterp/arm64/op_iput_quick.S +++ /dev/null @@ -1,13 +0,0 @@ -%def op_iput_quick(store="str"): - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset//CCCC */ - lsr w2, wINST, #12 // w2<- B - FETCH w1, 1 // w1<- field byte offset - GET_VREG w3, w2 // w3<- fp[B], the object pointer - ubfx w2, wINST, #8, #4 // w2<- A - cbz w3, common_errNullObject // object was null - GET_VREG w0, w2 // w0<- fp[A] - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - $store w0, [x3, x1] // obj.field<- w0 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_iput_short.S b/runtime/interpreter/mterp/arm64/op_iput_short.S deleted file mode 100644 index e631a3b259..0000000000 --- a/runtime/interpreter/mterp/arm64/op_iput_short.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_short(): -% op_iput(helper="MterpIPutI16") diff --git a/runtime/interpreter/mterp/arm64/op_iput_short_quick.S b/runtime/interpreter/mterp/arm64/op_iput_short_quick.S deleted file mode 100644 index 6a1b65194e..0000000000 --- a/runtime/interpreter/mterp/arm64/op_iput_short_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_short_quick(): -% op_iput_quick(store="strh") diff --git a/runtime/interpreter/mterp/arm64/op_iput_wide.S b/runtime/interpreter/mterp/arm64/op_iput_wide.S deleted file mode 100644 index 2f34fd39f9..0000000000 --- a/runtime/interpreter/mterp/arm64/op_iput_wide.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_wide(): -% op_iput(helper="MterpIPutU64") diff --git a/runtime/interpreter/mterp/arm64/op_iput_wide_quick.S b/runtime/interpreter/mterp/arm64/op_iput_wide_quick.S deleted file mode 100644 index a78918819b..0000000000 --- a/runtime/interpreter/mterp/arm64/op_iput_wide_quick.S +++ /dev/null @@ -1,12 +0,0 @@ -%def op_iput_wide_quick(): - /* iput-wide-quick vA, vB, offset//CCCC */ - lsr w2, wINST, #12 // w2<- B - FETCH w3, 1 // w3<- field byte offset - GET_VREG w2, w2 // w2<- fp[B], the object pointer - ubfx w0, wINST, #8, #4 // w0<- A - cbz w2, common_errNullObject // object was null - GET_VREG_WIDE x0, w0 // x0<- fp[A] - FETCH_ADVANCE_INST 2 // advance rPC, load wINST - str x0, [x2, x3] // obj.field<- x0 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_long_to_double.S b/runtime/interpreter/mterp/arm64/op_long_to_double.S deleted file mode 100644 index b1b7b4e694..0000000000 --- a/runtime/interpreter/mterp/arm64/op_long_to_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_long_to_double(): -% funopWide(instr="scvtf d0, x0", srcreg="x0", tgtreg="d0") diff --git a/runtime/interpreter/mterp/arm64/op_long_to_float.S b/runtime/interpreter/mterp/arm64/op_long_to_float.S deleted file mode 100644 index 424dea0964..0000000000 --- a/runtime/interpreter/mterp/arm64/op_long_to_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_long_to_float(): -% funopNarrower(instr="scvtf s0, x0", srcreg="x0", tgtreg="s0") diff --git a/runtime/interpreter/mterp/arm64/op_long_to_int.S b/runtime/interpreter/mterp/arm64/op_long_to_int.S deleted file mode 100644 index eacb8f59ec..0000000000 --- a/runtime/interpreter/mterp/arm64/op_long_to_int.S +++ /dev/null @@ -1,3 +0,0 @@ -%def op_long_to_int(): -/* we ignore the high word, making this equivalent to a 32-bit reg move */ -% op_move() diff --git a/runtime/interpreter/mterp/arm64/op_monitor_enter.S b/runtime/interpreter/mterp/arm64/op_monitor_enter.S deleted file mode 100644 index 9d167a25da..0000000000 --- a/runtime/interpreter/mterp/arm64/op_monitor_enter.S +++ /dev/null @@ -1,14 +0,0 @@ -%def op_monitor_enter(): - /* - * Synchronize on an object. - */ - /* monitor-enter vAA */ - EXPORT_PC - lsr w2, wINST, #8 // w2<- AA - GET_VREG w0, w2 // w0<- vAA (object) - mov x1, xSELF // w1<- self - bl artLockObjectFromCode - cbnz w0, MterpException - FETCH_ADVANCE_INST 1 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_monitor_exit.S b/runtime/interpreter/mterp/arm64/op_monitor_exit.S deleted file mode 100644 index 985769f15b..0000000000 --- a/runtime/interpreter/mterp/arm64/op_monitor_exit.S +++ /dev/null @@ -1,18 +0,0 @@ -%def op_monitor_exit(): - /* - * Unlock an object. - * - * Exceptions that occur when unlocking a monitor need to appear as - * if they happened at the following instruction. See the Dalvik - * instruction spec. - */ - /* monitor-exit vAA */ - EXPORT_PC - lsr w2, wINST, #8 // w2<- AA - GET_VREG w0, w2 // w0<- vAA (object) - mov x1, xSELF // w0<- self - bl artUnlockObjectFromCode // w0<- success for unlock(self, obj) - cbnz w0, MterpException - FETCH_ADVANCE_INST 1 // before throw: advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_move.S b/runtime/interpreter/mterp/arm64/op_move.S deleted file mode 100644 index d3324f1158..0000000000 --- a/runtime/interpreter/mterp/arm64/op_move.S +++ /dev/null @@ -1,14 +0,0 @@ -%def op_move(is_object="0"): - /* for move, move-object, long-to-int */ - /* op vA, vB */ - lsr w1, wINST, #12 // x1<- B from 15:12 - ubfx w0, wINST, #8, #4 // x0<- A from 11:8 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - GET_VREG w2, w1 // x2<- fp[B] - GET_INST_OPCODE ip // ip<- opcode from wINST - .if $is_object - SET_VREG_OBJECT w2, w0 // fp[A]<- x2 - .else - SET_VREG w2, w0 // fp[A]<- x2 - .endif - GOTO_OPCODE ip // execute next instruction diff --git a/runtime/interpreter/mterp/arm64/op_move_16.S b/runtime/interpreter/mterp/arm64/op_move_16.S deleted file mode 100644 index 0dc862d5df..0000000000 --- a/runtime/interpreter/mterp/arm64/op_move_16.S +++ /dev/null @@ -1,14 +0,0 @@ -%def op_move_16(is_object="0"): - /* for: move/16, move-object/16 */ - /* op vAAAA, vBBBB */ - FETCH w1, 2 // w1<- BBBB - FETCH w0, 1 // w0<- AAAA - FETCH_ADVANCE_INST 3 // advance xPC, load xINST - GET_VREG w2, w1 // w2<- fp[BBBB] - GET_INST_OPCODE ip // extract opcode from xINST - .if $is_object - SET_VREG_OBJECT w2, w0 // fp[AAAA]<- w2 - .else - SET_VREG w2, w0 // fp[AAAA]<- w2 - .endif - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_move_exception.S b/runtime/interpreter/mterp/arm64/op_move_exception.S deleted file mode 100644 index 2ae5ca898c..0000000000 --- a/runtime/interpreter/mterp/arm64/op_move_exception.S +++ /dev/null @@ -1,10 +0,0 @@ -%def op_move_exception(): - /* move-exception vAA */ - lsr w2, wINST, #8 // w2<- AA - ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] - mov x1, #0 // w1<- 0 - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - SET_VREG_OBJECT w3, w2 // fp[AA]<- exception obj - GET_INST_OPCODE ip // extract opcode from rINST - str x1, [xSELF, #THREAD_EXCEPTION_OFFSET] // clear exception - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_move_from16.S b/runtime/interpreter/mterp/arm64/op_move_from16.S deleted file mode 100644 index 5c7344504d..0000000000 --- a/runtime/interpreter/mterp/arm64/op_move_from16.S +++ /dev/null @@ -1,14 +0,0 @@ -%def op_move_from16(is_object="0"): - /* for: move/from16, move-object/from16 */ - /* op vAA, vBBBB */ - FETCH w1, 1 // r1<- BBBB - lsr w0, wINST, #8 // r0<- AA - FETCH_ADVANCE_INST 2 // advance rPC, load wINST - GET_VREG w2, w1 // r2<- fp[BBBB] - GET_INST_OPCODE ip // extract opcode from wINST - .if $is_object - SET_VREG_OBJECT w2, w0 // fp[AA]<- r2 - .else - SET_VREG w2, w0 // fp[AA]<- r2 - .endif - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_move_object.S b/runtime/interpreter/mterp/arm64/op_move_object.S deleted file mode 100644 index dbb4d59710..0000000000 --- a/runtime/interpreter/mterp/arm64/op_move_object.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_move_object(): -% op_move(is_object="1") diff --git a/runtime/interpreter/mterp/arm64/op_move_object_16.S b/runtime/interpreter/mterp/arm64/op_move_object_16.S deleted file mode 100644 index 40120379d5..0000000000 --- a/runtime/interpreter/mterp/arm64/op_move_object_16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_move_object_16(): -% op_move_16(is_object="1") diff --git a/runtime/interpreter/mterp/arm64/op_move_object_from16.S b/runtime/interpreter/mterp/arm64/op_move_object_from16.S deleted file mode 100644 index c82698e81e..0000000000 --- a/runtime/interpreter/mterp/arm64/op_move_object_from16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_move_object_from16(): -% op_move_from16(is_object="1") diff --git a/runtime/interpreter/mterp/arm64/op_move_result.S b/runtime/interpreter/mterp/arm64/op_move_result.S deleted file mode 100644 index 9c048f05a1..0000000000 --- a/runtime/interpreter/mterp/arm64/op_move_result.S +++ /dev/null @@ -1,14 +0,0 @@ -%def op_move_result(is_object="0"): - /* for: move-result, move-result-object */ - /* op vAA */ - lsr w2, wINST, #8 // r2<- AA - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - ldr x0, [xFP, #OFF_FP_RESULT_REGISTER] // get pointer to result JType. - ldr w0, [x0] // r0 <- result.i. - GET_INST_OPCODE ip // extract opcode from wINST - .if $is_object - SET_VREG_OBJECT w0, w2, w1 // fp[AA]<- r0 - .else - SET_VREG w0, w2 // fp[AA]<- r0 - .endif - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_move_result_object.S b/runtime/interpreter/mterp/arm64/op_move_result_object.S deleted file mode 100644 index 87aea2646a..0000000000 --- a/runtime/interpreter/mterp/arm64/op_move_result_object.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_move_result_object(): -% op_move_result(is_object="1") diff --git a/runtime/interpreter/mterp/arm64/op_move_result_wide.S b/runtime/interpreter/mterp/arm64/op_move_result_wide.S deleted file mode 100644 index 96347ea2d0..0000000000 --- a/runtime/interpreter/mterp/arm64/op_move_result_wide.S +++ /dev/null @@ -1,10 +0,0 @@ -%def op_move_result_wide(): - /* for: move-result-wide */ - /* op vAA */ - lsr w2, wINST, #8 // r2<- AA - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - ldr x0, [xFP, #OFF_FP_RESULT_REGISTER] // get pointer to result JType. - ldr x0, [x0] // r0 <- result.i. - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG_WIDE x0, x2 // fp[AA]<- r0 - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_move_wide.S b/runtime/interpreter/mterp/arm64/op_move_wide.S deleted file mode 100644 index 4576987b90..0000000000 --- a/runtime/interpreter/mterp/arm64/op_move_wide.S +++ /dev/null @@ -1,10 +0,0 @@ -%def op_move_wide(): - /* move-wide vA, vB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - lsr w3, wINST, #12 // w3<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG_WIDE x3, w3 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG_WIDE x3, w2 - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_move_wide_16.S b/runtime/interpreter/mterp/arm64/op_move_wide_16.S deleted file mode 100644 index 09f7a61c55..0000000000 --- a/runtime/interpreter/mterp/arm64/op_move_wide_16.S +++ /dev/null @@ -1,10 +0,0 @@ -%def op_move_wide_16(): - /* move-wide/16 vAAAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - FETCH w3, 2 // w3<- BBBB - FETCH w2, 1 // w2<- AAAA - GET_VREG_WIDE x3, w3 - FETCH_ADVANCE_INST 3 // advance rPC, load rINST - SET_VREG_WIDE x3, w2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_move_wide_from16.S b/runtime/interpreter/mterp/arm64/op_move_wide_from16.S deleted file mode 100644 index 6afc20a8c0..0000000000 --- a/runtime/interpreter/mterp/arm64/op_move_wide_from16.S +++ /dev/null @@ -1,10 +0,0 @@ -%def op_move_wide_from16(): - /* move-wide/from16 vAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - FETCH w3, 1 // w3<- BBBB - lsr w2, wINST, #8 // w2<- AA - GET_VREG_WIDE x3, w3 - FETCH_ADVANCE_INST 2 // advance rPC, load wINST - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG_WIDE x3, w2 - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_mul_double.S b/runtime/interpreter/mterp/arm64/op_mul_double.S deleted file mode 100644 index 30ca309997..0000000000 --- a/runtime/interpreter/mterp/arm64/op_mul_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_mul_double(): -% binopWide(instr="fmul d0, d1, d2", result="d0", r1="d1", r2="d2") diff --git a/runtime/interpreter/mterp/arm64/op_mul_double_2addr.S b/runtime/interpreter/mterp/arm64/op_mul_double_2addr.S deleted file mode 100644 index dedecb5be8..0000000000 --- a/runtime/interpreter/mterp/arm64/op_mul_double_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_mul_double_2addr(): -% binopWide2addr(instr="fmul d0, d0, d1", r0="d0", r1="d1") diff --git a/runtime/interpreter/mterp/arm64/op_mul_float.S b/runtime/interpreter/mterp/arm64/op_mul_float.S deleted file mode 100644 index 3bbbe7305b..0000000000 --- a/runtime/interpreter/mterp/arm64/op_mul_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_mul_float(): -% fbinop(instr="fmul s0, s0, s1") diff --git a/runtime/interpreter/mterp/arm64/op_mul_float_2addr.S b/runtime/interpreter/mterp/arm64/op_mul_float_2addr.S deleted file mode 100644 index 035a1fb662..0000000000 --- a/runtime/interpreter/mterp/arm64/op_mul_float_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_mul_float_2addr(): -% fbinop2addr(instr="fmul s2, s0, s1") diff --git a/runtime/interpreter/mterp/arm64/op_mul_int.S b/runtime/interpreter/mterp/arm64/op_mul_int.S deleted file mode 100644 index 267623d1f5..0000000000 --- a/runtime/interpreter/mterp/arm64/op_mul_int.S +++ /dev/null @@ -1,3 +0,0 @@ -%def op_mul_int(): -/* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */ -% binop(instr="mul w0, w1, w0") diff --git a/runtime/interpreter/mterp/arm64/op_mul_int_2addr.S b/runtime/interpreter/mterp/arm64/op_mul_int_2addr.S deleted file mode 100644 index c0f533a0c1..0000000000 --- a/runtime/interpreter/mterp/arm64/op_mul_int_2addr.S +++ /dev/null @@ -1,3 +0,0 @@ -%def op_mul_int_2addr(): -/* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */ -% binop2addr(instr="mul w0, w1, w0") diff --git a/runtime/interpreter/mterp/arm64/op_mul_int_lit16.S b/runtime/interpreter/mterp/arm64/op_mul_int_lit16.S deleted file mode 100644 index d309c86299..0000000000 --- a/runtime/interpreter/mterp/arm64/op_mul_int_lit16.S +++ /dev/null @@ -1,3 +0,0 @@ -%def op_mul_int_lit16(): -/* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */ -% binopLit16(instr="mul w0, w1, w0") diff --git a/runtime/interpreter/mterp/arm64/op_mul_int_lit8.S b/runtime/interpreter/mterp/arm64/op_mul_int_lit8.S deleted file mode 100644 index b3368416d1..0000000000 --- a/runtime/interpreter/mterp/arm64/op_mul_int_lit8.S +++ /dev/null @@ -1,3 +0,0 @@ -%def op_mul_int_lit8(): -/* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */ -% binopLit8(instr="mul w0, w1, w0") diff --git a/runtime/interpreter/mterp/arm64/op_mul_long.S b/runtime/interpreter/mterp/arm64/op_mul_long.S deleted file mode 100644 index 5056c0e4c1..0000000000 --- a/runtime/interpreter/mterp/arm64/op_mul_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_mul_long(): -% binopWide(instr="mul x0, x1, x2") diff --git a/runtime/interpreter/mterp/arm64/op_mul_long_2addr.S b/runtime/interpreter/mterp/arm64/op_mul_long_2addr.S deleted file mode 100644 index e69d40aadf..0000000000 --- a/runtime/interpreter/mterp/arm64/op_mul_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_mul_long_2addr(): -% binopWide2addr(instr="mul x0, x0, x1") diff --git a/runtime/interpreter/mterp/arm64/op_neg_double.S b/runtime/interpreter/mterp/arm64/op_neg_double.S deleted file mode 100644 index a56eff5493..0000000000 --- a/runtime/interpreter/mterp/arm64/op_neg_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_neg_double(): -% unopWide(instr="eor x0, x0, #0x8000000000000000") diff --git a/runtime/interpreter/mterp/arm64/op_neg_float.S b/runtime/interpreter/mterp/arm64/op_neg_float.S deleted file mode 100644 index 1366168def..0000000000 --- a/runtime/interpreter/mterp/arm64/op_neg_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_neg_float(): -% unop(instr="eor w0, w0, #0x80000000") diff --git a/runtime/interpreter/mterp/arm64/op_neg_int.S b/runtime/interpreter/mterp/arm64/op_neg_int.S deleted file mode 100644 index be56dd2aca..0000000000 --- a/runtime/interpreter/mterp/arm64/op_neg_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_neg_int(): -% unop(instr="sub w0, wzr, w0") diff --git a/runtime/interpreter/mterp/arm64/op_neg_long.S b/runtime/interpreter/mterp/arm64/op_neg_long.S deleted file mode 100644 index eb2882c9a7..0000000000 --- a/runtime/interpreter/mterp/arm64/op_neg_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_neg_long(): -% unopWide(instr="sub x0, xzr, x0") diff --git a/runtime/interpreter/mterp/arm64/op_new_array.S b/runtime/interpreter/mterp/arm64/op_new_array.S deleted file mode 100644 index 34729a7aeb..0000000000 --- a/runtime/interpreter/mterp/arm64/op_new_array.S +++ /dev/null @@ -1,19 +0,0 @@ -%def op_new_array(): - /* - * Allocate an array of objects, specified with the array class - * and a count. - * - * The verifier guarantees that this is an array class, so we don't - * check for it here. - */ - /* new-array vA, vB, class//CCCC */ - EXPORT_PC - add x0, xFP, #OFF_FP_SHADOWFRAME - mov x1, xPC - mov w2, wINST - mov x3, xSELF - bl MterpNewArray - cbz w0, MterpPossibleException - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_new_instance.S b/runtime/interpreter/mterp/arm64/op_new_instance.S deleted file mode 100644 index beb1f6e2e0..0000000000 --- a/runtime/interpreter/mterp/arm64/op_new_instance.S +++ /dev/null @@ -1,14 +0,0 @@ -%def op_new_instance(): - /* - * Create a new instance of a class. - */ - /* new-instance vAA, class//BBBB */ - EXPORT_PC - add x0, xFP, #OFF_FP_SHADOWFRAME - mov x1, xSELF - mov w2, wINST - bl MterpNewInstance // (shadow_frame, self, inst_data) - cbz w0, MterpPossibleException - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_nop.S b/runtime/interpreter/mterp/arm64/op_nop.S deleted file mode 100644 index 9702c5cd48..0000000000 --- a/runtime/interpreter/mterp/arm64/op_nop.S +++ /dev/null @@ -1,4 +0,0 @@ -%def op_nop(): - FETCH_ADVANCE_INST 1 // advance to next instr, load rINST - GET_INST_OPCODE ip // ip<- opcode from rINST - GOTO_OPCODE ip // execute it diff --git a/runtime/interpreter/mterp/arm64/op_not_int.S b/runtime/interpreter/mterp/arm64/op_not_int.S deleted file mode 100644 index d2fc205318..0000000000 --- a/runtime/interpreter/mterp/arm64/op_not_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_not_int(): -% unop(instr="mvn w0, w0") diff --git a/runtime/interpreter/mterp/arm64/op_not_long.S b/runtime/interpreter/mterp/arm64/op_not_long.S deleted file mode 100644 index 014a60dc40..0000000000 --- a/runtime/interpreter/mterp/arm64/op_not_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_not_long(): -% unopWide(instr="mvn x0, x0") diff --git a/runtime/interpreter/mterp/arm64/op_or_int.S b/runtime/interpreter/mterp/arm64/op_or_int.S deleted file mode 100644 index 8041c6d805..0000000000 --- a/runtime/interpreter/mterp/arm64/op_or_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_or_int(): -% binop(instr="orr w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_or_int_2addr.S b/runtime/interpreter/mterp/arm64/op_or_int_2addr.S deleted file mode 100644 index 918c5233ee..0000000000 --- a/runtime/interpreter/mterp/arm64/op_or_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_or_int_2addr(): -% binop2addr(instr="orr w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_or_int_lit16.S b/runtime/interpreter/mterp/arm64/op_or_int_lit16.S deleted file mode 100644 index dda068bbbf..0000000000 --- a/runtime/interpreter/mterp/arm64/op_or_int_lit16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_or_int_lit16(): -% binopLit16(instr="orr w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_or_int_lit8.S b/runtime/interpreter/mterp/arm64/op_or_int_lit8.S deleted file mode 100644 index 0fe6122e79..0000000000 --- a/runtime/interpreter/mterp/arm64/op_or_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_or_int_lit8(): -% binopLit8(extract="", instr="orr w0, w0, w3, asr #8") diff --git a/runtime/interpreter/mterp/arm64/op_or_long.S b/runtime/interpreter/mterp/arm64/op_or_long.S deleted file mode 100644 index f434d3fae9..0000000000 --- a/runtime/interpreter/mterp/arm64/op_or_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_or_long(): -% binopWide(instr="orr x0, x1, x2") diff --git a/runtime/interpreter/mterp/arm64/op_or_long_2addr.S b/runtime/interpreter/mterp/arm64/op_or_long_2addr.S deleted file mode 100644 index 4186ce9ef9..0000000000 --- a/runtime/interpreter/mterp/arm64/op_or_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_or_long_2addr(): -% binopWide2addr(instr="orr x0, x0, x1") diff --git a/runtime/interpreter/mterp/arm64/op_packed_switch.S b/runtime/interpreter/mterp/arm64/op_packed_switch.S deleted file mode 100644 index 9e4eb9bd37..0000000000 --- a/runtime/interpreter/mterp/arm64/op_packed_switch.S +++ /dev/null @@ -1,20 +0,0 @@ -%def op_packed_switch(func="MterpDoPackedSwitch"): - /* - * Handle a packed-switch or sparse-switch instruction. In both cases - * we decode it and hand it off to a helper function. - * - * We don't really expect backward branches in a switch statement, but - * they're perfectly legal, so we check for them here. - * - * for: packed-switch, sparse-switch - */ - /* op vAA, +BBBB */ - FETCH w0, 1 // x0<- 000000000000bbbb (lo) - FETCH_S x1, 2 // x1<- ssssssssssssBBBB (hi) - lsr w3, wINST, #8 // w3<- AA - orr x0, x0, x1, lsl #16 // x0<- ssssssssBBBBbbbb - GET_VREG w1, w3 // w1<- vAA - add x0, xPC, x0, lsl #1 // x0<- PC + ssssssssBBBBbbbb*2 - bl $func // w0<- code-unit branch offset - sxtw xINST, w0 - b MterpCommonTakenBranchNoFlags diff --git a/runtime/interpreter/mterp/arm64/op_rem_double.S b/runtime/interpreter/mterp/arm64/op_rem_double.S deleted file mode 100644 index 3d43467e63..0000000000 --- a/runtime/interpreter/mterp/arm64/op_rem_double.S +++ /dev/null @@ -1,14 +0,0 @@ -%def op_rem_double(): - /* rem vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w2, w0, #8 // w2<- CC - and w1, w0, #255 // w1<- BB - GET_VREG_WIDE d1, w2 // d1<- vCC - GET_VREG_WIDE d0, w1 // d0<- vBB - bl fmod - lsr w4, wINST, #8 // w4<- AA - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE d0, w4 // vAA<- result - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ diff --git a/runtime/interpreter/mterp/arm64/op_rem_double_2addr.S b/runtime/interpreter/mterp/arm64/op_rem_double_2addr.S deleted file mode 100644 index 179886d46b..0000000000 --- a/runtime/interpreter/mterp/arm64/op_rem_double_2addr.S +++ /dev/null @@ -1,13 +0,0 @@ -%def op_rem_double_2addr(): - /* rem vA, vB */ - lsr w1, wINST, #12 // w1<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG_WIDE d1, w1 // d1<- vB - GET_VREG_WIDE d0, w2 // d0<- vA - bl fmod - ubfx w2, wINST, #8, #4 // w2<- A (need to reload - killed across call) - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE d0, w2 // vAA<- result - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ diff --git a/runtime/interpreter/mterp/arm64/op_rem_float.S b/runtime/interpreter/mterp/arm64/op_rem_float.S deleted file mode 100644 index 29241e5722..0000000000 --- a/runtime/interpreter/mterp/arm64/op_rem_float.S +++ /dev/null @@ -1,3 +0,0 @@ -%def op_rem_float(): -/* EABI doesn't define a float remainder function, but libm does */ -% fbinop(instr="bl fmodf") diff --git a/runtime/interpreter/mterp/arm64/op_rem_float_2addr.S b/runtime/interpreter/mterp/arm64/op_rem_float_2addr.S deleted file mode 100644 index 49bf8ea320..0000000000 --- a/runtime/interpreter/mterp/arm64/op_rem_float_2addr.S +++ /dev/null @@ -1,12 +0,0 @@ -%def op_rem_float_2addr(): - /* rem vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG s1, w3 - GET_VREG s0, w9 - bl fmodf - ubfx w9, wINST, #8, #4 // w9<- A - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG s0, w9 - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_rem_int.S b/runtime/interpreter/mterp/arm64/op_rem_int.S deleted file mode 100644 index 6f2f999f3f..0000000000 --- a/runtime/interpreter/mterp/arm64/op_rem_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_rem_int(): -% binop(preinstr="sdiv w2, w0, w1", instr="msub w0, w2, w1, w0", chkzero="1") diff --git a/runtime/interpreter/mterp/arm64/op_rem_int_2addr.S b/runtime/interpreter/mterp/arm64/op_rem_int_2addr.S deleted file mode 100644 index dc46b2feb4..0000000000 --- a/runtime/interpreter/mterp/arm64/op_rem_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_rem_int_2addr(): -% binop2addr(preinstr="sdiv w2, w0, w1", instr="msub w0, w2, w1, w0", chkzero="1") diff --git a/runtime/interpreter/mterp/arm64/op_rem_int_lit16.S b/runtime/interpreter/mterp/arm64/op_rem_int_lit16.S deleted file mode 100644 index 75be3343ba..0000000000 --- a/runtime/interpreter/mterp/arm64/op_rem_int_lit16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_rem_int_lit16(): -% binopLit16(preinstr="sdiv w3, w0, w1", instr="msub w0, w3, w1, w0", chkzero="1") diff --git a/runtime/interpreter/mterp/arm64/op_rem_int_lit8.S b/runtime/interpreter/mterp/arm64/op_rem_int_lit8.S deleted file mode 100644 index c5fef4be01..0000000000 --- a/runtime/interpreter/mterp/arm64/op_rem_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_rem_int_lit8(): -% binopLit8(preinstr="sdiv w3, w0, w1", instr="msub w0, w3, w1, w0", chkzero="1") diff --git a/runtime/interpreter/mterp/arm64/op_rem_long.S b/runtime/interpreter/mterp/arm64/op_rem_long.S deleted file mode 100644 index 31dd6bec52..0000000000 --- a/runtime/interpreter/mterp/arm64/op_rem_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_rem_long(): -% binopWide(preinstr="sdiv x3, x1, x2", instr="msub x0, x3, x2, x1", chkzero="1") diff --git a/runtime/interpreter/mterp/arm64/op_rem_long_2addr.S b/runtime/interpreter/mterp/arm64/op_rem_long_2addr.S deleted file mode 100644 index b30ef674b3..0000000000 --- a/runtime/interpreter/mterp/arm64/op_rem_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_rem_long_2addr(): -% binopWide2addr(preinstr="sdiv x3, x0, x1", instr="msub x0, x3, x1, x0", chkzero="1") diff --git a/runtime/interpreter/mterp/arm64/op_return.S b/runtime/interpreter/mterp/arm64/op_return.S deleted file mode 100644 index eedae64d4e..0000000000 --- a/runtime/interpreter/mterp/arm64/op_return.S +++ /dev/null @@ -1,20 +0,0 @@ -%def op_return(): - /* - * Return a 32-bit value. - * - * for: return, return-object - */ - /* op vAA */ - .extern MterpThreadFenceForConstructor - bl MterpThreadFenceForConstructor - ldr w7, [xSELF, #THREAD_FLAGS_OFFSET] - mov x0, xSELF - ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - b.ne .L${opcode}_check -.L${opcode}_return: - lsr w2, wINST, #8 // r2<- AA - GET_VREG w0, w2 // r0<- vAA - b MterpReturn -.L${opcode}_check: - bl MterpSuspendCheck // (self) - b .L${opcode}_return diff --git a/runtime/interpreter/mterp/arm64/op_return_object.S b/runtime/interpreter/mterp/arm64/op_return_object.S deleted file mode 100644 index 2eeec0b948..0000000000 --- a/runtime/interpreter/mterp/arm64/op_return_object.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_return_object(): -% op_return() diff --git a/runtime/interpreter/mterp/arm64/op_return_void.S b/runtime/interpreter/mterp/arm64/op_return_void.S deleted file mode 100644 index 6962bb21d0..0000000000 --- a/runtime/interpreter/mterp/arm64/op_return_void.S +++ /dev/null @@ -1,13 +0,0 @@ -%def op_return_void(): - .extern MterpThreadFenceForConstructor - bl MterpThreadFenceForConstructor - ldr w7, [xSELF, #THREAD_FLAGS_OFFSET] - mov x0, xSELF - ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - b.ne .L${opcode}_check -.L${opcode}_return: - mov x0, #0 - b MterpReturn -.L${opcode}_check: - bl MterpSuspendCheck // (self) - b .L${opcode}_return diff --git a/runtime/interpreter/mterp/arm64/op_return_void_no_barrier.S b/runtime/interpreter/mterp/arm64/op_return_void_no_barrier.S deleted file mode 100644 index 8d872d1faa..0000000000 --- a/runtime/interpreter/mterp/arm64/op_return_void_no_barrier.S +++ /dev/null @@ -1,11 +0,0 @@ -%def op_return_void_no_barrier(): - ldr w7, [xSELF, #THREAD_FLAGS_OFFSET] - mov x0, xSELF - ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - b.ne .L${opcode}_check -.L${opcode}_return: - mov x0, #0 - b MterpReturn -.L${opcode}_check: - bl MterpSuspendCheck // (self) - b .L${opcode}_return diff --git a/runtime/interpreter/mterp/arm64/op_return_wide.S b/runtime/interpreter/mterp/arm64/op_return_wide.S deleted file mode 100644 index 5d31c6a5ab..0000000000 --- a/runtime/interpreter/mterp/arm64/op_return_wide.S +++ /dev/null @@ -1,19 +0,0 @@ -%def op_return_wide(): - /* - * Return a 64-bit value. - */ - /* return-wide vAA */ - /* op vAA */ - .extern MterpThreadFenceForConstructor - bl MterpThreadFenceForConstructor - ldr w7, [xSELF, #THREAD_FLAGS_OFFSET] - mov x0, xSELF - ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - b.ne .L${opcode}_check -.L${opcode}_return: - lsr w2, wINST, #8 // w2<- AA - GET_VREG_WIDE x0, w2 // x0<- vAA - b MterpReturn -.L${opcode}_check: - bl MterpSuspendCheck // (self) - b .L${opcode}_return diff --git a/runtime/interpreter/mterp/arm64/op_rsub_int.S b/runtime/interpreter/mterp/arm64/op_rsub_int.S deleted file mode 100644 index dc2342d018..0000000000 --- a/runtime/interpreter/mterp/arm64/op_rsub_int.S +++ /dev/null @@ -1,3 +0,0 @@ -%def op_rsub_int(): -/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ -% binopLit16(instr="sub w0, w1, w0") diff --git a/runtime/interpreter/mterp/arm64/op_rsub_int_lit8.S b/runtime/interpreter/mterp/arm64/op_rsub_int_lit8.S deleted file mode 100644 index 51a48fb9bd..0000000000 --- a/runtime/interpreter/mterp/arm64/op_rsub_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_rsub_int_lit8(): -% binopLit8(instr="sub w0, w1, w0") diff --git a/runtime/interpreter/mterp/arm64/op_sget.S b/runtime/interpreter/mterp/arm64/op_sget.S deleted file mode 100644 index 8a6a66ab60..0000000000 --- a/runtime/interpreter/mterp/arm64/op_sget.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sget(is_object="0", helper="MterpSGetU32"): -% field(helper=helper) diff --git a/runtime/interpreter/mterp/arm64/op_sget_boolean.S b/runtime/interpreter/mterp/arm64/op_sget_boolean.S deleted file mode 100644 index d9c12c9b28..0000000000 --- a/runtime/interpreter/mterp/arm64/op_sget_boolean.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sget_boolean(): -% op_sget(helper="MterpSGetU8") diff --git a/runtime/interpreter/mterp/arm64/op_sget_byte.S b/runtime/interpreter/mterp/arm64/op_sget_byte.S deleted file mode 100644 index 37c6879cd4..0000000000 --- a/runtime/interpreter/mterp/arm64/op_sget_byte.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sget_byte(): -% op_sget(helper="MterpSGetI8") diff --git a/runtime/interpreter/mterp/arm64/op_sget_char.S b/runtime/interpreter/mterp/arm64/op_sget_char.S deleted file mode 100644 index 003bcd1683..0000000000 --- a/runtime/interpreter/mterp/arm64/op_sget_char.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sget_char(): -% op_sget(helper="MterpSGetU16") diff --git a/runtime/interpreter/mterp/arm64/op_sget_object.S b/runtime/interpreter/mterp/arm64/op_sget_object.S deleted file mode 100644 index 7cf3597f44..0000000000 --- a/runtime/interpreter/mterp/arm64/op_sget_object.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sget_object(): -% op_sget(is_object="1", helper="MterpSGetObj") diff --git a/runtime/interpreter/mterp/arm64/op_sget_short.S b/runtime/interpreter/mterp/arm64/op_sget_short.S deleted file mode 100644 index afacb578d9..0000000000 --- a/runtime/interpreter/mterp/arm64/op_sget_short.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sget_short(): -% op_sget(helper="MterpSGetI16") diff --git a/runtime/interpreter/mterp/arm64/op_sget_wide.S b/runtime/interpreter/mterp/arm64/op_sget_wide.S deleted file mode 100644 index fff2be6945..0000000000 --- a/runtime/interpreter/mterp/arm64/op_sget_wide.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sget_wide(): -% op_sget(helper="MterpSGetU64") diff --git a/runtime/interpreter/mterp/arm64/op_shl_int.S b/runtime/interpreter/mterp/arm64/op_shl_int.S deleted file mode 100644 index 673d4a0a74..0000000000 --- a/runtime/interpreter/mterp/arm64/op_shl_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shl_int(): -% binop(instr="lsl w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_shl_int_2addr.S b/runtime/interpreter/mterp/arm64/op_shl_int_2addr.S deleted file mode 100644 index f4c2f8ceca..0000000000 --- a/runtime/interpreter/mterp/arm64/op_shl_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shl_int_2addr(): -% binop2addr(instr="lsl w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_shl_int_lit8.S b/runtime/interpreter/mterp/arm64/op_shl_int_lit8.S deleted file mode 100644 index 38f3f8edcb..0000000000 --- a/runtime/interpreter/mterp/arm64/op_shl_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shl_int_lit8(): -% binopLit8(extract="ubfx w1, w3, #8, #5", instr="lsl w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_shl_long.S b/runtime/interpreter/mterp/arm64/op_shl_long.S deleted file mode 100644 index c56b59fb3c..0000000000 --- a/runtime/interpreter/mterp/arm64/op_shl_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shl_long(): -% shiftWide(opcode="lsl") diff --git a/runtime/interpreter/mterp/arm64/op_shl_long_2addr.S b/runtime/interpreter/mterp/arm64/op_shl_long_2addr.S deleted file mode 100644 index ed10db2fd8..0000000000 --- a/runtime/interpreter/mterp/arm64/op_shl_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shl_long_2addr(): -% shiftWide2addr(opcode="lsl") diff --git a/runtime/interpreter/mterp/arm64/op_shr_int.S b/runtime/interpreter/mterp/arm64/op_shr_int.S deleted file mode 100644 index 9dab83d553..0000000000 --- a/runtime/interpreter/mterp/arm64/op_shr_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shr_int(): -% binop(instr="asr w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_shr_int_2addr.S b/runtime/interpreter/mterp/arm64/op_shr_int_2addr.S deleted file mode 100644 index 8bdcc11b70..0000000000 --- a/runtime/interpreter/mterp/arm64/op_shr_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shr_int_2addr(): -% binop2addr(instr="asr w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_shr_int_lit8.S b/runtime/interpreter/mterp/arm64/op_shr_int_lit8.S deleted file mode 100644 index 7f58bca4e9..0000000000 --- a/runtime/interpreter/mterp/arm64/op_shr_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shr_int_lit8(): -% binopLit8(extract="ubfx w1, w3, #8, #5", instr="asr w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_shr_long.S b/runtime/interpreter/mterp/arm64/op_shr_long.S deleted file mode 100644 index fcaf0ec45d..0000000000 --- a/runtime/interpreter/mterp/arm64/op_shr_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shr_long(): -% shiftWide(opcode="asr") diff --git a/runtime/interpreter/mterp/arm64/op_shr_long_2addr.S b/runtime/interpreter/mterp/arm64/op_shr_long_2addr.S deleted file mode 100644 index 359778ab53..0000000000 --- a/runtime/interpreter/mterp/arm64/op_shr_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shr_long_2addr(): -% shiftWide2addr(opcode="asr") diff --git a/runtime/interpreter/mterp/arm64/op_sparse_switch.S b/runtime/interpreter/mterp/arm64/op_sparse_switch.S deleted file mode 100644 index b74d7da816..0000000000 --- a/runtime/interpreter/mterp/arm64/op_sparse_switch.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sparse_switch(): -% op_packed_switch(func="MterpDoSparseSwitch") diff --git a/runtime/interpreter/mterp/arm64/op_sput.S b/runtime/interpreter/mterp/arm64/op_sput.S deleted file mode 100644 index cbd6ee96d3..0000000000 --- a/runtime/interpreter/mterp/arm64/op_sput.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sput(is_object="0", helper="MterpSPutU32"): -% field(helper=helper) diff --git a/runtime/interpreter/mterp/arm64/op_sput_boolean.S b/runtime/interpreter/mterp/arm64/op_sput_boolean.S deleted file mode 100644 index 36fba8448b..0000000000 --- a/runtime/interpreter/mterp/arm64/op_sput_boolean.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sput_boolean(): -% op_sput(helper="MterpSPutU8") diff --git a/runtime/interpreter/mterp/arm64/op_sput_byte.S b/runtime/interpreter/mterp/arm64/op_sput_byte.S deleted file mode 100644 index 84ad4a0ff8..0000000000 --- a/runtime/interpreter/mterp/arm64/op_sput_byte.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sput_byte(): -% op_sput(helper="MterpSPutI8") diff --git a/runtime/interpreter/mterp/arm64/op_sput_char.S b/runtime/interpreter/mterp/arm64/op_sput_char.S deleted file mode 100644 index 9b8eeba578..0000000000 --- a/runtime/interpreter/mterp/arm64/op_sput_char.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sput_char(): -% op_sput(helper="MterpSPutU16") diff --git a/runtime/interpreter/mterp/arm64/op_sput_object.S b/runtime/interpreter/mterp/arm64/op_sput_object.S deleted file mode 100644 index 081360c40f..0000000000 --- a/runtime/interpreter/mterp/arm64/op_sput_object.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sput_object(): -% op_sput(is_object="1", helper="MterpSPutObj") diff --git a/runtime/interpreter/mterp/arm64/op_sput_short.S b/runtime/interpreter/mterp/arm64/op_sput_short.S deleted file mode 100644 index ee16513486..0000000000 --- a/runtime/interpreter/mterp/arm64/op_sput_short.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sput_short(): -% op_sput(helper="MterpSPutI16") diff --git a/runtime/interpreter/mterp/arm64/op_sput_wide.S b/runtime/interpreter/mterp/arm64/op_sput_wide.S deleted file mode 100644 index 44c1a188ed..0000000000 --- a/runtime/interpreter/mterp/arm64/op_sput_wide.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sput_wide(): -% op_sput(helper="MterpSPutU64") diff --git a/runtime/interpreter/mterp/arm64/op_sub_double.S b/runtime/interpreter/mterp/arm64/op_sub_double.S deleted file mode 100644 index cca75564da..0000000000 --- a/runtime/interpreter/mterp/arm64/op_sub_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_double(): -% binopWide(instr="fsub d0, d1, d2", result="d0", r1="d1", r2="d2") diff --git a/runtime/interpreter/mterp/arm64/op_sub_double_2addr.S b/runtime/interpreter/mterp/arm64/op_sub_double_2addr.S deleted file mode 100644 index 6d425fc29d..0000000000 --- a/runtime/interpreter/mterp/arm64/op_sub_double_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_double_2addr(): -% binopWide2addr(instr="fsub d0, d0, d1", r0="d0", r1="d1") diff --git a/runtime/interpreter/mterp/arm64/op_sub_float.S b/runtime/interpreter/mterp/arm64/op_sub_float.S deleted file mode 100644 index e1c469b95c..0000000000 --- a/runtime/interpreter/mterp/arm64/op_sub_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_float(): -% fbinop(instr="fsub s0, s0, s1") diff --git a/runtime/interpreter/mterp/arm64/op_sub_float_2addr.S b/runtime/interpreter/mterp/arm64/op_sub_float_2addr.S deleted file mode 100644 index 91b8346985..0000000000 --- a/runtime/interpreter/mterp/arm64/op_sub_float_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_float_2addr(): -% fbinop2addr(instr="fsub s2, s0, s1") diff --git a/runtime/interpreter/mterp/arm64/op_sub_int.S b/runtime/interpreter/mterp/arm64/op_sub_int.S deleted file mode 100644 index 895146324b..0000000000 --- a/runtime/interpreter/mterp/arm64/op_sub_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_int(): -% binop(instr="sub w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_sub_int_2addr.S b/runtime/interpreter/mterp/arm64/op_sub_int_2addr.S deleted file mode 100644 index a450ce499c..0000000000 --- a/runtime/interpreter/mterp/arm64/op_sub_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_int_2addr(): -% binop2addr(instr="sub w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_sub_long.S b/runtime/interpreter/mterp/arm64/op_sub_long.S deleted file mode 100644 index 696e79a77f..0000000000 --- a/runtime/interpreter/mterp/arm64/op_sub_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_long(): -% binopWide(instr="sub x0, x1, x2") diff --git a/runtime/interpreter/mterp/arm64/op_sub_long_2addr.S b/runtime/interpreter/mterp/arm64/op_sub_long_2addr.S deleted file mode 100644 index a622451669..0000000000 --- a/runtime/interpreter/mterp/arm64/op_sub_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_long_2addr(): -% binopWide2addr(instr="sub x0, x0, x1") diff --git a/runtime/interpreter/mterp/arm64/op_throw.S b/runtime/interpreter/mterp/arm64/op_throw.S deleted file mode 100644 index ed5a19effd..0000000000 --- a/runtime/interpreter/mterp/arm64/op_throw.S +++ /dev/null @@ -1,11 +0,0 @@ -%def op_throw(): - /* - * Throw an exception object in the current thread. - */ - /* throw vAA */ - EXPORT_PC - lsr w2, wINST, #8 // r2<- AA - GET_VREG w1, w2 // r1<- vAA (exception object) - cbz w1, common_errNullObject - str x1, [xSELF, #THREAD_EXCEPTION_OFFSET] // thread->exception<- obj - b MterpException diff --git a/runtime/interpreter/mterp/arm64/op_unused_3e.S b/runtime/interpreter/mterp/arm64/op_unused_3e.S deleted file mode 100644 index d889f1a5fb..0000000000 --- a/runtime/interpreter/mterp/arm64/op_unused_3e.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_3e(): -% unused() diff --git a/runtime/interpreter/mterp/arm64/op_unused_3f.S b/runtime/interpreter/mterp/arm64/op_unused_3f.S deleted file mode 100644 index b3ebcfaeaa..0000000000 --- a/runtime/interpreter/mterp/arm64/op_unused_3f.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_3f(): -% unused() diff --git a/runtime/interpreter/mterp/arm64/op_unused_40.S b/runtime/interpreter/mterp/arm64/op_unused_40.S deleted file mode 100644 index 7920fb350f..0000000000 --- a/runtime/interpreter/mterp/arm64/op_unused_40.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_40(): -% unused() diff --git a/runtime/interpreter/mterp/arm64/op_unused_41.S b/runtime/interpreter/mterp/arm64/op_unused_41.S deleted file mode 100644 index 5ed03b8506..0000000000 --- a/runtime/interpreter/mterp/arm64/op_unused_41.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_41(): -% unused() diff --git a/runtime/interpreter/mterp/arm64/op_unused_42.S b/runtime/interpreter/mterp/arm64/op_unused_42.S deleted file mode 100644 index ac32521add..0000000000 --- a/runtime/interpreter/mterp/arm64/op_unused_42.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_42(): -% unused() diff --git a/runtime/interpreter/mterp/arm64/op_unused_43.S b/runtime/interpreter/mterp/arm64/op_unused_43.S deleted file mode 100644 index 33e2aa10f8..0000000000 --- a/runtime/interpreter/mterp/arm64/op_unused_43.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_43(): -% unused() diff --git a/runtime/interpreter/mterp/arm64/op_unused_73.S b/runtime/interpreter/mterp/arm64/op_unused_73.S deleted file mode 100644 index e3267a30a1..0000000000 --- a/runtime/interpreter/mterp/arm64/op_unused_73.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_73(): -% unused() diff --git a/runtime/interpreter/mterp/arm64/op_unused_79.S b/runtime/interpreter/mterp/arm64/op_unused_79.S deleted file mode 100644 index 3c6dafc789..0000000000 --- a/runtime/interpreter/mterp/arm64/op_unused_79.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_79(): -% unused() diff --git a/runtime/interpreter/mterp/arm64/op_unused_7a.S b/runtime/interpreter/mterp/arm64/op_unused_7a.S deleted file mode 100644 index 9c03cd5535..0000000000 --- a/runtime/interpreter/mterp/arm64/op_unused_7a.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_7a(): -% unused() diff --git a/runtime/interpreter/mterp/arm64/op_unused_f3.S b/runtime/interpreter/mterp/arm64/op_unused_f3.S deleted file mode 100644 index ab10b78be2..0000000000 --- a/runtime/interpreter/mterp/arm64/op_unused_f3.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_f3(): -% unused() diff --git a/runtime/interpreter/mterp/arm64/op_unused_f4.S b/runtime/interpreter/mterp/arm64/op_unused_f4.S deleted file mode 100644 index 09229d6d99..0000000000 --- a/runtime/interpreter/mterp/arm64/op_unused_f4.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_f4(): -% unused() diff --git a/runtime/interpreter/mterp/arm64/op_unused_f5.S b/runtime/interpreter/mterp/arm64/op_unused_f5.S deleted file mode 100644 index 0d6149b5fd..0000000000 --- a/runtime/interpreter/mterp/arm64/op_unused_f5.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_f5(): -% unused() diff --git a/runtime/interpreter/mterp/arm64/op_unused_f6.S b/runtime/interpreter/mterp/arm64/op_unused_f6.S deleted file mode 100644 index 117b03de6d..0000000000 --- a/runtime/interpreter/mterp/arm64/op_unused_f6.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_f6(): -% unused() diff --git a/runtime/interpreter/mterp/arm64/op_unused_f7.S b/runtime/interpreter/mterp/arm64/op_unused_f7.S deleted file mode 100644 index 4e3a0f3c9a..0000000000 --- a/runtime/interpreter/mterp/arm64/op_unused_f7.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_f7(): -% unused() diff --git a/runtime/interpreter/mterp/arm64/op_unused_f8.S b/runtime/interpreter/mterp/arm64/op_unused_f8.S deleted file mode 100644 index d1220752d7..0000000000 --- a/runtime/interpreter/mterp/arm64/op_unused_f8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_f8(): -% unused() diff --git a/runtime/interpreter/mterp/arm64/op_unused_f9.S b/runtime/interpreter/mterp/arm64/op_unused_f9.S deleted file mode 100644 index 7d09a0ebcf..0000000000 --- a/runtime/interpreter/mterp/arm64/op_unused_f9.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_f9(): -% unused() diff --git a/runtime/interpreter/mterp/arm64/op_unused_fc.S b/runtime/interpreter/mterp/arm64/op_unused_fc.S deleted file mode 100644 index 06978191eb..0000000000 --- a/runtime/interpreter/mterp/arm64/op_unused_fc.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_fc(): -% unused() diff --git a/runtime/interpreter/mterp/arm64/op_unused_fd.S b/runtime/interpreter/mterp/arm64/op_unused_fd.S deleted file mode 100644 index 4bc2b4bdb6..0000000000 --- a/runtime/interpreter/mterp/arm64/op_unused_fd.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_fd(): -% unused() diff --git a/runtime/interpreter/mterp/arm64/op_ushr_int.S b/runtime/interpreter/mterp/arm64/op_ushr_int.S deleted file mode 100644 index 5f6ad2d8fd..0000000000 --- a/runtime/interpreter/mterp/arm64/op_ushr_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_ushr_int(): -% binop(instr="lsr w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_ushr_int_2addr.S b/runtime/interpreter/mterp/arm64/op_ushr_int_2addr.S deleted file mode 100644 index 47527b182f..0000000000 --- a/runtime/interpreter/mterp/arm64/op_ushr_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_ushr_int_2addr(): -% binop2addr(instr="lsr w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_ushr_int_lit8.S b/runtime/interpreter/mterp/arm64/op_ushr_int_lit8.S deleted file mode 100644 index abc5898bcb..0000000000 --- a/runtime/interpreter/mterp/arm64/op_ushr_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_ushr_int_lit8(): -% binopLit8(extract="ubfx w1, w3, #8, #5", instr="lsr w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_ushr_long.S b/runtime/interpreter/mterp/arm64/op_ushr_long.S deleted file mode 100644 index 4f3e941872..0000000000 --- a/runtime/interpreter/mterp/arm64/op_ushr_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_ushr_long(): -% shiftWide(opcode="lsr") diff --git a/runtime/interpreter/mterp/arm64/op_ushr_long_2addr.S b/runtime/interpreter/mterp/arm64/op_ushr_long_2addr.S deleted file mode 100644 index 5606d12a21..0000000000 --- a/runtime/interpreter/mterp/arm64/op_ushr_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_ushr_long_2addr(): -% shiftWide2addr(opcode="lsr") diff --git a/runtime/interpreter/mterp/arm64/op_xor_int.S b/runtime/interpreter/mterp/arm64/op_xor_int.S deleted file mode 100644 index 369af7dc11..0000000000 --- a/runtime/interpreter/mterp/arm64/op_xor_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_xor_int(): -% binop(instr="eor w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_xor_int_2addr.S b/runtime/interpreter/mterp/arm64/op_xor_int_2addr.S deleted file mode 100644 index f8e87b359f..0000000000 --- a/runtime/interpreter/mterp/arm64/op_xor_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_xor_int_2addr(): -% binop2addr(instr="eor w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_xor_int_lit16.S b/runtime/interpreter/mterp/arm64/op_xor_int_lit16.S deleted file mode 100644 index bcfc6e20b3..0000000000 --- a/runtime/interpreter/mterp/arm64/op_xor_int_lit16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_xor_int_lit16(): -% binopLit16(instr="eor w0, w0, w1") diff --git a/runtime/interpreter/mterp/arm64/op_xor_int_lit8.S b/runtime/interpreter/mterp/arm64/op_xor_int_lit8.S deleted file mode 100644 index bd59c4cdbd..0000000000 --- a/runtime/interpreter/mterp/arm64/op_xor_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_xor_int_lit8(): -% binopLit8(extract="", instr="eor w0, w0, w3, asr #8") diff --git a/runtime/interpreter/mterp/arm64/op_xor_long.S b/runtime/interpreter/mterp/arm64/op_xor_long.S deleted file mode 100644 index 58b97bd247..0000000000 --- a/runtime/interpreter/mterp/arm64/op_xor_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_xor_long(): -% binopWide(instr="eor x0, x1, x2") diff --git a/runtime/interpreter/mterp/arm64/op_xor_long_2addr.S b/runtime/interpreter/mterp/arm64/op_xor_long_2addr.S deleted file mode 100644 index 5877665de7..0000000000 --- a/runtime/interpreter/mterp/arm64/op_xor_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_xor_long_2addr(): -% binopWide2addr(instr="eor x0, x0, x1") diff --git a/runtime/interpreter/mterp/arm64/other.S b/runtime/interpreter/mterp/arm64/other.S new file mode 100644 index 0000000000..024a5c8a07 --- /dev/null +++ b/runtime/interpreter/mterp/arm64/other.S @@ -0,0 +1,355 @@ +%def const(helper="UndefinedConstHandler"): + /* const/class vAA, type@BBBB */ + /* const/method-handle vAA, method_handle@BBBB */ + /* const/method-type vAA, proto@BBBB */ + /* const/string vAA, string@@BBBB */ + .extern $helper + EXPORT_PC + FETCH w0, 1 // w0<- BBBB + lsr w1, wINST, #8 // w1<- AA + add x2, xFP, #OFF_FP_SHADOWFRAME + mov x3, xSELF + bl $helper // (index, tgt_reg, shadow_frame, self) + PREFETCH_INST 2 // load rINST + cbnz w0, MterpPossibleException // let reference interpreter deal with it. + ADVANCE 2 // advance rPC + GET_INST_OPCODE ip // extract opcode from rINST + GOTO_OPCODE ip // jump to next instruction + +%def unused(): +/* + * Bail to reference interpreter to throw. + */ + b MterpFallback + +%def op_const(): + /* const vAA, #+BBBBbbbb */ + lsr w3, wINST, #8 // w3<- AA + FETCH w0, 1 // w0<- bbbb (low + FETCH w1, 2 // w1<- BBBB (high + FETCH_ADVANCE_INST 3 // advance rPC, load wINST + orr w0, w0, w1, lsl #16 // w0<- BBBBbbbb + GET_INST_OPCODE ip // extract opcode from wINST + SET_VREG w0, w3 // vAA<- w0 + GOTO_OPCODE ip // jump to next instruction + +%def op_const_16(): + /* const/16 vAA, #+BBBB */ + FETCH_S w0, 1 // w0<- ssssBBBB (sign-extended) + lsr w3, wINST, #8 // w3<- AA + FETCH_ADVANCE_INST 2 // advance xPC, load wINST + SET_VREG w0, w3 // vAA<- w0 + GET_INST_OPCODE ip // extract opcode from wINST + GOTO_OPCODE ip // jump to next instruction + +%def op_const_4(): + /* const/4 vA, #+B */ + sbfx w1, wINST, #12, #4 // w1<- sssssssB + ubfx w0, wINST, #8, #4 // w0<- A + FETCH_ADVANCE_INST 1 // advance xPC, load wINST + GET_INST_OPCODE ip // ip<- opcode from xINST + SET_VREG w1, w0 // fp[A]<- w1 + GOTO_OPCODE ip // execute next instruction + +%def op_const_class(): +% const(helper="MterpConstClass") + +%def op_const_high16(): + /* const/high16 vAA, #+BBBB0000 */ + FETCH w0, 1 // r0<- 0000BBBB (zero-extended) + lsr w3, wINST, #8 // r3<- AA + lsl w0, w0, #16 // r0<- BBBB0000 + FETCH_ADVANCE_INST 2 // advance rPC, load rINST + SET_VREG w0, w3 // vAA<- r0 + GET_INST_OPCODE ip // extract opcode from rINST + GOTO_OPCODE ip // jump to next instruction + +%def op_const_method_handle(): +% const(helper="MterpConstMethodHandle") + +%def op_const_method_type(): +% const(helper="MterpConstMethodType") + +%def op_const_string(): +% const(helper="MterpConstString") + +%def op_const_string_jumbo(): + /* const/string vAA, String//BBBBBBBB */ + EXPORT_PC + FETCH w0, 1 // w0<- bbbb (low + FETCH w2, 2 // w2<- BBBB (high + lsr w1, wINST, #8 // w1<- AA + orr w0, w0, w2, lsl #16 // w1<- BBBBbbbb + add x2, xFP, #OFF_FP_SHADOWFRAME + mov x3, xSELF + bl MterpConstString // (index, tgt_reg, shadow_frame, self) + PREFETCH_INST 3 // advance rPC + cbnz w0, MterpPossibleException // let reference interpreter deal with it. + ADVANCE 3 // advance rPC + GET_INST_OPCODE ip // extract opcode from rINST + GOTO_OPCODE ip // jump to next instruction + +%def op_const_wide(): + /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ + FETCH w0, 1 // w0<- bbbb (low) + FETCH w1, 2 // w1<- BBBB (low middle) + FETCH w2, 3 // w2<- hhhh (high middle) + FETCH w3, 4 // w3<- HHHH (high) + lsr w4, wINST, #8 // r4<- AA + FETCH_ADVANCE_INST 5 // advance rPC, load wINST + GET_INST_OPCODE ip // extract opcode from wINST + orr w0, w0, w1, lsl #16 // w0<- BBBBbbbb + orr x0, x0, x2, lsl #32 // w0<- hhhhBBBBbbbb + orr x0, x0, x3, lsl #48 // w0<- HHHHhhhhBBBBbbbb + SET_VREG_WIDE x0, w4 + GOTO_OPCODE ip // jump to next instruction + +%def op_const_wide_16(): + /* const-wide/16 vAA, #+BBBB */ + FETCH_S x0, 1 // x0<- ssssssssssssBBBB (sign-extended) + lsr w3, wINST, #8 // w3<- AA + FETCH_ADVANCE_INST 2 // advance rPC, load rINST + GET_INST_OPCODE ip // extract opcode from rINST + SET_VREG_WIDE x0, w3 + GOTO_OPCODE ip // jump to next instruction + +%def op_const_wide_32(): + /* const-wide/32 vAA, #+BBBBbbbb */ + FETCH w0, 1 // x0<- 000000000000bbbb (low) + lsr w3, wINST, #8 // w3<- AA + FETCH_S x2, 2 // x2<- ssssssssssssBBBB (high) + FETCH_ADVANCE_INST 3 // advance rPC, load wINST + GET_INST_OPCODE ip // extract opcode from wINST + orr x0, x0, x2, lsl #16 // x0<- ssssssssBBBBbbbb + SET_VREG_WIDE x0, w3 + GOTO_OPCODE ip // jump to next instruction + +%def op_const_wide_high16(): + /* const-wide/high16 vAA, #+BBBB000000000000 */ + FETCH w0, 1 // w0<- 0000BBBB (zero-extended) + lsr w1, wINST, #8 // w1<- AA + FETCH_ADVANCE_INST 2 // advance rPC, load wINST + lsl x0, x0, #48 + SET_VREG_WIDE x0, w1 + GET_INST_OPCODE ip // extract opcode from wINST + GOTO_OPCODE ip // jump to next instruction + +%def op_monitor_enter(): + /* + * Synchronize on an object. + */ + /* monitor-enter vAA */ + EXPORT_PC + lsr w2, wINST, #8 // w2<- AA + GET_VREG w0, w2 // w0<- vAA (object) + mov x1, xSELF // w1<- self + bl artLockObjectFromCode + cbnz w0, MterpException + FETCH_ADVANCE_INST 1 + GET_INST_OPCODE ip // extract opcode from rINST + GOTO_OPCODE ip // jump to next instruction + +%def op_monitor_exit(): + /* + * Unlock an object. + * + * Exceptions that occur when unlocking a monitor need to appear as + * if they happened at the following instruction. See the Dalvik + * instruction spec. + */ + /* monitor-exit vAA */ + EXPORT_PC + lsr w2, wINST, #8 // w2<- AA + GET_VREG w0, w2 // w0<- vAA (object) + mov x1, xSELF // w0<- self + bl artUnlockObjectFromCode // w0<- success for unlock(self, obj) + cbnz w0, MterpException + FETCH_ADVANCE_INST 1 // before throw: advance rPC, load rINST + GET_INST_OPCODE ip // extract opcode from rINST + GOTO_OPCODE ip // jump to next instruction + +%def op_move(is_object="0"): + /* for move, move-object, long-to-int */ + /* op vA, vB */ + lsr w1, wINST, #12 // x1<- B from 15:12 + ubfx w0, wINST, #8, #4 // x0<- A from 11:8 + FETCH_ADVANCE_INST 1 // advance rPC, load wINST + GET_VREG w2, w1 // x2<- fp[B] + GET_INST_OPCODE ip // ip<- opcode from wINST + .if $is_object + SET_VREG_OBJECT w2, w0 // fp[A]<- x2 + .else + SET_VREG w2, w0 // fp[A]<- x2 + .endif + GOTO_OPCODE ip // execute next instruction + +%def op_move_16(is_object="0"): + /* for: move/16, move-object/16 */ + /* op vAAAA, vBBBB */ + FETCH w1, 2 // w1<- BBBB + FETCH w0, 1 // w0<- AAAA + FETCH_ADVANCE_INST 3 // advance xPC, load xINST + GET_VREG w2, w1 // w2<- fp[BBBB] + GET_INST_OPCODE ip // extract opcode from xINST + .if $is_object + SET_VREG_OBJECT w2, w0 // fp[AAAA]<- w2 + .else + SET_VREG w2, w0 // fp[AAAA]<- w2 + .endif + GOTO_OPCODE ip // jump to next instruction + +%def op_move_exception(): + /* move-exception vAA */ + lsr w2, wINST, #8 // w2<- AA + ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] + mov x1, #0 // w1<- 0 + FETCH_ADVANCE_INST 1 // advance rPC, load rINST + SET_VREG_OBJECT w3, w2 // fp[AA]<- exception obj + GET_INST_OPCODE ip // extract opcode from rINST + str x1, [xSELF, #THREAD_EXCEPTION_OFFSET] // clear exception + GOTO_OPCODE ip // jump to next instruction + +%def op_move_from16(is_object="0"): + /* for: move/from16, move-object/from16 */ + /* op vAA, vBBBB */ + FETCH w1, 1 // r1<- BBBB + lsr w0, wINST, #8 // r0<- AA + FETCH_ADVANCE_INST 2 // advance rPC, load wINST + GET_VREG w2, w1 // r2<- fp[BBBB] + GET_INST_OPCODE ip // extract opcode from wINST + .if $is_object + SET_VREG_OBJECT w2, w0 // fp[AA]<- r2 + .else + SET_VREG w2, w0 // fp[AA]<- r2 + .endif + GOTO_OPCODE ip // jump to next instruction + +%def op_move_object(): +% op_move(is_object="1") + +%def op_move_object_16(): +% op_move_16(is_object="1") + +%def op_move_object_from16(): +% op_move_from16(is_object="1") + +%def op_move_result(is_object="0"): + /* for: move-result, move-result-object */ + /* op vAA */ + lsr w2, wINST, #8 // r2<- AA + FETCH_ADVANCE_INST 1 // advance rPC, load wINST + ldr x0, [xFP, #OFF_FP_RESULT_REGISTER] // get pointer to result JType. + ldr w0, [x0] // r0 <- result.i. + GET_INST_OPCODE ip // extract opcode from wINST + .if $is_object + SET_VREG_OBJECT w0, w2, w1 // fp[AA]<- r0 + .else + SET_VREG w0, w2 // fp[AA]<- r0 + .endif + GOTO_OPCODE ip // jump to next instruction + +%def op_move_result_object(): +% op_move_result(is_object="1") + +%def op_move_result_wide(): + /* for: move-result-wide */ + /* op vAA */ + lsr w2, wINST, #8 // r2<- AA + FETCH_ADVANCE_INST 1 // advance rPC, load wINST + ldr x0, [xFP, #OFF_FP_RESULT_REGISTER] // get pointer to result JType. + ldr x0, [x0] // r0 <- result.i. + GET_INST_OPCODE ip // extract opcode from wINST + SET_VREG_WIDE x0, x2 // fp[AA]<- r0 + GOTO_OPCODE ip // jump to next instruction + +%def op_move_wide(): + /* move-wide vA, vB */ + /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ + lsr w3, wINST, #12 // w3<- B + ubfx w2, wINST, #8, #4 // w2<- A + GET_VREG_WIDE x3, w3 + FETCH_ADVANCE_INST 1 // advance rPC, load wINST + GET_INST_OPCODE ip // extract opcode from wINST + SET_VREG_WIDE x3, w2 + GOTO_OPCODE ip // jump to next instruction + +%def op_move_wide_16(): + /* move-wide/16 vAAAA, vBBBB */ + /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ + FETCH w3, 2 // w3<- BBBB + FETCH w2, 1 // w2<- AAAA + GET_VREG_WIDE x3, w3 + FETCH_ADVANCE_INST 3 // advance rPC, load rINST + SET_VREG_WIDE x3, w2 + GET_INST_OPCODE ip // extract opcode from rINST + GOTO_OPCODE ip // jump to next instruction + +%def op_move_wide_from16(): + /* move-wide/from16 vAA, vBBBB */ + /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ + FETCH w3, 1 // w3<- BBBB + lsr w2, wINST, #8 // w2<- AA + GET_VREG_WIDE x3, w3 + FETCH_ADVANCE_INST 2 // advance rPC, load wINST + GET_INST_OPCODE ip // extract opcode from wINST + SET_VREG_WIDE x3, w2 + GOTO_OPCODE ip // jump to next instruction + +%def op_nop(): + FETCH_ADVANCE_INST 1 // advance to next instr, load rINST + GET_INST_OPCODE ip // ip<- opcode from rINST + GOTO_OPCODE ip // execute it + +%def op_unused_3e(): +% unused() + +%def op_unused_3f(): +% unused() + +%def op_unused_40(): +% unused() + +%def op_unused_41(): +% unused() + +%def op_unused_42(): +% unused() + +%def op_unused_43(): +% unused() + +%def op_unused_73(): +% unused() + +%def op_unused_79(): +% unused() + +%def op_unused_7a(): +% unused() + +%def op_unused_f3(): +% unused() + +%def op_unused_f4(): +% unused() + +%def op_unused_f5(): +% unused() + +%def op_unused_f6(): +% unused() + +%def op_unused_f7(): +% unused() + +%def op_unused_f8(): +% unused() + +%def op_unused_f9(): +% unused() + +%def op_unused_fc(): +% unused() + +%def op_unused_fd(): +% unused() diff --git a/runtime/interpreter/mterp/arm64/shiftWide.S b/runtime/interpreter/mterp/arm64/shiftWide.S deleted file mode 100644 index 46922c8626..0000000000 --- a/runtime/interpreter/mterp/arm64/shiftWide.S +++ /dev/null @@ -1,19 +0,0 @@ -%def shiftWide(opcode="shl"): - /* - * 64-bit shift operation. - * - * For: shl-long, shr-long, ushr-long - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w3, wINST, #8 // w3<- AA - lsr w2, w0, #8 // w2<- CC - GET_VREG w2, w2 // w2<- vCC (shift count) - and w1, w0, #255 // w1<- BB - GET_VREG_WIDE x1, w1 // x1<- vBB - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - $opcode x0, x1, x2 // Do the shift. Only low 6 bits of x2 are used. - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w3 // vAA<- x0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ diff --git a/runtime/interpreter/mterp/arm64/shiftWide2addr.S b/runtime/interpreter/mterp/arm64/shiftWide2addr.S deleted file mode 100644 index 2780d455e3..0000000000 --- a/runtime/interpreter/mterp/arm64/shiftWide2addr.S +++ /dev/null @@ -1,15 +0,0 @@ -%def shiftWide2addr(opcode="lsl"): - /* - * Generic 64-bit shift operation. - */ - /* binop/2addr vA, vB */ - lsr w1, wINST, #12 // w1<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG w1, w1 // x1<- vB - GET_VREG_WIDE x0, w2 // x0<- vA - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - $opcode x0, x0, x1 // Do the shift. Only low 6 bits of x1 are used. - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w2 // vAA<- result - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ diff --git a/runtime/interpreter/mterp/arm64/unop.S b/runtime/interpreter/mterp/arm64/unop.S deleted file mode 100644 index 65faf665ab..0000000000 --- a/runtime/interpreter/mterp/arm64/unop.S +++ /dev/null @@ -1,19 +0,0 @@ -%def unop(instr=""): - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op w0". - * This could be an ARM instruction or a function call. - * - * for: neg-int, not-int, neg-float, int-to-float, float-to-int, - * int-to-byte, int-to-char, int-to-short - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - GET_VREG w0, w3 // w0<- vB - ubfx w9, wINST, #8, #4 // w9<- A - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - $instr // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 8-9 instructions */ diff --git a/runtime/interpreter/mterp/arm64/unopWide.S b/runtime/interpreter/mterp/arm64/unopWide.S deleted file mode 100644 index 6a16dfa9f0..0000000000 --- a/runtime/interpreter/mterp/arm64/unopWide.S +++ /dev/null @@ -1,17 +0,0 @@ -%def unopWide(instr="sub x0, xzr, x0"): - /* - * Generic 64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op x0". - * - * For: neg-long, not-long - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w4, wINST, #8, #4 // w4<- A - GET_VREG_WIDE x0, w3 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - $instr - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG_WIDE x0, w4 - GOTO_OPCODE ip // jump to next instruction - /* 10-11 instructions */ diff --git a/runtime/interpreter/mterp/arm64/unused.S b/runtime/interpreter/mterp/arm64/unused.S deleted file mode 100644 index 3f37e74bb4..0000000000 --- a/runtime/interpreter/mterp/arm64/unused.S +++ /dev/null @@ -1,5 +0,0 @@ -%def unused(): -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback diff --git a/runtime/interpreter/mterp/arm64/zcmp.S b/runtime/interpreter/mterp/arm64/zcmp.S deleted file mode 100644 index 4435854d14..0000000000 --- a/runtime/interpreter/mterp/arm64/zcmp.S +++ /dev/null @@ -1,20 +0,0 @@ -%def zcmp(compare="1", branch=""): - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - lsr w0, wINST, #8 // w0<- AA - GET_VREG w2, w0 // w2<- vAA - FETCH_S wINST, 1 // w1<- branch offset, in code units - .if ${compare} - cmp w2, #0 // compare (vA, 0) - .endif - ${branch} MterpCommonTakenBranchNoFlags - cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? - b.eq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/mips/alt_stub.S b/runtime/interpreter/mterp/mips/alt_stub.S deleted file mode 100644 index 1ce75617a0..0000000000 --- a/runtime/interpreter/mterp/mips/alt_stub.S +++ /dev/null @@ -1,14 +0,0 @@ -%def alt_stub(): -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (${opnum} * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) diff --git a/runtime/interpreter/mterp/mips/arithmetic.S b/runtime/interpreter/mterp/mips/arithmetic.S new file mode 100644 index 0000000000..0743bdea76 --- /dev/null +++ b/runtime/interpreter/mterp/mips/arithmetic.S @@ -0,0 +1,803 @@ +%def binop(preinstr="", result="a0", chkzero="0", instr=""): + /* + * Generic 32-bit binary operation. Provide an "instr" line that + * specifies an instruction that performs "result = a0 op a1". + * This could be a MIPS instruction or a function call. (If the result + * comes back in a register other than a0, you can override "result".) + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vCC (a1). Useful for integer division and modulus. Note that we + * *don't* check for (INT_MIN / -1) here, because the CPU handles it + * correctly. + * + * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, + * xor-int, shl-int, shr-int, ushr-int + */ + /* binop vAA, vBB, vCC */ + FETCH(a0, 1) # a0 <- CCBB + GET_OPA(rOBJ) # rOBJ <- AA + srl a3, a0, 8 # a3 <- CC + and a2, a0, 255 # a2 <- BB + GET_VREG(a1, a3) # a1 <- vCC + GET_VREG(a0, a2) # a0 <- vBB + .if $chkzero + # is second operand zero? + beqz a1, common_errDivideByZero + .endif + + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + $preinstr # optional op + $instr # $result <- op, a0-a3 changed + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG_GOTO($result, rOBJ, t0) # vAA <- $result + +%def binop2addr(preinstr="", result="a0", chkzero="0", instr=""): + /* + * Generic 32-bit "/2addr" binary operation. Provide an "instr" line + * that specifies an instruction that performs "result = a0 op a1". + * This could be an MIPS instruction or a function call. + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vCC (a1). Useful for integer division and modulus. + * + * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, + * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, + * shl-int/2addr, shr-int/2addr, ushr-int/2addr + */ + /* binop/2addr vA, vB */ + GET_OPA4(rOBJ) # rOBJ <- A+ + GET_OPB(a3) # a3 <- B + GET_VREG(a0, rOBJ) # a0 <- vA + GET_VREG(a1, a3) # a1 <- vB + .if $chkzero + # is second operand zero? + beqz a1, common_errDivideByZero + .endif + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + + $preinstr # optional op + $instr # $result <- op, a0-a3 changed + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG_GOTO($result, rOBJ, t0) # vA <- $result + +%def binopLit16(preinstr="", result="a0", chkzero="0", instr=""): + /* + * Generic 32-bit "lit16" binary operation. Provide an "instr" line + * that specifies an instruction that performs "result = a0 op a1". + * This could be an MIPS instruction or a function call. (If the result + * comes back in a register other than a0, you can override "result".) + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vCC (a1). Useful for integer division and modulus. + * + * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, + * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 + */ + /* binop/lit16 vA, vB, +CCCC */ + FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) + GET_OPB(a2) # a2 <- B + GET_OPA4(rOBJ) # rOBJ <- A+ + GET_VREG(a0, a2) # a0 <- vB + .if $chkzero + # cmp a1, 0; is second operand zero? + beqz a1, common_errDivideByZero + .endif + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + + $preinstr # optional op + $instr # $result <- op, a0-a3 changed + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG_GOTO($result, rOBJ, t0) # vA <- $result + +%def binopLit8(preinstr="", result="a0", chkzero="0", instr=""): + /* + * Generic 32-bit "lit8" binary operation. Provide an "instr" line + * that specifies an instruction that performs "result = a0 op a1". + * This could be an MIPS instruction or a function call. (If the result + * comes back in a register other than a0, you can override "result".) + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vCC (a1). Useful for integer division and modulus. + * + * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, + * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, + * shl-int/lit8, shr-int/lit8, ushr-int/lit8 + */ + /* binop/lit8 vAA, vBB, +CC */ + FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) + GET_OPA(rOBJ) # rOBJ <- AA + and a2, a3, 255 # a2 <- BB + GET_VREG(a0, a2) # a0 <- vBB + sra a1, a3, 8 # a1 <- ssssssCC (sign extended) + .if $chkzero + # is second operand zero? + beqz a1, common_errDivideByZero + .endif + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + + $preinstr # optional op + $instr # $result <- op, a0-a3 changed + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG_GOTO($result, rOBJ, t0) # vAA <- $result + +%def binopWide(preinstr="", result0="a0", result1="a1", chkzero="0", arg0="a0", arg1="a1", arg2="a2", arg3="a3", instr=""): + /* + * Generic 64-bit binary operation. Provide an "instr" line that + * specifies an instruction that performs "result = a0-a1 op a2-a3". + * This could be a MIPS instruction or a function call. (If the result + * comes back in a register pair other than a0-a1, you can override "result".) + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vCC (a2-a3). Useful for integer division and modulus. + * + * for: add-long, sub-long, div-long, rem-long, and-long, or-long, + * xor-long + * + * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. + */ + /* binop vAA, vBB, vCC */ + FETCH(a0, 1) # a0 <- CCBB + GET_OPA(rOBJ) # rOBJ <- AA + and a2, a0, 255 # a2 <- BB + srl a3, a0, 8 # a3 <- CC + EAS2(a2, rFP, a2) # a2 <- &fp[BB] + EAS2(t1, rFP, a3) # a3 <- &fp[CC] + LOAD64($arg0, $arg1, a2) # a0/a1 <- vBB/vBB+1 + LOAD64($arg2, $arg3, t1) # a2/a3 <- vCC/vCC+1 + .if $chkzero + or t0, $arg2, $arg3 # second arg (a2-a3) is zero? + beqz t0, common_errDivideByZero + .endif + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + + $preinstr # optional op + $instr # result <- op, a0-a3 changed + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG64_GOTO($result0, $result1, rOBJ, t0) # vAA/vAA+1 <- $result0/$result1 + +%def binopWide2addr(preinstr="", result0="a0", result1="a1", chkzero="0", arg0="a0", arg1="a1", arg2="a2", arg3="a3", instr=""): + /* + * Generic 64-bit "/2addr" binary operation. Provide an "instr" line + * that specifies an instruction that performs "result = a0-a1 op a2-a3". + * This could be a MIPS instruction or a function call. (If the result + * comes back in a register pair other than a0-a1, you can override "result".) + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vB (a2-a3). Useful for integer division and modulus. + * + * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, + * and-long/2addr, or-long/2addr, xor-long/2addr + */ + /* binop/2addr vA, vB */ + GET_OPA4(rOBJ) # rOBJ <- A+ + GET_OPB(a1) # a1 <- B + EAS2(a1, rFP, a1) # a1 <- &fp[B] + EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] + LOAD64($arg2, $arg3, a1) # a2/a3 <- vB/vB+1 + LOAD64($arg0, $arg1, t0) # a0/a1 <- vA/vA+1 + .if $chkzero + or t0, $arg2, $arg3 # second arg (a2-a3) is zero? + beqz t0, common_errDivideByZero + .endif + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + + $preinstr # optional op + $instr # result <- op, a0-a3 changed + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG64_GOTO($result0, $result1, rOBJ, t0) # vA/vA+1 <- $result0/$result1 + +%def unop(preinstr="", result0="a0", instr=""): + /* + * Generic 32-bit unary operation. Provide an "instr" line that + * specifies an instruction that performs "result0 = op a0". + * This could be a MIPS instruction or a function call. + * + * for: int-to-byte, int-to-char, int-to-short, + * neg-int, not-int, neg-float + */ + /* unop vA, vB */ + GET_OPB(a3) # a3 <- B + GET_OPA4(t0) # t0 <- A+ + GET_VREG(a0, a3) # a0 <- vB + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + $preinstr # optional op + $instr # a0 <- op, a0-a3 changed + GET_INST_OPCODE(t1) # extract opcode from rINST + SET_VREG_GOTO($result0, t0, t1) # vA <- result0 + +%def unopNarrower(load="LOAD64_F(fa0, fa0f, a3)", instr=""): + /* + * Generic 64bit-to-32bit floating-point unary operation. Provide an "instr" + * line that specifies an instruction that performs "fv0 = op fa0". + * + * For: double-to-float + */ + /* unop vA, vB */ + GET_OPB(a3) # a3 <- B + GET_OPA4(rOBJ) # rOBJ <- A+ + EAS2(a3, rFP, a3) # a3 <- &fp[B] + $load + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + $instr + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG_F_GOTO(fv0, rOBJ, t0) # vA <- fv0 + +%def unopWide(preinstr="", result0="a0", result1="a1", instr=""): + /* + * Generic 64-bit unary operation. Provide an "instr" line that + * specifies an instruction that performs "result0/result1 = op a0/a1". + * This could be MIPS instruction or a function call. + * + * For: neg-long, not-long, neg-double, + */ + /* unop vA, vB */ + GET_OPA4(rOBJ) # rOBJ <- A+ + GET_OPB(a3) # a3 <- B + EAS2(a3, rFP, a3) # a3 <- &fp[B] + LOAD64(a0, a1, a3) # a0/a1 <- vA + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + $preinstr # optional op + $instr # a0/a1 <- op, a2-a3 changed + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG64_GOTO($result0, $result1, rOBJ, t0) # vA/vA+1 <- a0/a1 + +%def unopWider(preinstr="", result0="a0", result1="a1", instr=""): + /* + * Generic 32bit-to-64bit unary operation. Provide an "instr" line + * that specifies an instruction that performs "result0/result1 = op a0". + * + * For: int-to-long + */ + /* unop vA, vB */ + GET_OPA4(rOBJ) # rOBJ <- A+ + GET_OPB(a3) # a3 <- B + GET_VREG(a0, a3) # a0 <- vB + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + $preinstr # optional op + $instr # result <- op, a0-a3 changed + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG64_GOTO($result0, $result1, rOBJ, t0) # vA/vA+1 <- a0/a1 + +%def op_add_int(): +% binop(instr="addu a0, a0, a1") + +%def op_add_int_2addr(): +% binop2addr(instr="addu a0, a0, a1") + +%def op_add_int_lit16(): +% binopLit16(instr="addu a0, a0, a1") + +%def op_add_int_lit8(): +% binopLit8(instr="addu a0, a0, a1") + +%def op_add_long(): +/* + * The compiler generates the following sequence for + * [v1 v0] = [a1 a0] + [a3 a2]; + * addu v0,a2,a0 + * addu a1,a3,a1 + * sltu v1,v0,a2 + * addu v1,v1,a1 + */ +% binopWide(result0="v0", result1="v1", preinstr="addu v0, a2, a0", instr="addu a1, a3, a1; sltu v1, v0, a2; addu v1, v1, a1") + +%def op_add_long_2addr(): +/* + * See op_add_long.S for details + */ +% binopWide2addr(result0="v0", result1="v1", preinstr="addu v0, a2, a0", instr="addu a1, a3, a1; sltu v1, v0, a2; addu v1, v1, a1") + +%def op_and_int(): +% binop(instr="and a0, a0, a1") + +%def op_and_int_2addr(): +% binop2addr(instr="and a0, a0, a1") + +%def op_and_int_lit16(): +% binopLit16(instr="and a0, a0, a1") + +%def op_and_int_lit8(): +% binopLit8(instr="and a0, a0, a1") + +%def op_and_long(): +% binopWide(preinstr="and a0, a0, a2", instr="and a1, a1, a3") + +%def op_and_long_2addr(): +% binopWide2addr(preinstr="and a0, a0, a2", instr="and a1, a1, a3") + +%def op_cmp_long(): + /* + * Compare two 64-bit values + * x = y return 0 + * x < y return -1 + * x > y return 1 + * + * I think I can improve on the ARM code by the following observation + * slt t0, x.hi, y.hi; # (x.hi < y.hi) ? 1:0 + * sgt t1, x.hi, y.hi; # (y.hi > x.hi) ? 1:0 + * subu v0, t0, t1 # v0= -1:1:0 for [ < > = ] + */ + /* cmp-long vAA, vBB, vCC */ + FETCH(a0, 1) # a0 <- CCBB + GET_OPA(rOBJ) # rOBJ <- AA + and a2, a0, 255 # a2 <- BB + srl a3, a0, 8 # a3 <- CC + EAS2(a2, rFP, a2) # a2 <- &fp[BB] + EAS2(a3, rFP, a3) # a3 <- &fp[CC] + LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 + LOAD64(a2, a3, a3) # a2/a3 <- vCC/vCC+1 + + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + slt t0, a1, a3 # compare hi + sgt t1, a1, a3 + subu v0, t1, t0 # v0 <- (-1, 1, 0) + bnez v0, .L${opcode}_finish + # at this point x.hi==y.hi + sltu t0, a0, a2 # compare lo + sgtu t1, a0, a2 + subu v0, t1, t0 # v0 <- (-1, 1, 0) for [< > =] + +.L${opcode}_finish: + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG_GOTO(v0, rOBJ, t0) # vAA <- v0 + +%def op_div_int(): +#ifdef MIPS32REVGE6 +% binop(instr="div a0, a0, a1", chkzero="1") +#else +% binop(preinstr="div zero, a0, a1", instr="mflo a0", chkzero="1") +#endif + +%def op_div_int_2addr(): +#ifdef MIPS32REVGE6 +% binop2addr(instr="div a0, a0, a1", chkzero="1") +#else +% binop2addr(preinstr="div zero, a0, a1", instr="mflo a0", chkzero="1") +#endif + +%def op_div_int_lit16(): +#ifdef MIPS32REVGE6 +% binopLit16(instr="div a0, a0, a1", chkzero="1") +#else +% binopLit16(preinstr="div zero, a0, a1", instr="mflo a0", chkzero="1") +#endif + +%def op_div_int_lit8(): +#ifdef MIPS32REVGE6 +% binopLit8(instr="div a0, a0, a1", chkzero="1") +#else +% binopLit8(preinstr="div zero, a0, a1", instr="mflo a0", chkzero="1") +#endif + +%def op_div_long(): +% binopWide(result0="v0", result1="v1", instr="JAL(__divdi3)", chkzero="1") + +%def op_div_long_2addr(): +% binopWide2addr(result0="v0", result1="v1", instr="JAL(__divdi3)", chkzero="1") + +%def op_int_to_byte(): +% unop(instr="SEB(a0, a0)") + +%def op_int_to_char(): +% unop(preinstr="", instr="and a0, 0xffff") + +%def op_int_to_long(): +% unopWider(instr="sra a1, a0, 31") + +%def op_int_to_short(): +% unop(instr="SEH(a0, a0)") + +%def op_long_to_int(): +/* we ignore the high word, making this equivalent to a 32-bit reg move */ +% op_move() + +%def op_mul_int(): +% binop(instr="mul a0, a0, a1") + +%def op_mul_int_2addr(): +% binop2addr(instr="mul a0, a0, a1") + +%def op_mul_int_lit16(): +% binopLit16(instr="mul a0, a0, a1") + +%def op_mul_int_lit8(): +% binopLit8(instr="mul a0, a0, a1") + +%def op_mul_long(): + /* + * Signed 64-bit integer multiply. + * a1 a0 + * x a3 a2 + * ------------- + * a2a1 a2a0 + * a3a0 + * a3a1 (<= unused) + * --------------- + * v1 v0 + */ + /* mul-long vAA, vBB, vCC */ + FETCH(a0, 1) # a0 <- CCBB + and t0, a0, 255 # a2 <- BB + srl t1, a0, 8 # a3 <- CC + EAS2(t0, rFP, t0) # t0 <- &fp[BB] + LOAD64(a0, a1, t0) # a0/a1 <- vBB/vBB+1 + + EAS2(t1, rFP, t1) # t0 <- &fp[CC] + LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 + + mul v1, a3, a0 # v1= a3a0 +#ifdef MIPS32REVGE6 + mulu v0, a2, a0 # v0= a2a0 + muhu t1, a2, a0 +#else + multu a2, a0 + mfhi t1 + mflo v0 # v0= a2a0 +#endif + mul t0, a2, a1 # t0= a2a1 + addu v1, v1, t1 # v1+= hi(a2a0) + addu v1, v1, t0 # v1= a3a0 + a2a1; + + GET_OPA(a0) # a0 <- AA + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + b .L${opcode}_finish +%def op_mul_long_sister_code(): + +.L${opcode}_finish: + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG64_GOTO(v0, v1, a0, t0) # vAA/vAA+1 <- v0(low)/v1(high) + +%def op_mul_long_2addr(): + /* + * See op_mul_long.S for more details + */ + /* mul-long/2addr vA, vB */ + GET_OPA4(rOBJ) # rOBJ <- A+ + + EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] + LOAD64(a0, a1, t0) # vAA.low / high + + GET_OPB(t1) # t1 <- B + EAS2(t1, rFP, t1) # t1 <- &fp[B] + LOAD64(a2, a3, t1) # vBB.low / high + + mul v1, a3, a0 # v1= a3a0 +#ifdef MIPS32REVGE6 + mulu v0, a2, a0 # v0= a2a0 + muhu t1, a2, a0 +#else + multu a2, a0 + mfhi t1 + mflo v0 # v0= a2a0 + #endif + mul t2, a2, a1 # t2= a2a1 + addu v1, v1, t1 # v1= a3a0 + hi(a2a0) + addu v1, v1, t2 # v1= v1 + a2a1; + + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + GET_INST_OPCODE(t1) # extract opcode from rINST + SET_VREG64_GOTO(v0, v1, rOBJ, t1) # vA/vA+1 <- v0(low)/v1(high) + +%def op_neg_int(): +% unop(instr="negu a0, a0") + +%def op_neg_long(): +% unopWide(result0="v0", result1="v1", preinstr="negu v0, a0", instr="negu v1, a1; sltu a0, zero, v0; subu v1, v1, a0") + +%def op_not_int(): +% unop(instr="not a0, a0") + +%def op_not_long(): +% unopWide(preinstr="not a0, a0", instr="not a1, a1") + +%def op_or_int(): +% binop(instr="or a0, a0, a1") + +%def op_or_int_2addr(): +% binop2addr(instr="or a0, a0, a1") + +%def op_or_int_lit16(): +% binopLit16(instr="or a0, a0, a1") + +%def op_or_int_lit8(): +% binopLit8(instr="or a0, a0, a1") + +%def op_or_long(): +% binopWide(preinstr="or a0, a0, a2", instr="or a1, a1, a3") + +%def op_or_long_2addr(): +% binopWide2addr(preinstr="or a0, a0, a2", instr="or a1, a1, a3") + +%def op_rem_int(): +#ifdef MIPS32REVGE6 +% binop(instr="mod a0, a0, a1", chkzero="1") +#else +% binop(preinstr="div zero, a0, a1", instr="mfhi a0", chkzero="1") +#endif + +%def op_rem_int_2addr(): +#ifdef MIPS32REVGE6 +% binop2addr(instr="mod a0, a0, a1", chkzero="1") +#else +% binop2addr(preinstr="div zero, a0, a1", instr="mfhi a0", chkzero="1") +#endif + +%def op_rem_int_lit16(): +#ifdef MIPS32REVGE6 +% binopLit16(instr="mod a0, a0, a1", chkzero="1") +#else +% binopLit16(preinstr="div zero, a0, a1", instr="mfhi a0", chkzero="1") +#endif + +%def op_rem_int_lit8(): +#ifdef MIPS32REVGE6 +% binopLit8(instr="mod a0, a0, a1", chkzero="1") +#else +% binopLit8(preinstr="div zero, a0, a1", instr="mfhi a0", chkzero="1") +#endif + +%def op_rem_long(): +% binopWide(result0="v0", result1="v1", instr="JAL(__moddi3)", chkzero="1") + +%def op_rem_long_2addr(): +% binopWide2addr(result0="v0", result1="v1", instr="JAL(__moddi3)", chkzero="1") + +%def op_rsub_int(): +/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ +% binopLit16(instr="subu a0, a1, a0") + +%def op_rsub_int_lit8(): +% binopLit8(instr="subu a0, a1, a0") + +%def op_shl_int(): +% binop(instr="sll a0, a0, a1") + +%def op_shl_int_2addr(): +% binop2addr(instr="sll a0, a0, a1") + +%def op_shl_int_lit8(): +% binopLit8(instr="sll a0, a0, a1") + +%def op_shl_long(): + /* + * Long integer shift. This is different from the generic 32/64-bit + * binary operations because vAA/vBB are 64-bit but vCC (the shift + * distance) is 32-bit. Also, Dalvik requires us to mask off the low + * 6 bits of the shift distance. + */ + /* shl-long vAA, vBB, vCC */ + FETCH(a0, 1) # a0 <- CCBB + GET_OPA(t2) # t2 <- AA + and a3, a0, 255 # a3 <- BB + srl a0, a0, 8 # a0 <- CC + EAS2(a3, rFP, a3) # a3 <- &fp[BB] + GET_VREG(a2, a0) # a2 <- vCC + LOAD64(a0, a1, a3) # a0/a1 <- vBB/vBB+1 + + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + + andi v1, a2, 0x20 # shift< shift & 0x20 + sll v0, a0, a2 # rlo<- alo << (shift&31) + bnez v1, .L${opcode}_finish + not v1, a2 # rhi<- 31-shift (shift is 5b) + srl a0, 1 + srl a0, v1 # alo<- alo >> (32-(shift&31)) + sll v1, a1, a2 # rhi<- ahi << (shift&31) + or v1, a0 # rhi<- rhi | alo + SET_VREG64_GOTO(v0, v1, t2, t0) # vAA/vAA+1 <- v0/v1 +%def op_shl_long_sister_code(): + +.L${opcode}_finish: + SET_VREG64_GOTO(zero, v0, t2, t0) # vAA/vAA+1 <- rlo/rhi + +%def op_shl_long_2addr(): + /* + * Long integer shift, 2addr version. vA is 64-bit value/result, vB is + * 32-bit shift distance. + */ + /* shl-long/2addr vA, vB */ + GET_OPA4(rOBJ) # rOBJ <- A+ + GET_OPB(a3) # a3 <- B + GET_VREG(a2, a3) # a2 <- vB + EAS2(t2, rFP, rOBJ) # t2 <- &fp[A] + LOAD64(a0, a1, t2) # a0/a1 <- vA/vA+1 + + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + + andi v1, a2, 0x20 # shift< shift & 0x20 + sll v0, a0, a2 # rlo<- alo << (shift&31) + bnez v1, .L${opcode}_finish + not v1, a2 # rhi<- 31-shift (shift is 5b) + srl a0, 1 + srl a0, v1 # alo<- alo >> (32-(shift&31)) + sll v1, a1, a2 # rhi<- ahi << (shift&31) + or v1, a0 # rhi<- rhi | alo + SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vA/vA+1 <- v0/v1 +%def op_shl_long_2addr_sister_code(): + +.L${opcode}_finish: + SET_VREG64_GOTO(zero, v0, rOBJ, t0) # vA/vA+1 <- rlo/rhi + +%def op_shr_int(): +% binop(instr="sra a0, a0, a1") + +%def op_shr_int_2addr(): +% binop2addr(instr="sra a0, a0, a1") + +%def op_shr_int_lit8(): +% binopLit8(instr="sra a0, a0, a1") + +%def op_shr_long(): + /* + * Long integer shift. This is different from the generic 32/64-bit + * binary operations because vAA/vBB are 64-bit but vCC (the shift + * distance) is 32-bit. Also, Dalvik requires us to mask off the low + * 6 bits of the shift distance. + */ + /* shr-long vAA, vBB, vCC */ + FETCH(a0, 1) # a0 <- CCBB + GET_OPA(t3) # t3 <- AA + and a3, a0, 255 # a3 <- BB + srl a0, a0, 8 # a0 <- CC + EAS2(a3, rFP, a3) # a3 <- &fp[BB] + GET_VREG(a2, a0) # a2 <- vCC + LOAD64(a0, a1, a3) # a0/a1 <- vBB/vBB+1 + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + + andi v0, a2, 0x20 # shift & 0x20 + sra v1, a1, a2 # rhi<- ahi >> (shift&31) + bnez v0, .L${opcode}_finish + srl v0, a0, a2 # rlo<- alo >> (shift&31) + not a0, a2 # alo<- 31-shift (shift is 5b) + sll a1, 1 + sll a1, a0 # ahi<- ahi << (32-(shift&31)) + or v0, a1 # rlo<- rlo | ahi + SET_VREG64_GOTO(v0, v1, t3, t0) # vAA/VAA+1 <- v0/v1 +%def op_shr_long_sister_code(): + +.L${opcode}_finish: + sra a3, a1, 31 # a3<- sign(ah) + SET_VREG64_GOTO(v1, a3, t3, t0) # vAA/VAA+1 <- rlo/rhi + +%def op_shr_long_2addr(): + /* + * Long integer shift, 2addr version. vA is 64-bit value/result, vB is + * 32-bit shift distance. + */ + /* shr-long/2addr vA, vB */ + GET_OPA4(t2) # t2 <- A+ + GET_OPB(a3) # a3 <- B + GET_VREG(a2, a3) # a2 <- vB + EAS2(t0, rFP, t2) # t0 <- &fp[A] + LOAD64(a0, a1, t0) # a0/a1 <- vA/vA+1 + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + + andi v0, a2, 0x20 # shift & 0x20 + sra v1, a1, a2 # rhi<- ahi >> (shift&31) + bnez v0, .L${opcode}_finish + srl v0, a0, a2 # rlo<- alo >> (shift&31) + not a0, a2 # alo<- 31-shift (shift is 5b) + sll a1, 1 + sll a1, a0 # ahi<- ahi << (32-(shift&31)) + or v0, a1 # rlo<- rlo | ahi + SET_VREG64_GOTO(v0, v1, t2, t0) # vA/vA+1 <- v0/v1 +%def op_shr_long_2addr_sister_code(): + +.L${opcode}_finish: + sra a3, a1, 31 # a3<- sign(ah) + SET_VREG64_GOTO(v1, a3, t2, t0) # vA/vA+1 <- rlo/rhi + +%def op_sub_int(): +% binop(instr="subu a0, a0, a1") + +%def op_sub_int_2addr(): +% binop2addr(instr="subu a0, a0, a1") + +%def op_sub_long(): +/* + * For little endian the code sequence looks as follows: + * subu v0,a0,a2 + * subu v1,a1,a3 + * sltu a0,a0,v0 + * subu v1,v1,a0 + */ +% binopWide(result0="v0", result1="v1", preinstr="subu v0, a0, a2", instr="subu v1, a1, a3; sltu a0, a0, v0; subu v1, v1, a0") + +%def op_sub_long_2addr(): +/* + * See op_sub_long.S for more details + */ +% binopWide2addr(result0="v0", result1="v1", preinstr="subu v0, a0, a2", instr="subu v1, a1, a3; sltu a0, a0, v0; subu v1, v1, a0") + +%def op_ushr_int(): +% binop(instr="srl a0, a0, a1") + +%def op_ushr_int_2addr(): +% binop2addr(instr="srl a0, a0, a1 ") + +%def op_ushr_int_lit8(): +% binopLit8(instr="srl a0, a0, a1") + +%def op_ushr_long(): + /* + * Long integer shift. This is different from the generic 32/64-bit + * binary operations because vAA/vBB are 64-bit but vCC (the shift + * distance) is 32-bit. Also, Dalvik requires us to mask off the low + * 6 bits of the shift distance. + */ + /* ushr-long vAA, vBB, vCC */ + FETCH(a0, 1) # a0 <- CCBB + GET_OPA(rOBJ) # rOBJ <- AA + and a3, a0, 255 # a3 <- BB + srl a0, a0, 8 # a0 <- CC + EAS2(a3, rFP, a3) # a3 <- &fp[BB] + GET_VREG(a2, a0) # a2 <- vCC + LOAD64(a0, a1, a3) # a0/a1 <- vBB/vBB+1 + + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + + andi v0, a2, 0x20 # shift & 0x20 + srl v1, a1, a2 # rhi<- ahi >> (shift&31) + bnez v0, .L${opcode}_finish + srl v0, a0, a2 # rlo<- alo >> (shift&31) + not a0, a2 # alo<- 31-n (shift is 5b) + sll a1, 1 + sll a1, a0 # ahi<- ahi << (32-(shift&31)) + or v0, a1 # rlo<- rlo | ahi + SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vAA/vAA+1 <- v0/v1 +%def op_ushr_long_sister_code(): + +.L${opcode}_finish: + SET_VREG64_GOTO(v1, zero, rOBJ, t0) # vAA/vAA+1 <- rlo/rhi + +%def op_ushr_long_2addr(): + /* + * Long integer shift, 2addr version. vA is 64-bit value/result, vB is + * 32-bit shift distance. + */ + /* ushr-long/2addr vA, vB */ + GET_OPA4(t3) # t3 <- A+ + GET_OPB(a3) # a3 <- B + GET_VREG(a2, a3) # a2 <- vB + EAS2(t0, rFP, t3) # t0 <- &fp[A] + LOAD64(a0, a1, t0) # a0/a1 <- vA/vA+1 + + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + + andi v0, a2, 0x20 # shift & 0x20 + srl v1, a1, a2 # rhi<- ahi >> (shift&31) + bnez v0, .L${opcode}_finish + srl v0, a0, a2 # rlo<- alo >> (shift&31) + not a0, a2 # alo<- 31-n (shift is 5b) + sll a1, 1 + sll a1, a0 # ahi<- ahi << (32-(shift&31)) + or v0, a1 # rlo<- rlo | ahi + SET_VREG64_GOTO(v0, v1, t3, t0) # vA/vA+1 <- v0/v1 +%def op_ushr_long_2addr_sister_code(): + +.L${opcode}_finish: + SET_VREG64_GOTO(v1, zero, t3, t0) # vA/vA+1 <- rlo/rhi + +%def op_xor_int(): +% binop(instr="xor a0, a0, a1") + +%def op_xor_int_2addr(): +% binop2addr(instr="xor a0, a0, a1") + +%def op_xor_int_lit16(): +% binopLit16(instr="xor a0, a0, a1") + +%def op_xor_int_lit8(): +% binopLit8(instr="xor a0, a0, a1") + +%def op_xor_long(): +% binopWide(preinstr="xor a0, a0, a2", instr="xor a1, a1, a3") + +%def op_xor_long_2addr(): +% binopWide2addr(preinstr="xor a0, a0, a2", instr="xor a1, a1, a3") diff --git a/runtime/interpreter/mterp/mips/array.S b/runtime/interpreter/mterp/mips/array.S new file mode 100644 index 0000000000..57ab14743e --- /dev/null +++ b/runtime/interpreter/mterp/mips/array.S @@ -0,0 +1,239 @@ +%def op_aget(load="lw", shift="2", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"): + /* + * Array get, 32 bits or less. vAA <- vBB[vCC]. + * + * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 + * instructions. We use a pair of FETCH_Bs instead. + * + * for: aget, aget-boolean, aget-byte, aget-char, aget-short + * + * NOTE: assumes data offset for arrays is the same for all non-wide types. + * If this changes, specialize. + */ + /* op vAA, vBB, vCC */ + FETCH_B(a2, 1, 0) # a2 <- BB + GET_OPA(rOBJ) # rOBJ <- AA + FETCH_B(a3, 1, 1) # a3 <- CC + GET_VREG(a0, a2) # a0 <- vBB (array object) + GET_VREG(a1, a3) # a1 <- vCC (requested index) + # null array object? + beqz a0, common_errNullObject # yes, bail + LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length + EASN(a0, a0, a1, $shift) # a0 <- arrayObj + index*width + # a1 >= a3; compare unsigned index + bgeu a1, a3, common_errArrayIndex # index >= length, bail + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + $load a2, $data_offset(a0) # a2 <- vBB[vCC] + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG_GOTO(a2, rOBJ, t0) # vAA <- a2 + +%def op_aget_boolean(): +% op_aget(load="lbu", shift="0", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") + +%def op_aget_byte(): +% op_aget(load="lb", shift="0", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") + +%def op_aget_char(): +% op_aget(load="lhu", shift="1", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") + +%def op_aget_object(): + /* + * Array object get. vAA <- vBB[vCC]. + * + * for: aget-object + */ + /* op vAA, vBB, vCC */ + FETCH_B(a2, 1, 0) # a2 <- BB + GET_OPA(rOBJ) # rOBJ <- AA + FETCH_B(a3, 1, 1) # a3 <- CC + EXPORT_PC() + GET_VREG(a0, a2) # a0 <- vBB (array object) + GET_VREG(a1, a3) # a1 <- vCC (requested index) + JAL(artAGetObjectFromMterp) # v0 <- GetObj(array, index) + lw a1, THREAD_EXCEPTION_OFFSET(rSELF) + PREFETCH_INST(2) # load rINST + bnez a1, MterpException + ADVANCE(2) # advance rPC + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG_OBJECT_GOTO(v0, rOBJ, t0) # vAA <- v0 + +%def op_aget_short(): +% op_aget(load="lh", shift="1", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") + +%def op_aget_wide(): + /* + * Array get, 64 bits. vAA <- vBB[vCC]. + * + * Arrays of long/double are 64-bit aligned. + */ + /* aget-wide vAA, vBB, vCC */ + FETCH(a0, 1) # a0 <- CCBB + GET_OPA(rOBJ) # rOBJ <- AA + and a2, a0, 255 # a2 <- BB + srl a3, a0, 8 # a3 <- CC + GET_VREG(a0, a2) # a0 <- vBB (array object) + GET_VREG(a1, a3) # a1 <- vCC (requested index) + # null array object? + beqz a0, common_errNullObject # yes, bail + LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length + EAS3(a0, a0, a1) # a0 <- arrayObj + index*width + bgeu a1, a3, common_errArrayIndex # index >= length, bail + + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + LOAD64_off(a2, a3, a0, MIRROR_WIDE_ARRAY_DATA_OFFSET) + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG64_GOTO(a2, a3, rOBJ, t0) # vAA/vAA+1 <- a2/a3 + +%def op_aput(store="sw", shift="2", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"): + + /* + * Array put, 32 bits or less. vBB[vCC] <- vAA. + * + * for: aput, aput-boolean, aput-byte, aput-char, aput-short + * + * NOTE: this assumes data offset for arrays is the same for all non-wide types. + * If this changes, specialize. + */ + /* op vAA, vBB, vCC */ + FETCH_B(a2, 1, 0) # a2 <- BB + GET_OPA(rOBJ) # rOBJ <- AA + FETCH_B(a3, 1, 1) # a3 <- CC + GET_VREG(a0, a2) # a0 <- vBB (array object) + GET_VREG(a1, a3) # a1 <- vCC (requested index) + # null array object? + beqz a0, common_errNullObject # yes, bail + LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length + EASN(a0, a0, a1, $shift) # a0 <- arrayObj + index*width + bgeu a1, a3, common_errArrayIndex # index >= length, bail + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + GET_VREG(a2, rOBJ) # a2 <- vAA + GET_INST_OPCODE(t0) # extract opcode from rINST + GET_OPCODE_TARGET(t0) + $store a2, $data_offset(a0) # vBB[vCC] <- a2 + JR(t0) # jump to next instruction + +%def op_aput_boolean(): +% op_aput(store="sb", shift="0", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") + +%def op_aput_byte(): +% op_aput(store="sb", shift="0", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") + +%def op_aput_char(): +% op_aput(store="sh", shift="1", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") + +%def op_aput_object(): + /* + * Store an object into an array. vBB[vCC] <- vAA. + * + */ + /* op vAA, vBB, vCC */ + EXPORT_PC() + addu a0, rFP, OFF_FP_SHADOWFRAME + move a1, rPC + move a2, rINST + JAL(MterpAputObject) + beqz v0, MterpPossibleException + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + GOTO_OPCODE(t0) # jump to next instruction + +%def op_aput_short(): +% op_aput(store="sh", shift="1", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") + +%def op_aput_wide(): + /* + * Array put, 64 bits. vBB[vCC] <- vAA. + */ + /* aput-wide vAA, vBB, vCC */ + FETCH(a0, 1) # a0 <- CCBB + GET_OPA(t0) # t0 <- AA + and a2, a0, 255 # a2 <- BB + srl a3, a0, 8 # a3 <- CC + GET_VREG(a0, a2) # a0 <- vBB (array object) + GET_VREG(a1, a3) # a1 <- vCC (requested index) + # null array object? + beqz a0, common_errNullObject # yes, bail + LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length + EAS3(a0, a0, a1) # a0 <- arrayObj + index*width + EAS2(rOBJ, rFP, t0) # rOBJ <- &fp[AA] + # compare unsigned index, length + bgeu a1, a3, common_errArrayIndex # index >= length, bail + + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + LOAD64(a2, a3, rOBJ) # a2/a3 <- vAA/vAA+1 + GET_INST_OPCODE(t0) # extract opcode from rINST + GET_OPCODE_TARGET(t0) + STORE64_off(a2, a3, a0, MIRROR_WIDE_ARRAY_DATA_OFFSET) # a2/a3 <- vBB[vCC] + JR(t0) # jump to next instruction + +%def op_array_length(): + /* + * Return the length of an array. + */ + /* array-length vA, vB */ + GET_OPB(a1) # a1 <- B + GET_OPA4(a2) # a2 <- A+ + GET_VREG(a0, a1) # a0 <- vB (object ref) + # is object null? + beqz a0, common_errNullObject # yup, fail + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + LOAD_base_offMirrorArray_length(a3, a0) # a3 <- array length + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG_GOTO(a3, a2, t0) # vA <- length + +%def op_fill_array_data(): + /* fill-array-data vAA, +BBBBBBBB */ + EXPORT_PC() + FETCH(a1, 1) # a1 <- bbbb (lo) + FETCH(a0, 2) # a0 <- BBBB (hi) + GET_OPA(a3) # a3 <- AA + INSERT_HIGH_HALF(a1, a0) # a1 <- BBBBbbbb + GET_VREG(a0, a3) # a0 <- vAA (array object) + EAS1(a1, rPC, a1) # a1 <- PC + BBBBbbbb*2 (array data off.) + JAL(MterpFillArrayData) # v0 <- Mterp(obj, payload) + beqz v0, MterpPossibleException # has exception + FETCH_ADVANCE_INST(3) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + GOTO_OPCODE(t0) # jump to next instruction + +%def op_filled_new_array(helper="MterpFilledNewArray"): + /* + * Create a new array with elements filled from registers. + * + * for: filled-new-array, filled-new-array/range + */ + /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ + /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ + .extern $helper + EXPORT_PC() + addu a0, rFP, OFF_FP_SHADOWFRAME # a0 <- shadow frame + move a1, rPC + move a2, rSELF + JAL($helper) # v0 <- helper(shadow_frame, pc, self) + beqz v0, MterpPossibleException # has exception + FETCH_ADVANCE_INST(3) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + GOTO_OPCODE(t0) # jump to next instruction + +%def op_filled_new_array_range(): +% op_filled_new_array(helper="MterpFilledNewArrayRange") + +%def op_new_array(): + /* + * Allocate an array of objects, specified with the array class + * and a count. + * + * The verifier guarantees that this is an array class, so we don't + * check for it here. + */ + /* new-array vA, vB, class@CCCC */ + EXPORT_PC() + addu a0, rFP, OFF_FP_SHADOWFRAME + move a1, rPC + move a2, rINST + move a3, rSELF + JAL(MterpNewArray) + beqz v0, MterpPossibleException + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + GOTO_OPCODE(t0) # jump to next instruction diff --git a/runtime/interpreter/mterp/mips/bincmp.S b/runtime/interpreter/mterp/mips/bincmp.S deleted file mode 100644 index b4b671fd95..0000000000 --- a/runtime/interpreter/mterp/mips/bincmp.S +++ /dev/null @@ -1,19 +0,0 @@ -%def bincmp(condition=""): - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - GET_OPA4(a0) # a0 <- A+ - GET_OPB(a1) # a1 <- B - GET_VREG(a3, a1) # a3 <- vB - GET_VREG(a0, a0) # a0 <- vA - FETCH_S(rINST, 1) # rINST<- branch offset, in code units - b${condition} a0, a3, MterpCommonTakenBranchNoFlags # compare (vA, vB) - li t0, JIT_CHECK_OSR - beq rPROFILE, t0, .L_check_not_taken_osr - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction diff --git a/runtime/interpreter/mterp/mips/binop.S b/runtime/interpreter/mterp/mips/binop.S deleted file mode 100644 index 062b22da87..0000000000 --- a/runtime/interpreter/mterp/mips/binop.S +++ /dev/null @@ -1,32 +0,0 @@ -%def binop(preinstr="", result="a0", chkzero="0", instr=""): - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - srl a3, a0, 8 # a3 <- CC - and a2, a0, 255 # a2 <- BB - GET_VREG(a1, a3) # a1 <- vCC - GET_VREG(a0, a2) # a0 <- vBB - .if $chkzero - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - $preinstr # optional op - $instr # $result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO($result, rOBJ, t0) # vAA <- $result diff --git a/runtime/interpreter/mterp/mips/binop2addr.S b/runtime/interpreter/mterp/mips/binop2addr.S deleted file mode 100644 index 89af6e1eea..0000000000 --- a/runtime/interpreter/mterp/mips/binop2addr.S +++ /dev/null @@ -1,28 +0,0 @@ -%def binop2addr(preinstr="", result="a0", chkzero="0", instr=""): - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a0, rOBJ) # a0 <- vA - GET_VREG(a1, a3) # a1 <- vB - .if $chkzero - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - $preinstr # optional op - $instr # $result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO($result, rOBJ, t0) # vA <- $result diff --git a/runtime/interpreter/mterp/mips/binopLit16.S b/runtime/interpreter/mterp/mips/binopLit16.S deleted file mode 100644 index 9ae0da79e9..0000000000 --- a/runtime/interpreter/mterp/mips/binopLit16.S +++ /dev/null @@ -1,28 +0,0 @@ -%def binopLit16(preinstr="", result="a0", chkzero="0", instr=""): - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, +CCCC */ - FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) - GET_OPB(a2) # a2 <- B - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_VREG(a0, a2) # a0 <- vB - .if $chkzero - # cmp a1, 0; is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - $preinstr # optional op - $instr # $result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO($result, rOBJ, t0) # vA <- $result diff --git a/runtime/interpreter/mterp/mips/binopLit8.S b/runtime/interpreter/mterp/mips/binopLit8.S deleted file mode 100644 index ecf08c2d0c..0000000000 --- a/runtime/interpreter/mterp/mips/binopLit8.S +++ /dev/null @@ -1,30 +0,0 @@ -%def binopLit8(preinstr="", result="a0", chkzero="0", instr=""): - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, +CC */ - FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a3, 255 # a2 <- BB - GET_VREG(a0, a2) # a0 <- vBB - sra a1, a3, 8 # a1 <- ssssssCC (sign extended) - .if $chkzero - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - $preinstr # optional op - $instr # $result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO($result, rOBJ, t0) # vAA <- $result diff --git a/runtime/interpreter/mterp/mips/binopWide.S b/runtime/interpreter/mterp/mips/binopWide.S deleted file mode 100644 index 5768e95c48..0000000000 --- a/runtime/interpreter/mterp/mips/binopWide.S +++ /dev/null @@ -1,34 +0,0 @@ -%def binopWide(preinstr="", result0="a0", result1="a1", chkzero="0", arg0="a0", arg1="a1", arg2="a2", arg3="a3", instr=""): - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0-a1 op a2-a3". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register pair other than a0-a1, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a2-a3). Useful for integer division and modulus. - * - * for: add-long, sub-long, div-long, rem-long, and-long, or-long, - * xor-long - * - * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 # a3 <- CC - EAS2(a2, rFP, a2) # a2 <- &fp[BB] - EAS2(t1, rFP, a3) # a3 <- &fp[CC] - LOAD64($arg0, $arg1, a2) # a0/a1 <- vBB/vBB+1 - LOAD64($arg2, $arg3, t1) # a2/a3 <- vCC/vCC+1 - .if $chkzero - or t0, $arg2, $arg3 # second arg (a2-a3) is zero? - beqz t0, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - $preinstr # optional op - $instr # result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO($result0, $result1, rOBJ, t0) # vAA/vAA+1 <- $result0/$result1 diff --git a/runtime/interpreter/mterp/mips/binopWide2addr.S b/runtime/interpreter/mterp/mips/binopWide2addr.S deleted file mode 100644 index 4e00c81961..0000000000 --- a/runtime/interpreter/mterp/mips/binopWide2addr.S +++ /dev/null @@ -1,30 +0,0 @@ -%def binopWide2addr(preinstr="", result0="a0", result1="a1", chkzero="0", arg0="a0", arg1="a1", arg2="a2", arg3="a3", instr=""): - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0-a1 op a2-a3". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register pair other than a0-a1, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a2-a3). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a1) # a1 <- B - EAS2(a1, rFP, a1) # a1 <- &fp[B] - EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] - LOAD64($arg2, $arg3, a1) # a2/a3 <- vB/vB+1 - LOAD64($arg0, $arg1, t0) # a0/a1 <- vA/vA+1 - .if $chkzero - or t0, $arg2, $arg3 # second arg (a2-a3) is zero? - beqz t0, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - $preinstr # optional op - $instr # result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO($result0, $result1, rOBJ, t0) # vA/vA+1 <- $result0/$result1 diff --git a/runtime/interpreter/mterp/mips/const.S b/runtime/interpreter/mterp/mips/const.S deleted file mode 100644 index 403dfc7389..0000000000 --- a/runtime/interpreter/mterp/mips/const.S +++ /dev/null @@ -1,17 +0,0 @@ -%def const(helper="UndefinedConstHandler"): - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern $helper - EXPORT_PC() - FETCH(a0, 1) # a0 <- BBBB - GET_OPA(a1) # a1 <- AA - addu a2, rFP, OFF_FP_SHADOWFRAME # a2 <- shadow frame - move a3, rSELF - JAL($helper) # v0 <- Mterp(index, tgt_reg, shadow_frame, self) - PREFETCH_INST(2) # load rINST - bnez v0, MterpPossibleException - ADVANCE(2) # advance rPC - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction diff --git a/runtime/interpreter/mterp/mips/control_flow.S b/runtime/interpreter/mterp/mips/control_flow.S new file mode 100644 index 0000000000..88e1f0ed4b --- /dev/null +++ b/runtime/interpreter/mterp/mips/control_flow.S @@ -0,0 +1,214 @@ +%def bincmp(condition=""): + /* + * Generic two-operand compare-and-branch operation. Provide a "condition" + * fragment that specifies the comparison to perform. + * + * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le + */ + /* if-cmp vA, vB, +CCCC */ + GET_OPA4(a0) # a0 <- A+ + GET_OPB(a1) # a1 <- B + GET_VREG(a3, a1) # a3 <- vB + GET_VREG(a0, a0) # a0 <- vA + FETCH_S(rINST, 1) # rINST<- branch offset, in code units + b${condition} a0, a3, MterpCommonTakenBranchNoFlags # compare (vA, vB) + li t0, JIT_CHECK_OSR + beq rPROFILE, t0, .L_check_not_taken_osr + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + GOTO_OPCODE(t0) # jump to next instruction + +%def zcmp(condition=""): + /* + * Generic one-operand compare-and-branch operation. Provide a "condition" + * fragment that specifies the comparison to perform. + * + * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez + */ + /* if-cmp vAA, +BBBB */ + GET_OPA(a0) # a0 <- AA + GET_VREG(a0, a0) # a0 <- vAA + FETCH_S(rINST, 1) # rINST <- branch offset, in code units + b${condition} a0, zero, MterpCommonTakenBranchNoFlags + li t0, JIT_CHECK_OSR # possible OSR re-entry? + beq rPROFILE, t0, .L_check_not_taken_osr + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + GOTO_OPCODE(t0) # jump to next instruction + +%def op_goto(): + /* + * Unconditional branch, 8-bit offset. + * + * The branch distance is a signed code-unit offset, which we need to + * double to get a byte offset. + */ + /* goto +AA */ + sll a0, rINST, 16 # a0 <- AAxx0000 + sra rINST, a0, 24 # rINST <- ssssssAA (sign-extended) + b MterpCommonTakenBranchNoFlags + +%def op_goto_16(): + /* + * Unconditional branch, 16-bit offset. + * + * The branch distance is a signed code-unit offset, which we need to + * double to get a byte offset. + */ + /* goto/16 +AAAA */ + FETCH_S(rINST, 1) # rINST <- ssssAAAA (sign-extended) + b MterpCommonTakenBranchNoFlags + +%def op_goto_32(): + /* + * Unconditional branch, 32-bit offset. + * + * The branch distance is a signed code-unit offset, which we need to + * double to get a byte offset. + * + * Unlike most opcodes, this one is allowed to branch to itself, so + * our "backward branch" test must be "<=0" instead of "<0". + */ + /* goto/32 +AAAAAAAA */ + FETCH(rINST, 1) # rINST <- aaaa (lo) + FETCH(a1, 2) # a1 <- AAAA (hi) + INSERT_HIGH_HALF(rINST, a1) # rINST <- AAAAaaaa + b MterpCommonTakenBranchNoFlags + +%def op_if_eq(): +% bincmp(condition="eq") + +%def op_if_eqz(): +% zcmp(condition="eq") + +%def op_if_ge(): +% bincmp(condition="ge") + +%def op_if_gez(): +% zcmp(condition="ge") + +%def op_if_gt(): +% bincmp(condition="gt") + +%def op_if_gtz(): +% zcmp(condition="gt") + +%def op_if_le(): +% bincmp(condition="le") + +%def op_if_lez(): +% zcmp(condition="le") + +%def op_if_lt(): +% bincmp(condition="lt") + +%def op_if_ltz(): +% zcmp(condition="lt") + +%def op_if_ne(): +% bincmp(condition="ne") + +%def op_if_nez(): +% zcmp(condition="ne") + +%def op_packed_switch(func="MterpDoPackedSwitch"): + /* + * Handle a packed-switch or sparse-switch instruction. In both cases + * we decode it and hand it off to a helper function. + * + * We don't really expect backward branches in a switch statement, but + * they're perfectly legal, so we check for them here. + * + * for: packed-switch, sparse-switch + */ + /* op vAA, +BBBB */ + FETCH(a0, 1) # a0 <- bbbb (lo) + FETCH(a1, 2) # a1 <- BBBB (hi) + GET_OPA(a3) # a3 <- AA + INSERT_HIGH_HALF(a0, a1) # a0 <- BBBBbbbb + GET_VREG(a1, a3) # a1 <- vAA + EAS1(a0, rPC, a0) # a0 <- PC + BBBBbbbb*2 + JAL($func) # a0 <- code-unit branch offset + move rINST, v0 + b MterpCommonTakenBranchNoFlags + +%def op_return(): + /* + * Return a 32-bit value. + * + * for: return, return-object + */ + /* op vAA */ + .extern MterpThreadFenceForConstructor + JAL(MterpThreadFenceForConstructor) + lw ra, THREAD_FLAGS_OFFSET(rSELF) + move a0, rSELF + and ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST + beqz ra, 1f + JAL(MterpSuspendCheck) # (self) +1: + GET_OPA(a2) # a2 <- AA + GET_VREG(v0, a2) # v0 <- vAA + move v1, zero + b MterpReturn + +%def op_return_object(): +% op_return() + +%def op_return_void(): + .extern MterpThreadFenceForConstructor + JAL(MterpThreadFenceForConstructor) + lw ra, THREAD_FLAGS_OFFSET(rSELF) + move a0, rSELF + and ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST + beqz ra, 1f + JAL(MterpSuspendCheck) # (self) +1: + move v0, zero + move v1, zero + b MterpReturn + +%def op_return_void_no_barrier(): + lw ra, THREAD_FLAGS_OFFSET(rSELF) + move a0, rSELF + and ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST + beqz ra, 1f + JAL(MterpSuspendCheck) # (self) +1: + move v0, zero + move v1, zero + b MterpReturn + +%def op_return_wide(): + /* + * Return a 64-bit value. + */ + /* return-wide vAA */ + .extern MterpThreadFenceForConstructor + JAL(MterpThreadFenceForConstructor) + lw ra, THREAD_FLAGS_OFFSET(rSELF) + move a0, rSELF + and ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST + beqz ra, 1f + JAL(MterpSuspendCheck) # (self) +1: + GET_OPA(a2) # a2 <- AA + EAS2(a2, rFP, a2) # a2 <- &fp[AA] + LOAD64(v0, v1, a2) # v0/v1 <- vAA/vAA+1 + b MterpReturn + +%def op_sparse_switch(): +% op_packed_switch(func="MterpDoSparseSwitch") + +%def op_throw(): + /* + * Throw an exception object in the current thread. + */ + /* throw vAA */ + EXPORT_PC() # exception handler can throw + GET_OPA(a2) # a2 <- AA + GET_VREG(a1, a2) # a1 <- vAA (exception object) + # null object? + beqz a1, common_errNullObject # yes, throw an NPE instead + sw a1, THREAD_EXCEPTION_OFFSET(rSELF) # thread->exception <- obj + b MterpException diff --git a/runtime/interpreter/mterp/mips/entry.S b/runtime/interpreter/mterp/mips/entry.S deleted file mode 100644 index e40fc0203f..0000000000 --- a/runtime/interpreter/mterp/mips/entry.S +++ /dev/null @@ -1,76 +0,0 @@ -%def entry(): -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -/* - * Interpreter entry point. - */ - - .text - .align 2 - .global ExecuteMterpImpl - .ent ExecuteMterpImpl - .frame sp, STACK_SIZE, ra -/* - * On entry: - * a0 Thread* self - * a1 dex_instructions - * a2 ShadowFrame - * a3 JValue* result_register - * - */ - -ExecuteMterpImpl: - .cfi_startproc - .set noreorder - .cpload t9 - .set reorder -/* Save to the stack. Frame size = STACK_SIZE */ - STACK_STORE_FULL() -/* This directive will make sure all subsequent jal restore gp at a known offset */ - .cprestore STACK_OFFSET_GP - - /* Remember the return register */ - sw a3, SHADOWFRAME_RESULT_REGISTER_OFFSET(a2) - - /* Remember the dex instruction pointer */ - sw a1, SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET(a2) - - /* set up "named" registers */ - move rSELF, a0 - lw a0, SHADOWFRAME_NUMBER_OF_VREGS_OFFSET(a2) - addu rFP, a2, SHADOWFRAME_VREGS_OFFSET # point to vregs. - EAS2(rREFS, rFP, a0) # point to reference array in shadow frame - lw a0, SHADOWFRAME_DEX_PC_OFFSET(a2) # Get starting dex_pc - EAS1(rPC, a1, a0) # Create direct pointer to 1st dex opcode - CFI_DEFINE_DEX_PC_WITH_OFFSET(CFI_TMP, CFI_DEX, 0) - - EXPORT_PC() - - /* Starting ibase */ - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) - - /* Set up for backwards branches & osr profiling */ - lw a0, OFF_FP_METHOD(rFP) - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rSELF - JAL(MterpSetUpHotnessCountdown) # (method, shadow_frame, self) - move rPROFILE, v0 # Starting hotness countdown to rPROFILE - - /* start executing the instruction at rPC */ - FETCH_INST() # load rINST from rPC - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - /* NOTE: no fallthrough */ diff --git a/runtime/interpreter/mterp/mips/fallback.S b/runtime/interpreter/mterp/mips/fallback.S deleted file mode 100644 index 6133d9f825..0000000000 --- a/runtime/interpreter/mterp/mips/fallback.S +++ /dev/null @@ -1,3 +0,0 @@ -%def fallback(): -/* Transfer stub to alternate interpreter */ - b MterpFallback diff --git a/runtime/interpreter/mterp/mips/fbinop.S b/runtime/interpreter/mterp/mips/fbinop.S deleted file mode 100644 index 7cbf73fda8..0000000000 --- a/runtime/interpreter/mterp/mips/fbinop.S +++ /dev/null @@ -1,19 +0,0 @@ -%def fbinop(instr=""): - /* - * Generic 32-bit binary float operation. - * - * For: add-fp, sub-fp, mul-fp, div-fp, rem-fp - */ - - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - srl a3, a0, 8 # a3 <- CC - and a2, a0, 255 # a2 <- BB - GET_VREG_F(fa1, a3) # a1 <- vCC - GET_VREG_F(fa0, a2) # a0 <- vBB - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - $instr # f0 = result - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_F_GOTO(fv0, rOBJ, t0) # vAA <- fv0 diff --git a/runtime/interpreter/mterp/mips/fbinop2addr.S b/runtime/interpreter/mterp/mips/fbinop2addr.S deleted file mode 100644 index ea9970fb0b..0000000000 --- a/runtime/interpreter/mterp/mips/fbinop2addr.S +++ /dev/null @@ -1,19 +0,0 @@ -%def fbinop2addr(instr=""): - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" - * that specifies an instruction that performs "fv0 = fa0 op fa1". - * This could be an MIPS instruction or a function call. - * - * For: add-float/2addr, sub-float/2addr, mul-float/2addr, - * div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG_F(fa0, rOBJ) - GET_VREG_F(fa1, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - $instr - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_F_GOTO(fv0, rOBJ, t0) # vA <- result diff --git a/runtime/interpreter/mterp/mips/fbinopWide.S b/runtime/interpreter/mterp/mips/fbinopWide.S deleted file mode 100644 index 1b5c0c1387..0000000000 --- a/runtime/interpreter/mterp/mips/fbinopWide.S +++ /dev/null @@ -1,24 +0,0 @@ -%def fbinopWide(instr=""): - /* - * Generic 64-bit floating-point binary operation. Provide an "instr" - * line that specifies an instruction that performs "fv0 = fa0 op fa1". - * This could be an MIPS instruction or a function call. - * - * for: add-double, sub-double, mul-double, div-double, - * rem-double - * - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 # a3 <- CC - EAS2(a2, rFP, a2) # a2 <- &fp[BB] - EAS2(t1, rFP, a3) # a3 <- &fp[CC] - LOAD64_F(fa0, fa0f, a2) - LOAD64_F(fa1, fa1f, t1) - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - $instr - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vAA/vAA+1 <- fv0 diff --git a/runtime/interpreter/mterp/mips/fbinopWide2addr.S b/runtime/interpreter/mterp/mips/fbinopWide2addr.S deleted file mode 100644 index e36f1f874d..0000000000 --- a/runtime/interpreter/mterp/mips/fbinopWide2addr.S +++ /dev/null @@ -1,22 +0,0 @@ -%def fbinopWide2addr(instr=""): - /* - * Generic 64-bit floating-point "/2addr" binary operation. - * Provide an "instr" line that specifies an instruction that - * performs "fv0 = fa0 op fa1". - * This could be an MIPS instruction or a function call. - * - * For: add-double/2addr, sub-double/2addr, mul-double/2addr, - * div-double/2addr, rem-double/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a1) # a1 <- B - EAS2(a1, rFP, a1) # a1 <- &fp[B] - EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] - LOAD64_F(fa0, fa0f, t0) - LOAD64_F(fa1, fa1f, a1) - - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - $instr - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vA/vA+1 <- fv0 diff --git a/runtime/interpreter/mterp/mips/field.S b/runtime/interpreter/mterp/mips/field.S deleted file mode 100644 index d61b06afd4..0000000000 --- a/runtime/interpreter/mterp/mips/field.S +++ /dev/null @@ -1,2 +0,0 @@ -%def field(helper=""): -TODO diff --git a/runtime/interpreter/mterp/mips/floating_point.S b/runtime/interpreter/mterp/mips/floating_point.S new file mode 100644 index 0000000000..6f0dda3dbc --- /dev/null +++ b/runtime/interpreter/mterp/mips/floating_point.S @@ -0,0 +1,518 @@ +%def fbinop(instr=""): + /* + * Generic 32-bit binary float operation. + * + * For: add-fp, sub-fp, mul-fp, div-fp, rem-fp + */ + + /* binop vAA, vBB, vCC */ + FETCH(a0, 1) # a0 <- CCBB + GET_OPA(rOBJ) # rOBJ <- AA + srl a3, a0, 8 # a3 <- CC + and a2, a0, 255 # a2 <- BB + GET_VREG_F(fa1, a3) # a1 <- vCC + GET_VREG_F(fa0, a2) # a0 <- vBB + + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + $instr # f0 = result + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG_F_GOTO(fv0, rOBJ, t0) # vAA <- fv0 + +%def fbinop2addr(instr=""): + /* + * Generic 32-bit "/2addr" binary operation. Provide an "instr" + * that specifies an instruction that performs "fv0 = fa0 op fa1". + * This could be an MIPS instruction or a function call. + * + * For: add-float/2addr, sub-float/2addr, mul-float/2addr, + * div-float/2addr, rem-float/2addr + */ + /* binop/2addr vA, vB */ + GET_OPA4(rOBJ) # rOBJ <- A+ + GET_OPB(a3) # a3 <- B + GET_VREG_F(fa0, rOBJ) + GET_VREG_F(fa1, a3) + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + + $instr + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG_F_GOTO(fv0, rOBJ, t0) # vA <- result + +%def fbinopWide(instr=""): + /* + * Generic 64-bit floating-point binary operation. Provide an "instr" + * line that specifies an instruction that performs "fv0 = fa0 op fa1". + * This could be an MIPS instruction or a function call. + * + * for: add-double, sub-double, mul-double, div-double, + * rem-double + * + */ + /* binop vAA, vBB, vCC */ + FETCH(a0, 1) # a0 <- CCBB + GET_OPA(rOBJ) # rOBJ <- AA + and a2, a0, 255 # a2 <- BB + srl a3, a0, 8 # a3 <- CC + EAS2(a2, rFP, a2) # a2 <- &fp[BB] + EAS2(t1, rFP, a3) # a3 <- &fp[CC] + LOAD64_F(fa0, fa0f, a2) + LOAD64_F(fa1, fa1f, t1) + + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + $instr + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vAA/vAA+1 <- fv0 + +%def fbinopWide2addr(instr=""): + /* + * Generic 64-bit floating-point "/2addr" binary operation. + * Provide an "instr" line that specifies an instruction that + * performs "fv0 = fa0 op fa1". + * This could be an MIPS instruction or a function call. + * + * For: add-double/2addr, sub-double/2addr, mul-double/2addr, + * div-double/2addr, rem-double/2addr + */ + /* binop/2addr vA, vB */ + GET_OPA4(rOBJ) # rOBJ <- A+ + GET_OPB(a1) # a1 <- B + EAS2(a1, rFP, a1) # a1 <- &fp[B] + EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] + LOAD64_F(fa0, fa0f, t0) + LOAD64_F(fa1, fa1f, a1) + + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + $instr + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vA/vA+1 <- fv0 + +%def funop(instr=""): + /* + * Generic 32-bit floating-point unary operation. Provide an "instr" + * line that specifies an instruction that performs "fv0 = op fa0". + * This could be a MIPS instruction or a function call. + * + * for: int-to-float + */ + /* unop vA, vB */ + GET_OPB(a3) # a3 <- B + GET_OPA4(rOBJ) # rOBJ <- A+ + GET_VREG_F(fa0, a3) + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + $instr + GET_INST_OPCODE(t1) # extract opcode from rINST + SET_VREG_F_GOTO(fv0, rOBJ, t1) # vA <- fv0 + +%def funopWider(instr=""): + /* + * Generic 32bit-to-64bit floating-point unary operation. Provide an "instr" + * line that specifies an instruction that performs "fv0 = op fa0". + * + * For: int-to-double, float-to-double + */ + /* unop vA, vB */ + GET_OPA4(rOBJ) # rOBJ <- A+ + GET_OPB(a3) # a3 <- B + GET_VREG_F(fa0, a3) + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + $instr + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vA/vA+1 <- fv0 + +%def op_add_double(): +% fbinopWide(instr="add.d fv0, fa0, fa1") + +%def op_add_double_2addr(): +% fbinopWide2addr(instr="add.d fv0, fa0, fa1") + +%def op_add_float(): +% fbinop(instr="add.s fv0, fa0, fa1") + +%def op_add_float_2addr(): +% fbinop2addr(instr="add.s fv0, fa0, fa1") + +%def op_cmpg_double(): +% op_cmpl_double(gt_bias="1") + +%def op_cmpg_float(): +% op_cmpl_float(gt_bias="1") + +%def op_cmpl_double(gt_bias="0"): + /* + * Compare two floating-point values. Puts 0(==), 1(>), or -1(<) + * into the destination register based on the comparison results. + * + * For: cmpl-double, cmpg-double + */ + /* op vAA, vBB, vCC */ + + FETCH(a0, 1) # a0 <- CCBB + and rOBJ, a0, 255 # rOBJ <- BB + srl t0, a0, 8 # t0 <- CC + EAS2(rOBJ, rFP, rOBJ) # rOBJ <- &fp[BB] + EAS2(t0, rFP, t0) # t0 <- &fp[CC] + LOAD64_F(ft0, ft0f, rOBJ) + LOAD64_F(ft1, ft1f, t0) +#ifdef MIPS32REVGE6 + cmp.eq.d ft2, ft0, ft1 + li rTEMP, 0 + bc1nez ft2, 1f # done if vBB == vCC (ordered) + .if $gt_bias + cmp.lt.d ft2, ft0, ft1 + li rTEMP, -1 + bc1nez ft2, 1f # done if vBB < vCC (ordered) + li rTEMP, 1 # vBB > vCC or unordered + .else + cmp.lt.d ft2, ft1, ft0 + li rTEMP, 1 + bc1nez ft2, 1f # done if vBB > vCC (ordered) + li rTEMP, -1 # vBB < vCC or unordered + .endif +#else + c.eq.d fcc0, ft0, ft1 + li rTEMP, 0 + bc1t fcc0, 1f # done if vBB == vCC (ordered) + .if $gt_bias + c.olt.d fcc0, ft0, ft1 + li rTEMP, -1 + bc1t fcc0, 1f # done if vBB < vCC (ordered) + li rTEMP, 1 # vBB > vCC or unordered + .else + c.olt.d fcc0, ft1, ft0 + li rTEMP, 1 + bc1t fcc0, 1f # done if vBB > vCC (ordered) + li rTEMP, -1 # vBB < vCC or unordered + .endif +#endif +1: + GET_OPA(rOBJ) + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG_GOTO(rTEMP, rOBJ, t0) # vAA <- rTEMP + +%def op_cmpl_float(gt_bias="0"): + /* + * Compare two floating-point values. Puts 0(==), 1(>), or -1(<) + * into the destination register based on the comparison results. + * + * for: cmpl-float, cmpg-float + */ + /* op vAA, vBB, vCC */ + + FETCH(a0, 1) # a0 <- CCBB + and a2, a0, 255 # a2 <- BB + srl a3, a0, 8 + GET_VREG_F(ft0, a2) + GET_VREG_F(ft1, a3) +#ifdef MIPS32REVGE6 + cmp.eq.s ft2, ft0, ft1 + li rTEMP, 0 + bc1nez ft2, 1f # done if vBB == vCC (ordered) + .if $gt_bias + cmp.lt.s ft2, ft0, ft1 + li rTEMP, -1 + bc1nez ft2, 1f # done if vBB < vCC (ordered) + li rTEMP, 1 # vBB > vCC or unordered + .else + cmp.lt.s ft2, ft1, ft0 + li rTEMP, 1 + bc1nez ft2, 1f # done if vBB > vCC (ordered) + li rTEMP, -1 # vBB < vCC or unordered + .endif +#else + c.eq.s fcc0, ft0, ft1 + li rTEMP, 0 + bc1t fcc0, 1f # done if vBB == vCC (ordered) + .if $gt_bias + c.olt.s fcc0, ft0, ft1 + li rTEMP, -1 + bc1t fcc0, 1f # done if vBB < vCC (ordered) + li rTEMP, 1 # vBB > vCC or unordered + .else + c.olt.s fcc0, ft1, ft0 + li rTEMP, 1 + bc1t fcc0, 1f # done if vBB > vCC (ordered) + li rTEMP, -1 # vBB < vCC or unordered + .endif +#endif +1: + GET_OPA(rOBJ) + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG_GOTO(rTEMP, rOBJ, t0) # vAA <- rTEMP + +%def op_div_double(): +% fbinopWide(instr="div.d fv0, fa0, fa1") + +%def op_div_double_2addr(): +% fbinopWide2addr(instr="div.d fv0, fa0, fa1") + +%def op_div_float(): +% fbinop(instr="div.s fv0, fa0, fa1") + +%def op_div_float_2addr(): +% fbinop2addr(instr="div.s fv0, fa0, fa1") + +%def op_double_to_float(): +% unopNarrower(instr="cvt.s.d fv0, fa0") + +%def op_double_to_int(): + /* + * double-to-int + * + * We have to clip values to int min/max per the specification. The + * expected common case is a "reasonable" value that converts directly + * to modest integer. The EABI convert function isn't doing this for us + * for pre-R6. + */ + /* unop vA, vB */ + GET_OPB(a3) # a3 <- B + GET_OPA4(rOBJ) # rOBJ <- A+ + EAS2(a3, rFP, a3) # a3 <- &fp[B] + LOAD64_F(fa0, fa0f, a3) + FETCH_ADVANCE_INST(1) # advance rPC, load rINST +#ifndef MIPS32REVGE6 + li t0, INT_MIN_AS_DOUBLE_HIGH + mtc1 zero, fa1 + MOVE_TO_FPU_HIGH(t0, fa1, fa1f) + c.ole.d fcc0, fa1, fa0 +#endif + GET_INST_OPCODE(t1) # extract opcode from rINST +#ifndef MIPS32REVGE6 + bc1t fcc0, 1f # if INT_MIN <= vB, proceed to truncation + c.eq.d fcc0, fa0, fa0 + mtc1 zero, fa0 + MOVE_TO_FPU_HIGH(zero, fa0, fa0f) + movt.d fa0, fa1, fcc0 # fa0 = ordered(vB) ? INT_MIN_AS_DOUBLE : 0 +1: +#endif + trunc.w.d fa0, fa0 + SET_VREG_F_GOTO(fa0, rOBJ, t1) # vA <- result + +%def op_double_to_long(): + /* + * double-to-long + * + * We have to clip values to long min/max per the specification. The + * expected common case is a "reasonable" value that converts directly + * to modest integer. The EABI convert function isn't doing this for us + * for pre-R6. + */ + /* unop vA, vB */ + GET_OPA4(rOBJ) # rOBJ <- A+ + GET_OPB(a3) # a3 <- B + EAS2(a3, rFP, a3) # a3 <- &fp[B] + LOAD64_F(fa0, fa0f, a3) + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + +#ifdef MIPS32REVGE6 + GET_INST_OPCODE(t1) # extract opcode from rINST + trunc.l.d fa0, fa0 + SET_VREG64_F_GOTO(fa0, fa0f, rOBJ, t1) # vA <- result +#else + c.eq.d fcc0, fa0, fa0 + li rRESULT0, 0 + li rRESULT1, 0 + bc1f fcc0, .L${opcode}_get_opcode + + li t0, LONG_MIN_AS_DOUBLE_HIGH + mtc1 zero, fa1 + MOVE_TO_FPU_HIGH(t0, fa1, fa1f) + c.ole.d fcc0, fa0, fa1 + li rRESULT1, LONG_MIN_HIGH + bc1t fcc0, .L${opcode}_get_opcode + + neg.d fa1, fa1 + c.ole.d fcc0, fa1, fa0 + nor rRESULT0, rRESULT0, zero + nor rRESULT1, rRESULT1, zero + bc1t fcc0, .L${opcode}_get_opcode + + JAL(__fixdfdi) + GET_INST_OPCODE(t1) # extract opcode from rINST + b .L${opcode}_set_vreg +#endif +%def op_double_to_long_sister_code(): + +#ifndef MIPS32REVGE6 +.L${opcode}_get_opcode: + GET_INST_OPCODE(t1) # extract opcode from rINST +.L${opcode}_set_vreg: + SET_VREG64_GOTO(rRESULT0, rRESULT1, rOBJ, t1) # vA/vA+1 <- v0/v1 +#endif + +%def op_float_to_double(): +% funopWider(instr="cvt.d.s fv0, fa0") + +%def op_float_to_int(): + /* + * float-to-int + * + * We have to clip values to int min/max per the specification. The + * expected common case is a "reasonable" value that converts directly + * to modest integer. The EABI convert function isn't doing this for us + * for pre-R6. + */ + /* unop vA, vB */ + GET_OPB(a3) # a3 <- B + GET_OPA4(rOBJ) # rOBJ <- A+ + GET_VREG_F(fa0, a3) + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + +#ifndef MIPS32REVGE6 + li t0, INT_MIN_AS_FLOAT + mtc1 t0, fa1 + c.ole.s fcc0, fa1, fa0 +#endif + GET_INST_OPCODE(t1) # extract opcode from rINST +#ifndef MIPS32REVGE6 + bc1t fcc0, 1f # if INT_MIN <= vB, proceed to truncation + c.eq.s fcc0, fa0, fa0 + mtc1 zero, fa0 + movt.s fa0, fa1, fcc0 # fa0 = ordered(vB) ? INT_MIN_AS_FLOAT : 0 +1: +#endif + trunc.w.s fa0, fa0 + SET_VREG_F_GOTO(fa0, rOBJ, t1) # vA <- result + +%def op_float_to_long(): + /* + * float-to-long + * + * We have to clip values to long min/max per the specification. The + * expected common case is a "reasonable" value that converts directly + * to modest integer. The EABI convert function isn't doing this for us + * for pre-R6. + */ + /* unop vA, vB */ + GET_OPA4(rOBJ) # rOBJ <- A+ + GET_OPB(a3) # a3 <- B + GET_VREG_F(fa0, a3) + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + +#ifdef MIPS32REVGE6 + GET_INST_OPCODE(t1) # extract opcode from rINST + trunc.l.s fa0, fa0 + SET_VREG64_F_GOTO(fa0, fa0f, rOBJ, t1) # vA <- result +#else + c.eq.s fcc0, fa0, fa0 + li rRESULT0, 0 + li rRESULT1, 0 + bc1f fcc0, .L${opcode}_get_opcode + + li t0, LONG_MIN_AS_FLOAT + mtc1 t0, fa1 + c.ole.s fcc0, fa0, fa1 + li rRESULT1, LONG_MIN_HIGH + bc1t fcc0, .L${opcode}_get_opcode + + neg.s fa1, fa1 + c.ole.s fcc0, fa1, fa0 + nor rRESULT0, rRESULT0, zero + nor rRESULT1, rRESULT1, zero + bc1t fcc0, .L${opcode}_get_opcode + + JAL(__fixsfdi) + GET_INST_OPCODE(t1) # extract opcode from rINST + b .L${opcode}_set_vreg +#endif +%def op_float_to_long_sister_code(): + +#ifndef MIPS32REVGE6 +.L${opcode}_get_opcode: + GET_INST_OPCODE(t1) # extract opcode from rINST +.L${opcode}_set_vreg: + SET_VREG64_GOTO(rRESULT0, rRESULT1, rOBJ, t1) # vA/vA+1 <- v0/v1 +#endif + +%def op_int_to_double(): +% funopWider(instr="cvt.d.w fv0, fa0") + +%def op_int_to_float(): +% funop(instr="cvt.s.w fv0, fa0") + +%def op_long_to_double(): + /* + * long-to-double + */ + /* unop vA, vB */ + GET_OPA4(rOBJ) # rOBJ <- A+ + GET_OPB(a3) # a3 <- B + EAS2(a3, rFP, a3) # a3 <- &fp[B] + +#ifdef MIPS32REVGE6 + LOAD64_F(fv0, fv0f, a3) + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + cvt.d.l fv0, fv0 +#else + LOAD64(rARG0, rARG1, a3) + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + JAL(__floatdidf) # a0/a1 <- op, a2-a3 changed +#endif + + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vA/vA+1 <- result + +%def op_long_to_float(): + /* + * long-to-float + */ + /* unop vA, vB */ + GET_OPB(a3) # a3 <- B + GET_OPA4(rOBJ) # rOBJ <- A+ + EAS2(a3, rFP, a3) # a3 <- &fp[B] + +#ifdef MIPS32REVGE6 + LOAD64_F(fv0, fv0f, a3) + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + cvt.s.l fv0, fv0 +#else + LOAD64(rARG0, rARG1, a3) + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + JAL(__floatdisf) +#endif + + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG_F_GOTO(fv0, rOBJ, t0) # vA <- fv0 + +%def op_mul_double(): +% fbinopWide(instr="mul.d fv0, fa0, fa1") + +%def op_mul_double_2addr(): +% fbinopWide2addr(instr="mul.d fv0, fa0, fa1") + +%def op_mul_float(): +% fbinop(instr="mul.s fv0, fa0, fa1") + +%def op_mul_float_2addr(): +% fbinop2addr(instr="mul.s fv0, fa0, fa1") + +%def op_neg_double(): +% unopWide(instr="addu a1, a1, 0x80000000") + +%def op_neg_float(): +% unop(instr="addu a0, a0, 0x80000000") + +%def op_rem_double(): +% fbinopWide(instr="JAL(fmod)") + +%def op_rem_double_2addr(): +% fbinopWide2addr(instr="JAL(fmod)") + +%def op_rem_float(): +% fbinop(instr="JAL(fmodf)") + +%def op_rem_float_2addr(): +% fbinop2addr(instr="JAL(fmodf)") + +%def op_sub_double(): +% fbinopWide(instr="sub.d fv0, fa0, fa1") + +%def op_sub_double_2addr(): +% fbinopWide2addr(instr="sub.d fv0, fa0, fa1") + +%def op_sub_float(): +% fbinop(instr="sub.s fv0, fa0, fa1") + +%def op_sub_float_2addr(): +% fbinop2addr(instr="sub.s fv0, fa0, fa1") diff --git a/runtime/interpreter/mterp/mips/footer.S b/runtime/interpreter/mterp/mips/footer.S deleted file mode 100644 index 0f641d213b..0000000000 --- a/runtime/interpreter/mterp/mips/footer.S +++ /dev/null @@ -1,289 +0,0 @@ -%def footer(): -/* - * =========================================================================== - * Common subroutines and data - * =========================================================================== - */ - - .text - .align 2 - -/* - * We've detected a condition that will result in an exception, but the exception - * has not yet been thrown. Just bail out to the reference interpreter to deal with it. - * TUNING: for consistency, we may want to just go ahead and handle these here. - */ -common_errDivideByZero: - EXPORT_PC() -#if MTERP_LOGGING - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - JAL(MterpLogDivideByZeroException) -#endif - b MterpCommonFallback - -common_errArrayIndex: - EXPORT_PC() -#if MTERP_LOGGING - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - JAL(MterpLogArrayIndexException) -#endif - b MterpCommonFallback - -common_errNegativeArraySize: - EXPORT_PC() -#if MTERP_LOGGING - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - JAL(MterpLogNegativeArraySizeException) -#endif - b MterpCommonFallback - -common_errNoSuchMethod: - EXPORT_PC() -#if MTERP_LOGGING - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - JAL(MterpLogNoSuchMethodException) -#endif - b MterpCommonFallback - -common_errNullObject: - EXPORT_PC() -#if MTERP_LOGGING - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - JAL(MterpLogNullObjectException) -#endif - b MterpCommonFallback - -common_exceptionThrown: - EXPORT_PC() -#if MTERP_LOGGING - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - JAL(MterpLogExceptionThrownException) -#endif - b MterpCommonFallback - -MterpSuspendFallback: - EXPORT_PC() -#if MTERP_LOGGING - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - lw a2, THREAD_FLAGS_OFFSET(rSELF) - JAL(MterpLogSuspendFallback) -#endif - b MterpCommonFallback - -/* - * If we're here, something is out of the ordinary. If there is a pending - * exception, handle it. Otherwise, roll back and retry with the reference - * interpreter. - */ -MterpPossibleException: - lw a0, THREAD_EXCEPTION_OFFSET(rSELF) - beqz a0, MterpFallback # If exception, fall back to reference interpreter. - /* intentional fallthrough - handle pending exception. */ -/* - * On return from a runtime helper routine, we've found a pending exception. - * Can we handle it here - or need to bail out to caller? - * - */ -MterpException: - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - JAL(MterpHandleException) # (self, shadow_frame) - beqz v0, MterpExceptionReturn # no local catch, back to caller. - lw a0, OFF_FP_DEX_INSTRUCTIONS(rFP) - lw a1, OFF_FP_DEX_PC(rFP) - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) - EAS1(rPC, a0, a1) # generate new dex_pc_ptr - /* Do we need to switch interpreters? */ - JAL(MterpShouldSwitchInterpreters) - bnez v0, MterpFallback - /* resume execution at catch block */ - EXPORT_PC() - FETCH_INST() - GET_INST_OPCODE(t0) - GOTO_OPCODE(t0) - /* NOTE: no fallthrough */ - -/* - * Common handling for branches with support for Jit profiling. - * On entry: - * rINST <= signed offset - * rPROFILE <= signed hotness countdown (expanded to 32 bits) - * - * We have quite a few different cases for branch profiling, OSR detection and - * suspend check support here. - * - * Taken backward branches: - * If profiling active, do hotness countdown and report if we hit zero. - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * Is there a pending suspend request? If so, suspend. - * - * Taken forward branches and not-taken backward branches: - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * - * Our most common case is expected to be a taken backward branch with active jit profiling, - * but no full OSR check and no pending suspend request. - * Next most common case is not-taken branch with no full OSR check. - */ -MterpCommonTakenBranchNoFlags: - bgtz rINST, .L_forward_branch # don't add forward branches to hotness -/* - * We need to subtract 1 from positive values and we should not see 0 here, - * so we may use the result of the comparison with -1. - */ -#if JIT_CHECK_OSR != -1 -# error "JIT_CHECK_OSR must be -1." -#endif - li t0, JIT_CHECK_OSR - beq rPROFILE, t0, .L_osr_check - blt rPROFILE, t0, .L_resume_backward_branch - subu rPROFILE, 1 - beqz rPROFILE, .L_add_batch # counted down to zero - report -.L_resume_backward_branch: - lw ra, THREAD_FLAGS_OFFSET(rSELF) - REFRESH_IBASE() - addu a2, rINST, rINST # a2<- byte offset - FETCH_ADVANCE_INST_RB(a2) # update rPC, load rINST - and ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - bnez ra, .L_suspend_request_pending - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - -.L_suspend_request_pending: - EXPORT_PC() - move a0, rSELF - JAL(MterpSuspendCheck) # (self) - bnez v0, MterpFallback - REFRESH_IBASE() # might have changed during suspend - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - -.L_no_count_backwards: - li t0, JIT_CHECK_OSR # check for possible OSR re-entry - bne rPROFILE, t0, .L_resume_backward_branch -.L_osr_check: - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rINST - EXPORT_PC() - JAL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) - bnez v0, MterpOnStackReplacement - b .L_resume_backward_branch - -.L_forward_branch: - li t0, JIT_CHECK_OSR # check for possible OSR re-entry - beq rPROFILE, t0, .L_check_osr_forward -.L_resume_forward_branch: - add a2, rINST, rINST # a2<- byte offset - FETCH_ADVANCE_INST_RB(a2) # update rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - -.L_check_osr_forward: - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rINST - EXPORT_PC() - JAL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) - bnez v0, MterpOnStackReplacement - b .L_resume_forward_branch - -.L_add_batch: - addu a1, rFP, OFF_FP_SHADOWFRAME - sh rPROFILE, SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET(a1) - lw a0, OFF_FP_METHOD(rFP) - move a2, rSELF - JAL(MterpAddHotnessBatch) # (method, shadow_frame, self) - move rPROFILE, v0 # restore new hotness countdown to rPROFILE - b .L_no_count_backwards - -/* - * Entered from the conditional branch handlers when OSR check request active on - * not-taken path. All Dalvik not-taken conditional branch offsets are 2. - */ -.L_check_not_taken_osr: - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - li a2, 2 - EXPORT_PC() - JAL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) - bnez v0, MterpOnStackReplacement - FETCH_ADVANCE_INST(2) - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - -/* - * On-stack replacement has happened, and now we've returned from the compiled method. - */ -MterpOnStackReplacement: -#if MTERP_LOGGING - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rINST - JAL(MterpLogOSR) -#endif - li v0, 1 # Signal normal return - b MterpDone - -/* - * Bail out to reference interpreter. - */ -MterpFallback: - EXPORT_PC() -#if MTERP_LOGGING - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - JAL(MterpLogFallback) -#endif -MterpCommonFallback: - move v0, zero # signal retry with reference interpreter. - b MterpDone -/* - * We pushed some registers on the stack in ExecuteMterpImpl, then saved - * SP and LR. Here we restore SP, restore the registers, and then restore - * LR to PC. - * - * On entry: - * uint32_t* rFP (should still be live, pointer to base of vregs) - */ -MterpExceptionReturn: - li v0, 1 # signal return to caller. - b MterpDone -MterpReturn: - lw a2, OFF_FP_RESULT_REGISTER(rFP) - sw v0, 0(a2) - sw v1, 4(a2) - li v0, 1 # signal return to caller. -MterpDone: -/* - * At this point, we expect rPROFILE to be non-zero. If negative, hotness is disabled or we're - * checking for OSR. If greater than zero, we might have unreported hotness to register - * (the difference between the ending rPROFILE and the cached hotness counter). rPROFILE - * should only reach zero immediately after a hotness decrement, and is then reset to either - * a negative special state or the new non-zero countdown value. - */ - blez rPROFILE, .L_pop_and_return # if > 0, we may have some counts to report. - -MterpProfileActive: - move rINST, v0 # stash return value - /* Report cached hotness counts */ - lw a0, OFF_FP_METHOD(rFP) - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rSELF - sh rPROFILE, SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET(a1) - JAL(MterpAddHotnessBatch) # (method, shadow_frame, self) - move v0, rINST # restore return value - -.L_pop_and_return: -/* Restore from the stack and return. Frame size = STACK_SIZE */ - STACK_LOAD_FULL() - jalr zero, ra - - .cfi_endproc - .end ExecuteMterpImpl diff --git a/runtime/interpreter/mterp/mips/funop.S b/runtime/interpreter/mterp/mips/funop.S deleted file mode 100644 index 64f40ac23b..0000000000 --- a/runtime/interpreter/mterp/mips/funop.S +++ /dev/null @@ -1,16 +0,0 @@ -%def funop(instr=""): - /* - * Generic 32-bit floating-point unary operation. Provide an "instr" - * line that specifies an instruction that performs "fv0 = op fa0". - * This could be a MIPS instruction or a function call. - * - * for: int-to-float - */ - /* unop vA, vB */ - GET_OPB(a3) # a3 <- B - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_VREG_F(fa0, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - $instr - GET_INST_OPCODE(t1) # extract opcode from rINST - SET_VREG_F_GOTO(fv0, rOBJ, t1) # vA <- fv0 diff --git a/runtime/interpreter/mterp/mips/funopWider.S b/runtime/interpreter/mterp/mips/funopWider.S deleted file mode 100644 index afc45ee9f5..0000000000 --- a/runtime/interpreter/mterp/mips/funopWider.S +++ /dev/null @@ -1,15 +0,0 @@ -%def funopWider(instr=""): - /* - * Generic 32bit-to-64bit floating-point unary operation. Provide an "instr" - * line that specifies an instruction that performs "fv0 = op fa0". - * - * For: int-to-double, float-to-double - */ - /* unop vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG_F(fa0, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - $instr - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vA/vA+1 <- fv0 diff --git a/runtime/interpreter/mterp/mips/instruction_end.S b/runtime/interpreter/mterp/mips/instruction_end.S deleted file mode 100644 index 3d4429365a..0000000000 --- a/runtime/interpreter/mterp/mips/instruction_end.S +++ /dev/null @@ -1,4 +0,0 @@ -%def instruction_end(): - - .global artMterpAsmInstructionEnd -artMterpAsmInstructionEnd: diff --git a/runtime/interpreter/mterp/mips/instruction_end_alt.S b/runtime/interpreter/mterp/mips/instruction_end_alt.S deleted file mode 100644 index 86a1068f10..0000000000 --- a/runtime/interpreter/mterp/mips/instruction_end_alt.S +++ /dev/null @@ -1,4 +0,0 @@ -%def instruction_end_alt(): - - .global artMterpAsmAltInstructionEnd -artMterpAsmAltInstructionEnd: diff --git a/runtime/interpreter/mterp/mips/instruction_end_sister.S b/runtime/interpreter/mterp/mips/instruction_end_sister.S deleted file mode 100644 index 8cc4513025..0000000000 --- a/runtime/interpreter/mterp/mips/instruction_end_sister.S +++ /dev/null @@ -1,4 +0,0 @@ -%def instruction_end_sister(): - - .global artMterpAsmSisterEnd -artMterpAsmSisterEnd: diff --git a/runtime/interpreter/mterp/mips/instruction_start.S b/runtime/interpreter/mterp/mips/instruction_start.S deleted file mode 100644 index 4b777f2fd5..0000000000 --- a/runtime/interpreter/mterp/mips/instruction_start.S +++ /dev/null @@ -1,5 +0,0 @@ -%def instruction_start(): - - .global artMterpAsmInstructionStart -artMterpAsmInstructionStart = .L_op_nop - .text diff --git a/runtime/interpreter/mterp/mips/instruction_start_alt.S b/runtime/interpreter/mterp/mips/instruction_start_alt.S deleted file mode 100644 index e7731b7505..0000000000 --- a/runtime/interpreter/mterp/mips/instruction_start_alt.S +++ /dev/null @@ -1,5 +0,0 @@ -%def instruction_start_alt(): - - .global artMterpAsmAltInstructionStart -artMterpAsmAltInstructionStart = .L_ALT_op_nop - .text diff --git a/runtime/interpreter/mterp/mips/instruction_start_sister.S b/runtime/interpreter/mterp/mips/instruction_start_sister.S deleted file mode 100644 index e09ea90b8e..0000000000 --- a/runtime/interpreter/mterp/mips/instruction_start_sister.S +++ /dev/null @@ -1,6 +0,0 @@ -%def instruction_start_sister(): - - .global artMterpAsmSisterStart - .text - .balign 4 -artMterpAsmSisterStart: diff --git a/runtime/interpreter/mterp/mips/invoke.S b/runtime/interpreter/mterp/mips/invoke.S index fa744527de..c77d12b506 100644 --- a/runtime/interpreter/mterp/mips/invoke.S +++ b/runtime/interpreter/mterp/mips/invoke.S @@ -17,3 +17,71 @@ bnez v0, MterpFallback GET_INST_OPCODE(t0) GOTO_OPCODE(t0) + +%def invoke_polymorphic(helper="UndefinedInvokeHandler"): + /* + * invoke-polymorphic handler wrapper. + */ + /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ + /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ + .extern $helper + EXPORT_PC() + move a0, rSELF + addu a1, rFP, OFF_FP_SHADOWFRAME + move a2, rPC + move a3, rINST + JAL($helper) + beqz v0, MterpException + FETCH_ADVANCE_INST(4) + JAL(MterpShouldSwitchInterpreters) + bnez v0, MterpFallback + GET_INST_OPCODE(t0) + GOTO_OPCODE(t0) + +%def op_invoke_custom(): +% invoke(helper="MterpInvokeCustom") + +%def op_invoke_custom_range(): +% invoke(helper="MterpInvokeCustomRange") + +%def op_invoke_direct(): +% invoke(helper="MterpInvokeDirect") + +%def op_invoke_direct_range(): +% invoke(helper="MterpInvokeDirectRange") + +%def op_invoke_interface(): +% invoke(helper="MterpInvokeInterface") + +%def op_invoke_interface_range(): +% invoke(helper="MterpInvokeInterfaceRange") + +%def op_invoke_polymorphic(): +% invoke_polymorphic(helper="MterpInvokePolymorphic") + +%def op_invoke_polymorphic_range(): +% invoke_polymorphic(helper="MterpInvokePolymorphicRange") + +%def op_invoke_static(): +% invoke(helper="MterpInvokeStatic") + +%def op_invoke_static_range(): +% invoke(helper="MterpInvokeStaticRange") + +%def op_invoke_super(): +% invoke(helper="MterpInvokeSuper") + +%def op_invoke_super_range(): +% invoke(helper="MterpInvokeSuperRange") + +%def op_invoke_virtual(): +% invoke(helper="MterpInvokeVirtual") + +%def op_invoke_virtual_quick(): +% invoke(helper="MterpInvokeVirtualQuick") + +%def op_invoke_virtual_range(): +% invoke(helper="MterpInvokeVirtualRange") + +%def op_invoke_virtual_range_quick(): +% invoke(helper="MterpInvokeVirtualQuickRange") diff --git a/runtime/interpreter/mterp/mips/invoke_polymorphic.S b/runtime/interpreter/mterp/mips/invoke_polymorphic.S deleted file mode 100644 index f2532e7b2b..0000000000 --- a/runtime/interpreter/mterp/mips/invoke_polymorphic.S +++ /dev/null @@ -1,19 +0,0 @@ -%def invoke_polymorphic(helper="UndefinedInvokeHandler"): - /* - * invoke-polymorphic handler wrapper. - */ - /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ - .extern $helper - EXPORT_PC() - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - JAL($helper) - beqz v0, MterpException - FETCH_ADVANCE_INST(4) - JAL(MterpShouldSwitchInterpreters) - bnez v0, MterpFallback - GET_INST_OPCODE(t0) - GOTO_OPCODE(t0) diff --git a/runtime/interpreter/mterp/mips/header.S b/runtime/interpreter/mterp/mips/main.S similarity index 59% rename from runtime/interpreter/mterp/mips/header.S rename to runtime/interpreter/mterp/mips/main.S index 57339d0f7f..6e91af8a70 100644 --- a/runtime/interpreter/mterp/mips/header.S +++ b/runtime/interpreter/mterp/mips/main.S @@ -725,3 +725,423 @@ #define LONG_MIN_HIGH 0x80000000 #define LONG_MIN_AS_FLOAT 0xDF000000 #define LONG_MIN_AS_DOUBLE_HIGH 0xC3E00000 + +%def entry(): +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* + * Interpreter entry point. + */ + + .text + .align 2 + .global ExecuteMterpImpl + .ent ExecuteMterpImpl + .frame sp, STACK_SIZE, ra +/* + * On entry: + * a0 Thread* self + * a1 dex_instructions + * a2 ShadowFrame + * a3 JValue* result_register + * + */ + +ExecuteMterpImpl: + .cfi_startproc + .set noreorder + .cpload t9 + .set reorder +/* Save to the stack. Frame size = STACK_SIZE */ + STACK_STORE_FULL() +/* This directive will make sure all subsequent jal restore gp at a known offset */ + .cprestore STACK_OFFSET_GP + + /* Remember the return register */ + sw a3, SHADOWFRAME_RESULT_REGISTER_OFFSET(a2) + + /* Remember the dex instruction pointer */ + sw a1, SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET(a2) + + /* set up "named" registers */ + move rSELF, a0 + lw a0, SHADOWFRAME_NUMBER_OF_VREGS_OFFSET(a2) + addu rFP, a2, SHADOWFRAME_VREGS_OFFSET # point to vregs. + EAS2(rREFS, rFP, a0) # point to reference array in shadow frame + lw a0, SHADOWFRAME_DEX_PC_OFFSET(a2) # Get starting dex_pc + EAS1(rPC, a1, a0) # Create direct pointer to 1st dex opcode + CFI_DEFINE_DEX_PC_WITH_OFFSET(CFI_TMP, CFI_DEX, 0) + + EXPORT_PC() + + /* Starting ibase */ + lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) + + /* Set up for backwards branches & osr profiling */ + lw a0, OFF_FP_METHOD(rFP) + addu a1, rFP, OFF_FP_SHADOWFRAME + move a2, rSELF + JAL(MterpSetUpHotnessCountdown) # (method, shadow_frame, self) + move rPROFILE, v0 # Starting hotness countdown to rPROFILE + + /* start executing the instruction at rPC */ + FETCH_INST() # load rINST from rPC + GET_INST_OPCODE(t0) # extract opcode from rINST + GOTO_OPCODE(t0) # jump to next instruction + /* NOTE: no fallthrough */ + +%def alt_stub(): +/* + * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle + * any interesting requests and then jump to the real instruction + * handler. Note that the call to MterpCheckBefore is done as a tail call. + */ + .extern MterpCheckBefore + la ra, artMterpAsmInstructionStart + (${opnum} * 128) # Addr of primary handler + lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE + move a0, rSELF # arg0 + addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 + move a2, rPC + la t9, MterpCheckBefore + jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) + +%def fallback(): +/* Transfer stub to alternate interpreter */ + b MterpFallback + +%def footer(): +/* + * =========================================================================== + * Common subroutines and data + * =========================================================================== + */ + + .text + .align 2 + +/* + * We've detected a condition that will result in an exception, but the exception + * has not yet been thrown. Just bail out to the reference interpreter to deal with it. + * TUNING: for consistency, we may want to just go ahead and handle these here. + */ +common_errDivideByZero: + EXPORT_PC() +#if MTERP_LOGGING + move a0, rSELF + addu a1, rFP, OFF_FP_SHADOWFRAME + JAL(MterpLogDivideByZeroException) +#endif + b MterpCommonFallback + +common_errArrayIndex: + EXPORT_PC() +#if MTERP_LOGGING + move a0, rSELF + addu a1, rFP, OFF_FP_SHADOWFRAME + JAL(MterpLogArrayIndexException) +#endif + b MterpCommonFallback + +common_errNegativeArraySize: + EXPORT_PC() +#if MTERP_LOGGING + move a0, rSELF + addu a1, rFP, OFF_FP_SHADOWFRAME + JAL(MterpLogNegativeArraySizeException) +#endif + b MterpCommonFallback + +common_errNoSuchMethod: + EXPORT_PC() +#if MTERP_LOGGING + move a0, rSELF + addu a1, rFP, OFF_FP_SHADOWFRAME + JAL(MterpLogNoSuchMethodException) +#endif + b MterpCommonFallback + +common_errNullObject: + EXPORT_PC() +#if MTERP_LOGGING + move a0, rSELF + addu a1, rFP, OFF_FP_SHADOWFRAME + JAL(MterpLogNullObjectException) +#endif + b MterpCommonFallback + +common_exceptionThrown: + EXPORT_PC() +#if MTERP_LOGGING + move a0, rSELF + addu a1, rFP, OFF_FP_SHADOWFRAME + JAL(MterpLogExceptionThrownException) +#endif + b MterpCommonFallback + +MterpSuspendFallback: + EXPORT_PC() +#if MTERP_LOGGING + move a0, rSELF + addu a1, rFP, OFF_FP_SHADOWFRAME + lw a2, THREAD_FLAGS_OFFSET(rSELF) + JAL(MterpLogSuspendFallback) +#endif + b MterpCommonFallback + +/* + * If we're here, something is out of the ordinary. If there is a pending + * exception, handle it. Otherwise, roll back and retry with the reference + * interpreter. + */ +MterpPossibleException: + lw a0, THREAD_EXCEPTION_OFFSET(rSELF) + beqz a0, MterpFallback # If exception, fall back to reference interpreter. + /* intentional fallthrough - handle pending exception. */ +/* + * On return from a runtime helper routine, we've found a pending exception. + * Can we handle it here - or need to bail out to caller? + * + */ +MterpException: + move a0, rSELF + addu a1, rFP, OFF_FP_SHADOWFRAME + JAL(MterpHandleException) # (self, shadow_frame) + beqz v0, MterpExceptionReturn # no local catch, back to caller. + lw a0, OFF_FP_DEX_INSTRUCTIONS(rFP) + lw a1, OFF_FP_DEX_PC(rFP) + lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) + EAS1(rPC, a0, a1) # generate new dex_pc_ptr + /* Do we need to switch interpreters? */ + JAL(MterpShouldSwitchInterpreters) + bnez v0, MterpFallback + /* resume execution at catch block */ + EXPORT_PC() + FETCH_INST() + GET_INST_OPCODE(t0) + GOTO_OPCODE(t0) + /* NOTE: no fallthrough */ + +/* + * Common handling for branches with support for Jit profiling. + * On entry: + * rINST <= signed offset + * rPROFILE <= signed hotness countdown (expanded to 32 bits) + * + * We have quite a few different cases for branch profiling, OSR detection and + * suspend check support here. + * + * Taken backward branches: + * If profiling active, do hotness countdown and report if we hit zero. + * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. + * Is there a pending suspend request? If so, suspend. + * + * Taken forward branches and not-taken backward branches: + * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. + * + * Our most common case is expected to be a taken backward branch with active jit profiling, + * but no full OSR check and no pending suspend request. + * Next most common case is not-taken branch with no full OSR check. + */ +MterpCommonTakenBranchNoFlags: + bgtz rINST, .L_forward_branch # don't add forward branches to hotness +/* + * We need to subtract 1 from positive values and we should not see 0 here, + * so we may use the result of the comparison with -1. + */ +#if JIT_CHECK_OSR != -1 +# error "JIT_CHECK_OSR must be -1." +#endif + li t0, JIT_CHECK_OSR + beq rPROFILE, t0, .L_osr_check + blt rPROFILE, t0, .L_resume_backward_branch + subu rPROFILE, 1 + beqz rPROFILE, .L_add_batch # counted down to zero - report +.L_resume_backward_branch: + lw ra, THREAD_FLAGS_OFFSET(rSELF) + REFRESH_IBASE() + addu a2, rINST, rINST # a2<- byte offset + FETCH_ADVANCE_INST_RB(a2) # update rPC, load rINST + and ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST + bnez ra, .L_suspend_request_pending + GET_INST_OPCODE(t0) # extract opcode from rINST + GOTO_OPCODE(t0) # jump to next instruction + +.L_suspend_request_pending: + EXPORT_PC() + move a0, rSELF + JAL(MterpSuspendCheck) # (self) + bnez v0, MterpFallback + REFRESH_IBASE() # might have changed during suspend + GET_INST_OPCODE(t0) # extract opcode from rINST + GOTO_OPCODE(t0) # jump to next instruction + +.L_no_count_backwards: + li t0, JIT_CHECK_OSR # check for possible OSR re-entry + bne rPROFILE, t0, .L_resume_backward_branch +.L_osr_check: + move a0, rSELF + addu a1, rFP, OFF_FP_SHADOWFRAME + move a2, rINST + EXPORT_PC() + JAL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) + bnez v0, MterpOnStackReplacement + b .L_resume_backward_branch + +.L_forward_branch: + li t0, JIT_CHECK_OSR # check for possible OSR re-entry + beq rPROFILE, t0, .L_check_osr_forward +.L_resume_forward_branch: + add a2, rINST, rINST # a2<- byte offset + FETCH_ADVANCE_INST_RB(a2) # update rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + GOTO_OPCODE(t0) # jump to next instruction + +.L_check_osr_forward: + move a0, rSELF + addu a1, rFP, OFF_FP_SHADOWFRAME + move a2, rINST + EXPORT_PC() + JAL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) + bnez v0, MterpOnStackReplacement + b .L_resume_forward_branch + +.L_add_batch: + addu a1, rFP, OFF_FP_SHADOWFRAME + sh rPROFILE, SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET(a1) + lw a0, OFF_FP_METHOD(rFP) + move a2, rSELF + JAL(MterpAddHotnessBatch) # (method, shadow_frame, self) + move rPROFILE, v0 # restore new hotness countdown to rPROFILE + b .L_no_count_backwards + +/* + * Entered from the conditional branch handlers when OSR check request active on + * not-taken path. All Dalvik not-taken conditional branch offsets are 2. + */ +.L_check_not_taken_osr: + move a0, rSELF + addu a1, rFP, OFF_FP_SHADOWFRAME + li a2, 2 + EXPORT_PC() + JAL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) + bnez v0, MterpOnStackReplacement + FETCH_ADVANCE_INST(2) + GET_INST_OPCODE(t0) # extract opcode from rINST + GOTO_OPCODE(t0) # jump to next instruction + +/* + * On-stack replacement has happened, and now we've returned from the compiled method. + */ +MterpOnStackReplacement: +#if MTERP_LOGGING + move a0, rSELF + addu a1, rFP, OFF_FP_SHADOWFRAME + move a2, rINST + JAL(MterpLogOSR) +#endif + li v0, 1 # Signal normal return + b MterpDone + +/* + * Bail out to reference interpreter. + */ +MterpFallback: + EXPORT_PC() +#if MTERP_LOGGING + move a0, rSELF + addu a1, rFP, OFF_FP_SHADOWFRAME + JAL(MterpLogFallback) +#endif +MterpCommonFallback: + move v0, zero # signal retry with reference interpreter. + b MterpDone +/* + * We pushed some registers on the stack in ExecuteMterpImpl, then saved + * SP and LR. Here we restore SP, restore the registers, and then restore + * LR to PC. + * + * On entry: + * uint32_t* rFP (should still be live, pointer to base of vregs) + */ +MterpExceptionReturn: + li v0, 1 # signal return to caller. + b MterpDone +MterpReturn: + lw a2, OFF_FP_RESULT_REGISTER(rFP) + sw v0, 0(a2) + sw v1, 4(a2) + li v0, 1 # signal return to caller. +MterpDone: +/* + * At this point, we expect rPROFILE to be non-zero. If negative, hotness is disabled or we're + * checking for OSR. If greater than zero, we might have unreported hotness to register + * (the difference between the ending rPROFILE and the cached hotness counter). rPROFILE + * should only reach zero immediately after a hotness decrement, and is then reset to either + * a negative special state or the new non-zero countdown value. + */ + blez rPROFILE, .L_pop_and_return # if > 0, we may have some counts to report. + +MterpProfileActive: + move rINST, v0 # stash return value + /* Report cached hotness counts */ + lw a0, OFF_FP_METHOD(rFP) + addu a1, rFP, OFF_FP_SHADOWFRAME + move a2, rSELF + sh rPROFILE, SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET(a1) + JAL(MterpAddHotnessBatch) # (method, shadow_frame, self) + move v0, rINST # restore return value + +.L_pop_and_return: +/* Restore from the stack and return. Frame size = STACK_SIZE */ + STACK_LOAD_FULL() + jalr zero, ra + + .cfi_endproc + .end ExecuteMterpImpl + +%def instruction_end(): + + .global artMterpAsmInstructionEnd +artMterpAsmInstructionEnd: + +%def instruction_end_alt(): + + .global artMterpAsmAltInstructionEnd +artMterpAsmAltInstructionEnd: + +%def instruction_end_sister(): + + .global artMterpAsmSisterEnd +artMterpAsmSisterEnd: + +%def instruction_start(): + + .global artMterpAsmInstructionStart +artMterpAsmInstructionStart = .L_op_nop + .text + +%def instruction_start_alt(): + + .global artMterpAsmAltInstructionStart +artMterpAsmAltInstructionStart = .L_ALT_op_nop + .text + +%def instruction_start_sister(): + + .global artMterpAsmSisterStart + .text + .balign 4 +artMterpAsmSisterStart: diff --git a/runtime/interpreter/mterp/mips/object.S b/runtime/interpreter/mterp/mips/object.S new file mode 100644 index 0000000000..a98778919f --- /dev/null +++ b/runtime/interpreter/mterp/mips/object.S @@ -0,0 +1,257 @@ +%def field(helper=""): +TODO + +%def op_check_cast(): + /* + * Check to see if a cast from one class to another is allowed. + */ + /* check-cast vAA, class@BBBB */ + EXPORT_PC() + FETCH(a0, 1) # a0 <- BBBB + GET_OPA(a1) # a1 <- AA + EAS2(a1, rFP, a1) # a1 <- &object + lw a2, OFF_FP_METHOD(rFP) # a2 <- method + move a3, rSELF # a3 <- self + JAL(MterpCheckCast) # v0 <- CheckCast(index, &obj, method, self) + PREFETCH_INST(2) + bnez v0, MterpPossibleException + ADVANCE(2) + GET_INST_OPCODE(t0) # extract opcode from rINST + GOTO_OPCODE(t0) # jump to next instruction + +%def op_iget(is_object="0", helper="MterpIGetU32"): +% field(helper=helper) + +%def op_iget_boolean(): +% op_iget(helper="MterpIGetU8") + +%def op_iget_boolean_quick(): +% op_iget_quick(load="lbu") + +%def op_iget_byte(): +% op_iget(helper="MterpIGetI8") + +%def op_iget_byte_quick(): +% op_iget_quick(load="lb") + +%def op_iget_char(): +% op_iget(helper="MterpIGetU16") + +%def op_iget_char_quick(): +% op_iget_quick(load="lhu") + +%def op_iget_object(): +% op_iget(is_object="1", helper="MterpIGetObj") + +%def op_iget_object_quick(): + /* For: iget-object-quick */ + /* op vA, vB, offset@CCCC */ + GET_OPB(a2) # a2 <- B + FETCH(a1, 1) # a1 <- field byte offset + EXPORT_PC() + GET_VREG(a0, a2) # a0 <- object we're operating on + JAL(artIGetObjectFromMterp) # v0 <- GetObj(obj, offset) + lw a3, THREAD_EXCEPTION_OFFSET(rSELF) + GET_OPA4(a2) # a2<- A+ + PREFETCH_INST(2) # load rINST + bnez a3, MterpPossibleException # bail out + ADVANCE(2) # advance rPC + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG_OBJECT_GOTO(v0, a2, t0) # fp[A] <- v0 + +%def op_iget_quick(load="lw"): + /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ + /* op vA, vB, offset@CCCC */ + GET_OPB(a2) # a2 <- B + GET_VREG(a3, a2) # a3 <- object we're operating on + FETCH(a1, 1) # a1 <- field byte offset + GET_OPA4(a2) # a2 <- A(+) + # check object for null + beqz a3, common_errNullObject # object was null + addu t0, a3, a1 + $load a0, 0(t0) # a0 <- obj.field (8/16/32 bits) + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG_GOTO(a0, a2, t0) # fp[A] <- a0 + +%def op_iget_short(): +% op_iget(helper="MterpIGetI16") + +%def op_iget_short_quick(): +% op_iget_quick(load="lh") + +%def op_iget_wide(): +% op_iget(helper="MterpIGetU64") + +%def op_iget_wide_quick(): + /* iget-wide-quick vA, vB, offset@CCCC */ + GET_OPB(a2) # a2 <- B + GET_VREG(a3, a2) # a3 <- object we're operating on + FETCH(a1, 1) # a1 <- field byte offset + GET_OPA4(a2) # a2 <- A(+) + # check object for null + beqz a3, common_errNullObject # object was null + addu t0, a3, a1 # t0 <- a3 + a1 + LOAD64(a0, a1, t0) # a0 <- obj.field (64 bits, aligned) + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG64_GOTO(a0, a1, a2, t0) # fp[A] <- a0/a1 + +%def op_instance_of(): + /* + * Check to see if an object reference is an instance of a class. + * + * Most common situation is a non-null object, being compared against + * an already-resolved class. + */ + /* instance-of vA, vB, class@CCCC */ + EXPORT_PC() + FETCH(a0, 1) # a0 <- CCCC + GET_OPB(a1) # a1 <- B + EAS2(a1, rFP, a1) # a1 <- &object + lw a2, OFF_FP_METHOD(rFP) # a2 <- method + move a3, rSELF # a3 <- self + GET_OPA4(rOBJ) # rOBJ <- A+ + JAL(MterpInstanceOf) # v0 <- Mterp(index, &obj, method, self) + lw a1, THREAD_EXCEPTION_OFFSET(rSELF) + PREFETCH_INST(2) # load rINST + bnez a1, MterpException + ADVANCE(2) # advance rPC + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG_GOTO(v0, rOBJ, t0) # vA <- v0 + +%def op_iput(is_object="0", helper="MterpIPutU32"): +% field(helper=helper) + +%def op_iput_boolean(): +% op_iput(helper="MterpIPutU8") + +%def op_iput_boolean_quick(): +% op_iput_quick(store="sb") + +%def op_iput_byte(): +% op_iput(helper="MterpIPutI8") + +%def op_iput_byte_quick(): +% op_iput_quick(store="sb") + +%def op_iput_char(): +% op_iput(helper="MterpIPutU16") + +%def op_iput_char_quick(): +% op_iput_quick(store="sh") + +%def op_iput_object(): +% op_iput(is_object="1", helper="MterpIPutObj") + +%def op_iput_object_quick(): + /* For: iput-object-quick */ + /* op vA, vB, offset@CCCC */ + EXPORT_PC() + addu a0, rFP, OFF_FP_SHADOWFRAME + move a1, rPC + move a2, rINST + JAL(MterpIputObjectQuick) + beqz v0, MterpException + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + GOTO_OPCODE(t0) # jump to next instruction + +%def op_iput_quick(store="sw"): + /* For: iput-quick, iput-object-quick */ + /* op vA, vB, offset@CCCC */ + GET_OPB(a2) # a2 <- B + GET_VREG(a3, a2) # a3 <- fp[B], the object pointer + FETCH(a1, 1) # a1 <- field byte offset + GET_OPA4(a2) # a2 <- A(+) + beqz a3, common_errNullObject # object was null + GET_VREG(a0, a2) # a0 <- fp[A] + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + addu t0, a3, a1 + GET_INST_OPCODE(t1) # extract opcode from rINST + GET_OPCODE_TARGET(t1) + $store a0, 0(t0) # obj.field (8/16/32 bits) <- a0 + JR(t1) # jump to next instruction + +%def op_iput_short(): +% op_iput(helper="MterpIPutI16") + +%def op_iput_short_quick(): +% op_iput_quick(store="sh") + +%def op_iput_wide(): +% op_iput(helper="MterpIPutU64") + +%def op_iput_wide_quick(): + /* iput-wide-quick vA, vB, offset@CCCC */ + GET_OPA4(a0) # a0 <- A(+) + GET_OPB(a1) # a1 <- B + GET_VREG(a2, a1) # a2 <- fp[B], the object pointer + # check object for null + beqz a2, common_errNullObject # object was null + EAS2(a3, rFP, a0) # a3 <- &fp[A] + LOAD64(a0, a1, a3) # a0/a1 <- fp[A] + FETCH(a3, 1) # a3 <- field byte offset + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + addu a2, a2, a3 # obj.field (64 bits, aligned) <- a0/a1 + GET_INST_OPCODE(t0) # extract opcode from rINST + GET_OPCODE_TARGET(t0) + STORE64(a0, a1, a2) # obj.field (64 bits, aligned) <- a0/a1 + JR(t0) # jump to next instruction + +%def op_new_instance(): + /* + * Create a new instance of a class. + */ + /* new-instance vAA, class@BBBB */ + EXPORT_PC() + addu a0, rFP, OFF_FP_SHADOWFRAME + move a1, rSELF + move a2, rINST + JAL(MterpNewInstance) + beqz v0, MterpPossibleException + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + GOTO_OPCODE(t0) # jump to next instruction + +%def op_sget(is_object="0", helper="MterpSGetU32"): +% field(helper=helper) + +%def op_sget_boolean(): +% op_sget(helper="MterpSGetU8") + +%def op_sget_byte(): +% op_sget(helper="MterpSGetI8") + +%def op_sget_char(): +% op_sget(helper="MterpSGetU16") + +%def op_sget_object(): +% op_sget(is_object="1", helper="MterpSGetObj") + +%def op_sget_short(): +% op_sget(helper="MterpSGetI16") + +%def op_sget_wide(): +% op_sget(helper="MterpSGetU64") + +%def op_sput(is_object="0", helper="MterpSPutU32"): +% field(helper=helper) + +%def op_sput_boolean(): +% op_sput(helper="MterpSPutU8") + +%def op_sput_byte(): +% op_sput(helper="MterpSPutI8") + +%def op_sput_char(): +% op_sput(helper="MterpSPutU16") + +%def op_sput_object(): +% op_sput(is_object="1", helper="MterpSPutObj") + +%def op_sput_short(): +% op_sput(helper="MterpSPutI16") + +%def op_sput_wide(): +% op_sput(helper="MterpSPutU64") diff --git a/runtime/interpreter/mterp/mips/op_add_double.S b/runtime/interpreter/mterp/mips/op_add_double.S deleted file mode 100644 index 8308cdc4dd..0000000000 --- a/runtime/interpreter/mterp/mips/op_add_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_double(): -% fbinopWide(instr="add.d fv0, fa0, fa1") diff --git a/runtime/interpreter/mterp/mips/op_add_double_2addr.S b/runtime/interpreter/mterp/mips/op_add_double_2addr.S deleted file mode 100644 index 41b099676c..0000000000 --- a/runtime/interpreter/mterp/mips/op_add_double_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_double_2addr(): -% fbinopWide2addr(instr="add.d fv0, fa0, fa1") diff --git a/runtime/interpreter/mterp/mips/op_add_float.S b/runtime/interpreter/mterp/mips/op_add_float.S deleted file mode 100644 index 807ea97481..0000000000 --- a/runtime/interpreter/mterp/mips/op_add_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_float(): -% fbinop(instr="add.s fv0, fa0, fa1") diff --git a/runtime/interpreter/mterp/mips/op_add_float_2addr.S b/runtime/interpreter/mterp/mips/op_add_float_2addr.S deleted file mode 100644 index c5735ae2e0..0000000000 --- a/runtime/interpreter/mterp/mips/op_add_float_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_float_2addr(): -% fbinop2addr(instr="add.s fv0, fa0, fa1") diff --git a/runtime/interpreter/mterp/mips/op_add_int.S b/runtime/interpreter/mterp/mips/op_add_int.S deleted file mode 100644 index ed0fc012b8..0000000000 --- a/runtime/interpreter/mterp/mips/op_add_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_int(): -% binop(instr="addu a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_add_int_2addr.S b/runtime/interpreter/mterp/mips/op_add_int_2addr.S deleted file mode 100644 index ed0b1314ef..0000000000 --- a/runtime/interpreter/mterp/mips/op_add_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_int_2addr(): -% binop2addr(instr="addu a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_add_int_lit16.S b/runtime/interpreter/mterp/mips/op_add_int_lit16.S deleted file mode 100644 index 126807a303..0000000000 --- a/runtime/interpreter/mterp/mips/op_add_int_lit16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_int_lit16(): -% binopLit16(instr="addu a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_add_int_lit8.S b/runtime/interpreter/mterp/mips/op_add_int_lit8.S deleted file mode 100644 index 30184c40f5..0000000000 --- a/runtime/interpreter/mterp/mips/op_add_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_int_lit8(): -% binopLit8(instr="addu a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_add_long.S b/runtime/interpreter/mterp/mips/op_add_long.S deleted file mode 100644 index 32205068ba..0000000000 --- a/runtime/interpreter/mterp/mips/op_add_long.S +++ /dev/null @@ -1,10 +0,0 @@ -%def op_add_long(): -/* - * The compiler generates the following sequence for - * [v1 v0] = [a1 a0] + [a3 a2]; - * addu v0,a2,a0 - * addu a1,a3,a1 - * sltu v1,v0,a2 - * addu v1,v1,a1 - */ -% binopWide(result0="v0", result1="v1", preinstr="addu v0, a2, a0", instr="addu a1, a3, a1; sltu v1, v0, a2; addu v1, v1, a1") diff --git a/runtime/interpreter/mterp/mips/op_add_long_2addr.S b/runtime/interpreter/mterp/mips/op_add_long_2addr.S deleted file mode 100644 index 3bbc1f393d..0000000000 --- a/runtime/interpreter/mterp/mips/op_add_long_2addr.S +++ /dev/null @@ -1,5 +0,0 @@ -%def op_add_long_2addr(): -/* - * See op_add_long.S for details - */ -% binopWide2addr(result0="v0", result1="v1", preinstr="addu v0, a2, a0", instr="addu a1, a3, a1; sltu v1, v0, a2; addu v1, v1, a1") diff --git a/runtime/interpreter/mterp/mips/op_aget.S b/runtime/interpreter/mterp/mips/op_aget.S deleted file mode 100644 index 026095f7ac..0000000000 --- a/runtime/interpreter/mterp/mips/op_aget.S +++ /dev/null @@ -1,28 +0,0 @@ -%def op_aget(load="lw", shift="2", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"): - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B(a2, 1, 0) # a2 <- BB - GET_OPA(rOBJ) # rOBJ <- AA - FETCH_B(a3, 1, 1) # a3 <- CC - GET_VREG(a0, a2) # a0 <- vBB (array object) - GET_VREG(a1, a3) # a1 <- vCC (requested index) - # null array object? - beqz a0, common_errNullObject # yes, bail - LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length - EASN(a0, a0, a1, $shift) # a0 <- arrayObj + index*width - # a1 >= a3; compare unsigned index - bgeu a1, a3, common_errArrayIndex # index >= length, bail - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - $load a2, $data_offset(a0) # a2 <- vBB[vCC] - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a2, rOBJ, t0) # vAA <- a2 diff --git a/runtime/interpreter/mterp/mips/op_aget_boolean.S b/runtime/interpreter/mterp/mips/op_aget_boolean.S deleted file mode 100644 index 7b28bc8e06..0000000000 --- a/runtime/interpreter/mterp/mips/op_aget_boolean.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aget_boolean(): -% op_aget(load="lbu", shift="0", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/mips/op_aget_byte.S b/runtime/interpreter/mterp/mips/op_aget_byte.S deleted file mode 100644 index a4a0b7e9b7..0000000000 --- a/runtime/interpreter/mterp/mips/op_aget_byte.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aget_byte(): -% op_aget(load="lb", shift="0", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/mips/op_aget_char.S b/runtime/interpreter/mterp/mips/op_aget_char.S deleted file mode 100644 index 465de097cd..0000000000 --- a/runtime/interpreter/mterp/mips/op_aget_char.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aget_char(): -% op_aget(load="lhu", shift="1", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/mips/op_aget_object.S b/runtime/interpreter/mterp/mips/op_aget_object.S deleted file mode 100644 index 17a1e0ca8c..0000000000 --- a/runtime/interpreter/mterp/mips/op_aget_object.S +++ /dev/null @@ -1,20 +0,0 @@ -%def op_aget_object(): - /* - * Array object get. vAA <- vBB[vCC]. - * - * for: aget-object - */ - /* op vAA, vBB, vCC */ - FETCH_B(a2, 1, 0) # a2 <- BB - GET_OPA(rOBJ) # rOBJ <- AA - FETCH_B(a3, 1, 1) # a3 <- CC - EXPORT_PC() - GET_VREG(a0, a2) # a0 <- vBB (array object) - GET_VREG(a1, a3) # a1 <- vCC (requested index) - JAL(artAGetObjectFromMterp) # v0 <- GetObj(array, index) - lw a1, THREAD_EXCEPTION_OFFSET(rSELF) - PREFETCH_INST(2) # load rINST - bnez a1, MterpException - ADVANCE(2) # advance rPC - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_OBJECT_GOTO(v0, rOBJ, t0) # vAA <- v0 diff --git a/runtime/interpreter/mterp/mips/op_aget_short.S b/runtime/interpreter/mterp/mips/op_aget_short.S deleted file mode 100644 index 4faa9ad358..0000000000 --- a/runtime/interpreter/mterp/mips/op_aget_short.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aget_short(): -% op_aget(load="lh", shift="1", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/mips/op_aget_wide.S b/runtime/interpreter/mterp/mips/op_aget_wide.S deleted file mode 100644 index 4045c11dbe..0000000000 --- a/runtime/interpreter/mterp/mips/op_aget_wide.S +++ /dev/null @@ -1,23 +0,0 @@ -%def op_aget_wide(): - /* - * Array get, 64 bits. vAA <- vBB[vCC]. - * - * Arrays of long/double are 64-bit aligned. - */ - /* aget-wide vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 # a3 <- CC - GET_VREG(a0, a2) # a0 <- vBB (array object) - GET_VREG(a1, a3) # a1 <- vCC (requested index) - # null array object? - beqz a0, common_errNullObject # yes, bail - LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length - EAS3(a0, a0, a1) # a0 <- arrayObj + index*width - bgeu a1, a3, common_errArrayIndex # index >= length, bail - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - LOAD64_off(a2, a3, a0, MIRROR_WIDE_ARRAY_DATA_OFFSET) - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(a2, a3, rOBJ, t0) # vAA/vAA+1 <- a2/a3 diff --git a/runtime/interpreter/mterp/mips/op_and_int.S b/runtime/interpreter/mterp/mips/op_and_int.S deleted file mode 100644 index 740411ddf7..0000000000 --- a/runtime/interpreter/mterp/mips/op_and_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_and_int(): -% binop(instr="and a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_and_int_2addr.S b/runtime/interpreter/mterp/mips/op_and_int_2addr.S deleted file mode 100644 index 8224e5f18a..0000000000 --- a/runtime/interpreter/mterp/mips/op_and_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_and_int_2addr(): -% binop2addr(instr="and a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_and_int_lit16.S b/runtime/interpreter/mterp/mips/op_and_int_lit16.S deleted file mode 100644 index 5031f500ce..0000000000 --- a/runtime/interpreter/mterp/mips/op_and_int_lit16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_and_int_lit16(): -% binopLit16(instr="and a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_and_int_lit8.S b/runtime/interpreter/mterp/mips/op_and_int_lit8.S deleted file mode 100644 index 7a7b8b5d5a..0000000000 --- a/runtime/interpreter/mterp/mips/op_and_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_and_int_lit8(): -% binopLit8(instr="and a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_and_long.S b/runtime/interpreter/mterp/mips/op_and_long.S deleted file mode 100644 index 210e6a1acc..0000000000 --- a/runtime/interpreter/mterp/mips/op_and_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_and_long(): -% binopWide(preinstr="and a0, a0, a2", instr="and a1, a1, a3") diff --git a/runtime/interpreter/mterp/mips/op_and_long_2addr.S b/runtime/interpreter/mterp/mips/op_and_long_2addr.S deleted file mode 100644 index c76a5af695..0000000000 --- a/runtime/interpreter/mterp/mips/op_and_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_and_long_2addr(): -% binopWide2addr(preinstr="and a0, a0, a2", instr="and a1, a1, a3") diff --git a/runtime/interpreter/mterp/mips/op_aput.S b/runtime/interpreter/mterp/mips/op_aput.S deleted file mode 100644 index 6561f8f79f..0000000000 --- a/runtime/interpreter/mterp/mips/op_aput.S +++ /dev/null @@ -1,27 +0,0 @@ -%def op_aput(store="sw", shift="2", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"): - - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B(a2, 1, 0) # a2 <- BB - GET_OPA(rOBJ) # rOBJ <- AA - FETCH_B(a3, 1, 1) # a3 <- CC - GET_VREG(a0, a2) # a0 <- vBB (array object) - GET_VREG(a1, a3) # a1 <- vCC (requested index) - # null array object? - beqz a0, common_errNullObject # yes, bail - LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length - EASN(a0, a0, a1, $shift) # a0 <- arrayObj + index*width - bgeu a1, a3, common_errArrayIndex # index >= length, bail - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_VREG(a2, rOBJ) # a2 <- vAA - GET_INST_OPCODE(t0) # extract opcode from rINST - GET_OPCODE_TARGET(t0) - $store a2, $data_offset(a0) # vBB[vCC] <- a2 - JR(t0) # jump to next instruction diff --git a/runtime/interpreter/mterp/mips/op_aput_boolean.S b/runtime/interpreter/mterp/mips/op_aput_boolean.S deleted file mode 100644 index 098bbcd1c4..0000000000 --- a/runtime/interpreter/mterp/mips/op_aput_boolean.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aput_boolean(): -% op_aput(store="sb", shift="0", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/mips/op_aput_byte.S b/runtime/interpreter/mterp/mips/op_aput_byte.S deleted file mode 100644 index f4b42ee6e8..0000000000 --- a/runtime/interpreter/mterp/mips/op_aput_byte.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aput_byte(): -% op_aput(store="sb", shift="0", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/mips/op_aput_char.S b/runtime/interpreter/mterp/mips/op_aput_char.S deleted file mode 100644 index 18eedae68d..0000000000 --- a/runtime/interpreter/mterp/mips/op_aput_char.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aput_char(): -% op_aput(store="sh", shift="1", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/mips/op_aput_object.S b/runtime/interpreter/mterp/mips/op_aput_object.S deleted file mode 100644 index 89c72bac4e..0000000000 --- a/runtime/interpreter/mterp/mips/op_aput_object.S +++ /dev/null @@ -1,15 +0,0 @@ -%def op_aput_object(): - /* - * Store an object into an array. vBB[vCC] <- vAA. - * - */ - /* op vAA, vBB, vCC */ - EXPORT_PC() - addu a0, rFP, OFF_FP_SHADOWFRAME - move a1, rPC - move a2, rINST - JAL(MterpAputObject) - beqz v0, MterpPossibleException - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction diff --git a/runtime/interpreter/mterp/mips/op_aput_short.S b/runtime/interpreter/mterp/mips/op_aput_short.S deleted file mode 100644 index 61a3c0d6ea..0000000000 --- a/runtime/interpreter/mterp/mips/op_aput_short.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aput_short(): -% op_aput(store="sh", shift="1", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/mips/op_aput_wide.S b/runtime/interpreter/mterp/mips/op_aput_wide.S deleted file mode 100644 index 2fd0cbb932..0000000000 --- a/runtime/interpreter/mterp/mips/op_aput_wide.S +++ /dev/null @@ -1,25 +0,0 @@ -%def op_aput_wide(): - /* - * Array put, 64 bits. vBB[vCC] <- vAA. - */ - /* aput-wide vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(t0) # t0 <- AA - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 # a3 <- CC - GET_VREG(a0, a2) # a0 <- vBB (array object) - GET_VREG(a1, a3) # a1 <- vCC (requested index) - # null array object? - beqz a0, common_errNullObject # yes, bail - LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length - EAS3(a0, a0, a1) # a0 <- arrayObj + index*width - EAS2(rOBJ, rFP, t0) # rOBJ <- &fp[AA] - # compare unsigned index, length - bgeu a1, a3, common_errArrayIndex # index >= length, bail - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - LOAD64(a2, a3, rOBJ) # a2/a3 <- vAA/vAA+1 - GET_INST_OPCODE(t0) # extract opcode from rINST - GET_OPCODE_TARGET(t0) - STORE64_off(a2, a3, a0, MIRROR_WIDE_ARRAY_DATA_OFFSET) # a2/a3 <- vBB[vCC] - JR(t0) # jump to next instruction diff --git a/runtime/interpreter/mterp/mips/op_array_length.S b/runtime/interpreter/mterp/mips/op_array_length.S deleted file mode 100644 index 12348bd3f2..0000000000 --- a/runtime/interpreter/mterp/mips/op_array_length.S +++ /dev/null @@ -1,14 +0,0 @@ -%def op_array_length(): - /* - * Return the length of an array. - */ - /* array-length vA, vB */ - GET_OPB(a1) # a1 <- B - GET_OPA4(a2) # a2 <- A+ - GET_VREG(a0, a1) # a0 <- vB (object ref) - # is object null? - beqz a0, common_errNullObject # yup, fail - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - LOAD_base_offMirrorArray_length(a3, a0) # a3 <- array length - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a3, a2, t0) # vA <- length diff --git a/runtime/interpreter/mterp/mips/op_check_cast.S b/runtime/interpreter/mterp/mips/op_check_cast.S deleted file mode 100644 index 4d0f28681c..0000000000 --- a/runtime/interpreter/mterp/mips/op_check_cast.S +++ /dev/null @@ -1,17 +0,0 @@ -%def op_check_cast(): - /* - * Check to see if a cast from one class to another is allowed. - */ - /* check-cast vAA, class@BBBB */ - EXPORT_PC() - FETCH(a0, 1) # a0 <- BBBB - GET_OPA(a1) # a1 <- AA - EAS2(a1, rFP, a1) # a1 <- &object - lw a2, OFF_FP_METHOD(rFP) # a2 <- method - move a3, rSELF # a3 <- self - JAL(MterpCheckCast) # v0 <- CheckCast(index, &obj, method, self) - PREFETCH_INST(2) - bnez v0, MterpPossibleException - ADVANCE(2) - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction diff --git a/runtime/interpreter/mterp/mips/op_cmp_long.S b/runtime/interpreter/mterp/mips/op_cmp_long.S deleted file mode 100644 index 7d40b0e459..0000000000 --- a/runtime/interpreter/mterp/mips/op_cmp_long.S +++ /dev/null @@ -1,35 +0,0 @@ -%def op_cmp_long(): - /* - * Compare two 64-bit values - * x = y return 0 - * x < y return -1 - * x > y return 1 - * - * I think I can improve on the ARM code by the following observation - * slt t0, x.hi, y.hi; # (x.hi < y.hi) ? 1:0 - * sgt t1, x.hi, y.hi; # (y.hi > x.hi) ? 1:0 - * subu v0, t0, t1 # v0= -1:1:0 for [ < > = ] - */ - /* cmp-long vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 # a3 <- CC - EAS2(a2, rFP, a2) # a2 <- &fp[BB] - EAS2(a3, rFP, a3) # a3 <- &fp[CC] - LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 - LOAD64(a2, a3, a3) # a2/a3 <- vCC/vCC+1 - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - slt t0, a1, a3 # compare hi - sgt t1, a1, a3 - subu v0, t1, t0 # v0 <- (-1, 1, 0) - bnez v0, .L${opcode}_finish - # at this point x.hi==y.hi - sltu t0, a0, a2 # compare lo - sgtu t1, a0, a2 - subu v0, t1, t0 # v0 <- (-1, 1, 0) for [< > =] - -.L${opcode}_finish: - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(v0, rOBJ, t0) # vAA <- v0 diff --git a/runtime/interpreter/mterp/mips/op_cmpg_double.S b/runtime/interpreter/mterp/mips/op_cmpg_double.S deleted file mode 100644 index 8e3d181850..0000000000 --- a/runtime/interpreter/mterp/mips/op_cmpg_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_cmpg_double(): -% op_cmpl_double(gt_bias="1") diff --git a/runtime/interpreter/mterp/mips/op_cmpg_float.S b/runtime/interpreter/mterp/mips/op_cmpg_float.S deleted file mode 100644 index d8afa2a1f4..0000000000 --- a/runtime/interpreter/mterp/mips/op_cmpg_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_cmpg_float(): -% op_cmpl_float(gt_bias="1") diff --git a/runtime/interpreter/mterp/mips/op_cmpl_double.S b/runtime/interpreter/mterp/mips/op_cmpl_double.S deleted file mode 100644 index ab6dd49a5d..0000000000 --- a/runtime/interpreter/mterp/mips/op_cmpl_double.S +++ /dev/null @@ -1,52 +0,0 @@ -%def op_cmpl_double(gt_bias="0"): - /* - * Compare two floating-point values. Puts 0(==), 1(>), or -1(<) - * into the destination register based on the comparison results. - * - * For: cmpl-double, cmpg-double - */ - /* op vAA, vBB, vCC */ - - FETCH(a0, 1) # a0 <- CCBB - and rOBJ, a0, 255 # rOBJ <- BB - srl t0, a0, 8 # t0 <- CC - EAS2(rOBJ, rFP, rOBJ) # rOBJ <- &fp[BB] - EAS2(t0, rFP, t0) # t0 <- &fp[CC] - LOAD64_F(ft0, ft0f, rOBJ) - LOAD64_F(ft1, ft1f, t0) -#ifdef MIPS32REVGE6 - cmp.eq.d ft2, ft0, ft1 - li rTEMP, 0 - bc1nez ft2, 1f # done if vBB == vCC (ordered) - .if $gt_bias - cmp.lt.d ft2, ft0, ft1 - li rTEMP, -1 - bc1nez ft2, 1f # done if vBB < vCC (ordered) - li rTEMP, 1 # vBB > vCC or unordered - .else - cmp.lt.d ft2, ft1, ft0 - li rTEMP, 1 - bc1nez ft2, 1f # done if vBB > vCC (ordered) - li rTEMP, -1 # vBB < vCC or unordered - .endif -#else - c.eq.d fcc0, ft0, ft1 - li rTEMP, 0 - bc1t fcc0, 1f # done if vBB == vCC (ordered) - .if $gt_bias - c.olt.d fcc0, ft0, ft1 - li rTEMP, -1 - bc1t fcc0, 1f # done if vBB < vCC (ordered) - li rTEMP, 1 # vBB > vCC or unordered - .else - c.olt.d fcc0, ft1, ft0 - li rTEMP, 1 - bc1t fcc0, 1f # done if vBB > vCC (ordered) - li rTEMP, -1 # vBB < vCC or unordered - .endif -#endif -1: - GET_OPA(rOBJ) - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(rTEMP, rOBJ, t0) # vAA <- rTEMP diff --git a/runtime/interpreter/mterp/mips/op_cmpl_float.S b/runtime/interpreter/mterp/mips/op_cmpl_float.S deleted file mode 100644 index 6542844215..0000000000 --- a/runtime/interpreter/mterp/mips/op_cmpl_float.S +++ /dev/null @@ -1,50 +0,0 @@ -%def op_cmpl_float(gt_bias="0"): - /* - * Compare two floating-point values. Puts 0(==), 1(>), or -1(<) - * into the destination register based on the comparison results. - * - * for: cmpl-float, cmpg-float - */ - /* op vAA, vBB, vCC */ - - FETCH(a0, 1) # a0 <- CCBB - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 - GET_VREG_F(ft0, a2) - GET_VREG_F(ft1, a3) -#ifdef MIPS32REVGE6 - cmp.eq.s ft2, ft0, ft1 - li rTEMP, 0 - bc1nez ft2, 1f # done if vBB == vCC (ordered) - .if $gt_bias - cmp.lt.s ft2, ft0, ft1 - li rTEMP, -1 - bc1nez ft2, 1f # done if vBB < vCC (ordered) - li rTEMP, 1 # vBB > vCC or unordered - .else - cmp.lt.s ft2, ft1, ft0 - li rTEMP, 1 - bc1nez ft2, 1f # done if vBB > vCC (ordered) - li rTEMP, -1 # vBB < vCC or unordered - .endif -#else - c.eq.s fcc0, ft0, ft1 - li rTEMP, 0 - bc1t fcc0, 1f # done if vBB == vCC (ordered) - .if $gt_bias - c.olt.s fcc0, ft0, ft1 - li rTEMP, -1 - bc1t fcc0, 1f # done if vBB < vCC (ordered) - li rTEMP, 1 # vBB > vCC or unordered - .else - c.olt.s fcc0, ft1, ft0 - li rTEMP, 1 - bc1t fcc0, 1f # done if vBB > vCC (ordered) - li rTEMP, -1 # vBB < vCC or unordered - .endif -#endif -1: - GET_OPA(rOBJ) - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(rTEMP, rOBJ, t0) # vAA <- rTEMP diff --git a/runtime/interpreter/mterp/mips/op_const.S b/runtime/interpreter/mterp/mips/op_const.S deleted file mode 100644 index 5b429d4b54..0000000000 --- a/runtime/interpreter/mterp/mips/op_const.S +++ /dev/null @@ -1,9 +0,0 @@ -%def op_const(): - /* const vAA, +BBBBbbbb */ - GET_OPA(a3) # a3 <- AA - FETCH(a0, 1) # a0 <- bbbb (low) - FETCH(a1, 2) # a1 <- BBBB (high) - FETCH_ADVANCE_INST(3) # advance rPC, load rINST - INSERT_HIGH_HALF(a0, a1) # a0 <- BBBBbbbb - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, a3, t0) # vAA <- a0 diff --git a/runtime/interpreter/mterp/mips/op_const_16.S b/runtime/interpreter/mterp/mips/op_const_16.S deleted file mode 100644 index 85669a91b3..0000000000 --- a/runtime/interpreter/mterp/mips/op_const_16.S +++ /dev/null @@ -1,7 +0,0 @@ -%def op_const_16(): - /* const/16 vAA, +BBBB */ - FETCH_S(a0, 1) # a0 <- ssssBBBB (sign-extended) - GET_OPA(a3) # a3 <- AA - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, a3, t0) # vAA <- a0 diff --git a/runtime/interpreter/mterp/mips/op_const_4.S b/runtime/interpreter/mterp/mips/op_const_4.S deleted file mode 100644 index 158a24658a..0000000000 --- a/runtime/interpreter/mterp/mips/op_const_4.S +++ /dev/null @@ -1,9 +0,0 @@ -%def op_const_4(): - /* const/4 vA, +B */ - sll a1, rINST, 16 # a1 <- Bxxx0000 - GET_OPA(a0) # a0 <- A+ - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - sra a1, a1, 28 # a1 <- sssssssB (sign-extended) - and a0, a0, 15 - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a1, a0, t0) # fp[A] <- a1 diff --git a/runtime/interpreter/mterp/mips/op_const_class.S b/runtime/interpreter/mterp/mips/op_const_class.S deleted file mode 100644 index db12ec3141..0000000000 --- a/runtime/interpreter/mterp/mips/op_const_class.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_const_class(): -% const(helper="MterpConstClass") diff --git a/runtime/interpreter/mterp/mips/op_const_high16.S b/runtime/interpreter/mterp/mips/op_const_high16.S deleted file mode 100644 index fee5296320..0000000000 --- a/runtime/interpreter/mterp/mips/op_const_high16.S +++ /dev/null @@ -1,8 +0,0 @@ -%def op_const_high16(): - /* const/high16 vAA, +BBBB0000 */ - FETCH(a0, 1) # a0 <- 0000BBBB (zero-extended) - GET_OPA(a3) # a3 <- AA - sll a0, a0, 16 # a0 <- BBBB0000 - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, a3, t0) # vAA <- a0 diff --git a/runtime/interpreter/mterp/mips/op_const_method_handle.S b/runtime/interpreter/mterp/mips/op_const_method_handle.S deleted file mode 100644 index 2680c17aad..0000000000 --- a/runtime/interpreter/mterp/mips/op_const_method_handle.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_const_method_handle(): -% const(helper="MterpConstMethodHandle") diff --git a/runtime/interpreter/mterp/mips/op_const_method_type.S b/runtime/interpreter/mterp/mips/op_const_method_type.S deleted file mode 100644 index ea814bf648..0000000000 --- a/runtime/interpreter/mterp/mips/op_const_method_type.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_const_method_type(): -% const(helper="MterpConstMethodType") diff --git a/runtime/interpreter/mterp/mips/op_const_string.S b/runtime/interpreter/mterp/mips/op_const_string.S deleted file mode 100644 index 41376f8703..0000000000 --- a/runtime/interpreter/mterp/mips/op_const_string.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_const_string(): -% const(helper="MterpConstString") diff --git a/runtime/interpreter/mterp/mips/op_const_string_jumbo.S b/runtime/interpreter/mterp/mips/op_const_string_jumbo.S deleted file mode 100644 index 0a031f3356..0000000000 --- a/runtime/interpreter/mterp/mips/op_const_string_jumbo.S +++ /dev/null @@ -1,15 +0,0 @@ -%def op_const_string_jumbo(): - /* const/string vAA, string@BBBBBBBB */ - EXPORT_PC() - FETCH(a0, 1) # a0 <- bbbb (low) - FETCH(a2, 2) # a2 <- BBBB (high) - GET_OPA(a1) # a1 <- AA - INSERT_HIGH_HALF(a0, a2) # a0 <- BBBBbbbb - addu a2, rFP, OFF_FP_SHADOWFRAME # a2 <- shadow frame - move a3, rSELF - JAL(MterpConstString) # v0 <- Mterp(index, tgt_reg, shadow_frame, self) - PREFETCH_INST(3) # load rINST - bnez v0, MterpPossibleException - ADVANCE(3) # advance rPC - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction diff --git a/runtime/interpreter/mterp/mips/op_const_wide.S b/runtime/interpreter/mterp/mips/op_const_wide.S deleted file mode 100644 index b424237135..0000000000 --- a/runtime/interpreter/mterp/mips/op_const_wide.S +++ /dev/null @@ -1,12 +0,0 @@ -%def op_const_wide(): - /* const-wide vAA, +HHHHhhhhBBBBbbbb */ - FETCH(a0, 1) # a0 <- bbbb (low) - FETCH(a1, 2) # a1 <- BBBB (low middle) - FETCH(a2, 3) # a2 <- hhhh (high middle) - INSERT_HIGH_HALF(a0, a1) # a0 <- BBBBbbbb (low word) - FETCH(a3, 4) # a3 <- HHHH (high) - GET_OPA(t1) # t1 <- AA - INSERT_HIGH_HALF(a2, a3) # a2 <- HHHHhhhh (high word) - FETCH_ADVANCE_INST(5) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(a0, a2, t1, t0) # vAA/vAA+1 <- a0/a2 diff --git a/runtime/interpreter/mterp/mips/op_const_wide_16.S b/runtime/interpreter/mterp/mips/op_const_wide_16.S deleted file mode 100644 index d89a2b629c..0000000000 --- a/runtime/interpreter/mterp/mips/op_const_wide_16.S +++ /dev/null @@ -1,8 +0,0 @@ -%def op_const_wide_16(): - /* const-wide/16 vAA, +BBBB */ - FETCH_S(a0, 1) # a0 <- ssssBBBB (sign-extended) - GET_OPA(a3) # a3 <- AA - sra a1, a0, 31 # a1 <- ssssssss - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(a0, a1, a3, t0) # vAA/vAA+1 <- a0/a1 diff --git a/runtime/interpreter/mterp/mips/op_const_wide_32.S b/runtime/interpreter/mterp/mips/op_const_wide_32.S deleted file mode 100644 index f9db95367a..0000000000 --- a/runtime/interpreter/mterp/mips/op_const_wide_32.S +++ /dev/null @@ -1,10 +0,0 @@ -%def op_const_wide_32(): - /* const-wide/32 vAA, +BBBBbbbb */ - FETCH(a0, 1) # a0 <- 0000bbbb (low) - GET_OPA(a3) # a3 <- AA - FETCH_S(a2, 2) # a2 <- ssssBBBB (high) - FETCH_ADVANCE_INST(3) # advance rPC, load rINST - INSERT_HIGH_HALF(a0, a2) # a0 <- BBBBbbbb - sra a1, a0, 31 # a1 <- ssssssss - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(a0, a1, a3, t0) # vAA/vAA+1 <- a0/a1 diff --git a/runtime/interpreter/mterp/mips/op_const_wide_high16.S b/runtime/interpreter/mterp/mips/op_const_wide_high16.S deleted file mode 100644 index dd0cd947f2..0000000000 --- a/runtime/interpreter/mterp/mips/op_const_wide_high16.S +++ /dev/null @@ -1,9 +0,0 @@ -%def op_const_wide_high16(): - /* const-wide/high16 vAA, +BBBB000000000000 */ - FETCH(a1, 1) # a1 <- 0000BBBB (zero-extended) - GET_OPA(a3) # a3 <- AA - li a0, 0 # a0 <- 00000000 - sll a1, 16 # a1 <- BBBB0000 - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(a0, a1, a3, t0) # vAA/vAA+1 <- a0/a1 diff --git a/runtime/interpreter/mterp/mips/op_div_double.S b/runtime/interpreter/mterp/mips/op_div_double.S deleted file mode 100644 index e1324d0dc7..0000000000 --- a/runtime/interpreter/mterp/mips/op_div_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_double(): -% fbinopWide(instr="div.d fv0, fa0, fa1") diff --git a/runtime/interpreter/mterp/mips/op_div_double_2addr.S b/runtime/interpreter/mterp/mips/op_div_double_2addr.S deleted file mode 100644 index aa6d16d4a9..0000000000 --- a/runtime/interpreter/mterp/mips/op_div_double_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_double_2addr(): -% fbinopWide2addr(instr="div.d fv0, fa0, fa1") diff --git a/runtime/interpreter/mterp/mips/op_div_float.S b/runtime/interpreter/mterp/mips/op_div_float.S deleted file mode 100644 index b00c44c545..0000000000 --- a/runtime/interpreter/mterp/mips/op_div_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_float(): -% fbinop(instr="div.s fv0, fa0, fa1") diff --git a/runtime/interpreter/mterp/mips/op_div_float_2addr.S b/runtime/interpreter/mterp/mips/op_div_float_2addr.S deleted file mode 100644 index 5201603e42..0000000000 --- a/runtime/interpreter/mterp/mips/op_div_float_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_float_2addr(): -% fbinop2addr(instr="div.s fv0, fa0, fa1") diff --git a/runtime/interpreter/mterp/mips/op_div_int.S b/runtime/interpreter/mterp/mips/op_div_int.S deleted file mode 100644 index 2b49fd25e7..0000000000 --- a/runtime/interpreter/mterp/mips/op_div_int.S +++ /dev/null @@ -1,6 +0,0 @@ -%def op_div_int(): -#ifdef MIPS32REVGE6 -% binop(instr="div a0, a0, a1", chkzero="1") -#else -% binop(preinstr="div zero, a0, a1", instr="mflo a0", chkzero="1") -#endif diff --git a/runtime/interpreter/mterp/mips/op_div_int_2addr.S b/runtime/interpreter/mterp/mips/op_div_int_2addr.S deleted file mode 100644 index 325a5e6b0a..0000000000 --- a/runtime/interpreter/mterp/mips/op_div_int_2addr.S +++ /dev/null @@ -1,6 +0,0 @@ -%def op_div_int_2addr(): -#ifdef MIPS32REVGE6 -% binop2addr(instr="div a0, a0, a1", chkzero="1") -#else -% binop2addr(preinstr="div zero, a0, a1", instr="mflo a0", chkzero="1") -#endif diff --git a/runtime/interpreter/mterp/mips/op_div_int_lit16.S b/runtime/interpreter/mterp/mips/op_div_int_lit16.S deleted file mode 100644 index 7eaf340a4b..0000000000 --- a/runtime/interpreter/mterp/mips/op_div_int_lit16.S +++ /dev/null @@ -1,6 +0,0 @@ -%def op_div_int_lit16(): -#ifdef MIPS32REVGE6 -% binopLit16(instr="div a0, a0, a1", chkzero="1") -#else -% binopLit16(preinstr="div zero, a0, a1", instr="mflo a0", chkzero="1") -#endif diff --git a/runtime/interpreter/mterp/mips/op_div_int_lit8.S b/runtime/interpreter/mterp/mips/op_div_int_lit8.S deleted file mode 100644 index b6aebb72be..0000000000 --- a/runtime/interpreter/mterp/mips/op_div_int_lit8.S +++ /dev/null @@ -1,6 +0,0 @@ -%def op_div_int_lit8(): -#ifdef MIPS32REVGE6 -% binopLit8(instr="div a0, a0, a1", chkzero="1") -#else -% binopLit8(preinstr="div zero, a0, a1", instr="mflo a0", chkzero="1") -#endif diff --git a/runtime/interpreter/mterp/mips/op_div_long.S b/runtime/interpreter/mterp/mips/op_div_long.S deleted file mode 100644 index 631125927c..0000000000 --- a/runtime/interpreter/mterp/mips/op_div_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_long(): -% binopWide(result0="v0", result1="v1", instr="JAL(__divdi3)", chkzero="1") diff --git a/runtime/interpreter/mterp/mips/op_div_long_2addr.S b/runtime/interpreter/mterp/mips/op_div_long_2addr.S deleted file mode 100644 index b3f72932d6..0000000000 --- a/runtime/interpreter/mterp/mips/op_div_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_long_2addr(): -% binopWide2addr(result0="v0", result1="v1", instr="JAL(__divdi3)", chkzero="1") diff --git a/runtime/interpreter/mterp/mips/op_double_to_float.S b/runtime/interpreter/mterp/mips/op_double_to_float.S deleted file mode 100644 index c3f2fedb03..0000000000 --- a/runtime/interpreter/mterp/mips/op_double_to_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_double_to_float(): -% unopNarrower(instr="cvt.s.d fv0, fa0") diff --git a/runtime/interpreter/mterp/mips/op_double_to_int.S b/runtime/interpreter/mterp/mips/op_double_to_int.S deleted file mode 100644 index a522c9c542..0000000000 --- a/runtime/interpreter/mterp/mips/op_double_to_int.S +++ /dev/null @@ -1,32 +0,0 @@ -%def op_double_to_int(): - /* - * double-to-int - * - * We have to clip values to int min/max per the specification. The - * expected common case is a "reasonable" value that converts directly - * to modest integer. The EABI convert function isn't doing this for us - * for pre-R6. - */ - /* unop vA, vB */ - GET_OPB(a3) # a3 <- B - GET_OPA4(rOBJ) # rOBJ <- A+ - EAS2(a3, rFP, a3) # a3 <- &fp[B] - LOAD64_F(fa0, fa0f, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST -#ifndef MIPS32REVGE6 - li t0, INT_MIN_AS_DOUBLE_HIGH - mtc1 zero, fa1 - MOVE_TO_FPU_HIGH(t0, fa1, fa1f) - c.ole.d fcc0, fa1, fa0 -#endif - GET_INST_OPCODE(t1) # extract opcode from rINST -#ifndef MIPS32REVGE6 - bc1t fcc0, 1f # if INT_MIN <= vB, proceed to truncation - c.eq.d fcc0, fa0, fa0 - mtc1 zero, fa0 - MOVE_TO_FPU_HIGH(zero, fa0, fa0f) - movt.d fa0, fa1, fcc0 # fa0 = ordered(vB) ? INT_MIN_AS_DOUBLE : 0 -1: -#endif - trunc.w.d fa0, fa0 - SET_VREG_F_GOTO(fa0, rOBJ, t1) # vA <- result diff --git a/runtime/interpreter/mterp/mips/op_double_to_long.S b/runtime/interpreter/mterp/mips/op_double_to_long.S deleted file mode 100644 index bfc17f51ce..0000000000 --- a/runtime/interpreter/mterp/mips/op_double_to_long.S +++ /dev/null @@ -1,51 +0,0 @@ -%def op_double_to_long(): - /* - * double-to-long - * - * We have to clip values to long min/max per the specification. The - * expected common case is a "reasonable" value that converts directly - * to modest integer. The EABI convert function isn't doing this for us - * for pre-R6. - */ - /* unop vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - EAS2(a3, rFP, a3) # a3 <- &fp[B] - LOAD64_F(fa0, fa0f, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - -#ifdef MIPS32REVGE6 - GET_INST_OPCODE(t1) # extract opcode from rINST - trunc.l.d fa0, fa0 - SET_VREG64_F_GOTO(fa0, fa0f, rOBJ, t1) # vA <- result -#else - c.eq.d fcc0, fa0, fa0 - li rRESULT0, 0 - li rRESULT1, 0 - bc1f fcc0, .L${opcode}_get_opcode - - li t0, LONG_MIN_AS_DOUBLE_HIGH - mtc1 zero, fa1 - MOVE_TO_FPU_HIGH(t0, fa1, fa1f) - c.ole.d fcc0, fa0, fa1 - li rRESULT1, LONG_MIN_HIGH - bc1t fcc0, .L${opcode}_get_opcode - - neg.d fa1, fa1 - c.ole.d fcc0, fa1, fa0 - nor rRESULT0, rRESULT0, zero - nor rRESULT1, rRESULT1, zero - bc1t fcc0, .L${opcode}_get_opcode - - JAL(__fixdfdi) - GET_INST_OPCODE(t1) # extract opcode from rINST - b .L${opcode}_set_vreg -#endif -%def op_double_to_long_sister_code(): - -#ifndef MIPS32REVGE6 -.L${opcode}_get_opcode: - GET_INST_OPCODE(t1) # extract opcode from rINST -.L${opcode}_set_vreg: - SET_VREG64_GOTO(rRESULT0, rRESULT1, rOBJ, t1) # vA/vA+1 <- v0/v1 -#endif diff --git a/runtime/interpreter/mterp/mips/op_fill_array_data.S b/runtime/interpreter/mterp/mips/op_fill_array_data.S deleted file mode 100644 index 558f68e5b8..0000000000 --- a/runtime/interpreter/mterp/mips/op_fill_array_data.S +++ /dev/null @@ -1,14 +0,0 @@ -%def op_fill_array_data(): - /* fill-array-data vAA, +BBBBBBBB */ - EXPORT_PC() - FETCH(a1, 1) # a1 <- bbbb (lo) - FETCH(a0, 2) # a0 <- BBBB (hi) - GET_OPA(a3) # a3 <- AA - INSERT_HIGH_HALF(a1, a0) # a1 <- BBBBbbbb - GET_VREG(a0, a3) # a0 <- vAA (array object) - EAS1(a1, rPC, a1) # a1 <- PC + BBBBbbbb*2 (array data off.) - JAL(MterpFillArrayData) # v0 <- Mterp(obj, payload) - beqz v0, MterpPossibleException # has exception - FETCH_ADVANCE_INST(3) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction diff --git a/runtime/interpreter/mterp/mips/op_filled_new_array.S b/runtime/interpreter/mterp/mips/op_filled_new_array.S deleted file mode 100644 index 6ac6314bf8..0000000000 --- a/runtime/interpreter/mterp/mips/op_filled_new_array.S +++ /dev/null @@ -1,18 +0,0 @@ -%def op_filled_new_array(helper="MterpFilledNewArray"): - /* - * Create a new array with elements filled from registers. - * - * for: filled-new-array, filled-new-array/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ - .extern $helper - EXPORT_PC() - addu a0, rFP, OFF_FP_SHADOWFRAME # a0 <- shadow frame - move a1, rPC - move a2, rSELF - JAL($helper) # v0 <- helper(shadow_frame, pc, self) - beqz v0, MterpPossibleException # has exception - FETCH_ADVANCE_INST(3) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction diff --git a/runtime/interpreter/mterp/mips/op_filled_new_array_range.S b/runtime/interpreter/mterp/mips/op_filled_new_array_range.S deleted file mode 100644 index 1667de149a..0000000000 --- a/runtime/interpreter/mterp/mips/op_filled_new_array_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_filled_new_array_range(): -% op_filled_new_array(helper="MterpFilledNewArrayRange") diff --git a/runtime/interpreter/mterp/mips/op_float_to_double.S b/runtime/interpreter/mterp/mips/op_float_to_double.S deleted file mode 100644 index c0235a88e7..0000000000 --- a/runtime/interpreter/mterp/mips/op_float_to_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_float_to_double(): -% funopWider(instr="cvt.d.s fv0, fa0") diff --git a/runtime/interpreter/mterp/mips/op_float_to_int.S b/runtime/interpreter/mterp/mips/op_float_to_int.S deleted file mode 100644 index 2c0c418323..0000000000 --- a/runtime/interpreter/mterp/mips/op_float_to_int.S +++ /dev/null @@ -1,30 +0,0 @@ -%def op_float_to_int(): - /* - * float-to-int - * - * We have to clip values to int min/max per the specification. The - * expected common case is a "reasonable" value that converts directly - * to modest integer. The EABI convert function isn't doing this for us - * for pre-R6. - */ - /* unop vA, vB */ - GET_OPB(a3) # a3 <- B - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_VREG_F(fa0, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - -#ifndef MIPS32REVGE6 - li t0, INT_MIN_AS_FLOAT - mtc1 t0, fa1 - c.ole.s fcc0, fa1, fa0 -#endif - GET_INST_OPCODE(t1) # extract opcode from rINST -#ifndef MIPS32REVGE6 - bc1t fcc0, 1f # if INT_MIN <= vB, proceed to truncation - c.eq.s fcc0, fa0, fa0 - mtc1 zero, fa0 - movt.s fa0, fa1, fcc0 # fa0 = ordered(vB) ? INT_MIN_AS_FLOAT : 0 -1: -#endif - trunc.w.s fa0, fa0 - SET_VREG_F_GOTO(fa0, rOBJ, t1) # vA <- result diff --git a/runtime/interpreter/mterp/mips/op_float_to_long.S b/runtime/interpreter/mterp/mips/op_float_to_long.S deleted file mode 100644 index 2134e630ae..0000000000 --- a/runtime/interpreter/mterp/mips/op_float_to_long.S +++ /dev/null @@ -1,49 +0,0 @@ -%def op_float_to_long(): - /* - * float-to-long - * - * We have to clip values to long min/max per the specification. The - * expected common case is a "reasonable" value that converts directly - * to modest integer. The EABI convert function isn't doing this for us - * for pre-R6. - */ - /* unop vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG_F(fa0, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - -#ifdef MIPS32REVGE6 - GET_INST_OPCODE(t1) # extract opcode from rINST - trunc.l.s fa0, fa0 - SET_VREG64_F_GOTO(fa0, fa0f, rOBJ, t1) # vA <- result -#else - c.eq.s fcc0, fa0, fa0 - li rRESULT0, 0 - li rRESULT1, 0 - bc1f fcc0, .L${opcode}_get_opcode - - li t0, LONG_MIN_AS_FLOAT - mtc1 t0, fa1 - c.ole.s fcc0, fa0, fa1 - li rRESULT1, LONG_MIN_HIGH - bc1t fcc0, .L${opcode}_get_opcode - - neg.s fa1, fa1 - c.ole.s fcc0, fa1, fa0 - nor rRESULT0, rRESULT0, zero - nor rRESULT1, rRESULT1, zero - bc1t fcc0, .L${opcode}_get_opcode - - JAL(__fixsfdi) - GET_INST_OPCODE(t1) # extract opcode from rINST - b .L${opcode}_set_vreg -#endif -%def op_float_to_long_sister_code(): - -#ifndef MIPS32REVGE6 -.L${opcode}_get_opcode: - GET_INST_OPCODE(t1) # extract opcode from rINST -.L${opcode}_set_vreg: - SET_VREG64_GOTO(rRESULT0, rRESULT1, rOBJ, t1) # vA/vA+1 <- v0/v1 -#endif diff --git a/runtime/interpreter/mterp/mips/op_goto.S b/runtime/interpreter/mterp/mips/op_goto.S deleted file mode 100644 index 8da1339257..0000000000 --- a/runtime/interpreter/mterp/mips/op_goto.S +++ /dev/null @@ -1,11 +0,0 @@ -%def op_goto(): - /* - * Unconditional branch, 8-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto +AA */ - sll a0, rINST, 16 # a0 <- AAxx0000 - sra rINST, a0, 24 # rINST <- ssssssAA (sign-extended) - b MterpCommonTakenBranchNoFlags diff --git a/runtime/interpreter/mterp/mips/op_goto_16.S b/runtime/interpreter/mterp/mips/op_goto_16.S deleted file mode 100644 index 55a055b329..0000000000 --- a/runtime/interpreter/mterp/mips/op_goto_16.S +++ /dev/null @@ -1,10 +0,0 @@ -%def op_goto_16(): - /* - * Unconditional branch, 16-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto/16 +AAAA */ - FETCH_S(rINST, 1) # rINST <- ssssAAAA (sign-extended) - b MterpCommonTakenBranchNoFlags diff --git a/runtime/interpreter/mterp/mips/op_goto_32.S b/runtime/interpreter/mterp/mips/op_goto_32.S deleted file mode 100644 index e969bd2048..0000000000 --- a/runtime/interpreter/mterp/mips/op_goto_32.S +++ /dev/null @@ -1,15 +0,0 @@ -%def op_goto_32(): - /* - * Unconditional branch, 32-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - * - * Unlike most opcodes, this one is allowed to branch to itself, so - * our "backward branch" test must be "<=0" instead of "<0". - */ - /* goto/32 +AAAAAAAA */ - FETCH(rINST, 1) # rINST <- aaaa (lo) - FETCH(a1, 2) # a1 <- AAAA (hi) - INSERT_HIGH_HALF(rINST, a1) # rINST <- AAAAaaaa - b MterpCommonTakenBranchNoFlags diff --git a/runtime/interpreter/mterp/mips/op_if_eq.S b/runtime/interpreter/mterp/mips/op_if_eq.S deleted file mode 100644 index da58674fd4..0000000000 --- a/runtime/interpreter/mterp/mips/op_if_eq.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_eq(): -% bincmp(condition="eq") diff --git a/runtime/interpreter/mterp/mips/op_if_eqz.S b/runtime/interpreter/mterp/mips/op_if_eqz.S deleted file mode 100644 index 0639664d47..0000000000 --- a/runtime/interpreter/mterp/mips/op_if_eqz.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_eqz(): -% zcmp(condition="eq") diff --git a/runtime/interpreter/mterp/mips/op_if_ge.S b/runtime/interpreter/mterp/mips/op_if_ge.S deleted file mode 100644 index 5b6ed2f994..0000000000 --- a/runtime/interpreter/mterp/mips/op_if_ge.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_ge(): -% bincmp(condition="ge") diff --git a/runtime/interpreter/mterp/mips/op_if_gez.S b/runtime/interpreter/mterp/mips/op_if_gez.S deleted file mode 100644 index ea6cda71fb..0000000000 --- a/runtime/interpreter/mterp/mips/op_if_gez.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_gez(): -% zcmp(condition="ge") diff --git a/runtime/interpreter/mterp/mips/op_if_gt.S b/runtime/interpreter/mterp/mips/op_if_gt.S deleted file mode 100644 index 201decff1a..0000000000 --- a/runtime/interpreter/mterp/mips/op_if_gt.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_gt(): -% bincmp(condition="gt") diff --git a/runtime/interpreter/mterp/mips/op_if_gtz.S b/runtime/interpreter/mterp/mips/op_if_gtz.S deleted file mode 100644 index 1fdbb6e8d2..0000000000 --- a/runtime/interpreter/mterp/mips/op_if_gtz.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_gtz(): -% zcmp(condition="gt") diff --git a/runtime/interpreter/mterp/mips/op_if_le.S b/runtime/interpreter/mterp/mips/op_if_le.S deleted file mode 100644 index e6024f2b3e..0000000000 --- a/runtime/interpreter/mterp/mips/op_if_le.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_le(): -% bincmp(condition="le") diff --git a/runtime/interpreter/mterp/mips/op_if_lez.S b/runtime/interpreter/mterp/mips/op_if_lez.S deleted file mode 100644 index 62c0d2cd39..0000000000 --- a/runtime/interpreter/mterp/mips/op_if_lez.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_lez(): -% zcmp(condition="le") diff --git a/runtime/interpreter/mterp/mips/op_if_lt.S b/runtime/interpreter/mterp/mips/op_if_lt.S deleted file mode 100644 index 4ef22fd798..0000000000 --- a/runtime/interpreter/mterp/mips/op_if_lt.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_lt(): -% bincmp(condition="lt") diff --git a/runtime/interpreter/mterp/mips/op_if_ltz.S b/runtime/interpreter/mterp/mips/op_if_ltz.S deleted file mode 100644 index 84b2d0b53a..0000000000 --- a/runtime/interpreter/mterp/mips/op_if_ltz.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_ltz(): -% zcmp(condition="lt") diff --git a/runtime/interpreter/mterp/mips/op_if_ne.S b/runtime/interpreter/mterp/mips/op_if_ne.S deleted file mode 100644 index ec3a688b29..0000000000 --- a/runtime/interpreter/mterp/mips/op_if_ne.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_ne(): -% bincmp(condition="ne") diff --git a/runtime/interpreter/mterp/mips/op_if_nez.S b/runtime/interpreter/mterp/mips/op_if_nez.S deleted file mode 100644 index 7009c3acaa..0000000000 --- a/runtime/interpreter/mterp/mips/op_if_nez.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_nez(): -% zcmp(condition="ne") diff --git a/runtime/interpreter/mterp/mips/op_iget.S b/runtime/interpreter/mterp/mips/op_iget.S deleted file mode 100644 index d09edc0a17..0000000000 --- a/runtime/interpreter/mterp/mips/op_iget.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget(is_object="0", helper="MterpIGetU32"): -% field(helper=helper) diff --git a/runtime/interpreter/mterp/mips/op_iget_boolean.S b/runtime/interpreter/mterp/mips/op_iget_boolean.S deleted file mode 100644 index cb8edeec77..0000000000 --- a/runtime/interpreter/mterp/mips/op_iget_boolean.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_boolean(): -% op_iget(helper="MterpIGetU8") diff --git a/runtime/interpreter/mterp/mips/op_iget_boolean_quick.S b/runtime/interpreter/mterp/mips/op_iget_boolean_quick.S deleted file mode 100644 index f3d2cb1e97..0000000000 --- a/runtime/interpreter/mterp/mips/op_iget_boolean_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_boolean_quick(): -% op_iget_quick(load="lbu") diff --git a/runtime/interpreter/mterp/mips/op_iget_byte.S b/runtime/interpreter/mterp/mips/op_iget_byte.S deleted file mode 100644 index 2b87fb16b5..0000000000 --- a/runtime/interpreter/mterp/mips/op_iget_byte.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_byte(): -% op_iget(helper="MterpIGetI8") diff --git a/runtime/interpreter/mterp/mips/op_iget_byte_quick.S b/runtime/interpreter/mterp/mips/op_iget_byte_quick.S deleted file mode 100644 index ddb469b3de..0000000000 --- a/runtime/interpreter/mterp/mips/op_iget_byte_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_byte_quick(): -% op_iget_quick(load="lb") diff --git a/runtime/interpreter/mterp/mips/op_iget_char.S b/runtime/interpreter/mterp/mips/op_iget_char.S deleted file mode 100644 index 001bd03e2b..0000000000 --- a/runtime/interpreter/mterp/mips/op_iget_char.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_char(): -% op_iget(helper="MterpIGetU16") diff --git a/runtime/interpreter/mterp/mips/op_iget_char_quick.S b/runtime/interpreter/mterp/mips/op_iget_char_quick.S deleted file mode 100644 index ef0b350d4e..0000000000 --- a/runtime/interpreter/mterp/mips/op_iget_char_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_char_quick(): -% op_iget_quick(load="lhu") diff --git a/runtime/interpreter/mterp/mips/op_iget_object.S b/runtime/interpreter/mterp/mips/op_iget_object.S deleted file mode 100644 index 4e5f769547..0000000000 --- a/runtime/interpreter/mterp/mips/op_iget_object.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_object(): -% op_iget(is_object="1", helper="MterpIGetObj") diff --git a/runtime/interpreter/mterp/mips/op_iget_object_quick.S b/runtime/interpreter/mterp/mips/op_iget_object_quick.S deleted file mode 100644 index 8bfd40b44c..0000000000 --- a/runtime/interpreter/mterp/mips/op_iget_object_quick.S +++ /dev/null @@ -1,15 +0,0 @@ -%def op_iget_object_quick(): - /* For: iget-object-quick */ - /* op vA, vB, offset@CCCC */ - GET_OPB(a2) # a2 <- B - FETCH(a1, 1) # a1 <- field byte offset - EXPORT_PC() - GET_VREG(a0, a2) # a0 <- object we're operating on - JAL(artIGetObjectFromMterp) # v0 <- GetObj(obj, offset) - lw a3, THREAD_EXCEPTION_OFFSET(rSELF) - GET_OPA4(a2) # a2<- A+ - PREFETCH_INST(2) # load rINST - bnez a3, MterpPossibleException # bail out - ADVANCE(2) # advance rPC - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_OBJECT_GOTO(v0, a2, t0) # fp[A] <- v0 diff --git a/runtime/interpreter/mterp/mips/op_iget_quick.S b/runtime/interpreter/mterp/mips/op_iget_quick.S deleted file mode 100644 index b8892fdb91..0000000000 --- a/runtime/interpreter/mterp/mips/op_iget_quick.S +++ /dev/null @@ -1,14 +0,0 @@ -%def op_iget_quick(load="lw"): - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset@CCCC */ - GET_OPB(a2) # a2 <- B - GET_VREG(a3, a2) # a3 <- object we're operating on - FETCH(a1, 1) # a1 <- field byte offset - GET_OPA4(a2) # a2 <- A(+) - # check object for null - beqz a3, common_errNullObject # object was null - addu t0, a3, a1 - $load a0, 0(t0) # a0 <- obj.field (8/16/32 bits) - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, a2, t0) # fp[A] <- a0 diff --git a/runtime/interpreter/mterp/mips/op_iget_short.S b/runtime/interpreter/mterp/mips/op_iget_short.S deleted file mode 100644 index a62c4d998f..0000000000 --- a/runtime/interpreter/mterp/mips/op_iget_short.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_short(): -% op_iget(helper="MterpIGetI16") diff --git a/runtime/interpreter/mterp/mips/op_iget_short_quick.S b/runtime/interpreter/mterp/mips/op_iget_short_quick.S deleted file mode 100644 index 5957cb4600..0000000000 --- a/runtime/interpreter/mterp/mips/op_iget_short_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_short_quick(): -% op_iget_quick(load="lh") diff --git a/runtime/interpreter/mterp/mips/op_iget_wide.S b/runtime/interpreter/mterp/mips/op_iget_wide.S deleted file mode 100644 index 9643cc3403..0000000000 --- a/runtime/interpreter/mterp/mips/op_iget_wide.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_wide(): -% op_iget(helper="MterpIGetU64") diff --git a/runtime/interpreter/mterp/mips/op_iget_wide_quick.S b/runtime/interpreter/mterp/mips/op_iget_wide_quick.S deleted file mode 100644 index 5bc90762dd..0000000000 --- a/runtime/interpreter/mterp/mips/op_iget_wide_quick.S +++ /dev/null @@ -1,13 +0,0 @@ -%def op_iget_wide_quick(): - /* iget-wide-quick vA, vB, offset@CCCC */ - GET_OPB(a2) # a2 <- B - GET_VREG(a3, a2) # a3 <- object we're operating on - FETCH(a1, 1) # a1 <- field byte offset - GET_OPA4(a2) # a2 <- A(+) - # check object for null - beqz a3, common_errNullObject # object was null - addu t0, a3, a1 # t0 <- a3 + a1 - LOAD64(a0, a1, t0) # a0 <- obj.field (64 bits, aligned) - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(a0, a1, a2, t0) # fp[A] <- a0/a1 diff --git a/runtime/interpreter/mterp/mips/op_instance_of.S b/runtime/interpreter/mterp/mips/op_instance_of.S deleted file mode 100644 index 9312e72a10..0000000000 --- a/runtime/interpreter/mterp/mips/op_instance_of.S +++ /dev/null @@ -1,22 +0,0 @@ -%def op_instance_of(): - /* - * Check to see if an object reference is an instance of a class. - * - * Most common situation is a non-null object, being compared against - * an already-resolved class. - */ - /* instance-of vA, vB, class@CCCC */ - EXPORT_PC() - FETCH(a0, 1) # a0 <- CCCC - GET_OPB(a1) # a1 <- B - EAS2(a1, rFP, a1) # a1 <- &object - lw a2, OFF_FP_METHOD(rFP) # a2 <- method - move a3, rSELF # a3 <- self - GET_OPA4(rOBJ) # rOBJ <- A+ - JAL(MterpInstanceOf) # v0 <- Mterp(index, &obj, method, self) - lw a1, THREAD_EXCEPTION_OFFSET(rSELF) - PREFETCH_INST(2) # load rINST - bnez a1, MterpException - ADVANCE(2) # advance rPC - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(v0, rOBJ, t0) # vA <- v0 diff --git a/runtime/interpreter/mterp/mips/op_int_to_byte.S b/runtime/interpreter/mterp/mips/op_int_to_byte.S deleted file mode 100644 index 584172583a..0000000000 --- a/runtime/interpreter/mterp/mips/op_int_to_byte.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_int_to_byte(): -% unop(instr="SEB(a0, a0)") diff --git a/runtime/interpreter/mterp/mips/op_int_to_char.S b/runtime/interpreter/mterp/mips/op_int_to_char.S deleted file mode 100644 index 7fda63792c..0000000000 --- a/runtime/interpreter/mterp/mips/op_int_to_char.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_int_to_char(): -% unop(preinstr="", instr="and a0, 0xffff") diff --git a/runtime/interpreter/mterp/mips/op_int_to_double.S b/runtime/interpreter/mterp/mips/op_int_to_double.S deleted file mode 100644 index 736ebb3053..0000000000 --- a/runtime/interpreter/mterp/mips/op_int_to_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_int_to_double(): -% funopWider(instr="cvt.d.w fv0, fa0") diff --git a/runtime/interpreter/mterp/mips/op_int_to_float.S b/runtime/interpreter/mterp/mips/op_int_to_float.S deleted file mode 100644 index 45ab4c8f8b..0000000000 --- a/runtime/interpreter/mterp/mips/op_int_to_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_int_to_float(): -% funop(instr="cvt.s.w fv0, fa0") diff --git a/runtime/interpreter/mterp/mips/op_int_to_long.S b/runtime/interpreter/mterp/mips/op_int_to_long.S deleted file mode 100644 index 093f181eda..0000000000 --- a/runtime/interpreter/mterp/mips/op_int_to_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_int_to_long(): -% unopWider(instr="sra a1, a0, 31") diff --git a/runtime/interpreter/mterp/mips/op_int_to_short.S b/runtime/interpreter/mterp/mips/op_int_to_short.S deleted file mode 100644 index 38bc451886..0000000000 --- a/runtime/interpreter/mterp/mips/op_int_to_short.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_int_to_short(): -% unop(instr="SEH(a0, a0)") diff --git a/runtime/interpreter/mterp/mips/op_invoke_custom.S b/runtime/interpreter/mterp/mips/op_invoke_custom.S deleted file mode 100644 index 4bba9ee524..0000000000 --- a/runtime/interpreter/mterp/mips/op_invoke_custom.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_custom(): -% invoke(helper="MterpInvokeCustom") diff --git a/runtime/interpreter/mterp/mips/op_invoke_custom_range.S b/runtime/interpreter/mterp/mips/op_invoke_custom_range.S deleted file mode 100644 index 57e61af1fa..0000000000 --- a/runtime/interpreter/mterp/mips/op_invoke_custom_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_custom_range(): -% invoke(helper="MterpInvokeCustomRange") diff --git a/runtime/interpreter/mterp/mips/op_invoke_direct.S b/runtime/interpreter/mterp/mips/op_invoke_direct.S deleted file mode 100644 index d3139cf39b..0000000000 --- a/runtime/interpreter/mterp/mips/op_invoke_direct.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_direct(): -% invoke(helper="MterpInvokeDirect") diff --git a/runtime/interpreter/mterp/mips/op_invoke_direct_range.S b/runtime/interpreter/mterp/mips/op_invoke_direct_range.S deleted file mode 100644 index b4a161f48b..0000000000 --- a/runtime/interpreter/mterp/mips/op_invoke_direct_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_direct_range(): -% invoke(helper="MterpInvokeDirectRange") diff --git a/runtime/interpreter/mterp/mips/op_invoke_interface.S b/runtime/interpreter/mterp/mips/op_invoke_interface.S deleted file mode 100644 index 2e749aa263..0000000000 --- a/runtime/interpreter/mterp/mips/op_invoke_interface.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_interface(): -% invoke(helper="MterpInvokeInterface") diff --git a/runtime/interpreter/mterp/mips/op_invoke_interface_range.S b/runtime/interpreter/mterp/mips/op_invoke_interface_range.S deleted file mode 100644 index 2989115377..0000000000 --- a/runtime/interpreter/mterp/mips/op_invoke_interface_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_interface_range(): -% invoke(helper="MterpInvokeInterfaceRange") diff --git a/runtime/interpreter/mterp/mips/op_invoke_polymorphic.S b/runtime/interpreter/mterp/mips/op_invoke_polymorphic.S deleted file mode 100644 index ce61f5aa0e..0000000000 --- a/runtime/interpreter/mterp/mips/op_invoke_polymorphic.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_polymorphic(): -% invoke_polymorphic(helper="MterpInvokePolymorphic") diff --git a/runtime/interpreter/mterp/mips/op_invoke_polymorphic_range.S b/runtime/interpreter/mterp/mips/op_invoke_polymorphic_range.S deleted file mode 100644 index 16731bdb40..0000000000 --- a/runtime/interpreter/mterp/mips/op_invoke_polymorphic_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_polymorphic_range(): -% invoke_polymorphic(helper="MterpInvokePolymorphicRange") diff --git a/runtime/interpreter/mterp/mips/op_invoke_static.S b/runtime/interpreter/mterp/mips/op_invoke_static.S deleted file mode 100644 index 8b104a66b0..0000000000 --- a/runtime/interpreter/mterp/mips/op_invoke_static.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_static(): -% invoke(helper="MterpInvokeStatic") diff --git a/runtime/interpreter/mterp/mips/op_invoke_static_range.S b/runtime/interpreter/mterp/mips/op_invoke_static_range.S deleted file mode 100644 index e0a546c92b..0000000000 --- a/runtime/interpreter/mterp/mips/op_invoke_static_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_static_range(): -% invoke(helper="MterpInvokeStaticRange") diff --git a/runtime/interpreter/mterp/mips/op_invoke_super.S b/runtime/interpreter/mterp/mips/op_invoke_super.S deleted file mode 100644 index e5921f3d43..0000000000 --- a/runtime/interpreter/mterp/mips/op_invoke_super.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_super(): -% invoke(helper="MterpInvokeSuper") diff --git a/runtime/interpreter/mterp/mips/op_invoke_super_range.S b/runtime/interpreter/mterp/mips/op_invoke_super_range.S deleted file mode 100644 index caeafaa13c..0000000000 --- a/runtime/interpreter/mterp/mips/op_invoke_super_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_super_range(): -% invoke(helper="MterpInvokeSuperRange") diff --git a/runtime/interpreter/mterp/mips/op_invoke_virtual.S b/runtime/interpreter/mterp/mips/op_invoke_virtual.S deleted file mode 100644 index 8767741f28..0000000000 --- a/runtime/interpreter/mterp/mips/op_invoke_virtual.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_virtual(): -% invoke(helper="MterpInvokeVirtual") diff --git a/runtime/interpreter/mterp/mips/op_invoke_virtual_quick.S b/runtime/interpreter/mterp/mips/op_invoke_virtual_quick.S deleted file mode 100644 index ea72c171ec..0000000000 --- a/runtime/interpreter/mterp/mips/op_invoke_virtual_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_virtual_quick(): -% invoke(helper="MterpInvokeVirtualQuick") diff --git a/runtime/interpreter/mterp/mips/op_invoke_virtual_range.S b/runtime/interpreter/mterp/mips/op_invoke_virtual_range.S deleted file mode 100644 index baa0779593..0000000000 --- a/runtime/interpreter/mterp/mips/op_invoke_virtual_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_virtual_range(): -% invoke(helper="MterpInvokeVirtualRange") diff --git a/runtime/interpreter/mterp/mips/op_invoke_virtual_range_quick.S b/runtime/interpreter/mterp/mips/op_invoke_virtual_range_quick.S deleted file mode 100644 index 1d961a0781..0000000000 --- a/runtime/interpreter/mterp/mips/op_invoke_virtual_range_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_virtual_range_quick(): -% invoke(helper="MterpInvokeVirtualQuickRange") diff --git a/runtime/interpreter/mterp/mips/op_iput.S b/runtime/interpreter/mterp/mips/op_iput.S deleted file mode 100644 index e5351baf55..0000000000 --- a/runtime/interpreter/mterp/mips/op_iput.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput(is_object="0", helper="MterpIPutU32"): -% field(helper=helper) diff --git a/runtime/interpreter/mterp/mips/op_iput_boolean.S b/runtime/interpreter/mterp/mips/op_iput_boolean.S deleted file mode 100644 index 9eb849877b..0000000000 --- a/runtime/interpreter/mterp/mips/op_iput_boolean.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_boolean(): -% op_iput(helper="MterpIPutU8") diff --git a/runtime/interpreter/mterp/mips/op_iput_boolean_quick.S b/runtime/interpreter/mterp/mips/op_iput_boolean_quick.S deleted file mode 100644 index 3d818a5a69..0000000000 --- a/runtime/interpreter/mterp/mips/op_iput_boolean_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_boolean_quick(): -% op_iput_quick(store="sb") diff --git a/runtime/interpreter/mterp/mips/op_iput_byte.S b/runtime/interpreter/mterp/mips/op_iput_byte.S deleted file mode 100644 index 4b74f9fb0e..0000000000 --- a/runtime/interpreter/mterp/mips/op_iput_byte.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_byte(): -% op_iput(helper="MterpIPutI8") diff --git a/runtime/interpreter/mterp/mips/op_iput_byte_quick.S b/runtime/interpreter/mterp/mips/op_iput_byte_quick.S deleted file mode 100644 index 06dc24e095..0000000000 --- a/runtime/interpreter/mterp/mips/op_iput_byte_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_byte_quick(): -% op_iput_quick(store="sb") diff --git a/runtime/interpreter/mterp/mips/op_iput_char.S b/runtime/interpreter/mterp/mips/op_iput_char.S deleted file mode 100644 index 64a249fc12..0000000000 --- a/runtime/interpreter/mterp/mips/op_iput_char.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_char(): -% op_iput(helper="MterpIPutU16") diff --git a/runtime/interpreter/mterp/mips/op_iput_char_quick.S b/runtime/interpreter/mterp/mips/op_iput_char_quick.S deleted file mode 100644 index 3b6af5b9fe..0000000000 --- a/runtime/interpreter/mterp/mips/op_iput_char_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_char_quick(): -% op_iput_quick(store="sh") diff --git a/runtime/interpreter/mterp/mips/op_iput_object.S b/runtime/interpreter/mterp/mips/op_iput_object.S deleted file mode 100644 index 131edd5dbd..0000000000 --- a/runtime/interpreter/mterp/mips/op_iput_object.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_object(): -% op_iput(is_object="1", helper="MterpIPutObj") diff --git a/runtime/interpreter/mterp/mips/op_iput_object_quick.S b/runtime/interpreter/mterp/mips/op_iput_object_quick.S deleted file mode 100644 index bb3cbe88ec..0000000000 --- a/runtime/interpreter/mterp/mips/op_iput_object_quick.S +++ /dev/null @@ -1,12 +0,0 @@ -%def op_iput_object_quick(): - /* For: iput-object-quick */ - /* op vA, vB, offset@CCCC */ - EXPORT_PC() - addu a0, rFP, OFF_FP_SHADOWFRAME - move a1, rPC - move a2, rINST - JAL(MterpIputObjectQuick) - beqz v0, MterpException - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction diff --git a/runtime/interpreter/mterp/mips/op_iput_quick.S b/runtime/interpreter/mterp/mips/op_iput_quick.S deleted file mode 100644 index 55067bea22..0000000000 --- a/runtime/interpreter/mterp/mips/op_iput_quick.S +++ /dev/null @@ -1,15 +0,0 @@ -%def op_iput_quick(store="sw"): - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - GET_OPB(a2) # a2 <- B - GET_VREG(a3, a2) # a3 <- fp[B], the object pointer - FETCH(a1, 1) # a1 <- field byte offset - GET_OPA4(a2) # a2 <- A(+) - beqz a3, common_errNullObject # object was null - GET_VREG(a0, a2) # a0 <- fp[A] - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - addu t0, a3, a1 - GET_INST_OPCODE(t1) # extract opcode from rINST - GET_OPCODE_TARGET(t1) - $store a0, 0(t0) # obj.field (8/16/32 bits) <- a0 - JR(t1) # jump to next instruction diff --git a/runtime/interpreter/mterp/mips/op_iput_short.S b/runtime/interpreter/mterp/mips/op_iput_short.S deleted file mode 100644 index e631a3b259..0000000000 --- a/runtime/interpreter/mterp/mips/op_iput_short.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_short(): -% op_iput(helper="MterpIPutI16") diff --git a/runtime/interpreter/mterp/mips/op_iput_short_quick.S b/runtime/interpreter/mterp/mips/op_iput_short_quick.S deleted file mode 100644 index fade093fc1..0000000000 --- a/runtime/interpreter/mterp/mips/op_iput_short_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_short_quick(): -% op_iput_quick(store="sh") diff --git a/runtime/interpreter/mterp/mips/op_iput_wide.S b/runtime/interpreter/mterp/mips/op_iput_wide.S deleted file mode 100644 index 2f34fd39f9..0000000000 --- a/runtime/interpreter/mterp/mips/op_iput_wide.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_wide(): -% op_iput(helper="MterpIPutU64") diff --git a/runtime/interpreter/mterp/mips/op_iput_wide_quick.S b/runtime/interpreter/mterp/mips/op_iput_wide_quick.S deleted file mode 100644 index 7b8e632be0..0000000000 --- a/runtime/interpreter/mterp/mips/op_iput_wide_quick.S +++ /dev/null @@ -1,16 +0,0 @@ -%def op_iput_wide_quick(): - /* iput-wide-quick vA, vB, offset@CCCC */ - GET_OPA4(a0) # a0 <- A(+) - GET_OPB(a1) # a1 <- B - GET_VREG(a2, a1) # a2 <- fp[B], the object pointer - # check object for null - beqz a2, common_errNullObject # object was null - EAS2(a3, rFP, a0) # a3 <- &fp[A] - LOAD64(a0, a1, a3) # a0/a1 <- fp[A] - FETCH(a3, 1) # a3 <- field byte offset - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - addu a2, a2, a3 # obj.field (64 bits, aligned) <- a0/a1 - GET_INST_OPCODE(t0) # extract opcode from rINST - GET_OPCODE_TARGET(t0) - STORE64(a0, a1, a2) # obj.field (64 bits, aligned) <- a0/a1 - JR(t0) # jump to next instruction diff --git a/runtime/interpreter/mterp/mips/op_long_to_double.S b/runtime/interpreter/mterp/mips/op_long_to_double.S deleted file mode 100644 index 5dfc76b0cf..0000000000 --- a/runtime/interpreter/mterp/mips/op_long_to_double.S +++ /dev/null @@ -1,21 +0,0 @@ -%def op_long_to_double(): - /* - * long-to-double - */ - /* unop vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - EAS2(a3, rFP, a3) # a3 <- &fp[B] - -#ifdef MIPS32REVGE6 - LOAD64_F(fv0, fv0f, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - cvt.d.l fv0, fv0 -#else - LOAD64(rARG0, rARG1, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - JAL(__floatdidf) # a0/a1 <- op, a2-a3 changed -#endif - - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vA/vA+1 <- result diff --git a/runtime/interpreter/mterp/mips/op_long_to_float.S b/runtime/interpreter/mterp/mips/op_long_to_float.S deleted file mode 100644 index fcf2a2e22a..0000000000 --- a/runtime/interpreter/mterp/mips/op_long_to_float.S +++ /dev/null @@ -1,21 +0,0 @@ -%def op_long_to_float(): - /* - * long-to-float - */ - /* unop vA, vB */ - GET_OPB(a3) # a3 <- B - GET_OPA4(rOBJ) # rOBJ <- A+ - EAS2(a3, rFP, a3) # a3 <- &fp[B] - -#ifdef MIPS32REVGE6 - LOAD64_F(fv0, fv0f, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - cvt.s.l fv0, fv0 -#else - LOAD64(rARG0, rARG1, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - JAL(__floatdisf) -#endif - - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_F_GOTO(fv0, rOBJ, t0) # vA <- fv0 diff --git a/runtime/interpreter/mterp/mips/op_long_to_int.S b/runtime/interpreter/mterp/mips/op_long_to_int.S deleted file mode 100644 index eacb8f59ec..0000000000 --- a/runtime/interpreter/mterp/mips/op_long_to_int.S +++ /dev/null @@ -1,3 +0,0 @@ -%def op_long_to_int(): -/* we ignore the high word, making this equivalent to a 32-bit reg move */ -% op_move() diff --git a/runtime/interpreter/mterp/mips/op_monitor_enter.S b/runtime/interpreter/mterp/mips/op_monitor_enter.S deleted file mode 100644 index 66e3af5847..0000000000 --- a/runtime/interpreter/mterp/mips/op_monitor_enter.S +++ /dev/null @@ -1,14 +0,0 @@ -%def op_monitor_enter(): - /* - * Synchronize on an object. - */ - /* monitor-enter vAA */ - EXPORT_PC() - GET_OPA(a2) # a2 <- AA - GET_VREG(a0, a2) # a0 <- vAA (object) - move a1, rSELF # a1 <- self - JAL(artLockObjectFromCode) # v0 <- artLockObject(obj, self) - bnez v0, MterpException - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction diff --git a/runtime/interpreter/mterp/mips/op_monitor_exit.S b/runtime/interpreter/mterp/mips/op_monitor_exit.S deleted file mode 100644 index d32d75ccc0..0000000000 --- a/runtime/interpreter/mterp/mips/op_monitor_exit.S +++ /dev/null @@ -1,18 +0,0 @@ -%def op_monitor_exit(): - /* - * Unlock an object. - * - * Exceptions that occur when unlocking a monitor need to appear as - * if they happened at the following instruction. See the Dalvik - * instruction spec. - */ - /* monitor-exit vAA */ - EXPORT_PC() - GET_OPA(a2) # a2 <- AA - GET_VREG(a0, a2) # a0 <- vAA (object) - move a1, rSELF # a1 <- self - JAL(artUnlockObjectFromCode) # v0 <- artUnlockObject(obj, self) - bnez v0, MterpException - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction diff --git a/runtime/interpreter/mterp/mips/op_move.S b/runtime/interpreter/mterp/mips/op_move.S deleted file mode 100644 index a0c1c31016..0000000000 --- a/runtime/interpreter/mterp/mips/op_move.S +++ /dev/null @@ -1,13 +0,0 @@ -%def op_move(is_object="0"): - /* for move, move-object, long-to-int */ - /* op vA, vB */ - GET_OPB(a1) # a1 <- B from 15:12 - GET_OPA4(a0) # a0 <- A from 11:8 - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - GET_VREG(a2, a1) # a2 <- fp[B] - GET_INST_OPCODE(t0) # t0 <- opcode from rINST - .if $is_object - SET_VREG_OBJECT_GOTO(a2, a0, t0) # fp[A] <- a2 - .else - SET_VREG_GOTO(a2, a0, t0) # fp[A] <- a2 - .endif diff --git a/runtime/interpreter/mterp/mips/op_move_16.S b/runtime/interpreter/mterp/mips/op_move_16.S deleted file mode 100644 index 273858ec5a..0000000000 --- a/runtime/interpreter/mterp/mips/op_move_16.S +++ /dev/null @@ -1,13 +0,0 @@ -%def op_move_16(is_object="0"): - /* for: move/16, move-object/16 */ - /* op vAAAA, vBBBB */ - FETCH(a1, 2) # a1 <- BBBB - FETCH(a0, 1) # a0 <- AAAA - FETCH_ADVANCE_INST(3) # advance rPC, load rINST - GET_VREG(a2, a1) # a2 <- fp[BBBB] - GET_INST_OPCODE(t0) # extract opcode from rINST - .if $is_object - SET_VREG_OBJECT_GOTO(a2, a0, t0) # fp[AAAA] <- a2 - .else - SET_VREG_GOTO(a2, a0, t0) # fp[AAAA] <- a2 - .endif diff --git a/runtime/interpreter/mterp/mips/op_move_exception.S b/runtime/interpreter/mterp/mips/op_move_exception.S deleted file mode 100644 index 80c554b3c1..0000000000 --- a/runtime/interpreter/mterp/mips/op_move_exception.S +++ /dev/null @@ -1,10 +0,0 @@ -%def op_move_exception(): - /* move-exception vAA */ - GET_OPA(a2) # a2 <- AA - lw a3, THREAD_EXCEPTION_OFFSET(rSELF) # get exception obj - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GET_OPCODE_TARGET(t0) - SET_VREG_OBJECT(a3, a2) # fp[AA] <- exception obj - sw zero, THREAD_EXCEPTION_OFFSET(rSELF) # clear exception - JR(t0) # jump to next instruction diff --git a/runtime/interpreter/mterp/mips/op_move_from16.S b/runtime/interpreter/mterp/mips/op_move_from16.S deleted file mode 100644 index 7306ed85ad..0000000000 --- a/runtime/interpreter/mterp/mips/op_move_from16.S +++ /dev/null @@ -1,13 +0,0 @@ -%def op_move_from16(is_object="0"): - /* for: move/from16, move-object/from16 */ - /* op vAA, vBBBB */ - FETCH(a1, 1) # a1 <- BBBB - GET_OPA(a0) # a0 <- AA - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_VREG(a2, a1) # a2 <- fp[BBBB] - GET_INST_OPCODE(t0) # extract opcode from rINST - .if $is_object - SET_VREG_OBJECT_GOTO(a2, a0, t0) # fp[AA] <- a2 - .else - SET_VREG_GOTO(a2, a0, t0) # fp[AA] <- a2 - .endif diff --git a/runtime/interpreter/mterp/mips/op_move_object.S b/runtime/interpreter/mterp/mips/op_move_object.S deleted file mode 100644 index dbb4d59710..0000000000 --- a/runtime/interpreter/mterp/mips/op_move_object.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_move_object(): -% op_move(is_object="1") diff --git a/runtime/interpreter/mterp/mips/op_move_object_16.S b/runtime/interpreter/mterp/mips/op_move_object_16.S deleted file mode 100644 index 40120379d5..0000000000 --- a/runtime/interpreter/mterp/mips/op_move_object_16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_move_object_16(): -% op_move_16(is_object="1") diff --git a/runtime/interpreter/mterp/mips/op_move_object_from16.S b/runtime/interpreter/mterp/mips/op_move_object_from16.S deleted file mode 100644 index c82698e81e..0000000000 --- a/runtime/interpreter/mterp/mips/op_move_object_from16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_move_object_from16(): -% op_move_from16(is_object="1") diff --git a/runtime/interpreter/mterp/mips/op_move_result.S b/runtime/interpreter/mterp/mips/op_move_result.S deleted file mode 100644 index 20651d9185..0000000000 --- a/runtime/interpreter/mterp/mips/op_move_result.S +++ /dev/null @@ -1,13 +0,0 @@ -%def op_move_result(is_object="0"): - /* for: move-result, move-result-object */ - /* op vAA */ - GET_OPA(a2) # a2 <- AA - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - lw a0, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType - lw a0, 0(a0) # a0 <- result.i - GET_INST_OPCODE(t0) # extract opcode from rINST - .if $is_object - SET_VREG_OBJECT_GOTO(a0, a2, t0) # fp[AA] <- a0 - .else - SET_VREG_GOTO(a0, a2, t0) # fp[AA] <- a0 - .endif diff --git a/runtime/interpreter/mterp/mips/op_move_result_object.S b/runtime/interpreter/mterp/mips/op_move_result_object.S deleted file mode 100644 index 87aea2646a..0000000000 --- a/runtime/interpreter/mterp/mips/op_move_result_object.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_move_result_object(): -% op_move_result(is_object="1") diff --git a/runtime/interpreter/mterp/mips/op_move_result_wide.S b/runtime/interpreter/mterp/mips/op_move_result_wide.S deleted file mode 100644 index 205f174120..0000000000 --- a/runtime/interpreter/mterp/mips/op_move_result_wide.S +++ /dev/null @@ -1,8 +0,0 @@ -%def op_move_result_wide(): - /* move-result-wide vAA */ - GET_OPA(a2) # a2 <- AA - lw a3, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType - LOAD64(a0, a1, a3) # a0/a1 <- retval.j - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(a0, a1, a2, t0) # fp[AA] <- a0/a1 diff --git a/runtime/interpreter/mterp/mips/op_move_wide.S b/runtime/interpreter/mterp/mips/op_move_wide.S deleted file mode 100644 index ad71022108..0000000000 --- a/runtime/interpreter/mterp/mips/op_move_wide.S +++ /dev/null @@ -1,10 +0,0 @@ -%def op_move_wide(): - /* move-wide vA, vB */ - /* NOTE: regs can overlap, e.g. "move v6, v7" or "move v7, v6" */ - GET_OPA4(a2) # a2 <- A(+) - GET_OPB(a3) # a3 <- B - EAS2(a3, rFP, a3) # a3 <- &fp[B] - LOAD64(a0, a1, a3) # a0/a1 <- fp[B] - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(a0, a1, a2, t0) # fp[A] <- a0/a1 diff --git a/runtime/interpreter/mterp/mips/op_move_wide_16.S b/runtime/interpreter/mterp/mips/op_move_wide_16.S deleted file mode 100644 index 60d41a5734..0000000000 --- a/runtime/interpreter/mterp/mips/op_move_wide_16.S +++ /dev/null @@ -1,10 +0,0 @@ -%def op_move_wide_16(): - /* move-wide/16 vAAAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6, v7" or "move v7, v6" */ - FETCH(a3, 2) # a3 <- BBBB - FETCH(a2, 1) # a2 <- AAAA - EAS2(a3, rFP, a3) # a3 <- &fp[BBBB] - LOAD64(a0, a1, a3) # a0/a1 <- fp[BBBB] - FETCH_ADVANCE_INST(3) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(a0, a1, a2, t0) # fp[AAAA] <- a0/a1 diff --git a/runtime/interpreter/mterp/mips/op_move_wide_from16.S b/runtime/interpreter/mterp/mips/op_move_wide_from16.S deleted file mode 100644 index 0a970ef611..0000000000 --- a/runtime/interpreter/mterp/mips/op_move_wide_from16.S +++ /dev/null @@ -1,10 +0,0 @@ -%def op_move_wide_from16(): - /* move-wide/from16 vAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6, v7" or "move v7, v6" */ - FETCH(a3, 1) # a3 <- BBBB - GET_OPA(a2) # a2 <- AA - EAS2(a3, rFP, a3) # a3 <- &fp[BBBB] - LOAD64(a0, a1, a3) # a0/a1 <- fp[BBBB] - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(a0, a1, a2, t0) # fp[AA] <- a0/a1 diff --git a/runtime/interpreter/mterp/mips/op_mul_double.S b/runtime/interpreter/mterp/mips/op_mul_double.S deleted file mode 100644 index 609a462a32..0000000000 --- a/runtime/interpreter/mterp/mips/op_mul_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_mul_double(): -% fbinopWide(instr="mul.d fv0, fa0, fa1") diff --git a/runtime/interpreter/mterp/mips/op_mul_double_2addr.S b/runtime/interpreter/mterp/mips/op_mul_double_2addr.S deleted file mode 100644 index ae0b13f1e9..0000000000 --- a/runtime/interpreter/mterp/mips/op_mul_double_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_mul_double_2addr(): -% fbinopWide2addr(instr="mul.d fv0, fa0, fa1") diff --git a/runtime/interpreter/mterp/mips/op_mul_float.S b/runtime/interpreter/mterp/mips/op_mul_float.S deleted file mode 100644 index e4a578e7a9..0000000000 --- a/runtime/interpreter/mterp/mips/op_mul_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_mul_float(): -% fbinop(instr="mul.s fv0, fa0, fa1") diff --git a/runtime/interpreter/mterp/mips/op_mul_float_2addr.S b/runtime/interpreter/mterp/mips/op_mul_float_2addr.S deleted file mode 100644 index 38b2a88ebd..0000000000 --- a/runtime/interpreter/mterp/mips/op_mul_float_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_mul_float_2addr(): -% fbinop2addr(instr="mul.s fv0, fa0, fa1") diff --git a/runtime/interpreter/mterp/mips/op_mul_int.S b/runtime/interpreter/mterp/mips/op_mul_int.S deleted file mode 100644 index 34e42f0783..0000000000 --- a/runtime/interpreter/mterp/mips/op_mul_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_mul_int(): -% binop(instr="mul a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_mul_int_2addr.S b/runtime/interpreter/mterp/mips/op_mul_int_2addr.S deleted file mode 100644 index 0224a6e2c1..0000000000 --- a/runtime/interpreter/mterp/mips/op_mul_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_mul_int_2addr(): -% binop2addr(instr="mul a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_mul_int_lit16.S b/runtime/interpreter/mterp/mips/op_mul_int_lit16.S deleted file mode 100644 index 935d632e11..0000000000 --- a/runtime/interpreter/mterp/mips/op_mul_int_lit16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_mul_int_lit16(): -% binopLit16(instr="mul a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_mul_int_lit8.S b/runtime/interpreter/mterp/mips/op_mul_int_lit8.S deleted file mode 100644 index 4a2bfca5c1..0000000000 --- a/runtime/interpreter/mterp/mips/op_mul_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_mul_int_lit8(): -% binopLit8(instr="mul a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_mul_long.S b/runtime/interpreter/mterp/mips/op_mul_long.S deleted file mode 100644 index ae31e1910f..0000000000 --- a/runtime/interpreter/mterp/mips/op_mul_long.S +++ /dev/null @@ -1,43 +0,0 @@ -%def op_mul_long(): - /* - * Signed 64-bit integer multiply. - * a1 a0 - * x a3 a2 - * ------------- - * a2a1 a2a0 - * a3a0 - * a3a1 (<= unused) - * --------------- - * v1 v0 - */ - /* mul-long vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - and t0, a0, 255 # a2 <- BB - srl t1, a0, 8 # a3 <- CC - EAS2(t0, rFP, t0) # t0 <- &fp[BB] - LOAD64(a0, a1, t0) # a0/a1 <- vBB/vBB+1 - - EAS2(t1, rFP, t1) # t0 <- &fp[CC] - LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 - - mul v1, a3, a0 # v1= a3a0 -#ifdef MIPS32REVGE6 - mulu v0, a2, a0 # v0= a2a0 - muhu t1, a2, a0 -#else - multu a2, a0 - mfhi t1 - mflo v0 # v0= a2a0 -#endif - mul t0, a2, a1 # t0= a2a1 - addu v1, v1, t1 # v1+= hi(a2a0) - addu v1, v1, t0 # v1= a3a0 + a2a1; - - GET_OPA(a0) # a0 <- AA - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - b .L${opcode}_finish -%def op_mul_long_sister_code(): - -.L${opcode}_finish: - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(v0, v1, a0, t0) # vAA/vAA+1 <- v0(low)/v1(high) diff --git a/runtime/interpreter/mterp/mips/op_mul_long_2addr.S b/runtime/interpreter/mterp/mips/op_mul_long_2addr.S deleted file mode 100644 index ef53254180..0000000000 --- a/runtime/interpreter/mterp/mips/op_mul_long_2addr.S +++ /dev/null @@ -1,30 +0,0 @@ -%def op_mul_long_2addr(): - /* - * See op_mul_long.S for more details - */ - /* mul-long/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - - EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] - LOAD64(a0, a1, t0) # vAA.low / high - - GET_OPB(t1) # t1 <- B - EAS2(t1, rFP, t1) # t1 <- &fp[B] - LOAD64(a2, a3, t1) # vBB.low / high - - mul v1, a3, a0 # v1= a3a0 -#ifdef MIPS32REVGE6 - mulu v0, a2, a0 # v0= a2a0 - muhu t1, a2, a0 -#else - multu a2, a0 - mfhi t1 - mflo v0 # v0= a2a0 - #endif - mul t2, a2, a1 # t2= a2a1 - addu v1, v1, t1 # v1= a3a0 + hi(a2a0) - addu v1, v1, t2 # v1= v1 + a2a1; - - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - GET_INST_OPCODE(t1) # extract opcode from rINST - SET_VREG64_GOTO(v0, v1, rOBJ, t1) # vA/vA+1 <- v0(low)/v1(high) diff --git a/runtime/interpreter/mterp/mips/op_neg_double.S b/runtime/interpreter/mterp/mips/op_neg_double.S deleted file mode 100644 index b53ccbb63a..0000000000 --- a/runtime/interpreter/mterp/mips/op_neg_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_neg_double(): -% unopWide(instr="addu a1, a1, 0x80000000") diff --git a/runtime/interpreter/mterp/mips/op_neg_float.S b/runtime/interpreter/mterp/mips/op_neg_float.S deleted file mode 100644 index 655d827d22..0000000000 --- a/runtime/interpreter/mterp/mips/op_neg_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_neg_float(): -% unop(instr="addu a0, a0, 0x80000000") diff --git a/runtime/interpreter/mterp/mips/op_neg_int.S b/runtime/interpreter/mterp/mips/op_neg_int.S deleted file mode 100644 index acc3440a33..0000000000 --- a/runtime/interpreter/mterp/mips/op_neg_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_neg_int(): -% unop(instr="negu a0, a0") diff --git a/runtime/interpreter/mterp/mips/op_neg_long.S b/runtime/interpreter/mterp/mips/op_neg_long.S deleted file mode 100644 index 9108b2b0ed..0000000000 --- a/runtime/interpreter/mterp/mips/op_neg_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_neg_long(): -% unopWide(result0="v0", result1="v1", preinstr="negu v0, a0", instr="negu v1, a1; sltu a0, zero, v0; subu v1, v1, a0") diff --git a/runtime/interpreter/mterp/mips/op_new_array.S b/runtime/interpreter/mterp/mips/op_new_array.S deleted file mode 100644 index 6ae04cc32b..0000000000 --- a/runtime/interpreter/mterp/mips/op_new_array.S +++ /dev/null @@ -1,19 +0,0 @@ -%def op_new_array(): - /* - * Allocate an array of objects, specified with the array class - * and a count. - * - * The verifier guarantees that this is an array class, so we don't - * check for it here. - */ - /* new-array vA, vB, class@CCCC */ - EXPORT_PC() - addu a0, rFP, OFF_FP_SHADOWFRAME - move a1, rPC - move a2, rINST - move a3, rSELF - JAL(MterpNewArray) - beqz v0, MterpPossibleException - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction diff --git a/runtime/interpreter/mterp/mips/op_new_instance.S b/runtime/interpreter/mterp/mips/op_new_instance.S deleted file mode 100644 index 0c98c93aaa..0000000000 --- a/runtime/interpreter/mterp/mips/op_new_instance.S +++ /dev/null @@ -1,14 +0,0 @@ -%def op_new_instance(): - /* - * Create a new instance of a class. - */ - /* new-instance vAA, class@BBBB */ - EXPORT_PC() - addu a0, rFP, OFF_FP_SHADOWFRAME - move a1, rSELF - move a2, rINST - JAL(MterpNewInstance) - beqz v0, MterpPossibleException - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction diff --git a/runtime/interpreter/mterp/mips/op_nop.S b/runtime/interpreter/mterp/mips/op_nop.S deleted file mode 100644 index 10f607478f..0000000000 --- a/runtime/interpreter/mterp/mips/op_nop.S +++ /dev/null @@ -1,4 +0,0 @@ -%def op_nop(): - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction diff --git a/runtime/interpreter/mterp/mips/op_not_int.S b/runtime/interpreter/mterp/mips/op_not_int.S deleted file mode 100644 index 7dc7aebc5c..0000000000 --- a/runtime/interpreter/mterp/mips/op_not_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_not_int(): -% unop(instr="not a0, a0") diff --git a/runtime/interpreter/mterp/mips/op_not_long.S b/runtime/interpreter/mterp/mips/op_not_long.S deleted file mode 100644 index 0bca4bde59..0000000000 --- a/runtime/interpreter/mterp/mips/op_not_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_not_long(): -% unopWide(preinstr="not a0, a0", instr="not a1, a1") diff --git a/runtime/interpreter/mterp/mips/op_or_int.S b/runtime/interpreter/mterp/mips/op_or_int.S deleted file mode 100644 index df60be5896..0000000000 --- a/runtime/interpreter/mterp/mips/op_or_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_or_int(): -% binop(instr="or a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_or_int_2addr.S b/runtime/interpreter/mterp/mips/op_or_int_2addr.S deleted file mode 100644 index c202e6799b..0000000000 --- a/runtime/interpreter/mterp/mips/op_or_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_or_int_2addr(): -% binop2addr(instr="or a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_or_int_lit16.S b/runtime/interpreter/mterp/mips/op_or_int_lit16.S deleted file mode 100644 index 09961e8845..0000000000 --- a/runtime/interpreter/mterp/mips/op_or_int_lit16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_or_int_lit16(): -% binopLit16(instr="or a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_or_int_lit8.S b/runtime/interpreter/mterp/mips/op_or_int_lit8.S deleted file mode 100644 index 1bd6809d90..0000000000 --- a/runtime/interpreter/mterp/mips/op_or_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_or_int_lit8(): -% binopLit8(instr="or a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_or_long.S b/runtime/interpreter/mterp/mips/op_or_long.S deleted file mode 100644 index 5f53085e0d..0000000000 --- a/runtime/interpreter/mterp/mips/op_or_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_or_long(): -% binopWide(preinstr="or a0, a0, a2", instr="or a1, a1, a3") diff --git a/runtime/interpreter/mterp/mips/op_or_long_2addr.S b/runtime/interpreter/mterp/mips/op_or_long_2addr.S deleted file mode 100644 index f9b2f9c13e..0000000000 --- a/runtime/interpreter/mterp/mips/op_or_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_or_long_2addr(): -% binopWide2addr(preinstr="or a0, a0, a2", instr="or a1, a1, a3") diff --git a/runtime/interpreter/mterp/mips/op_packed_switch.S b/runtime/interpreter/mterp/mips/op_packed_switch.S deleted file mode 100644 index e18a652f65..0000000000 --- a/runtime/interpreter/mterp/mips/op_packed_switch.S +++ /dev/null @@ -1,20 +0,0 @@ -%def op_packed_switch(func="MterpDoPackedSwitch"): - /* - * Handle a packed-switch or sparse-switch instruction. In both cases - * we decode it and hand it off to a helper function. - * - * We don't really expect backward branches in a switch statement, but - * they're perfectly legal, so we check for them here. - * - * for: packed-switch, sparse-switch - */ - /* op vAA, +BBBB */ - FETCH(a0, 1) # a0 <- bbbb (lo) - FETCH(a1, 2) # a1 <- BBBB (hi) - GET_OPA(a3) # a3 <- AA - INSERT_HIGH_HALF(a0, a1) # a0 <- BBBBbbbb - GET_VREG(a1, a3) # a1 <- vAA - EAS1(a0, rPC, a0) # a0 <- PC + BBBBbbbb*2 - JAL($func) # a0 <- code-unit branch offset - move rINST, v0 - b MterpCommonTakenBranchNoFlags diff --git a/runtime/interpreter/mterp/mips/op_rem_double.S b/runtime/interpreter/mterp/mips/op_rem_double.S deleted file mode 100644 index 99857a383f..0000000000 --- a/runtime/interpreter/mterp/mips/op_rem_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_rem_double(): -% fbinopWide(instr="JAL(fmod)") diff --git a/runtime/interpreter/mterp/mips/op_rem_double_2addr.S b/runtime/interpreter/mterp/mips/op_rem_double_2addr.S deleted file mode 100644 index cf2d3a7456..0000000000 --- a/runtime/interpreter/mterp/mips/op_rem_double_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_rem_double_2addr(): -% fbinopWide2addr(instr="JAL(fmod)") diff --git a/runtime/interpreter/mterp/mips/op_rem_float.S b/runtime/interpreter/mterp/mips/op_rem_float.S deleted file mode 100644 index 2295ae58ed..0000000000 --- a/runtime/interpreter/mterp/mips/op_rem_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_rem_float(): -% fbinop(instr="JAL(fmodf)") diff --git a/runtime/interpreter/mterp/mips/op_rem_float_2addr.S b/runtime/interpreter/mterp/mips/op_rem_float_2addr.S deleted file mode 100644 index 9f6abee390..0000000000 --- a/runtime/interpreter/mterp/mips/op_rem_float_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_rem_float_2addr(): -% fbinop2addr(instr="JAL(fmodf)") diff --git a/runtime/interpreter/mterp/mips/op_rem_int.S b/runtime/interpreter/mterp/mips/op_rem_int.S deleted file mode 100644 index 2f67adc1c7..0000000000 --- a/runtime/interpreter/mterp/mips/op_rem_int.S +++ /dev/null @@ -1,6 +0,0 @@ -%def op_rem_int(): -#ifdef MIPS32REVGE6 -% binop(instr="mod a0, a0, a1", chkzero="1") -#else -% binop(preinstr="div zero, a0, a1", instr="mfhi a0", chkzero="1") -#endif diff --git a/runtime/interpreter/mterp/mips/op_rem_int_2addr.S b/runtime/interpreter/mterp/mips/op_rem_int_2addr.S deleted file mode 100644 index 78766a7b55..0000000000 --- a/runtime/interpreter/mterp/mips/op_rem_int_2addr.S +++ /dev/null @@ -1,6 +0,0 @@ -%def op_rem_int_2addr(): -#ifdef MIPS32REVGE6 -% binop2addr(instr="mod a0, a0, a1", chkzero="1") -#else -% binop2addr(preinstr="div zero, a0, a1", instr="mfhi a0", chkzero="1") -#endif diff --git a/runtime/interpreter/mterp/mips/op_rem_int_lit16.S b/runtime/interpreter/mterp/mips/op_rem_int_lit16.S deleted file mode 100644 index ce136cbf37..0000000000 --- a/runtime/interpreter/mterp/mips/op_rem_int_lit16.S +++ /dev/null @@ -1,6 +0,0 @@ -%def op_rem_int_lit16(): -#ifdef MIPS32REVGE6 -% binopLit16(instr="mod a0, a0, a1", chkzero="1") -#else -% binopLit16(preinstr="div zero, a0, a1", instr="mfhi a0", chkzero="1") -#endif diff --git a/runtime/interpreter/mterp/mips/op_rem_int_lit8.S b/runtime/interpreter/mterp/mips/op_rem_int_lit8.S deleted file mode 100644 index 0a5084449d..0000000000 --- a/runtime/interpreter/mterp/mips/op_rem_int_lit8.S +++ /dev/null @@ -1,6 +0,0 @@ -%def op_rem_int_lit8(): -#ifdef MIPS32REVGE6 -% binopLit8(instr="mod a0, a0, a1", chkzero="1") -#else -% binopLit8(preinstr="div zero, a0, a1", instr="mfhi a0", chkzero="1") -#endif diff --git a/runtime/interpreter/mterp/mips/op_rem_long.S b/runtime/interpreter/mterp/mips/op_rem_long.S deleted file mode 100644 index 2403deccc2..0000000000 --- a/runtime/interpreter/mterp/mips/op_rem_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_rem_long(): -% binopWide(result0="v0", result1="v1", instr="JAL(__moddi3)", chkzero="1") diff --git a/runtime/interpreter/mterp/mips/op_rem_long_2addr.S b/runtime/interpreter/mterp/mips/op_rem_long_2addr.S deleted file mode 100644 index 6cf3c09cea..0000000000 --- a/runtime/interpreter/mterp/mips/op_rem_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_rem_long_2addr(): -% binopWide2addr(result0="v0", result1="v1", instr="JAL(__moddi3)", chkzero="1") diff --git a/runtime/interpreter/mterp/mips/op_return.S b/runtime/interpreter/mterp/mips/op_return.S deleted file mode 100644 index 4e422d2999..0000000000 --- a/runtime/interpreter/mterp/mips/op_return.S +++ /dev/null @@ -1,19 +0,0 @@ -%def op_return(): - /* - * Return a 32-bit value. - * - * for: return, return-object - */ - /* op vAA */ - .extern MterpThreadFenceForConstructor - JAL(MterpThreadFenceForConstructor) - lw ra, THREAD_FLAGS_OFFSET(rSELF) - move a0, rSELF - and ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - beqz ra, 1f - JAL(MterpSuspendCheck) # (self) -1: - GET_OPA(a2) # a2 <- AA - GET_VREG(v0, a2) # v0 <- vAA - move v1, zero - b MterpReturn diff --git a/runtime/interpreter/mterp/mips/op_return_object.S b/runtime/interpreter/mterp/mips/op_return_object.S deleted file mode 100644 index 2eeec0b948..0000000000 --- a/runtime/interpreter/mterp/mips/op_return_object.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_return_object(): -% op_return() diff --git a/runtime/interpreter/mterp/mips/op_return_void.S b/runtime/interpreter/mterp/mips/op_return_void.S deleted file mode 100644 index 14e532b6f9..0000000000 --- a/runtime/interpreter/mterp/mips/op_return_void.S +++ /dev/null @@ -1,12 +0,0 @@ -%def op_return_void(): - .extern MterpThreadFenceForConstructor - JAL(MterpThreadFenceForConstructor) - lw ra, THREAD_FLAGS_OFFSET(rSELF) - move a0, rSELF - and ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - beqz ra, 1f - JAL(MterpSuspendCheck) # (self) -1: - move v0, zero - move v1, zero - b MterpReturn diff --git a/runtime/interpreter/mterp/mips/op_return_void_no_barrier.S b/runtime/interpreter/mterp/mips/op_return_void_no_barrier.S deleted file mode 100644 index a74f0855d1..0000000000 --- a/runtime/interpreter/mterp/mips/op_return_void_no_barrier.S +++ /dev/null @@ -1,10 +0,0 @@ -%def op_return_void_no_barrier(): - lw ra, THREAD_FLAGS_OFFSET(rSELF) - move a0, rSELF - and ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - beqz ra, 1f - JAL(MterpSuspendCheck) # (self) -1: - move v0, zero - move v1, zero - b MterpReturn diff --git a/runtime/interpreter/mterp/mips/op_return_wide.S b/runtime/interpreter/mterp/mips/op_return_wide.S deleted file mode 100644 index fb065a56d6..0000000000 --- a/runtime/interpreter/mterp/mips/op_return_wide.S +++ /dev/null @@ -1,17 +0,0 @@ -%def op_return_wide(): - /* - * Return a 64-bit value. - */ - /* return-wide vAA */ - .extern MterpThreadFenceForConstructor - JAL(MterpThreadFenceForConstructor) - lw ra, THREAD_FLAGS_OFFSET(rSELF) - move a0, rSELF - and ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - beqz ra, 1f - JAL(MterpSuspendCheck) # (self) -1: - GET_OPA(a2) # a2 <- AA - EAS2(a2, rFP, a2) # a2 <- &fp[AA] - LOAD64(v0, v1, a2) # v0/v1 <- vAA/vAA+1 - b MterpReturn diff --git a/runtime/interpreter/mterp/mips/op_rsub_int.S b/runtime/interpreter/mterp/mips/op_rsub_int.S deleted file mode 100644 index 21ead06dbf..0000000000 --- a/runtime/interpreter/mterp/mips/op_rsub_int.S +++ /dev/null @@ -1,3 +0,0 @@ -%def op_rsub_int(): -/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ -% binopLit16(instr="subu a0, a1, a0") diff --git a/runtime/interpreter/mterp/mips/op_rsub_int_lit8.S b/runtime/interpreter/mterp/mips/op_rsub_int_lit8.S deleted file mode 100644 index b9b214da94..0000000000 --- a/runtime/interpreter/mterp/mips/op_rsub_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_rsub_int_lit8(): -% binopLit8(instr="subu a0, a1, a0") diff --git a/runtime/interpreter/mterp/mips/op_sget.S b/runtime/interpreter/mterp/mips/op_sget.S deleted file mode 100644 index 8a6a66ab60..0000000000 --- a/runtime/interpreter/mterp/mips/op_sget.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sget(is_object="0", helper="MterpSGetU32"): -% field(helper=helper) diff --git a/runtime/interpreter/mterp/mips/op_sget_boolean.S b/runtime/interpreter/mterp/mips/op_sget_boolean.S deleted file mode 100644 index d9c12c9b28..0000000000 --- a/runtime/interpreter/mterp/mips/op_sget_boolean.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sget_boolean(): -% op_sget(helper="MterpSGetU8") diff --git a/runtime/interpreter/mterp/mips/op_sget_byte.S b/runtime/interpreter/mterp/mips/op_sget_byte.S deleted file mode 100644 index 37c6879cd4..0000000000 --- a/runtime/interpreter/mterp/mips/op_sget_byte.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sget_byte(): -% op_sget(helper="MterpSGetI8") diff --git a/runtime/interpreter/mterp/mips/op_sget_char.S b/runtime/interpreter/mterp/mips/op_sget_char.S deleted file mode 100644 index 003bcd1683..0000000000 --- a/runtime/interpreter/mterp/mips/op_sget_char.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sget_char(): -% op_sget(helper="MterpSGetU16") diff --git a/runtime/interpreter/mterp/mips/op_sget_object.S b/runtime/interpreter/mterp/mips/op_sget_object.S deleted file mode 100644 index 7cf3597f44..0000000000 --- a/runtime/interpreter/mterp/mips/op_sget_object.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sget_object(): -% op_sget(is_object="1", helper="MterpSGetObj") diff --git a/runtime/interpreter/mterp/mips/op_sget_short.S b/runtime/interpreter/mterp/mips/op_sget_short.S deleted file mode 100644 index afacb578d9..0000000000 --- a/runtime/interpreter/mterp/mips/op_sget_short.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sget_short(): -% op_sget(helper="MterpSGetI16") diff --git a/runtime/interpreter/mterp/mips/op_sget_wide.S b/runtime/interpreter/mterp/mips/op_sget_wide.S deleted file mode 100644 index fff2be6945..0000000000 --- a/runtime/interpreter/mterp/mips/op_sget_wide.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sget_wide(): -% op_sget(helper="MterpSGetU64") diff --git a/runtime/interpreter/mterp/mips/op_shl_int.S b/runtime/interpreter/mterp/mips/op_shl_int.S deleted file mode 100644 index efd213c09a..0000000000 --- a/runtime/interpreter/mterp/mips/op_shl_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shl_int(): -% binop(instr="sll a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_shl_int_2addr.S b/runtime/interpreter/mterp/mips/op_shl_int_2addr.S deleted file mode 100644 index 0901e6b65a..0000000000 --- a/runtime/interpreter/mterp/mips/op_shl_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shl_int_2addr(): -% binop2addr(instr="sll a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_shl_int_lit8.S b/runtime/interpreter/mterp/mips/op_shl_int_lit8.S deleted file mode 100644 index 2263ec70c2..0000000000 --- a/runtime/interpreter/mterp/mips/op_shl_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shl_int_lit8(): -% binopLit8(instr="sll a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_shl_long.S b/runtime/interpreter/mterp/mips/op_shl_long.S deleted file mode 100644 index 8bb4216425..0000000000 --- a/runtime/interpreter/mterp/mips/op_shl_long.S +++ /dev/null @@ -1,32 +0,0 @@ -%def op_shl_long(): - /* - * Long integer shift. This is different from the generic 32/64-bit - * binary operations because vAA/vBB are 64-bit but vCC (the shift - * distance) is 32-bit. Also, Dalvik requires us to mask off the low - * 6 bits of the shift distance. - */ - /* shl-long vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(t2) # t2 <- AA - and a3, a0, 255 # a3 <- BB - srl a0, a0, 8 # a0 <- CC - EAS2(a3, rFP, a3) # a3 <- &fp[BB] - GET_VREG(a2, a0) # a2 <- vCC - LOAD64(a0, a1, a3) # a0/a1 <- vBB/vBB+1 - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - - andi v1, a2, 0x20 # shift< shift & 0x20 - sll v0, a0, a2 # rlo<- alo << (shift&31) - bnez v1, .L${opcode}_finish - not v1, a2 # rhi<- 31-shift (shift is 5b) - srl a0, 1 - srl a0, v1 # alo<- alo >> (32-(shift&31)) - sll v1, a1, a2 # rhi<- ahi << (shift&31) - or v1, a0 # rhi<- rhi | alo - SET_VREG64_GOTO(v0, v1, t2, t0) # vAA/vAA+1 <- v0/v1 -%def op_shl_long_sister_code(): - -.L${opcode}_finish: - SET_VREG64_GOTO(zero, v0, t2, t0) # vAA/vAA+1 <- rlo/rhi diff --git a/runtime/interpreter/mterp/mips/op_shl_long_2addr.S b/runtime/interpreter/mterp/mips/op_shl_long_2addr.S deleted file mode 100644 index 12015f5b15..0000000000 --- a/runtime/interpreter/mterp/mips/op_shl_long_2addr.S +++ /dev/null @@ -1,28 +0,0 @@ -%def op_shl_long_2addr(): - /* - * Long integer shift, 2addr version. vA is 64-bit value/result, vB is - * 32-bit shift distance. - */ - /* shl-long/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a2, a3) # a2 <- vB - EAS2(t2, rFP, rOBJ) # t2 <- &fp[A] - LOAD64(a0, a1, t2) # a0/a1 <- vA/vA+1 - - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - - andi v1, a2, 0x20 # shift< shift & 0x20 - sll v0, a0, a2 # rlo<- alo << (shift&31) - bnez v1, .L${opcode}_finish - not v1, a2 # rhi<- 31-shift (shift is 5b) - srl a0, 1 - srl a0, v1 # alo<- alo >> (32-(shift&31)) - sll v1, a1, a2 # rhi<- ahi << (shift&31) - or v1, a0 # rhi<- rhi | alo - SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vA/vA+1 <- v0/v1 -%def op_shl_long_2addr_sister_code(): - -.L${opcode}_finish: - SET_VREG64_GOTO(zero, v0, rOBJ, t0) # vA/vA+1 <- rlo/rhi diff --git a/runtime/interpreter/mterp/mips/op_shr_int.S b/runtime/interpreter/mterp/mips/op_shr_int.S deleted file mode 100644 index 8d55e7afa9..0000000000 --- a/runtime/interpreter/mterp/mips/op_shr_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shr_int(): -% binop(instr="sra a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_shr_int_2addr.S b/runtime/interpreter/mterp/mips/op_shr_int_2addr.S deleted file mode 100644 index e102baa99f..0000000000 --- a/runtime/interpreter/mterp/mips/op_shr_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shr_int_2addr(): -% binop2addr(instr="sra a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_shr_int_lit8.S b/runtime/interpreter/mterp/mips/op_shr_int_lit8.S deleted file mode 100644 index 437c5c49a6..0000000000 --- a/runtime/interpreter/mterp/mips/op_shr_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shr_int_lit8(): -% binopLit8(instr="sra a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_shr_long.S b/runtime/interpreter/mterp/mips/op_shr_long.S deleted file mode 100644 index adffa615a1..0000000000 --- a/runtime/interpreter/mterp/mips/op_shr_long.S +++ /dev/null @@ -1,32 +0,0 @@ -%def op_shr_long(): - /* - * Long integer shift. This is different from the generic 32/64-bit - * binary operations because vAA/vBB are 64-bit but vCC (the shift - * distance) is 32-bit. Also, Dalvik requires us to mask off the low - * 6 bits of the shift distance. - */ - /* shr-long vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(t3) # t3 <- AA - and a3, a0, 255 # a3 <- BB - srl a0, a0, 8 # a0 <- CC - EAS2(a3, rFP, a3) # a3 <- &fp[BB] - GET_VREG(a2, a0) # a2 <- vCC - LOAD64(a0, a1, a3) # a0/a1 <- vBB/vBB+1 - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - - andi v0, a2, 0x20 # shift & 0x20 - sra v1, a1, a2 # rhi<- ahi >> (shift&31) - bnez v0, .L${opcode}_finish - srl v0, a0, a2 # rlo<- alo >> (shift&31) - not a0, a2 # alo<- 31-shift (shift is 5b) - sll a1, 1 - sll a1, a0 # ahi<- ahi << (32-(shift&31)) - or v0, a1 # rlo<- rlo | ahi - SET_VREG64_GOTO(v0, v1, t3, t0) # vAA/VAA+1 <- v0/v1 -%def op_shr_long_sister_code(): - -.L${opcode}_finish: - sra a3, a1, 31 # a3<- sign(ah) - SET_VREG64_GOTO(v1, a3, t3, t0) # vAA/VAA+1 <- rlo/rhi diff --git a/runtime/interpreter/mterp/mips/op_shr_long_2addr.S b/runtime/interpreter/mterp/mips/op_shr_long_2addr.S deleted file mode 100644 index d8acb790b6..0000000000 --- a/runtime/interpreter/mterp/mips/op_shr_long_2addr.S +++ /dev/null @@ -1,28 +0,0 @@ -%def op_shr_long_2addr(): - /* - * Long integer shift, 2addr version. vA is 64-bit value/result, vB is - * 32-bit shift distance. - */ - /* shr-long/2addr vA, vB */ - GET_OPA4(t2) # t2 <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a2, a3) # a2 <- vB - EAS2(t0, rFP, t2) # t0 <- &fp[A] - LOAD64(a0, a1, t0) # a0/a1 <- vA/vA+1 - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - - andi v0, a2, 0x20 # shift & 0x20 - sra v1, a1, a2 # rhi<- ahi >> (shift&31) - bnez v0, .L${opcode}_finish - srl v0, a0, a2 # rlo<- alo >> (shift&31) - not a0, a2 # alo<- 31-shift (shift is 5b) - sll a1, 1 - sll a1, a0 # ahi<- ahi << (32-(shift&31)) - or v0, a1 # rlo<- rlo | ahi - SET_VREG64_GOTO(v0, v1, t2, t0) # vA/vA+1 <- v0/v1 -%def op_shr_long_2addr_sister_code(): - -.L${opcode}_finish: - sra a3, a1, 31 # a3<- sign(ah) - SET_VREG64_GOTO(v1, a3, t2, t0) # vA/vA+1 <- rlo/rhi diff --git a/runtime/interpreter/mterp/mips/op_sparse_switch.S b/runtime/interpreter/mterp/mips/op_sparse_switch.S deleted file mode 100644 index b74d7da816..0000000000 --- a/runtime/interpreter/mterp/mips/op_sparse_switch.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sparse_switch(): -% op_packed_switch(func="MterpDoSparseSwitch") diff --git a/runtime/interpreter/mterp/mips/op_sput.S b/runtime/interpreter/mterp/mips/op_sput.S deleted file mode 100644 index cbd6ee96d3..0000000000 --- a/runtime/interpreter/mterp/mips/op_sput.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sput(is_object="0", helper="MterpSPutU32"): -% field(helper=helper) diff --git a/runtime/interpreter/mterp/mips/op_sput_boolean.S b/runtime/interpreter/mterp/mips/op_sput_boolean.S deleted file mode 100644 index 36fba8448b..0000000000 --- a/runtime/interpreter/mterp/mips/op_sput_boolean.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sput_boolean(): -% op_sput(helper="MterpSPutU8") diff --git a/runtime/interpreter/mterp/mips/op_sput_byte.S b/runtime/interpreter/mterp/mips/op_sput_byte.S deleted file mode 100644 index 84ad4a0ff8..0000000000 --- a/runtime/interpreter/mterp/mips/op_sput_byte.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sput_byte(): -% op_sput(helper="MterpSPutI8") diff --git a/runtime/interpreter/mterp/mips/op_sput_char.S b/runtime/interpreter/mterp/mips/op_sput_char.S deleted file mode 100644 index 9b8eeba578..0000000000 --- a/runtime/interpreter/mterp/mips/op_sput_char.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sput_char(): -% op_sput(helper="MterpSPutU16") diff --git a/runtime/interpreter/mterp/mips/op_sput_object.S b/runtime/interpreter/mterp/mips/op_sput_object.S deleted file mode 100644 index 081360c40f..0000000000 --- a/runtime/interpreter/mterp/mips/op_sput_object.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sput_object(): -% op_sput(is_object="1", helper="MterpSPutObj") diff --git a/runtime/interpreter/mterp/mips/op_sput_short.S b/runtime/interpreter/mterp/mips/op_sput_short.S deleted file mode 100644 index ee16513486..0000000000 --- a/runtime/interpreter/mterp/mips/op_sput_short.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sput_short(): -% op_sput(helper="MterpSPutI16") diff --git a/runtime/interpreter/mterp/mips/op_sput_wide.S b/runtime/interpreter/mterp/mips/op_sput_wide.S deleted file mode 100644 index 44c1a188ed..0000000000 --- a/runtime/interpreter/mterp/mips/op_sput_wide.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sput_wide(): -% op_sput(helper="MterpSPutU64") diff --git a/runtime/interpreter/mterp/mips/op_sub_double.S b/runtime/interpreter/mterp/mips/op_sub_double.S deleted file mode 100644 index ad8f12cfb3..0000000000 --- a/runtime/interpreter/mterp/mips/op_sub_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_double(): -% fbinopWide(instr="sub.d fv0, fa0, fa1") diff --git a/runtime/interpreter/mterp/mips/op_sub_double_2addr.S b/runtime/interpreter/mterp/mips/op_sub_double_2addr.S deleted file mode 100644 index ed5598d2a4..0000000000 --- a/runtime/interpreter/mterp/mips/op_sub_double_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_double_2addr(): -% fbinopWide2addr(instr="sub.d fv0, fa0, fa1") diff --git a/runtime/interpreter/mterp/mips/op_sub_float.S b/runtime/interpreter/mterp/mips/op_sub_float.S deleted file mode 100644 index 402fa2cfd7..0000000000 --- a/runtime/interpreter/mterp/mips/op_sub_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_float(): -% fbinop(instr="sub.s fv0, fa0, fa1") diff --git a/runtime/interpreter/mterp/mips/op_sub_float_2addr.S b/runtime/interpreter/mterp/mips/op_sub_float_2addr.S deleted file mode 100644 index 1d38188048..0000000000 --- a/runtime/interpreter/mterp/mips/op_sub_float_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_float_2addr(): -% fbinop2addr(instr="sub.s fv0, fa0, fa1") diff --git a/runtime/interpreter/mterp/mips/op_sub_int.S b/runtime/interpreter/mterp/mips/op_sub_int.S deleted file mode 100644 index 57f618d65a..0000000000 --- a/runtime/interpreter/mterp/mips/op_sub_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_int(): -% binop(instr="subu a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_sub_int_2addr.S b/runtime/interpreter/mterp/mips/op_sub_int_2addr.S deleted file mode 100644 index 445ffca50f..0000000000 --- a/runtime/interpreter/mterp/mips/op_sub_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_int_2addr(): -% binop2addr(instr="subu a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_sub_long.S b/runtime/interpreter/mterp/mips/op_sub_long.S deleted file mode 100644 index a54460b3b2..0000000000 --- a/runtime/interpreter/mterp/mips/op_sub_long.S +++ /dev/null @@ -1,9 +0,0 @@ -%def op_sub_long(): -/* - * For little endian the code sequence looks as follows: - * subu v0,a0,a2 - * subu v1,a1,a3 - * sltu a0,a0,v0 - * subu v1,v1,a0 - */ -% binopWide(result0="v0", result1="v1", preinstr="subu v0, a0, a2", instr="subu v1, a1, a3; sltu a0, a0, v0; subu v1, v1, a0") diff --git a/runtime/interpreter/mterp/mips/op_sub_long_2addr.S b/runtime/interpreter/mterp/mips/op_sub_long_2addr.S deleted file mode 100644 index b3dd6b2cd2..0000000000 --- a/runtime/interpreter/mterp/mips/op_sub_long_2addr.S +++ /dev/null @@ -1,5 +0,0 @@ -%def op_sub_long_2addr(): -/* - * See op_sub_long.S for more details - */ -% binopWide2addr(result0="v0", result1="v1", preinstr="subu v0, a0, a2", instr="subu v1, a1, a3; sltu a0, a0, v0; subu v1, v1, a0") diff --git a/runtime/interpreter/mterp/mips/op_throw.S b/runtime/interpreter/mterp/mips/op_throw.S deleted file mode 100644 index 84b9e5ecfc..0000000000 --- a/runtime/interpreter/mterp/mips/op_throw.S +++ /dev/null @@ -1,12 +0,0 @@ -%def op_throw(): - /* - * Throw an exception object in the current thread. - */ - /* throw vAA */ - EXPORT_PC() # exception handler can throw - GET_OPA(a2) # a2 <- AA - GET_VREG(a1, a2) # a1 <- vAA (exception object) - # null object? - beqz a1, common_errNullObject # yes, throw an NPE instead - sw a1, THREAD_EXCEPTION_OFFSET(rSELF) # thread->exception <- obj - b MterpException diff --git a/runtime/interpreter/mterp/mips/op_unused_3e.S b/runtime/interpreter/mterp/mips/op_unused_3e.S deleted file mode 100644 index d889f1a5fb..0000000000 --- a/runtime/interpreter/mterp/mips/op_unused_3e.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_3e(): -% unused() diff --git a/runtime/interpreter/mterp/mips/op_unused_3f.S b/runtime/interpreter/mterp/mips/op_unused_3f.S deleted file mode 100644 index b3ebcfaeaa..0000000000 --- a/runtime/interpreter/mterp/mips/op_unused_3f.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_3f(): -% unused() diff --git a/runtime/interpreter/mterp/mips/op_unused_40.S b/runtime/interpreter/mterp/mips/op_unused_40.S deleted file mode 100644 index 7920fb350f..0000000000 --- a/runtime/interpreter/mterp/mips/op_unused_40.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_40(): -% unused() diff --git a/runtime/interpreter/mterp/mips/op_unused_41.S b/runtime/interpreter/mterp/mips/op_unused_41.S deleted file mode 100644 index 5ed03b8506..0000000000 --- a/runtime/interpreter/mterp/mips/op_unused_41.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_41(): -% unused() diff --git a/runtime/interpreter/mterp/mips/op_unused_42.S b/runtime/interpreter/mterp/mips/op_unused_42.S deleted file mode 100644 index ac32521add..0000000000 --- a/runtime/interpreter/mterp/mips/op_unused_42.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_42(): -% unused() diff --git a/runtime/interpreter/mterp/mips/op_unused_43.S b/runtime/interpreter/mterp/mips/op_unused_43.S deleted file mode 100644 index 33e2aa10f8..0000000000 --- a/runtime/interpreter/mterp/mips/op_unused_43.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_43(): -% unused() diff --git a/runtime/interpreter/mterp/mips/op_unused_73.S b/runtime/interpreter/mterp/mips/op_unused_73.S deleted file mode 100644 index e3267a30a1..0000000000 --- a/runtime/interpreter/mterp/mips/op_unused_73.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_73(): -% unused() diff --git a/runtime/interpreter/mterp/mips/op_unused_79.S b/runtime/interpreter/mterp/mips/op_unused_79.S deleted file mode 100644 index 3c6dafc789..0000000000 --- a/runtime/interpreter/mterp/mips/op_unused_79.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_79(): -% unused() diff --git a/runtime/interpreter/mterp/mips/op_unused_7a.S b/runtime/interpreter/mterp/mips/op_unused_7a.S deleted file mode 100644 index 9c03cd5535..0000000000 --- a/runtime/interpreter/mterp/mips/op_unused_7a.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_7a(): -% unused() diff --git a/runtime/interpreter/mterp/mips/op_unused_f3.S b/runtime/interpreter/mterp/mips/op_unused_f3.S deleted file mode 100644 index ab10b78be2..0000000000 --- a/runtime/interpreter/mterp/mips/op_unused_f3.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_f3(): -% unused() diff --git a/runtime/interpreter/mterp/mips/op_unused_f4.S b/runtime/interpreter/mterp/mips/op_unused_f4.S deleted file mode 100644 index 09229d6d99..0000000000 --- a/runtime/interpreter/mterp/mips/op_unused_f4.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_f4(): -% unused() diff --git a/runtime/interpreter/mterp/mips/op_unused_f5.S b/runtime/interpreter/mterp/mips/op_unused_f5.S deleted file mode 100644 index 0d6149b5fd..0000000000 --- a/runtime/interpreter/mterp/mips/op_unused_f5.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_f5(): -% unused() diff --git a/runtime/interpreter/mterp/mips/op_unused_f6.S b/runtime/interpreter/mterp/mips/op_unused_f6.S deleted file mode 100644 index 117b03de6d..0000000000 --- a/runtime/interpreter/mterp/mips/op_unused_f6.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_f6(): -% unused() diff --git a/runtime/interpreter/mterp/mips/op_unused_f7.S b/runtime/interpreter/mterp/mips/op_unused_f7.S deleted file mode 100644 index 4e3a0f3c9a..0000000000 --- a/runtime/interpreter/mterp/mips/op_unused_f7.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_f7(): -% unused() diff --git a/runtime/interpreter/mterp/mips/op_unused_f8.S b/runtime/interpreter/mterp/mips/op_unused_f8.S deleted file mode 100644 index d1220752d7..0000000000 --- a/runtime/interpreter/mterp/mips/op_unused_f8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_f8(): -% unused() diff --git a/runtime/interpreter/mterp/mips/op_unused_f9.S b/runtime/interpreter/mterp/mips/op_unused_f9.S deleted file mode 100644 index 7d09a0ebcf..0000000000 --- a/runtime/interpreter/mterp/mips/op_unused_f9.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_f9(): -% unused() diff --git a/runtime/interpreter/mterp/mips/op_unused_fc.S b/runtime/interpreter/mterp/mips/op_unused_fc.S deleted file mode 100644 index 06978191eb..0000000000 --- a/runtime/interpreter/mterp/mips/op_unused_fc.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_fc(): -% unused() diff --git a/runtime/interpreter/mterp/mips/op_unused_fd.S b/runtime/interpreter/mterp/mips/op_unused_fd.S deleted file mode 100644 index 4bc2b4bdb6..0000000000 --- a/runtime/interpreter/mterp/mips/op_unused_fd.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_fd(): -% unused() diff --git a/runtime/interpreter/mterp/mips/op_ushr_int.S b/runtime/interpreter/mterp/mips/op_ushr_int.S deleted file mode 100644 index 98d2dfbc9c..0000000000 --- a/runtime/interpreter/mterp/mips/op_ushr_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_ushr_int(): -% binop(instr="srl a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_ushr_int_2addr.S b/runtime/interpreter/mterp/mips/op_ushr_int_2addr.S deleted file mode 100644 index 4b09cacabc..0000000000 --- a/runtime/interpreter/mterp/mips/op_ushr_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_ushr_int_2addr(): -% binop2addr(instr="srl a0, a0, a1 ") diff --git a/runtime/interpreter/mterp/mips/op_ushr_int_lit8.S b/runtime/interpreter/mterp/mips/op_ushr_int_lit8.S deleted file mode 100644 index 531c30a000..0000000000 --- a/runtime/interpreter/mterp/mips/op_ushr_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_ushr_int_lit8(): -% binopLit8(instr="srl a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_ushr_long.S b/runtime/interpreter/mterp/mips/op_ushr_long.S deleted file mode 100644 index b09e7b3c6a..0000000000 --- a/runtime/interpreter/mterp/mips/op_ushr_long.S +++ /dev/null @@ -1,32 +0,0 @@ -%def op_ushr_long(): - /* - * Long integer shift. This is different from the generic 32/64-bit - * binary operations because vAA/vBB are 64-bit but vCC (the shift - * distance) is 32-bit. Also, Dalvik requires us to mask off the low - * 6 bits of the shift distance. - */ - /* ushr-long vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - and a3, a0, 255 # a3 <- BB - srl a0, a0, 8 # a0 <- CC - EAS2(a3, rFP, a3) # a3 <- &fp[BB] - GET_VREG(a2, a0) # a2 <- vCC - LOAD64(a0, a1, a3) # a0/a1 <- vBB/vBB+1 - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - - andi v0, a2, 0x20 # shift & 0x20 - srl v1, a1, a2 # rhi<- ahi >> (shift&31) - bnez v0, .L${opcode}_finish - srl v0, a0, a2 # rlo<- alo >> (shift&31) - not a0, a2 # alo<- 31-n (shift is 5b) - sll a1, 1 - sll a1, a0 # ahi<- ahi << (32-(shift&31)) - or v0, a1 # rlo<- rlo | ahi - SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vAA/vAA+1 <- v0/v1 -%def op_ushr_long_sister_code(): - -.L${opcode}_finish: - SET_VREG64_GOTO(v1, zero, rOBJ, t0) # vAA/vAA+1 <- rlo/rhi diff --git a/runtime/interpreter/mterp/mips/op_ushr_long_2addr.S b/runtime/interpreter/mterp/mips/op_ushr_long_2addr.S deleted file mode 100644 index 0da2011e6a..0000000000 --- a/runtime/interpreter/mterp/mips/op_ushr_long_2addr.S +++ /dev/null @@ -1,28 +0,0 @@ -%def op_ushr_long_2addr(): - /* - * Long integer shift, 2addr version. vA is 64-bit value/result, vB is - * 32-bit shift distance. - */ - /* ushr-long/2addr vA, vB */ - GET_OPA4(t3) # t3 <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a2, a3) # a2 <- vB - EAS2(t0, rFP, t3) # t0 <- &fp[A] - LOAD64(a0, a1, t0) # a0/a1 <- vA/vA+1 - - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - - andi v0, a2, 0x20 # shift & 0x20 - srl v1, a1, a2 # rhi<- ahi >> (shift&31) - bnez v0, .L${opcode}_finish - srl v0, a0, a2 # rlo<- alo >> (shift&31) - not a0, a2 # alo<- 31-n (shift is 5b) - sll a1, 1 - sll a1, a0 # ahi<- ahi << (32-(shift&31)) - or v0, a1 # rlo<- rlo | ahi - SET_VREG64_GOTO(v0, v1, t3, t0) # vA/vA+1 <- v0/v1 -%def op_ushr_long_2addr_sister_code(): - -.L${opcode}_finish: - SET_VREG64_GOTO(v1, zero, t3, t0) # vA/vA+1 <- rlo/rhi diff --git a/runtime/interpreter/mterp/mips/op_xor_int.S b/runtime/interpreter/mterp/mips/op_xor_int.S deleted file mode 100644 index 1379a344e0..0000000000 --- a/runtime/interpreter/mterp/mips/op_xor_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_xor_int(): -% binop(instr="xor a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_xor_int_2addr.S b/runtime/interpreter/mterp/mips/op_xor_int_2addr.S deleted file mode 100644 index 6dbe11c3a8..0000000000 --- a/runtime/interpreter/mterp/mips/op_xor_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_xor_int_2addr(): -% binop2addr(instr="xor a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_xor_int_lit16.S b/runtime/interpreter/mterp/mips/op_xor_int_lit16.S deleted file mode 100644 index f8cbce04f4..0000000000 --- a/runtime/interpreter/mterp/mips/op_xor_int_lit16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_xor_int_lit16(): -% binopLit16(instr="xor a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_xor_int_lit8.S b/runtime/interpreter/mterp/mips/op_xor_int_lit8.S deleted file mode 100644 index 268a43aac8..0000000000 --- a/runtime/interpreter/mterp/mips/op_xor_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_xor_int_lit8(): -% binopLit8(instr="xor a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips/op_xor_long.S b/runtime/interpreter/mterp/mips/op_xor_long.S deleted file mode 100644 index 5c0c641243..0000000000 --- a/runtime/interpreter/mterp/mips/op_xor_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_xor_long(): -% binopWide(preinstr="xor a0, a0, a2", instr="xor a1, a1, a3") diff --git a/runtime/interpreter/mterp/mips/op_xor_long_2addr.S b/runtime/interpreter/mterp/mips/op_xor_long_2addr.S deleted file mode 100644 index a84e9f05e0..0000000000 --- a/runtime/interpreter/mterp/mips/op_xor_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_xor_long_2addr(): -% binopWide2addr(preinstr="xor a0, a0, a2", instr="xor a1, a1, a3") diff --git a/runtime/interpreter/mterp/mips/other.S b/runtime/interpreter/mterp/mips/other.S new file mode 100644 index 0000000000..500232984b --- /dev/null +++ b/runtime/interpreter/mterp/mips/other.S @@ -0,0 +1,345 @@ +%def const(helper="UndefinedConstHandler"): + /* const/class vAA, type@BBBB */ + /* const/method-handle vAA, method_handle@BBBB */ + /* const/method-type vAA, proto@BBBB */ + /* const/string vAA, string@@BBBB */ + .extern $helper + EXPORT_PC() + FETCH(a0, 1) # a0 <- BBBB + GET_OPA(a1) # a1 <- AA + addu a2, rFP, OFF_FP_SHADOWFRAME # a2 <- shadow frame + move a3, rSELF + JAL($helper) # v0 <- Mterp(index, tgt_reg, shadow_frame, self) + PREFETCH_INST(2) # load rINST + bnez v0, MterpPossibleException + ADVANCE(2) # advance rPC + GET_INST_OPCODE(t0) # extract opcode from rINST + GOTO_OPCODE(t0) # jump to next instruction + +%def unused(): +/* + * Bail to reference interpreter to throw. + */ + b MterpFallback + +%def op_const(): + /* const vAA, +BBBBbbbb */ + GET_OPA(a3) # a3 <- AA + FETCH(a0, 1) # a0 <- bbbb (low) + FETCH(a1, 2) # a1 <- BBBB (high) + FETCH_ADVANCE_INST(3) # advance rPC, load rINST + INSERT_HIGH_HALF(a0, a1) # a0 <- BBBBbbbb + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG_GOTO(a0, a3, t0) # vAA <- a0 + +%def op_const_16(): + /* const/16 vAA, +BBBB */ + FETCH_S(a0, 1) # a0 <- ssssBBBB (sign-extended) + GET_OPA(a3) # a3 <- AA + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG_GOTO(a0, a3, t0) # vAA <- a0 + +%def op_const_4(): + /* const/4 vA, +B */ + sll a1, rINST, 16 # a1 <- Bxxx0000 + GET_OPA(a0) # a0 <- A+ + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + sra a1, a1, 28 # a1 <- sssssssB (sign-extended) + and a0, a0, 15 + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG_GOTO(a1, a0, t0) # fp[A] <- a1 + +%def op_const_class(): +% const(helper="MterpConstClass") + +%def op_const_high16(): + /* const/high16 vAA, +BBBB0000 */ + FETCH(a0, 1) # a0 <- 0000BBBB (zero-extended) + GET_OPA(a3) # a3 <- AA + sll a0, a0, 16 # a0 <- BBBB0000 + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG_GOTO(a0, a3, t0) # vAA <- a0 + +%def op_const_method_handle(): +% const(helper="MterpConstMethodHandle") + +%def op_const_method_type(): +% const(helper="MterpConstMethodType") + +%def op_const_string(): +% const(helper="MterpConstString") + +%def op_const_string_jumbo(): + /* const/string vAA, string@BBBBBBBB */ + EXPORT_PC() + FETCH(a0, 1) # a0 <- bbbb (low) + FETCH(a2, 2) # a2 <- BBBB (high) + GET_OPA(a1) # a1 <- AA + INSERT_HIGH_HALF(a0, a2) # a0 <- BBBBbbbb + addu a2, rFP, OFF_FP_SHADOWFRAME # a2 <- shadow frame + move a3, rSELF + JAL(MterpConstString) # v0 <- Mterp(index, tgt_reg, shadow_frame, self) + PREFETCH_INST(3) # load rINST + bnez v0, MterpPossibleException + ADVANCE(3) # advance rPC + GET_INST_OPCODE(t0) # extract opcode from rINST + GOTO_OPCODE(t0) # jump to next instruction + +%def op_const_wide(): + /* const-wide vAA, +HHHHhhhhBBBBbbbb */ + FETCH(a0, 1) # a0 <- bbbb (low) + FETCH(a1, 2) # a1 <- BBBB (low middle) + FETCH(a2, 3) # a2 <- hhhh (high middle) + INSERT_HIGH_HALF(a0, a1) # a0 <- BBBBbbbb (low word) + FETCH(a3, 4) # a3 <- HHHH (high) + GET_OPA(t1) # t1 <- AA + INSERT_HIGH_HALF(a2, a3) # a2 <- HHHHhhhh (high word) + FETCH_ADVANCE_INST(5) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG64_GOTO(a0, a2, t1, t0) # vAA/vAA+1 <- a0/a2 + +%def op_const_wide_16(): + /* const-wide/16 vAA, +BBBB */ + FETCH_S(a0, 1) # a0 <- ssssBBBB (sign-extended) + GET_OPA(a3) # a3 <- AA + sra a1, a0, 31 # a1 <- ssssssss + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG64_GOTO(a0, a1, a3, t0) # vAA/vAA+1 <- a0/a1 + +%def op_const_wide_32(): + /* const-wide/32 vAA, +BBBBbbbb */ + FETCH(a0, 1) # a0 <- 0000bbbb (low) + GET_OPA(a3) # a3 <- AA + FETCH_S(a2, 2) # a2 <- ssssBBBB (high) + FETCH_ADVANCE_INST(3) # advance rPC, load rINST + INSERT_HIGH_HALF(a0, a2) # a0 <- BBBBbbbb + sra a1, a0, 31 # a1 <- ssssssss + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG64_GOTO(a0, a1, a3, t0) # vAA/vAA+1 <- a0/a1 + +%def op_const_wide_high16(): + /* const-wide/high16 vAA, +BBBB000000000000 */ + FETCH(a1, 1) # a1 <- 0000BBBB (zero-extended) + GET_OPA(a3) # a3 <- AA + li a0, 0 # a0 <- 00000000 + sll a1, 16 # a1 <- BBBB0000 + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG64_GOTO(a0, a1, a3, t0) # vAA/vAA+1 <- a0/a1 + +%def op_monitor_enter(): + /* + * Synchronize on an object. + */ + /* monitor-enter vAA */ + EXPORT_PC() + GET_OPA(a2) # a2 <- AA + GET_VREG(a0, a2) # a0 <- vAA (object) + move a1, rSELF # a1 <- self + JAL(artLockObjectFromCode) # v0 <- artLockObject(obj, self) + bnez v0, MterpException + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + GOTO_OPCODE(t0) # jump to next instruction + +%def op_monitor_exit(): + /* + * Unlock an object. + * + * Exceptions that occur when unlocking a monitor need to appear as + * if they happened at the following instruction. See the Dalvik + * instruction spec. + */ + /* monitor-exit vAA */ + EXPORT_PC() + GET_OPA(a2) # a2 <- AA + GET_VREG(a0, a2) # a0 <- vAA (object) + move a1, rSELF # a1 <- self + JAL(artUnlockObjectFromCode) # v0 <- artUnlockObject(obj, self) + bnez v0, MterpException + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + GOTO_OPCODE(t0) # jump to next instruction + +%def op_move(is_object="0"): + /* for move, move-object, long-to-int */ + /* op vA, vB */ + GET_OPB(a1) # a1 <- B from 15:12 + GET_OPA4(a0) # a0 <- A from 11:8 + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + GET_VREG(a2, a1) # a2 <- fp[B] + GET_INST_OPCODE(t0) # t0 <- opcode from rINST + .if $is_object + SET_VREG_OBJECT_GOTO(a2, a0, t0) # fp[A] <- a2 + .else + SET_VREG_GOTO(a2, a0, t0) # fp[A] <- a2 + .endif + +%def op_move_16(is_object="0"): + /* for: move/16, move-object/16 */ + /* op vAAAA, vBBBB */ + FETCH(a1, 2) # a1 <- BBBB + FETCH(a0, 1) # a0 <- AAAA + FETCH_ADVANCE_INST(3) # advance rPC, load rINST + GET_VREG(a2, a1) # a2 <- fp[BBBB] + GET_INST_OPCODE(t0) # extract opcode from rINST + .if $is_object + SET_VREG_OBJECT_GOTO(a2, a0, t0) # fp[AAAA] <- a2 + .else + SET_VREG_GOTO(a2, a0, t0) # fp[AAAA] <- a2 + .endif + +%def op_move_exception(): + /* move-exception vAA */ + GET_OPA(a2) # a2 <- AA + lw a3, THREAD_EXCEPTION_OFFSET(rSELF) # get exception obj + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + GET_OPCODE_TARGET(t0) + SET_VREG_OBJECT(a3, a2) # fp[AA] <- exception obj + sw zero, THREAD_EXCEPTION_OFFSET(rSELF) # clear exception + JR(t0) # jump to next instruction + +%def op_move_from16(is_object="0"): + /* for: move/from16, move-object/from16 */ + /* op vAA, vBBBB */ + FETCH(a1, 1) # a1 <- BBBB + GET_OPA(a0) # a0 <- AA + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + GET_VREG(a2, a1) # a2 <- fp[BBBB] + GET_INST_OPCODE(t0) # extract opcode from rINST + .if $is_object + SET_VREG_OBJECT_GOTO(a2, a0, t0) # fp[AA] <- a2 + .else + SET_VREG_GOTO(a2, a0, t0) # fp[AA] <- a2 + .endif + +%def op_move_object(): +% op_move(is_object="1") + +%def op_move_object_16(): +% op_move_16(is_object="1") + +%def op_move_object_from16(): +% op_move_from16(is_object="1") + +%def op_move_result(is_object="0"): + /* for: move-result, move-result-object */ + /* op vAA */ + GET_OPA(a2) # a2 <- AA + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + lw a0, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType + lw a0, 0(a0) # a0 <- result.i + GET_INST_OPCODE(t0) # extract opcode from rINST + .if $is_object + SET_VREG_OBJECT_GOTO(a0, a2, t0) # fp[AA] <- a0 + .else + SET_VREG_GOTO(a0, a2, t0) # fp[AA] <- a0 + .endif + +%def op_move_result_object(): +% op_move_result(is_object="1") + +%def op_move_result_wide(): + /* move-result-wide vAA */ + GET_OPA(a2) # a2 <- AA + lw a3, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType + LOAD64(a0, a1, a3) # a0/a1 <- retval.j + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG64_GOTO(a0, a1, a2, t0) # fp[AA] <- a0/a1 + +%def op_move_wide(): + /* move-wide vA, vB */ + /* NOTE: regs can overlap, e.g. "move v6, v7" or "move v7, v6" */ + GET_OPA4(a2) # a2 <- A(+) + GET_OPB(a3) # a3 <- B + EAS2(a3, rFP, a3) # a3 <- &fp[B] + LOAD64(a0, a1, a3) # a0/a1 <- fp[B] + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG64_GOTO(a0, a1, a2, t0) # fp[A] <- a0/a1 + +%def op_move_wide_16(): + /* move-wide/16 vAAAA, vBBBB */ + /* NOTE: regs can overlap, e.g. "move v6, v7" or "move v7, v6" */ + FETCH(a3, 2) # a3 <- BBBB + FETCH(a2, 1) # a2 <- AAAA + EAS2(a3, rFP, a3) # a3 <- &fp[BBBB] + LOAD64(a0, a1, a3) # a0/a1 <- fp[BBBB] + FETCH_ADVANCE_INST(3) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG64_GOTO(a0, a1, a2, t0) # fp[AAAA] <- a0/a1 + +%def op_move_wide_from16(): + /* move-wide/from16 vAA, vBBBB */ + /* NOTE: regs can overlap, e.g. "move v6, v7" or "move v7, v6" */ + FETCH(a3, 1) # a3 <- BBBB + GET_OPA(a2) # a2 <- AA + EAS2(a3, rFP, a3) # a3 <- &fp[BBBB] + LOAD64(a0, a1, a3) # a0/a1 <- fp[BBBB] + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG64_GOTO(a0, a1, a2, t0) # fp[AA] <- a0/a1 + +%def op_nop(): + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + GOTO_OPCODE(t0) # jump to next instruction + +%def op_unused_3e(): +% unused() + +%def op_unused_3f(): +% unused() + +%def op_unused_40(): +% unused() + +%def op_unused_41(): +% unused() + +%def op_unused_42(): +% unused() + +%def op_unused_43(): +% unused() + +%def op_unused_73(): +% unused() + +%def op_unused_79(): +% unused() + +%def op_unused_7a(): +% unused() + +%def op_unused_f3(): +% unused() + +%def op_unused_f4(): +% unused() + +%def op_unused_f5(): +% unused() + +%def op_unused_f6(): +% unused() + +%def op_unused_f7(): +% unused() + +%def op_unused_f8(): +% unused() + +%def op_unused_f9(): +% unused() + +%def op_unused_fc(): +% unused() + +%def op_unused_fd(): +% unused() diff --git a/runtime/interpreter/mterp/mips/unop.S b/runtime/interpreter/mterp/mips/unop.S deleted file mode 100644 index 34eb118946..0000000000 --- a/runtime/interpreter/mterp/mips/unop.S +++ /dev/null @@ -1,18 +0,0 @@ -%def unop(preinstr="", result0="a0", instr=""): - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result0 = op a0". - * This could be a MIPS instruction or a function call. - * - * for: int-to-byte, int-to-char, int-to-short, - * neg-int, not-int, neg-float - */ - /* unop vA, vB */ - GET_OPB(a3) # a3 <- B - GET_OPA4(t0) # t0 <- A+ - GET_VREG(a0, a3) # a0 <- vB - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - $preinstr # optional op - $instr # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t1) # extract opcode from rINST - SET_VREG_GOTO($result0, t0, t1) # vA <- result0 diff --git a/runtime/interpreter/mterp/mips/unopNarrower.S b/runtime/interpreter/mterp/mips/unopNarrower.S deleted file mode 100644 index 4f0bb1dc1b..0000000000 --- a/runtime/interpreter/mterp/mips/unopNarrower.S +++ /dev/null @@ -1,16 +0,0 @@ -%def unopNarrower(load="LOAD64_F(fa0, fa0f, a3)", instr=""): - /* - * Generic 64bit-to-32bit floating-point unary operation. Provide an "instr" - * line that specifies an instruction that performs "fv0 = op fa0". - * - * For: double-to-float - */ - /* unop vA, vB */ - GET_OPB(a3) # a3 <- B - GET_OPA4(rOBJ) # rOBJ <- A+ - EAS2(a3, rFP, a3) # a3 <- &fp[B] - $load - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - $instr - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_F_GOTO(fv0, rOBJ, t0) # vA <- fv0 diff --git a/runtime/interpreter/mterp/mips/unopWide.S b/runtime/interpreter/mterp/mips/unopWide.S deleted file mode 100644 index 269a29651f..0000000000 --- a/runtime/interpreter/mterp/mips/unopWide.S +++ /dev/null @@ -1,18 +0,0 @@ -%def unopWide(preinstr="", result0="a0", result1="a1", instr=""): - /* - * Generic 64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result0/result1 = op a0/a1". - * This could be MIPS instruction or a function call. - * - * For: neg-long, not-long, neg-double, - */ - /* unop vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - EAS2(a3, rFP, a3) # a3 <- &fp[B] - LOAD64(a0, a1, a3) # a0/a1 <- vA - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - $preinstr # optional op - $instr # a0/a1 <- op, a2-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO($result0, $result1, rOBJ, t0) # vA/vA+1 <- a0/a1 diff --git a/runtime/interpreter/mterp/mips/unopWider.S b/runtime/interpreter/mterp/mips/unopWider.S deleted file mode 100644 index 7767d6ee50..0000000000 --- a/runtime/interpreter/mterp/mips/unopWider.S +++ /dev/null @@ -1,16 +0,0 @@ -%def unopWider(preinstr="", result0="a0", result1="a1", instr=""): - /* - * Generic 32bit-to-64bit unary operation. Provide an "instr" line - * that specifies an instruction that performs "result0/result1 = op a0". - * - * For: int-to-long - */ - /* unop vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a0, a3) # a0 <- vB - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - $preinstr # optional op - $instr # result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO($result0, $result1, rOBJ, t0) # vA/vA+1 <- a0/a1 diff --git a/runtime/interpreter/mterp/mips/unused.S b/runtime/interpreter/mterp/mips/unused.S deleted file mode 100644 index 3f37e74bb4..0000000000 --- a/runtime/interpreter/mterp/mips/unused.S +++ /dev/null @@ -1,5 +0,0 @@ -%def unused(): -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback diff --git a/runtime/interpreter/mterp/mips/zcmp.S b/runtime/interpreter/mterp/mips/zcmp.S deleted file mode 100644 index eb23eea744..0000000000 --- a/runtime/interpreter/mterp/mips/zcmp.S +++ /dev/null @@ -1,17 +0,0 @@ -%def zcmp(condition=""): - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - GET_OPA(a0) # a0 <- AA - GET_VREG(a0, a0) # a0 <- vAA - FETCH_S(rINST, 1) # rINST <- branch offset, in code units - b${condition} a0, zero, MterpCommonTakenBranchNoFlags - li t0, JIT_CHECK_OSR # possible OSR re-entry? - beq rPROFILE, t0, .L_check_not_taken_osr - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/alt_stub.S b/runtime/interpreter/mterp/mips64/alt_stub.S deleted file mode 100644 index 17558bb4c2..0000000000 --- a/runtime/interpreter/mterp/mips64/alt_stub.S +++ /dev/null @@ -1,15 +0,0 @@ -%def alt_stub(): -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (${opnum} * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. diff --git a/runtime/interpreter/mterp/mips64/arithmetic.S b/runtime/interpreter/mterp/mips64/arithmetic.S new file mode 100644 index 0000000000..0b03e02b5f --- /dev/null +++ b/runtime/interpreter/mterp/mips64/arithmetic.S @@ -0,0 +1,458 @@ +%def binop(preinstr="", result="a0", chkzero="0", instr=""): + /* + * Generic 32-bit binary operation. Provide an "instr" line that + * specifies an instruction that performs "result = a0 op a1". + * This could be a MIPS instruction or a function call. (If the result + * comes back in a register other than a0, you can override "result".) + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vCC (a1). Useful for integer division and modulus. Note that we + * *don't* check for (INT_MIN / -1) here, because the CPU handles it + * correctly. + * + * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, + * xor-int, shl-int, shr-int, ushr-int + */ + /* binop vAA, vBB, vCC */ + srl a4, rINST, 8 # a4 <- AA + lbu a2, 2(rPC) # a2 <- BB + lbu a3, 3(rPC) # a3 <- CC + GET_VREG a0, a2 # a0 <- vBB + GET_VREG a1, a3 # a1 <- vCC + .if $chkzero + beqz a1, common_errDivideByZero # is second operand zero? + .endif + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + $preinstr # optional op + $instr # $result <- op, a0-a3 changed + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG $result, a4 # vAA <- $result + GOTO_OPCODE v0 # jump to next instruction + +%def binop2addr(preinstr="", result="a0", chkzero="0", instr=""): + /* + * Generic 32-bit "/2addr" binary operation. Provide an "instr" line + * that specifies an instruction that performs "result = a0 op a1". + * This could be a MIPS instruction or a function call. (If the result + * comes back in a register other than a0, you can override "result".) + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vB (a1). Useful for integer division and modulus. Note that we + * *don't* check for (INT_MIN / -1) here, because the CPU handles it + * correctly. + * + * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, + * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, + * shl-int/2addr, shr-int/2addr, ushr-int/2addr + */ + /* binop/2addr vA, vB */ + ext a2, rINST, 8, 4 # a2 <- A + ext a3, rINST, 12, 4 # a3 <- B + GET_VREG a0, a2 # a0 <- vA + GET_VREG a1, a3 # a1 <- vB + .if $chkzero + beqz a1, common_errDivideByZero # is second operand zero? + .endif + FETCH_ADVANCE_INST 1 # advance rPC, load rINST + $preinstr # optional op + $instr # $result <- op, a0-a3 changed + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG $result, a2 # vA <- $result + GOTO_OPCODE v0 # jump to next instruction + +%def binopLit16(preinstr="", result="a0", chkzero="0", instr=""): + /* + * Generic 32-bit "lit16" binary operation. Provide an "instr" line + * that specifies an instruction that performs "result = a0 op a1". + * This could be an MIPS instruction or a function call. (If the result + * comes back in a register other than a0, you can override "result".) + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * CCCC (a1). Useful for integer division and modulus. + * + * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, + * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 + */ + /* binop/lit16 vA, vB, #+CCCC */ + lh a1, 2(rPC) # a1 <- sign-extended CCCC + ext a2, rINST, 8, 4 # a2 <- A + ext a3, rINST, 12, 4 # a3 <- B + GET_VREG a0, a3 # a0 <- vB + .if $chkzero + beqz a1, common_errDivideByZero # is second operand zero? + .endif + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + $preinstr # optional op + $instr # $result <- op, a0-a3 changed + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG $result, a2 # vA <- $result + GOTO_OPCODE v0 # jump to next instruction + + +%def binopLit8(preinstr="", result="a0", chkzero="0", instr=""): + /* + * Generic 32-bit "lit8" binary operation. Provide an "instr" line + * that specifies an instruction that performs "result = a0 op a1". + * This could be an MIPS instruction or a function call. (If the result + * comes back in a register other than a0, you can override "result".) + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * CC (a1). Useful for integer division and modulus. + * + * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, + * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, + * shl-int/lit8, shr-int/lit8, ushr-int/lit8 + */ + /* binop/lit8 vAA, vBB, #+CC */ + lbu a3, 2(rPC) # a3 <- BB + lb a1, 3(rPC) # a1 <- sign-extended CC + srl a2, rINST, 8 # a2 <- AA + GET_VREG a0, a3 # a0 <- vBB + .if $chkzero + beqz a1, common_errDivideByZero # is second operand zero? + .endif + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + $preinstr # optional op + $instr # $result <- op, a0-a3 changed + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG $result, a2 # vAA <- $result + GOTO_OPCODE v0 # jump to next instruction + + +%def binopWide(preinstr="", result="a0", chkzero="0", instr=""): + /* + * Generic 64-bit binary operation. Provide an "instr" line that + * specifies an instruction that performs "result = a0 op a1". + * This could be a MIPS instruction or a function call. (If the result + * comes back in a register other than a0, you can override "result".) + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vCC (a1). Useful for integer division and modulus. Note that we + * *don't* check for (LONG_MIN / -1) here, because the CPU handles it + * correctly. + * + * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, + * xor-long, shl-long, shr-long, ushr-long + */ + /* binop vAA, vBB, vCC */ + srl a4, rINST, 8 # a4 <- AA + lbu a2, 2(rPC) # a2 <- BB + lbu a3, 3(rPC) # a3 <- CC + GET_VREG_WIDE a0, a2 # a0 <- vBB + GET_VREG_WIDE a1, a3 # a1 <- vCC + .if $chkzero + beqz a1, common_errDivideByZero # is second operand zero? + .endif + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + $preinstr # optional op + $instr # $result <- op, a0-a3 changed + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG_WIDE $result, a4 # vAA <- $result + GOTO_OPCODE v0 # jump to next instruction + +%def binopWide2addr(preinstr="", result="a0", chkzero="0", instr=""): + /* + * Generic 64-bit "/2addr" binary operation. Provide an "instr" line + * that specifies an instruction that performs "result = a0 op a1". + * This could be a MIPS instruction or a function call. (If the result + * comes back in a register other than a0, you can override "result".) + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vB (a1). Useful for integer division and modulus. Note that we + * *don't* check for (LONG_MIN / -1) here, because the CPU handles it + * correctly. + * + * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, + * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, + * shl-long/2addr, shr-long/2addr, ushr-long/2addr + */ + /* binop/2addr vA, vB */ + ext a2, rINST, 8, 4 # a2 <- A + ext a3, rINST, 12, 4 # a3 <- B + GET_VREG_WIDE a0, a2 # a0 <- vA + GET_VREG_WIDE a1, a3 # a1 <- vB + .if $chkzero + beqz a1, common_errDivideByZero # is second operand zero? + .endif + FETCH_ADVANCE_INST 1 # advance rPC, load rINST + $preinstr # optional op + $instr # $result <- op, a0-a3 changed + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG_WIDE $result, a2 # vA <- $result + GOTO_OPCODE v0 # jump to next instruction + +%def unop(preinstr="", instr=""): + /* + * Generic 32-bit unary operation. Provide an "instr" line that + * specifies an instruction that performs "a0 = op a0". + * + * for: int-to-byte, int-to-char, int-to-short, + * not-int, neg-int + */ + /* unop vA, vB */ + ext a3, rINST, 12, 4 # a3 <- B + GET_VREG a0, a3 # a0 <- vB + ext a2, rINST, 8, 4 # a2 <- A + $preinstr # optional op + FETCH_ADVANCE_INST 1 # advance rPC, load rINST + $instr # a0 <- op, a0-a3 changed + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG a0, a2 # vA <- a0 + GOTO_OPCODE v0 # jump to next instruction + +%def unopWide(preinstr="", instr=""): + /* + * Generic 64-bit unary operation. Provide an "instr" line that + * specifies an instruction that performs "a0 = op a0". + * + * For: not-long, neg-long + */ + /* unop vA, vB */ + ext a3, rINST, 12, 4 # a3 <- B + GET_VREG_WIDE a0, a3 # a0 <- vB + ext a2, rINST, 8, 4 # a2 <- A + $preinstr # optional op + FETCH_ADVANCE_INST 1 # advance rPC, load rINST + $instr # a0 <- op, a0-a3 changed + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG_WIDE a0, a2 # vA <- a0 + GOTO_OPCODE v0 # jump to next instruction + +%def op_add_int(): +% binop(instr="addu a0, a0, a1") + +%def op_add_int_2addr(): +% binop2addr(instr="addu a0, a0, a1") + +%def op_add_int_lit16(): +% binopLit16(instr="addu a0, a0, a1") + +%def op_add_int_lit8(): +% binopLit8(instr="addu a0, a0, a1") + +%def op_add_long(): +% binopWide(instr="daddu a0, a0, a1") + +%def op_add_long_2addr(): +% binopWide2addr(instr="daddu a0, a0, a1") + +%def op_and_int(): +% binop(instr="and a0, a0, a1") + +%def op_and_int_2addr(): +% binop2addr(instr="and a0, a0, a1") + +%def op_and_int_lit16(): +% binopLit16(instr="and a0, a0, a1") + +%def op_and_int_lit8(): +% binopLit8(instr="and a0, a0, a1") + +%def op_and_long(): +% binopWide(instr="and a0, a0, a1") + +%def op_and_long_2addr(): +% binopWide2addr(instr="and a0, a0, a1") + +%def op_cmp_long(): + /* cmp-long vAA, vBB, vCC */ + lbu a2, 2(rPC) # a2 <- BB + lbu a3, 3(rPC) # a3 <- CC + srl a4, rINST, 8 # a4 <- AA + GET_VREG_WIDE a0, a2 # a0 <- vBB + GET_VREG_WIDE a1, a3 # a1 <- vCC + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + slt a2, a0, a1 + slt a0, a1, a0 + subu a0, a0, a2 + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG a0, a4 # vAA <- result + GOTO_OPCODE v0 # jump to next instruction + +%def op_div_int(): +% binop(instr="div a0, a0, a1", chkzero="1") + +%def op_div_int_2addr(): +% binop2addr(instr="div a0, a0, a1", chkzero="1") + +%def op_div_int_lit16(): +% binopLit16(instr="div a0, a0, a1", chkzero="1") + +%def op_div_int_lit8(): +% binopLit8(instr="div a0, a0, a1", chkzero="1") + +%def op_div_long(): +% binopWide(instr="ddiv a0, a0, a1", chkzero="1") + +%def op_div_long_2addr(): +% binopWide2addr(instr="ddiv a0, a0, a1", chkzero="1") + +%def op_int_to_byte(): +% unop(instr="seb a0, a0") + +%def op_int_to_char(): +% unop(instr="and a0, a0, 0xffff") + +%def op_int_to_long(): + /* int-to-long vA, vB */ + ext a3, rINST, 12, 4 # a3 <- B + GET_VREG a0, a3 # a0 <- vB (sign-extended to 64 bits) + ext a2, rINST, 8, 4 # a2 <- A + FETCH_ADVANCE_INST 1 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG_WIDE a0, a2 # vA <- vB + GOTO_OPCODE v0 # jump to next instruction + +%def op_int_to_short(): +% unop(instr="seh a0, a0") + +%def op_long_to_int(): +/* we ignore the high word, making this equivalent to a 32-bit reg move */ +% op_move() + +%def op_mul_int(): +% binop(instr="mul a0, a0, a1") + +%def op_mul_int_2addr(): +% binop2addr(instr="mul a0, a0, a1") + +%def op_mul_int_lit16(): +% binopLit16(instr="mul a0, a0, a1") + +%def op_mul_int_lit8(): +% binopLit8(instr="mul a0, a0, a1") + +%def op_mul_long(): +% binopWide(instr="dmul a0, a0, a1") + +%def op_mul_long_2addr(): +% binopWide2addr(instr="dmul a0, a0, a1") + +%def op_neg_int(): +% unop(instr="subu a0, zero, a0") + +%def op_neg_long(): +% unopWide(instr="dsubu a0, zero, a0") + +%def op_not_int(): +% unop(instr="nor a0, zero, a0") + +%def op_not_long(): +% unopWide(instr="nor a0, zero, a0") + +%def op_or_int(): +% binop(instr="or a0, a0, a1") + +%def op_or_int_2addr(): +% binop2addr(instr="or a0, a0, a1") + +%def op_or_int_lit16(): +% binopLit16(instr="or a0, a0, a1") + +%def op_or_int_lit8(): +% binopLit8(instr="or a0, a0, a1") + +%def op_or_long(): +% binopWide(instr="or a0, a0, a1") + +%def op_or_long_2addr(): +% binopWide2addr(instr="or a0, a0, a1") + +%def op_rem_int(): +% binop(instr="mod a0, a0, a1", chkzero="1") + +%def op_rem_int_2addr(): +% binop2addr(instr="mod a0, a0, a1", chkzero="1") + +%def op_rem_int_lit16(): +% binopLit16(instr="mod a0, a0, a1", chkzero="1") + +%def op_rem_int_lit8(): +% binopLit8(instr="mod a0, a0, a1", chkzero="1") + +%def op_rem_long(): +% binopWide(instr="dmod a0, a0, a1", chkzero="1") + +%def op_rem_long_2addr(): +% binopWide2addr(instr="dmod a0, a0, a1", chkzero="1") + +%def op_rsub_int(): +% binopLit16(instr="subu a0, a1, a0") + +%def op_rsub_int_lit8(): +% binopLit8(instr="subu a0, a1, a0") + +%def op_shl_int(): +% binop(instr="sll a0, a0, a1") + +%def op_shl_int_2addr(): +% binop2addr(instr="sll a0, a0, a1") + +%def op_shl_int_lit8(): +% binopLit8(instr="sll a0, a0, a1") + +%def op_shl_long(): +% binopWide(instr="dsll a0, a0, a1") + +%def op_shl_long_2addr(): +% binopWide2addr(instr="dsll a0, a0, a1") + +%def op_shr_int(): +% binop(instr="sra a0, a0, a1") + +%def op_shr_int_2addr(): +% binop2addr(instr="sra a0, a0, a1") + +%def op_shr_int_lit8(): +% binopLit8(instr="sra a0, a0, a1") + +%def op_shr_long(): +% binopWide(instr="dsra a0, a0, a1") + +%def op_shr_long_2addr(): +% binopWide2addr(instr="dsra a0, a0, a1") + +%def op_sub_int(): +% binop(instr="subu a0, a0, a1") + +%def op_sub_int_2addr(): +% binop2addr(instr="subu a0, a0, a1") + +%def op_sub_long(): +% binopWide(instr="dsubu a0, a0, a1") + +%def op_sub_long_2addr(): +% binopWide2addr(instr="dsubu a0, a0, a1") + +%def op_ushr_int(): +% binop(instr="srl a0, a0, a1") + +%def op_ushr_int_2addr(): +% binop2addr(instr="srl a0, a0, a1") + +%def op_ushr_int_lit8(): +% binopLit8(instr="srl a0, a0, a1") + +%def op_ushr_long(): +% binopWide(instr="dsrl a0, a0, a1") + +%def op_ushr_long_2addr(): +% binopWide2addr(instr="dsrl a0, a0, a1") + +%def op_xor_int(): +% binop(instr="xor a0, a0, a1") + +%def op_xor_int_2addr(): +% binop2addr(instr="xor a0, a0, a1") + +%def op_xor_int_lit16(): +% binopLit16(instr="xor a0, a0, a1") + +%def op_xor_int_lit8(): +% binopLit8(instr="xor a0, a0, a1") + +%def op_xor_long(): +% binopWide(instr="xor a0, a0, a1") + +%def op_xor_long_2addr(): +% binopWide2addr(instr="xor a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/array.S b/runtime/interpreter/mterp/mips64/array.S new file mode 100644 index 0000000000..9d97f0ad8d --- /dev/null +++ b/runtime/interpreter/mterp/mips64/array.S @@ -0,0 +1,241 @@ +%def op_aget(load="lw", shift="2", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"): + /* + * Array get, 32 bits or less. vAA <- vBB[vCC]. + * + * for: aget, aget-boolean, aget-byte, aget-char, aget-short + * + * NOTE: assumes data offset for arrays is the same for all non-wide types. + * If this changes, specialize. + */ + /* op vAA, vBB, vCC */ + lbu a2, 2(rPC) # a2 <- BB + lbu a3, 3(rPC) # a3 <- CC + srl a4, rINST, 8 # a4 <- AA + GET_VREG_U a0, a2 # a0 <- vBB (array object) + GET_VREG a1, a3 # a1 <- vCC (requested index) + beqz a0, common_errNullObject # bail if null array object + lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length + .if $shift + # [d]lsa does not support shift count of 0. + dlsa a0, a1, a0, $shift # a0 <- arrayObj + index*width + .else + daddu a0, a1, a0 # a0 <- arrayObj + index*width + .endif + bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + $load a2, $data_offset(a0) # a2 <- vBB[vCC] + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG a2, a4 # vAA <- a2 + GOTO_OPCODE v0 # jump to next instruction + +%def op_aget_boolean(): +% op_aget(load="lbu", shift="0", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") + +%def op_aget_byte(): +% op_aget(load="lb", shift="0", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") + +%def op_aget_char(): +% op_aget(load="lhu", shift="1", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") + +%def op_aget_object(): + /* + * Array object get. vAA <- vBB[vCC]. + * + * for: aget-object + */ + /* op vAA, vBB, vCC */ + .extern artAGetObjectFromMterp + lbu a2, 2(rPC) # a2 <- BB + lbu a3, 3(rPC) # a3 <- CC + EXPORT_PC + GET_VREG_U a0, a2 # a0 <- vBB (array object) + GET_VREG a1, a3 # a1 <- vCC (requested index) + jal artAGetObjectFromMterp # (array, index) + ld a1, THREAD_EXCEPTION_OFFSET(rSELF) + srl a4, rINST, 8 # a4 <- AA + PREFETCH_INST 2 + bnez a1, MterpException + SET_VREG_OBJECT v0, a4 # vAA <- v0 + ADVANCE 2 + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +%def op_aget_short(): +% op_aget(load="lh", shift="1", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") + +%def op_aget_wide(): + /* + * Array get, 64 bits. vAA <- vBB[vCC]. + * + */ + /* aget-wide vAA, vBB, vCC */ + lbu a2, 2(rPC) # a2 <- BB + lbu a3, 3(rPC) # a3 <- CC + srl a4, rINST, 8 # a4 <- AA + GET_VREG_U a0, a2 # a0 <- vBB (array object) + GET_VREG a1, a3 # a1 <- vCC (requested index) + beqz a0, common_errNullObject # bail if null array object + lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length + dlsa a0, a1, a0, 3 # a0 <- arrayObj + index*width + bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + lw a2, MIRROR_WIDE_ARRAY_DATA_OFFSET(a0) + lw a3, (MIRROR_WIDE_ARRAY_DATA_OFFSET+4)(a0) + dinsu a2, a3, 32, 32 # a2 <- vBB[vCC] + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG_WIDE a2, a4 # vAA <- a2 + GOTO_OPCODE v0 # jump to next instruction + +%def op_aput(store="sw", shift="2", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"): + /* + * Array put, 32 bits or less. vBB[vCC] <- vAA. + * + * for: aput, aput-boolean, aput-byte, aput-char, aput-short + * + * NOTE: this assumes data offset for arrays is the same for all non-wide types. + * If this changes, specialize. + */ + /* op vAA, vBB, vCC */ + lbu a2, 2(rPC) # a2 <- BB + lbu a3, 3(rPC) # a3 <- CC + srl a4, rINST, 8 # a4 <- AA + GET_VREG_U a0, a2 # a0 <- vBB (array object) + GET_VREG a1, a3 # a1 <- vCC (requested index) + beqz a0, common_errNullObject # bail if null array object + lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length + .if $shift + # [d]lsa does not support shift count of 0. + dlsa a0, a1, a0, $shift # a0 <- arrayObj + index*width + .else + daddu a0, a1, a0 # a0 <- arrayObj + index*width + .endif + bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + GET_VREG a2, a4 # a2 <- vAA + GET_INST_OPCODE v0 # extract opcode from rINST + $store a2, $data_offset(a0) # vBB[vCC] <- a2 + GOTO_OPCODE v0 # jump to next instruction + +%def op_aput_boolean(): +% op_aput(store="sb", shift="0", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") + +%def op_aput_byte(): +% op_aput(store="sb", shift="0", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") + +%def op_aput_char(): +% op_aput(store="sh", shift="1", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") + +%def op_aput_object(): + /* + * Store an object into an array. vBB[vCC] <- vAA. + */ + /* op vAA, vBB, vCC */ + .extern MterpAputObject + EXPORT_PC + daddu a0, rFP, OFF_FP_SHADOWFRAME + move a1, rPC + move a2, rINST + jal MterpAputObject + beqzc v0, MterpPossibleException + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +%def op_aput_short(): +% op_aput(store="sh", shift="1", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") + +%def op_aput_wide(): + /* + * Array put, 64 bits. vBB[vCC] <- vAA. + * + */ + /* aput-wide vAA, vBB, vCC */ + lbu a2, 2(rPC) # a2 <- BB + lbu a3, 3(rPC) # a3 <- CC + srl a4, rINST, 8 # a4 <- AA + GET_VREG_U a0, a2 # a0 <- vBB (array object) + GET_VREG a1, a3 # a1 <- vCC (requested index) + beqz a0, common_errNullObject # bail if null array object + lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length + dlsa a0, a1, a0, 3 # a0 <- arrayObj + index*width + bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail + GET_VREG_WIDE a2, a4 # a2 <- vAA + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + sw a2, MIRROR_WIDE_ARRAY_DATA_OFFSET(a0) + dsrl32 a2, a2, 0 + sw a2, (MIRROR_WIDE_ARRAY_DATA_OFFSET+4)(a0) # vBB[vCC] <- a2 + GOTO_OPCODE v0 # jump to next instruction + +%def op_array_length(): + /* + * Return the length of an array. + */ + srl a1, rINST, 12 # a1 <- B + GET_VREG_U a0, a1 # a0 <- vB (object ref) + ext a2, rINST, 8, 4 # a2 <- A + beqz a0, common_errNullObject # yup, fail + FETCH_ADVANCE_INST 1 # advance rPC, load rINST + lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- array length + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG a3, a2 # vB <- length + GOTO_OPCODE v0 # jump to next instruction + +%def op_fill_array_data(): + /* fill-array-data vAA, +BBBBBBBB */ + .extern MterpFillArrayData + EXPORT_PC + lh a1, 2(rPC) # a1 <- bbbb (lo) + lh a0, 4(rPC) # a0 <- BBBB (hi) + srl a3, rINST, 8 # a3 <- AA + ins a1, a0, 16, 16 # a1 <- BBBBbbbb + GET_VREG_U a0, a3 # a0 <- vAA (array object) + dlsa a1, a1, rPC, 1 # a1 <- PC + BBBBbbbb*2 (array data off.) + jal MterpFillArrayData # (obj, payload) + beqzc v0, MterpPossibleException # exception? + FETCH_ADVANCE_INST 3 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +%def op_filled_new_array(helper="MterpFilledNewArray"): + /* + * Create a new array with elements filled from registers. + * + * for: filled-new-array, filled-new-array/range + */ + /* op vB, {vD, vE, vF, vG, vA}, class//CCCC */ + /* op {vCCCC..v(CCCC+AA-1)}, type//BBBB */ + .extern $helper + EXPORT_PC + daddu a0, rFP, OFF_FP_SHADOWFRAME + move a1, rPC + move a2, rSELF + jal $helper + beqzc v0, MterpPossibleException + FETCH_ADVANCE_INST 3 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +%def op_filled_new_array_range(): +% op_filled_new_array(helper="MterpFilledNewArrayRange") + +%def op_new_array(): + /* + * Allocate an array of objects, specified with the array class + * and a count. + * + * The verifier guarantees that this is an array class, so we don't + * check for it here. + */ + /* new-array vA, vB, class//CCCC */ + .extern MterpNewArray + EXPORT_PC + daddu a0, rFP, OFF_FP_SHADOWFRAME + move a1, rPC + move a2, rINST + move a3, rSELF + jal MterpNewArray + beqzc v0, MterpPossibleException + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/bincmp.S b/runtime/interpreter/mterp/mips64/bincmp.S deleted file mode 100644 index bdf01dc5e3..0000000000 --- a/runtime/interpreter/mterp/mips64/bincmp.S +++ /dev/null @@ -1,20 +0,0 @@ -%def bincmp(condition=""): - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform, e.g. for - * "if-le" you would use "le". - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - lh rINST, 2(rPC) # rINST <- offset (sign-extended CCCC) - GET_VREG a0, a2 # a0 <- vA - GET_VREG a1, a3 # a1 <- vB - b${condition}c a0, a1, MterpCommonTakenBranchNoFlags - li v0, JIT_CHECK_OSR # possible OSR re-entry? - beqc rPROFILE, v0, .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/binop.S b/runtime/interpreter/mterp/mips64/binop.S deleted file mode 100644 index 9332fadd5f..0000000000 --- a/runtime/interpreter/mterp/mips64/binop.S +++ /dev/null @@ -1,30 +0,0 @@ -%def binop(preinstr="", result="a0", chkzero="0", instr=""): - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG a0, a2 # a0 <- vBB - GET_VREG a1, a3 # a1 <- vCC - .if $chkzero - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - $preinstr # optional op - $instr # $result <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG $result, a4 # vAA <- $result - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/binop2addr.S b/runtime/interpreter/mterp/mips64/binop2addr.S deleted file mode 100644 index 19f18151eb..0000000000 --- a/runtime/interpreter/mterp/mips64/binop2addr.S +++ /dev/null @@ -1,30 +0,0 @@ -%def binop2addr(preinstr="", result="a0", chkzero="0", instr=""): - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a2 # a0 <- vA - GET_VREG a1, a3 # a1 <- vB - .if $chkzero - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - $preinstr # optional op - $instr # $result <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG $result, a2 # vA <- $result - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/binopLit16.S b/runtime/interpreter/mterp/mips64/binopLit16.S deleted file mode 100644 index 7cb2b97605..0000000000 --- a/runtime/interpreter/mterp/mips64/binopLit16.S +++ /dev/null @@ -1,28 +0,0 @@ -%def binopLit16(preinstr="", result="a0", chkzero="0", instr=""): - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * CCCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - lh a1, 2(rPC) # a1 <- sign-extended CCCC - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a3 # a0 <- vB - .if $chkzero - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - $preinstr # optional op - $instr # $result <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG $result, a2 # vA <- $result - GOTO_OPCODE v0 # jump to next instruction - diff --git a/runtime/interpreter/mterp/mips64/binopLit8.S b/runtime/interpreter/mterp/mips64/binopLit8.S deleted file mode 100644 index 3c0449f179..0000000000 --- a/runtime/interpreter/mterp/mips64/binopLit8.S +++ /dev/null @@ -1,29 +0,0 @@ -%def binopLit8(preinstr="", result="a0", chkzero="0", instr=""): - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * CC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - lbu a3, 2(rPC) # a3 <- BB - lb a1, 3(rPC) # a1 <- sign-extended CC - srl a2, rINST, 8 # a2 <- AA - GET_VREG a0, a3 # a0 <- vBB - .if $chkzero - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - $preinstr # optional op - $instr # $result <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG $result, a2 # vAA <- $result - GOTO_OPCODE v0 # jump to next instruction - diff --git a/runtime/interpreter/mterp/mips64/binopWide.S b/runtime/interpreter/mterp/mips64/binopWide.S deleted file mode 100644 index 2206b31630..0000000000 --- a/runtime/interpreter/mterp/mips64/binopWide.S +++ /dev/null @@ -1,30 +0,0 @@ -%def binopWide(preinstr="", result="a0", chkzero="0", instr=""): - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, shl-long, shr-long, ushr-long - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_WIDE a0, a2 # a0 <- vBB - GET_VREG_WIDE a1, a3 # a1 <- vCC - .if $chkzero - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - $preinstr # optional op - $instr # $result <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE $result, a4 # vAA <- $result - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/binopWide2addr.S b/runtime/interpreter/mterp/mips64/binopWide2addr.S deleted file mode 100644 index 8758a806db..0000000000 --- a/runtime/interpreter/mterp/mips64/binopWide2addr.S +++ /dev/null @@ -1,30 +0,0 @@ -%def binopWide2addr(preinstr="", result="a0", chkzero="0", instr=""): - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_WIDE a0, a2 # a0 <- vA - GET_VREG_WIDE a1, a3 # a1 <- vB - .if $chkzero - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - $preinstr # optional op - $instr # $result <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE $result, a2 # vA <- $result - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/const.S b/runtime/interpreter/mterp/mips64/const.S deleted file mode 100644 index 5de2404fc7..0000000000 --- a/runtime/interpreter/mterp/mips64/const.S +++ /dev/null @@ -1,17 +0,0 @@ -%def const(helper="UndefinedConstHandler"): - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern $helper - EXPORT_PC - lhu a0, 2(rPC) # a0 <- BBBB - srl a1, rINST, 8 # a1 <- AA - daddu a2, rFP, OFF_FP_SHADOWFRAME - move a3, rSELF - jal $helper # (index, tgt_reg, shadow_frame, self) - PREFETCH_INST 2 # load rINST - bnez v0, MterpPossibleException # let reference interpreter deal with it. - ADVANCE 2 # advance rPC - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/control_flow.S b/runtime/interpreter/mterp/mips64/control_flow.S new file mode 100644 index 0000000000..457b93894a --- /dev/null +++ b/runtime/interpreter/mterp/mips64/control_flow.S @@ -0,0 +1,217 @@ +%def bincmp(condition=""): + /* + * Generic two-operand compare-and-branch operation. Provide a "condition" + * fragment that specifies the comparison to perform, e.g. for + * "if-le" you would use "le". + * + * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le + */ + /* if-cmp vA, vB, +CCCC */ + ext a2, rINST, 8, 4 # a2 <- A + ext a3, rINST, 12, 4 # a3 <- B + lh rINST, 2(rPC) # rINST <- offset (sign-extended CCCC) + GET_VREG a0, a2 # a0 <- vA + GET_VREG a1, a3 # a1 <- vB + b${condition}c a0, a1, MterpCommonTakenBranchNoFlags + li v0, JIT_CHECK_OSR # possible OSR re-entry? + beqc rPROFILE, v0, .L_check_not_taken_osr + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +%def zcmp(condition=""): + /* + * Generic one-operand compare-and-branch operation. Provide a "condition" + * fragment that specifies the comparison to perform, e.g. for + * "if-lez" you would use "le". + * + * For: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez + */ + /* if-cmp vAA, +BBBB */ + srl a2, rINST, 8 # a2 <- AA + lh rINST, 2(rPC) # rINST <- offset (sign-extended BBBB) + GET_VREG a0, a2 # a0 <- vAA + b${condition}zc a0, MterpCommonTakenBranchNoFlags + li v0, JIT_CHECK_OSR # possible OSR re-entry? + beqc rPROFILE, v0, .L_check_not_taken_osr + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +%def op_goto(): + /* + * Unconditional branch, 8-bit offset. + * + * The branch distance is a signed code-unit offset, which we need to + * double to get a byte offset. + */ + /* goto +AA */ + srl rINST, rINST, 8 + seb rINST, rINST # rINST <- offset (sign-extended AA) + b MterpCommonTakenBranchNoFlags + +%def op_goto_16(): + /* + * Unconditional branch, 16-bit offset. + * + * The branch distance is a signed code-unit offset, which we need to + * double to get a byte offset. + */ + /* goto/16 +AAAA */ + lh rINST, 2(rPC) # rINST <- offset (sign-extended AAAA) + b MterpCommonTakenBranchNoFlags + +%def op_goto_32(): + /* + * Unconditional branch, 32-bit offset. + * + * The branch distance is a signed code-unit offset, which we need to + * double to get a byte offset. + * + * Unlike most opcodes, this one is allowed to branch to itself, so + * our "backward branch" test must be "<=0" instead of "<0". + */ + /* goto/32 +AAAAAAAA */ + lh rINST, 2(rPC) # rINST <- aaaa (low) + lh a1, 4(rPC) # a1 <- AAAA (high) + ins rINST, a1, 16, 16 # rINST <- offset (sign-extended AAAAaaaa) + b MterpCommonTakenBranchNoFlags + +%def op_if_eq(): +% bincmp(condition="eq") + +%def op_if_eqz(): +% zcmp(condition="eq") + +%def op_if_ge(): +% bincmp(condition="ge") + +%def op_if_gez(): +% zcmp(condition="ge") + +%def op_if_gt(): +% bincmp(condition="gt") + +%def op_if_gtz(): +% zcmp(condition="gt") + +%def op_if_le(): +% bincmp(condition="le") + +%def op_if_lez(): +% zcmp(condition="le") + +%def op_if_lt(): +% bincmp(condition="lt") + +%def op_if_ltz(): +% zcmp(condition="lt") + +%def op_if_ne(): +% bincmp(condition="ne") + +%def op_if_nez(): +% zcmp(condition="ne") + +%def op_packed_switch(func="MterpDoPackedSwitch"): + /* + * Handle a packed-switch or sparse-switch instruction. In both cases + * we decode it and hand it off to a helper function. + * + * We don't really expect backward branches in a switch statement, but + * they're perfectly legal, so we check for them here. + * + * for: packed-switch, sparse-switch + */ + /* op vAA, +BBBBBBBB */ + .extern $func + lh a0, 2(rPC) # a0 <- bbbb (lo) + lh a1, 4(rPC) # a1 <- BBBB (hi) + srl a3, rINST, 8 # a3 <- AA + ins a0, a1, 16, 16 # a0 <- BBBBbbbb + GET_VREG a1, a3 # a1 <- vAA + dlsa a0, a0, rPC, 1 # a0 <- PC + BBBBbbbb*2 + jal $func # v0 <- code-unit branch offset + move rINST, v0 + b MterpCommonTakenBranchNoFlags + +%def op_return(instr="GET_VREG"): + /* + * Return a 32-bit value. + * + * for: return (sign-extend), return-object (zero-extend) + */ + /* op vAA */ + .extern MterpThreadFenceForConstructor + .extern MterpSuspendCheck + jal MterpThreadFenceForConstructor + lw ra, THREAD_FLAGS_OFFSET(rSELF) + move a0, rSELF + and ra, ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST + beqzc ra, 1f + jal MterpSuspendCheck # (self) +1: + srl a2, rINST, 8 # a2 <- AA + $instr a0, a2 # a0 <- vAA + b MterpReturn + +%def op_return_object(): +% op_return(instr="GET_VREG_U") + +%def op_return_void(): + .extern MterpThreadFenceForConstructor + .extern MterpSuspendCheck + jal MterpThreadFenceForConstructor + lw ra, THREAD_FLAGS_OFFSET(rSELF) + move a0, rSELF + and ra, ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST + beqzc ra, 1f + jal MterpSuspendCheck # (self) +1: + li a0, 0 + b MterpReturn + +%def op_return_void_no_barrier(): + .extern MterpSuspendCheck + lw ra, THREAD_FLAGS_OFFSET(rSELF) + move a0, rSELF + and ra, ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST + beqzc ra, 1f + jal MterpSuspendCheck # (self) +1: + li a0, 0 + b MterpReturn + +%def op_return_wide(): + /* + * Return a 64-bit value. + */ + /* return-wide vAA */ + /* op vAA */ + .extern MterpThreadFenceForConstructor + .extern MterpSuspendCheck + jal MterpThreadFenceForConstructor + lw ra, THREAD_FLAGS_OFFSET(rSELF) + move a0, rSELF + and ra, ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST + beqzc ra, 1f + jal MterpSuspendCheck # (self) +1: + srl a2, rINST, 8 # a2 <- AA + GET_VREG_WIDE a0, a2 # a0 <- vAA + b MterpReturn + +%def op_sparse_switch(): +% op_packed_switch(func="MterpDoSparseSwitch") + +%def op_throw(): + /* + * Throw an exception object in the current thread. + */ + /* throw vAA */ + EXPORT_PC + srl a2, rINST, 8 # a2 <- AA + GET_VREG_U a0, a2 # a0 <- vAA (exception object) + beqzc a0, common_errNullObject + sd a0, THREAD_EXCEPTION_OFFSET(rSELF) # thread->exception <- obj + b MterpException diff --git a/runtime/interpreter/mterp/mips64/entry.S b/runtime/interpreter/mterp/mips64/entry.S deleted file mode 100644 index 0c64137fa8..0000000000 --- a/runtime/interpreter/mterp/mips64/entry.S +++ /dev/null @@ -1,95 +0,0 @@ -%def entry(): -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * Interpreter entry point. - */ - - .set reorder - - .text - .global ExecuteMterpImpl - .type ExecuteMterpImpl, %function - .balign 16 -/* - * On entry: - * a0 Thread* self - * a1 dex_instructions - * a2 ShadowFrame - * a3 JValue* result_register - * - */ -ExecuteMterpImpl: - .cfi_startproc - .cpsetup t9, t8, ExecuteMterpImpl - - .cfi_def_cfa sp, 0 - daddu sp, sp, -STACK_SIZE - .cfi_adjust_cfa_offset STACK_SIZE - - sd t8, STACK_OFFSET_GP(sp) - .cfi_rel_offset 28, STACK_OFFSET_GP - sd ra, STACK_OFFSET_RA(sp) - .cfi_rel_offset 31, STACK_OFFSET_RA - - sd s0, STACK_OFFSET_S0(sp) - .cfi_rel_offset 16, STACK_OFFSET_S0 - sd s1, STACK_OFFSET_S1(sp) - .cfi_rel_offset 17, STACK_OFFSET_S1 - sd s2, STACK_OFFSET_S2(sp) - .cfi_rel_offset 18, STACK_OFFSET_S2 - sd s3, STACK_OFFSET_S3(sp) - .cfi_rel_offset 19, STACK_OFFSET_S3 - sd s4, STACK_OFFSET_S4(sp) - .cfi_rel_offset 20, STACK_OFFSET_S4 - sd s5, STACK_OFFSET_S5(sp) - .cfi_rel_offset 21, STACK_OFFSET_S5 - sd s6, STACK_OFFSET_S6(sp) - .cfi_rel_offset 22, STACK_OFFSET_S6 - - /* Remember the return register */ - sd a3, SHADOWFRAME_RESULT_REGISTER_OFFSET(a2) - - /* Remember the dex instruction pointer */ - sd a1, SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET(a2) - - /* set up "named" registers */ - move rSELF, a0 - daddu rFP, a2, SHADOWFRAME_VREGS_OFFSET - lw v0, SHADOWFRAME_NUMBER_OF_VREGS_OFFSET(a2) - dlsa rREFS, v0, rFP, 2 - lw v0, SHADOWFRAME_DEX_PC_OFFSET(a2) - dlsa rPC, v0, a1, 1 - CFI_DEFINE_DEX_PC_WITH_OFFSET(CFI_TMP, CFI_DEX, 0) - EXPORT_PC - - /* Starting ibase */ - REFRESH_IBASE - - /* Set up for backwards branches & osr profiling */ - ld a0, OFF_FP_METHOD(rFP) - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rSELF - jal MterpSetUpHotnessCountdown - move rPROFILE, v0 # Starting hotness countdown to rPROFILE - - /* start executing the instruction at rPC */ - FETCH_INST - GET_INST_OPCODE v0 - GOTO_OPCODE v0 - - /* NOTE: no fallthrough */ diff --git a/runtime/interpreter/mterp/mips64/fallback.S b/runtime/interpreter/mterp/mips64/fallback.S deleted file mode 100644 index 71abfeb23d..0000000000 --- a/runtime/interpreter/mterp/mips64/fallback.S +++ /dev/null @@ -1,3 +0,0 @@ -%def fallback(): -/* Transfer stub to alternate interpreter */ - b MterpFallback diff --git a/runtime/interpreter/mterp/mips64/fbinop.S b/runtime/interpreter/mterp/mips64/fbinop.S deleted file mode 100644 index 5090528201..0000000000 --- a/runtime/interpreter/mterp/mips64/fbinop.S +++ /dev/null @@ -1,18 +0,0 @@ -%def fbinop(instr=""): - /*: - * Generic 32-bit floating-point operation. - * - * For: add-float, sub-float, mul-float, div-float. - * form: f0, f0, f1 - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_FLOAT f0, a2 # f0 <- vBB - GET_VREG_FLOAT f1, a3 # f1 <- vCC - $instr # f0 <- f0 op f1 - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_FLOAT f0, a4 # vAA <- f0 - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/fbinop2addr.S b/runtime/interpreter/mterp/mips64/fbinop2addr.S deleted file mode 100644 index fe5ad2bec4..0000000000 --- a/runtime/interpreter/mterp/mips64/fbinop2addr.S +++ /dev/null @@ -1,17 +0,0 @@ -%def fbinop2addr(instr=""): - /*: - * Generic 32-bit "/2addr" floating-point operation. - * - * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr. - * form: f0, f0, f1 - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_FLOAT f0, a2 # f0 <- vA - GET_VREG_FLOAT f1, a3 # f1 <- vB - $instr # f0 <- f0 op f1 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_FLOAT f0, a2 # vA <- f0 - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/fbinopWide.S b/runtime/interpreter/mterp/mips64/fbinopWide.S deleted file mode 100644 index ca7765bb82..0000000000 --- a/runtime/interpreter/mterp/mips64/fbinopWide.S +++ /dev/null @@ -1,18 +0,0 @@ -%def fbinopWide(instr=""): - /*: - * Generic 64-bit floating-point operation. - * - * For: add-double, sub-double, mul-double, div-double. - * form: f0, f0, f1 - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_DOUBLE f0, a2 # f0 <- vBB - GET_VREG_DOUBLE f1, a3 # f1 <- vCC - $instr # f0 <- f0 op f1 - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_DOUBLE f0, a4 # vAA <- f0 - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/fbinopWide2addr.S b/runtime/interpreter/mterp/mips64/fbinopWide2addr.S deleted file mode 100644 index a4dfd4c793..0000000000 --- a/runtime/interpreter/mterp/mips64/fbinopWide2addr.S +++ /dev/null @@ -1,17 +0,0 @@ -%def fbinopWide2addr(instr=""): - /*: - * Generic 64-bit "/2addr" floating-point operation. - * - * For: add-double/2addr, sub-double/2addr, mul-double/2addr, div-double/2addr. - * form: f0, f0, f1 - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_DOUBLE f0, a2 # f0 <- vA - GET_VREG_DOUBLE f1, a3 # f1 <- vB - $instr # f0 <- f0 op f1 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_DOUBLE f0, a2 # vA <- f0 - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/fcmp.S b/runtime/interpreter/mterp/mips64/fcmp.S deleted file mode 100644 index bc40f9627e..0000000000 --- a/runtime/interpreter/mterp/mips64/fcmp.S +++ /dev/null @@ -1,32 +0,0 @@ -%def fcmp(gt_bias=""): - /* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * For: cmpl-float, cmpg-float - */ - /* op vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_FLOAT f0, a2 # f0 <- vBB - GET_VREG_FLOAT f1, a3 # f1 <- vCC - cmp.eq.s f2, f0, f1 - li a0, 0 - bc1nez f2, 1f # done if vBB == vCC (ordered) - .if $gt_bias - cmp.lt.s f2, f0, f1 - li a0, -1 - bc1nez f2, 1f # done if vBB < vCC (ordered) - li a0, 1 # vBB > vCC or unordered - .else - cmp.lt.s f2, f1, f0 - li a0, 1 - bc1nez f2, 1f # done if vBB > vCC (ordered) - li a0, -1 # vBB < vCC or unordered - .endif -1: - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/fcmpWide.S b/runtime/interpreter/mterp/mips64/fcmpWide.S deleted file mode 100644 index 05f33e6afa..0000000000 --- a/runtime/interpreter/mterp/mips64/fcmpWide.S +++ /dev/null @@ -1,32 +0,0 @@ -%def fcmpWide(gt_bias=""): - /* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * For: cmpl-double, cmpg-double - */ - /* op vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_DOUBLE f0, a2 # f0 <- vBB - GET_VREG_DOUBLE f1, a3 # f1 <- vCC - cmp.eq.d f2, f0, f1 - li a0, 0 - bc1nez f2, 1f # done if vBB == vCC (ordered) - .if $gt_bias - cmp.lt.d f2, f0, f1 - li a0, -1 - bc1nez f2, 1f # done if vBB < vCC (ordered) - li a0, 1 # vBB > vCC or unordered - .else - cmp.lt.d f2, f1, f0 - li a0, 1 - bc1nez f2, 1f # done if vBB > vCC (ordered) - li a0, -1 # vBB < vCC or unordered - .endif -1: - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/fcvtFooter.S b/runtime/interpreter/mterp/mips64/fcvtFooter.S deleted file mode 100644 index 711f3f3e25..0000000000 --- a/runtime/interpreter/mterp/mips64/fcvtFooter.S +++ /dev/null @@ -1,19 +0,0 @@ -%def fcvtFooter(suffix="", valreg=""): - /* - * Stores a specified register containing the result of conversion - * from or to a floating-point type and jumps to the next instruction. - * - * Expects a1 to contain the destination Dalvik register number. - * a1 is set up by fcvtHeader.S. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - * - * Note that this file can't be included after a break in other files - * and in those files its contents appear as a copy. - * See: float-to-int, float-to-long, double-to-int, double-to-long. - */ - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG$suffix $valreg, a1 - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/fcvtHeader.S b/runtime/interpreter/mterp/mips64/fcvtHeader.S deleted file mode 100644 index 688b6be0f7..0000000000 --- a/runtime/interpreter/mterp/mips64/fcvtHeader.S +++ /dev/null @@ -1,16 +0,0 @@ -%def fcvtHeader(suffix="", valreg=""): - /* - * Loads a specified register from vB. Used primarily for conversions - * from or to a floating-point type. - * - * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to - * store the result in vA and jump to the next instruction. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - */ - ext a1, rINST, 8, 4 # a1 <- A - srl a2, rINST, 12 # a2 <- B - GET_VREG$suffix $valreg, a2 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST diff --git a/runtime/interpreter/mterp/mips64/field.S b/runtime/interpreter/mterp/mips64/field.S deleted file mode 100644 index d61b06afd4..0000000000 --- a/runtime/interpreter/mterp/mips64/field.S +++ /dev/null @@ -1,2 +0,0 @@ -%def field(helper=""): -TODO diff --git a/runtime/interpreter/mterp/mips64/floating_point.S b/runtime/interpreter/mterp/mips64/floating_point.S new file mode 100644 index 0000000000..1132a09e7c --- /dev/null +++ b/runtime/interpreter/mterp/mips64/floating_point.S @@ -0,0 +1,382 @@ +%def fbinop(instr=""): + /*: + * Generic 32-bit floating-point operation. + * + * For: add-float, sub-float, mul-float, div-float. + * form: f0, f0, f1 + */ + /* binop vAA, vBB, vCC */ + srl a4, rINST, 8 # a4 <- AA + lbu a2, 2(rPC) # a2 <- BB + lbu a3, 3(rPC) # a3 <- CC + GET_VREG_FLOAT f0, a2 # f0 <- vBB + GET_VREG_FLOAT f1, a3 # f1 <- vCC + $instr # f0 <- f0 op f1 + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG_FLOAT f0, a4 # vAA <- f0 + GOTO_OPCODE v0 # jump to next instruction + +%def fbinop2addr(instr=""): + /*: + * Generic 32-bit "/2addr" floating-point operation. + * + * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr. + * form: f0, f0, f1 + */ + /* binop/2addr vA, vB */ + ext a2, rINST, 8, 4 # a2 <- A + ext a3, rINST, 12, 4 # a3 <- B + GET_VREG_FLOAT f0, a2 # f0 <- vA + GET_VREG_FLOAT f1, a3 # f1 <- vB + $instr # f0 <- f0 op f1 + FETCH_ADVANCE_INST 1 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG_FLOAT f0, a2 # vA <- f0 + GOTO_OPCODE v0 # jump to next instruction + +%def fbinopWide(instr=""): + /*: + * Generic 64-bit floating-point operation. + * + * For: add-double, sub-double, mul-double, div-double. + * form: f0, f0, f1 + */ + /* binop vAA, vBB, vCC */ + srl a4, rINST, 8 # a4 <- AA + lbu a2, 2(rPC) # a2 <- BB + lbu a3, 3(rPC) # a3 <- CC + GET_VREG_DOUBLE f0, a2 # f0 <- vBB + GET_VREG_DOUBLE f1, a3 # f1 <- vCC + $instr # f0 <- f0 op f1 + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG_DOUBLE f0, a4 # vAA <- f0 + GOTO_OPCODE v0 # jump to next instruction + +%def fbinopWide2addr(instr=""): + /*: + * Generic 64-bit "/2addr" floating-point operation. + * + * For: add-double/2addr, sub-double/2addr, mul-double/2addr, div-double/2addr. + * form: f0, f0, f1 + */ + /* binop/2addr vA, vB */ + ext a2, rINST, 8, 4 # a2 <- A + ext a3, rINST, 12, 4 # a3 <- B + GET_VREG_DOUBLE f0, a2 # f0 <- vA + GET_VREG_DOUBLE f1, a3 # f1 <- vB + $instr # f0 <- f0 op f1 + FETCH_ADVANCE_INST 1 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG_DOUBLE f0, a2 # vA <- f0 + GOTO_OPCODE v0 # jump to next instruction + +%def fcmp(gt_bias=""): + /* + * Compare two floating-point values. Puts 0, 1, or -1 into the + * destination register based on the results of the comparison. + * + * For: cmpl-float, cmpg-float + */ + /* op vAA, vBB, vCC */ + srl a4, rINST, 8 # a4 <- AA + lbu a2, 2(rPC) # a2 <- BB + lbu a3, 3(rPC) # a3 <- CC + GET_VREG_FLOAT f0, a2 # f0 <- vBB + GET_VREG_FLOAT f1, a3 # f1 <- vCC + cmp.eq.s f2, f0, f1 + li a0, 0 + bc1nez f2, 1f # done if vBB == vCC (ordered) + .if $gt_bias + cmp.lt.s f2, f0, f1 + li a0, -1 + bc1nez f2, 1f # done if vBB < vCC (ordered) + li a0, 1 # vBB > vCC or unordered + .else + cmp.lt.s f2, f1, f0 + li a0, 1 + bc1nez f2, 1f # done if vBB > vCC (ordered) + li a0, -1 # vBB < vCC or unordered + .endif +1: + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG a0, a4 # vAA <- a0 + GOTO_OPCODE v0 # jump to next instruction + +%def fcmpWide(gt_bias=""): + /* + * Compare two floating-point values. Puts 0, 1, or -1 into the + * destination register based on the results of the comparison. + * + * For: cmpl-double, cmpg-double + */ + /* op vAA, vBB, vCC */ + srl a4, rINST, 8 # a4 <- AA + lbu a2, 2(rPC) # a2 <- BB + lbu a3, 3(rPC) # a3 <- CC + GET_VREG_DOUBLE f0, a2 # f0 <- vBB + GET_VREG_DOUBLE f1, a3 # f1 <- vCC + cmp.eq.d f2, f0, f1 + li a0, 0 + bc1nez f2, 1f # done if vBB == vCC (ordered) + .if $gt_bias + cmp.lt.d f2, f0, f1 + li a0, -1 + bc1nez f2, 1f # done if vBB < vCC (ordered) + li a0, 1 # vBB > vCC or unordered + .else + cmp.lt.d f2, f1, f0 + li a0, 1 + bc1nez f2, 1f # done if vBB > vCC (ordered) + li a0, -1 # vBB < vCC or unordered + .endif +1: + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG a0, a4 # vAA <- a0 + GOTO_OPCODE v0 # jump to next instruction + +%def fcvtFooter(suffix="", valreg=""): + /* + * Stores a specified register containing the result of conversion + * from or to a floating-point type and jumps to the next instruction. + * + * Expects a1 to contain the destination Dalvik register number. + * a1 is set up by fcvtHeader.S. + * + * For: int-to-float, int-to-double, long-to-float, long-to-double, + * float-to-int, float-to-long, float-to-double, double-to-int, + * double-to-long, double-to-float, neg-float, neg-double. + * + * Note that this file can't be included after a break in other files + * and in those files its contents appear as a copy. + * See: float-to-int, float-to-long, double-to-int, double-to-long. + */ + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG$suffix $valreg, a1 + GOTO_OPCODE v0 # jump to next instruction + +%def fcvtHeader(suffix="", valreg=""): + /* + * Loads a specified register from vB. Used primarily for conversions + * from or to a floating-point type. + * + * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to + * store the result in vA and jump to the next instruction. + * + * For: int-to-float, int-to-double, long-to-float, long-to-double, + * float-to-int, float-to-long, float-to-double, double-to-int, + * double-to-long, double-to-float, neg-float, neg-double. + */ + ext a1, rINST, 8, 4 # a1 <- A + srl a2, rINST, 12 # a2 <- B + GET_VREG$suffix $valreg, a2 + FETCH_ADVANCE_INST 1 # advance rPC, load rINST + +%def op_add_double(): +% fbinopWide(instr="add.d f0, f0, f1") + +%def op_add_double_2addr(): +% fbinopWide2addr(instr="add.d f0, f0, f1") + +%def op_add_float(): +% fbinop(instr="add.s f0, f0, f1") + +%def op_add_float_2addr(): +% fbinop2addr(instr="add.s f0, f0, f1") + +%def op_cmpg_double(): +% fcmpWide(gt_bias="1") + +%def op_cmpg_float(): +% fcmp(gt_bias="1") + +%def op_cmpl_double(): +% fcmpWide(gt_bias="0") + +%def op_cmpl_float(): +% fcmp(gt_bias="0") + +%def op_div_double(): +% fbinopWide(instr="div.d f0, f0, f1") + +%def op_div_double_2addr(): +% fbinopWide2addr(instr="div.d f0, f0, f1") + +%def op_div_float(): +% fbinop(instr="div.s f0, f0, f1") + +%def op_div_float_2addr(): +% fbinop2addr(instr="div.s f0, f0, f1") + +%def op_double_to_float(): + /* + * Conversion from or to floating-point happens in a floating-point register. + * Therefore we load the input and store the output into or from a + * floating-point register irrespective of the type. + */ +% fcvtHeader(suffix="_DOUBLE", valreg="f0") + cvt.s.d f0, f0 +% fcvtFooter(suffix="_FLOAT", valreg="f0") + +%def op_double_to_int(): +% fcvtHeader(suffix="_DOUBLE", valreg="f0") + trunc.w.d f0, f0 +% fcvtFooter(suffix="_FLOAT", valreg="f0") + +%def op_double_to_long(): +% fcvtHeader(suffix="_DOUBLE", valreg="f0") + trunc.l.d f0, f0 +% fcvtFooter(suffix="_DOUBLE", valreg="f0") + +%def op_float_to_double(): + /* + * Conversion from or to floating-point happens in a floating-point register. + * Therefore we load the input and store the output into or from a + * floating-point register irrespective of the type. + */ +% fcvtHeader(suffix="_FLOAT", valreg="f0") + cvt.d.s f0, f0 +% fcvtFooter(suffix="_DOUBLE", valreg="f0") + +%def op_float_to_int(): +% fcvtHeader(suffix="_FLOAT", valreg="f0") + trunc.w.s f0, f0 +% fcvtFooter(suffix="_FLOAT", valreg="f0") + +%def op_float_to_long(): +% fcvtHeader(suffix="_FLOAT", valreg="f0") + trunc.l.s f0, f0 +% fcvtFooter(suffix="_DOUBLE", valreg="f0") + +%def op_int_to_double(): + /* + * Conversion from or to floating-point happens in a floating-point register. + * Therefore we load the input and store the output into or from a + * floating-point register irrespective of the type. + */ +% fcvtHeader(suffix="_FLOAT", valreg="f0") + cvt.d.w f0, f0 +% fcvtFooter(suffix="_DOUBLE", valreg="f0") + +%def op_int_to_float(): + /* + * Conversion from or to floating-point happens in a floating-point register. + * Therefore we load the input and store the output into or from a + * floating-point register irrespective of the type. + */ +% fcvtHeader(suffix="_FLOAT", valreg="f0") + cvt.s.w f0, f0 +% fcvtFooter(suffix="_FLOAT", valreg="f0") + +%def op_long_to_double(): + /* + * Conversion from or to floating-point happens in a floating-point register. + * Therefore we load the input and store the output into or from a + * floating-point register irrespective of the type. + */ +% fcvtHeader(suffix="_DOUBLE", valreg="f0") + cvt.d.l f0, f0 +% fcvtFooter(suffix="_DOUBLE", valreg="f0") + +%def op_long_to_float(): + /* + * Conversion from or to floating-point happens in a floating-point register. + * Therefore we load the input and store the output into or from a + * floating-point register irrespective of the type. + */ +% fcvtHeader(suffix="_DOUBLE", valreg="f0") + cvt.s.l f0, f0 +% fcvtFooter(suffix="_FLOAT", valreg="f0") + +%def op_mul_double(): +% fbinopWide(instr="mul.d f0, f0, f1") + +%def op_mul_double_2addr(): +% fbinopWide2addr(instr="mul.d f0, f0, f1") + +%def op_mul_float(): +% fbinop(instr="mul.s f0, f0, f1") + +%def op_mul_float_2addr(): +% fbinop2addr(instr="mul.s f0, f0, f1") + +%def op_neg_double(): +% fcvtHeader(suffix="_DOUBLE", valreg="f0") + neg.d f0, f0 +% fcvtFooter(suffix="_DOUBLE", valreg="f0") + +%def op_neg_float(): +% fcvtHeader(suffix="_FLOAT", valreg="f0") + neg.s f0, f0 +% fcvtFooter(suffix="_FLOAT", valreg="f0") + +%def op_rem_double(): + /* rem-double vAA, vBB, vCC */ + .extern fmod + lbu a2, 2(rPC) # a2 <- BB + lbu a3, 3(rPC) # a3 <- CC + GET_VREG_DOUBLE f12, a2 # f12 <- vBB + GET_VREG_DOUBLE f13, a3 # f13 <- vCC + jal fmod # f0 <- f12 op f13 + srl a4, rINST, 8 # a4 <- AA + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG_DOUBLE f0, a4 # vAA <- f0 + GOTO_OPCODE v0 # jump to next instruction + +%def op_rem_double_2addr(): + /* rem-double/2addr vA, vB */ + .extern fmod + ext a2, rINST, 8, 4 # a2 <- A + ext a3, rINST, 12, 4 # a3 <- B + GET_VREG_DOUBLE f12, a2 # f12 <- vA + GET_VREG_DOUBLE f13, a3 # f13 <- vB + jal fmod # f0 <- f12 op f13 + ext a2, rINST, 8, 4 # a2 <- A + FETCH_ADVANCE_INST 1 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG_DOUBLE f0, a2 # vA <- f0 + GOTO_OPCODE v0 # jump to next instruction + +%def op_rem_float(): + /* rem-float vAA, vBB, vCC */ + .extern fmodf + lbu a2, 2(rPC) # a2 <- BB + lbu a3, 3(rPC) # a3 <- CC + GET_VREG_FLOAT f12, a2 # f12 <- vBB + GET_VREG_FLOAT f13, a3 # f13 <- vCC + jal fmodf # f0 <- f12 op f13 + srl a4, rINST, 8 # a4 <- AA + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG_FLOAT f0, a4 # vAA <- f0 + GOTO_OPCODE v0 # jump to next instruction + +%def op_rem_float_2addr(): + /* rem-float/2addr vA, vB */ + .extern fmodf + ext a2, rINST, 8, 4 # a2 <- A + ext a3, rINST, 12, 4 # a3 <- B + GET_VREG_FLOAT f12, a2 # f12 <- vA + GET_VREG_FLOAT f13, a3 # f13 <- vB + jal fmodf # f0 <- f12 op f13 + ext a2, rINST, 8, 4 # a2 <- A + FETCH_ADVANCE_INST 1 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG_FLOAT f0, a2 # vA <- f0 + GOTO_OPCODE v0 # jump to next instruction + +%def op_sub_double(): +% fbinopWide(instr="sub.d f0, f0, f1") + +%def op_sub_double_2addr(): +% fbinopWide2addr(instr="sub.d f0, f0, f1") + +%def op_sub_float(): +% fbinop(instr="sub.s f0, f0, f1") + +%def op_sub_float_2addr(): +% fbinop2addr(instr="sub.s f0, f0, f1") diff --git a/runtime/interpreter/mterp/mips64/footer.S b/runtime/interpreter/mterp/mips64/footer.S deleted file mode 100644 index 5673151f1c..0000000000 --- a/runtime/interpreter/mterp/mips64/footer.S +++ /dev/null @@ -1,277 +0,0 @@ -%def footer(): -/* - * We've detected a condition that will result in an exception, but the exception - * has not yet been thrown. Just bail out to the reference interpreter to deal with it. - * TUNING: for consistency, we may want to just go ahead and handle these here. - */ - - .extern MterpLogDivideByZeroException -common_errDivideByZero: - EXPORT_PC -#if MTERP_LOGGING - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - jal MterpLogDivideByZeroException -#endif - b MterpCommonFallback - - .extern MterpLogArrayIndexException -common_errArrayIndex: - EXPORT_PC -#if MTERP_LOGGING - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - jal MterpLogArrayIndexException -#endif - b MterpCommonFallback - - .extern MterpLogNullObjectException -common_errNullObject: - EXPORT_PC -#if MTERP_LOGGING - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - jal MterpLogNullObjectException -#endif - b MterpCommonFallback - -/* - * If we're here, something is out of the ordinary. If there is a pending - * exception, handle it. Otherwise, roll back and retry with the reference - * interpreter. - */ -MterpPossibleException: - ld a0, THREAD_EXCEPTION_OFFSET(rSELF) - beqzc a0, MterpFallback # If not, fall back to reference interpreter. - /* intentional fallthrough - handle pending exception. */ -/* - * On return from a runtime helper routine, we've found a pending exception. - * Can we handle it here - or need to bail out to caller? - * - */ - .extern MterpHandleException - .extern MterpShouldSwitchInterpreters -MterpException: - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - jal MterpHandleException # (self, shadow_frame) - beqzc v0, MterpExceptionReturn # no local catch, back to caller. - ld a0, OFF_FP_DEX_INSTRUCTIONS(rFP) - lwu a1, OFF_FP_DEX_PC(rFP) - REFRESH_IBASE - dlsa rPC, a1, a0, 1 # generate new dex_pc_ptr - /* Do we need to switch interpreters? */ - jal MterpShouldSwitchInterpreters - bnezc v0, MterpFallback - /* resume execution at catch block */ - EXPORT_PC - FETCH_INST - GET_INST_OPCODE v0 - GOTO_OPCODE v0 - /* NOTE: no fallthrough */ - -/* - * Common handling for branches with support for Jit profiling. - * On entry: - * rINST <= signed offset - * rPROFILE <= signed hotness countdown (expanded to 64 bits) - * - * We have quite a few different cases for branch profiling, OSR detection and - * suspend check support here. - * - * Taken backward branches: - * If profiling active, do hotness countdown and report if we hit zero. - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * Is there a pending suspend request? If so, suspend. - * - * Taken forward branches and not-taken backward branches: - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * - * Our most common case is expected to be a taken backward branch with active jit profiling, - * but no full OSR check and no pending suspend request. - * Next most common case is not-taken branch with no full OSR check. - * - */ -MterpCommonTakenBranchNoFlags: - bgtzc rINST, .L_forward_branch # don't add forward branches to hotness -/* - * We need to subtract 1 from positive values and we should not see 0 here, - * so we may use the result of the comparison with -1. - */ - li v0, JIT_CHECK_OSR - beqc rPROFILE, v0, .L_osr_check - bltc rPROFILE, v0, .L_resume_backward_branch - dsubu rPROFILE, 1 - beqzc rPROFILE, .L_add_batch # counted down to zero - report -.L_resume_backward_branch: - lw ra, THREAD_FLAGS_OFFSET(rSELF) - REFRESH_IBASE - daddu a2, rINST, rINST # a2<- byte offset - FETCH_ADVANCE_INST_RB a2 # update rPC, load rINST - and ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - bnezc ra, .L_suspend_request_pending - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -.L_suspend_request_pending: - EXPORT_PC - move a0, rSELF - jal MterpSuspendCheck # (self) - bnezc v0, MterpFallback - REFRESH_IBASE # might have changed during suspend - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -.L_no_count_backwards: - li v0, JIT_CHECK_OSR # check for possible OSR re-entry - bnec rPROFILE, v0, .L_resume_backward_branch -.L_osr_check: - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rINST - EXPORT_PC - jal MterpMaybeDoOnStackReplacement # (self, shadow_frame, offset) - bnezc v0, MterpOnStackReplacement - b .L_resume_backward_branch - -.L_forward_branch: - li v0, JIT_CHECK_OSR # check for possible OSR re-entry - beqc rPROFILE, v0, .L_check_osr_forward -.L_resume_forward_branch: - daddu a2, rINST, rINST # a2<- byte offset - FETCH_ADVANCE_INST_RB a2 # update rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -.L_check_osr_forward: - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rINST - EXPORT_PC - jal MterpMaybeDoOnStackReplacement # (self, shadow_frame, offset) - bnezc v0, MterpOnStackReplacement - b .L_resume_forward_branch - -.L_add_batch: - daddu a1, rFP, OFF_FP_SHADOWFRAME - sh rPROFILE, SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET(a1) - ld a0, OFF_FP_METHOD(rFP) - move a2, rSELF - jal MterpAddHotnessBatch # (method, shadow_frame, self) - move rPROFILE, v0 # restore new hotness countdown to rPROFILE - b .L_no_count_backwards - -/* - * Entered from the conditional branch handlers when OSR check request active on - * not-taken path. All Dalvik not-taken conditional branch offsets are 2. - */ -.L_check_not_taken_osr: - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - li a2, 2 - EXPORT_PC - jal MterpMaybeDoOnStackReplacement # (self, shadow_frame, offset) - bnezc v0, MterpOnStackReplacement - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* - * On-stack replacement has happened, and now we've returned from the compiled method. - */ -MterpOnStackReplacement: -#if MTERP_LOGGING - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rINST # rINST contains offset - jal MterpLogOSR -#endif - li v0, 1 # Signal normal return - b MterpDone - -/* - * Bail out to reference interpreter. - */ - .extern MterpLogFallback -MterpFallback: - EXPORT_PC -#if MTERP_LOGGING - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - jal MterpLogFallback -#endif -MterpCommonFallback: - li v0, 0 # signal retry with reference interpreter. - b MterpDone - -/* - * We pushed some registers on the stack in ExecuteMterpImpl, then saved - * SP and RA. Here we restore SP, restore the registers, and then restore - * RA to PC. - * - * On entry: - * uint32_t* rFP (should still be live, pointer to base of vregs) - */ -MterpExceptionReturn: - li v0, 1 # signal return to caller. - b MterpDone -/* - * Returned value is expected in a0 and if it's not 64-bit, the 32 most - * significant bits of a0 must be zero-extended or sign-extended - * depending on the return type. - */ -MterpReturn: - ld a2, OFF_FP_RESULT_REGISTER(rFP) - sd a0, 0(a2) - li v0, 1 # signal return to caller. -MterpDone: -/* - * At this point, we expect rPROFILE to be non-zero. If negative, hotness is disabled or we're - * checking for OSR. If greater than zero, we might have unreported hotness to register - * (the difference between the ending rPROFILE and the cached hotness counter). rPROFILE - * should only reach zero immediately after a hotness decrement, and is then reset to either - * a negative special state or the new non-zero countdown value. - */ - blez rPROFILE, .L_pop_and_return # if > 0, we may have some counts to report. - -MterpProfileActive: - move rINST, v0 # stash return value - /* Report cached hotness counts */ - ld a0, OFF_FP_METHOD(rFP) - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rSELF - sh rPROFILE, SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET(a1) - jal MterpAddHotnessBatch # (method, shadow_frame, self) - move v0, rINST # restore return value - -.L_pop_and_return: - ld s6, STACK_OFFSET_S6(sp) - .cfi_restore 22 - ld s5, STACK_OFFSET_S5(sp) - .cfi_restore 21 - ld s4, STACK_OFFSET_S4(sp) - .cfi_restore 20 - ld s3, STACK_OFFSET_S3(sp) - .cfi_restore 19 - ld s2, STACK_OFFSET_S2(sp) - .cfi_restore 18 - ld s1, STACK_OFFSET_S1(sp) - .cfi_restore 17 - ld s0, STACK_OFFSET_S0(sp) - .cfi_restore 16 - - ld ra, STACK_OFFSET_RA(sp) - .cfi_restore 31 - - ld t8, STACK_OFFSET_GP(sp) - .cpreturn - .cfi_restore 28 - - .set noreorder - jr ra - daddu sp, sp, STACK_SIZE - .cfi_adjust_cfa_offset -STACK_SIZE - - .cfi_endproc - .set reorder - .size ExecuteMterpImpl, .-ExecuteMterpImpl diff --git a/runtime/interpreter/mterp/mips64/header.S b/runtime/interpreter/mterp/mips64/header.S deleted file mode 100644 index 42c712654d..0000000000 --- a/runtime/interpreter/mterp/mips64/header.S +++ /dev/null @@ -1,329 +0,0 @@ -%def header(): -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#define zero $$0 /* always zero */ -#define AT $$at /* assembler temp */ -#define v0 $$2 /* return value */ -#define v1 $$3 -#define a0 $$4 /* argument registers */ -#define a1 $$5 -#define a2 $$6 -#define a3 $$7 -#define a4 $$8 /* expanded register arguments */ -#define a5 $$9 -#define a6 $$10 -#define a7 $$11 -#define ta0 $$8 /* alias */ -#define ta1 $$9 -#define ta2 $$10 -#define ta3 $$11 -#define t0 $$12 /* temp registers (not saved across subroutine calls) */ -#define t1 $$13 -#define t2 $$14 -#define t3 $$15 - -#define s0 $$16 /* saved across subroutine calls (callee saved) */ -#define s1 $$17 -#define s2 $$18 -#define s3 $$19 -#define s4 $$20 -#define s5 $$21 -#define s6 $$22 -#define s7 $$23 -#define t8 $$24 /* two more temp registers */ -#define t9 $$25 -#define k0 $$26 /* kernel temporary */ -#define k1 $$27 -#define gp $$28 /* global pointer */ -#define sp $$29 /* stack pointer */ -#define s8 $$30 /* one more callee saved */ -#define ra $$31 /* return address */ - -#define f0 $$f0 -#define f1 $$f1 -#define f2 $$f2 -#define f3 $$f3 -#define f12 $$f12 -#define f13 $$f13 - -/* - * It looks like the GNU assembler currently does not support the blec and bgtc - * idioms, which should translate into bgec and bltc respectively with swapped - * left and right register operands. - * TODO: remove these macros when the assembler is fixed. - */ -.macro blec lreg, rreg, target - bgec \rreg, \lreg, \target -.endm -.macro bgtc lreg, rreg, target - bltc \rreg, \lreg, \target -.endm - -/* -Mterp and MIPS64 notes: - -The following registers have fixed assignments: - - reg nick purpose - s0 rPC interpreted program counter, used for fetching instructions - s1 rFP interpreted frame pointer, used for accessing locals and args - s2 rSELF self (Thread) pointer - s3 rINST first 16-bit code unit of current instruction - s4 rIBASE interpreted instruction base pointer, used for computed goto - s5 rREFS base of object references in shadow frame (ideally, we'll get rid of this later). - s6 rPROFILE jit profile hotness countdown -*/ - -/* During bringup, we'll use the shadow frame model instead of rFP */ -/* single-purpose registers, given names for clarity */ -#define rPC s0 -#define CFI_DEX 16 // DWARF register number of the register holding dex-pc (s0). -#define CFI_TMP 4 // DWARF register number of the first argument register (a0). -#define rFP s1 -#define rSELF s2 -#define rINST s3 -#define rIBASE s4 -#define rREFS s5 -#define rPROFILE s6 - -/* - * This is a #include, not a %include, because we want the C pre-processor - * to expand the macros into assembler assignment statements. - */ -#include "asm_support.h" -#include "interpreter/cfi_asm_support.h" - -/* - * Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs. So, - * to access other shadow frame fields, we need to use a backwards offset. Define those here. - */ -#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) -#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) -#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) -#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) -#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) -#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) -#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) -#define OFF_FP_DEX_INSTRUCTIONS OFF_FP(SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET) -#define OFF_FP_SHADOWFRAME OFF_FP(0) - -#define MTERP_PROFILE_BRANCHES 1 -#define MTERP_LOGGING 0 - -/* - * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must - * be done *before* something throws. - * - * It's okay to do this more than once. - * - * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped - * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction - * offset into the code_items_[] array. For effiency, we will "export" the - * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC - * to convert to a dex pc when needed. - */ -.macro EXPORT_PC - sd rPC, OFF_FP_DEX_PC_PTR(rFP) -.endm - -/* - * Refresh handler table. - */ -.macro REFRESH_IBASE - ld rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) -.endm - -/* - * Fetch the next instruction from rPC into rINST. Does not advance rPC. - */ -.macro FETCH_INST - lhu rINST, 0(rPC) -.endm - -/* Advance rPC by some number of code units. */ -.macro ADVANCE count - daddu rPC, rPC, (\count) * 2 -.endm - -/* - * Fetch the next instruction from an offset specified by _reg and advance xPC. - * xPC to point to the next instruction. "_reg" must specify the distance - * in bytes, *not* 16-bit code units, and may be a signed value. Must not set flags. - * - */ -.macro FETCH_ADVANCE_INST_RB reg - daddu rPC, rPC, \reg - FETCH_INST -.endm - -/* - * Fetch the next instruction from the specified offset. Advances rPC - * to point to the next instruction. - * - * This must come AFTER anything that can throw an exception, or the - * exception catch may miss. (This also implies that it must come after - * EXPORT_PC.) - */ -.macro FETCH_ADVANCE_INST count - ADVANCE \count - FETCH_INST -.endm - -/* - * Similar to FETCH_ADVANCE_INST, but does not update rPC. Used to load - * rINST ahead of possible exception point. Be sure to manually advance rPC - * later. - */ -.macro PREFETCH_INST count - lhu rINST, ((\count) * 2)(rPC) -.endm - -/* - * Put the instruction's opcode field into the specified register. - */ -.macro GET_INST_OPCODE reg - and \reg, rINST, 255 -.endm - -/* - * Begin executing the opcode in _reg. - */ -.macro GOTO_OPCODE reg - .set noat - sll AT, \reg, 7 - daddu AT, rIBASE, AT - jic AT, 0 - .set at -.endm - -/* - * Get/set the 32-bit value from a Dalvik register. - * Note, GET_VREG does sign extension to 64 bits while - * GET_VREG_U does zero extension to 64 bits. - * One is useful for arithmetic while the other is - * useful for storing the result value as 64-bit. - */ -.macro GET_VREG reg, vreg - .set noat - dlsa AT, \vreg, rFP, 2 - lw \reg, 0(AT) - .set at -.endm -.macro GET_VREG_U reg, vreg - .set noat - dlsa AT, \vreg, rFP, 2 - lwu \reg, 0(AT) - .set at -.endm -.macro GET_VREG_FLOAT reg, vreg - .set noat - dlsa AT, \vreg, rFP, 2 - lwc1 \reg, 0(AT) - .set at -.endm -.macro SET_VREG reg, vreg - .set noat - dlsa AT, \vreg, rFP, 2 - sw \reg, 0(AT) - dlsa AT, \vreg, rREFS, 2 - sw zero, 0(AT) - .set at -.endm -.macro SET_VREG_OBJECT reg, vreg - .set noat - dlsa AT, \vreg, rFP, 2 - sw \reg, 0(AT) - dlsa AT, \vreg, rREFS, 2 - sw \reg, 0(AT) - .set at -.endm -.macro SET_VREG_FLOAT reg, vreg - .set noat - dlsa AT, \vreg, rFP, 2 - swc1 \reg, 0(AT) - dlsa AT, \vreg, rREFS, 2 - sw zero, 0(AT) - .set at -.endm - -/* - * Get/set the 64-bit value from a Dalvik register. - * Avoid unaligned memory accesses. - * Note, SET_VREG_WIDE clobbers the register containing the value being stored. - * Note, SET_VREG_DOUBLE clobbers the register containing the Dalvik register number. - */ -.macro GET_VREG_WIDE reg, vreg - .set noat - dlsa AT, \vreg, rFP, 2 - lw \reg, 0(AT) - lw AT, 4(AT) - dinsu \reg, AT, 32, 32 - .set at -.endm -.macro GET_VREG_DOUBLE reg, vreg - .set noat - dlsa AT, \vreg, rFP, 2 - lwc1 \reg, 0(AT) - lw AT, 4(AT) - mthc1 AT, \reg - .set at -.endm -.macro SET_VREG_WIDE reg, vreg - .set noat - dlsa AT, \vreg, rFP, 2 - sw \reg, 0(AT) - drotr32 \reg, \reg, 0 - sw \reg, 4(AT) - dlsa AT, \vreg, rREFS, 2 - sw zero, 0(AT) - sw zero, 4(AT) - .set at -.endm -.macro SET_VREG_DOUBLE reg, vreg - .set noat - dlsa AT, \vreg, rREFS, 2 - sw zero, 0(AT) - sw zero, 4(AT) - dlsa AT, \vreg, rFP, 2 - swc1 \reg, 0(AT) - mfhc1 \vreg, \reg - sw \vreg, 4(AT) - .set at -.endm - -/* - * On-stack offsets for spilling/unspilling callee-saved registers - * and the frame size. - */ -#define STACK_OFFSET_RA 0 -#define STACK_OFFSET_GP 8 -#define STACK_OFFSET_S0 16 -#define STACK_OFFSET_S1 24 -#define STACK_OFFSET_S2 32 -#define STACK_OFFSET_S3 40 -#define STACK_OFFSET_S4 48 -#define STACK_OFFSET_S5 56 -#define STACK_OFFSET_S6 64 -#define STACK_SIZE 80 /* needs 16 byte alignment */ - -/* Constants for float/double_to_int/long conversions */ -#define INT_MIN 0x80000000 -#define INT_MIN_AS_FLOAT 0xCF000000 -#define INT_MIN_AS_DOUBLE 0xC1E0000000000000 -#define LONG_MIN 0x8000000000000000 -#define LONG_MIN_AS_FLOAT 0xDF000000 -#define LONG_MIN_AS_DOUBLE 0xC3E0000000000000 diff --git a/runtime/interpreter/mterp/mips64/instruction_end.S b/runtime/interpreter/mterp/mips64/instruction_end.S deleted file mode 100644 index 3d4429365a..0000000000 --- a/runtime/interpreter/mterp/mips64/instruction_end.S +++ /dev/null @@ -1,4 +0,0 @@ -%def instruction_end(): - - .global artMterpAsmInstructionEnd -artMterpAsmInstructionEnd: diff --git a/runtime/interpreter/mterp/mips64/instruction_end_alt.S b/runtime/interpreter/mterp/mips64/instruction_end_alt.S deleted file mode 100644 index 86a1068f10..0000000000 --- a/runtime/interpreter/mterp/mips64/instruction_end_alt.S +++ /dev/null @@ -1,4 +0,0 @@ -%def instruction_end_alt(): - - .global artMterpAsmAltInstructionEnd -artMterpAsmAltInstructionEnd: diff --git a/runtime/interpreter/mterp/mips64/instruction_end_sister.S b/runtime/interpreter/mterp/mips64/instruction_end_sister.S deleted file mode 100644 index 8cc4513025..0000000000 --- a/runtime/interpreter/mterp/mips64/instruction_end_sister.S +++ /dev/null @@ -1,4 +0,0 @@ -%def instruction_end_sister(): - - .global artMterpAsmSisterEnd -artMterpAsmSisterEnd: diff --git a/runtime/interpreter/mterp/mips64/instruction_start.S b/runtime/interpreter/mterp/mips64/instruction_start.S deleted file mode 100644 index 4b777f2fd5..0000000000 --- a/runtime/interpreter/mterp/mips64/instruction_start.S +++ /dev/null @@ -1,5 +0,0 @@ -%def instruction_start(): - - .global artMterpAsmInstructionStart -artMterpAsmInstructionStart = .L_op_nop - .text diff --git a/runtime/interpreter/mterp/mips64/instruction_start_alt.S b/runtime/interpreter/mterp/mips64/instruction_start_alt.S deleted file mode 100644 index e7731b7505..0000000000 --- a/runtime/interpreter/mterp/mips64/instruction_start_alt.S +++ /dev/null @@ -1,5 +0,0 @@ -%def instruction_start_alt(): - - .global artMterpAsmAltInstructionStart -artMterpAsmAltInstructionStart = .L_ALT_op_nop - .text diff --git a/runtime/interpreter/mterp/mips64/instruction_start_sister.S b/runtime/interpreter/mterp/mips64/instruction_start_sister.S deleted file mode 100644 index e09ea90b8e..0000000000 --- a/runtime/interpreter/mterp/mips64/instruction_start_sister.S +++ /dev/null @@ -1,6 +0,0 @@ -%def instruction_start_sister(): - - .global artMterpAsmSisterStart - .text - .balign 4 -artMterpAsmSisterStart: diff --git a/runtime/interpreter/mterp/mips64/invoke.S b/runtime/interpreter/mterp/mips64/invoke.S index caf5698f52..c2967cfa17 100644 --- a/runtime/interpreter/mterp/mips64/invoke.S +++ b/runtime/interpreter/mterp/mips64/invoke.S @@ -18,3 +18,93 @@ bnezc v0, MterpFallback GET_INST_OPCODE v0 GOTO_OPCODE v0 + +%def invoke_polymorphic(helper="UndefinedInvokeHandler"): + /* + * invoke-polymorphic handler wrapper. + */ + /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ + /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ + .extern $helper + .extern MterpShouldSwitchInterpreters + EXPORT_PC + move a0, rSELF + daddu a1, rFP, OFF_FP_SHADOWFRAME + move a2, rPC + move a3, rINST + jal $helper + beqzc v0, MterpException + FETCH_ADVANCE_INST 4 + jal MterpShouldSwitchInterpreters + bnezc v0, MterpFallback + GET_INST_OPCODE v0 + GOTO_OPCODE v0 + +%def op_invoke_custom(): +% invoke(helper="MterpInvokeCustom") + +%def op_invoke_custom_range(): +% invoke(helper="MterpInvokeCustomRange") + +%def op_invoke_direct(): +% invoke(helper="MterpInvokeDirect") + +%def op_invoke_direct_range(): +% invoke(helper="MterpInvokeDirectRange") + +%def op_invoke_interface(): +% invoke(helper="MterpInvokeInterface") + /* + * Handle an interface method call. + * + * for: invoke-interface, invoke-interface/range + */ + /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ + /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ + +%def op_invoke_interface_range(): +% invoke(helper="MterpInvokeInterfaceRange") + +%def op_invoke_polymorphic(): +% invoke_polymorphic(helper="MterpInvokePolymorphic") + +%def op_invoke_polymorphic_range(): +% invoke_polymorphic(helper="MterpInvokePolymorphicRange") + +%def op_invoke_static(): +% invoke(helper="MterpInvokeStatic") + +%def op_invoke_static_range(): +% invoke(helper="MterpInvokeStaticRange") + +%def op_invoke_super(): +% invoke(helper="MterpInvokeSuper") + /* + * Handle a "super" method call. + * + * for: invoke-super, invoke-super/range + */ + /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ + /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ + +%def op_invoke_super_range(): +% invoke(helper="MterpInvokeSuperRange") + +%def op_invoke_virtual(): +% invoke(helper="MterpInvokeVirtual") + /* + * Handle a virtual method call. + * + * for: invoke-virtual, invoke-virtual/range + */ + /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ + /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ + +%def op_invoke_virtual_quick(): +% invoke(helper="MterpInvokeVirtualQuick") + +%def op_invoke_virtual_range(): +% invoke(helper="MterpInvokeVirtualRange") + +%def op_invoke_virtual_range_quick(): +% invoke(helper="MterpInvokeVirtualQuickRange") diff --git a/runtime/interpreter/mterp/mips64/invoke_polymorphic.S b/runtime/interpreter/mterp/mips64/invoke_polymorphic.S deleted file mode 100644 index 3a10554b66..0000000000 --- a/runtime/interpreter/mterp/mips64/invoke_polymorphic.S +++ /dev/null @@ -1,20 +0,0 @@ -%def invoke_polymorphic(helper="UndefinedInvokeHandler"): - /* - * invoke-polymorphic handler wrapper. - */ - /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ - .extern $helper - .extern MterpShouldSwitchInterpreters - EXPORT_PC - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - jal $helper - beqzc v0, MterpException - FETCH_ADVANCE_INST 4 - jal MterpShouldSwitchInterpreters - bnezc v0, MterpFallback - GET_INST_OPCODE v0 - GOTO_OPCODE v0 diff --git a/runtime/interpreter/mterp/mips64/main.S b/runtime/interpreter/mterp/mips64/main.S new file mode 100644 index 0000000000..c2c305ac76 --- /dev/null +++ b/runtime/interpreter/mterp/mips64/main.S @@ -0,0 +1,757 @@ +%def header(): +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#define zero $$0 /* always zero */ +#define AT $$at /* assembler temp */ +#define v0 $$2 /* return value */ +#define v1 $$3 +#define a0 $$4 /* argument registers */ +#define a1 $$5 +#define a2 $$6 +#define a3 $$7 +#define a4 $$8 /* expanded register arguments */ +#define a5 $$9 +#define a6 $$10 +#define a7 $$11 +#define ta0 $$8 /* alias */ +#define ta1 $$9 +#define ta2 $$10 +#define ta3 $$11 +#define t0 $$12 /* temp registers (not saved across subroutine calls) */ +#define t1 $$13 +#define t2 $$14 +#define t3 $$15 + +#define s0 $$16 /* saved across subroutine calls (callee saved) */ +#define s1 $$17 +#define s2 $$18 +#define s3 $$19 +#define s4 $$20 +#define s5 $$21 +#define s6 $$22 +#define s7 $$23 +#define t8 $$24 /* two more temp registers */ +#define t9 $$25 +#define k0 $$26 /* kernel temporary */ +#define k1 $$27 +#define gp $$28 /* global pointer */ +#define sp $$29 /* stack pointer */ +#define s8 $$30 /* one more callee saved */ +#define ra $$31 /* return address */ + +#define f0 $$f0 +#define f1 $$f1 +#define f2 $$f2 +#define f3 $$f3 +#define f12 $$f12 +#define f13 $$f13 + +/* + * It looks like the GNU assembler currently does not support the blec and bgtc + * idioms, which should translate into bgec and bltc respectively with swapped + * left and right register operands. + * TODO: remove these macros when the assembler is fixed. + */ +.macro blec lreg, rreg, target + bgec \rreg, \lreg, \target +.endm +.macro bgtc lreg, rreg, target + bltc \rreg, \lreg, \target +.endm + +/* +Mterp and MIPS64 notes: + +The following registers have fixed assignments: + + reg nick purpose + s0 rPC interpreted program counter, used for fetching instructions + s1 rFP interpreted frame pointer, used for accessing locals and args + s2 rSELF self (Thread) pointer + s3 rINST first 16-bit code unit of current instruction + s4 rIBASE interpreted instruction base pointer, used for computed goto + s5 rREFS base of object references in shadow frame (ideally, we'll get rid of this later). + s6 rPROFILE jit profile hotness countdown +*/ + +/* During bringup, we'll use the shadow frame model instead of rFP */ +/* single-purpose registers, given names for clarity */ +#define rPC s0 +#define CFI_DEX 16 // DWARF register number of the register holding dex-pc (s0). +#define CFI_TMP 4 // DWARF register number of the first argument register (a0). +#define rFP s1 +#define rSELF s2 +#define rINST s3 +#define rIBASE s4 +#define rREFS s5 +#define rPROFILE s6 + +/* + * This is a #include, not a %include, because we want the C pre-processor + * to expand the macros into assembler assignment statements. + */ +#include "asm_support.h" +#include "interpreter/cfi_asm_support.h" + +/* + * Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs. So, + * to access other shadow frame fields, we need to use a backwards offset. Define those here. + */ +#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) +#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) +#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) +#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) +#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) +#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) +#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) +#define OFF_FP_DEX_INSTRUCTIONS OFF_FP(SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET) +#define OFF_FP_SHADOWFRAME OFF_FP(0) + +#define MTERP_PROFILE_BRANCHES 1 +#define MTERP_LOGGING 0 + +/* + * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must + * be done *before* something throws. + * + * It's okay to do this more than once. + * + * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped + * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction + * offset into the code_items_[] array. For effiency, we will "export" the + * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC + * to convert to a dex pc when needed. + */ +.macro EXPORT_PC + sd rPC, OFF_FP_DEX_PC_PTR(rFP) +.endm + +/* + * Refresh handler table. + */ +.macro REFRESH_IBASE + ld rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) +.endm + +/* + * Fetch the next instruction from rPC into rINST. Does not advance rPC. + */ +.macro FETCH_INST + lhu rINST, 0(rPC) +.endm + +/* Advance rPC by some number of code units. */ +.macro ADVANCE count + daddu rPC, rPC, (\count) * 2 +.endm + +/* + * Fetch the next instruction from an offset specified by _reg and advance xPC. + * xPC to point to the next instruction. "_reg" must specify the distance + * in bytes, *not* 16-bit code units, and may be a signed value. Must not set flags. + * + */ +.macro FETCH_ADVANCE_INST_RB reg + daddu rPC, rPC, \reg + FETCH_INST +.endm + +/* + * Fetch the next instruction from the specified offset. Advances rPC + * to point to the next instruction. + * + * This must come AFTER anything that can throw an exception, or the + * exception catch may miss. (This also implies that it must come after + * EXPORT_PC.) + */ +.macro FETCH_ADVANCE_INST count + ADVANCE \count + FETCH_INST +.endm + +/* + * Similar to FETCH_ADVANCE_INST, but does not update rPC. Used to load + * rINST ahead of possible exception point. Be sure to manually advance rPC + * later. + */ +.macro PREFETCH_INST count + lhu rINST, ((\count) * 2)(rPC) +.endm + +/* + * Put the instruction's opcode field into the specified register. + */ +.macro GET_INST_OPCODE reg + and \reg, rINST, 255 +.endm + +/* + * Begin executing the opcode in _reg. + */ +.macro GOTO_OPCODE reg + .set noat + sll AT, \reg, 7 + daddu AT, rIBASE, AT + jic AT, 0 + .set at +.endm + +/* + * Get/set the 32-bit value from a Dalvik register. + * Note, GET_VREG does sign extension to 64 bits while + * GET_VREG_U does zero extension to 64 bits. + * One is useful for arithmetic while the other is + * useful for storing the result value as 64-bit. + */ +.macro GET_VREG reg, vreg + .set noat + dlsa AT, \vreg, rFP, 2 + lw \reg, 0(AT) + .set at +.endm +.macro GET_VREG_U reg, vreg + .set noat + dlsa AT, \vreg, rFP, 2 + lwu \reg, 0(AT) + .set at +.endm +.macro GET_VREG_FLOAT reg, vreg + .set noat + dlsa AT, \vreg, rFP, 2 + lwc1 \reg, 0(AT) + .set at +.endm +.macro SET_VREG reg, vreg + .set noat + dlsa AT, \vreg, rFP, 2 + sw \reg, 0(AT) + dlsa AT, \vreg, rREFS, 2 + sw zero, 0(AT) + .set at +.endm +.macro SET_VREG_OBJECT reg, vreg + .set noat + dlsa AT, \vreg, rFP, 2 + sw \reg, 0(AT) + dlsa AT, \vreg, rREFS, 2 + sw \reg, 0(AT) + .set at +.endm +.macro SET_VREG_FLOAT reg, vreg + .set noat + dlsa AT, \vreg, rFP, 2 + swc1 \reg, 0(AT) + dlsa AT, \vreg, rREFS, 2 + sw zero, 0(AT) + .set at +.endm + +/* + * Get/set the 64-bit value from a Dalvik register. + * Avoid unaligned memory accesses. + * Note, SET_VREG_WIDE clobbers the register containing the value being stored. + * Note, SET_VREG_DOUBLE clobbers the register containing the Dalvik register number. + */ +.macro GET_VREG_WIDE reg, vreg + .set noat + dlsa AT, \vreg, rFP, 2 + lw \reg, 0(AT) + lw AT, 4(AT) + dinsu \reg, AT, 32, 32 + .set at +.endm +.macro GET_VREG_DOUBLE reg, vreg + .set noat + dlsa AT, \vreg, rFP, 2 + lwc1 \reg, 0(AT) + lw AT, 4(AT) + mthc1 AT, \reg + .set at +.endm +.macro SET_VREG_WIDE reg, vreg + .set noat + dlsa AT, \vreg, rFP, 2 + sw \reg, 0(AT) + drotr32 \reg, \reg, 0 + sw \reg, 4(AT) + dlsa AT, \vreg, rREFS, 2 + sw zero, 0(AT) + sw zero, 4(AT) + .set at +.endm +.macro SET_VREG_DOUBLE reg, vreg + .set noat + dlsa AT, \vreg, rREFS, 2 + sw zero, 0(AT) + sw zero, 4(AT) + dlsa AT, \vreg, rFP, 2 + swc1 \reg, 0(AT) + mfhc1 \vreg, \reg + sw \vreg, 4(AT) + .set at +.endm + +/* + * On-stack offsets for spilling/unspilling callee-saved registers + * and the frame size. + */ +#define STACK_OFFSET_RA 0 +#define STACK_OFFSET_GP 8 +#define STACK_OFFSET_S0 16 +#define STACK_OFFSET_S1 24 +#define STACK_OFFSET_S2 32 +#define STACK_OFFSET_S3 40 +#define STACK_OFFSET_S4 48 +#define STACK_OFFSET_S5 56 +#define STACK_OFFSET_S6 64 +#define STACK_SIZE 80 /* needs 16 byte alignment */ + +/* Constants for float/double_to_int/long conversions */ +#define INT_MIN 0x80000000 +#define INT_MIN_AS_FLOAT 0xCF000000 +#define INT_MIN_AS_DOUBLE 0xC1E0000000000000 +#define LONG_MIN 0x8000000000000000 +#define LONG_MIN_AS_FLOAT 0xDF000000 +#define LONG_MIN_AS_DOUBLE 0xC3E0000000000000 + +%def entry(): +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Interpreter entry point. + */ + + .set reorder + + .text + .global ExecuteMterpImpl + .type ExecuteMterpImpl, %function + .balign 16 +/* + * On entry: + * a0 Thread* self + * a1 dex_instructions + * a2 ShadowFrame + * a3 JValue* result_register + * + */ +ExecuteMterpImpl: + .cfi_startproc + .cpsetup t9, t8, ExecuteMterpImpl + + .cfi_def_cfa sp, 0 + daddu sp, sp, -STACK_SIZE + .cfi_adjust_cfa_offset STACK_SIZE + + sd t8, STACK_OFFSET_GP(sp) + .cfi_rel_offset 28, STACK_OFFSET_GP + sd ra, STACK_OFFSET_RA(sp) + .cfi_rel_offset 31, STACK_OFFSET_RA + + sd s0, STACK_OFFSET_S0(sp) + .cfi_rel_offset 16, STACK_OFFSET_S0 + sd s1, STACK_OFFSET_S1(sp) + .cfi_rel_offset 17, STACK_OFFSET_S1 + sd s2, STACK_OFFSET_S2(sp) + .cfi_rel_offset 18, STACK_OFFSET_S2 + sd s3, STACK_OFFSET_S3(sp) + .cfi_rel_offset 19, STACK_OFFSET_S3 + sd s4, STACK_OFFSET_S4(sp) + .cfi_rel_offset 20, STACK_OFFSET_S4 + sd s5, STACK_OFFSET_S5(sp) + .cfi_rel_offset 21, STACK_OFFSET_S5 + sd s6, STACK_OFFSET_S6(sp) + .cfi_rel_offset 22, STACK_OFFSET_S6 + + /* Remember the return register */ + sd a3, SHADOWFRAME_RESULT_REGISTER_OFFSET(a2) + + /* Remember the dex instruction pointer */ + sd a1, SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET(a2) + + /* set up "named" registers */ + move rSELF, a0 + daddu rFP, a2, SHADOWFRAME_VREGS_OFFSET + lw v0, SHADOWFRAME_NUMBER_OF_VREGS_OFFSET(a2) + dlsa rREFS, v0, rFP, 2 + lw v0, SHADOWFRAME_DEX_PC_OFFSET(a2) + dlsa rPC, v0, a1, 1 + CFI_DEFINE_DEX_PC_WITH_OFFSET(CFI_TMP, CFI_DEX, 0) + EXPORT_PC + + /* Starting ibase */ + REFRESH_IBASE + + /* Set up for backwards branches & osr profiling */ + ld a0, OFF_FP_METHOD(rFP) + daddu a1, rFP, OFF_FP_SHADOWFRAME + move a2, rSELF + jal MterpSetUpHotnessCountdown + move rPROFILE, v0 # Starting hotness countdown to rPROFILE + + /* start executing the instruction at rPC */ + FETCH_INST + GET_INST_OPCODE v0 + GOTO_OPCODE v0 + + /* NOTE: no fallthrough */ + +%def alt_stub(): +/* + * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle + * any interesting requests and then jump to the real instruction + * handler. Note that the call to MterpCheckBefore is done as a tail call. + */ + .extern MterpCheckBefore + REFRESH_IBASE + dla ra, artMterpAsmInstructionStart + dla t9, MterpCheckBefore + move a0, rSELF + daddu a1, rFP, OFF_FP_SHADOWFRAME + move a2, rPC + daddu ra, ra, (${opnum} * 128) # Addr of primary handler. + jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. + +%def fallback(): +/* Transfer stub to alternate interpreter */ + b MterpFallback + +%def footer(): +/* + * We've detected a condition that will result in an exception, but the exception + * has not yet been thrown. Just bail out to the reference interpreter to deal with it. + * TUNING: for consistency, we may want to just go ahead and handle these here. + */ + + .extern MterpLogDivideByZeroException +common_errDivideByZero: + EXPORT_PC +#if MTERP_LOGGING + move a0, rSELF + daddu a1, rFP, OFF_FP_SHADOWFRAME + jal MterpLogDivideByZeroException +#endif + b MterpCommonFallback + + .extern MterpLogArrayIndexException +common_errArrayIndex: + EXPORT_PC +#if MTERP_LOGGING + move a0, rSELF + daddu a1, rFP, OFF_FP_SHADOWFRAME + jal MterpLogArrayIndexException +#endif + b MterpCommonFallback + + .extern MterpLogNullObjectException +common_errNullObject: + EXPORT_PC +#if MTERP_LOGGING + move a0, rSELF + daddu a1, rFP, OFF_FP_SHADOWFRAME + jal MterpLogNullObjectException +#endif + b MterpCommonFallback + +/* + * If we're here, something is out of the ordinary. If there is a pending + * exception, handle it. Otherwise, roll back and retry with the reference + * interpreter. + */ +MterpPossibleException: + ld a0, THREAD_EXCEPTION_OFFSET(rSELF) + beqzc a0, MterpFallback # If not, fall back to reference interpreter. + /* intentional fallthrough - handle pending exception. */ +/* + * On return from a runtime helper routine, we've found a pending exception. + * Can we handle it here - or need to bail out to caller? + * + */ + .extern MterpHandleException + .extern MterpShouldSwitchInterpreters +MterpException: + move a0, rSELF + daddu a1, rFP, OFF_FP_SHADOWFRAME + jal MterpHandleException # (self, shadow_frame) + beqzc v0, MterpExceptionReturn # no local catch, back to caller. + ld a0, OFF_FP_DEX_INSTRUCTIONS(rFP) + lwu a1, OFF_FP_DEX_PC(rFP) + REFRESH_IBASE + dlsa rPC, a1, a0, 1 # generate new dex_pc_ptr + /* Do we need to switch interpreters? */ + jal MterpShouldSwitchInterpreters + bnezc v0, MterpFallback + /* resume execution at catch block */ + EXPORT_PC + FETCH_INST + GET_INST_OPCODE v0 + GOTO_OPCODE v0 + /* NOTE: no fallthrough */ + +/* + * Common handling for branches with support for Jit profiling. + * On entry: + * rINST <= signed offset + * rPROFILE <= signed hotness countdown (expanded to 64 bits) + * + * We have quite a few different cases for branch profiling, OSR detection and + * suspend check support here. + * + * Taken backward branches: + * If profiling active, do hotness countdown and report if we hit zero. + * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. + * Is there a pending suspend request? If so, suspend. + * + * Taken forward branches and not-taken backward branches: + * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. + * + * Our most common case is expected to be a taken backward branch with active jit profiling, + * but no full OSR check and no pending suspend request. + * Next most common case is not-taken branch with no full OSR check. + * + */ +MterpCommonTakenBranchNoFlags: + bgtzc rINST, .L_forward_branch # don't add forward branches to hotness +/* + * We need to subtract 1 from positive values and we should not see 0 here, + * so we may use the result of the comparison with -1. + */ + li v0, JIT_CHECK_OSR + beqc rPROFILE, v0, .L_osr_check + bltc rPROFILE, v0, .L_resume_backward_branch + dsubu rPROFILE, 1 + beqzc rPROFILE, .L_add_batch # counted down to zero - report +.L_resume_backward_branch: + lw ra, THREAD_FLAGS_OFFSET(rSELF) + REFRESH_IBASE + daddu a2, rINST, rINST # a2<- byte offset + FETCH_ADVANCE_INST_RB a2 # update rPC, load rINST + and ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST + bnezc ra, .L_suspend_request_pending + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +.L_suspend_request_pending: + EXPORT_PC + move a0, rSELF + jal MterpSuspendCheck # (self) + bnezc v0, MterpFallback + REFRESH_IBASE # might have changed during suspend + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +.L_no_count_backwards: + li v0, JIT_CHECK_OSR # check for possible OSR re-entry + bnec rPROFILE, v0, .L_resume_backward_branch +.L_osr_check: + move a0, rSELF + daddu a1, rFP, OFF_FP_SHADOWFRAME + move a2, rINST + EXPORT_PC + jal MterpMaybeDoOnStackReplacement # (self, shadow_frame, offset) + bnezc v0, MterpOnStackReplacement + b .L_resume_backward_branch + +.L_forward_branch: + li v0, JIT_CHECK_OSR # check for possible OSR re-entry + beqc rPROFILE, v0, .L_check_osr_forward +.L_resume_forward_branch: + daddu a2, rINST, rINST # a2<- byte offset + FETCH_ADVANCE_INST_RB a2 # update rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +.L_check_osr_forward: + move a0, rSELF + daddu a1, rFP, OFF_FP_SHADOWFRAME + move a2, rINST + EXPORT_PC + jal MterpMaybeDoOnStackReplacement # (self, shadow_frame, offset) + bnezc v0, MterpOnStackReplacement + b .L_resume_forward_branch + +.L_add_batch: + daddu a1, rFP, OFF_FP_SHADOWFRAME + sh rPROFILE, SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET(a1) + ld a0, OFF_FP_METHOD(rFP) + move a2, rSELF + jal MterpAddHotnessBatch # (method, shadow_frame, self) + move rPROFILE, v0 # restore new hotness countdown to rPROFILE + b .L_no_count_backwards + +/* + * Entered from the conditional branch handlers when OSR check request active on + * not-taken path. All Dalvik not-taken conditional branch offsets are 2. + */ +.L_check_not_taken_osr: + move a0, rSELF + daddu a1, rFP, OFF_FP_SHADOWFRAME + li a2, 2 + EXPORT_PC + jal MterpMaybeDoOnStackReplacement # (self, shadow_frame, offset) + bnezc v0, MterpOnStackReplacement + FETCH_ADVANCE_INST 2 + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +/* + * On-stack replacement has happened, and now we've returned from the compiled method. + */ +MterpOnStackReplacement: +#if MTERP_LOGGING + move a0, rSELF + daddu a1, rFP, OFF_FP_SHADOWFRAME + move a2, rINST # rINST contains offset + jal MterpLogOSR +#endif + li v0, 1 # Signal normal return + b MterpDone + +/* + * Bail out to reference interpreter. + */ + .extern MterpLogFallback +MterpFallback: + EXPORT_PC +#if MTERP_LOGGING + move a0, rSELF + daddu a1, rFP, OFF_FP_SHADOWFRAME + jal MterpLogFallback +#endif +MterpCommonFallback: + li v0, 0 # signal retry with reference interpreter. + b MterpDone + +/* + * We pushed some registers on the stack in ExecuteMterpImpl, then saved + * SP and RA. Here we restore SP, restore the registers, and then restore + * RA to PC. + * + * On entry: + * uint32_t* rFP (should still be live, pointer to base of vregs) + */ +MterpExceptionReturn: + li v0, 1 # signal return to caller. + b MterpDone +/* + * Returned value is expected in a0 and if it's not 64-bit, the 32 most + * significant bits of a0 must be zero-extended or sign-extended + * depending on the return type. + */ +MterpReturn: + ld a2, OFF_FP_RESULT_REGISTER(rFP) + sd a0, 0(a2) + li v0, 1 # signal return to caller. +MterpDone: +/* + * At this point, we expect rPROFILE to be non-zero. If negative, hotness is disabled or we're + * checking for OSR. If greater than zero, we might have unreported hotness to register + * (the difference between the ending rPROFILE and the cached hotness counter). rPROFILE + * should only reach zero immediately after a hotness decrement, and is then reset to either + * a negative special state or the new non-zero countdown value. + */ + blez rPROFILE, .L_pop_and_return # if > 0, we may have some counts to report. + +MterpProfileActive: + move rINST, v0 # stash return value + /* Report cached hotness counts */ + ld a0, OFF_FP_METHOD(rFP) + daddu a1, rFP, OFF_FP_SHADOWFRAME + move a2, rSELF + sh rPROFILE, SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET(a1) + jal MterpAddHotnessBatch # (method, shadow_frame, self) + move v0, rINST # restore return value + +.L_pop_and_return: + ld s6, STACK_OFFSET_S6(sp) + .cfi_restore 22 + ld s5, STACK_OFFSET_S5(sp) + .cfi_restore 21 + ld s4, STACK_OFFSET_S4(sp) + .cfi_restore 20 + ld s3, STACK_OFFSET_S3(sp) + .cfi_restore 19 + ld s2, STACK_OFFSET_S2(sp) + .cfi_restore 18 + ld s1, STACK_OFFSET_S1(sp) + .cfi_restore 17 + ld s0, STACK_OFFSET_S0(sp) + .cfi_restore 16 + + ld ra, STACK_OFFSET_RA(sp) + .cfi_restore 31 + + ld t8, STACK_OFFSET_GP(sp) + .cpreturn + .cfi_restore 28 + + .set noreorder + jr ra + daddu sp, sp, STACK_SIZE + .cfi_adjust_cfa_offset -STACK_SIZE + + .cfi_endproc + .set reorder + .size ExecuteMterpImpl, .-ExecuteMterpImpl + +%def instruction_end(): + + .global artMterpAsmInstructionEnd +artMterpAsmInstructionEnd: + +%def instruction_end_alt(): + + .global artMterpAsmAltInstructionEnd +artMterpAsmAltInstructionEnd: + +%def instruction_end_sister(): + + .global artMterpAsmSisterEnd +artMterpAsmSisterEnd: + +%def instruction_start(): + + .global artMterpAsmInstructionStart +artMterpAsmInstructionStart = .L_op_nop + .text + +%def instruction_start_alt(): + + .global artMterpAsmAltInstructionStart +artMterpAsmAltInstructionStart = .L_ALT_op_nop + .text + +%def instruction_start_sister(): + + .global artMterpAsmSisterStart + .text + .balign 4 +artMterpAsmSisterStart: diff --git a/runtime/interpreter/mterp/mips64/object.S b/runtime/interpreter/mterp/mips64/object.S new file mode 100644 index 0000000000..a5a2b3d1db --- /dev/null +++ b/runtime/interpreter/mterp/mips64/object.S @@ -0,0 +1,262 @@ +%def field(helper=""): +TODO + +%def op_check_cast(): + /* + * Check to see if a cast from one class to another is allowed. + */ + /* check-cast vAA, class//BBBB */ + .extern MterpCheckCast + EXPORT_PC + lhu a0, 2(rPC) # a0 <- BBBB + srl a1, rINST, 8 # a1 <- AA + dlsa a1, a1, rFP, 2 # a1 <- &object + ld a2, OFF_FP_METHOD(rFP) # a2 <- method + move a3, rSELF # a3 <- self + jal MterpCheckCast # (index, &obj, method, self) + PREFETCH_INST 2 + bnez v0, MterpPossibleException + ADVANCE 2 + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +%def op_iget(is_object="0", helper="MterpIGetU32"): +% field(helper=helper) + +%def op_iget_boolean(): +% op_iget(helper="MterpIGetU8") + +%def op_iget_boolean_quick(): +% op_iget_quick(load="lbu") + +%def op_iget_byte(): +% op_iget(helper="MterpIGetI8") + +%def op_iget_byte_quick(): +% op_iget_quick(load="lb") + +%def op_iget_char(): +% op_iget(helper="MterpIGetU16") + +%def op_iget_char_quick(): +% op_iget_quick(load="lhu") + +%def op_iget_object(): +% op_iget(is_object="1", helper="MterpIGetObj") + +%def op_iget_object_quick(): + /* For: iget-object-quick */ + /* op vA, vB, offset//CCCC */ + .extern artIGetObjectFromMterp + srl a2, rINST, 12 # a2 <- B + lhu a1, 2(rPC) # a1 <- field byte offset + EXPORT_PC + GET_VREG_U a0, a2 # a0 <- object we're operating on + jal artIGetObjectFromMterp # (obj, offset) + ld a3, THREAD_EXCEPTION_OFFSET(rSELF) + ext a2, rINST, 8, 4 # a2 <- A + PREFETCH_INST 2 + bnez a3, MterpPossibleException # bail out + SET_VREG_OBJECT v0, a2 # fp[A] <- v0 + ADVANCE 2 # advance rPC + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +%def op_iget_quick(load="lw"): + /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ + /* op vA, vB, offset//CCCC */ + srl a2, rINST, 12 # a2 <- B + lhu a1, 2(rPC) # a1 <- field byte offset + GET_VREG_U a3, a2 # a3 <- object we're operating on + ext a4, rINST, 8, 4 # a4 <- A + daddu a1, a1, a3 + beqz a3, common_errNullObject # object was null + $load a0, 0(a1) # a0 <- obj.field + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + SET_VREG a0, a4 # fp[A] <- a0 + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +%def op_iget_short(): +% op_iget(helper="MterpIGetI16") + +%def op_iget_short_quick(): +% op_iget_quick(load="lh") + +%def op_iget_wide(): +% op_iget(helper="MterpIGetU64") + +%def op_iget_wide_quick(): + /* iget-wide-quick vA, vB, offset//CCCC */ + srl a2, rINST, 12 # a2 <- B + lhu a4, 2(rPC) # a4 <- field byte offset + GET_VREG_U a3, a2 # a3 <- object we're operating on + ext a2, rINST, 8, 4 # a2 <- A + beqz a3, common_errNullObject # object was null + daddu a4, a3, a4 # create direct pointer + lw a0, 0(a4) + lw a1, 4(a4) + dinsu a0, a1, 32, 32 + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + SET_VREG_WIDE a0, a2 + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +%def op_instance_of(): + /* + * Check to see if an object reference is an instance of a class. + * + * Most common situation is a non-null object, being compared against + * an already-resolved class. + */ + /* instance-of vA, vB, class//CCCC */ + .extern MterpInstanceOf + EXPORT_PC + lhu a0, 2(rPC) # a0 <- CCCC + srl a1, rINST, 12 # a1 <- B + dlsa a1, a1, rFP, 2 # a1 <- &object + ld a2, OFF_FP_METHOD(rFP) # a2 <- method + move a3, rSELF # a3 <- self + jal MterpInstanceOf # (index, &obj, method, self) + ld a1, THREAD_EXCEPTION_OFFSET(rSELF) + ext a2, rINST, 8, 4 # a2 <- A + PREFETCH_INST 2 + bnez a1, MterpException + ADVANCE 2 # advance rPC + SET_VREG v0, a2 # vA <- v0 + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +%def op_iput(is_object="0", helper="MterpIPutU32"): +% field(helper=helper) + +%def op_iput_boolean(): +% op_iput(helper="MterpIPutU8") + +%def op_iput_boolean_quick(): +% op_iput_quick(store="sb") + +%def op_iput_byte(): +% op_iput(helper="MterpIPutI8") + +%def op_iput_byte_quick(): +% op_iput_quick(store="sb") + +%def op_iput_char(): +% op_iput(helper="MterpIPutU16") + +%def op_iput_char_quick(): +% op_iput_quick(store="sh") + +%def op_iput_object(): +% op_iput(is_object="1", helper="MterpIPutObj") + +%def op_iput_object_quick(): + .extern MterpIputObjectQuick + EXPORT_PC + daddu a0, rFP, OFF_FP_SHADOWFRAME + move a1, rPC + move a2, rINST + jal MterpIputObjectQuick + beqzc v0, MterpException + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +%def op_iput_quick(store="sw"): + /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */ + /* op vA, vB, offset//CCCC */ + srl a2, rINST, 12 # a2 <- B + lhu a1, 2(rPC) # a1 <- field byte offset + GET_VREG_U a3, a2 # a3 <- fp[B], the object pointer + ext a2, rINST, 8, 4 # a2 <- A + beqz a3, common_errNullObject # object was null + GET_VREG a0, a2 # a0 <- fp[A] + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + daddu a1, a1, a3 + $store a0, 0(a1) # obj.field <- a0 + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +%def op_iput_short(): +% op_iput(helper="MterpIPutI16") + +%def op_iput_short_quick(): +% op_iput_quick(store="sh") + +%def op_iput_wide(): +% op_iput(helper="MterpIPutU64") + +%def op_iput_wide_quick(): + /* iput-wide-quick vA, vB, offset//CCCC */ + srl a2, rINST, 12 # a2 <- B + lhu a3, 2(rPC) # a3 <- field byte offset + GET_VREG_U a2, a2 # a2 <- fp[B], the object pointer + ext a0, rINST, 8, 4 # a0 <- A + beqz a2, common_errNullObject # object was null + GET_VREG_WIDE a0, a0 # a0 <- fp[A] + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + daddu a1, a2, a3 # create a direct pointer + sw a0, 0(a1) + dsrl32 a0, a0, 0 + sw a0, 4(a1) + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +%def op_new_instance(): + /* + * Create a new instance of a class. + */ + /* new-instance vAA, class//BBBB */ + .extern MterpNewInstance + EXPORT_PC + daddu a0, rFP, OFF_FP_SHADOWFRAME + move a1, rSELF + move a2, rINST + jal MterpNewInstance # (shadow_frame, self, inst_data) + beqzc v0, MterpPossibleException + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +%def op_sget(is_object="0", helper="MterpSGetU32"): +% field(helper=helper) + +%def op_sget_boolean(): +% op_sget(helper="MterpSGetU8") + +%def op_sget_byte(): +% op_sget(helper="MterpSGetI8") + +%def op_sget_char(): +% op_sget(helper="MterpSGetU16") + +%def op_sget_object(): +% op_sget(is_object="1", helper="MterpSGetObj") + +%def op_sget_short(): +% op_sget(helper="MterpSGetI16") + +%def op_sget_wide(): +% op_sget(helper="MterpSGetU64") + +%def op_sput(is_object="0", helper="MterpSPutU32"): +% field(helper=helper) + +%def op_sput_boolean(): +% op_sput(helper="MterpSPutU8") + +%def op_sput_byte(): +% op_sput(helper="MterpSPutI8") + +%def op_sput_char(): +% op_sput(helper="MterpSPutU16") + +%def op_sput_object(): +% op_sput(is_object="1", helper="MterpSPutObj") + +%def op_sput_short(): +% op_sput(helper="MterpSPutI16") + +%def op_sput_wide(): +% op_sput(helper="MterpSPutU64") diff --git a/runtime/interpreter/mterp/mips64/op_add_double.S b/runtime/interpreter/mterp/mips64/op_add_double.S deleted file mode 100644 index 0c1f6a28be..0000000000 --- a/runtime/interpreter/mterp/mips64/op_add_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_double(): -% fbinopWide(instr="add.d f0, f0, f1") diff --git a/runtime/interpreter/mterp/mips64/op_add_double_2addr.S b/runtime/interpreter/mterp/mips64/op_add_double_2addr.S deleted file mode 100644 index f667996243..0000000000 --- a/runtime/interpreter/mterp/mips64/op_add_double_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_double_2addr(): -% fbinopWide2addr(instr="add.d f0, f0, f1") diff --git a/runtime/interpreter/mterp/mips64/op_add_float.S b/runtime/interpreter/mterp/mips64/op_add_float.S deleted file mode 100644 index 4c0f88c71a..0000000000 --- a/runtime/interpreter/mterp/mips64/op_add_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_float(): -% fbinop(instr="add.s f0, f0, f1") diff --git a/runtime/interpreter/mterp/mips64/op_add_float_2addr.S b/runtime/interpreter/mterp/mips64/op_add_float_2addr.S deleted file mode 100644 index 0bcc91aa27..0000000000 --- a/runtime/interpreter/mterp/mips64/op_add_float_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_float_2addr(): -% fbinop2addr(instr="add.s f0, f0, f1") diff --git a/runtime/interpreter/mterp/mips64/op_add_int.S b/runtime/interpreter/mterp/mips64/op_add_int.S deleted file mode 100644 index ed0fc012b8..0000000000 --- a/runtime/interpreter/mterp/mips64/op_add_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_int(): -% binop(instr="addu a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_add_int_2addr.S b/runtime/interpreter/mterp/mips64/op_add_int_2addr.S deleted file mode 100644 index ed0b1314ef..0000000000 --- a/runtime/interpreter/mterp/mips64/op_add_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_int_2addr(): -% binop2addr(instr="addu a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_add_int_lit16.S b/runtime/interpreter/mterp/mips64/op_add_int_lit16.S deleted file mode 100644 index 126807a303..0000000000 --- a/runtime/interpreter/mterp/mips64/op_add_int_lit16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_int_lit16(): -% binopLit16(instr="addu a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_add_int_lit8.S b/runtime/interpreter/mterp/mips64/op_add_int_lit8.S deleted file mode 100644 index 30184c40f5..0000000000 --- a/runtime/interpreter/mterp/mips64/op_add_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_int_lit8(): -% binopLit8(instr="addu a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_add_long.S b/runtime/interpreter/mterp/mips64/op_add_long.S deleted file mode 100644 index 72a1f24abb..0000000000 --- a/runtime/interpreter/mterp/mips64/op_add_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_long(): -% binopWide(instr="daddu a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_add_long_2addr.S b/runtime/interpreter/mterp/mips64/op_add_long_2addr.S deleted file mode 100644 index caf29e230d..0000000000 --- a/runtime/interpreter/mterp/mips64/op_add_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_long_2addr(): -% binopWide2addr(instr="daddu a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_aget.S b/runtime/interpreter/mterp/mips64/op_aget.S deleted file mode 100644 index 60be23dc7a..0000000000 --- a/runtime/interpreter/mterp/mips64/op_aget.S +++ /dev/null @@ -1,29 +0,0 @@ -%def op_aget(load="lw", shift="2", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"): - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - srl a4, rINST, 8 # a4 <- AA - GET_VREG_U a0, a2 # a0 <- vBB (array object) - GET_VREG a1, a3 # a1 <- vCC (requested index) - beqz a0, common_errNullObject # bail if null array object - lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length - .if $shift - # [d]lsa does not support shift count of 0. - dlsa a0, a1, a0, $shift # a0 <- arrayObj + index*width - .else - daddu a0, a1, a0 # a0 <- arrayObj + index*width - .endif - bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - $load a2, $data_offset(a0) # a2 <- vBB[vCC] - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a2, a4 # vAA <- a2 - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_aget_boolean.S b/runtime/interpreter/mterp/mips64/op_aget_boolean.S deleted file mode 100644 index 7b28bc8e06..0000000000 --- a/runtime/interpreter/mterp/mips64/op_aget_boolean.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aget_boolean(): -% op_aget(load="lbu", shift="0", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/mips64/op_aget_byte.S b/runtime/interpreter/mterp/mips64/op_aget_byte.S deleted file mode 100644 index a4a0b7e9b7..0000000000 --- a/runtime/interpreter/mterp/mips64/op_aget_byte.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aget_byte(): -% op_aget(load="lb", shift="0", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/mips64/op_aget_char.S b/runtime/interpreter/mterp/mips64/op_aget_char.S deleted file mode 100644 index 465de097cd..0000000000 --- a/runtime/interpreter/mterp/mips64/op_aget_char.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aget_char(): -% op_aget(load="lhu", shift="1", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/mips64/op_aget_object.S b/runtime/interpreter/mterp/mips64/op_aget_object.S deleted file mode 100644 index 48d751b197..0000000000 --- a/runtime/interpreter/mterp/mips64/op_aget_object.S +++ /dev/null @@ -1,22 +0,0 @@ -%def op_aget_object(): - /* - * Array object get. vAA <- vBB[vCC]. - * - * for: aget-object - */ - /* op vAA, vBB, vCC */ - .extern artAGetObjectFromMterp - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - EXPORT_PC - GET_VREG_U a0, a2 # a0 <- vBB (array object) - GET_VREG a1, a3 # a1 <- vCC (requested index) - jal artAGetObjectFromMterp # (array, index) - ld a1, THREAD_EXCEPTION_OFFSET(rSELF) - srl a4, rINST, 8 # a4 <- AA - PREFETCH_INST 2 - bnez a1, MterpException - SET_VREG_OBJECT v0, a4 # vAA <- v0 - ADVANCE 2 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_aget_short.S b/runtime/interpreter/mterp/mips64/op_aget_short.S deleted file mode 100644 index 4faa9ad358..0000000000 --- a/runtime/interpreter/mterp/mips64/op_aget_short.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aget_short(): -% op_aget(load="lh", shift="1", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/mips64/op_aget_wide.S b/runtime/interpreter/mterp/mips64/op_aget_wide.S deleted file mode 100644 index 99b0de9b64..0000000000 --- a/runtime/interpreter/mterp/mips64/op_aget_wide.S +++ /dev/null @@ -1,22 +0,0 @@ -%def op_aget_wide(): - /* - * Array get, 64 bits. vAA <- vBB[vCC]. - * - */ - /* aget-wide vAA, vBB, vCC */ - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - srl a4, rINST, 8 # a4 <- AA - GET_VREG_U a0, a2 # a0 <- vBB (array object) - GET_VREG a1, a3 # a1 <- vCC (requested index) - beqz a0, common_errNullObject # bail if null array object - lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length - dlsa a0, a1, a0, 3 # a0 <- arrayObj + index*width - bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - lw a2, MIRROR_WIDE_ARRAY_DATA_OFFSET(a0) - lw a3, (MIRROR_WIDE_ARRAY_DATA_OFFSET+4)(a0) - dinsu a2, a3, 32, 32 # a2 <- vBB[vCC] - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a2, a4 # vAA <- a2 - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_and_int.S b/runtime/interpreter/mterp/mips64/op_and_int.S deleted file mode 100644 index 740411ddf7..0000000000 --- a/runtime/interpreter/mterp/mips64/op_and_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_and_int(): -% binop(instr="and a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_and_int_2addr.S b/runtime/interpreter/mterp/mips64/op_and_int_2addr.S deleted file mode 100644 index 8224e5f18a..0000000000 --- a/runtime/interpreter/mterp/mips64/op_and_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_and_int_2addr(): -% binop2addr(instr="and a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_and_int_lit16.S b/runtime/interpreter/mterp/mips64/op_and_int_lit16.S deleted file mode 100644 index 5031f500ce..0000000000 --- a/runtime/interpreter/mterp/mips64/op_and_int_lit16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_and_int_lit16(): -% binopLit16(instr="and a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_and_int_lit8.S b/runtime/interpreter/mterp/mips64/op_and_int_lit8.S deleted file mode 100644 index 7a7b8b5d5a..0000000000 --- a/runtime/interpreter/mterp/mips64/op_and_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_and_int_lit8(): -% binopLit8(instr="and a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_and_long.S b/runtime/interpreter/mterp/mips64/op_and_long.S deleted file mode 100644 index 242ddf2e2c..0000000000 --- a/runtime/interpreter/mterp/mips64/op_and_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_and_long(): -% binopWide(instr="and a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_and_long_2addr.S b/runtime/interpreter/mterp/mips64/op_and_long_2addr.S deleted file mode 100644 index 64b5a7e65e..0000000000 --- a/runtime/interpreter/mterp/mips64/op_and_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_and_long_2addr(): -% binopWide2addr(instr="and a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_aput.S b/runtime/interpreter/mterp/mips64/op_aput.S deleted file mode 100644 index f4c04d01d0..0000000000 --- a/runtime/interpreter/mterp/mips64/op_aput.S +++ /dev/null @@ -1,29 +0,0 @@ -%def op_aput(store="sw", shift="2", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"): - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - srl a4, rINST, 8 # a4 <- AA - GET_VREG_U a0, a2 # a0 <- vBB (array object) - GET_VREG a1, a3 # a1 <- vCC (requested index) - beqz a0, common_errNullObject # bail if null array object - lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length - .if $shift - # [d]lsa does not support shift count of 0. - dlsa a0, a1, a0, $shift # a0 <- arrayObj + index*width - .else - daddu a0, a1, a0 # a0 <- arrayObj + index*width - .endif - bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_VREG a2, a4 # a2 <- vAA - GET_INST_OPCODE v0 # extract opcode from rINST - $store a2, $data_offset(a0) # vBB[vCC] <- a2 - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_aput_boolean.S b/runtime/interpreter/mterp/mips64/op_aput_boolean.S deleted file mode 100644 index 098bbcd1c4..0000000000 --- a/runtime/interpreter/mterp/mips64/op_aput_boolean.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aput_boolean(): -% op_aput(store="sb", shift="0", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/mips64/op_aput_byte.S b/runtime/interpreter/mterp/mips64/op_aput_byte.S deleted file mode 100644 index f4b42ee6e8..0000000000 --- a/runtime/interpreter/mterp/mips64/op_aput_byte.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aput_byte(): -% op_aput(store="sb", shift="0", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/mips64/op_aput_char.S b/runtime/interpreter/mterp/mips64/op_aput_char.S deleted file mode 100644 index 18eedae68d..0000000000 --- a/runtime/interpreter/mterp/mips64/op_aput_char.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aput_char(): -% op_aput(store="sh", shift="1", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/mips64/op_aput_object.S b/runtime/interpreter/mterp/mips64/op_aput_object.S deleted file mode 100644 index 6b23e90e41..0000000000 --- a/runtime/interpreter/mterp/mips64/op_aput_object.S +++ /dev/null @@ -1,15 +0,0 @@ -%def op_aput_object(): - /* - * Store an object into an array. vBB[vCC] <- vAA. - */ - /* op vAA, vBB, vCC */ - .extern MterpAputObject - EXPORT_PC - daddu a0, rFP, OFF_FP_SHADOWFRAME - move a1, rPC - move a2, rINST - jal MterpAputObject - beqzc v0, MterpPossibleException - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_aput_short.S b/runtime/interpreter/mterp/mips64/op_aput_short.S deleted file mode 100644 index 61a3c0d6ea..0000000000 --- a/runtime/interpreter/mterp/mips64/op_aput_short.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aput_short(): -% op_aput(store="sh", shift="1", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/mips64/op_aput_wide.S b/runtime/interpreter/mterp/mips64/op_aput_wide.S deleted file mode 100644 index 4fad5c462c..0000000000 --- a/runtime/interpreter/mterp/mips64/op_aput_wide.S +++ /dev/null @@ -1,22 +0,0 @@ -%def op_aput_wide(): - /* - * Array put, 64 bits. vBB[vCC] <- vAA. - * - */ - /* aput-wide vAA, vBB, vCC */ - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - srl a4, rINST, 8 # a4 <- AA - GET_VREG_U a0, a2 # a0 <- vBB (array object) - GET_VREG a1, a3 # a1 <- vCC (requested index) - beqz a0, common_errNullObject # bail if null array object - lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length - dlsa a0, a1, a0, 3 # a0 <- arrayObj + index*width - bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail - GET_VREG_WIDE a2, a4 # a2 <- vAA - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - sw a2, MIRROR_WIDE_ARRAY_DATA_OFFSET(a0) - dsrl32 a2, a2, 0 - sw a2, (MIRROR_WIDE_ARRAY_DATA_OFFSET+4)(a0) # vBB[vCC] <- a2 - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_array_length.S b/runtime/interpreter/mterp/mips64/op_array_length.S deleted file mode 100644 index 13b9a13b9c..0000000000 --- a/runtime/interpreter/mterp/mips64/op_array_length.S +++ /dev/null @@ -1,13 +0,0 @@ -%def op_array_length(): - /* - * Return the length of an array. - */ - srl a1, rINST, 12 # a1 <- B - GET_VREG_U a0, a1 # a0 <- vB (object ref) - ext a2, rINST, 8, 4 # a2 <- A - beqz a0, common_errNullObject # yup, fail - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- array length - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a3, a2 # vB <- length - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_check_cast.S b/runtime/interpreter/mterp/mips64/op_check_cast.S deleted file mode 100644 index b5f0f1fb27..0000000000 --- a/runtime/interpreter/mterp/mips64/op_check_cast.S +++ /dev/null @@ -1,18 +0,0 @@ -%def op_check_cast(): - /* - * Check to see if a cast from one class to another is allowed. - */ - /* check-cast vAA, class//BBBB */ - .extern MterpCheckCast - EXPORT_PC - lhu a0, 2(rPC) # a0 <- BBBB - srl a1, rINST, 8 # a1 <- AA - dlsa a1, a1, rFP, 2 # a1 <- &object - ld a2, OFF_FP_METHOD(rFP) # a2 <- method - move a3, rSELF # a3 <- self - jal MterpCheckCast # (index, &obj, method, self) - PREFETCH_INST 2 - bnez v0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_cmp_long.S b/runtime/interpreter/mterp/mips64/op_cmp_long.S deleted file mode 100644 index 87eba4421c..0000000000 --- a/runtime/interpreter/mterp/mips64/op_cmp_long.S +++ /dev/null @@ -1,14 +0,0 @@ -%def op_cmp_long(): - /* cmp-long vAA, vBB, vCC */ - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - srl a4, rINST, 8 # a4 <- AA - GET_VREG_WIDE a0, a2 # a0 <- vBB - GET_VREG_WIDE a1, a3 # a1 <- vCC - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - slt a2, a0, a1 - slt a0, a1, a0 - subu a0, a0, a2 - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a4 # vAA <- result - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_cmpg_double.S b/runtime/interpreter/mterp/mips64/op_cmpg_double.S deleted file mode 100644 index 4c3117b7e7..0000000000 --- a/runtime/interpreter/mterp/mips64/op_cmpg_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_cmpg_double(): -% fcmpWide(gt_bias="1") diff --git a/runtime/interpreter/mterp/mips64/op_cmpg_float.S b/runtime/interpreter/mterp/mips64/op_cmpg_float.S deleted file mode 100644 index 99c4530f82..0000000000 --- a/runtime/interpreter/mterp/mips64/op_cmpg_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_cmpg_float(): -% fcmp(gt_bias="1") diff --git a/runtime/interpreter/mterp/mips64/op_cmpl_double.S b/runtime/interpreter/mterp/mips64/op_cmpl_double.S deleted file mode 100644 index 4900bddffc..0000000000 --- a/runtime/interpreter/mterp/mips64/op_cmpl_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_cmpl_double(): -% fcmpWide(gt_bias="0") diff --git a/runtime/interpreter/mterp/mips64/op_cmpl_float.S b/runtime/interpreter/mterp/mips64/op_cmpl_float.S deleted file mode 100644 index 159c66dc06..0000000000 --- a/runtime/interpreter/mterp/mips64/op_cmpl_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_cmpl_float(): -% fcmp(gt_bias="0") diff --git a/runtime/interpreter/mterp/mips64/op_const.S b/runtime/interpreter/mterp/mips64/op_const.S deleted file mode 100644 index 619304264f..0000000000 --- a/runtime/interpreter/mterp/mips64/op_const.S +++ /dev/null @@ -1,10 +0,0 @@ -%def op_const(): - /* const vAA, #+BBBBbbbb */ - srl a2, rINST, 8 # a2 <- AA - lh a0, 2(rPC) # a0 <- bbbb (low) - lh a1, 4(rPC) # a1 <- BBBB (high) - FETCH_ADVANCE_INST 3 # advance rPC, load rINST - ins a0, a1, 16, 16 # a0 = BBBBbbbb - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vAA <- +BBBBbbbb - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_const_16.S b/runtime/interpreter/mterp/mips64/op_const_16.S deleted file mode 100644 index aac542d847..0000000000 --- a/runtime/interpreter/mterp/mips64/op_const_16.S +++ /dev/null @@ -1,8 +0,0 @@ -%def op_const_16(): - /* const/16 vAA, #+BBBB */ - srl a2, rINST, 8 # a2 <- AA - lh a0, 2(rPC) # a0 <- sign-extended BBBB - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vAA <- +BBBB - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_const_4.S b/runtime/interpreter/mterp/mips64/op_const_4.S deleted file mode 100644 index d26f4e56b1..0000000000 --- a/runtime/interpreter/mterp/mips64/op_const_4.S +++ /dev/null @@ -1,9 +0,0 @@ -%def op_const_4(): - /* const/4 vA, #+B */ - ext a2, rINST, 8, 4 # a2 <- A - seh a0, rINST # sign extend B in rINST - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - sra a0, a0, 12 # shift B into its final position - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- +B - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_const_class.S b/runtime/interpreter/mterp/mips64/op_const_class.S deleted file mode 100644 index db12ec3141..0000000000 --- a/runtime/interpreter/mterp/mips64/op_const_class.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_const_class(): -% const(helper="MterpConstClass") diff --git a/runtime/interpreter/mterp/mips64/op_const_high16.S b/runtime/interpreter/mterp/mips64/op_const_high16.S deleted file mode 100644 index bf14ab6907..0000000000 --- a/runtime/interpreter/mterp/mips64/op_const_high16.S +++ /dev/null @@ -1,9 +0,0 @@ -%def op_const_high16(): - /* const/high16 vAA, #+BBBB0000 */ - srl a2, rINST, 8 # a2 <- AA - lh a0, 2(rPC) # a0 <- BBBB - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - sll a0, a0, 16 # a0 <- BBBB0000 - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vAA <- +BBBB0000 - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_const_method_handle.S b/runtime/interpreter/mterp/mips64/op_const_method_handle.S deleted file mode 100644 index 2680c17aad..0000000000 --- a/runtime/interpreter/mterp/mips64/op_const_method_handle.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_const_method_handle(): -% const(helper="MterpConstMethodHandle") diff --git a/runtime/interpreter/mterp/mips64/op_const_method_type.S b/runtime/interpreter/mterp/mips64/op_const_method_type.S deleted file mode 100644 index ea814bf648..0000000000 --- a/runtime/interpreter/mterp/mips64/op_const_method_type.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_const_method_type(): -% const(helper="MterpConstMethodType") diff --git a/runtime/interpreter/mterp/mips64/op_const_string.S b/runtime/interpreter/mterp/mips64/op_const_string.S deleted file mode 100644 index 41376f8703..0000000000 --- a/runtime/interpreter/mterp/mips64/op_const_string.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_const_string(): -% const(helper="MterpConstString") diff --git a/runtime/interpreter/mterp/mips64/op_const_string_jumbo.S b/runtime/interpreter/mterp/mips64/op_const_string_jumbo.S deleted file mode 100644 index 25ec0e2b8d..0000000000 --- a/runtime/interpreter/mterp/mips64/op_const_string_jumbo.S +++ /dev/null @@ -1,16 +0,0 @@ -%def op_const_string_jumbo(): - /* const/string vAA, String//BBBBBBBB */ - .extern MterpConstString - EXPORT_PC - lh a0, 2(rPC) # a0 <- bbbb (low) - lh a4, 4(rPC) # a4 <- BBBB (high) - srl a1, rINST, 8 # a1 <- AA - ins a0, a4, 16, 16 # a0 <- BBBBbbbb - daddu a2, rFP, OFF_FP_SHADOWFRAME - move a3, rSELF - jal MterpConstString # (index, tgt_reg, shadow_frame, self) - PREFETCH_INST 3 # load rINST - bnez v0, MterpPossibleException # let reference interpreter deal with it. - ADVANCE 3 # advance rPC - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_const_wide.S b/runtime/interpreter/mterp/mips64/op_const_wide.S deleted file mode 100644 index 7c4a99acac..0000000000 --- a/runtime/interpreter/mterp/mips64/op_const_wide.S +++ /dev/null @@ -1,14 +0,0 @@ -%def op_const_wide(): - /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ - srl a4, rINST, 8 # a4 <- AA - lh a0, 2(rPC) # a0 <- bbbb (low) - lh a1, 4(rPC) # a1 <- BBBB (low middle) - lh a2, 6(rPC) # a2 <- hhhh (high middle) - lh a3, 8(rPC) # a3 <- HHHH (high) - FETCH_ADVANCE_INST 5 # advance rPC, load rINST - ins a0, a1, 16, 16 # a0 = BBBBbbbb - ins a2, a3, 16, 16 # a2 = HHHHhhhh - dinsu a0, a2, 32, 32 # a0 = HHHHhhhhBBBBbbbb - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a4 # vAA <- +HHHHhhhhBBBBbbbb - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_const_wide_16.S b/runtime/interpreter/mterp/mips64/op_const_wide_16.S deleted file mode 100644 index 65f30682a7..0000000000 --- a/runtime/interpreter/mterp/mips64/op_const_wide_16.S +++ /dev/null @@ -1,8 +0,0 @@ -%def op_const_wide_16(): - /* const-wide/16 vAA, #+BBBB */ - srl a2, rINST, 8 # a2 <- AA - lh a0, 2(rPC) # a0 <- sign-extended BBBB - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vAA <- +BBBB - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_const_wide_32.S b/runtime/interpreter/mterp/mips64/op_const_wide_32.S deleted file mode 100644 index 39fa0f9c02..0000000000 --- a/runtime/interpreter/mterp/mips64/op_const_wide_32.S +++ /dev/null @@ -1,10 +0,0 @@ -%def op_const_wide_32(): - /* const-wide/32 vAA, #+BBBBbbbb */ - srl a2, rINST, 8 # a2 <- AA - lh a0, 2(rPC) # a0 <- bbbb (low) - lh a1, 4(rPC) # a1 <- BBBB (high) - FETCH_ADVANCE_INST 3 # advance rPC, load rINST - ins a0, a1, 16, 16 # a0 = BBBBbbbb - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vAA <- +BBBBbbbb - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_const_wide_high16.S b/runtime/interpreter/mterp/mips64/op_const_wide_high16.S deleted file mode 100644 index 7c538c135d..0000000000 --- a/runtime/interpreter/mterp/mips64/op_const_wide_high16.S +++ /dev/null @@ -1,9 +0,0 @@ -%def op_const_wide_high16(): - /* const-wide/high16 vAA, #+BBBB000000000000 */ - srl a2, rINST, 8 # a2 <- AA - lh a0, 2(rPC) # a0 <- BBBB - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - dsll32 a0, a0, 16 # a0 <- BBBB000000000000 - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vAA <- +BBBB000000000000 - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_div_double.S b/runtime/interpreter/mterp/mips64/op_div_double.S deleted file mode 100644 index c134dfb738..0000000000 --- a/runtime/interpreter/mterp/mips64/op_div_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_double(): -% fbinopWide(instr="div.d f0, f0, f1") diff --git a/runtime/interpreter/mterp/mips64/op_div_double_2addr.S b/runtime/interpreter/mterp/mips64/op_div_double_2addr.S deleted file mode 100644 index 6ac1d757dc..0000000000 --- a/runtime/interpreter/mterp/mips64/op_div_double_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_double_2addr(): -% fbinopWide2addr(instr="div.d f0, f0, f1") diff --git a/runtime/interpreter/mterp/mips64/op_div_float.S b/runtime/interpreter/mterp/mips64/op_div_float.S deleted file mode 100644 index 97530321b7..0000000000 --- a/runtime/interpreter/mterp/mips64/op_div_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_float(): -% fbinop(instr="div.s f0, f0, f1") diff --git a/runtime/interpreter/mterp/mips64/op_div_float_2addr.S b/runtime/interpreter/mterp/mips64/op_div_float_2addr.S deleted file mode 100644 index 53421ce295..0000000000 --- a/runtime/interpreter/mterp/mips64/op_div_float_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_float_2addr(): -% fbinop2addr(instr="div.s f0, f0, f1") diff --git a/runtime/interpreter/mterp/mips64/op_div_int.S b/runtime/interpreter/mterp/mips64/op_div_int.S deleted file mode 100644 index da9bfcbdb0..0000000000 --- a/runtime/interpreter/mterp/mips64/op_div_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_int(): -% binop(instr="div a0, a0, a1", chkzero="1") diff --git a/runtime/interpreter/mterp/mips64/op_div_int_2addr.S b/runtime/interpreter/mterp/mips64/op_div_int_2addr.S deleted file mode 100644 index 7c9444277e..0000000000 --- a/runtime/interpreter/mterp/mips64/op_div_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_int_2addr(): -% binop2addr(instr="div a0, a0, a1", chkzero="1") diff --git a/runtime/interpreter/mterp/mips64/op_div_int_lit16.S b/runtime/interpreter/mterp/mips64/op_div_int_lit16.S deleted file mode 100644 index 4afe80e07d..0000000000 --- a/runtime/interpreter/mterp/mips64/op_div_int_lit16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_int_lit16(): -% binopLit16(instr="div a0, a0, a1", chkzero="1") diff --git a/runtime/interpreter/mterp/mips64/op_div_int_lit8.S b/runtime/interpreter/mterp/mips64/op_div_int_lit8.S deleted file mode 100644 index 7e2df1b312..0000000000 --- a/runtime/interpreter/mterp/mips64/op_div_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_int_lit8(): -% binopLit8(instr="div a0, a0, a1", chkzero="1") diff --git a/runtime/interpreter/mterp/mips64/op_div_long.S b/runtime/interpreter/mterp/mips64/op_div_long.S deleted file mode 100644 index 93c21874ba..0000000000 --- a/runtime/interpreter/mterp/mips64/op_div_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_long(): -% binopWide(instr="ddiv a0, a0, a1", chkzero="1") diff --git a/runtime/interpreter/mterp/mips64/op_div_long_2addr.S b/runtime/interpreter/mterp/mips64/op_div_long_2addr.S deleted file mode 100644 index 74ecb20154..0000000000 --- a/runtime/interpreter/mterp/mips64/op_div_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_long_2addr(): -% binopWide2addr(instr="ddiv a0, a0, a1", chkzero="1") diff --git a/runtime/interpreter/mterp/mips64/op_double_to_float.S b/runtime/interpreter/mterp/mips64/op_double_to_float.S deleted file mode 100644 index f19b47fcae..0000000000 --- a/runtime/interpreter/mterp/mips64/op_double_to_float.S +++ /dev/null @@ -1,9 +0,0 @@ -%def op_double_to_float(): - /* - * Conversion from or to floating-point happens in a floating-point register. - * Therefore we load the input and store the output into or from a - * floating-point register irrespective of the type. - */ -% fcvtHeader(suffix="_DOUBLE", valreg="f0") - cvt.s.d f0, f0 -% fcvtFooter(suffix="_FLOAT", valreg="f0") diff --git a/runtime/interpreter/mterp/mips64/op_double_to_int.S b/runtime/interpreter/mterp/mips64/op_double_to_int.S deleted file mode 100644 index ba370a26bb..0000000000 --- a/runtime/interpreter/mterp/mips64/op_double_to_int.S +++ /dev/null @@ -1,4 +0,0 @@ -%def op_double_to_int(): -% fcvtHeader(suffix="_DOUBLE", valreg="f0") - trunc.w.d f0, f0 -% fcvtFooter(suffix="_FLOAT", valreg="f0") diff --git a/runtime/interpreter/mterp/mips64/op_double_to_long.S b/runtime/interpreter/mterp/mips64/op_double_to_long.S deleted file mode 100644 index 1050a725ab..0000000000 --- a/runtime/interpreter/mterp/mips64/op_double_to_long.S +++ /dev/null @@ -1,4 +0,0 @@ -%def op_double_to_long(): -% fcvtHeader(suffix="_DOUBLE", valreg="f0") - trunc.l.d f0, f0 -% fcvtFooter(suffix="_DOUBLE", valreg="f0") diff --git a/runtime/interpreter/mterp/mips64/op_fill_array_data.S b/runtime/interpreter/mterp/mips64/op_fill_array_data.S deleted file mode 100644 index 5ccff911c9..0000000000 --- a/runtime/interpreter/mterp/mips64/op_fill_array_data.S +++ /dev/null @@ -1,15 +0,0 @@ -%def op_fill_array_data(): - /* fill-array-data vAA, +BBBBBBBB */ - .extern MterpFillArrayData - EXPORT_PC - lh a1, 2(rPC) # a1 <- bbbb (lo) - lh a0, 4(rPC) # a0 <- BBBB (hi) - srl a3, rINST, 8 # a3 <- AA - ins a1, a0, 16, 16 # a1 <- BBBBbbbb - GET_VREG_U a0, a3 # a0 <- vAA (array object) - dlsa a1, a1, rPC, 1 # a1 <- PC + BBBBbbbb*2 (array data off.) - jal MterpFillArrayData # (obj, payload) - beqzc v0, MterpPossibleException # exception? - FETCH_ADVANCE_INST 3 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_filled_new_array.S b/runtime/interpreter/mterp/mips64/op_filled_new_array.S deleted file mode 100644 index d86ce16cce..0000000000 --- a/runtime/interpreter/mterp/mips64/op_filled_new_array.S +++ /dev/null @@ -1,18 +0,0 @@ -%def op_filled_new_array(helper="MterpFilledNewArray"): - /* - * Create a new array with elements filled from registers. - * - * for: filled-new-array, filled-new-array/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class//CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, type//BBBB */ - .extern $helper - EXPORT_PC - daddu a0, rFP, OFF_FP_SHADOWFRAME - move a1, rPC - move a2, rSELF - jal $helper - beqzc v0, MterpPossibleException - FETCH_ADVANCE_INST 3 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_filled_new_array_range.S b/runtime/interpreter/mterp/mips64/op_filled_new_array_range.S deleted file mode 100644 index 1667de149a..0000000000 --- a/runtime/interpreter/mterp/mips64/op_filled_new_array_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_filled_new_array_range(): -% op_filled_new_array(helper="MterpFilledNewArrayRange") diff --git a/runtime/interpreter/mterp/mips64/op_float_to_double.S b/runtime/interpreter/mterp/mips64/op_float_to_double.S deleted file mode 100644 index feebdd8b1d..0000000000 --- a/runtime/interpreter/mterp/mips64/op_float_to_double.S +++ /dev/null @@ -1,9 +0,0 @@ -%def op_float_to_double(): - /* - * Conversion from or to floating-point happens in a floating-point register. - * Therefore we load the input and store the output into or from a - * floating-point register irrespective of the type. - */ -% fcvtHeader(suffix="_FLOAT", valreg="f0") - cvt.d.s f0, f0 -% fcvtFooter(suffix="_DOUBLE", valreg="f0") diff --git a/runtime/interpreter/mterp/mips64/op_float_to_int.S b/runtime/interpreter/mterp/mips64/op_float_to_int.S deleted file mode 100644 index cbfe85339c..0000000000 --- a/runtime/interpreter/mterp/mips64/op_float_to_int.S +++ /dev/null @@ -1,4 +0,0 @@ -%def op_float_to_int(): -% fcvtHeader(suffix="_FLOAT", valreg="f0") - trunc.w.s f0, f0 -% fcvtFooter(suffix="_FLOAT", valreg="f0") diff --git a/runtime/interpreter/mterp/mips64/op_float_to_long.S b/runtime/interpreter/mterp/mips64/op_float_to_long.S deleted file mode 100644 index ccf23b1006..0000000000 --- a/runtime/interpreter/mterp/mips64/op_float_to_long.S +++ /dev/null @@ -1,4 +0,0 @@ -%def op_float_to_long(): -% fcvtHeader(suffix="_FLOAT", valreg="f0") - trunc.l.s f0, f0 -% fcvtFooter(suffix="_DOUBLE", valreg="f0") diff --git a/runtime/interpreter/mterp/mips64/op_goto.S b/runtime/interpreter/mterp/mips64/op_goto.S deleted file mode 100644 index 371bae7d1c..0000000000 --- a/runtime/interpreter/mterp/mips64/op_goto.S +++ /dev/null @@ -1,11 +0,0 @@ -%def op_goto(): - /* - * Unconditional branch, 8-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto +AA */ - srl rINST, rINST, 8 - seb rINST, rINST # rINST <- offset (sign-extended AA) - b MterpCommonTakenBranchNoFlags diff --git a/runtime/interpreter/mterp/mips64/op_goto_16.S b/runtime/interpreter/mterp/mips64/op_goto_16.S deleted file mode 100644 index 3b0b52a0ce..0000000000 --- a/runtime/interpreter/mterp/mips64/op_goto_16.S +++ /dev/null @@ -1,10 +0,0 @@ -%def op_goto_16(): - /* - * Unconditional branch, 16-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto/16 +AAAA */ - lh rINST, 2(rPC) # rINST <- offset (sign-extended AAAA) - b MterpCommonTakenBranchNoFlags diff --git a/runtime/interpreter/mterp/mips64/op_goto_32.S b/runtime/interpreter/mterp/mips64/op_goto_32.S deleted file mode 100644 index d48f0a04d5..0000000000 --- a/runtime/interpreter/mterp/mips64/op_goto_32.S +++ /dev/null @@ -1,15 +0,0 @@ -%def op_goto_32(): - /* - * Unconditional branch, 32-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - * - * Unlike most opcodes, this one is allowed to branch to itself, so - * our "backward branch" test must be "<=0" instead of "<0". - */ - /* goto/32 +AAAAAAAA */ - lh rINST, 2(rPC) # rINST <- aaaa (low) - lh a1, 4(rPC) # a1 <- AAAA (high) - ins rINST, a1, 16, 16 # rINST <- offset (sign-extended AAAAaaaa) - b MterpCommonTakenBranchNoFlags diff --git a/runtime/interpreter/mterp/mips64/op_if_eq.S b/runtime/interpreter/mterp/mips64/op_if_eq.S deleted file mode 100644 index da58674fd4..0000000000 --- a/runtime/interpreter/mterp/mips64/op_if_eq.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_eq(): -% bincmp(condition="eq") diff --git a/runtime/interpreter/mterp/mips64/op_if_eqz.S b/runtime/interpreter/mterp/mips64/op_if_eqz.S deleted file mode 100644 index 0639664d47..0000000000 --- a/runtime/interpreter/mterp/mips64/op_if_eqz.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_eqz(): -% zcmp(condition="eq") diff --git a/runtime/interpreter/mterp/mips64/op_if_ge.S b/runtime/interpreter/mterp/mips64/op_if_ge.S deleted file mode 100644 index 5b6ed2f994..0000000000 --- a/runtime/interpreter/mterp/mips64/op_if_ge.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_ge(): -% bincmp(condition="ge") diff --git a/runtime/interpreter/mterp/mips64/op_if_gez.S b/runtime/interpreter/mterp/mips64/op_if_gez.S deleted file mode 100644 index ea6cda71fb..0000000000 --- a/runtime/interpreter/mterp/mips64/op_if_gez.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_gez(): -% zcmp(condition="ge") diff --git a/runtime/interpreter/mterp/mips64/op_if_gt.S b/runtime/interpreter/mterp/mips64/op_if_gt.S deleted file mode 100644 index 201decff1a..0000000000 --- a/runtime/interpreter/mterp/mips64/op_if_gt.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_gt(): -% bincmp(condition="gt") diff --git a/runtime/interpreter/mterp/mips64/op_if_gtz.S b/runtime/interpreter/mterp/mips64/op_if_gtz.S deleted file mode 100644 index 1fdbb6e8d2..0000000000 --- a/runtime/interpreter/mterp/mips64/op_if_gtz.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_gtz(): -% zcmp(condition="gt") diff --git a/runtime/interpreter/mterp/mips64/op_if_le.S b/runtime/interpreter/mterp/mips64/op_if_le.S deleted file mode 100644 index e6024f2b3e..0000000000 --- a/runtime/interpreter/mterp/mips64/op_if_le.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_le(): -% bincmp(condition="le") diff --git a/runtime/interpreter/mterp/mips64/op_if_lez.S b/runtime/interpreter/mterp/mips64/op_if_lez.S deleted file mode 100644 index 62c0d2cd39..0000000000 --- a/runtime/interpreter/mterp/mips64/op_if_lez.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_lez(): -% zcmp(condition="le") diff --git a/runtime/interpreter/mterp/mips64/op_if_lt.S b/runtime/interpreter/mterp/mips64/op_if_lt.S deleted file mode 100644 index 4ef22fd798..0000000000 --- a/runtime/interpreter/mterp/mips64/op_if_lt.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_lt(): -% bincmp(condition="lt") diff --git a/runtime/interpreter/mterp/mips64/op_if_ltz.S b/runtime/interpreter/mterp/mips64/op_if_ltz.S deleted file mode 100644 index 84b2d0b53a..0000000000 --- a/runtime/interpreter/mterp/mips64/op_if_ltz.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_ltz(): -% zcmp(condition="lt") diff --git a/runtime/interpreter/mterp/mips64/op_if_ne.S b/runtime/interpreter/mterp/mips64/op_if_ne.S deleted file mode 100644 index ec3a688b29..0000000000 --- a/runtime/interpreter/mterp/mips64/op_if_ne.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_ne(): -% bincmp(condition="ne") diff --git a/runtime/interpreter/mterp/mips64/op_if_nez.S b/runtime/interpreter/mterp/mips64/op_if_nez.S deleted file mode 100644 index 7009c3acaa..0000000000 --- a/runtime/interpreter/mterp/mips64/op_if_nez.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_nez(): -% zcmp(condition="ne") diff --git a/runtime/interpreter/mterp/mips64/op_iget.S b/runtime/interpreter/mterp/mips64/op_iget.S deleted file mode 100644 index d09edc0a17..0000000000 --- a/runtime/interpreter/mterp/mips64/op_iget.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget(is_object="0", helper="MterpIGetU32"): -% field(helper=helper) diff --git a/runtime/interpreter/mterp/mips64/op_iget_boolean.S b/runtime/interpreter/mterp/mips64/op_iget_boolean.S deleted file mode 100644 index cb8edeec77..0000000000 --- a/runtime/interpreter/mterp/mips64/op_iget_boolean.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_boolean(): -% op_iget(helper="MterpIGetU8") diff --git a/runtime/interpreter/mterp/mips64/op_iget_boolean_quick.S b/runtime/interpreter/mterp/mips64/op_iget_boolean_quick.S deleted file mode 100644 index f3d2cb1e97..0000000000 --- a/runtime/interpreter/mterp/mips64/op_iget_boolean_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_boolean_quick(): -% op_iget_quick(load="lbu") diff --git a/runtime/interpreter/mterp/mips64/op_iget_byte.S b/runtime/interpreter/mterp/mips64/op_iget_byte.S deleted file mode 100644 index 2b87fb16b5..0000000000 --- a/runtime/interpreter/mterp/mips64/op_iget_byte.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_byte(): -% op_iget(helper="MterpIGetI8") diff --git a/runtime/interpreter/mterp/mips64/op_iget_byte_quick.S b/runtime/interpreter/mterp/mips64/op_iget_byte_quick.S deleted file mode 100644 index ddb469b3de..0000000000 --- a/runtime/interpreter/mterp/mips64/op_iget_byte_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_byte_quick(): -% op_iget_quick(load="lb") diff --git a/runtime/interpreter/mterp/mips64/op_iget_char.S b/runtime/interpreter/mterp/mips64/op_iget_char.S deleted file mode 100644 index 001bd03e2b..0000000000 --- a/runtime/interpreter/mterp/mips64/op_iget_char.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_char(): -% op_iget(helper="MterpIGetU16") diff --git a/runtime/interpreter/mterp/mips64/op_iget_char_quick.S b/runtime/interpreter/mterp/mips64/op_iget_char_quick.S deleted file mode 100644 index ef0b350d4e..0000000000 --- a/runtime/interpreter/mterp/mips64/op_iget_char_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_char_quick(): -% op_iget_quick(load="lhu") diff --git a/runtime/interpreter/mterp/mips64/op_iget_object.S b/runtime/interpreter/mterp/mips64/op_iget_object.S deleted file mode 100644 index 4e5f769547..0000000000 --- a/runtime/interpreter/mterp/mips64/op_iget_object.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_object(): -% op_iget(is_object="1", helper="MterpIGetObj") diff --git a/runtime/interpreter/mterp/mips64/op_iget_object_quick.S b/runtime/interpreter/mterp/mips64/op_iget_object_quick.S deleted file mode 100644 index 518b747e87..0000000000 --- a/runtime/interpreter/mterp/mips64/op_iget_object_quick.S +++ /dev/null @@ -1,17 +0,0 @@ -%def op_iget_object_quick(): - /* For: iget-object-quick */ - /* op vA, vB, offset//CCCC */ - .extern artIGetObjectFromMterp - srl a2, rINST, 12 # a2 <- B - lhu a1, 2(rPC) # a1 <- field byte offset - EXPORT_PC - GET_VREG_U a0, a2 # a0 <- object we're operating on - jal artIGetObjectFromMterp # (obj, offset) - ld a3, THREAD_EXCEPTION_OFFSET(rSELF) - ext a2, rINST, 8, 4 # a2 <- A - PREFETCH_INST 2 - bnez a3, MterpPossibleException # bail out - SET_VREG_OBJECT v0, a2 # fp[A] <- v0 - ADVANCE 2 # advance rPC - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_iget_quick.S b/runtime/interpreter/mterp/mips64/op_iget_quick.S deleted file mode 100644 index eb597969aa..0000000000 --- a/runtime/interpreter/mterp/mips64/op_iget_quick.S +++ /dev/null @@ -1,14 +0,0 @@ -%def op_iget_quick(load="lw"): - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset//CCCC */ - srl a2, rINST, 12 # a2 <- B - lhu a1, 2(rPC) # a1 <- field byte offset - GET_VREG_U a3, a2 # a3 <- object we're operating on - ext a4, rINST, 8, 4 # a4 <- A - daddu a1, a1, a3 - beqz a3, common_errNullObject # object was null - $load a0, 0(a1) # a0 <- obj.field - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - SET_VREG a0, a4 # fp[A] <- a0 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_iget_short.S b/runtime/interpreter/mterp/mips64/op_iget_short.S deleted file mode 100644 index a62c4d998f..0000000000 --- a/runtime/interpreter/mterp/mips64/op_iget_short.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_short(): -% op_iget(helper="MterpIGetI16") diff --git a/runtime/interpreter/mterp/mips64/op_iget_short_quick.S b/runtime/interpreter/mterp/mips64/op_iget_short_quick.S deleted file mode 100644 index 5957cb4600..0000000000 --- a/runtime/interpreter/mterp/mips64/op_iget_short_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_short_quick(): -% op_iget_quick(load="lh") diff --git a/runtime/interpreter/mterp/mips64/op_iget_wide.S b/runtime/interpreter/mterp/mips64/op_iget_wide.S deleted file mode 100644 index 9643cc3403..0000000000 --- a/runtime/interpreter/mterp/mips64/op_iget_wide.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_wide(): -% op_iget(helper="MterpIGetU64") diff --git a/runtime/interpreter/mterp/mips64/op_iget_wide_quick.S b/runtime/interpreter/mterp/mips64/op_iget_wide_quick.S deleted file mode 100644 index e914e0d446..0000000000 --- a/runtime/interpreter/mterp/mips64/op_iget_wide_quick.S +++ /dev/null @@ -1,15 +0,0 @@ -%def op_iget_wide_quick(): - /* iget-wide-quick vA, vB, offset//CCCC */ - srl a2, rINST, 12 # a2 <- B - lhu a4, 2(rPC) # a4 <- field byte offset - GET_VREG_U a3, a2 # a3 <- object we're operating on - ext a2, rINST, 8, 4 # a2 <- A - beqz a3, common_errNullObject # object was null - daddu a4, a3, a4 # create direct pointer - lw a0, 0(a4) - lw a1, 4(a4) - dinsu a0, a1, 32, 32 - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - SET_VREG_WIDE a0, a2 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_instance_of.S b/runtime/interpreter/mterp/mips64/op_instance_of.S deleted file mode 100644 index 1929944d32..0000000000 --- a/runtime/interpreter/mterp/mips64/op_instance_of.S +++ /dev/null @@ -1,24 +0,0 @@ -%def op_instance_of(): - /* - * Check to see if an object reference is an instance of a class. - * - * Most common situation is a non-null object, being compared against - * an already-resolved class. - */ - /* instance-of vA, vB, class//CCCC */ - .extern MterpInstanceOf - EXPORT_PC - lhu a0, 2(rPC) # a0 <- CCCC - srl a1, rINST, 12 # a1 <- B - dlsa a1, a1, rFP, 2 # a1 <- &object - ld a2, OFF_FP_METHOD(rFP) # a2 <- method - move a3, rSELF # a3 <- self - jal MterpInstanceOf # (index, &obj, method, self) - ld a1, THREAD_EXCEPTION_OFFSET(rSELF) - ext a2, rINST, 8, 4 # a2 <- A - PREFETCH_INST 2 - bnez a1, MterpException - ADVANCE 2 # advance rPC - SET_VREG v0, a2 # vA <- v0 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_int_to_byte.S b/runtime/interpreter/mterp/mips64/op_int_to_byte.S deleted file mode 100644 index 47440c6f3a..0000000000 --- a/runtime/interpreter/mterp/mips64/op_int_to_byte.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_int_to_byte(): -% unop(instr="seb a0, a0") diff --git a/runtime/interpreter/mterp/mips64/op_int_to_char.S b/runtime/interpreter/mterp/mips64/op_int_to_char.S deleted file mode 100644 index bea4e9e81b..0000000000 --- a/runtime/interpreter/mterp/mips64/op_int_to_char.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_int_to_char(): -% unop(instr="and a0, a0, 0xffff") diff --git a/runtime/interpreter/mterp/mips64/op_int_to_double.S b/runtime/interpreter/mterp/mips64/op_int_to_double.S deleted file mode 100644 index 6cc83ae282..0000000000 --- a/runtime/interpreter/mterp/mips64/op_int_to_double.S +++ /dev/null @@ -1,9 +0,0 @@ -%def op_int_to_double(): - /* - * Conversion from or to floating-point happens in a floating-point register. - * Therefore we load the input and store the output into or from a - * floating-point register irrespective of the type. - */ -% fcvtHeader(suffix="_FLOAT", valreg="f0") - cvt.d.w f0, f0 -% fcvtFooter(suffix="_DOUBLE", valreg="f0") diff --git a/runtime/interpreter/mterp/mips64/op_int_to_float.S b/runtime/interpreter/mterp/mips64/op_int_to_float.S deleted file mode 100644 index 837f8f9df3..0000000000 --- a/runtime/interpreter/mterp/mips64/op_int_to_float.S +++ /dev/null @@ -1,9 +0,0 @@ -%def op_int_to_float(): - /* - * Conversion from or to floating-point happens in a floating-point register. - * Therefore we load the input and store the output into or from a - * floating-point register irrespective of the type. - */ -% fcvtHeader(suffix="_FLOAT", valreg="f0") - cvt.s.w f0, f0 -% fcvtFooter(suffix="_FLOAT", valreg="f0") diff --git a/runtime/interpreter/mterp/mips64/op_int_to_long.S b/runtime/interpreter/mterp/mips64/op_int_to_long.S deleted file mode 100644 index c0cfd72f46..0000000000 --- a/runtime/interpreter/mterp/mips64/op_int_to_long.S +++ /dev/null @@ -1,9 +0,0 @@ -%def op_int_to_long(): - /* int-to-long vA, vB */ - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a3 # a0 <- vB (sign-extended to 64 bits) - ext a2, rINST, 8, 4 # a2 <- A - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vA <- vB - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_int_to_short.S b/runtime/interpreter/mterp/mips64/op_int_to_short.S deleted file mode 100644 index 3d90de3e6a..0000000000 --- a/runtime/interpreter/mterp/mips64/op_int_to_short.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_int_to_short(): -% unop(instr="seh a0, a0") diff --git a/runtime/interpreter/mterp/mips64/op_invoke_custom.S b/runtime/interpreter/mterp/mips64/op_invoke_custom.S deleted file mode 100644 index 4bba9ee524..0000000000 --- a/runtime/interpreter/mterp/mips64/op_invoke_custom.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_custom(): -% invoke(helper="MterpInvokeCustom") diff --git a/runtime/interpreter/mterp/mips64/op_invoke_custom_range.S b/runtime/interpreter/mterp/mips64/op_invoke_custom_range.S deleted file mode 100644 index 57e61af1fa..0000000000 --- a/runtime/interpreter/mterp/mips64/op_invoke_custom_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_custom_range(): -% invoke(helper="MterpInvokeCustomRange") diff --git a/runtime/interpreter/mterp/mips64/op_invoke_direct.S b/runtime/interpreter/mterp/mips64/op_invoke_direct.S deleted file mode 100644 index d3139cf39b..0000000000 --- a/runtime/interpreter/mterp/mips64/op_invoke_direct.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_direct(): -% invoke(helper="MterpInvokeDirect") diff --git a/runtime/interpreter/mterp/mips64/op_invoke_direct_range.S b/runtime/interpreter/mterp/mips64/op_invoke_direct_range.S deleted file mode 100644 index b4a161f48b..0000000000 --- a/runtime/interpreter/mterp/mips64/op_invoke_direct_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_direct_range(): -% invoke(helper="MterpInvokeDirectRange") diff --git a/runtime/interpreter/mterp/mips64/op_invoke_interface.S b/runtime/interpreter/mterp/mips64/op_invoke_interface.S deleted file mode 100644 index b064126253..0000000000 --- a/runtime/interpreter/mterp/mips64/op_invoke_interface.S +++ /dev/null @@ -1,9 +0,0 @@ -%def op_invoke_interface(): -% invoke(helper="MterpInvokeInterface") - /* - * Handle an interface method call. - * - * for: invoke-interface, invoke-interface/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ diff --git a/runtime/interpreter/mterp/mips64/op_invoke_interface_range.S b/runtime/interpreter/mterp/mips64/op_invoke_interface_range.S deleted file mode 100644 index 2989115377..0000000000 --- a/runtime/interpreter/mterp/mips64/op_invoke_interface_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_interface_range(): -% invoke(helper="MterpInvokeInterfaceRange") diff --git a/runtime/interpreter/mterp/mips64/op_invoke_polymorphic.S b/runtime/interpreter/mterp/mips64/op_invoke_polymorphic.S deleted file mode 100644 index ce61f5aa0e..0000000000 --- a/runtime/interpreter/mterp/mips64/op_invoke_polymorphic.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_polymorphic(): -% invoke_polymorphic(helper="MterpInvokePolymorphic") diff --git a/runtime/interpreter/mterp/mips64/op_invoke_polymorphic_range.S b/runtime/interpreter/mterp/mips64/op_invoke_polymorphic_range.S deleted file mode 100644 index 16731bdb40..0000000000 --- a/runtime/interpreter/mterp/mips64/op_invoke_polymorphic_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_polymorphic_range(): -% invoke_polymorphic(helper="MterpInvokePolymorphicRange") diff --git a/runtime/interpreter/mterp/mips64/op_invoke_static.S b/runtime/interpreter/mterp/mips64/op_invoke_static.S deleted file mode 100644 index 8b104a66b0..0000000000 --- a/runtime/interpreter/mterp/mips64/op_invoke_static.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_static(): -% invoke(helper="MterpInvokeStatic") diff --git a/runtime/interpreter/mterp/mips64/op_invoke_static_range.S b/runtime/interpreter/mterp/mips64/op_invoke_static_range.S deleted file mode 100644 index e0a546c92b..0000000000 --- a/runtime/interpreter/mterp/mips64/op_invoke_static_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_static_range(): -% invoke(helper="MterpInvokeStaticRange") diff --git a/runtime/interpreter/mterp/mips64/op_invoke_super.S b/runtime/interpreter/mterp/mips64/op_invoke_super.S deleted file mode 100644 index 3c34c9942e..0000000000 --- a/runtime/interpreter/mterp/mips64/op_invoke_super.S +++ /dev/null @@ -1,9 +0,0 @@ -%def op_invoke_super(): -% invoke(helper="MterpInvokeSuper") - /* - * Handle a "super" method call. - * - * for: invoke-super, invoke-super/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ diff --git a/runtime/interpreter/mterp/mips64/op_invoke_super_range.S b/runtime/interpreter/mterp/mips64/op_invoke_super_range.S deleted file mode 100644 index caeafaa13c..0000000000 --- a/runtime/interpreter/mterp/mips64/op_invoke_super_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_super_range(): -% invoke(helper="MterpInvokeSuperRange") diff --git a/runtime/interpreter/mterp/mips64/op_invoke_virtual.S b/runtime/interpreter/mterp/mips64/op_invoke_virtual.S deleted file mode 100644 index 249177b813..0000000000 --- a/runtime/interpreter/mterp/mips64/op_invoke_virtual.S +++ /dev/null @@ -1,9 +0,0 @@ -%def op_invoke_virtual(): -% invoke(helper="MterpInvokeVirtual") - /* - * Handle a virtual method call. - * - * for: invoke-virtual, invoke-virtual/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ diff --git a/runtime/interpreter/mterp/mips64/op_invoke_virtual_quick.S b/runtime/interpreter/mterp/mips64/op_invoke_virtual_quick.S deleted file mode 100644 index ea72c171ec..0000000000 --- a/runtime/interpreter/mterp/mips64/op_invoke_virtual_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_virtual_quick(): -% invoke(helper="MterpInvokeVirtualQuick") diff --git a/runtime/interpreter/mterp/mips64/op_invoke_virtual_range.S b/runtime/interpreter/mterp/mips64/op_invoke_virtual_range.S deleted file mode 100644 index baa0779593..0000000000 --- a/runtime/interpreter/mterp/mips64/op_invoke_virtual_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_virtual_range(): -% invoke(helper="MterpInvokeVirtualRange") diff --git a/runtime/interpreter/mterp/mips64/op_invoke_virtual_range_quick.S b/runtime/interpreter/mterp/mips64/op_invoke_virtual_range_quick.S deleted file mode 100644 index 1d961a0781..0000000000 --- a/runtime/interpreter/mterp/mips64/op_invoke_virtual_range_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_virtual_range_quick(): -% invoke(helper="MterpInvokeVirtualQuickRange") diff --git a/runtime/interpreter/mterp/mips64/op_iput.S b/runtime/interpreter/mterp/mips64/op_iput.S deleted file mode 100644 index e5351baf55..0000000000 --- a/runtime/interpreter/mterp/mips64/op_iput.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput(is_object="0", helper="MterpIPutU32"): -% field(helper=helper) diff --git a/runtime/interpreter/mterp/mips64/op_iput_boolean.S b/runtime/interpreter/mterp/mips64/op_iput_boolean.S deleted file mode 100644 index 9eb849877b..0000000000 --- a/runtime/interpreter/mterp/mips64/op_iput_boolean.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_boolean(): -% op_iput(helper="MterpIPutU8") diff --git a/runtime/interpreter/mterp/mips64/op_iput_boolean_quick.S b/runtime/interpreter/mterp/mips64/op_iput_boolean_quick.S deleted file mode 100644 index 3d818a5a69..0000000000 --- a/runtime/interpreter/mterp/mips64/op_iput_boolean_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_boolean_quick(): -% op_iput_quick(store="sb") diff --git a/runtime/interpreter/mterp/mips64/op_iput_byte.S b/runtime/interpreter/mterp/mips64/op_iput_byte.S deleted file mode 100644 index 4b74f9fb0e..0000000000 --- a/runtime/interpreter/mterp/mips64/op_iput_byte.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_byte(): -% op_iput(helper="MterpIPutI8") diff --git a/runtime/interpreter/mterp/mips64/op_iput_byte_quick.S b/runtime/interpreter/mterp/mips64/op_iput_byte_quick.S deleted file mode 100644 index 06dc24e095..0000000000 --- a/runtime/interpreter/mterp/mips64/op_iput_byte_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_byte_quick(): -% op_iput_quick(store="sb") diff --git a/runtime/interpreter/mterp/mips64/op_iput_char.S b/runtime/interpreter/mterp/mips64/op_iput_char.S deleted file mode 100644 index 64a249fc12..0000000000 --- a/runtime/interpreter/mterp/mips64/op_iput_char.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_char(): -% op_iput(helper="MterpIPutU16") diff --git a/runtime/interpreter/mterp/mips64/op_iput_char_quick.S b/runtime/interpreter/mterp/mips64/op_iput_char_quick.S deleted file mode 100644 index 3b6af5b9fe..0000000000 --- a/runtime/interpreter/mterp/mips64/op_iput_char_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_char_quick(): -% op_iput_quick(store="sh") diff --git a/runtime/interpreter/mterp/mips64/op_iput_object.S b/runtime/interpreter/mterp/mips64/op_iput_object.S deleted file mode 100644 index 131edd5dbd..0000000000 --- a/runtime/interpreter/mterp/mips64/op_iput_object.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_object(): -% op_iput(is_object="1", helper="MterpIPutObj") diff --git a/runtime/interpreter/mterp/mips64/op_iput_object_quick.S b/runtime/interpreter/mterp/mips64/op_iput_object_quick.S deleted file mode 100644 index 0a15857398..0000000000 --- a/runtime/interpreter/mterp/mips64/op_iput_object_quick.S +++ /dev/null @@ -1,11 +0,0 @@ -%def op_iput_object_quick(): - .extern MterpIputObjectQuick - EXPORT_PC - daddu a0, rFP, OFF_FP_SHADOWFRAME - move a1, rPC - move a2, rINST - jal MterpIputObjectQuick - beqzc v0, MterpException - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_iput_quick.S b/runtime/interpreter/mterp/mips64/op_iput_quick.S deleted file mode 100644 index b38b75317f..0000000000 --- a/runtime/interpreter/mterp/mips64/op_iput_quick.S +++ /dev/null @@ -1,14 +0,0 @@ -%def op_iput_quick(store="sw"): - /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */ - /* op vA, vB, offset//CCCC */ - srl a2, rINST, 12 # a2 <- B - lhu a1, 2(rPC) # a1 <- field byte offset - GET_VREG_U a3, a2 # a3 <- fp[B], the object pointer - ext a2, rINST, 8, 4 # a2 <- A - beqz a3, common_errNullObject # object was null - GET_VREG a0, a2 # a0 <- fp[A] - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - daddu a1, a1, a3 - $store a0, 0(a1) # obj.field <- a0 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_iput_short.S b/runtime/interpreter/mterp/mips64/op_iput_short.S deleted file mode 100644 index e631a3b259..0000000000 --- a/runtime/interpreter/mterp/mips64/op_iput_short.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_short(): -% op_iput(helper="MterpIPutI16") diff --git a/runtime/interpreter/mterp/mips64/op_iput_short_quick.S b/runtime/interpreter/mterp/mips64/op_iput_short_quick.S deleted file mode 100644 index fade093fc1..0000000000 --- a/runtime/interpreter/mterp/mips64/op_iput_short_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_short_quick(): -% op_iput_quick(store="sh") diff --git a/runtime/interpreter/mterp/mips64/op_iput_wide.S b/runtime/interpreter/mterp/mips64/op_iput_wide.S deleted file mode 100644 index 2f34fd39f9..0000000000 --- a/runtime/interpreter/mterp/mips64/op_iput_wide.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_wide(): -% op_iput(helper="MterpIPutU64") diff --git a/runtime/interpreter/mterp/mips64/op_iput_wide_quick.S b/runtime/interpreter/mterp/mips64/op_iput_wide_quick.S deleted file mode 100644 index 240f90200a..0000000000 --- a/runtime/interpreter/mterp/mips64/op_iput_wide_quick.S +++ /dev/null @@ -1,15 +0,0 @@ -%def op_iput_wide_quick(): - /* iput-wide-quick vA, vB, offset//CCCC */ - srl a2, rINST, 12 # a2 <- B - lhu a3, 2(rPC) # a3 <- field byte offset - GET_VREG_U a2, a2 # a2 <- fp[B], the object pointer - ext a0, rINST, 8, 4 # a0 <- A - beqz a2, common_errNullObject # object was null - GET_VREG_WIDE a0, a0 # a0 <- fp[A] - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - daddu a1, a2, a3 # create a direct pointer - sw a0, 0(a1) - dsrl32 a0, a0, 0 - sw a0, 4(a1) - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_long_to_double.S b/runtime/interpreter/mterp/mips64/op_long_to_double.S deleted file mode 100644 index f4d346ca29..0000000000 --- a/runtime/interpreter/mterp/mips64/op_long_to_double.S +++ /dev/null @@ -1,9 +0,0 @@ -%def op_long_to_double(): - /* - * Conversion from or to floating-point happens in a floating-point register. - * Therefore we load the input and store the output into or from a - * floating-point register irrespective of the type. - */ -% fcvtHeader(suffix="_DOUBLE", valreg="f0") - cvt.d.l f0, f0 -% fcvtFooter(suffix="_DOUBLE", valreg="f0") diff --git a/runtime/interpreter/mterp/mips64/op_long_to_float.S b/runtime/interpreter/mterp/mips64/op_long_to_float.S deleted file mode 100644 index 3c616d15e5..0000000000 --- a/runtime/interpreter/mterp/mips64/op_long_to_float.S +++ /dev/null @@ -1,9 +0,0 @@ -%def op_long_to_float(): - /* - * Conversion from or to floating-point happens in a floating-point register. - * Therefore we load the input and store the output into or from a - * floating-point register irrespective of the type. - */ -% fcvtHeader(suffix="_DOUBLE", valreg="f0") - cvt.s.l f0, f0 -% fcvtFooter(suffix="_FLOAT", valreg="f0") diff --git a/runtime/interpreter/mterp/mips64/op_long_to_int.S b/runtime/interpreter/mterp/mips64/op_long_to_int.S deleted file mode 100644 index eacb8f59ec..0000000000 --- a/runtime/interpreter/mterp/mips64/op_long_to_int.S +++ /dev/null @@ -1,3 +0,0 @@ -%def op_long_to_int(): -/* we ignore the high word, making this equivalent to a 32-bit reg move */ -% op_move() diff --git a/runtime/interpreter/mterp/mips64/op_monitor_enter.S b/runtime/interpreter/mterp/mips64/op_monitor_enter.S deleted file mode 100644 index 47184f9a7b..0000000000 --- a/runtime/interpreter/mterp/mips64/op_monitor_enter.S +++ /dev/null @@ -1,15 +0,0 @@ -%def op_monitor_enter(): - /* - * Synchronize on an object. - */ - /* monitor-enter vAA */ - .extern artLockObjectFromCode - EXPORT_PC - srl a2, rINST, 8 # a2 <- AA - GET_VREG_U a0, a2 # a0 <- vAA (object) - move a1, rSELF # a1 <- self - jal artLockObjectFromCode - bnezc v0, MterpException - FETCH_ADVANCE_INST 1 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_monitor_exit.S b/runtime/interpreter/mterp/mips64/op_monitor_exit.S deleted file mode 100644 index 58f8541aa2..0000000000 --- a/runtime/interpreter/mterp/mips64/op_monitor_exit.S +++ /dev/null @@ -1,19 +0,0 @@ -%def op_monitor_exit(): - /* - * Unlock an object. - * - * Exceptions that occur when unlocking a monitor need to appear as - * if they happened at the following instruction. See the Dalvik - * instruction spec. - */ - /* monitor-exit vAA */ - .extern artUnlockObjectFromCode - EXPORT_PC - srl a2, rINST, 8 # a2 <- AA - GET_VREG_U a0, a2 # a0 <- vAA (object) - move a1, rSELF # a1 <- self - jal artUnlockObjectFromCode # v0 <- success for unlock(self, obj) - bnezc v0, MterpException - FETCH_ADVANCE_INST 1 # before throw: advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_move.S b/runtime/interpreter/mterp/mips64/op_move.S deleted file mode 100644 index c6de44ccf5..0000000000 --- a/runtime/interpreter/mterp/mips64/op_move.S +++ /dev/null @@ -1,14 +0,0 @@ -%def op_move(is_object="0"): - /* for move, move-object, long-to-int */ - /* op vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_VREG a0, a3 # a0 <- vB - GET_INST_OPCODE v0 # extract opcode from rINST - .if $is_object - SET_VREG_OBJECT a0, a2 # vA <- vB - .else - SET_VREG a0, a2 # vA <- vB - .endif - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_move_16.S b/runtime/interpreter/mterp/mips64/op_move_16.S deleted file mode 100644 index 68b7037939..0000000000 --- a/runtime/interpreter/mterp/mips64/op_move_16.S +++ /dev/null @@ -1,14 +0,0 @@ -%def op_move_16(is_object="0"): - /* for: move/16, move-object/16 */ - /* op vAAAA, vBBBB */ - lhu a3, 4(rPC) # a3 <- BBBB - lhu a2, 2(rPC) # a2 <- AAAA - FETCH_ADVANCE_INST 3 # advance rPC, load rINST - GET_VREG a0, a3 # a0 <- vBBBB - GET_INST_OPCODE v0 # extract opcode from rINST - .if $is_object - SET_VREG_OBJECT a0, a2 # vAAAA <- vBBBB - .else - SET_VREG a0, a2 # vAAAA <- vBBBB - .endif - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_move_exception.S b/runtime/interpreter/mterp/mips64/op_move_exception.S deleted file mode 100644 index 8f441c7f7a..0000000000 --- a/runtime/interpreter/mterp/mips64/op_move_exception.S +++ /dev/null @@ -1,9 +0,0 @@ -%def op_move_exception(): - /* move-exception vAA */ - srl a2, rINST, 8 # a2 <- AA - ld a0, THREAD_EXCEPTION_OFFSET(rSELF) # load exception obj - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - SET_VREG_OBJECT a0, a2 # vAA <- exception obj - GET_INST_OPCODE v0 # extract opcode from rINST - sd zero, THREAD_EXCEPTION_OFFSET(rSELF) # clear exception - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_move_from16.S b/runtime/interpreter/mterp/mips64/op_move_from16.S deleted file mode 100644 index f4c254c682..0000000000 --- a/runtime/interpreter/mterp/mips64/op_move_from16.S +++ /dev/null @@ -1,14 +0,0 @@ -%def op_move_from16(is_object="0"): - /* for: move/from16, move-object/from16 */ - /* op vAA, vBBBB */ - lhu a3, 2(rPC) # a3 <- BBBB - srl a2, rINST, 8 # a2 <- AA - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_VREG a0, a3 # a0 <- vBBBB - GET_INST_OPCODE v0 # extract opcode from rINST - .if $is_object - SET_VREG_OBJECT a0, a2 # vAA <- vBBBB - .else - SET_VREG a0, a2 # vAA <- vBBBB - .endif - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_move_object.S b/runtime/interpreter/mterp/mips64/op_move_object.S deleted file mode 100644 index dbb4d59710..0000000000 --- a/runtime/interpreter/mterp/mips64/op_move_object.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_move_object(): -% op_move(is_object="1") diff --git a/runtime/interpreter/mterp/mips64/op_move_object_16.S b/runtime/interpreter/mterp/mips64/op_move_object_16.S deleted file mode 100644 index 40120379d5..0000000000 --- a/runtime/interpreter/mterp/mips64/op_move_object_16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_move_object_16(): -% op_move_16(is_object="1") diff --git a/runtime/interpreter/mterp/mips64/op_move_object_from16.S b/runtime/interpreter/mterp/mips64/op_move_object_from16.S deleted file mode 100644 index c82698e81e..0000000000 --- a/runtime/interpreter/mterp/mips64/op_move_object_from16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_move_object_from16(): -% op_move_from16(is_object="1") diff --git a/runtime/interpreter/mterp/mips64/op_move_result.S b/runtime/interpreter/mterp/mips64/op_move_result.S deleted file mode 100644 index 9d4bdfe0f0..0000000000 --- a/runtime/interpreter/mterp/mips64/op_move_result.S +++ /dev/null @@ -1,14 +0,0 @@ -%def op_move_result(is_object="0"): - /* for: move-result, move-result-object */ - /* op vAA */ - srl a2, rINST, 8 # a2 <- AA - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - ld a0, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType - lw a0, 0(a0) # a0 <- result.i - GET_INST_OPCODE v0 # extract opcode from rINST - .if $is_object - SET_VREG_OBJECT a0, a2 # vAA <- result - .else - SET_VREG a0, a2 # vAA <- result - .endif - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_move_result_object.S b/runtime/interpreter/mterp/mips64/op_move_result_object.S deleted file mode 100644 index 87aea2646a..0000000000 --- a/runtime/interpreter/mterp/mips64/op_move_result_object.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_move_result_object(): -% op_move_result(is_object="1") diff --git a/runtime/interpreter/mterp/mips64/op_move_result_wide.S b/runtime/interpreter/mterp/mips64/op_move_result_wide.S deleted file mode 100644 index 048ab3fa94..0000000000 --- a/runtime/interpreter/mterp/mips64/op_move_result_wide.S +++ /dev/null @@ -1,10 +0,0 @@ -%def op_move_result_wide(): - /* for: move-result-wide */ - /* op vAA */ - srl a2, rINST, 8 # a2 <- AA - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - ld a0, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType - ld a0, 0(a0) # a0 <- result.j - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vAA <- result - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_move_wide.S b/runtime/interpreter/mterp/mips64/op_move_wide.S deleted file mode 100644 index 94cfa47584..0000000000 --- a/runtime/interpreter/mterp/mips64/op_move_wide.S +++ /dev/null @@ -1,10 +0,0 @@ -%def op_move_wide(): - /* move-wide vA, vB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - ext a3, rINST, 12, 4 # a3 <- B - ext a2, rINST, 8, 4 # a2 <- A - GET_VREG_WIDE a0, a3 # a0 <- vB - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vA <- vB - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_move_wide_16.S b/runtime/interpreter/mterp/mips64/op_move_wide_16.S deleted file mode 100644 index f3a923e33c..0000000000 --- a/runtime/interpreter/mterp/mips64/op_move_wide_16.S +++ /dev/null @@ -1,10 +0,0 @@ -%def op_move_wide_16(): - /* move-wide/16 vAAAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - lhu a3, 4(rPC) # a3 <- BBBB - lhu a2, 2(rPC) # a2 <- AAAA - GET_VREG_WIDE a0, a3 # a0 <- vBBBB - FETCH_ADVANCE_INST 3 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vAAAA <- vBBBB - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_move_wide_from16.S b/runtime/interpreter/mterp/mips64/op_move_wide_from16.S deleted file mode 100644 index 822035e8fa..0000000000 --- a/runtime/interpreter/mterp/mips64/op_move_wide_from16.S +++ /dev/null @@ -1,10 +0,0 @@ -%def op_move_wide_from16(): - /* move-wide/from16 vAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - lhu a3, 2(rPC) # a3 <- BBBB - srl a2, rINST, 8 # a2 <- AA - GET_VREG_WIDE a0, a3 # a0 <- vBBBB - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vAA <- vBBBB - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_mul_double.S b/runtime/interpreter/mterp/mips64/op_mul_double.S deleted file mode 100644 index 84cf5af93e..0000000000 --- a/runtime/interpreter/mterp/mips64/op_mul_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_mul_double(): -% fbinopWide(instr="mul.d f0, f0, f1") diff --git a/runtime/interpreter/mterp/mips64/op_mul_double_2addr.S b/runtime/interpreter/mterp/mips64/op_mul_double_2addr.S deleted file mode 100644 index 1ba6740c18..0000000000 --- a/runtime/interpreter/mterp/mips64/op_mul_double_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_mul_double_2addr(): -% fbinopWide2addr(instr="mul.d f0, f0, f1") diff --git a/runtime/interpreter/mterp/mips64/op_mul_float.S b/runtime/interpreter/mterp/mips64/op_mul_float.S deleted file mode 100644 index 16594ede76..0000000000 --- a/runtime/interpreter/mterp/mips64/op_mul_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_mul_float(): -% fbinop(instr="mul.s f0, f0, f1") diff --git a/runtime/interpreter/mterp/mips64/op_mul_float_2addr.S b/runtime/interpreter/mterp/mips64/op_mul_float_2addr.S deleted file mode 100644 index 318ddab015..0000000000 --- a/runtime/interpreter/mterp/mips64/op_mul_float_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_mul_float_2addr(): -% fbinop2addr(instr="mul.s f0, f0, f1") diff --git a/runtime/interpreter/mterp/mips64/op_mul_int.S b/runtime/interpreter/mterp/mips64/op_mul_int.S deleted file mode 100644 index 34e42f0783..0000000000 --- a/runtime/interpreter/mterp/mips64/op_mul_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_mul_int(): -% binop(instr="mul a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_mul_int_2addr.S b/runtime/interpreter/mterp/mips64/op_mul_int_2addr.S deleted file mode 100644 index 0224a6e2c1..0000000000 --- a/runtime/interpreter/mterp/mips64/op_mul_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_mul_int_2addr(): -% binop2addr(instr="mul a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_mul_int_lit16.S b/runtime/interpreter/mterp/mips64/op_mul_int_lit16.S deleted file mode 100644 index 935d632e11..0000000000 --- a/runtime/interpreter/mterp/mips64/op_mul_int_lit16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_mul_int_lit16(): -% binopLit16(instr="mul a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_mul_int_lit8.S b/runtime/interpreter/mterp/mips64/op_mul_int_lit8.S deleted file mode 100644 index 4a2bfca5c1..0000000000 --- a/runtime/interpreter/mterp/mips64/op_mul_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_mul_int_lit8(): -% binopLit8(instr="mul a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_mul_long.S b/runtime/interpreter/mterp/mips64/op_mul_long.S deleted file mode 100644 index 296138d66e..0000000000 --- a/runtime/interpreter/mterp/mips64/op_mul_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_mul_long(): -% binopWide(instr="dmul a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_mul_long_2addr.S b/runtime/interpreter/mterp/mips64/op_mul_long_2addr.S deleted file mode 100644 index a99eaa49b8..0000000000 --- a/runtime/interpreter/mterp/mips64/op_mul_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_mul_long_2addr(): -% binopWide2addr(instr="dmul a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_neg_double.S b/runtime/interpreter/mterp/mips64/op_neg_double.S deleted file mode 100644 index aa24c32791..0000000000 --- a/runtime/interpreter/mterp/mips64/op_neg_double.S +++ /dev/null @@ -1,4 +0,0 @@ -%def op_neg_double(): -% fcvtHeader(suffix="_DOUBLE", valreg="f0") - neg.d f0, f0 -% fcvtFooter(suffix="_DOUBLE", valreg="f0") diff --git a/runtime/interpreter/mterp/mips64/op_neg_float.S b/runtime/interpreter/mterp/mips64/op_neg_float.S deleted file mode 100644 index 1554a4db3d..0000000000 --- a/runtime/interpreter/mterp/mips64/op_neg_float.S +++ /dev/null @@ -1,4 +0,0 @@ -%def op_neg_float(): -% fcvtHeader(suffix="_FLOAT", valreg="f0") - neg.s f0, f0 -% fcvtFooter(suffix="_FLOAT", valreg="f0") diff --git a/runtime/interpreter/mterp/mips64/op_neg_int.S b/runtime/interpreter/mterp/mips64/op_neg_int.S deleted file mode 100644 index 9243a2154f..0000000000 --- a/runtime/interpreter/mterp/mips64/op_neg_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_neg_int(): -% unop(instr="subu a0, zero, a0") diff --git a/runtime/interpreter/mterp/mips64/op_neg_long.S b/runtime/interpreter/mterp/mips64/op_neg_long.S deleted file mode 100644 index ad9d5599e5..0000000000 --- a/runtime/interpreter/mterp/mips64/op_neg_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_neg_long(): -% unopWide(instr="dsubu a0, zero, a0") diff --git a/runtime/interpreter/mterp/mips64/op_new_array.S b/runtime/interpreter/mterp/mips64/op_new_array.S deleted file mode 100644 index 8da7d832fc..0000000000 --- a/runtime/interpreter/mterp/mips64/op_new_array.S +++ /dev/null @@ -1,20 +0,0 @@ -%def op_new_array(): - /* - * Allocate an array of objects, specified with the array class - * and a count. - * - * The verifier guarantees that this is an array class, so we don't - * check for it here. - */ - /* new-array vA, vB, class//CCCC */ - .extern MterpNewArray - EXPORT_PC - daddu a0, rFP, OFF_FP_SHADOWFRAME - move a1, rPC - move a2, rINST - move a3, rSELF - jal MterpNewArray - beqzc v0, MterpPossibleException - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_new_instance.S b/runtime/interpreter/mterp/mips64/op_new_instance.S deleted file mode 100644 index a14fd8f8e7..0000000000 --- a/runtime/interpreter/mterp/mips64/op_new_instance.S +++ /dev/null @@ -1,15 +0,0 @@ -%def op_new_instance(): - /* - * Create a new instance of a class. - */ - /* new-instance vAA, class//BBBB */ - .extern MterpNewInstance - EXPORT_PC - daddu a0, rFP, OFF_FP_SHADOWFRAME - move a1, rSELF - move a2, rINST - jal MterpNewInstance # (shadow_frame, self, inst_data) - beqzc v0, MterpPossibleException - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_nop.S b/runtime/interpreter/mterp/mips64/op_nop.S deleted file mode 100644 index 925fe4c979..0000000000 --- a/runtime/interpreter/mterp/mips64/op_nop.S +++ /dev/null @@ -1,4 +0,0 @@ -%def op_nop(): - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_not_int.S b/runtime/interpreter/mterp/mips64/op_not_int.S deleted file mode 100644 index 2fc1dd76fa..0000000000 --- a/runtime/interpreter/mterp/mips64/op_not_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_not_int(): -% unop(instr="nor a0, zero, a0") diff --git a/runtime/interpreter/mterp/mips64/op_not_long.S b/runtime/interpreter/mterp/mips64/op_not_long.S deleted file mode 100644 index a551b3144c..0000000000 --- a/runtime/interpreter/mterp/mips64/op_not_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_not_long(): -% unopWide(instr="nor a0, zero, a0") diff --git a/runtime/interpreter/mterp/mips64/op_or_int.S b/runtime/interpreter/mterp/mips64/op_or_int.S deleted file mode 100644 index df60be5896..0000000000 --- a/runtime/interpreter/mterp/mips64/op_or_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_or_int(): -% binop(instr="or a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_or_int_2addr.S b/runtime/interpreter/mterp/mips64/op_or_int_2addr.S deleted file mode 100644 index c202e6799b..0000000000 --- a/runtime/interpreter/mterp/mips64/op_or_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_or_int_2addr(): -% binop2addr(instr="or a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_or_int_lit16.S b/runtime/interpreter/mterp/mips64/op_or_int_lit16.S deleted file mode 100644 index 09961e8845..0000000000 --- a/runtime/interpreter/mterp/mips64/op_or_int_lit16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_or_int_lit16(): -% binopLit16(instr="or a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_or_int_lit8.S b/runtime/interpreter/mterp/mips64/op_or_int_lit8.S deleted file mode 100644 index 1bd6809d90..0000000000 --- a/runtime/interpreter/mterp/mips64/op_or_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_or_int_lit8(): -% binopLit8(instr="or a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_or_long.S b/runtime/interpreter/mterp/mips64/op_or_long.S deleted file mode 100644 index 65d4c44c5a..0000000000 --- a/runtime/interpreter/mterp/mips64/op_or_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_or_long(): -% binopWide(instr="or a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_or_long_2addr.S b/runtime/interpreter/mterp/mips64/op_or_long_2addr.S deleted file mode 100644 index 5ad0113d4a..0000000000 --- a/runtime/interpreter/mterp/mips64/op_or_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_or_long_2addr(): -% binopWide2addr(instr="or a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_packed_switch.S b/runtime/interpreter/mterp/mips64/op_packed_switch.S deleted file mode 100644 index 36c21077ab..0000000000 --- a/runtime/interpreter/mterp/mips64/op_packed_switch.S +++ /dev/null @@ -1,21 +0,0 @@ -%def op_packed_switch(func="MterpDoPackedSwitch"): - /* - * Handle a packed-switch or sparse-switch instruction. In both cases - * we decode it and hand it off to a helper function. - * - * We don't really expect backward branches in a switch statement, but - * they're perfectly legal, so we check for them here. - * - * for: packed-switch, sparse-switch - */ - /* op vAA, +BBBBBBBB */ - .extern $func - lh a0, 2(rPC) # a0 <- bbbb (lo) - lh a1, 4(rPC) # a1 <- BBBB (hi) - srl a3, rINST, 8 # a3 <- AA - ins a0, a1, 16, 16 # a0 <- BBBBbbbb - GET_VREG a1, a3 # a1 <- vAA - dlsa a0, a0, rPC, 1 # a0 <- PC + BBBBbbbb*2 - jal $func # v0 <- code-unit branch offset - move rINST, v0 - b MterpCommonTakenBranchNoFlags diff --git a/runtime/interpreter/mterp/mips64/op_rem_double.S b/runtime/interpreter/mterp/mips64/op_rem_double.S deleted file mode 100644 index 16ad357a0a..0000000000 --- a/runtime/interpreter/mterp/mips64/op_rem_double.S +++ /dev/null @@ -1,13 +0,0 @@ -%def op_rem_double(): - /* rem-double vAA, vBB, vCC */ - .extern fmod - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_DOUBLE f12, a2 # f12 <- vBB - GET_VREG_DOUBLE f13, a3 # f13 <- vCC - jal fmod # f0 <- f12 op f13 - srl a4, rINST, 8 # a4 <- AA - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_DOUBLE f0, a4 # vAA <- f0 - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_rem_double_2addr.S b/runtime/interpreter/mterp/mips64/op_rem_double_2addr.S deleted file mode 100644 index 230d70b37e..0000000000 --- a/runtime/interpreter/mterp/mips64/op_rem_double_2addr.S +++ /dev/null @@ -1,13 +0,0 @@ -%def op_rem_double_2addr(): - /* rem-double/2addr vA, vB */ - .extern fmod - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_DOUBLE f12, a2 # f12 <- vA - GET_VREG_DOUBLE f13, a3 # f13 <- vB - jal fmod # f0 <- f12 op f13 - ext a2, rINST, 8, 4 # a2 <- A - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_DOUBLE f0, a2 # vA <- f0 - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_rem_float.S b/runtime/interpreter/mterp/mips64/op_rem_float.S deleted file mode 100644 index 08c65164cd..0000000000 --- a/runtime/interpreter/mterp/mips64/op_rem_float.S +++ /dev/null @@ -1,13 +0,0 @@ -%def op_rem_float(): - /* rem-float vAA, vBB, vCC */ - .extern fmodf - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_FLOAT f12, a2 # f12 <- vBB - GET_VREG_FLOAT f13, a3 # f13 <- vCC - jal fmodf # f0 <- f12 op f13 - srl a4, rINST, 8 # a4 <- AA - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_FLOAT f0, a4 # vAA <- f0 - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_rem_float_2addr.S b/runtime/interpreter/mterp/mips64/op_rem_float_2addr.S deleted file mode 100644 index d35a0f4623..0000000000 --- a/runtime/interpreter/mterp/mips64/op_rem_float_2addr.S +++ /dev/null @@ -1,13 +0,0 @@ -%def op_rem_float_2addr(): - /* rem-float/2addr vA, vB */ - .extern fmodf - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_FLOAT f12, a2 # f12 <- vA - GET_VREG_FLOAT f13, a3 # f13 <- vB - jal fmodf # f0 <- f12 op f13 - ext a2, rINST, 8, 4 # a2 <- A - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_FLOAT f0, a2 # vA <- f0 - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_rem_int.S b/runtime/interpreter/mterp/mips64/op_rem_int.S deleted file mode 100644 index 542fe286ed..0000000000 --- a/runtime/interpreter/mterp/mips64/op_rem_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_rem_int(): -% binop(instr="mod a0, a0, a1", chkzero="1") diff --git a/runtime/interpreter/mterp/mips64/op_rem_int_2addr.S b/runtime/interpreter/mterp/mips64/op_rem_int_2addr.S deleted file mode 100644 index da405767e7..0000000000 --- a/runtime/interpreter/mterp/mips64/op_rem_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_rem_int_2addr(): -% binop2addr(instr="mod a0, a0, a1", chkzero="1") diff --git a/runtime/interpreter/mterp/mips64/op_rem_int_lit16.S b/runtime/interpreter/mterp/mips64/op_rem_int_lit16.S deleted file mode 100644 index 2dc5173486..0000000000 --- a/runtime/interpreter/mterp/mips64/op_rem_int_lit16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_rem_int_lit16(): -% binopLit16(instr="mod a0, a0, a1", chkzero="1") diff --git a/runtime/interpreter/mterp/mips64/op_rem_int_lit8.S b/runtime/interpreter/mterp/mips64/op_rem_int_lit8.S deleted file mode 100644 index 4ea0ace7b5..0000000000 --- a/runtime/interpreter/mterp/mips64/op_rem_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_rem_int_lit8(): -% binopLit8(instr="mod a0, a0, a1", chkzero="1") diff --git a/runtime/interpreter/mterp/mips64/op_rem_long.S b/runtime/interpreter/mterp/mips64/op_rem_long.S deleted file mode 100644 index a10984ad0b..0000000000 --- a/runtime/interpreter/mterp/mips64/op_rem_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_rem_long(): -% binopWide(instr="dmod a0, a0, a1", chkzero="1") diff --git a/runtime/interpreter/mterp/mips64/op_rem_long_2addr.S b/runtime/interpreter/mterp/mips64/op_rem_long_2addr.S deleted file mode 100644 index 3cac4fba50..0000000000 --- a/runtime/interpreter/mterp/mips64/op_rem_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_rem_long_2addr(): -% binopWide2addr(instr="dmod a0, a0, a1", chkzero="1") diff --git a/runtime/interpreter/mterp/mips64/op_return.S b/runtime/interpreter/mterp/mips64/op_return.S deleted file mode 100644 index bfdf76a8e5..0000000000 --- a/runtime/interpreter/mterp/mips64/op_return.S +++ /dev/null @@ -1,19 +0,0 @@ -%def op_return(instr="GET_VREG"): - /* - * Return a 32-bit value. - * - * for: return (sign-extend), return-object (zero-extend) - */ - /* op vAA */ - .extern MterpThreadFenceForConstructor - .extern MterpSuspendCheck - jal MterpThreadFenceForConstructor - lw ra, THREAD_FLAGS_OFFSET(rSELF) - move a0, rSELF - and ra, ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - beqzc ra, 1f - jal MterpSuspendCheck # (self) -1: - srl a2, rINST, 8 # a2 <- AA - $instr a0, a2 # a0 <- vAA - b MterpReturn diff --git a/runtime/interpreter/mterp/mips64/op_return_object.S b/runtime/interpreter/mterp/mips64/op_return_object.S deleted file mode 100644 index 074c321ef7..0000000000 --- a/runtime/interpreter/mterp/mips64/op_return_object.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_return_object(): -% op_return(instr="GET_VREG_U") diff --git a/runtime/interpreter/mterp/mips64/op_return_void.S b/runtime/interpreter/mterp/mips64/op_return_void.S deleted file mode 100644 index b5aa76cb69..0000000000 --- a/runtime/interpreter/mterp/mips64/op_return_void.S +++ /dev/null @@ -1,12 +0,0 @@ -%def op_return_void(): - .extern MterpThreadFenceForConstructor - .extern MterpSuspendCheck - jal MterpThreadFenceForConstructor - lw ra, THREAD_FLAGS_OFFSET(rSELF) - move a0, rSELF - and ra, ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - beqzc ra, 1f - jal MterpSuspendCheck # (self) -1: - li a0, 0 - b MterpReturn diff --git a/runtime/interpreter/mterp/mips64/op_return_void_no_barrier.S b/runtime/interpreter/mterp/mips64/op_return_void_no_barrier.S deleted file mode 100644 index 0baddbbaaf..0000000000 --- a/runtime/interpreter/mterp/mips64/op_return_void_no_barrier.S +++ /dev/null @@ -1,10 +0,0 @@ -%def op_return_void_no_barrier(): - .extern MterpSuspendCheck - lw ra, THREAD_FLAGS_OFFSET(rSELF) - move a0, rSELF - and ra, ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - beqzc ra, 1f - jal MterpSuspendCheck # (self) -1: - li a0, 0 - b MterpReturn diff --git a/runtime/interpreter/mterp/mips64/op_return_wide.S b/runtime/interpreter/mterp/mips64/op_return_wide.S deleted file mode 100644 index dbcb704eb6..0000000000 --- a/runtime/interpreter/mterp/mips64/op_return_wide.S +++ /dev/null @@ -1,18 +0,0 @@ -%def op_return_wide(): - /* - * Return a 64-bit value. - */ - /* return-wide vAA */ - /* op vAA */ - .extern MterpThreadFenceForConstructor - .extern MterpSuspendCheck - jal MterpThreadFenceForConstructor - lw ra, THREAD_FLAGS_OFFSET(rSELF) - move a0, rSELF - and ra, ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - beqzc ra, 1f - jal MterpSuspendCheck # (self) -1: - srl a2, rINST, 8 # a2 <- AA - GET_VREG_WIDE a0, a2 # a0 <- vAA - b MterpReturn diff --git a/runtime/interpreter/mterp/mips64/op_rsub_int.S b/runtime/interpreter/mterp/mips64/op_rsub_int.S deleted file mode 100644 index 2d61e869e1..0000000000 --- a/runtime/interpreter/mterp/mips64/op_rsub_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_rsub_int(): -% binopLit16(instr="subu a0, a1, a0") diff --git a/runtime/interpreter/mterp/mips64/op_rsub_int_lit8.S b/runtime/interpreter/mterp/mips64/op_rsub_int_lit8.S deleted file mode 100644 index b9b214da94..0000000000 --- a/runtime/interpreter/mterp/mips64/op_rsub_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_rsub_int_lit8(): -% binopLit8(instr="subu a0, a1, a0") diff --git a/runtime/interpreter/mterp/mips64/op_sget.S b/runtime/interpreter/mterp/mips64/op_sget.S deleted file mode 100644 index 8a6a66ab60..0000000000 --- a/runtime/interpreter/mterp/mips64/op_sget.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sget(is_object="0", helper="MterpSGetU32"): -% field(helper=helper) diff --git a/runtime/interpreter/mterp/mips64/op_sget_boolean.S b/runtime/interpreter/mterp/mips64/op_sget_boolean.S deleted file mode 100644 index d9c12c9b28..0000000000 --- a/runtime/interpreter/mterp/mips64/op_sget_boolean.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sget_boolean(): -% op_sget(helper="MterpSGetU8") diff --git a/runtime/interpreter/mterp/mips64/op_sget_byte.S b/runtime/interpreter/mterp/mips64/op_sget_byte.S deleted file mode 100644 index 37c6879cd4..0000000000 --- a/runtime/interpreter/mterp/mips64/op_sget_byte.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sget_byte(): -% op_sget(helper="MterpSGetI8") diff --git a/runtime/interpreter/mterp/mips64/op_sget_char.S b/runtime/interpreter/mterp/mips64/op_sget_char.S deleted file mode 100644 index 003bcd1683..0000000000 --- a/runtime/interpreter/mterp/mips64/op_sget_char.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sget_char(): -% op_sget(helper="MterpSGetU16") diff --git a/runtime/interpreter/mterp/mips64/op_sget_object.S b/runtime/interpreter/mterp/mips64/op_sget_object.S deleted file mode 100644 index 7cf3597f44..0000000000 --- a/runtime/interpreter/mterp/mips64/op_sget_object.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sget_object(): -% op_sget(is_object="1", helper="MterpSGetObj") diff --git a/runtime/interpreter/mterp/mips64/op_sget_short.S b/runtime/interpreter/mterp/mips64/op_sget_short.S deleted file mode 100644 index afacb578d9..0000000000 --- a/runtime/interpreter/mterp/mips64/op_sget_short.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sget_short(): -% op_sget(helper="MterpSGetI16") diff --git a/runtime/interpreter/mterp/mips64/op_sget_wide.S b/runtime/interpreter/mterp/mips64/op_sget_wide.S deleted file mode 100644 index fff2be6945..0000000000 --- a/runtime/interpreter/mterp/mips64/op_sget_wide.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sget_wide(): -% op_sget(helper="MterpSGetU64") diff --git a/runtime/interpreter/mterp/mips64/op_shl_int.S b/runtime/interpreter/mterp/mips64/op_shl_int.S deleted file mode 100644 index efd213c09a..0000000000 --- a/runtime/interpreter/mterp/mips64/op_shl_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shl_int(): -% binop(instr="sll a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_shl_int_2addr.S b/runtime/interpreter/mterp/mips64/op_shl_int_2addr.S deleted file mode 100644 index 0901e6b65a..0000000000 --- a/runtime/interpreter/mterp/mips64/op_shl_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shl_int_2addr(): -% binop2addr(instr="sll a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_shl_int_lit8.S b/runtime/interpreter/mterp/mips64/op_shl_int_lit8.S deleted file mode 100644 index 2263ec70c2..0000000000 --- a/runtime/interpreter/mterp/mips64/op_shl_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shl_int_lit8(): -% binopLit8(instr="sll a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_shl_long.S b/runtime/interpreter/mterp/mips64/op_shl_long.S deleted file mode 100644 index 9ef03d8cfa..0000000000 --- a/runtime/interpreter/mterp/mips64/op_shl_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shl_long(): -% binopWide(instr="dsll a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_shl_long_2addr.S b/runtime/interpreter/mterp/mips64/op_shl_long_2addr.S deleted file mode 100644 index f748c3b045..0000000000 --- a/runtime/interpreter/mterp/mips64/op_shl_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shl_long_2addr(): -% binopWide2addr(instr="dsll a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_shr_int.S b/runtime/interpreter/mterp/mips64/op_shr_int.S deleted file mode 100644 index 8d55e7afa9..0000000000 --- a/runtime/interpreter/mterp/mips64/op_shr_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shr_int(): -% binop(instr="sra a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_shr_int_2addr.S b/runtime/interpreter/mterp/mips64/op_shr_int_2addr.S deleted file mode 100644 index e102baa99f..0000000000 --- a/runtime/interpreter/mterp/mips64/op_shr_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shr_int_2addr(): -% binop2addr(instr="sra a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_shr_int_lit8.S b/runtime/interpreter/mterp/mips64/op_shr_int_lit8.S deleted file mode 100644 index 437c5c49a6..0000000000 --- a/runtime/interpreter/mterp/mips64/op_shr_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shr_int_lit8(): -% binopLit8(instr="sra a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_shr_long.S b/runtime/interpreter/mterp/mips64/op_shr_long.S deleted file mode 100644 index 1be48f299a..0000000000 --- a/runtime/interpreter/mterp/mips64/op_shr_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shr_long(): -% binopWide(instr="dsra a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_shr_long_2addr.S b/runtime/interpreter/mterp/mips64/op_shr_long_2addr.S deleted file mode 100644 index a15861fefd..0000000000 --- a/runtime/interpreter/mterp/mips64/op_shr_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shr_long_2addr(): -% binopWide2addr(instr="dsra a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_sparse_switch.S b/runtime/interpreter/mterp/mips64/op_sparse_switch.S deleted file mode 100644 index b74d7da816..0000000000 --- a/runtime/interpreter/mterp/mips64/op_sparse_switch.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sparse_switch(): -% op_packed_switch(func="MterpDoSparseSwitch") diff --git a/runtime/interpreter/mterp/mips64/op_sput.S b/runtime/interpreter/mterp/mips64/op_sput.S deleted file mode 100644 index cbd6ee96d3..0000000000 --- a/runtime/interpreter/mterp/mips64/op_sput.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sput(is_object="0", helper="MterpSPutU32"): -% field(helper=helper) diff --git a/runtime/interpreter/mterp/mips64/op_sput_boolean.S b/runtime/interpreter/mterp/mips64/op_sput_boolean.S deleted file mode 100644 index 36fba8448b..0000000000 --- a/runtime/interpreter/mterp/mips64/op_sput_boolean.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sput_boolean(): -% op_sput(helper="MterpSPutU8") diff --git a/runtime/interpreter/mterp/mips64/op_sput_byte.S b/runtime/interpreter/mterp/mips64/op_sput_byte.S deleted file mode 100644 index 84ad4a0ff8..0000000000 --- a/runtime/interpreter/mterp/mips64/op_sput_byte.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sput_byte(): -% op_sput(helper="MterpSPutI8") diff --git a/runtime/interpreter/mterp/mips64/op_sput_char.S b/runtime/interpreter/mterp/mips64/op_sput_char.S deleted file mode 100644 index 9b8eeba578..0000000000 --- a/runtime/interpreter/mterp/mips64/op_sput_char.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sput_char(): -% op_sput(helper="MterpSPutU16") diff --git a/runtime/interpreter/mterp/mips64/op_sput_object.S b/runtime/interpreter/mterp/mips64/op_sput_object.S deleted file mode 100644 index 081360c40f..0000000000 --- a/runtime/interpreter/mterp/mips64/op_sput_object.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sput_object(): -% op_sput(is_object="1", helper="MterpSPutObj") diff --git a/runtime/interpreter/mterp/mips64/op_sput_short.S b/runtime/interpreter/mterp/mips64/op_sput_short.S deleted file mode 100644 index ee16513486..0000000000 --- a/runtime/interpreter/mterp/mips64/op_sput_short.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sput_short(): -% op_sput(helper="MterpSPutI16") diff --git a/runtime/interpreter/mterp/mips64/op_sput_wide.S b/runtime/interpreter/mterp/mips64/op_sput_wide.S deleted file mode 100644 index 44c1a188ed..0000000000 --- a/runtime/interpreter/mterp/mips64/op_sput_wide.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sput_wide(): -% op_sput(helper="MterpSPutU64") diff --git a/runtime/interpreter/mterp/mips64/op_sub_double.S b/runtime/interpreter/mterp/mips64/op_sub_double.S deleted file mode 100644 index aeb1b0f038..0000000000 --- a/runtime/interpreter/mterp/mips64/op_sub_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_double(): -% fbinopWide(instr="sub.d f0, f0, f1") diff --git a/runtime/interpreter/mterp/mips64/op_sub_double_2addr.S b/runtime/interpreter/mterp/mips64/op_sub_double_2addr.S deleted file mode 100644 index 03457ac325..0000000000 --- a/runtime/interpreter/mterp/mips64/op_sub_double_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_double_2addr(): -% fbinopWide2addr(instr="sub.d f0, f0, f1") diff --git a/runtime/interpreter/mterp/mips64/op_sub_float.S b/runtime/interpreter/mterp/mips64/op_sub_float.S deleted file mode 100644 index 4afd1adf3e..0000000000 --- a/runtime/interpreter/mterp/mips64/op_sub_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_float(): -% fbinop(instr="sub.s f0, f0, f1") diff --git a/runtime/interpreter/mterp/mips64/op_sub_float_2addr.S b/runtime/interpreter/mterp/mips64/op_sub_float_2addr.S deleted file mode 100644 index b4ade2c163..0000000000 --- a/runtime/interpreter/mterp/mips64/op_sub_float_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_float_2addr(): -% fbinop2addr(instr="sub.s f0, f0, f1") diff --git a/runtime/interpreter/mterp/mips64/op_sub_int.S b/runtime/interpreter/mterp/mips64/op_sub_int.S deleted file mode 100644 index 57f618d65a..0000000000 --- a/runtime/interpreter/mterp/mips64/op_sub_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_int(): -% binop(instr="subu a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_sub_int_2addr.S b/runtime/interpreter/mterp/mips64/op_sub_int_2addr.S deleted file mode 100644 index 445ffca50f..0000000000 --- a/runtime/interpreter/mterp/mips64/op_sub_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_int_2addr(): -% binop2addr(instr="subu a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_sub_long.S b/runtime/interpreter/mterp/mips64/op_sub_long.S deleted file mode 100644 index ba5fe49604..0000000000 --- a/runtime/interpreter/mterp/mips64/op_sub_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_long(): -% binopWide(instr="dsubu a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_sub_long_2addr.S b/runtime/interpreter/mterp/mips64/op_sub_long_2addr.S deleted file mode 100644 index e22b4f6cba..0000000000 --- a/runtime/interpreter/mterp/mips64/op_sub_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_long_2addr(): -% binopWide2addr(instr="dsubu a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_throw.S b/runtime/interpreter/mterp/mips64/op_throw.S deleted file mode 100644 index 7f26d88b2f..0000000000 --- a/runtime/interpreter/mterp/mips64/op_throw.S +++ /dev/null @@ -1,11 +0,0 @@ -%def op_throw(): - /* - * Throw an exception object in the current thread. - */ - /* throw vAA */ - EXPORT_PC - srl a2, rINST, 8 # a2 <- AA - GET_VREG_U a0, a2 # a0 <- vAA (exception object) - beqzc a0, common_errNullObject - sd a0, THREAD_EXCEPTION_OFFSET(rSELF) # thread->exception <- obj - b MterpException diff --git a/runtime/interpreter/mterp/mips64/op_unused_3e.S b/runtime/interpreter/mterp/mips64/op_unused_3e.S deleted file mode 100644 index d889f1a5fb..0000000000 --- a/runtime/interpreter/mterp/mips64/op_unused_3e.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_3e(): -% unused() diff --git a/runtime/interpreter/mterp/mips64/op_unused_3f.S b/runtime/interpreter/mterp/mips64/op_unused_3f.S deleted file mode 100644 index b3ebcfaeaa..0000000000 --- a/runtime/interpreter/mterp/mips64/op_unused_3f.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_3f(): -% unused() diff --git a/runtime/interpreter/mterp/mips64/op_unused_40.S b/runtime/interpreter/mterp/mips64/op_unused_40.S deleted file mode 100644 index 7920fb350f..0000000000 --- a/runtime/interpreter/mterp/mips64/op_unused_40.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_40(): -% unused() diff --git a/runtime/interpreter/mterp/mips64/op_unused_41.S b/runtime/interpreter/mterp/mips64/op_unused_41.S deleted file mode 100644 index 5ed03b8506..0000000000 --- a/runtime/interpreter/mterp/mips64/op_unused_41.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_41(): -% unused() diff --git a/runtime/interpreter/mterp/mips64/op_unused_42.S b/runtime/interpreter/mterp/mips64/op_unused_42.S deleted file mode 100644 index ac32521add..0000000000 --- a/runtime/interpreter/mterp/mips64/op_unused_42.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_42(): -% unused() diff --git a/runtime/interpreter/mterp/mips64/op_unused_43.S b/runtime/interpreter/mterp/mips64/op_unused_43.S deleted file mode 100644 index 33e2aa10f8..0000000000 --- a/runtime/interpreter/mterp/mips64/op_unused_43.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_43(): -% unused() diff --git a/runtime/interpreter/mterp/mips64/op_unused_79.S b/runtime/interpreter/mterp/mips64/op_unused_79.S deleted file mode 100644 index 3c6dafc789..0000000000 --- a/runtime/interpreter/mterp/mips64/op_unused_79.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_79(): -% unused() diff --git a/runtime/interpreter/mterp/mips64/op_unused_7a.S b/runtime/interpreter/mterp/mips64/op_unused_7a.S deleted file mode 100644 index 9c03cd5535..0000000000 --- a/runtime/interpreter/mterp/mips64/op_unused_7a.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_7a(): -% unused() diff --git a/runtime/interpreter/mterp/mips64/op_unused_f3.S b/runtime/interpreter/mterp/mips64/op_unused_f3.S deleted file mode 100644 index ab10b78be2..0000000000 --- a/runtime/interpreter/mterp/mips64/op_unused_f3.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_f3(): -% unused() diff --git a/runtime/interpreter/mterp/mips64/op_unused_f4.S b/runtime/interpreter/mterp/mips64/op_unused_f4.S deleted file mode 100644 index 09229d6d99..0000000000 --- a/runtime/interpreter/mterp/mips64/op_unused_f4.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_f4(): -% unused() diff --git a/runtime/interpreter/mterp/mips64/op_unused_f5.S b/runtime/interpreter/mterp/mips64/op_unused_f5.S deleted file mode 100644 index 0d6149b5fd..0000000000 --- a/runtime/interpreter/mterp/mips64/op_unused_f5.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_f5(): -% unused() diff --git a/runtime/interpreter/mterp/mips64/op_unused_f6.S b/runtime/interpreter/mterp/mips64/op_unused_f6.S deleted file mode 100644 index 117b03de6d..0000000000 --- a/runtime/interpreter/mterp/mips64/op_unused_f6.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_f6(): -% unused() diff --git a/runtime/interpreter/mterp/mips64/op_unused_f7.S b/runtime/interpreter/mterp/mips64/op_unused_f7.S deleted file mode 100644 index 4e3a0f3c9a..0000000000 --- a/runtime/interpreter/mterp/mips64/op_unused_f7.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_f7(): -% unused() diff --git a/runtime/interpreter/mterp/mips64/op_unused_f8.S b/runtime/interpreter/mterp/mips64/op_unused_f8.S deleted file mode 100644 index d1220752d7..0000000000 --- a/runtime/interpreter/mterp/mips64/op_unused_f8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_f8(): -% unused() diff --git a/runtime/interpreter/mterp/mips64/op_unused_f9.S b/runtime/interpreter/mterp/mips64/op_unused_f9.S deleted file mode 100644 index 7d09a0ebcf..0000000000 --- a/runtime/interpreter/mterp/mips64/op_unused_f9.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_f9(): -% unused() diff --git a/runtime/interpreter/mterp/mips64/op_unused_fc.S b/runtime/interpreter/mterp/mips64/op_unused_fc.S deleted file mode 100644 index 06978191eb..0000000000 --- a/runtime/interpreter/mterp/mips64/op_unused_fc.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_fc(): -% unused() diff --git a/runtime/interpreter/mterp/mips64/op_unused_fd.S b/runtime/interpreter/mterp/mips64/op_unused_fd.S deleted file mode 100644 index 4bc2b4bdb6..0000000000 --- a/runtime/interpreter/mterp/mips64/op_unused_fd.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_fd(): -% unused() diff --git a/runtime/interpreter/mterp/mips64/op_ushr_int.S b/runtime/interpreter/mterp/mips64/op_ushr_int.S deleted file mode 100644 index 98d2dfbc9c..0000000000 --- a/runtime/interpreter/mterp/mips64/op_ushr_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_ushr_int(): -% binop(instr="srl a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_ushr_int_2addr.S b/runtime/interpreter/mterp/mips64/op_ushr_int_2addr.S deleted file mode 100644 index 9b89e21643..0000000000 --- a/runtime/interpreter/mterp/mips64/op_ushr_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_ushr_int_2addr(): -% binop2addr(instr="srl a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_ushr_int_lit8.S b/runtime/interpreter/mterp/mips64/op_ushr_int_lit8.S deleted file mode 100644 index 531c30a000..0000000000 --- a/runtime/interpreter/mterp/mips64/op_ushr_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_ushr_int_lit8(): -% binopLit8(instr="srl a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_ushr_long.S b/runtime/interpreter/mterp/mips64/op_ushr_long.S deleted file mode 100644 index e900f76f90..0000000000 --- a/runtime/interpreter/mterp/mips64/op_ushr_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_ushr_long(): -% binopWide(instr="dsrl a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_ushr_long_2addr.S b/runtime/interpreter/mterp/mips64/op_ushr_long_2addr.S deleted file mode 100644 index e13fc75612..0000000000 --- a/runtime/interpreter/mterp/mips64/op_ushr_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_ushr_long_2addr(): -% binopWide2addr(instr="dsrl a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_xor_int.S b/runtime/interpreter/mterp/mips64/op_xor_int.S deleted file mode 100644 index 1379a344e0..0000000000 --- a/runtime/interpreter/mterp/mips64/op_xor_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_xor_int(): -% binop(instr="xor a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_xor_int_2addr.S b/runtime/interpreter/mterp/mips64/op_xor_int_2addr.S deleted file mode 100644 index 6dbe11c3a8..0000000000 --- a/runtime/interpreter/mterp/mips64/op_xor_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_xor_int_2addr(): -% binop2addr(instr="xor a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_xor_int_lit16.S b/runtime/interpreter/mterp/mips64/op_xor_int_lit16.S deleted file mode 100644 index f8cbce04f4..0000000000 --- a/runtime/interpreter/mterp/mips64/op_xor_int_lit16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_xor_int_lit16(): -% binopLit16(instr="xor a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_xor_int_lit8.S b/runtime/interpreter/mterp/mips64/op_xor_int_lit8.S deleted file mode 100644 index 268a43aac8..0000000000 --- a/runtime/interpreter/mterp/mips64/op_xor_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_xor_int_lit8(): -% binopLit8(instr="xor a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_xor_long.S b/runtime/interpreter/mterp/mips64/op_xor_long.S deleted file mode 100644 index 75d4c07984..0000000000 --- a/runtime/interpreter/mterp/mips64/op_xor_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_xor_long(): -% binopWide(instr="xor a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/op_xor_long_2addr.S b/runtime/interpreter/mterp/mips64/op_xor_long_2addr.S deleted file mode 100644 index 2e76613168..0000000000 --- a/runtime/interpreter/mterp/mips64/op_xor_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_xor_long_2addr(): -% binopWide2addr(instr="xor a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/other.S b/runtime/interpreter/mterp/mips64/other.S new file mode 100644 index 0000000000..789efeeaa1 --- /dev/null +++ b/runtime/interpreter/mterp/mips64/other.S @@ -0,0 +1,355 @@ +%def const(helper="UndefinedConstHandler"): + /* const/class vAA, type@BBBB */ + /* const/method-handle vAA, method_handle@BBBB */ + /* const/method-type vAA, proto@BBBB */ + /* const/string vAA, string@@BBBB */ + .extern $helper + EXPORT_PC + lhu a0, 2(rPC) # a0 <- BBBB + srl a1, rINST, 8 # a1 <- AA + daddu a2, rFP, OFF_FP_SHADOWFRAME + move a3, rSELF + jal $helper # (index, tgt_reg, shadow_frame, self) + PREFETCH_INST 2 # load rINST + bnez v0, MterpPossibleException # let reference interpreter deal with it. + ADVANCE 2 # advance rPC + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +%def unused(): +/* + * Bail to reference interpreter to throw. + */ + b MterpFallback + +%def op_const(): + /* const vAA, #+BBBBbbbb */ + srl a2, rINST, 8 # a2 <- AA + lh a0, 2(rPC) # a0 <- bbbb (low) + lh a1, 4(rPC) # a1 <- BBBB (high) + FETCH_ADVANCE_INST 3 # advance rPC, load rINST + ins a0, a1, 16, 16 # a0 = BBBBbbbb + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG a0, a2 # vAA <- +BBBBbbbb + GOTO_OPCODE v0 # jump to next instruction + +%def op_const_16(): + /* const/16 vAA, #+BBBB */ + srl a2, rINST, 8 # a2 <- AA + lh a0, 2(rPC) # a0 <- sign-extended BBBB + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG a0, a2 # vAA <- +BBBB + GOTO_OPCODE v0 # jump to next instruction + +%def op_const_4(): + /* const/4 vA, #+B */ + ext a2, rINST, 8, 4 # a2 <- A + seh a0, rINST # sign extend B in rINST + FETCH_ADVANCE_INST 1 # advance rPC, load rINST + sra a0, a0, 12 # shift B into its final position + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG a0, a2 # vA <- +B + GOTO_OPCODE v0 # jump to next instruction + +%def op_const_class(): +% const(helper="MterpConstClass") + +%def op_const_high16(): + /* const/high16 vAA, #+BBBB0000 */ + srl a2, rINST, 8 # a2 <- AA + lh a0, 2(rPC) # a0 <- BBBB + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + sll a0, a0, 16 # a0 <- BBBB0000 + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG a0, a2 # vAA <- +BBBB0000 + GOTO_OPCODE v0 # jump to next instruction + +%def op_const_method_handle(): +% const(helper="MterpConstMethodHandle") + +%def op_const_method_type(): +% const(helper="MterpConstMethodType") + +%def op_const_string(): +% const(helper="MterpConstString") + +%def op_const_string_jumbo(): + /* const/string vAA, String//BBBBBBBB */ + .extern MterpConstString + EXPORT_PC + lh a0, 2(rPC) # a0 <- bbbb (low) + lh a4, 4(rPC) # a4 <- BBBB (high) + srl a1, rINST, 8 # a1 <- AA + ins a0, a4, 16, 16 # a0 <- BBBBbbbb + daddu a2, rFP, OFF_FP_SHADOWFRAME + move a3, rSELF + jal MterpConstString # (index, tgt_reg, shadow_frame, self) + PREFETCH_INST 3 # load rINST + bnez v0, MterpPossibleException # let reference interpreter deal with it. + ADVANCE 3 # advance rPC + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +%def op_const_wide(): + /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ + srl a4, rINST, 8 # a4 <- AA + lh a0, 2(rPC) # a0 <- bbbb (low) + lh a1, 4(rPC) # a1 <- BBBB (low middle) + lh a2, 6(rPC) # a2 <- hhhh (high middle) + lh a3, 8(rPC) # a3 <- HHHH (high) + FETCH_ADVANCE_INST 5 # advance rPC, load rINST + ins a0, a1, 16, 16 # a0 = BBBBbbbb + ins a2, a3, 16, 16 # a2 = HHHHhhhh + dinsu a0, a2, 32, 32 # a0 = HHHHhhhhBBBBbbbb + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG_WIDE a0, a4 # vAA <- +HHHHhhhhBBBBbbbb + GOTO_OPCODE v0 # jump to next instruction + +%def op_const_wide_16(): + /* const-wide/16 vAA, #+BBBB */ + srl a2, rINST, 8 # a2 <- AA + lh a0, 2(rPC) # a0 <- sign-extended BBBB + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG_WIDE a0, a2 # vAA <- +BBBB + GOTO_OPCODE v0 # jump to next instruction + +%def op_const_wide_32(): + /* const-wide/32 vAA, #+BBBBbbbb */ + srl a2, rINST, 8 # a2 <- AA + lh a0, 2(rPC) # a0 <- bbbb (low) + lh a1, 4(rPC) # a1 <- BBBB (high) + FETCH_ADVANCE_INST 3 # advance rPC, load rINST + ins a0, a1, 16, 16 # a0 = BBBBbbbb + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG_WIDE a0, a2 # vAA <- +BBBBbbbb + GOTO_OPCODE v0 # jump to next instruction + +%def op_const_wide_high16(): + /* const-wide/high16 vAA, #+BBBB000000000000 */ + srl a2, rINST, 8 # a2 <- AA + lh a0, 2(rPC) # a0 <- BBBB + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + dsll32 a0, a0, 16 # a0 <- BBBB000000000000 + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG_WIDE a0, a2 # vAA <- +BBBB000000000000 + GOTO_OPCODE v0 # jump to next instruction + +%def op_monitor_enter(): + /* + * Synchronize on an object. + */ + /* monitor-enter vAA */ + .extern artLockObjectFromCode + EXPORT_PC + srl a2, rINST, 8 # a2 <- AA + GET_VREG_U a0, a2 # a0 <- vAA (object) + move a1, rSELF # a1 <- self + jal artLockObjectFromCode + bnezc v0, MterpException + FETCH_ADVANCE_INST 1 + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +%def op_monitor_exit(): + /* + * Unlock an object. + * + * Exceptions that occur when unlocking a monitor need to appear as + * if they happened at the following instruction. See the Dalvik + * instruction spec. + */ + /* monitor-exit vAA */ + .extern artUnlockObjectFromCode + EXPORT_PC + srl a2, rINST, 8 # a2 <- AA + GET_VREG_U a0, a2 # a0 <- vAA (object) + move a1, rSELF # a1 <- self + jal artUnlockObjectFromCode # v0 <- success for unlock(self, obj) + bnezc v0, MterpException + FETCH_ADVANCE_INST 1 # before throw: advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +%def op_move(is_object="0"): + /* for move, move-object, long-to-int */ + /* op vA, vB */ + ext a2, rINST, 8, 4 # a2 <- A + ext a3, rINST, 12, 4 # a3 <- B + FETCH_ADVANCE_INST 1 # advance rPC, load rINST + GET_VREG a0, a3 # a0 <- vB + GET_INST_OPCODE v0 # extract opcode from rINST + .if $is_object + SET_VREG_OBJECT a0, a2 # vA <- vB + .else + SET_VREG a0, a2 # vA <- vB + .endif + GOTO_OPCODE v0 # jump to next instruction + +%def op_move_16(is_object="0"): + /* for: move/16, move-object/16 */ + /* op vAAAA, vBBBB */ + lhu a3, 4(rPC) # a3 <- BBBB + lhu a2, 2(rPC) # a2 <- AAAA + FETCH_ADVANCE_INST 3 # advance rPC, load rINST + GET_VREG a0, a3 # a0 <- vBBBB + GET_INST_OPCODE v0 # extract opcode from rINST + .if $is_object + SET_VREG_OBJECT a0, a2 # vAAAA <- vBBBB + .else + SET_VREG a0, a2 # vAAAA <- vBBBB + .endif + GOTO_OPCODE v0 # jump to next instruction + +%def op_move_exception(): + /* move-exception vAA */ + srl a2, rINST, 8 # a2 <- AA + ld a0, THREAD_EXCEPTION_OFFSET(rSELF) # load exception obj + FETCH_ADVANCE_INST 1 # advance rPC, load rINST + SET_VREG_OBJECT a0, a2 # vAA <- exception obj + GET_INST_OPCODE v0 # extract opcode from rINST + sd zero, THREAD_EXCEPTION_OFFSET(rSELF) # clear exception + GOTO_OPCODE v0 # jump to next instruction + +%def op_move_from16(is_object="0"): + /* for: move/from16, move-object/from16 */ + /* op vAA, vBBBB */ + lhu a3, 2(rPC) # a3 <- BBBB + srl a2, rINST, 8 # a2 <- AA + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + GET_VREG a0, a3 # a0 <- vBBBB + GET_INST_OPCODE v0 # extract opcode from rINST + .if $is_object + SET_VREG_OBJECT a0, a2 # vAA <- vBBBB + .else + SET_VREG a0, a2 # vAA <- vBBBB + .endif + GOTO_OPCODE v0 # jump to next instruction + +%def op_move_object(): +% op_move(is_object="1") + +%def op_move_object_16(): +% op_move_16(is_object="1") + +%def op_move_object_from16(): +% op_move_from16(is_object="1") + +%def op_move_result(is_object="0"): + /* for: move-result, move-result-object */ + /* op vAA */ + srl a2, rINST, 8 # a2 <- AA + FETCH_ADVANCE_INST 1 # advance rPC, load rINST + ld a0, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType + lw a0, 0(a0) # a0 <- result.i + GET_INST_OPCODE v0 # extract opcode from rINST + .if $is_object + SET_VREG_OBJECT a0, a2 # vAA <- result + .else + SET_VREG a0, a2 # vAA <- result + .endif + GOTO_OPCODE v0 # jump to next instruction + +%def op_move_result_object(): +% op_move_result(is_object="1") + +%def op_move_result_wide(): + /* for: move-result-wide */ + /* op vAA */ + srl a2, rINST, 8 # a2 <- AA + FETCH_ADVANCE_INST 1 # advance rPC, load rINST + ld a0, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType + ld a0, 0(a0) # a0 <- result.j + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG_WIDE a0, a2 # vAA <- result + GOTO_OPCODE v0 # jump to next instruction + +%def op_move_wide(): + /* move-wide vA, vB */ + /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ + ext a3, rINST, 12, 4 # a3 <- B + ext a2, rINST, 8, 4 # a2 <- A + GET_VREG_WIDE a0, a3 # a0 <- vB + FETCH_ADVANCE_INST 1 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG_WIDE a0, a2 # vA <- vB + GOTO_OPCODE v0 # jump to next instruction + +%def op_move_wide_16(): + /* move-wide/16 vAAAA, vBBBB */ + /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ + lhu a3, 4(rPC) # a3 <- BBBB + lhu a2, 2(rPC) # a2 <- AAAA + GET_VREG_WIDE a0, a3 # a0 <- vBBBB + FETCH_ADVANCE_INST 3 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG_WIDE a0, a2 # vAAAA <- vBBBB + GOTO_OPCODE v0 # jump to next instruction + +%def op_move_wide_from16(): + /* move-wide/from16 vAA, vBBBB */ + /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ + lhu a3, 2(rPC) # a3 <- BBBB + srl a2, rINST, 8 # a2 <- AA + GET_VREG_WIDE a0, a3 # a0 <- vBBBB + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG_WIDE a0, a2 # vAA <- vBBBB + GOTO_OPCODE v0 # jump to next instruction + +%def op_nop(): + FETCH_ADVANCE_INST 1 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +%def op_unused_3e(): +% unused() + +%def op_unused_3f(): +% unused() + +%def op_unused_40(): +% unused() + +%def op_unused_41(): +% unused() + +%def op_unused_42(): +% unused() + +%def op_unused_43(): +% unused() + +%def op_unused_79(): +% unused() + +%def op_unused_7a(): +% unused() + +%def op_unused_f3(): +% unused() + +%def op_unused_f4(): +% unused() + +%def op_unused_f5(): +% unused() + +%def op_unused_f6(): +% unused() + +%def op_unused_f7(): +% unused() + +%def op_unused_f8(): +% unused() + +%def op_unused_f9(): +% unused() + +%def op_unused_fc(): +% unused() + +%def op_unused_fd(): +% unused() diff --git a/runtime/interpreter/mterp/mips64/unop.S b/runtime/interpreter/mterp/mips64/unop.S deleted file mode 100644 index 860e6bbb6a..0000000000 --- a/runtime/interpreter/mterp/mips64/unop.S +++ /dev/null @@ -1,18 +0,0 @@ -%def unop(preinstr="", instr=""): - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "a0 = op a0". - * - * for: int-to-byte, int-to-char, int-to-short, - * not-int, neg-int - */ - /* unop vA, vB */ - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a3 # a0 <- vB - ext a2, rINST, 8, 4 # a2 <- A - $preinstr # optional op - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - $instr # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/unopWide.S b/runtime/interpreter/mterp/mips64/unopWide.S deleted file mode 100644 index d0a6f5b766..0000000000 --- a/runtime/interpreter/mterp/mips64/unopWide.S +++ /dev/null @@ -1,17 +0,0 @@ -%def unopWide(preinstr="", instr=""): - /* - * Generic 64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "a0 = op a0". - * - * For: not-long, neg-long - */ - /* unop vA, vB */ - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_WIDE a0, a3 # a0 <- vB - ext a2, rINST, 8, 4 # a2 <- A - $preinstr # optional op - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - $instr # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/unused.S b/runtime/interpreter/mterp/mips64/unused.S deleted file mode 100644 index 3d611d170b..0000000000 --- a/runtime/interpreter/mterp/mips64/unused.S +++ /dev/null @@ -1,5 +0,0 @@ -%def unused(): -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback diff --git a/runtime/interpreter/mterp/mips64/zcmp.S b/runtime/interpreter/mterp/mips64/zcmp.S deleted file mode 100644 index a0d2832514..0000000000 --- a/runtime/interpreter/mterp/mips64/zcmp.S +++ /dev/null @@ -1,18 +0,0 @@ -%def zcmp(condition=""): - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform, e.g. for - * "if-lez" you would use "le". - * - * For: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - srl a2, rINST, 8 # a2 <- AA - lh rINST, 2(rPC) # rINST <- offset (sign-extended BBBB) - GET_VREG a0, a2 # a0 <- vAA - b${condition}zc a0, MterpCommonTakenBranchNoFlags - li v0, JIT_CHECK_OSR # possible OSR re-entry? - beqc rPROFILE, v0, .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/out/mterp_arm.S b/runtime/interpreter/mterp/out/mterp_arm.S index dc476b7ff8..b0595648b2 100644 --- a/runtime/interpreter/mterp/out/mterp_arm.S +++ b/runtime/interpreter/mterp/out/mterp_arm.S @@ -311,6 +311,7 @@ unspecified registers or condition codes. .cfi_endproc .size \name, .-\name .endm + /* * Copyright (C) 2016 The Android Open Source Project * @@ -393,6 +394,7 @@ ENTRY ExecuteMterpImpl .global artMterpAsmInstructionStart artMterpAsmInstructionStart = .L_op_nop .text + /* ------------------------------ */ .balign 128 .L_op_nop: /* 0x00 */ @@ -6733,6 +6735,7 @@ f2l_maybeNaN: mov r0, #0 mov r1, #0 bx lr @ return 0 for NaN + /* * Convert the double in r0/r1 to a long in r0/r1. * @@ -6774,6 +6777,7 @@ artMterpAsmSisterEnd: .global artMterpAsmAltInstructionStart artMterpAsmAltInstructionStart = .L_ALT_op_nop .text + /* ------------------------------ */ .balign 128 .L_ALT_op_nop: /* 0x00 */ @@ -11132,6 +11136,7 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop .hidden artMterpAsmAltInstructionEnd .global artMterpAsmAltInstructionEnd artMterpAsmAltInstructionEnd: + /* * =========================================================================== * Common subroutines and data diff --git a/runtime/interpreter/mterp/out/mterp_arm64.S b/runtime/interpreter/mterp/out/mterp_arm64.S index c8c9cdb0fe..d65019dcb6 100644 --- a/runtime/interpreter/mterp/out/mterp_arm64.S +++ b/runtime/interpreter/mterp/out/mterp_arm64.S @@ -352,6 +352,7 @@ codes. .cfi_endproc .size \name, .-\name .endm + /* * Copyright (C) 2016 The Android Open Source Project * @@ -424,6 +425,7 @@ ENTRY ExecuteMterpImpl .global artMterpAsmInstructionStart artMterpAsmInstructionStart = .L_op_nop .text + /* ------------------------------ */ .balign 128 .L_op_nop: /* 0x00 */ @@ -6235,6 +6237,7 @@ artMterpAsmSisterStart: .hidden artMterpAsmSisterEnd .global artMterpAsmSisterEnd artMterpAsmSisterEnd: + /* * =========================================================================== * Common subroutines and data @@ -6544,6 +6547,7 @@ MterpProfileActive: .global artMterpAsmAltInstructionStart artMterpAsmAltInstructionStart = .L_ALT_op_nop .text + /* ------------------------------ */ .balign 128 .L_ALT_op_nop: /* 0x00 */ @@ -10646,6 +10650,7 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop .hidden artMterpAsmAltInstructionEnd .global artMterpAsmAltInstructionEnd artMterpAsmAltInstructionEnd: + // Close out the cfi info. We're treating mterp as a single function. END ExecuteMterpImpl diff --git a/runtime/interpreter/mterp/out/mterp_mips.S b/runtime/interpreter/mterp/out/mterp_mips.S index f2f3453e0a..91d4ca113b 100644 --- a/runtime/interpreter/mterp/out/mterp_mips.S +++ b/runtime/interpreter/mterp/out/mterp_mips.S @@ -725,6 +725,7 @@ #define LONG_MIN_HIGH 0x80000000 #define LONG_MIN_AS_FLOAT 0xDF000000 #define LONG_MIN_AS_DOUBLE_HIGH 0xC3E00000 + /* * Copyright (C) 2016 The Android Open Source Project * @@ -804,6 +805,7 @@ ExecuteMterpImpl: .global artMterpAsmInstructionStart artMterpAsmInstructionStart = .L_op_nop .text + /* ------------------------------ */ .balign 128 .L_op_nop: /* 0x00 */ @@ -3527,6 +3529,7 @@ TODO div a0, a0, a1 # a0 <- op, a0-a3 changed GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 + #else /* * Generic 32-bit binary operation. Provide an "instr" line that @@ -3559,6 +3562,7 @@ TODO mflo a0 # a0 <- op, a0-a3 changed GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 + #endif /* ------------------------------ */ @@ -3596,6 +3600,7 @@ TODO mod a0, a0, a1 # a0 <- op, a0-a3 changed GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 + #else /* * Generic 32-bit binary operation. Provide an "instr" line that @@ -3628,6 +3633,7 @@ TODO mfhi a0 # a0 <- op, a0-a3 changed GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 + #endif /* ------------------------------ */ @@ -4616,6 +4622,7 @@ TODO div a0, a0, a1 # a0 <- op, a0-a3 changed GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 + #else /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line @@ -4644,6 +4651,7 @@ TODO mflo a0 # a0 <- op, a0-a3 changed GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 + #endif /* ------------------------------ */ @@ -4677,6 +4685,7 @@ TODO mod a0, a0, a1 # a0 <- op, a0-a3 changed GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 + #else /* * Generic 32-bit "/2addr" binary operation. Provide an "instr" line @@ -4705,6 +4714,7 @@ TODO mfhi a0 # a0 <- op, a0-a3 changed GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 + #endif /* ------------------------------ */ @@ -5603,6 +5613,7 @@ TODO div a0, a0, a1 # a0 <- op, a0-a3 changed GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 + #else /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line @@ -5631,6 +5642,7 @@ TODO mflo a0 # a0 <- op, a0-a3 changed GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 + #endif /* ------------------------------ */ @@ -5664,6 +5676,7 @@ TODO mod a0, a0, a1 # a0 <- op, a0-a3 changed GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 + #else /* * Generic 32-bit "lit16" binary operation. Provide an "instr" line @@ -5692,6 +5705,7 @@ TODO mfhi a0 # a0 <- op, a0-a3 changed GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 + #endif /* ------------------------------ */ @@ -5919,6 +5933,7 @@ TODO div a0, a0, a1 # a0 <- op, a0-a3 changed GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 + #else /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line @@ -5949,6 +5964,7 @@ TODO mflo a0 # a0 <- op, a0-a3 changed GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 + #endif /* ------------------------------ */ @@ -5984,6 +6000,7 @@ TODO mod a0, a0, a1 # a0 <- op, a0-a3 changed GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 + #else /* * Generic 32-bit "lit8" binary operation. Provide an "instr" line @@ -6014,6 +6031,7 @@ TODO mfhi a0 # a0 <- op, a0-a3 changed GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 + #endif /* ------------------------------ */ @@ -6739,6 +6757,7 @@ artMterpAsmSisterEnd: .global artMterpAsmAltInstructionStart artMterpAsmAltInstructionStart = .L_ALT_op_nop .text + /* ------------------------------ */ .balign 128 .L_ALT_op_nop: /* 0x00 */ @@ -11095,6 +11114,7 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop .global artMterpAsmAltInstructionEnd artMterpAsmAltInstructionEnd: + /* * =========================================================================== * Common subroutines and data @@ -11383,3 +11403,4 @@ MterpProfileActive: .cfi_endproc .end ExecuteMterpImpl + diff --git a/runtime/interpreter/mterp/out/mterp_mips64.S b/runtime/interpreter/mterp/out/mterp_mips64.S index cf95a57a0e..86b16a1ca8 100644 --- a/runtime/interpreter/mterp/out/mterp_mips64.S +++ b/runtime/interpreter/mterp/out/mterp_mips64.S @@ -327,6 +327,7 @@ The following registers have fixed assignments: #define LONG_MIN 0x8000000000000000 #define LONG_MIN_AS_FLOAT 0xDF000000 #define LONG_MIN_AS_DOUBLE 0xC3E0000000000000 + /* * Copyright (C) 2016 The Android Open Source Project * @@ -425,6 +426,7 @@ ExecuteMterpImpl: .global artMterpAsmInstructionStart artMterpAsmInstructionStart = .L_op_nop .text + /* ------------------------------ */ .balign 128 .L_op_nop: /* 0x00 */ @@ -2228,6 +2230,7 @@ TODO bnezc v0, MterpFallback GET_INST_OPCODE v0 GOTO_OPCODE v0 + /* * Handle a virtual method call. * @@ -2258,6 +2261,7 @@ TODO bnezc v0, MterpFallback GET_INST_OPCODE v0 GOTO_OPCODE v0 + /* * Handle a "super" method call. * @@ -2334,6 +2338,7 @@ TODO bnezc v0, MterpFallback GET_INST_OPCODE v0 GOTO_OPCODE v0 + /* * Handle an interface method call. * @@ -2586,6 +2591,7 @@ TODO srl a2, rINST, 12 # a2 <- B GET_VREG_FLOAT f0, a2 FETCH_ADVANCE_INST 1 # advance rPC, load rINST + neg.s f0, f0 /* * Stores a specified register containing the result of conversion @@ -2624,6 +2630,7 @@ TODO srl a2, rINST, 12 # a2 <- B GET_VREG_DOUBLE f0, a2 FETCH_ADVANCE_INST 1 # advance rPC, load rINST + neg.d f0, f0 /* * Stores a specified register containing the result of conversion @@ -2679,6 +2686,7 @@ TODO srl a2, rINST, 12 # a2 <- B GET_VREG_FLOAT f0, a2 FETCH_ADVANCE_INST 1 # advance rPC, load rINST + cvt.s.w f0, f0 /* * Stores a specified register containing the result of conversion @@ -2722,6 +2730,7 @@ TODO srl a2, rINST, 12 # a2 <- B GET_VREG_FLOAT f0, a2 FETCH_ADVANCE_INST 1 # advance rPC, load rINST + cvt.d.w f0, f0 /* * Stores a specified register containing the result of conversion @@ -2783,6 +2792,7 @@ TODO srl a2, rINST, 12 # a2 <- B GET_VREG_DOUBLE f0, a2 FETCH_ADVANCE_INST 1 # advance rPC, load rINST + cvt.s.l f0, f0 /* * Stores a specified register containing the result of conversion @@ -2826,6 +2836,7 @@ TODO srl a2, rINST, 12 # a2 <- B GET_VREG_DOUBLE f0, a2 FETCH_ADVANCE_INST 1 # advance rPC, load rINST + cvt.d.l f0, f0 /* * Stores a specified register containing the result of conversion @@ -2864,6 +2875,7 @@ TODO srl a2, rINST, 12 # a2 <- B GET_VREG_FLOAT f0, a2 FETCH_ADVANCE_INST 1 # advance rPC, load rINST + trunc.w.s f0, f0 /* * Stores a specified register containing the result of conversion @@ -2902,6 +2914,7 @@ TODO srl a2, rINST, 12 # a2 <- B GET_VREG_FLOAT f0, a2 FETCH_ADVANCE_INST 1 # advance rPC, load rINST + trunc.l.s f0, f0 /* * Stores a specified register containing the result of conversion @@ -2945,6 +2958,7 @@ TODO srl a2, rINST, 12 # a2 <- B GET_VREG_FLOAT f0, a2 FETCH_ADVANCE_INST 1 # advance rPC, load rINST + cvt.d.s f0, f0 /* * Stores a specified register containing the result of conversion @@ -2983,6 +2997,7 @@ TODO srl a2, rINST, 12 # a2 <- B GET_VREG_DOUBLE f0, a2 FETCH_ADVANCE_INST 1 # advance rPC, load rINST + trunc.w.d f0, f0 /* * Stores a specified register containing the result of conversion @@ -3021,6 +3036,7 @@ TODO srl a2, rINST, 12 # a2 <- B GET_VREG_DOUBLE f0, a2 FETCH_ADVANCE_INST 1 # advance rPC, load rINST + trunc.l.d f0, f0 /* * Stores a specified register containing the result of conversion @@ -3064,6 +3080,7 @@ TODO srl a2, rINST, 12 # a2 <- B GET_VREG_DOUBLE f0, a2 FETCH_ADVANCE_INST 1 # advance rPC, load rINST + cvt.s.d f0, f0 /* * Stores a specified register containing the result of conversion @@ -6062,6 +6079,7 @@ artMterpAsmSisterEnd: .global artMterpAsmAltInstructionStart artMterpAsmAltInstructionStart = .L_ALT_op_nop .text + /* ------------------------------ */ .balign 128 .L_ALT_op_nop: /* 0x00 */ @@ -10674,6 +10692,7 @@ artMterpAsmAltInstructionStart = .L_ALT_op_nop .global artMterpAsmAltInstructionEnd artMterpAsmAltInstructionEnd: + /* * We've detected a condition that will result in an exception, but the exception * has not yet been thrown. Just bail out to the reference interpreter to deal with it. @@ -10950,3 +10969,4 @@ MterpProfileActive: .cfi_endproc .set reorder .size ExecuteMterpImpl, .-ExecuteMterpImpl + diff --git a/runtime/interpreter/mterp/out/mterp_x86.S b/runtime/interpreter/mterp/out/mterp_x86.S index 5a1bbf264b..fb182fdf4d 100644 --- a/runtime/interpreter/mterp/out/mterp_x86.S +++ b/runtime/interpreter/mterp/out/mterp_x86.S @@ -315,6 +315,7 @@ unspecified registers or condition codes. movl MACRO_LITERAL(0), (rREFS,\_vreg,4) movl MACRO_LITERAL(0), 4(rREFS,\_vreg,4) .endm + /* * Copyright (C) 2016 The Android Open Source Project * @@ -404,6 +405,7 @@ SYMBOL(ExecuteMterpImpl): .global SYMBOL(artMterpAsmInstructionStart) SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .text + /* ------------------------------ */ .balign 128 .L_op_nop: /* 0x00 */ @@ -2532,6 +2534,7 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop RESTORE_IBASE FETCH_INST GOTO_NEXT + /* * Handle a virtual method call. * @@ -2567,6 +2570,7 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop RESTORE_IBASE FETCH_INST GOTO_NEXT + /* * Handle a "super" method call. * @@ -2658,6 +2662,7 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop RESTORE_IBASE FETCH_INST GOTO_NEXT + /* * Handle an interface method call. * @@ -5672,6 +5677,7 @@ SYMBOL(artMterpAsmSisterEnd): .global SYMBOL(artMterpAsmAltInstructionStart) .text SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop + /* ------------------------------ */ .balign 128 .L_ALT_op_nop: /* 0x00 */ @@ -11566,6 +11572,7 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionEnd) .global SYMBOL(artMterpAsmAltInstructionEnd) SYMBOL(artMterpAsmAltInstructionEnd): + /* * =========================================================================== * Common subroutines and data @@ -11891,3 +11898,4 @@ MRestoreFrame: ret .cfi_endproc SIZE(ExecuteMterpImpl,ExecuteMterpImpl) + diff --git a/runtime/interpreter/mterp/out/mterp_x86_64.S b/runtime/interpreter/mterp/out/mterp_x86_64.S index 1c45059e07..abb8986efb 100644 --- a/runtime/interpreter/mterp/out/mterp_x86_64.S +++ b/runtime/interpreter/mterp/out/mterp_x86_64.S @@ -301,6 +301,7 @@ unspecified registers or condition codes. movl MACRO_LITERAL(0), (rREFS,\_vreg,4) movl MACRO_LITERAL(0), 4(rREFS,\_vreg,4) .endm + /* * Copyright (C) 2016 The Android Open Source Project * @@ -386,6 +387,7 @@ SYMBOL(ExecuteMterpImpl): .global SYMBOL(artMterpAsmInstructionStart) SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .text + /* ------------------------------ */ .balign 128 .L_op_nop: /* 0x00 */ @@ -2388,6 +2390,7 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop jnz MterpFallback FETCH_INST GOTO_NEXT + /* * Handle a virtual method call. * @@ -2420,6 +2423,7 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop jnz MterpFallback FETCH_INST GOTO_NEXT + /* * Handle a "super" method call. * @@ -2502,6 +2506,7 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop jnz MterpFallback FETCH_INST GOTO_NEXT + /* * Handle an interface method call. * @@ -5364,6 +5369,7 @@ SYMBOL(artMterpAsmSisterEnd): .global SYMBOL(artMterpAsmAltInstructionStart) .text SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop + /* ------------------------------ */ .balign 128 .L_ALT_op_nop: /* 0x00 */ @@ -10746,6 +10752,7 @@ SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionEnd) .global SYMBOL(artMterpAsmAltInstructionEnd) SYMBOL(artMterpAsmAltInstructionEnd): + /* * =========================================================================== * Common subroutines and data @@ -11043,3 +11050,4 @@ MRestoreFrame: ret .cfi_endproc SIZE(ExecuteMterpImpl,ExecuteMterpImpl) + diff --git a/runtime/interpreter/mterp/x86/alt_stub.S b/runtime/interpreter/mterp/x86/alt_stub.S deleted file mode 100644 index 79e3f74d1a..0000000000 --- a/runtime/interpreter/mterp/x86/alt_stub.S +++ /dev/null @@ -1,20 +0,0 @@ -%def alt_stub(): -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(${opnum}*${handler_size_bytes}) diff --git a/runtime/interpreter/mterp/x86/arithmetic.S b/runtime/interpreter/mterp/x86/arithmetic.S new file mode 100644 index 0000000000..a9fa0fc68f --- /dev/null +++ b/runtime/interpreter/mterp/x86/arithmetic.S @@ -0,0 +1,936 @@ +%def bindiv(result="", special="", rem=""): +/* + * 32-bit binary div/rem operation. Handles special case of op0=minint and + * op1=-1. + */ + /* div/rem vAA, vBB, vCC */ + movzbl 2(rPC), %eax # eax <- BB + movzbl 3(rPC), %ecx # ecx <- CC + GET_VREG %eax, %eax # eax <- vBB + GET_VREG %ecx, %ecx # ecx <- vCC + mov rIBASE, LOCAL0(%esp) + testl %ecx, %ecx + je common_errDivideByZero + movl %eax, %edx + orl %ecx, %edx + testl $$0xFFFFFF00, %edx # If both arguments are less + # than 8-bit and +ve + jz .L${opcode}_8 # Do 8-bit divide + testl $$0xFFFF0000, %edx # If both arguments are less + # than 16-bit and +ve + jz .L${opcode}_16 # Do 16-bit divide + cmpl $$-1, %ecx + jne .L${opcode}_32 + cmpl $$0x80000000, %eax + jne .L${opcode}_32 + movl $special, $result + jmp .L${opcode}_finish +.L${opcode}_32: + cltd + idivl %ecx + jmp .L${opcode}_finish +.L${opcode}_8: + div %cl # 8-bit divide otherwise. + # Remainder in %ah, quotient in %al + .if $rem + movl %eax, %edx + shr $$8, %edx + .else + andl $$0x000000FF, %eax + .endif + jmp .L${opcode}_finish +.L${opcode}_16: + xorl %edx, %edx # Clear %edx before divide + div %cx +.L${opcode}_finish: + SET_VREG $result, rINST + mov LOCAL0(%esp), rIBASE + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def bindiv2addr(result="", special=""): +/* + * 32-bit binary div/rem operation. Handles special case of op0=minint and + * op1=-1. + */ + /* div/rem/2addr vA, vB */ + movzx rINSTbl, %ecx # eax <- BA + mov rIBASE, LOCAL0(%esp) + sarl $$4, %ecx # ecx <- B + GET_VREG %ecx, %ecx # eax <- vBB + andb $$0xf, rINSTbl # rINST <- A + GET_VREG %eax, rINST # eax <- vBB + testl %ecx, %ecx + je common_errDivideByZero + cmpl $$-1, %ecx + jne .L${opcode}_continue_div2addr + cmpl $$0x80000000, %eax + jne .L${opcode}_continue_div2addr + movl $special, $result + SET_VREG $result, rINST + mov LOCAL0(%esp), rIBASE + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +.L${opcode}_continue_div2addr: + cltd + idivl %ecx + SET_VREG $result, rINST + mov LOCAL0(%esp), rIBASE + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def bindivLit16(result="", special=""): +/* + * 32-bit binary div/rem operation. Handles special case of op0=minint and + * op1=-1. + */ + /* div/rem/lit16 vA, vB, #+CCCC */ + /* Need A in rINST, ssssCCCC in ecx, vB in eax */ + movzbl rINSTbl, %eax # eax <- 000000BA + sarl $$4, %eax # eax <- B + GET_VREG %eax, %eax # eax <- vB + movswl 2(rPC), %ecx # ecx <- ssssCCCC + andb $$0xf, rINSTbl # rINST <- A + testl %ecx, %ecx + je common_errDivideByZero + cmpl $$-1, %ecx + jne .L${opcode}_continue_div + cmpl $$0x80000000, %eax + jne .L${opcode}_continue_div + movl $special, %eax + SET_VREG %eax, rINST + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +.L${opcode}_continue_div: + mov rIBASE, LOCAL0(%esp) + cltd + idivl %ecx + SET_VREG $result, rINST + mov LOCAL0(%esp), rIBASE + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def bindivLit8(result="", special=""): +/* + * 32-bit div/rem "lit8" binary operation. Handles special case of + * op0=minint & op1=-1 + */ + /* div/rem/lit8 vAA, vBB, #+CC */ + movzbl 2(rPC), %eax # eax <- BB + movsbl 3(rPC), %ecx # ecx <- ssssssCC + GET_VREG %eax, %eax # eax <- rBB + testl %ecx, %ecx + je common_errDivideByZero + cmpl $$0x80000000, %eax + jne .L${opcode}_continue_div + cmpl $$-1, %ecx + jne .L${opcode}_continue_div + movl $special, %eax + SET_VREG %eax, rINST + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +.L${opcode}_continue_div: + mov rIBASE, LOCAL0(%esp) + cltd + idivl %ecx + SET_VREG $result, rINST + mov LOCAL0(%esp), rIBASE + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def binop(result="%eax", instr=""): +/* + * Generic 32-bit binary operation. Provide an "instr" line that + * specifies an instruction that performs "result = eax op (rFP,%ecx,4)". + * This could be an x86 instruction or a function call. (If the result + * comes back in a register other than eax, you can override "result".) + * + * For: add-int, sub-int, and-int, or-int, + * xor-int, shl-int, shr-int, ushr-int + */ + /* binop vAA, vBB, vCC */ + movzbl 2(rPC), %eax # eax <- BB + movzbl 3(rPC), %ecx # ecx <- CC + GET_VREG %eax, %eax # eax <- vBB + $instr # ex: addl (rFP,%ecx,4),%eax + SET_VREG $result, rINST + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def binop1(result="%eax", tmp="%ecx", instr=""): +/* + * Generic 32-bit binary operation in which both operands loaded to + * registers (op0 in eax, op1 in ecx). + */ + /* binop vAA, vBB, vCC */ + movzbl 2(rPC),%eax # eax <- BB + movzbl 3(rPC),%ecx # ecx <- CC + GET_VREG %eax, %eax # eax <- vBB + GET_VREG %ecx, %ecx # eax <- vBB + $instr # ex: addl %ecx,%eax + SET_VREG $result, rINST + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def binop2addr(result="%eax", instr=""): +/* + * Generic 32-bit "/2addr" binary operation. Provide an "instr" line + * that specifies an instruction that performs "result = r0 op r1". + * This could be an instruction or a function call. + * + * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, + * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, + * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, + * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr + */ + /* binop/2addr vA, vB */ + movzx rINSTbl, %ecx # ecx <- A+ + sarl $$4, rINST # rINST <- B + GET_VREG %eax, rINST # eax <- vB + andb $$0xf, %cl # ecx <- A + $instr # for ex: addl %eax,(rFP,%ecx,4) + CLEAR_REF %ecx + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def binopLit16(result="%eax", instr=""): +/* + * Generic 32-bit "lit16" binary operation. Provide an "instr" line + * that specifies an instruction that performs "result = eax op ecx". + * This could be an x86 instruction or a function call. (If the result + * comes back in a register other than eax, you can override "result".) + * + * For: add-int/lit16, rsub-int, + * and-int/lit16, or-int/lit16, xor-int/lit16 + */ + /* binop/lit16 vA, vB, #+CCCC */ + movzbl rINSTbl, %eax # eax <- 000000BA + sarl $$4, %eax # eax <- B + GET_VREG %eax, %eax # eax <- vB + movswl 2(rPC), %ecx # ecx <- ssssCCCC + andb $$0xf, rINSTbl # rINST <- A + $instr # for example: addl %ecx, %eax + SET_VREG $result, rINST + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def binopLit8(result="%eax", instr=""): +/* + * Generic 32-bit "lit8" binary operation. Provide an "instr" line + * that specifies an instruction that performs "result = eax op ecx". + * This could be an x86 instruction or a function call. (If the result + * comes back in a register other than r0, you can override "result".) + * + * For: add-int/lit8, rsub-int/lit8 + * and-int/lit8, or-int/lit8, xor-int/lit8, + * shl-int/lit8, shr-int/lit8, ushr-int/lit8 + */ + /* binop/lit8 vAA, vBB, #+CC */ + movzbl 2(rPC), %eax # eax <- BB + movsbl 3(rPC), %ecx # ecx <- ssssssCC + GET_VREG %eax, %eax # eax <- rBB + $instr # ex: addl %ecx,%eax + SET_VREG $result, rINST + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def binopWide(instr1="", instr2=""): +/* + * Generic 64-bit binary operation. + */ + /* binop vAA, vBB, vCC */ + movzbl 2(rPC), %eax # eax <- BB + movzbl 3(rPC), %ecx # ecx <- CC + movl rIBASE, LOCAL0(%esp) # save rIBASE + GET_VREG rIBASE, %eax # rIBASE <- v[BB+0] + GET_VREG_HIGH %eax, %eax # eax <- v[BB+1] + $instr1 # ex: addl (rFP,%ecx,4),rIBASE + $instr2 # ex: adcl 4(rFP,%ecx,4),%eax + SET_VREG rIBASE, rINST # v[AA+0] <- rIBASE + movl LOCAL0(%esp), rIBASE # restore rIBASE + SET_VREG_HIGH %eax, rINST # v[AA+1] <- eax + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def binopWide2addr(instr1="", instr2=""): +/* + * Generic 64-bit binary operation. + */ + /* binop/2addr vA, vB */ + movzbl rINSTbl, %ecx # ecx<- BA + sarl $$4, %ecx # ecx<- B + GET_VREG %eax, %ecx # eax<- v[B+0] + GET_VREG_HIGH %ecx, %ecx # eax<- v[B+1] + andb $$0xF, rINSTbl # rINST<- A + $instr1 # ex: addl %eax,(rFP,rINST,4) + $instr2 # ex: adcl %ecx,4(rFP,rINST,4) + CLEAR_WIDE_REF rINST + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def cvtfp_int(srcdouble="1", tgtlong="1"): +/* On fp to int conversions, Java requires that + * if the result > maxint, it should be clamped to maxint. If it is less + * than minint, it should be clamped to minint. If it is a nan, the result + * should be zero. Further, the rounding mode is to truncate. This model + * differs from what is delivered normally via the x86 fpu, so we have + * to play some games. + */ + /* float/double to int/long vA, vB */ + movzbl rINSTbl, %ecx # ecx <- A+ + sarl $$4, rINST # rINST <- B + .if $srcdouble + fldl VREG_ADDRESS(rINST) # %st0 <- vB + .else + flds VREG_ADDRESS(rINST) # %st0 <- vB + .endif + ftst + fnstcw LOCAL0(%esp) # remember original rounding mode + movzwl LOCAL0(%esp), %eax + movb $$0xc, %ah + movw %ax, LOCAL0+2(%esp) + fldcw LOCAL0+2(%esp) # set "to zero" rounding mode + andb $$0xf, %cl # ecx <- A + .if $tgtlong + fistpll VREG_ADDRESS(%ecx) # convert and store + .else + fistpl VREG_ADDRESS(%ecx) # convert and store + .endif + fldcw LOCAL0(%esp) # restore previous rounding mode + .if $tgtlong + movl $$0x80000000, %eax + xorl VREG_HIGH_ADDRESS(%ecx), %eax + orl VREG_ADDRESS(%ecx), %eax + .else + cmpl $$0x80000000, VREG_ADDRESS(%ecx) + .endif + je .L${opcode}_special_case # fix up result + +.L${opcode}_finish: + xor %eax, %eax + mov %eax, VREG_REF_ADDRESS(%ecx) + .if $tgtlong + mov %eax, VREG_REF_HIGH_ADDRESS(%ecx) + .endif + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +.L${opcode}_special_case: + fnstsw %ax + sahf + jp .L${opcode}_isNaN + adcl $$-1, VREG_ADDRESS(%ecx) + .if $tgtlong + adcl $$-1, VREG_HIGH_ADDRESS(%ecx) + .endif + jmp .L${opcode}_finish +.L${opcode}_isNaN: + movl $$0, VREG_ADDRESS(%ecx) + .if $tgtlong + movl $$0, VREG_HIGH_ADDRESS(%ecx) + .endif + jmp .L${opcode}_finish + +%def shop2addr(result="%eax", instr=""): +/* + * Generic 32-bit "shift/2addr" operation. + */ + /* shift/2addr vA, vB */ + movzx rINSTbl, %ecx # eax <- BA + sarl $$4, %ecx # ecx <- B + GET_VREG %ecx, %ecx # eax <- vBB + andb $$0xf, rINSTbl # rINST <- A + GET_VREG %eax, rINST # eax <- vAA + $instr # ex: sarl %cl, %eax + SET_VREG $result, rINST + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def unop(instr=""): +/* + * Generic 32-bit unary operation. Provide an "instr" line that + * specifies an instruction that performs "result = op eax". + */ + /* unop vA, vB */ + movzbl rINSTbl,%ecx # ecx <- A+ + sarl $$4,rINST # rINST <- B + GET_VREG %eax, rINST # eax <- vB + andb $$0xf,%cl # ecx <- A + $instr + SET_VREG %eax, %ecx + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_add_int(): +% binop(instr="addl (rFP,%ecx,4), %eax") + +%def op_add_int_2addr(): +% binop2addr(instr="addl %eax, (rFP,%ecx,4)") + +%def op_add_int_lit16(): +% binopLit16(instr="addl %ecx, %eax") + +%def op_add_int_lit8(): +% binopLit8(instr="addl %ecx, %eax") + +%def op_add_long(): +% binopWide(instr1="addl (rFP,%ecx,4), rIBASE", instr2="adcl 4(rFP,%ecx,4), %eax") + +%def op_add_long_2addr(): +% binopWide2addr(instr1="addl %eax, (rFP,rINST,4)", instr2="adcl %ecx, 4(rFP,rINST,4)") + +%def op_and_int(): +% binop(instr="andl (rFP,%ecx,4), %eax") + +%def op_and_int_2addr(): +% binop2addr(instr="andl %eax, (rFP,%ecx,4)") + +%def op_and_int_lit16(): +% binopLit16(instr="andl %ecx, %eax") + +%def op_and_int_lit8(): +% binopLit8(instr="andl %ecx, %eax") + +%def op_and_long(): +% binopWide(instr1="andl (rFP,%ecx,4), rIBASE", instr2="andl 4(rFP,%ecx,4), %eax") + +%def op_and_long_2addr(): +% binopWide2addr(instr1="andl %eax, (rFP,rINST,4)", instr2="andl %ecx, 4(rFP,rINST,4)") + +%def op_cmp_long(): +/* + * Compare two 64-bit values. Puts 0, 1, or -1 into the destination + * register based on the results of the comparison. + */ + /* cmp-long vAA, vBB, vCC */ + movzbl 2(rPC), %eax # eax <- BB + movzbl 3(rPC), %ecx # ecx <- CC + GET_VREG_HIGH %eax, %eax # eax <- v[BB+1], BB is clobbered + cmpl VREG_HIGH_ADDRESS(%ecx), %eax + jl .L${opcode}_smaller + jg .L${opcode}_bigger + movzbl 2(rPC), %eax # eax <- BB, restore BB + GET_VREG %eax, %eax # eax <- v[BB] + sub VREG_ADDRESS(%ecx), %eax + ja .L${opcode}_bigger + jb .L${opcode}_smaller +.L${opcode}_finish: + SET_VREG %eax, rINST + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +.L${opcode}_bigger: + movl $$1, %eax + jmp .L${opcode}_finish + +.L${opcode}_smaller: + movl $$-1, %eax + jmp .L${opcode}_finish + +%def op_div_int(): +% bindiv(result="%eax", special="$0x80000000", rem="0") + +%def op_div_int_2addr(): +% bindiv2addr(result="%eax", special="$0x80000000") + +%def op_div_int_lit16(): +% bindivLit16(result="%eax", special="$0x80000000") + +%def op_div_int_lit8(): +% bindivLit8(result="%eax", special="$0x80000000") + +%def op_div_long(routine="art_quick_ldiv"): +/* art_quick_* methods has quick abi, + * so use eax, ecx, edx, ebx for args + */ + /* div vAA, vBB, vCC */ + .extern $routine + mov rIBASE, LOCAL0(%esp) # save rIBASE/%edx + mov rINST, LOCAL1(%esp) # save rINST/%ebx + movzbl 3(rPC), %eax # eax <- CC + GET_VREG %ecx, %eax + GET_VREG_HIGH %ebx, %eax + movl %ecx, %edx + orl %ebx, %ecx + jz common_errDivideByZero + movzbl 2(rPC), %eax # eax <- BB + GET_VREG_HIGH %ecx, %eax + GET_VREG %eax, %eax + call SYMBOL($routine) + mov LOCAL1(%esp), rINST # restore rINST/%ebx + SET_VREG_HIGH rIBASE, rINST + SET_VREG %eax, rINST + mov LOCAL0(%esp), rIBASE # restore rIBASE/%edx + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_div_long_2addr(routine="art_quick_ldiv"): +/* art_quick_* methods has quick abi, + * so use eax, ecx, edx, ebx for args + */ + /* div/2addr vA, vB */ + .extern $routine + mov rIBASE, LOCAL0(%esp) # save rIBASE/%edx + movzbl rINSTbl, %eax + shrl $$4, %eax # eax <- B + andb $$0xf, rINSTbl # rINST <- A + mov rINST, LOCAL1(%esp) # save rINST/%ebx + movl %ebx, %ecx + GET_VREG %edx, %eax + GET_VREG_HIGH %ebx, %eax + movl %edx, %eax + orl %ebx, %eax + jz common_errDivideByZero + GET_VREG %eax, %ecx + GET_VREG_HIGH %ecx, %ecx + call SYMBOL($routine) + mov LOCAL1(%esp), rINST # restore rINST/%ebx + SET_VREG_HIGH rIBASE, rINST + SET_VREG %eax, rINST + mov LOCAL0(%esp), rIBASE # restore rIBASE/%edx + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_int_to_byte(): +% unop(instr="movsbl %al, %eax") + +%def op_int_to_char(): +% unop(instr="movzwl %ax,%eax") + +%def op_int_to_long(): + /* int to long vA, vB */ + movzbl rINSTbl, %eax # eax <- +A + sarl $$4, %eax # eax <- B + GET_VREG %eax, %eax # eax <- vB + andb $$0xf, rINSTbl # rINST <- A + movl rIBASE, %ecx # cltd trashes rIBASE/edx + cltd # rINST:eax<- sssssssBBBBBBBB + SET_VREG_HIGH rIBASE, rINST # v[A+1] <- rIBASE + SET_VREG %eax, rINST # v[A+0] <- %eax + movl %ecx, rIBASE + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + + +%def op_int_to_short(): +% unop(instr="movswl %ax, %eax") + +%def op_long_to_int(): +/* we ignore the high word, making this equivalent to a 32-bit reg move */ +% op_move() + +%def op_mul_int(): + /* + * 32-bit binary multiplication. + */ + /* mul vAA, vBB, vCC */ + movzbl 2(rPC), %eax # eax <- BB + movzbl 3(rPC), %ecx # ecx <- CC + GET_VREG %eax, %eax # eax <- vBB + mov rIBASE, LOCAL0(%esp) + imull (rFP,%ecx,4), %eax # trashes rIBASE/edx + mov LOCAL0(%esp), rIBASE + SET_VREG %eax, rINST + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_mul_int_2addr(): + /* mul vA, vB */ + movzx rINSTbl, %ecx # ecx <- A+ + sarl $$4, rINST # rINST <- B + GET_VREG %eax, rINST # eax <- vB + andb $$0xf, %cl # ecx <- A + movl rIBASE, rINST + imull (rFP,%ecx,4), %eax # trashes rIBASE/edx + movl rINST, rIBASE + SET_VREG %eax, %ecx + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_mul_int_lit16(): + /* mul/lit16 vA, vB, #+CCCC */ + /* Need A in rINST, ssssCCCC in ecx, vB in eax */ + movzbl rINSTbl, %eax # eax <- 000000BA + sarl $$4, %eax # eax <- B + GET_VREG %eax, %eax # eax <- vB + movl rIBASE, %ecx + movswl 2(rPC), rIBASE # rIBASE <- ssssCCCC + andb $$0xf, rINSTbl # rINST <- A + imull rIBASE, %eax # trashes rIBASE/edx + movl %ecx, rIBASE + SET_VREG %eax, rINST + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_mul_int_lit8(): + /* mul/lit8 vAA, vBB, #+CC */ + movzbl 2(rPC), %eax # eax <- BB + movl rIBASE, %ecx + GET_VREG %eax, %eax # eax <- rBB + movsbl 3(rPC), rIBASE # rIBASE <- ssssssCC + imull rIBASE, %eax # trashes rIBASE/edx + movl %ecx, rIBASE + SET_VREG %eax, rINST + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_mul_long(): +/* + * Signed 64-bit integer multiply. + * + * We could definately use more free registers for + * this code. We spill rINSTw (ebx), + * giving us eax, ebc, ecx and edx as computational + * temps. On top of that, we'll spill edi (rFP) + * for use as the vB pointer and esi (rPC) for use + * as the vC pointer. Yuck. + * + */ + /* mul-long vAA, vBB, vCC */ + movzbl 2(rPC), %eax # eax <- B + movzbl 3(rPC), %ecx # ecx <- C + mov rPC, LOCAL0(%esp) # save Interpreter PC + mov rFP, LOCAL1(%esp) # save FP + mov rIBASE, LOCAL2(%esp) # save rIBASE + leal (rFP,%eax,4), %esi # esi <- &v[B] + leal (rFP,%ecx,4), rFP # rFP <- &v[C] + movl 4(%esi), %ecx # ecx <- Bmsw + imull (rFP), %ecx # ecx <- (Bmsw*Clsw) + movl 4(rFP), %eax # eax <- Cmsw + imull (%esi), %eax # eax <- (Cmsw*Blsw) + addl %eax, %ecx # ecx <- (Bmsw*Clsw)+(Cmsw*Blsw) + movl (rFP), %eax # eax <- Clsw + mull (%esi) # eax <- (Clsw*Alsw) + mov LOCAL0(%esp), rPC # restore Interpreter PC + mov LOCAL1(%esp), rFP # restore FP + leal (%ecx,rIBASE), rIBASE # full result now in rIBASE:%eax + SET_VREG_HIGH rIBASE, rINST # v[B+1] <- rIBASE + mov LOCAL2(%esp), rIBASE # restore IBASE + SET_VREG %eax, rINST # v[B] <- eax + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_mul_long_2addr(): +/* + * Signed 64-bit integer multiply, 2-addr version + * + * We could definately use more free registers for + * this code. We must spill %edx (rIBASE) because it + * is used by imul. We'll also spill rINST (ebx), + * giving us eax, ebc, ecx and rIBASE as computational + * temps. On top of that, we'll spill %esi (edi) + * for use as the vA pointer and rFP (esi) for use + * as the vB pointer. Yuck. + */ + /* mul-long/2addr vA, vB */ + movzbl rINSTbl, %eax # eax <- BA + andb $$0xf, %al # eax <- A + CLEAR_WIDE_REF %eax # clear refs in advance + sarl $$4, rINST # rINST <- B + mov rPC, LOCAL0(%esp) # save Interpreter PC + mov rFP, LOCAL1(%esp) # save FP + mov rIBASE, LOCAL2(%esp) # save rIBASE + leal (rFP,%eax,4), %esi # esi <- &v[A] + leal (rFP,rINST,4), rFP # rFP <- &v[B] + movl 4(%esi), %ecx # ecx <- Amsw + imull (rFP), %ecx # ecx <- (Amsw*Blsw) + movl 4(rFP), %eax # eax <- Bmsw + imull (%esi), %eax # eax <- (Bmsw*Alsw) + addl %eax, %ecx # ecx <- (Amsw*Blsw)+(Bmsw*Alsw) + movl (rFP), %eax # eax <- Blsw + mull (%esi) # eax <- (Blsw*Alsw) + leal (%ecx,rIBASE), rIBASE # full result now in %edx:%eax + movl rIBASE, 4(%esi) # v[A+1] <- rIBASE + movl %eax, (%esi) # v[A] <- %eax + mov LOCAL0(%esp), rPC # restore Interpreter PC + mov LOCAL2(%esp), rIBASE # restore IBASE + mov LOCAL1(%esp), rFP # restore FP + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_neg_int(): +% unop(instr="negl %eax") + +%def op_neg_long(): + /* unop vA, vB */ + movzbl rINSTbl, %ecx # ecx <- BA + sarl $$4, %ecx # ecx <- B + andb $$0xf, rINSTbl # rINST <- A + GET_VREG %eax, %ecx # eax <- v[B+0] + GET_VREG_HIGH %ecx, %ecx # ecx <- v[B+1] + negl %eax + adcl $$0, %ecx + negl %ecx + SET_VREG %eax, rINST # v[A+0] <- eax + SET_VREG_HIGH %ecx, rINST # v[A+1] <- ecx + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + + +%def op_not_int(): +% unop(instr="notl %eax") + +%def op_not_long(): + /* unop vA, vB */ + movzbl rINSTbl, %ecx # ecx <- BA + sarl $$4, %ecx # ecx <- B + andb $$0xf, rINSTbl # rINST <- A + GET_VREG %eax, %ecx # eax <- v[B+0] + GET_VREG_HIGH %ecx, %ecx # ecx <- v[B+1] + notl %eax + notl %ecx + SET_VREG %eax, rINST # v[A+0] <- eax + SET_VREG_HIGH %ecx, rINST # v[A+1] <- ecx + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_or_int(): +% binop(instr="orl (rFP,%ecx,4), %eax") + +%def op_or_int_2addr(): +% binop2addr(instr="orl %eax, (rFP,%ecx,4)") + +%def op_or_int_lit16(): +% binopLit16(instr="orl %ecx, %eax") + +%def op_or_int_lit8(): +% binopLit8(instr="orl %ecx, %eax") + +%def op_or_long(): +% binopWide(instr1="orl (rFP,%ecx,4), rIBASE", instr2="orl 4(rFP,%ecx,4), %eax") + +%def op_or_long_2addr(): +% binopWide2addr(instr1="orl %eax, (rFP,rINST,4)", instr2="orl %ecx, 4(rFP,rINST,4)") + +%def op_rem_int(): +% bindiv(result="rIBASE", special="$0", rem="1") + +%def op_rem_int_2addr(): +% bindiv2addr(result="rIBASE", special="$0") + +%def op_rem_int_lit16(): +% bindivLit16(result="rIBASE", special="$0") + +%def op_rem_int_lit8(): +% bindivLit8(result="rIBASE", special="$0") + +%def op_rem_long(): +% op_div_long(routine="art_quick_lmod") + +%def op_rem_long_2addr(): +% op_div_long_2addr(routine="art_quick_lmod") + +%def op_rsub_int(): +/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ +% binopLit16(instr="subl %eax, %ecx", result="%ecx") + +%def op_rsub_int_lit8(): +% binopLit8(instr="subl %eax, %ecx", result="%ecx") + +%def op_shl_int(): +% binop1(instr="sall %cl, %eax") + +%def op_shl_int_2addr(): +% shop2addr(instr="sall %cl, %eax") + +%def op_shl_int_lit8(): +% binopLit8(instr="sall %cl, %eax") + +%def op_shl_long(): +/* + * Long integer shift. This is different from the generic 32/64-bit + * binary operations because vAA/vBB are 64-bit but vCC (the shift + * distance) is 32-bit. Also, Dalvik requires us to mask off the low + * 6 bits of the shift distance. x86 shifts automatically mask off + * the low 5 bits of %cl, so have to handle the 64 > shiftcount > 31 + * case specially. + */ + /* shl-long vAA, vBB, vCC */ + /* ecx gets shift count */ + /* Need to spill rINST */ + /* rINSTw gets AA */ + movzbl 2(rPC), %eax # eax <- BB + movzbl 3(rPC), %ecx # ecx <- CC + movl rIBASE, LOCAL0(%esp) + GET_VREG_HIGH rIBASE, %eax # ecx <- v[BB+1] + GET_VREG %ecx, %ecx # ecx <- vCC + GET_VREG %eax, %eax # eax <- v[BB+0] + shldl %eax,rIBASE + sall %cl, %eax + testb $$32, %cl + je 2f + movl %eax, rIBASE + xorl %eax, %eax +2: + SET_VREG_HIGH rIBASE, rINST # v[AA+1] <- rIBASE + movl LOCAL0(%esp), rIBASE + SET_VREG %eax, rINST # v[AA+0] <- %eax + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_shl_long_2addr(): +/* + * Long integer shift, 2addr version. vA is 64-bit value/result, vB is + * 32-bit shift distance. + */ + /* shl-long/2addr vA, vB */ + /* ecx gets shift count */ + /* Need to spill rIBASE */ + /* rINSTw gets AA */ + movzbl rINSTbl, %ecx # ecx <- BA + andb $$0xf, rINSTbl # rINST <- A + GET_VREG %eax, rINST # eax <- v[AA+0] + sarl $$4, %ecx # ecx <- B + movl rIBASE, LOCAL0(%esp) + GET_VREG_HIGH rIBASE, rINST # rIBASE <- v[AA+1] + GET_VREG %ecx, %ecx # ecx <- vBB + shldl %eax, rIBASE + sall %cl, %eax + testb $$32, %cl + je 2f + movl %eax, rIBASE + xorl %eax, %eax +2: + SET_VREG_HIGH rIBASE, rINST # v[AA+1] <- rIBASE + movl LOCAL0(%esp), rIBASE + SET_VREG %eax, rINST # v[AA+0] <- eax + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_shr_int(): +% binop1(instr="sarl %cl, %eax") + +%def op_shr_int_2addr(): +% shop2addr(instr="sarl %cl, %eax") + +%def op_shr_int_lit8(): +% binopLit8(instr="sarl %cl, %eax") + +%def op_shr_long(): +/* + * Long integer shift. This is different from the generic 32/64-bit + * binary operations because vAA/vBB are 64-bit but vCC (the shift + * distance) is 32-bit. Also, Dalvik requires us to mask off the low + * 6 bits of the shift distance. x86 shifts automatically mask off + * the low 5 bits of %cl, so have to handle the 64 > shiftcount > 31 + * case specially. + */ + /* shr-long vAA, vBB, vCC */ + /* ecx gets shift count */ + /* Need to spill rIBASE */ + /* rINSTw gets AA */ + movzbl 2(rPC), %eax # eax <- BB + movzbl 3(rPC), %ecx # ecx <- CC + movl rIBASE, LOCAL0(%esp) + GET_VREG_HIGH rIBASE, %eax # rIBASE<- v[BB+1] + GET_VREG %ecx, %ecx # ecx <- vCC + GET_VREG %eax, %eax # eax <- v[BB+0] + shrdl rIBASE, %eax + sarl %cl, rIBASE + testb $$32, %cl + je 2f + movl rIBASE, %eax + sarl $$31, rIBASE +2: + SET_VREG_HIGH rIBASE, rINST # v[AA+1] <- rIBASE + movl LOCAL0(%esp), rIBASE + SET_VREG %eax, rINST # v[AA+0] <- eax + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_shr_long_2addr(): +/* + * Long integer shift, 2addr version. vA is 64-bit value/result, vB is + * 32-bit shift distance. + */ + /* shl-long/2addr vA, vB */ + /* ecx gets shift count */ + /* Need to spill rIBASE */ + /* rINSTw gets AA */ + movzbl rINSTbl, %ecx # ecx <- BA + andb $$0xf, rINSTbl # rINST <- A + GET_VREG %eax, rINST # eax <- v[AA+0] + sarl $$4, %ecx # ecx <- B + movl rIBASE, LOCAL0(%esp) + GET_VREG_HIGH rIBASE, rINST # rIBASE <- v[AA+1] + GET_VREG %ecx, %ecx # ecx <- vBB + shrdl rIBASE, %eax + sarl %cl, rIBASE + testb $$32, %cl + je 2f + movl rIBASE, %eax + sarl $$31, rIBASE +2: + SET_VREG_HIGH rIBASE, rINST # v[AA+1] <- rIBASE + movl LOCAL0(%esp), rIBASE + SET_VREG %eax, rINST # v[AA+0] <- eax + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_sub_int(): +% binop(instr="subl (rFP,%ecx,4), %eax") + +%def op_sub_int_2addr(): +% binop2addr(instr="subl %eax, (rFP,%ecx,4)") + +%def op_sub_long(): +% binopWide(instr1="subl (rFP,%ecx,4), rIBASE", instr2="sbbl 4(rFP,%ecx,4), %eax") + +%def op_sub_long_2addr(): +% binopWide2addr(instr1="subl %eax, (rFP,rINST,4)", instr2="sbbl %ecx, 4(rFP,rINST,4)") + +%def op_ushr_int(): +% binop1(instr="shrl %cl, %eax") + +%def op_ushr_int_2addr(): +% shop2addr(instr="shrl %cl, %eax") + +%def op_ushr_int_lit8(): +% binopLit8(instr="shrl %cl, %eax") + +%def op_ushr_long(): +/* + * Long integer shift. This is different from the generic 32/64-bit + * binary operations because vAA/vBB are 64-bit but vCC (the shift + * distance) is 32-bit. Also, Dalvik requires us to mask off the low + * 6 bits of the shift distance. x86 shifts automatically mask off + * the low 5 bits of %cl, so have to handle the 64 > shiftcount > 31 + * case specially. + */ + /* shr-long vAA, vBB, vCC */ + /* ecx gets shift count */ + /* Need to spill rIBASE */ + /* rINSTw gets AA */ + movzbl 2(rPC), %eax # eax <- BB + movzbl 3(rPC), %ecx # ecx <- CC + movl rIBASE, LOCAL0(%esp) + GET_VREG_HIGH rIBASE, %eax # rIBASE <- v[BB+1] + GET_VREG %ecx, %ecx # ecx <- vCC + GET_VREG %eax, %eax # eax <- v[BB+0] + shrdl rIBASE, %eax + shrl %cl, rIBASE + testb $$32, %cl + je 2f + movl rIBASE, %eax + xorl rIBASE, rIBASE +2: + SET_VREG_HIGH rIBASE, rINST # v[AA+1] <- rIBASE + movl LOCAL0(%esp), rIBASE + SET_VREG %eax, rINST # v[BB+0] <- eax + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_ushr_long_2addr(): +/* + * Long integer shift, 2addr version. vA is 64-bit value/result, vB is + * 32-bit shift distance. + */ + /* shl-long/2addr vA, vB */ + /* ecx gets shift count */ + /* Need to spill rIBASE */ + /* rINSTw gets AA */ + movzbl rINSTbl, %ecx # ecx <- BA + andb $$0xf, rINSTbl # rINST <- A + GET_VREG %eax, rINST # eax <- v[AA+0] + sarl $$4, %ecx # ecx <- B + movl rIBASE, LOCAL0(%esp) + GET_VREG_HIGH rIBASE, rINST # rIBASE <- v[AA+1] + GET_VREG %ecx, %ecx # ecx <- vBB + shrdl rIBASE, %eax + shrl %cl, rIBASE + testb $$32, %cl + je 2f + movl rIBASE, %eax + xorl rIBASE, rIBASE +2: + SET_VREG_HIGH rIBASE, rINST # v[AA+1] <- rIBASE + movl LOCAL0(%esp), rIBASE + SET_VREG %eax, rINST # v[AA+0] <- eax + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_xor_int(): +% binop(instr="xorl (rFP,%ecx,4), %eax") + +%def op_xor_int_2addr(): +% binop2addr(instr="xorl %eax, (rFP,%ecx,4)") + +%def op_xor_int_lit16(): +% binopLit16(instr="xorl %ecx, %eax") + +%def op_xor_int_lit8(): +% binopLit8(instr="xorl %ecx, %eax") + +%def op_xor_long(): +% binopWide(instr1="xorl (rFP,%ecx,4), rIBASE", instr2="xorl 4(rFP,%ecx,4), %eax") + +%def op_xor_long_2addr(): +% binopWide2addr(instr1="xorl %eax, (rFP,rINST,4)", instr2="xorl %ecx, 4(rFP,rINST,4)") diff --git a/runtime/interpreter/mterp/x86/array.S b/runtime/interpreter/mterp/x86/array.S new file mode 100644 index 0000000000..de846a4728 --- /dev/null +++ b/runtime/interpreter/mterp/x86/array.S @@ -0,0 +1,215 @@ +%def op_aget(load="movl", shift="4", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"): +/* + * Array get, 32 bits or less. vAA <- vBB[vCC]. + * + * for: aget, aget-boolean, aget-byte, aget-char, aget-short + * + */ + /* op vAA, vBB, vCC */ + movzbl 2(rPC), %eax # eax <- BB + movzbl 3(rPC), %ecx # ecx <- CC + GET_VREG %eax, %eax # eax <- vBB (array object) + GET_VREG %ecx, %ecx # ecx <- vCC (requested index) + testl %eax, %eax # null array object? + je common_errNullObject # bail if so + cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx + jae common_errArrayIndex # index >= length, bail. + $load $data_offset(%eax,%ecx,$shift), %eax + SET_VREG %eax, rINST + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_aget_boolean(): +% op_aget(load="movzbl", shift="1", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") + +%def op_aget_byte(): +% op_aget(load="movsbl", shift="1", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") + +%def op_aget_char(): +% op_aget(load="movzwl", shift="2", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") + +%def op_aget_object(): +/* + * Array object get. vAA <- vBB[vCC]. + * + * for: aget-object + */ + /* op vAA, vBB, vCC */ + movzbl 2(rPC), %eax # eax <- BB + movzbl 3(rPC), %ecx # ecx <- CC + GET_VREG %eax, %eax # eax <- vBB (array object) + GET_VREG %ecx, %ecx # ecs <- vCC (requested index) + EXPORT_PC + movl %eax, OUT_ARG0(%esp) + movl %ecx, OUT_ARG1(%esp) + call SYMBOL(artAGetObjectFromMterp) # (array, index) + movl rSELF, %ecx + RESTORE_IBASE_FROM_SELF %ecx + cmpl $$0, THREAD_EXCEPTION_OFFSET(%ecx) + jnz MterpException + SET_VREG_OBJECT %eax, rINST + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_aget_short(): +% op_aget(load="movswl", shift="2", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") + +%def op_aget_wide(): +/* + * Array get, 64 bits. vAA <- vBB[vCC]. + */ + /* aget-wide vAA, vBB, vCC */ + movzbl 2(rPC), %eax # eax <- BB + movzbl 3(rPC), %ecx # ecx <- CC + GET_VREG %eax, %eax # eax <- vBB (array object) + GET_VREG %ecx, %ecx # ecx <- vCC (requested index) + testl %eax, %eax # null array object? + je common_errNullObject # bail if so + cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx + jae common_errArrayIndex # index >= length, bail. + leal MIRROR_WIDE_ARRAY_DATA_OFFSET(%eax,%ecx,8), %eax + movq (%eax), %xmm0 # xmm0 <- vBB[vCC] + SET_WIDE_FP_VREG %xmm0, rINST # vAA <- xmm0 + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_aput(reg="rINST", store="movl", shift="4", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"): +/* + * Array put, 32 bits or less. vBB[vCC] <- vAA. + * + * for: aput, aput-boolean, aput-byte, aput-char, aput-short + * + */ + /* op vAA, vBB, vCC */ + movzbl 2(rPC), %eax # eax <- BB + movzbl 3(rPC), %ecx # ecx <- CC + GET_VREG %eax, %eax # eax <- vBB (array object) + GET_VREG %ecx, %ecx # ecx <- vCC (requested index) + testl %eax, %eax # null array object? + je common_errNullObject # bail if so + cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx + jae common_errArrayIndex # index >= length, bail. + leal $data_offset(%eax,%ecx,$shift), %eax + GET_VREG rINST, rINST + $store $reg, (%eax) + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_aput_boolean(): +% op_aput(reg="rINSTbl", store="movb", shift="1", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") + +%def op_aput_byte(): +% op_aput(reg="rINSTbl", store="movb", shift="1", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") + +%def op_aput_char(): +% op_aput(reg="rINSTw", store="movw", shift="2", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") + +%def op_aput_object(): +/* + * Store an object into an array. vBB[vCC] <- vAA. + */ + /* op vAA, vBB, vCC */ + EXPORT_PC + leal OFF_FP_SHADOWFRAME(rFP), %eax + movl %eax, OUT_ARG0(%esp) + movl rPC, OUT_ARG1(%esp) + REFRESH_INST ${opnum} + movl rINST, OUT_ARG2(%esp) + call SYMBOL(MterpAputObject) # (array, index) + RESTORE_IBASE + testb %al, %al + jz MterpPossibleException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_aput_short(): +% op_aput(reg="rINSTw", store="movw", shift="2", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") + +%def op_aput_wide(): +/* + * Array put, 64 bits. vBB[vCC] <- vAA. + * + */ + /* aput-wide vAA, vBB, vCC */ + movzbl 2(rPC), %eax # eax <- BB + movzbl 3(rPC), %ecx # ecx <- CC + GET_VREG %eax, %eax # eax <- vBB (array object) + GET_VREG %ecx, %ecx # ecx <- vCC (requested index) + testl %eax, %eax # null array object? + je common_errNullObject # bail if so + cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx + jae common_errArrayIndex # index >= length, bail. + leal MIRROR_WIDE_ARRAY_DATA_OFFSET(%eax,%ecx,8), %eax + GET_WIDE_FP_VREG %xmm0, rINST # xmm0 <- vAA + movq %xmm0, (%eax) # vBB[vCC] <- xmm0 + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_array_length(): +/* + * Return the length of an array. + */ + mov rINST, %eax # eax <- BA + sarl $$4, rINST # rINST <- B + GET_VREG %ecx, rINST # ecx <- vB (object ref) + testl %ecx, %ecx # is null? + je common_errNullObject + andb $$0xf, %al # eax <- A + movl MIRROR_ARRAY_LENGTH_OFFSET(%ecx), rINST + SET_VREG rINST, %eax + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_fill_array_data(): + /* fill-array-data vAA, +BBBBBBBB */ + EXPORT_PC + movl 2(rPC), %ecx # ecx <- BBBBbbbb + leal (rPC,%ecx,2), %ecx # ecx <- PC + BBBBbbbb*2 + GET_VREG %eax, rINST # eax <- vAA (array object) + movl %eax, OUT_ARG0(%esp) + movl %ecx, OUT_ARG1(%esp) + call SYMBOL(MterpFillArrayData) # (obj, payload) + REFRESH_IBASE + testb %al, %al # 0 means an exception is thrown + jz MterpPossibleException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 + +%def op_filled_new_array(helper="MterpFilledNewArray"): +/* + * Create a new array with elements filled from registers. + * + * for: filled-new-array, filled-new-array/range + */ + /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ + /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ + .extern $helper + EXPORT_PC + leal OFF_FP_SHADOWFRAME(rFP), %eax + movl %eax, OUT_ARG0(%esp) + movl rPC, OUT_ARG1(%esp) + movl rSELF, %ecx + movl %ecx, OUT_ARG2(%esp) + call SYMBOL($helper) + REFRESH_IBASE + testb %al, %al # 0 means an exception is thrown + jz MterpPossibleException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 + +%def op_filled_new_array_range(): +% op_filled_new_array(helper="MterpFilledNewArrayRange") + +%def op_new_array(): +/* + * Allocate an array of objects, specified with the array class + * and a count. + * + * The verifier guarantees that this is an array class, so we don't + * check for it here. + */ + /* new-array vA, vB, class@CCCC */ + EXPORT_PC + leal OFF_FP_SHADOWFRAME(rFP), %eax + movl %eax, OUT_ARG0(%esp) + movl rPC, OUT_ARG1(%esp) + REFRESH_INST ${opnum} + movl rINST, OUT_ARG2(%esp) + movl rSELF, %ecx + movl %ecx, OUT_ARG3(%esp) + call SYMBOL(MterpNewArray) + RESTORE_IBASE + testb %al, %al # 0 means an exception is thrown + jz MterpPossibleException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/bincmp.S b/runtime/interpreter/mterp/x86/bincmp.S deleted file mode 100644 index 28ea08e341..0000000000 --- a/runtime/interpreter/mterp/x86/bincmp.S +++ /dev/null @@ -1,22 +0,0 @@ -%def bincmp(revcmp=""): -/* - * Generic two-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - movzx rINSTbl, %ecx # ecx <- A+ - andb $$0xf, %cl # ecx <- A - GET_VREG %eax, %ecx # eax <- vA - sarl $$4, rINST # rINST <- B - cmpl VREG_ADDRESS(rINST), %eax # compare (vA, vB) - j${revcmp} 1f - movswl 2(rPC), rINST # Get signed branch offset - testl rINST, rINST - jmp MterpCommonTakenBranch -1: - cmpw $$JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/bindiv.S b/runtime/interpreter/mterp/x86/bindiv.S deleted file mode 100644 index e59e6ad680..0000000000 --- a/runtime/interpreter/mterp/x86/bindiv.S +++ /dev/null @@ -1,48 +0,0 @@ -%def bindiv(result="", special="", rem=""): -/* - * 32-bit binary div/rem operation. Handles special case of op0=minint and - * op1=-1. - */ - /* div/rem vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB - GET_VREG %ecx, %ecx # ecx <- vCC - mov rIBASE, LOCAL0(%esp) - testl %ecx, %ecx - je common_errDivideByZero - movl %eax, %edx - orl %ecx, %edx - testl $$0xFFFFFF00, %edx # If both arguments are less - # than 8-bit and +ve - jz .L${opcode}_8 # Do 8-bit divide - testl $$0xFFFF0000, %edx # If both arguments are less - # than 16-bit and +ve - jz .L${opcode}_16 # Do 16-bit divide - cmpl $$-1, %ecx - jne .L${opcode}_32 - cmpl $$0x80000000, %eax - jne .L${opcode}_32 - movl $special, $result - jmp .L${opcode}_finish -.L${opcode}_32: - cltd - idivl %ecx - jmp .L${opcode}_finish -.L${opcode}_8: - div %cl # 8-bit divide otherwise. - # Remainder in %ah, quotient in %al - .if $rem - movl %eax, %edx - shr $$8, %edx - .else - andl $$0x000000FF, %eax - .endif - jmp .L${opcode}_finish -.L${opcode}_16: - xorl %edx, %edx # Clear %edx before divide - div %cx -.L${opcode}_finish: - SET_VREG $result, rINST - mov LOCAL0(%esp), rIBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/bindiv2addr.S b/runtime/interpreter/mterp/x86/bindiv2addr.S deleted file mode 100644 index 40c22bb271..0000000000 --- a/runtime/interpreter/mterp/x86/bindiv2addr.S +++ /dev/null @@ -1,29 +0,0 @@ -%def bindiv2addr(result="", special=""): -/* - * 32-bit binary div/rem operation. Handles special case of op0=minint and - * op1=-1. - */ - /* div/rem/2addr vA, vB */ - movzx rINSTbl, %ecx # eax <- BA - mov rIBASE, LOCAL0(%esp) - sarl $$4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # eax <- vBB - andb $$0xf, rINSTbl # rINST <- A - GET_VREG %eax, rINST # eax <- vBB - testl %ecx, %ecx - je common_errDivideByZero - cmpl $$-1, %ecx - jne .L${opcode}_continue_div2addr - cmpl $$0x80000000, %eax - jne .L${opcode}_continue_div2addr - movl $special, $result - SET_VREG $result, rINST - mov LOCAL0(%esp), rIBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -.L${opcode}_continue_div2addr: - cltd - idivl %ecx - SET_VREG $result, rINST - mov LOCAL0(%esp), rIBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/bindivLit16.S b/runtime/interpreter/mterp/x86/bindivLit16.S deleted file mode 100644 index a89f452031..0000000000 --- a/runtime/interpreter/mterp/x86/bindivLit16.S +++ /dev/null @@ -1,29 +0,0 @@ -%def bindivLit16(result="", special=""): -/* - * 32-bit binary div/rem operation. Handles special case of op0=minint and - * op1=-1. - */ - /* div/rem/lit16 vA, vB, #+CCCC */ - /* Need A in rINST, ssssCCCC in ecx, vB in eax */ - movzbl rINSTbl, %eax # eax <- 000000BA - sarl $$4, %eax # eax <- B - GET_VREG %eax, %eax # eax <- vB - movswl 2(rPC), %ecx # ecx <- ssssCCCC - andb $$0xf, rINSTbl # rINST <- A - testl %ecx, %ecx - je common_errDivideByZero - cmpl $$-1, %ecx - jne .L${opcode}_continue_div - cmpl $$0x80000000, %eax - jne .L${opcode}_continue_div - movl $special, %eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -.L${opcode}_continue_div: - mov rIBASE, LOCAL0(%esp) - cltd - idivl %ecx - SET_VREG $result, rINST - mov LOCAL0(%esp), rIBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/bindivLit8.S b/runtime/interpreter/mterp/x86/bindivLit8.S deleted file mode 100644 index ce130194b0..0000000000 --- a/runtime/interpreter/mterp/x86/bindivLit8.S +++ /dev/null @@ -1,26 +0,0 @@ -%def bindivLit8(result="", special=""): -/* - * 32-bit div/rem "lit8" binary operation. Handles special case of - * op0=minint & op1=-1 - */ - /* div/rem/lit8 vAA, vBB, #+CC */ - movzbl 2(rPC), %eax # eax <- BB - movsbl 3(rPC), %ecx # ecx <- ssssssCC - GET_VREG %eax, %eax # eax <- rBB - testl %ecx, %ecx - je common_errDivideByZero - cmpl $$0x80000000, %eax - jne .L${opcode}_continue_div - cmpl $$-1, %ecx - jne .L${opcode}_continue_div - movl $special, %eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -.L${opcode}_continue_div: - mov rIBASE, LOCAL0(%esp) - cltd - idivl %ecx - SET_VREG $result, rINST - mov LOCAL0(%esp), rIBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/binop.S b/runtime/interpreter/mterp/x86/binop.S deleted file mode 100644 index c82737209d..0000000000 --- a/runtime/interpreter/mterp/x86/binop.S +++ /dev/null @@ -1,17 +0,0 @@ -%def binop(result="%eax", instr=""): -/* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = eax op (rFP,%ecx,4)". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int, sub-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB - $instr # ex: addl (rFP,%ecx,4),%eax - SET_VREG $result, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/binop1.S b/runtime/interpreter/mterp/x86/binop1.S deleted file mode 100644 index e6ae857eed..0000000000 --- a/runtime/interpreter/mterp/x86/binop1.S +++ /dev/null @@ -1,13 +0,0 @@ -%def binop1(result="%eax", tmp="%ecx", instr=""): -/* - * Generic 32-bit binary operation in which both operands loaded to - * registers (op0 in eax, op1 in ecx). - */ - /* binop vAA, vBB, vCC */ - movzbl 2(rPC),%eax # eax <- BB - movzbl 3(rPC),%ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB - GET_VREG %ecx, %ecx # eax <- vBB - $instr # ex: addl %ecx,%eax - SET_VREG $result, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/binop2addr.S b/runtime/interpreter/mterp/x86/binop2addr.S deleted file mode 100644 index 0b74364897..0000000000 --- a/runtime/interpreter/mterp/x86/binop2addr.S +++ /dev/null @@ -1,19 +0,0 @@ -%def binop2addr(result="%eax", instr=""): -/* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an instruction or a function call. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - movzx rINSTbl, %ecx # ecx <- A+ - sarl $$4, rINST # rINST <- B - GET_VREG %eax, rINST # eax <- vB - andb $$0xf, %cl # ecx <- A - $instr # for ex: addl %eax,(rFP,%ecx,4) - CLEAR_REF %ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/binopLit16.S b/runtime/interpreter/mterp/x86/binopLit16.S deleted file mode 100644 index 5b162f16ca..0000000000 --- a/runtime/interpreter/mterp/x86/binopLit16.S +++ /dev/null @@ -1,19 +0,0 @@ -%def binopLit16(result="%eax", instr=""): -/* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int/lit16, rsub-int, - * and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - movzbl rINSTbl, %eax # eax <- 000000BA - sarl $$4, %eax # eax <- B - GET_VREG %eax, %eax # eax <- vB - movswl 2(rPC), %ecx # ecx <- ssssCCCC - andb $$0xf, rINSTbl # rINST <- A - $instr # for example: addl %ecx, %eax - SET_VREG $result, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/binopLit8.S b/runtime/interpreter/mterp/x86/binopLit8.S deleted file mode 100644 index c2ebc1800c..0000000000 --- a/runtime/interpreter/mterp/x86/binopLit8.S +++ /dev/null @@ -1,18 +0,0 @@ -%def binopLit8(result="%eax", instr=""): -/* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * For: add-int/lit8, rsub-int/lit8 - * and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - movzbl 2(rPC), %eax # eax <- BB - movsbl 3(rPC), %ecx # ecx <- ssssssCC - GET_VREG %eax, %eax # eax <- rBB - $instr # ex: addl %ecx,%eax - SET_VREG $result, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/binopWide.S b/runtime/interpreter/mterp/x86/binopWide.S deleted file mode 100644 index 1e878c8991..0000000000 --- a/runtime/interpreter/mterp/x86/binopWide.S +++ /dev/null @@ -1,16 +0,0 @@ -%def binopWide(instr1="", instr2=""): -/* - * Generic 64-bit binary operation. - */ - /* binop vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - movl rIBASE, LOCAL0(%esp) # save rIBASE - GET_VREG rIBASE, %eax # rIBASE <- v[BB+0] - GET_VREG_HIGH %eax, %eax # eax <- v[BB+1] - $instr1 # ex: addl (rFP,%ecx,4),rIBASE - $instr2 # ex: adcl 4(rFP,%ecx,4),%eax - SET_VREG rIBASE, rINST # v[AA+0] <- rIBASE - movl LOCAL0(%esp), rIBASE # restore rIBASE - SET_VREG_HIGH %eax, rINST # v[AA+1] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/binopWide2addr.S b/runtime/interpreter/mterp/x86/binopWide2addr.S deleted file mode 100644 index 65da1df36c..0000000000 --- a/runtime/interpreter/mterp/x86/binopWide2addr.S +++ /dev/null @@ -1,14 +0,0 @@ -%def binopWide2addr(instr1="", instr2=""): -/* - * Generic 64-bit binary operation. - */ - /* binop/2addr vA, vB */ - movzbl rINSTbl, %ecx # ecx<- BA - sarl $$4, %ecx # ecx<- B - GET_VREG %eax, %ecx # eax<- v[B+0] - GET_VREG_HIGH %ecx, %ecx # eax<- v[B+1] - andb $$0xF, rINSTbl # rINST<- A - $instr1 # ex: addl %eax,(rFP,rINST,4) - $instr2 # ex: adcl %ecx,4(rFP,rINST,4) - CLEAR_WIDE_REF rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/const.S b/runtime/interpreter/mterp/x86/const.S deleted file mode 100644 index aad76bb4ee..0000000000 --- a/runtime/interpreter/mterp/x86/const.S +++ /dev/null @@ -1,19 +0,0 @@ -%def const(helper="UndefinedConstHandler"): - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern $helper - EXPORT_PC - movzwl 2(rPC), %eax # eax <- BBBB - movl %eax, OUT_ARG0(%esp) - movl rINST, OUT_ARG1(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) - call SYMBOL($helper) # (index, tgt_reg, shadow_frame, self) - RESTORE_IBASE - testb %al, %al - jnz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/control_flow.S b/runtime/interpreter/mterp/x86/control_flow.S new file mode 100644 index 0000000000..74b4fad34f --- /dev/null +++ b/runtime/interpreter/mterp/x86/control_flow.S @@ -0,0 +1,219 @@ +%def bincmp(revcmp=""): +/* + * Generic two-operand compare-and-branch operation. Provide a "revcmp" + * fragment that specifies the *reverse* comparison to perform, e.g. + * for "if-le" you would use "gt". + * + * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le + */ + /* if-cmp vA, vB, +CCCC */ + movzx rINSTbl, %ecx # ecx <- A+ + andb $$0xf, %cl # ecx <- A + GET_VREG %eax, %ecx # eax <- vA + sarl $$4, rINST # rINST <- B + cmpl VREG_ADDRESS(rINST), %eax # compare (vA, vB) + j${revcmp} 1f + movswl 2(rPC), rINST # Get signed branch offset + testl rINST, rINST + jmp MterpCommonTakenBranch +1: + cmpw $$JIT_CHECK_OSR, rPROFILE + je .L_check_not_taken_osr + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def zcmp(revcmp=""): +/* + * Generic one-operand compare-and-branch operation. Provide a "revcmp" + * fragment that specifies the *reverse* comparison to perform, e.g. + * for "if-le" you would use "gt". + * + * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez + */ + /* if-cmp vAA, +BBBB */ + cmpl $$0, VREG_ADDRESS(rINST) # compare (vA, 0) + j${revcmp} 1f + movswl 2(rPC), rINST # fetch signed displacement + testl rINST, rINST + jmp MterpCommonTakenBranch +1: + cmpw $$JIT_CHECK_OSR, rPROFILE + je .L_check_not_taken_osr + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_goto(): +/* + * Unconditional branch, 8-bit offset. + * + * The branch distance is a signed code-unit offset, which we need to + * double to get a byte offset. + */ + /* goto +AA */ + movsbl rINSTbl, rINST # rINST <- ssssssAA + testl rINST, rINST + jmp MterpCommonTakenBranch + +%def op_goto_16(): +/* + * Unconditional branch, 16-bit offset. + * + * The branch distance is a signed code-unit offset, which we need to + * double to get a byte offset. + */ + /* goto/16 +AAAA */ + movswl 2(rPC), rINST # rINST <- ssssAAAA + testl rINST, rINST + jmp MterpCommonTakenBranch + +%def op_goto_32(): +/* + * Unconditional branch, 32-bit offset. + * + * The branch distance is a signed code-unit offset, which we need to + * double to get a byte offset. + * + * Unlike most opcodes, this one is allowed to branch to itself, so + * our "backward branch" test must be "<=0" instead of "<0". Because + * we need the V bit set, we'll use an adds to convert from Dalvik + * offset to byte offset. + */ + /* goto/32 +AAAAAAAA */ + movl 2(rPC), rINST # rINST <- AAAAAAAA + testl rINST, rINST + jmp MterpCommonTakenBranch + +%def op_if_eq(): +% bincmp(revcmp="ne") + +%def op_if_eqz(): +% zcmp(revcmp="ne") + +%def op_if_ge(): +% bincmp(revcmp="l") + +%def op_if_gez(): +% zcmp(revcmp="l") + +%def op_if_gt(): +% bincmp(revcmp="le") + +%def op_if_gtz(): +% zcmp(revcmp="le") + +%def op_if_le(): +% bincmp(revcmp="g") + +%def op_if_lez(): +% zcmp(revcmp="g") + +%def op_if_lt(): +% bincmp(revcmp="ge") + +%def op_if_ltz(): +% zcmp(revcmp="ge") + +%def op_if_ne(): +% bincmp(revcmp="e") + +%def op_if_nez(): +% zcmp(revcmp="e") + +%def op_packed_switch(func="MterpDoPackedSwitch"): +/* + * Handle a packed-switch or sparse-switch instruction. In both cases + * we decode it and hand it off to a helper function. + * + * We don't really expect backward branches in a switch statement, but + * they're perfectly legal, so we check for them here. + * + * for: packed-switch, sparse-switch + */ + /* op vAA, +BBBB */ + movl 2(rPC), %ecx # ecx <- BBBBbbbb + GET_VREG %eax, rINST # eax <- vAA + leal (rPC,%ecx,2), %ecx # ecx <- PC + BBBBbbbb*2 + movl %eax, OUT_ARG1(%esp) # ARG1 <- vAA + movl %ecx, OUT_ARG0(%esp) # ARG0 <- switchData + call SYMBOL($func) + REFRESH_IBASE + testl %eax, %eax + movl %eax, rINST + jmp MterpCommonTakenBranch + +%def op_return(): +/* + * Return a 32-bit value. + * + * for: return, return-object + */ + /* op vAA */ + .extern MterpThreadFenceForConstructor + call SYMBOL(MterpThreadFenceForConstructor) + movl rSELF, %eax + testl $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(%eax) + jz 1f + movl %eax, OUT_ARG0(%esp) + call SYMBOL(MterpSuspendCheck) +1: + GET_VREG %eax, rINST # eax <- vAA + xorl %ecx, %ecx + jmp MterpReturn + +%def op_return_object(): +% op_return() + +%def op_return_void(): + .extern MterpThreadFenceForConstructor + call SYMBOL(MterpThreadFenceForConstructor) + movl rSELF, %eax + testl $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(%eax) + jz 1f + movl %eax, OUT_ARG0(%esp) + call SYMBOL(MterpSuspendCheck) +1: + xorl %eax, %eax + xorl %ecx, %ecx + jmp MterpReturn + +%def op_return_void_no_barrier(): + movl rSELF, %eax + testl $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(%eax) + jz 1f + movl %eax, OUT_ARG0(%esp) + call SYMBOL(MterpSuspendCheck) +1: + xorl %eax, %eax + xorl %ecx, %ecx + jmp MterpReturn + +%def op_return_wide(): +/* + * Return a 64-bit value. + */ + /* return-wide vAA */ + .extern MterpThreadFenceForConstructor + call SYMBOL(MterpThreadFenceForConstructor) + movl rSELF, %eax + testl $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(%eax) + jz 1f + movl %eax, OUT_ARG0(%esp) + call SYMBOL(MterpSuspendCheck) +1: + GET_VREG %eax, rINST # eax <- v[AA+0] + GET_VREG_HIGH %ecx, rINST # ecx <- v[AA+1] + jmp MterpReturn + +%def op_sparse_switch(): +% op_packed_switch(func="MterpDoSparseSwitch") + +%def op_throw(): +/* + * Throw an exception object in the current thread. + */ + /* throw vAA */ + EXPORT_PC + GET_VREG %eax, rINST # eax<- vAA (exception object) + testl %eax, %eax + jz common_errNullObject + movl rSELF,%ecx + movl %eax, THREAD_EXCEPTION_OFFSET(%ecx) + jmp MterpException diff --git a/runtime/interpreter/mterp/x86/cvtfp_int.S b/runtime/interpreter/mterp/x86/cvtfp_int.S deleted file mode 100644 index 0bc9908e94..0000000000 --- a/runtime/interpreter/mterp/x86/cvtfp_int.S +++ /dev/null @@ -1,61 +0,0 @@ -%def cvtfp_int(srcdouble="1", tgtlong="1"): -/* On fp to int conversions, Java requires that - * if the result > maxint, it should be clamped to maxint. If it is less - * than minint, it should be clamped to minint. If it is a nan, the result - * should be zero. Further, the rounding mode is to truncate. This model - * differs from what is delivered normally via the x86 fpu, so we have - * to play some games. - */ - /* float/double to int/long vA, vB */ - movzbl rINSTbl, %ecx # ecx <- A+ - sarl $$4, rINST # rINST <- B - .if $srcdouble - fldl VREG_ADDRESS(rINST) # %st0 <- vB - .else - flds VREG_ADDRESS(rINST) # %st0 <- vB - .endif - ftst - fnstcw LOCAL0(%esp) # remember original rounding mode - movzwl LOCAL0(%esp), %eax - movb $$0xc, %ah - movw %ax, LOCAL0+2(%esp) - fldcw LOCAL0+2(%esp) # set "to zero" rounding mode - andb $$0xf, %cl # ecx <- A - .if $tgtlong - fistpll VREG_ADDRESS(%ecx) # convert and store - .else - fistpl VREG_ADDRESS(%ecx) # convert and store - .endif - fldcw LOCAL0(%esp) # restore previous rounding mode - .if $tgtlong - movl $$0x80000000, %eax - xorl VREG_HIGH_ADDRESS(%ecx), %eax - orl VREG_ADDRESS(%ecx), %eax - .else - cmpl $$0x80000000, VREG_ADDRESS(%ecx) - .endif - je .L${opcode}_special_case # fix up result - -.L${opcode}_finish: - xor %eax, %eax - mov %eax, VREG_REF_ADDRESS(%ecx) - .if $tgtlong - mov %eax, VREG_REF_HIGH_ADDRESS(%ecx) - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -.L${opcode}_special_case: - fnstsw %ax - sahf - jp .L${opcode}_isNaN - adcl $$-1, VREG_ADDRESS(%ecx) - .if $tgtlong - adcl $$-1, VREG_HIGH_ADDRESS(%ecx) - .endif - jmp .L${opcode}_finish -.L${opcode}_isNaN: - movl $$0, VREG_ADDRESS(%ecx) - .if $tgtlong - movl $$0, VREG_HIGH_ADDRESS(%ecx) - .endif - jmp .L${opcode}_finish diff --git a/runtime/interpreter/mterp/x86/entry.S b/runtime/interpreter/mterp/x86/entry.S deleted file mode 100644 index b6291c1393..0000000000 --- a/runtime/interpreter/mterp/x86/entry.S +++ /dev/null @@ -1,84 +0,0 @@ -%def entry(): -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -/* - * Interpreter entry point. - */ - - .text - ASM_HIDDEN SYMBOL(ExecuteMterpImpl) - .global SYMBOL(ExecuteMterpImpl) - FUNCTION_TYPE(ExecuteMterpImpl) - -/* - * On entry: - * 0 Thread* self - * 1 insns_ - * 2 ShadowFrame - * 3 JValue* result_register - * - */ - -SYMBOL(ExecuteMterpImpl): - .cfi_startproc - .cfi_def_cfa esp, 4 - - /* Spill callee save regs */ - PUSH %ebp - PUSH %edi - PUSH %esi - PUSH %ebx - - /* Allocate frame */ - subl $$FRAME_SIZE, %esp - .cfi_adjust_cfa_offset FRAME_SIZE - - /* Load ShadowFrame pointer */ - movl IN_ARG2(%esp), %edx - - /* Remember the return register */ - movl IN_ARG3(%esp), %eax - movl %eax, SHADOWFRAME_RESULT_REGISTER_OFFSET(%edx) - - /* Remember the code_item */ - movl IN_ARG1(%esp), %ecx - movl %ecx, SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET(%edx) - - /* set up "named" registers */ - movl SHADOWFRAME_NUMBER_OF_VREGS_OFFSET(%edx), %eax - leal SHADOWFRAME_VREGS_OFFSET(%edx), rFP - leal (rFP, %eax, 4), rREFS - movl SHADOWFRAME_DEX_PC_OFFSET(%edx), %eax - lea (%ecx, %eax, 2), rPC - CFI_DEFINE_DEX_PC_WITH_OFFSET(CFI_TMP, CFI_DEX, 0) - EXPORT_PC - - /* Set up for backwards branches & osr profiling */ - movl OFF_FP_METHOD(rFP), %eax - movl %eax, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - movl rSELF, %eax - movl %eax, OUT_ARG2(%esp) - call SYMBOL(MterpSetUpHotnessCountdown) - - /* Starting ibase */ - REFRESH_IBASE - - /* start executing the instruction at rPC */ - FETCH_INST - GOTO_NEXT - /* NOTE: no fallthrough */ diff --git a/runtime/interpreter/mterp/x86/fallback.S b/runtime/interpreter/mterp/x86/fallback.S deleted file mode 100644 index e3c2e2bd40..0000000000 --- a/runtime/interpreter/mterp/x86/fallback.S +++ /dev/null @@ -1,4 +0,0 @@ -%def fallback(): -/* Transfer stub to alternate interpreter */ - jmp MterpFallback - diff --git a/runtime/interpreter/mterp/x86/field.S b/runtime/interpreter/mterp/x86/field.S deleted file mode 100644 index 06362d866b..0000000000 --- a/runtime/interpreter/mterp/x86/field.S +++ /dev/null @@ -1,17 +0,0 @@ -%def field(helper=""): - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern $helper - REFRESH_INST ${opnum} # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL($helper) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/floating_point.S b/runtime/interpreter/mterp/x86/floating_point.S new file mode 100644 index 0000000000..3de1fc8f19 --- /dev/null +++ b/runtime/interpreter/mterp/x86/floating_point.S @@ -0,0 +1,236 @@ +%def fpcmp(suff="d", nanval="pos"): +/* + * Compare two floating-point values. Puts 0, 1, or -1 into the + * destination register based on the results of the comparison. + * + * int compare(x, y) { + * if (x == y) { + * return 0; + * } else if (x < y) { + * return -1; + * } else if (x > y) { + * return 1; + * } else { + * return nanval ? 1 : -1; + * } + * } + */ + /* op vAA, vBB, vCC */ + movzbl 3(rPC), %ecx # ecx<- CC + movzbl 2(rPC), %eax # eax<- BB + movs${suff} VREG_ADDRESS(%eax), %xmm0 + xor %eax, %eax + ucomis${suff} VREG_ADDRESS(%ecx), %xmm0 + jp .L${opcode}_nan_is_${nanval} + je .L${opcode}_finish + jb .L${opcode}_less +.L${opcode}_nan_is_pos: + incl %eax + jmp .L${opcode}_finish +.L${opcode}_nan_is_neg: +.L${opcode}_less: + decl %eax +.L${opcode}_finish: + SET_VREG %eax, rINST + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def fpcvt(instr="", load="", store="", wide="0"): +/* + * Generic 32-bit FP conversion operation. + */ + /* unop vA, vB */ + movzbl rINSTbl, %ecx # ecx <- A+ + sarl $$4, rINST # rINST <- B + $load VREG_ADDRESS(rINST) # %st0 <- vB + andb $$0xf, %cl # ecx <- A + $instr + $store VREG_ADDRESS(%ecx) # vA <- %st0 + .if $wide + CLEAR_WIDE_REF %ecx + .else + CLEAR_REF %ecx + .endif + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def sseBinop(instr="", suff=""): + movzbl 2(rPC), %ecx # ecx <- BB + movzbl 3(rPC), %eax # eax <- CC + movs${suff} VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src + ${instr}${suff} VREG_ADDRESS(%eax), %xmm0 + movs${suff} %xmm0, VREG_ADDRESS(rINST) # vAA <- %xmm0 + pxor %xmm0, %xmm0 + movs${suff} %xmm0, VREG_REF_ADDRESS(rINST) # clear ref + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def sseBinop2Addr(instr="", suff=""): + movzx rINSTbl, %ecx # ecx <- A+ + andl $$0xf, %ecx # ecx <- A + movs${suff} VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src + sarl $$4, rINST # rINST<- B + ${instr}${suff} VREG_ADDRESS(rINST), %xmm0 + movs${suff} %xmm0, VREG_ADDRESS(%ecx) # vAA<- %xmm0 + pxor %xmm0, %xmm0 + movs${suff} %xmm0, VREG_REF_ADDRESS(rINST) # clear ref + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_add_double(): +% sseBinop(instr="adds", suff="d") + +%def op_add_double_2addr(): +% sseBinop2Addr(instr="adds", suff="d") + +%def op_add_float(): +% sseBinop(instr="adds", suff="s") + +%def op_add_float_2addr(): +% sseBinop2Addr(instr="adds", suff="s") + +%def op_cmpg_double(): +% fpcmp(suff="d", nanval="pos") + +%def op_cmpg_float(): +% fpcmp(suff="s", nanval="pos") + +%def op_cmpl_double(): +% fpcmp(suff="d", nanval="neg") + +%def op_cmpl_float(): +% fpcmp(suff="s", nanval="neg") + +%def op_div_double(): +% sseBinop(instr="divs", suff="d") + +%def op_div_double_2addr(): +% sseBinop2Addr(instr="divs", suff="d") + +%def op_div_float(): +% sseBinop(instr="divs", suff="s") + +%def op_div_float_2addr(): +% sseBinop2Addr(instr="divs", suff="s") + +%def op_double_to_float(): +% fpcvt(load="fldl", store="fstps") + +%def op_double_to_int(): +% cvtfp_int(srcdouble="1", tgtlong="0") + +%def op_double_to_long(): +% cvtfp_int(srcdouble="1", tgtlong="1") + +%def op_float_to_double(): +% fpcvt(load="flds", store="fstpl", wide="1") + +%def op_float_to_int(): +% cvtfp_int(srcdouble="0", tgtlong="0") + +%def op_float_to_long(): +% cvtfp_int(srcdouble="0", tgtlong="1") + +%def op_int_to_double(): +% fpcvt(load="fildl", store="fstpl", wide="1") + +%def op_int_to_float(): +% fpcvt(load="fildl", store="fstps") + +%def op_long_to_double(): +% fpcvt(load="fildll", store="fstpl", wide="1") + +%def op_long_to_float(): +% fpcvt(load="fildll", store="fstps") + +%def op_mul_double(): +% sseBinop(instr="muls", suff="d") + +%def op_mul_double_2addr(): +% sseBinop2Addr(instr="muls", suff="d") + +%def op_mul_float(): +% sseBinop(instr="muls", suff="s") + +%def op_mul_float_2addr(): +% sseBinop2Addr(instr="muls", suff="s") + +%def op_neg_double(): +% fpcvt(instr="fchs", load="fldl", store="fstpl", wide="1") + +%def op_neg_float(): +% fpcvt(instr="fchs", load="flds", store="fstps") + +%def op_rem_double(): + /* rem_double vAA, vBB, vCC */ + movzbl 3(rPC), %ecx # ecx <- BB + movzbl 2(rPC), %eax # eax <- CC + fldl VREG_ADDRESS(%ecx) # %st1 <- fp[vBB] + fldl VREG_ADDRESS(%eax) # %st0 <- fp[vCC] +1: + fprem + fstsw %ax + sahf + jp 1b + fstp %st(1) + fstpl VREG_ADDRESS(rINST) # fp[vAA] <- %st + CLEAR_WIDE_REF rINST + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_rem_double_2addr(): + /* rem_double/2addr vA, vB */ + movzx rINSTbl, %ecx # ecx <- A+ + sarl $$4, rINST # rINST <- B + fldl VREG_ADDRESS(rINST) # vB to fp stack + andb $$0xf, %cl # ecx <- A + fldl VREG_ADDRESS(%ecx) # vA to fp stack +1: + fprem + fstsw %ax + sahf + jp 1b + fstp %st(1) + fstpl VREG_ADDRESS(%ecx) # %st to vA + CLEAR_WIDE_REF %ecx + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_rem_float(): + /* rem_float vAA, vBB, vCC */ + movzbl 3(rPC), %ecx # ecx <- BB + movzbl 2(rPC), %eax # eax <- CC + flds VREG_ADDRESS(%ecx) # vBB to fp stack + flds VREG_ADDRESS(%eax) # vCC to fp stack +1: + fprem + fstsw %ax + sahf + jp 1b + fstp %st(1) + fstps VREG_ADDRESS(rINST) # %st to vAA + CLEAR_REF rINST + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_rem_float_2addr(): + /* rem_float/2addr vA, vB */ + movzx rINSTbl, %ecx # ecx <- A+ + sarl $$4, rINST # rINST <- B + flds VREG_ADDRESS(rINST) # vB to fp stack + andb $$0xf, %cl # ecx <- A + flds VREG_ADDRESS(%ecx) # vA to fp stack +1: + fprem + fstsw %ax + sahf + jp 1b + fstp %st(1) + fstps VREG_ADDRESS(%ecx) # %st to vA + CLEAR_REF %ecx + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_sub_double(): +% sseBinop(instr="subs", suff="d") + +%def op_sub_double_2addr(): +% sseBinop2Addr(instr="subs", suff="d") + +%def op_sub_float(): +% sseBinop(instr="subs", suff="s") + +%def op_sub_float_2addr(): +% sseBinop2Addr(instr="subs", suff="s") diff --git a/runtime/interpreter/mterp/x86/footer.S b/runtime/interpreter/mterp/x86/footer.S deleted file mode 100644 index 31cc067d5a..0000000000 --- a/runtime/interpreter/mterp/x86/footer.S +++ /dev/null @@ -1,326 +0,0 @@ -%def footer(): -/* - * =========================================================================== - * Common subroutines and data - * =========================================================================== - */ - - .text - .align 2 - -/* - * We've detected a condition that will result in an exception, but the exception - * has not yet been thrown. Just bail out to the reference interpreter to deal with it. - * TUNING: for consistency, we may want to just go ahead and handle these here. - */ -common_errDivideByZero: - EXPORT_PC -#if MTERP_LOGGING - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - lea OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - call SYMBOL(MterpLogDivideByZeroException) -#endif - jmp MterpCommonFallback - -common_errArrayIndex: - EXPORT_PC -#if MTERP_LOGGING - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - lea OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - call SYMBOL(MterpLogArrayIndexException) -#endif - jmp MterpCommonFallback - -common_errNegativeArraySize: - EXPORT_PC -#if MTERP_LOGGING - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - lea OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - call SYMBOL(MterpLogNegativeArraySizeException) -#endif - jmp MterpCommonFallback - -common_errNoSuchMethod: - EXPORT_PC -#if MTERP_LOGGING - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - lea OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - call SYMBOL(MterpLogNoSuchMethodException) -#endif - jmp MterpCommonFallback - -common_errNullObject: - EXPORT_PC -#if MTERP_LOGGING - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - lea OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - call SYMBOL(MterpLogNullObjectException) -#endif - jmp MterpCommonFallback - -common_exceptionThrown: - EXPORT_PC -#if MTERP_LOGGING - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - lea OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG0(%esp) - call SYMBOL(MterpLogExceptionThrownException) -#endif - jmp MterpCommonFallback - -MterpSuspendFallback: - EXPORT_PC -#if MTERP_LOGGING - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - lea OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG0(%esp) - movl THREAD_FLAGS_OFFSET(%eax), %eax - movl %eax, OUT_ARG2(%esp) - call SYMBOL(MterpLogSuspendFallback) -#endif - jmp MterpCommonFallback - -/* - * If we're here, something is out of the ordinary. If there is a pending - * exception, handle it. Otherwise, roll back and retry with the reference - * interpreter. - */ -MterpPossibleException: - movl rSELF, %eax - testl $$-1, THREAD_EXCEPTION_OFFSET(%eax) - jz MterpFallback - /* intentional fallthrough - handle pending exception. */ - -/* - * On return from a runtime helper routine, we've found a pending exception. - * Can we handle it here - or need to bail out to caller? - * - */ -MterpException: - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - lea OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - call SYMBOL(MterpHandleException) - testb %al, %al - jz MterpExceptionReturn - movl OFF_FP_DEX_INSTRUCTIONS(rFP), %eax - movl OFF_FP_DEX_PC(rFP), %ecx - lea (%eax, %ecx, 2), rPC - movl rPC, OFF_FP_DEX_PC_PTR(rFP) - /* Do we need to switch interpreters? */ - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - /* resume execution at catch block */ - REFRESH_IBASE - FETCH_INST - GOTO_NEXT - /* NOTE: no fallthrough */ - -/* - * Common handling for branches with support for Jit profiling. - * On entry: - * rINST <= signed offset - * condition bits <= set to establish sign of offset (use "NoFlags" entry if not) - * - * We have quite a few different cases for branch profiling, OSR detection and - * suspend check support here. - * - * Taken backward branches: - * If profiling active, do hotness countdown and report if we hit zero. - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * Is there a pending suspend request? If so, suspend. - * - * Taken forward branches and not-taken backward branches: - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * - * Our most common case is expected to be a taken backward branch with active jit profiling, - * but no full OSR check and no pending suspend request. - * Next most common case is not-taken branch with no full OSR check. - * - */ -MterpCommonTakenBranch: - jg .L_forward_branch # don't add forward branches to hotness -/* - * We need to subtract 1 from positive values and we should not see 0 here, - * so we may use the result of the comparison with -1. - */ -#if JIT_CHECK_OSR != -1 -# error "JIT_CHECK_OSR must be -1." -#endif - cmpw $$JIT_CHECK_OSR, rPROFILE - je .L_osr_check - decw rPROFILE - je .L_add_batch # counted down to zero - report -.L_resume_backward_branch: - movl rSELF, %eax - testl $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(%eax) - leal (rPC, rINST, 2), rPC - FETCH_INST - jnz .L_suspend_request_pending - REFRESH_IBASE - GOTO_NEXT - -.L_suspend_request_pending: - EXPORT_PC - movl %eax, OUT_ARG0(%esp) # rSELF in eax - call SYMBOL(MterpSuspendCheck) # (self) - testb %al, %al - jnz MterpFallback - REFRESH_IBASE # might have changed during suspend - GOTO_NEXT - -.L_no_count_backwards: - cmpw $$JIT_CHECK_OSR, rPROFILE # possible OSR re-entry? - jne .L_resume_backward_branch -.L_osr_check: - EXPORT_PC - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - movl rINST, OUT_ARG2(%esp) - call SYMBOL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) - testb %al, %al - jz .L_resume_backward_branch - jmp MterpOnStackReplacement - -.L_forward_branch: - cmpw $$JIT_CHECK_OSR, rPROFILE # possible OSR re-entry? - je .L_check_osr_forward -.L_resume_forward_branch: - leal (rPC, rINST, 2), rPC - FETCH_INST - GOTO_NEXT - -.L_check_osr_forward: - EXPORT_PC - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - movl rINST, OUT_ARG2(%esp) - call SYMBOL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) - testb %al, %al - REFRESH_IBASE - jz .L_resume_forward_branch - jmp MterpOnStackReplacement - -.L_add_batch: - movl OFF_FP_METHOD(rFP), %eax - movl %eax, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - movl rSELF, %eax - movl %eax, OUT_ARG2(%esp) - call SYMBOL(MterpAddHotnessBatch) # (method, shadow_frame, self) - jmp .L_no_count_backwards - -/* - * Entered from the conditional branch handlers when OSR check request active on - * not-taken path. All Dalvik not-taken conditional branch offsets are 2. - */ -.L_check_not_taken_osr: - EXPORT_PC - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - movl $$2, OUT_ARG2(%esp) - call SYMBOL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) - testb %al, %al - REFRESH_IBASE - jnz MterpOnStackReplacement - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* - * On-stack replacement has happened, and now we've returned from the compiled method. - */ -MterpOnStackReplacement: -#if MTERP_LOGGING - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - lea OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - movl rINST, OUT_ARG2(%esp) - call SYMBOL(MterpLogOSR) -#endif - movl $$1, %eax - jmp MterpDone - -/* - * Bail out to reference interpreter. - */ -MterpFallback: - EXPORT_PC -#if MTERP_LOGGING - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - lea OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - call SYMBOL(MterpLogFallback) -#endif -MterpCommonFallback: - xor %eax, %eax - jmp MterpDone - -/* - * On entry: - * uint32_t* rFP (should still be live, pointer to base of vregs) - */ -MterpExceptionReturn: - movl $$1, %eax - jmp MterpDone -MterpReturn: - movl OFF_FP_RESULT_REGISTER(rFP), %edx - movl %eax, (%edx) - movl %ecx, 4(%edx) - mov $$1, %eax -MterpDone: -/* - * At this point, we expect rPROFILE to be non-zero. If negative, hotness is disabled or we're - * checking for OSR. If greater than zero, we might have unreported hotness to register - * (the difference between the ending rPROFILE and the cached hotness counter). rPROFILE - * should only reach zero immediately after a hotness decrement, and is then reset to either - * a negative special state or the new non-zero countdown value. - */ - cmpw $$0, rPROFILE - jle MRestoreFrame # if > 0, we may have some counts to report. - - movl %eax, rINST # stash return value - /* Report cached hotness counts */ - movl OFF_FP_METHOD(rFP), %eax - movl %eax, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - movl rSELF, %eax - movl %eax, OUT_ARG2(%esp) - call SYMBOL(MterpAddHotnessBatch) # (method, shadow_frame, self) - movl rINST, %eax # restore return value - - /* pop up frame */ -MRestoreFrame: - addl $$FRAME_SIZE, %esp - .cfi_adjust_cfa_offset -FRAME_SIZE - - /* Restore callee save register */ - POP %ebx - POP %esi - POP %edi - POP %ebp - ret - .cfi_endproc - SIZE(ExecuteMterpImpl,ExecuteMterpImpl) diff --git a/runtime/interpreter/mterp/x86/fpcmp.S b/runtime/interpreter/mterp/x86/fpcmp.S deleted file mode 100644 index 7cd18f6227..0000000000 --- a/runtime/interpreter/mterp/x86/fpcmp.S +++ /dev/null @@ -1,35 +0,0 @@ -%def fpcmp(suff="d", nanval="pos"): -/* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * int compare(x, y) { - * if (x == y) { - * return 0; - * } else if (x < y) { - * return -1; - * } else if (x > y) { - * return 1; - * } else { - * return nanval ? 1 : -1; - * } - * } - */ - /* op vAA, vBB, vCC */ - movzbl 3(rPC), %ecx # ecx<- CC - movzbl 2(rPC), %eax # eax<- BB - movs${suff} VREG_ADDRESS(%eax), %xmm0 - xor %eax, %eax - ucomis${suff} VREG_ADDRESS(%ecx), %xmm0 - jp .L${opcode}_nan_is_${nanval} - je .L${opcode}_finish - jb .L${opcode}_less -.L${opcode}_nan_is_pos: - incl %eax - jmp .L${opcode}_finish -.L${opcode}_nan_is_neg: -.L${opcode}_less: - decl %eax -.L${opcode}_finish: - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/fpcvt.S b/runtime/interpreter/mterp/x86/fpcvt.S deleted file mode 100644 index 4280f1580e..0000000000 --- a/runtime/interpreter/mterp/x86/fpcvt.S +++ /dev/null @@ -1,17 +0,0 @@ -%def fpcvt(instr="", load="", store="", wide="0"): -/* - * Generic 32-bit FP conversion operation. - */ - /* unop vA, vB */ - movzbl rINSTbl, %ecx # ecx <- A+ - sarl $$4, rINST # rINST <- B - $load VREG_ADDRESS(rINST) # %st0 <- vB - andb $$0xf, %cl # ecx <- A - $instr - $store VREG_ADDRESS(%ecx) # vA <- %st0 - .if $wide - CLEAR_WIDE_REF %ecx - .else - CLEAR_REF %ecx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/header.S b/runtime/interpreter/mterp/x86/header.S deleted file mode 100644 index f0d14fea19..0000000000 --- a/runtime/interpreter/mterp/x86/header.S +++ /dev/null @@ -1,317 +0,0 @@ -%def header(): -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - Art assembly interpreter notes: - - First validate assembly code by implementing ExecuteXXXImpl() style body (doesn't - handle invoke, allows higher-level code to create frame & shadow frame. - - Once that's working, support direct entry code & eliminate shadow frame (and - excess locals allocation. - - Some (hopefully) temporary ugliness. We'll treat rFP as pointing to the - base of the vreg array within the shadow frame. Access the other fields, - dex_pc_, method_ and number_of_vregs_ via negative offsets. For now, we'll continue - the shadow frame mechanism of double-storing object references - via rFP & - number_of_vregs_. - - */ - -/* -x86 ABI general notes: - -Caller save set: - eax, edx, ecx, st(0)-st(7) -Callee save set: - ebx, esi, edi, ebp -Return regs: - 32-bit in eax - 64-bit in edx:eax (low-order 32 in eax) - fp on top of fp stack st(0) - -Parameters passed on stack, pushed right-to-left. On entry to target, first -parm is at 4(%esp). Traditional entry code is: - -functEntry: - push %ebp # save old frame pointer - mov %ebp,%esp # establish new frame pointer - sub FrameSize,%esp # Allocate storage for spill, locals & outs - -Once past the prologue, arguments are referenced at ((argno + 2)*4)(%ebp) - -Stack must be 16-byte aligned to support SSE in native code. - -If we're not doing variable stack allocation (alloca), the frame pointer can be -eliminated and all arg references adjusted to be esp relative. -*/ - -/* -Mterp and x86 notes: - -Some key interpreter variables will be assigned to registers. - - nick reg purpose - rPC esi interpreted program counter, used for fetching instructions - rFP edi interpreted frame pointer, used for accessing locals and args - rINSTw bx first 16-bit code of current instruction - rINSTbl bl opcode portion of instruction word - rINSTbh bh high byte of inst word, usually contains src/tgt reg names - rIBASE edx base of instruction handler table - rREFS ebp base of object references in shadow frame. - -Notes: - o High order 16 bits of ebx must be zero on entry to handler - o rPC, rFP, rINSTw/rINSTbl valid on handler entry and exit - o eax and ecx are scratch, rINSTw/ebx sometimes scratch - -Macros are provided for common operations. Each macro MUST emit only -one instruction to make instruction-counting easier. They MUST NOT alter -unspecified registers or condition codes. -*/ - -/* - * This is a #include, not a %include, because we want the C pre-processor - * to expand the macros into assembler assignment statements. - */ -#include "asm_support.h" -#include "interpreter/cfi_asm_support.h" - -/* - * Handle mac compiler specific - */ -#if defined(__APPLE__) - #define MACRO_LITERAL(value) $$(value) - #define FUNCTION_TYPE(name) - #define OBJECT_TYPE(name) - #define SIZE(start,end) - // Mac OS' symbols have an _ prefix. - #define SYMBOL(name) _ ## name - #define ASM_HIDDEN .private_extern -#else - #define MACRO_LITERAL(value) $$value - #define FUNCTION_TYPE(name) .type name, @function - #define OBJECT_TYPE(name) .type name, @object - #define SIZE(start,end) .size start, .-end - #define SYMBOL(name) name - #define ASM_HIDDEN .hidden -#endif - -.macro PUSH _reg - pushl \_reg - .cfi_adjust_cfa_offset 4 - .cfi_rel_offset \_reg, 0 -.endm - -.macro POP _reg - popl \_reg - .cfi_adjust_cfa_offset -4 - .cfi_restore \_reg -.endm - -/* - * Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs. So, - * to access other shadow frame fields, we need to use a backwards offset. Define those here. - */ -#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) -#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) -#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) -#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) -#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) -#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) -#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) -#define OFF_FP_DEX_INSTRUCTIONS OFF_FP(SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET) -#define OFF_FP_COUNTDOWN_OFFSET OFF_FP(SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET) -#define OFF_FP_SHADOWFRAME OFF_FP(0) - -/* Frame size must be 16-byte aligned. - * Remember about 4 bytes for return address + 4 * 4 for spills - */ -#define FRAME_SIZE 28 - -/* Frame diagram while executing ExecuteMterpImpl, high to low addresses */ -#define IN_ARG3 (FRAME_SIZE + 16 + 16) -#define IN_ARG2 (FRAME_SIZE + 16 + 12) -#define IN_ARG1 (FRAME_SIZE + 16 + 8) -#define IN_ARG0 (FRAME_SIZE + 16 + 4) -/* Spill offsets relative to %esp */ -#define LOCAL0 (FRAME_SIZE - 4) -#define LOCAL1 (FRAME_SIZE - 8) -#define LOCAL2 (FRAME_SIZE - 12) -/* Out Arg offsets, relative to %esp */ -#define OUT_ARG3 ( 12) -#define OUT_ARG2 ( 8) -#define OUT_ARG1 ( 4) -#define OUT_ARG0 ( 0) /* <- ExecuteMterpImpl esp + 0 */ - -/* During bringup, we'll use the shadow frame model instead of rFP */ -/* single-purpose registers, given names for clarity */ -#define rSELF IN_ARG0(%esp) -#define rPC %esi -#define CFI_DEX 6 // DWARF register number of the register holding dex-pc (esi). -#define CFI_TMP 0 // DWARF register number of the first argument register (eax). -#define rFP %edi -#define rINST %ebx -#define rINSTw %bx -#define rINSTbh %bh -#define rINSTbl %bl -#define rIBASE %edx -#define rREFS %ebp -#define rPROFILE OFF_FP_COUNTDOWN_OFFSET(rFP) - -#define MTERP_LOGGING 0 - -/* - * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must - * be done *before* something throws. - * - * It's okay to do this more than once. - * - * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped - * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction - * offset into the code_items_[] array. For effiency, we will "export" the - * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC - * to convert to a dex pc when needed. - */ -.macro EXPORT_PC - movl rPC, OFF_FP_DEX_PC_PTR(rFP) -.endm - -/* - * Refresh handler table. - */ -.macro REFRESH_IBASE - movl rSELF, rIBASE - movl THREAD_CURRENT_IBASE_OFFSET(rIBASE), rIBASE -.endm - -/* - * Refresh handler table. - * IBase handles uses the caller save register so we must restore it after each call. - * Also it is used as a result of some 64-bit operations (like imul) and we should - * restore it in such cases also. - * - * TODO: Consider spilling the IBase instead of restoring it from Thread structure. - */ -.macro RESTORE_IBASE - movl rSELF, rIBASE - movl THREAD_CURRENT_IBASE_OFFSET(rIBASE), rIBASE -.endm - -/* - * If rSELF is already loaded then we can use it from known reg. - */ -.macro RESTORE_IBASE_FROM_SELF _reg - movl THREAD_CURRENT_IBASE_OFFSET(\_reg), rIBASE -.endm - -/* - * Refresh rINST. - * At enter to handler rINST does not contain the opcode number. - * However some utilities require the full value, so this macro - * restores the opcode number. - */ -.macro REFRESH_INST _opnum - movb rINSTbl, rINSTbh - movb MACRO_LITERAL(\_opnum), rINSTbl -.endm - -/* - * Fetch the next instruction from rPC into rINSTw. Does not advance rPC. - */ -.macro FETCH_INST - movzwl (rPC), rINST -.endm - -/* - * Remove opcode from rINST, compute the address of handler and jump to it. - */ -.macro GOTO_NEXT - movzx rINSTbl,%eax - movzbl rINSTbh,rINST - shll MACRO_LITERAL(${handler_size_bits}), %eax - addl rIBASE, %eax - jmp *%eax -.endm - -/* - * Advance rPC by instruction count. - */ -.macro ADVANCE_PC _count - leal 2*\_count(rPC), rPC -.endm - -/* - * Advance rPC by instruction count, fetch instruction and jump to handler. - */ -.macro ADVANCE_PC_FETCH_AND_GOTO_NEXT _count - ADVANCE_PC \_count - FETCH_INST - GOTO_NEXT -.endm - -/* - * Get/set the 32-bit value from a Dalvik register. - */ -#define VREG_ADDRESS(_vreg) (rFP,_vreg,4) -#define VREG_HIGH_ADDRESS(_vreg) 4(rFP,_vreg,4) -#define VREG_REF_ADDRESS(_vreg) (rREFS,_vreg,4) -#define VREG_REF_HIGH_ADDRESS(_vreg) 4(rREFS,_vreg,4) - -.macro GET_VREG _reg _vreg - movl (rFP,\_vreg,4), \_reg -.endm - -/* Read wide value to xmm. */ -.macro GET_WIDE_FP_VREG _reg _vreg - movq (rFP,\_vreg,4), \_reg -.endm - -.macro SET_VREG _reg _vreg - movl \_reg, (rFP,\_vreg,4) - movl MACRO_LITERAL(0), (rREFS,\_vreg,4) -.endm - -/* Write wide value from xmm. xmm is clobbered. */ -.macro SET_WIDE_FP_VREG _reg _vreg - movq \_reg, (rFP,\_vreg,4) - pxor \_reg, \_reg - movq \_reg, (rREFS,\_vreg,4) -.endm - -.macro SET_VREG_OBJECT _reg _vreg - movl \_reg, (rFP,\_vreg,4) - movl \_reg, (rREFS,\_vreg,4) -.endm - -.macro GET_VREG_HIGH _reg _vreg - movl 4(rFP,\_vreg,4), \_reg -.endm - -.macro SET_VREG_HIGH _reg _vreg - movl \_reg, 4(rFP,\_vreg,4) - movl MACRO_LITERAL(0), 4(rREFS,\_vreg,4) -.endm - -.macro CLEAR_REF _vreg - movl MACRO_LITERAL(0), (rREFS,\_vreg,4) -.endm - -.macro CLEAR_WIDE_REF _vreg - movl MACRO_LITERAL(0), (rREFS,\_vreg,4) - movl MACRO_LITERAL(0), 4(rREFS,\_vreg,4) -.endm diff --git a/runtime/interpreter/mterp/x86/instruction_end.S b/runtime/interpreter/mterp/x86/instruction_end.S deleted file mode 100644 index 5a24b66dec..0000000000 --- a/runtime/interpreter/mterp/x86/instruction_end.S +++ /dev/null @@ -1,6 +0,0 @@ -%def instruction_end(): - - OBJECT_TYPE(artMterpAsmInstructionEnd) - ASM_HIDDEN SYMBOL(artMterpAsmInstructionEnd) - .global SYMBOL(artMterpAsmInstructionEnd) -SYMBOL(artMterpAsmInstructionEnd): diff --git a/runtime/interpreter/mterp/x86/instruction_end_alt.S b/runtime/interpreter/mterp/x86/instruction_end_alt.S deleted file mode 100644 index d037db988c..0000000000 --- a/runtime/interpreter/mterp/x86/instruction_end_alt.S +++ /dev/null @@ -1,6 +0,0 @@ -%def instruction_end_alt(): - - OBJECT_TYPE(artMterpAsmAltInstructionEnd) - ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionEnd) - .global SYMBOL(artMterpAsmAltInstructionEnd) -SYMBOL(artMterpAsmAltInstructionEnd): diff --git a/runtime/interpreter/mterp/x86/instruction_end_sister.S b/runtime/interpreter/mterp/x86/instruction_end_sister.S deleted file mode 100644 index 7b1ec89d60..0000000000 --- a/runtime/interpreter/mterp/x86/instruction_end_sister.S +++ /dev/null @@ -1,6 +0,0 @@ -%def instruction_end_sister(): - - OBJECT_TYPE(artMterpAsmSisterEnd) - ASM_HIDDEN SYMBOL(artMterpAsmSisterEnd) - .global SYMBOL(artMterpAsmSisterEnd) -SYMBOL(artMterpAsmSisterEnd): diff --git a/runtime/interpreter/mterp/x86/instruction_start.S b/runtime/interpreter/mterp/x86/instruction_start.S deleted file mode 100644 index dee581b60f..0000000000 --- a/runtime/interpreter/mterp/x86/instruction_start.S +++ /dev/null @@ -1,7 +0,0 @@ -%def instruction_start(): - - OBJECT_TYPE(artMterpAsmInstructionStart) - ASM_HIDDEN SYMBOL(artMterpAsmInstructionStart) - .global SYMBOL(artMterpAsmInstructionStart) -SYMBOL(artMterpAsmInstructionStart) = .L_op_nop - .text diff --git a/runtime/interpreter/mterp/x86/instruction_start_alt.S b/runtime/interpreter/mterp/x86/instruction_start_alt.S deleted file mode 100644 index 66650e7a6e..0000000000 --- a/runtime/interpreter/mterp/x86/instruction_start_alt.S +++ /dev/null @@ -1,7 +0,0 @@ -%def instruction_start_alt(): - - OBJECT_TYPE(artMterpAsmAltInstructionStart) - ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionStart) - .global SYMBOL(artMterpAsmAltInstructionStart) - .text -SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop diff --git a/runtime/interpreter/mterp/x86/instruction_start_sister.S b/runtime/interpreter/mterp/x86/instruction_start_sister.S deleted file mode 100644 index 8c156adf7e..0000000000 --- a/runtime/interpreter/mterp/x86/instruction_start_sister.S +++ /dev/null @@ -1,8 +0,0 @@ -%def instruction_start_sister(): - - OBJECT_TYPE(artMterpAsmSisterStart) - ASM_HIDDEN SYMBOL(artMterpAsmSisterStart) - .global SYMBOL(artMterpAsmSisterStart) - .text - .balign 4 -SYMBOL(artMterpAsmSisterStart): diff --git a/runtime/interpreter/mterp/x86/invoke.S b/runtime/interpreter/mterp/x86/invoke.S index eb5cdbc786..587c4cfd63 100644 --- a/runtime/interpreter/mterp/x86/invoke.S +++ b/runtime/interpreter/mterp/x86/invoke.S @@ -23,3 +23,99 @@ RESTORE_IBASE FETCH_INST GOTO_NEXT + +%def invoke_polymorphic(helper="UndefinedInvokeHandler"): + /* + * invoke-polymorphic handler wrapper. + */ + /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ + /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ + .extern $helper + EXPORT_PC + movl rSELF, %ecx + movl %ecx, OUT_ARG0(%esp) + leal OFF_FP_SHADOWFRAME(rFP), %eax + movl %eax, OUT_ARG1(%esp) + movl rPC, OUT_ARG2(%esp) + REFRESH_INST ${opnum} + movl rINST, OUT_ARG3(%esp) + call SYMBOL($helper) + testb %al, %al + jz MterpException + ADVANCE_PC 4 + call SYMBOL(MterpShouldSwitchInterpreters) + testb %al, %al + jnz MterpFallback + RESTORE_IBASE + FETCH_INST + GOTO_NEXT + +%def op_invoke_custom(): +% invoke(helper="MterpInvokeCustom") + +%def op_invoke_custom_range(): +% invoke(helper="MterpInvokeCustomRange") + +%def op_invoke_direct(): +% invoke(helper="MterpInvokeDirect") + +%def op_invoke_direct_range(): +% invoke(helper="MterpInvokeDirectRange") + +%def op_invoke_interface(): +% invoke(helper="MterpInvokeInterface") +/* + * Handle an interface method call. + * + * for: invoke-interface, invoke-interface/range + */ + /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ + /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ + +%def op_invoke_interface_range(): +% invoke(helper="MterpInvokeInterfaceRange") + +%def op_invoke_polymorphic(): +% invoke_polymorphic(helper="MterpInvokePolymorphic") + +%def op_invoke_polymorphic_range(): +% invoke_polymorphic(helper="MterpInvokePolymorphicRange") + +%def op_invoke_static(): +% invoke(helper="MterpInvokeStatic") + + +%def op_invoke_static_range(): +% invoke(helper="MterpInvokeStaticRange") + +%def op_invoke_super(): +% invoke(helper="MterpInvokeSuper") +/* + * Handle a "super" method call. + * + * for: invoke-super, invoke-super/range + */ + /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ + /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ + +%def op_invoke_super_range(): +% invoke(helper="MterpInvokeSuperRange") + +%def op_invoke_virtual(): +% invoke(helper="MterpInvokeVirtual") +/* + * Handle a virtual method call. + * + * for: invoke-virtual, invoke-virtual/range + */ + /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ + /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ + +%def op_invoke_virtual_quick(): +% invoke(helper="MterpInvokeVirtualQuick") + +%def op_invoke_virtual_range(): +% invoke(helper="MterpInvokeVirtualRange") + +%def op_invoke_virtual_range_quick(): +% invoke(helper="MterpInvokeVirtualQuickRange") diff --git a/runtime/interpreter/mterp/x86/invoke_polymorphic.S b/runtime/interpreter/mterp/x86/invoke_polymorphic.S deleted file mode 100644 index 63196ec360..0000000000 --- a/runtime/interpreter/mterp/x86/invoke_polymorphic.S +++ /dev/null @@ -1,25 +0,0 @@ -%def invoke_polymorphic(helper="UndefinedInvokeHandler"): - /* - * invoke-polymorphic handler wrapper. - */ - /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ - .extern $helper - EXPORT_PC - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - REFRESH_INST ${opnum} - movl rINST, OUT_ARG3(%esp) - call SYMBOL($helper) - testb %al, %al - jz MterpException - ADVANCE_PC 4 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - RESTORE_IBASE - FETCH_INST - GOTO_NEXT diff --git a/runtime/interpreter/mterp/x86/main.S b/runtime/interpreter/mterp/x86/main.S new file mode 100644 index 0000000000..2dec6b4774 --- /dev/null +++ b/runtime/interpreter/mterp/x86/main.S @@ -0,0 +1,801 @@ +%def header(): +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + Art assembly interpreter notes: + + First validate assembly code by implementing ExecuteXXXImpl() style body (doesn't + handle invoke, allows higher-level code to create frame & shadow frame. + + Once that's working, support direct entry code & eliminate shadow frame (and + excess locals allocation. + + Some (hopefully) temporary ugliness. We'll treat rFP as pointing to the + base of the vreg array within the shadow frame. Access the other fields, + dex_pc_, method_ and number_of_vregs_ via negative offsets. For now, we'll continue + the shadow frame mechanism of double-storing object references - via rFP & + number_of_vregs_. + + */ + +/* +x86 ABI general notes: + +Caller save set: + eax, edx, ecx, st(0)-st(7) +Callee save set: + ebx, esi, edi, ebp +Return regs: + 32-bit in eax + 64-bit in edx:eax (low-order 32 in eax) + fp on top of fp stack st(0) + +Parameters passed on stack, pushed right-to-left. On entry to target, first +parm is at 4(%esp). Traditional entry code is: + +functEntry: + push %ebp # save old frame pointer + mov %ebp,%esp # establish new frame pointer + sub FrameSize,%esp # Allocate storage for spill, locals & outs + +Once past the prologue, arguments are referenced at ((argno + 2)*4)(%ebp) + +Stack must be 16-byte aligned to support SSE in native code. + +If we're not doing variable stack allocation (alloca), the frame pointer can be +eliminated and all arg references adjusted to be esp relative. +*/ + +/* +Mterp and x86 notes: + +Some key interpreter variables will be assigned to registers. + + nick reg purpose + rPC esi interpreted program counter, used for fetching instructions + rFP edi interpreted frame pointer, used for accessing locals and args + rINSTw bx first 16-bit code of current instruction + rINSTbl bl opcode portion of instruction word + rINSTbh bh high byte of inst word, usually contains src/tgt reg names + rIBASE edx base of instruction handler table + rREFS ebp base of object references in shadow frame. + +Notes: + o High order 16 bits of ebx must be zero on entry to handler + o rPC, rFP, rINSTw/rINSTbl valid on handler entry and exit + o eax and ecx are scratch, rINSTw/ebx sometimes scratch + +Macros are provided for common operations. Each macro MUST emit only +one instruction to make instruction-counting easier. They MUST NOT alter +unspecified registers or condition codes. +*/ + +/* + * This is a #include, not a %include, because we want the C pre-processor + * to expand the macros into assembler assignment statements. + */ +#include "asm_support.h" +#include "interpreter/cfi_asm_support.h" + +/* + * Handle mac compiler specific + */ +#if defined(__APPLE__) + #define MACRO_LITERAL(value) $$(value) + #define FUNCTION_TYPE(name) + #define OBJECT_TYPE(name) + #define SIZE(start,end) + // Mac OS' symbols have an _ prefix. + #define SYMBOL(name) _ ## name + #define ASM_HIDDEN .private_extern +#else + #define MACRO_LITERAL(value) $$value + #define FUNCTION_TYPE(name) .type name, @function + #define OBJECT_TYPE(name) .type name, @object + #define SIZE(start,end) .size start, .-end + #define SYMBOL(name) name + #define ASM_HIDDEN .hidden +#endif + +.macro PUSH _reg + pushl \_reg + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset \_reg, 0 +.endm + +.macro POP _reg + popl \_reg + .cfi_adjust_cfa_offset -4 + .cfi_restore \_reg +.endm + +/* + * Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs. So, + * to access other shadow frame fields, we need to use a backwards offset. Define those here. + */ +#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) +#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) +#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) +#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) +#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) +#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) +#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) +#define OFF_FP_DEX_INSTRUCTIONS OFF_FP(SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET) +#define OFF_FP_COUNTDOWN_OFFSET OFF_FP(SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET) +#define OFF_FP_SHADOWFRAME OFF_FP(0) + +/* Frame size must be 16-byte aligned. + * Remember about 4 bytes for return address + 4 * 4 for spills + */ +#define FRAME_SIZE 28 + +/* Frame diagram while executing ExecuteMterpImpl, high to low addresses */ +#define IN_ARG3 (FRAME_SIZE + 16 + 16) +#define IN_ARG2 (FRAME_SIZE + 16 + 12) +#define IN_ARG1 (FRAME_SIZE + 16 + 8) +#define IN_ARG0 (FRAME_SIZE + 16 + 4) +/* Spill offsets relative to %esp */ +#define LOCAL0 (FRAME_SIZE - 4) +#define LOCAL1 (FRAME_SIZE - 8) +#define LOCAL2 (FRAME_SIZE - 12) +/* Out Arg offsets, relative to %esp */ +#define OUT_ARG3 ( 12) +#define OUT_ARG2 ( 8) +#define OUT_ARG1 ( 4) +#define OUT_ARG0 ( 0) /* <- ExecuteMterpImpl esp + 0 */ + +/* During bringup, we'll use the shadow frame model instead of rFP */ +/* single-purpose registers, given names for clarity */ +#define rSELF IN_ARG0(%esp) +#define rPC %esi +#define CFI_DEX 6 // DWARF register number of the register holding dex-pc (esi). +#define CFI_TMP 0 // DWARF register number of the first argument register (eax). +#define rFP %edi +#define rINST %ebx +#define rINSTw %bx +#define rINSTbh %bh +#define rINSTbl %bl +#define rIBASE %edx +#define rREFS %ebp +#define rPROFILE OFF_FP_COUNTDOWN_OFFSET(rFP) + +#define MTERP_LOGGING 0 + +/* + * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must + * be done *before* something throws. + * + * It's okay to do this more than once. + * + * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped + * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction + * offset into the code_items_[] array. For effiency, we will "export" the + * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC + * to convert to a dex pc when needed. + */ +.macro EXPORT_PC + movl rPC, OFF_FP_DEX_PC_PTR(rFP) +.endm + +/* + * Refresh handler table. + */ +.macro REFRESH_IBASE + movl rSELF, rIBASE + movl THREAD_CURRENT_IBASE_OFFSET(rIBASE), rIBASE +.endm + +/* + * Refresh handler table. + * IBase handles uses the caller save register so we must restore it after each call. + * Also it is used as a result of some 64-bit operations (like imul) and we should + * restore it in such cases also. + * + * TODO: Consider spilling the IBase instead of restoring it from Thread structure. + */ +.macro RESTORE_IBASE + movl rSELF, rIBASE + movl THREAD_CURRENT_IBASE_OFFSET(rIBASE), rIBASE +.endm + +/* + * If rSELF is already loaded then we can use it from known reg. + */ +.macro RESTORE_IBASE_FROM_SELF _reg + movl THREAD_CURRENT_IBASE_OFFSET(\_reg), rIBASE +.endm + +/* + * Refresh rINST. + * At enter to handler rINST does not contain the opcode number. + * However some utilities require the full value, so this macro + * restores the opcode number. + */ +.macro REFRESH_INST _opnum + movb rINSTbl, rINSTbh + movb MACRO_LITERAL(\_opnum), rINSTbl +.endm + +/* + * Fetch the next instruction from rPC into rINSTw. Does not advance rPC. + */ +.macro FETCH_INST + movzwl (rPC), rINST +.endm + +/* + * Remove opcode from rINST, compute the address of handler and jump to it. + */ +.macro GOTO_NEXT + movzx rINSTbl,%eax + movzbl rINSTbh,rINST + shll MACRO_LITERAL(${handler_size_bits}), %eax + addl rIBASE, %eax + jmp *%eax +.endm + +/* + * Advance rPC by instruction count. + */ +.macro ADVANCE_PC _count + leal 2*\_count(rPC), rPC +.endm + +/* + * Advance rPC by instruction count, fetch instruction and jump to handler. + */ +.macro ADVANCE_PC_FETCH_AND_GOTO_NEXT _count + ADVANCE_PC \_count + FETCH_INST + GOTO_NEXT +.endm + +/* + * Get/set the 32-bit value from a Dalvik register. + */ +#define VREG_ADDRESS(_vreg) (rFP,_vreg,4) +#define VREG_HIGH_ADDRESS(_vreg) 4(rFP,_vreg,4) +#define VREG_REF_ADDRESS(_vreg) (rREFS,_vreg,4) +#define VREG_REF_HIGH_ADDRESS(_vreg) 4(rREFS,_vreg,4) + +.macro GET_VREG _reg _vreg + movl (rFP,\_vreg,4), \_reg +.endm + +/* Read wide value to xmm. */ +.macro GET_WIDE_FP_VREG _reg _vreg + movq (rFP,\_vreg,4), \_reg +.endm + +.macro SET_VREG _reg _vreg + movl \_reg, (rFP,\_vreg,4) + movl MACRO_LITERAL(0), (rREFS,\_vreg,4) +.endm + +/* Write wide value from xmm. xmm is clobbered. */ +.macro SET_WIDE_FP_VREG _reg _vreg + movq \_reg, (rFP,\_vreg,4) + pxor \_reg, \_reg + movq \_reg, (rREFS,\_vreg,4) +.endm + +.macro SET_VREG_OBJECT _reg _vreg + movl \_reg, (rFP,\_vreg,4) + movl \_reg, (rREFS,\_vreg,4) +.endm + +.macro GET_VREG_HIGH _reg _vreg + movl 4(rFP,\_vreg,4), \_reg +.endm + +.macro SET_VREG_HIGH _reg _vreg + movl \_reg, 4(rFP,\_vreg,4) + movl MACRO_LITERAL(0), 4(rREFS,\_vreg,4) +.endm + +.macro CLEAR_REF _vreg + movl MACRO_LITERAL(0), (rREFS,\_vreg,4) +.endm + +.macro CLEAR_WIDE_REF _vreg + movl MACRO_LITERAL(0), (rREFS,\_vreg,4) + movl MACRO_LITERAL(0), 4(rREFS,\_vreg,4) +.endm + +%def entry(): +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* + * Interpreter entry point. + */ + + .text + ASM_HIDDEN SYMBOL(ExecuteMterpImpl) + .global SYMBOL(ExecuteMterpImpl) + FUNCTION_TYPE(ExecuteMterpImpl) + +/* + * On entry: + * 0 Thread* self + * 1 insns_ + * 2 ShadowFrame + * 3 JValue* result_register + * + */ + +SYMBOL(ExecuteMterpImpl): + .cfi_startproc + .cfi_def_cfa esp, 4 + + /* Spill callee save regs */ + PUSH %ebp + PUSH %edi + PUSH %esi + PUSH %ebx + + /* Allocate frame */ + subl $$FRAME_SIZE, %esp + .cfi_adjust_cfa_offset FRAME_SIZE + + /* Load ShadowFrame pointer */ + movl IN_ARG2(%esp), %edx + + /* Remember the return register */ + movl IN_ARG3(%esp), %eax + movl %eax, SHADOWFRAME_RESULT_REGISTER_OFFSET(%edx) + + /* Remember the code_item */ + movl IN_ARG1(%esp), %ecx + movl %ecx, SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET(%edx) + + /* set up "named" registers */ + movl SHADOWFRAME_NUMBER_OF_VREGS_OFFSET(%edx), %eax + leal SHADOWFRAME_VREGS_OFFSET(%edx), rFP + leal (rFP, %eax, 4), rREFS + movl SHADOWFRAME_DEX_PC_OFFSET(%edx), %eax + lea (%ecx, %eax, 2), rPC + CFI_DEFINE_DEX_PC_WITH_OFFSET(CFI_TMP, CFI_DEX, 0) + EXPORT_PC + + /* Set up for backwards branches & osr profiling */ + movl OFF_FP_METHOD(rFP), %eax + movl %eax, OUT_ARG0(%esp) + leal OFF_FP_SHADOWFRAME(rFP), %ecx + movl %ecx, OUT_ARG1(%esp) + movl rSELF, %eax + movl %eax, OUT_ARG2(%esp) + call SYMBOL(MterpSetUpHotnessCountdown) + + /* Starting ibase */ + REFRESH_IBASE + + /* start executing the instruction at rPC */ + FETCH_INST + GOTO_NEXT + /* NOTE: no fallthrough */ + +%def alt_stub(): +/* + * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle + * any interesting requests and then jump to the real instruction + * handler. Unlike the Arm handler, we can't do this as a tail call + * because rIBASE is caller save and we need to reload it. + * + * Note that unlike in the Arm implementation, we should never arrive + * here with a zero breakFlag because we always refresh rIBASE on + * return. + */ + .extern MterpCheckBefore + movl rSELF, %ecx + movl %ecx, OUT_ARG0(%esp) + leal OFF_FP_SHADOWFRAME(rFP), %eax + movl %eax, OUT_ARG1(%esp) + movl rPC, OUT_ARG2(%esp) + call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) + REFRESH_IBASE + jmp .L_op_nop+(${opnum}*${handler_size_bytes}) + +%def fallback(): +/* Transfer stub to alternate interpreter */ + jmp MterpFallback + + +%def footer(): +/* + * =========================================================================== + * Common subroutines and data + * =========================================================================== + */ + + .text + .align 2 + +/* + * We've detected a condition that will result in an exception, but the exception + * has not yet been thrown. Just bail out to the reference interpreter to deal with it. + * TUNING: for consistency, we may want to just go ahead and handle these here. + */ +common_errDivideByZero: + EXPORT_PC +#if MTERP_LOGGING + movl rSELF, %eax + movl %eax, OUT_ARG0(%esp) + lea OFF_FP_SHADOWFRAME(rFP), %ecx + movl %ecx, OUT_ARG1(%esp) + call SYMBOL(MterpLogDivideByZeroException) +#endif + jmp MterpCommonFallback + +common_errArrayIndex: + EXPORT_PC +#if MTERP_LOGGING + movl rSELF, %eax + movl %eax, OUT_ARG0(%esp) + lea OFF_FP_SHADOWFRAME(rFP), %ecx + movl %ecx, OUT_ARG1(%esp) + call SYMBOL(MterpLogArrayIndexException) +#endif + jmp MterpCommonFallback + +common_errNegativeArraySize: + EXPORT_PC +#if MTERP_LOGGING + movl rSELF, %eax + movl %eax, OUT_ARG0(%esp) + lea OFF_FP_SHADOWFRAME(rFP), %ecx + movl %ecx, OUT_ARG1(%esp) + call SYMBOL(MterpLogNegativeArraySizeException) +#endif + jmp MterpCommonFallback + +common_errNoSuchMethod: + EXPORT_PC +#if MTERP_LOGGING + movl rSELF, %eax + movl %eax, OUT_ARG0(%esp) + lea OFF_FP_SHADOWFRAME(rFP), %ecx + movl %ecx, OUT_ARG1(%esp) + call SYMBOL(MterpLogNoSuchMethodException) +#endif + jmp MterpCommonFallback + +common_errNullObject: + EXPORT_PC +#if MTERP_LOGGING + movl rSELF, %eax + movl %eax, OUT_ARG0(%esp) + lea OFF_FP_SHADOWFRAME(rFP), %ecx + movl %ecx, OUT_ARG1(%esp) + call SYMBOL(MterpLogNullObjectException) +#endif + jmp MterpCommonFallback + +common_exceptionThrown: + EXPORT_PC +#if MTERP_LOGGING + movl rSELF, %eax + movl %eax, OUT_ARG0(%esp) + lea OFF_FP_SHADOWFRAME(rFP), %ecx + movl %ecx, OUT_ARG0(%esp) + call SYMBOL(MterpLogExceptionThrownException) +#endif + jmp MterpCommonFallback + +MterpSuspendFallback: + EXPORT_PC +#if MTERP_LOGGING + movl rSELF, %eax + movl %eax, OUT_ARG0(%esp) + lea OFF_FP_SHADOWFRAME(rFP), %ecx + movl %ecx, OUT_ARG0(%esp) + movl THREAD_FLAGS_OFFSET(%eax), %eax + movl %eax, OUT_ARG2(%esp) + call SYMBOL(MterpLogSuspendFallback) +#endif + jmp MterpCommonFallback + +/* + * If we're here, something is out of the ordinary. If there is a pending + * exception, handle it. Otherwise, roll back and retry with the reference + * interpreter. + */ +MterpPossibleException: + movl rSELF, %eax + testl $$-1, THREAD_EXCEPTION_OFFSET(%eax) + jz MterpFallback + /* intentional fallthrough - handle pending exception. */ + +/* + * On return from a runtime helper routine, we've found a pending exception. + * Can we handle it here - or need to bail out to caller? + * + */ +MterpException: + movl rSELF, %eax + movl %eax, OUT_ARG0(%esp) + lea OFF_FP_SHADOWFRAME(rFP), %ecx + movl %ecx, OUT_ARG1(%esp) + call SYMBOL(MterpHandleException) + testb %al, %al + jz MterpExceptionReturn + movl OFF_FP_DEX_INSTRUCTIONS(rFP), %eax + movl OFF_FP_DEX_PC(rFP), %ecx + lea (%eax, %ecx, 2), rPC + movl rPC, OFF_FP_DEX_PC_PTR(rFP) + /* Do we need to switch interpreters? */ + call SYMBOL(MterpShouldSwitchInterpreters) + testb %al, %al + jnz MterpFallback + /* resume execution at catch block */ + REFRESH_IBASE + FETCH_INST + GOTO_NEXT + /* NOTE: no fallthrough */ + +/* + * Common handling for branches with support for Jit profiling. + * On entry: + * rINST <= signed offset + * condition bits <= set to establish sign of offset (use "NoFlags" entry if not) + * + * We have quite a few different cases for branch profiling, OSR detection and + * suspend check support here. + * + * Taken backward branches: + * If profiling active, do hotness countdown and report if we hit zero. + * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. + * Is there a pending suspend request? If so, suspend. + * + * Taken forward branches and not-taken backward branches: + * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. + * + * Our most common case is expected to be a taken backward branch with active jit profiling, + * but no full OSR check and no pending suspend request. + * Next most common case is not-taken branch with no full OSR check. + * + */ +MterpCommonTakenBranch: + jg .L_forward_branch # don't add forward branches to hotness +/* + * We need to subtract 1 from positive values and we should not see 0 here, + * so we may use the result of the comparison with -1. + */ +#if JIT_CHECK_OSR != -1 +# error "JIT_CHECK_OSR must be -1." +#endif + cmpw $$JIT_CHECK_OSR, rPROFILE + je .L_osr_check + decw rPROFILE + je .L_add_batch # counted down to zero - report +.L_resume_backward_branch: + movl rSELF, %eax + testl $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(%eax) + leal (rPC, rINST, 2), rPC + FETCH_INST + jnz .L_suspend_request_pending + REFRESH_IBASE + GOTO_NEXT + +.L_suspend_request_pending: + EXPORT_PC + movl %eax, OUT_ARG0(%esp) # rSELF in eax + call SYMBOL(MterpSuspendCheck) # (self) + testb %al, %al + jnz MterpFallback + REFRESH_IBASE # might have changed during suspend + GOTO_NEXT + +.L_no_count_backwards: + cmpw $$JIT_CHECK_OSR, rPROFILE # possible OSR re-entry? + jne .L_resume_backward_branch +.L_osr_check: + EXPORT_PC + movl rSELF, %eax + movl %eax, OUT_ARG0(%esp) + leal OFF_FP_SHADOWFRAME(rFP), %ecx + movl %ecx, OUT_ARG1(%esp) + movl rINST, OUT_ARG2(%esp) + call SYMBOL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) + testb %al, %al + jz .L_resume_backward_branch + jmp MterpOnStackReplacement + +.L_forward_branch: + cmpw $$JIT_CHECK_OSR, rPROFILE # possible OSR re-entry? + je .L_check_osr_forward +.L_resume_forward_branch: + leal (rPC, rINST, 2), rPC + FETCH_INST + GOTO_NEXT + +.L_check_osr_forward: + EXPORT_PC + movl rSELF, %eax + movl %eax, OUT_ARG0(%esp) + leal OFF_FP_SHADOWFRAME(rFP), %ecx + movl %ecx, OUT_ARG1(%esp) + movl rINST, OUT_ARG2(%esp) + call SYMBOL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) + testb %al, %al + REFRESH_IBASE + jz .L_resume_forward_branch + jmp MterpOnStackReplacement + +.L_add_batch: + movl OFF_FP_METHOD(rFP), %eax + movl %eax, OUT_ARG0(%esp) + leal OFF_FP_SHADOWFRAME(rFP), %ecx + movl %ecx, OUT_ARG1(%esp) + movl rSELF, %eax + movl %eax, OUT_ARG2(%esp) + call SYMBOL(MterpAddHotnessBatch) # (method, shadow_frame, self) + jmp .L_no_count_backwards + +/* + * Entered from the conditional branch handlers when OSR check request active on + * not-taken path. All Dalvik not-taken conditional branch offsets are 2. + */ +.L_check_not_taken_osr: + EXPORT_PC + movl rSELF, %eax + movl %eax, OUT_ARG0(%esp) + leal OFF_FP_SHADOWFRAME(rFP), %ecx + movl %ecx, OUT_ARG1(%esp) + movl $$2, OUT_ARG2(%esp) + call SYMBOL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) + testb %al, %al + REFRESH_IBASE + jnz MterpOnStackReplacement + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +/* + * On-stack replacement has happened, and now we've returned from the compiled method. + */ +MterpOnStackReplacement: +#if MTERP_LOGGING + movl rSELF, %eax + movl %eax, OUT_ARG0(%esp) + lea OFF_FP_SHADOWFRAME(rFP), %ecx + movl %ecx, OUT_ARG1(%esp) + movl rINST, OUT_ARG2(%esp) + call SYMBOL(MterpLogOSR) +#endif + movl $$1, %eax + jmp MterpDone + +/* + * Bail out to reference interpreter. + */ +MterpFallback: + EXPORT_PC +#if MTERP_LOGGING + movl rSELF, %eax + movl %eax, OUT_ARG0(%esp) + lea OFF_FP_SHADOWFRAME(rFP), %ecx + movl %ecx, OUT_ARG1(%esp) + call SYMBOL(MterpLogFallback) +#endif +MterpCommonFallback: + xor %eax, %eax + jmp MterpDone + +/* + * On entry: + * uint32_t* rFP (should still be live, pointer to base of vregs) + */ +MterpExceptionReturn: + movl $$1, %eax + jmp MterpDone +MterpReturn: + movl OFF_FP_RESULT_REGISTER(rFP), %edx + movl %eax, (%edx) + movl %ecx, 4(%edx) + mov $$1, %eax +MterpDone: +/* + * At this point, we expect rPROFILE to be non-zero. If negative, hotness is disabled or we're + * checking for OSR. If greater than zero, we might have unreported hotness to register + * (the difference between the ending rPROFILE and the cached hotness counter). rPROFILE + * should only reach zero immediately after a hotness decrement, and is then reset to either + * a negative special state or the new non-zero countdown value. + */ + cmpw $$0, rPROFILE + jle MRestoreFrame # if > 0, we may have some counts to report. + + movl %eax, rINST # stash return value + /* Report cached hotness counts */ + movl OFF_FP_METHOD(rFP), %eax + movl %eax, OUT_ARG0(%esp) + leal OFF_FP_SHADOWFRAME(rFP), %ecx + movl %ecx, OUT_ARG1(%esp) + movl rSELF, %eax + movl %eax, OUT_ARG2(%esp) + call SYMBOL(MterpAddHotnessBatch) # (method, shadow_frame, self) + movl rINST, %eax # restore return value + + /* pop up frame */ +MRestoreFrame: + addl $$FRAME_SIZE, %esp + .cfi_adjust_cfa_offset -FRAME_SIZE + + /* Restore callee save register */ + POP %ebx + POP %esi + POP %edi + POP %ebp + ret + .cfi_endproc + SIZE(ExecuteMterpImpl,ExecuteMterpImpl) + +%def instruction_end(): + + OBJECT_TYPE(artMterpAsmInstructionEnd) + ASM_HIDDEN SYMBOL(artMterpAsmInstructionEnd) + .global SYMBOL(artMterpAsmInstructionEnd) +SYMBOL(artMterpAsmInstructionEnd): + +%def instruction_end_alt(): + + OBJECT_TYPE(artMterpAsmAltInstructionEnd) + ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionEnd) + .global SYMBOL(artMterpAsmAltInstructionEnd) +SYMBOL(artMterpAsmAltInstructionEnd): + +%def instruction_end_sister(): + + OBJECT_TYPE(artMterpAsmSisterEnd) + ASM_HIDDEN SYMBOL(artMterpAsmSisterEnd) + .global SYMBOL(artMterpAsmSisterEnd) +SYMBOL(artMterpAsmSisterEnd): + +%def instruction_start(): + + OBJECT_TYPE(artMterpAsmInstructionStart) + ASM_HIDDEN SYMBOL(artMterpAsmInstructionStart) + .global SYMBOL(artMterpAsmInstructionStart) +SYMBOL(artMterpAsmInstructionStart) = .L_op_nop + .text + +%def instruction_start_alt(): + + OBJECT_TYPE(artMterpAsmAltInstructionStart) + ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionStart) + .global SYMBOL(artMterpAsmAltInstructionStart) + .text +SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop + +%def instruction_start_sister(): + + OBJECT_TYPE(artMterpAsmSisterStart) + ASM_HIDDEN SYMBOL(artMterpAsmSisterStart) + .global SYMBOL(artMterpAsmSisterStart) + .text + .balign 4 +SYMBOL(artMterpAsmSisterStart): diff --git a/runtime/interpreter/mterp/x86/object.S b/runtime/interpreter/mterp/x86/object.S new file mode 100644 index 0000000000..a47fa3a930 --- /dev/null +++ b/runtime/interpreter/mterp/x86/object.S @@ -0,0 +1,278 @@ +%def field(helper=""): + /* + * General field read / write (iget-* iput-* sget-* sput-*). + */ + .extern $helper + REFRESH_INST ${opnum} # fix rINST to include opcode + movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst + movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data + leal OFF_FP_SHADOWFRAME(rFP), %eax + movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf + movl rSELF, %eax + movl %eax, OUT_ARG3(%esp) # arg3: Thread* self + call SYMBOL($helper) + testb %al, %al + jz MterpPossibleException + RESTORE_IBASE + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_check_cast(): +/* + * Check to see if a cast from one class to another is allowed. + */ + /* check-cast vAA, class@BBBB */ + EXPORT_PC + movzwl 2(rPC), %eax # eax <- BBBB + movl %eax, OUT_ARG0(%esp) + leal VREG_ADDRESS(rINST), %ecx + movl %ecx, OUT_ARG1(%esp) + movl OFF_FP_METHOD(rFP),%eax + movl %eax, OUT_ARG2(%esp) + movl rSELF, %ecx + movl %ecx, OUT_ARG3(%esp) + call SYMBOL(MterpCheckCast) # (index, &obj, method, self) + RESTORE_IBASE + testb %al, %al + jnz MterpPossibleException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_iget(is_object="0", helper="MterpIGetU32"): +% field(helper=helper) + +%def op_iget_boolean(): +% op_iget(helper="MterpIGetU8") + +%def op_iget_boolean_quick(): +% op_iget_quick(load="movsbl") + +%def op_iget_byte(): +% op_iget(helper="MterpIGetI8") + +%def op_iget_byte_quick(): +% op_iget_quick(load="movsbl") + +%def op_iget_char(): +% op_iget(helper="MterpIGetU16") + +%def op_iget_char_quick(): +% op_iget_quick(load="movzwl") + +%def op_iget_object(): +% op_iget(is_object="1", helper="MterpIGetObj") + +%def op_iget_object_quick(): + /* For: iget-object-quick */ + /* op vA, vB, offset@CCCC */ + movzbl rINSTbl, %ecx # ecx <- BA + sarl $$4, %ecx # ecx <- B + GET_VREG %ecx, %ecx # vB (object we're operating on) + movzwl 2(rPC), %eax # eax <- field byte offset + movl %ecx, OUT_ARG0(%esp) + movl %eax, OUT_ARG1(%esp) + EXPORT_PC + call SYMBOL(artIGetObjectFromMterp) # (obj, offset) + movl rSELF, %ecx + RESTORE_IBASE_FROM_SELF %ecx + cmpl $$0, THREAD_EXCEPTION_OFFSET(%ecx) + jnz MterpException # bail out + andb $$0xf,rINSTbl # rINST <- A + SET_VREG_OBJECT %eax, rINST # fp[A] <- value + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_iget_quick(load="movl"): + /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ + /* op vA, vB, offset@CCCC */ + movzbl rINSTbl, %ecx # ecx <- BA + sarl $$4, %ecx # ecx <- B + GET_VREG %ecx, %ecx # vB (object we're operating on) + movzwl 2(rPC), %eax # eax <- field byte offset + testl %ecx, %ecx # is object null? + je common_errNullObject + ${load} (%ecx,%eax,1), %eax + andb $$0xf,rINSTbl # rINST <- A + SET_VREG %eax, rINST # fp[A] <- value + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_iget_short(): +% op_iget(helper="MterpIGetI16") + +%def op_iget_short_quick(): +% op_iget_quick(load="movswl") + +%def op_iget_wide(): +% op_iget(helper="MterpIGetU64") + +%def op_iget_wide_quick(): + /* iget-wide-quick vA, vB, offset@CCCC */ + movzbl rINSTbl, %ecx # ecx <- BA + sarl $$4, %ecx # ecx <- B + GET_VREG %ecx, %ecx # vB (object we're operating on) + movzwl 2(rPC), %eax # eax <- field byte offset + testl %ecx, %ecx # is object null? + je common_errNullObject + movq (%ecx,%eax,1), %xmm0 + andb $$0xf, rINSTbl # rINST <- A + SET_WIDE_FP_VREG %xmm0, rINST + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_instance_of(): +/* + * Check to see if an object reference is an instance of a class. + * + * Most common situation is a non-null object, being compared against + * an already-resolved class. + */ + /* instance-of vA, vB, class@CCCC */ + EXPORT_PC + movzwl 2(rPC), %eax # eax <- BBBB + movl %eax, OUT_ARG0(%esp) + movl rINST, %eax # eax <- BA + sarl $$4, %eax # eax <- B + leal VREG_ADDRESS(%eax), %ecx # Get object address + movl %ecx, OUT_ARG1(%esp) + movl OFF_FP_METHOD(rFP),%eax + movl %eax, OUT_ARG2(%esp) + movl rSELF, %ecx + movl %ecx, OUT_ARG3(%esp) + call SYMBOL(MterpInstanceOf) # (index, &obj, method, self) + movl rSELF, %ecx + RESTORE_IBASE_FROM_SELF %ecx + cmpl $$0, THREAD_EXCEPTION_OFFSET(%ecx) + jnz MterpException + andb $$0xf, rINSTbl # rINSTbl <- A + SET_VREG %eax, rINST + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_iput(is_object="0", helper="MterpIPutU32"): +% field(helper=helper) + +%def op_iput_boolean(): +% op_iput(helper="MterpIPutU8") + +%def op_iput_boolean_quick(): +% op_iput_quick(reg="rINSTbl", store="movb") + +%def op_iput_byte(): +% op_iput(helper="MterpIPutI8") + +%def op_iput_byte_quick(): +% op_iput_quick(reg="rINSTbl", store="movb") + +%def op_iput_char(): +% op_iput(helper="MterpIPutU16") + +%def op_iput_char_quick(): +% op_iput_quick(reg="rINSTw", store="movw") + +%def op_iput_object(): +% op_iput(is_object="1", helper="MterpIPutObj") + +%def op_iput_object_quick(): + EXPORT_PC + leal OFF_FP_SHADOWFRAME(rFP), %eax + movl %eax, OUT_ARG0(%esp) + movl rPC, OUT_ARG1(%esp) + REFRESH_INST ${opnum} + movl rINST, OUT_ARG2(%esp) + call SYMBOL(MterpIputObjectQuick) + testb %al, %al + jz MterpException + RESTORE_IBASE + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_iput_quick(reg="rINST", store="movl"): + /* For: iput-quick, iput-object-quick */ + /* op vA, vB, offset@CCCC */ + movzbl rINSTbl, %ecx # ecx <- BA + sarl $$4, %ecx # ecx <- B + GET_VREG %ecx, %ecx # vB (object we're operating on) + testl %ecx, %ecx # is object null? + je common_errNullObject + andb $$0xf, rINSTbl # rINST <- A + GET_VREG rINST, rINST # rINST <- v[A] + movzwl 2(rPC), %eax # eax <- field byte offset + ${store} ${reg}, (%ecx,%eax,1) + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_iput_short(): +% op_iput(helper="MterpIPutI16") + +%def op_iput_short_quick(): +% op_iput_quick(reg="rINSTw", store="movw") + +%def op_iput_wide(): +% op_iput(helper="MterpIPutU64") + +%def op_iput_wide_quick(): + /* iput-wide-quick vA, vB, offset@CCCC */ + movzbl rINSTbl, %ecx # ecx<- BA + sarl $$4, %ecx # ecx<- B + GET_VREG %ecx, %ecx # vB (object we're operating on) + testl %ecx, %ecx # is object null? + je common_errNullObject + movzwl 2(rPC), %eax # eax<- field byte offset + leal (%ecx,%eax,1), %ecx # ecx<- Address of 64-bit target + andb $$0xf, rINSTbl # rINST<- A + GET_WIDE_FP_VREG %xmm0, rINST # xmm0<- fp[A]/fp[A+1] + movq %xmm0, (%ecx) # obj.field<- r0/r1 + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_new_instance(): +/* + * Create a new instance of a class. + */ + /* new-instance vAA, class@BBBB */ + EXPORT_PC + leal OFF_FP_SHADOWFRAME(rFP), %eax + movl %eax, OUT_ARG0(%esp) + movl rSELF, %ecx + movl %ecx, OUT_ARG1(%esp) + REFRESH_INST ${opnum} + movl rINST, OUT_ARG2(%esp) + call SYMBOL(MterpNewInstance) + RESTORE_IBASE + testb %al, %al # 0 means an exception is thrown + jz MterpPossibleException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_sget(is_object="0", helper="MterpSGetU32"): +% field(helper=helper) + +%def op_sget_boolean(): +% op_sget(helper="MterpSGetU8") + +%def op_sget_byte(): +% op_sget(helper="MterpSGetI8") + +%def op_sget_char(): +% op_sget(helper="MterpSGetU16") + +%def op_sget_object(): +% op_sget(is_object="1", helper="MterpSGetObj") + +%def op_sget_short(): +% op_sget(helper="MterpSGetI16") + +%def op_sget_wide(): +% op_sget(helper="MterpSGetU64") + +%def op_sput(is_object="0", helper="MterpSPutU32"): +% field(helper=helper) + +%def op_sput_boolean(): +% op_sput(helper="MterpSPutU8") + +%def op_sput_byte(): +% op_sput(helper="MterpSPutI8") + +%def op_sput_char(): +% op_sput(helper="MterpSPutU16") + +%def op_sput_object(): +% op_sput(is_object="1", helper="MterpSPutObj") + +%def op_sput_short(): +% op_sput(helper="MterpSPutI16") + +%def op_sput_wide(): +% op_sput(helper="MterpSPutU64") diff --git a/runtime/interpreter/mterp/x86/op_add_double.S b/runtime/interpreter/mterp/x86/op_add_double.S deleted file mode 100644 index a00923928b..0000000000 --- a/runtime/interpreter/mterp/x86/op_add_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_double(): -% sseBinop(instr="adds", suff="d") diff --git a/runtime/interpreter/mterp/x86/op_add_double_2addr.S b/runtime/interpreter/mterp/x86/op_add_double_2addr.S deleted file mode 100644 index 8cb45a9a20..0000000000 --- a/runtime/interpreter/mterp/x86/op_add_double_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_double_2addr(): -% sseBinop2Addr(instr="adds", suff="d") diff --git a/runtime/interpreter/mterp/x86/op_add_float.S b/runtime/interpreter/mterp/x86/op_add_float.S deleted file mode 100644 index dee28c7b8b..0000000000 --- a/runtime/interpreter/mterp/x86/op_add_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_float(): -% sseBinop(instr="adds", suff="s") diff --git a/runtime/interpreter/mterp/x86/op_add_float_2addr.S b/runtime/interpreter/mterp/x86/op_add_float_2addr.S deleted file mode 100644 index 4deb4451ce..0000000000 --- a/runtime/interpreter/mterp/x86/op_add_float_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_float_2addr(): -% sseBinop2Addr(instr="adds", suff="s") diff --git a/runtime/interpreter/mterp/x86/op_add_int.S b/runtime/interpreter/mterp/x86/op_add_int.S deleted file mode 100644 index 9c4455ab64..0000000000 --- a/runtime/interpreter/mterp/x86/op_add_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_int(): -% binop(instr="addl (rFP,%ecx,4), %eax") diff --git a/runtime/interpreter/mterp/x86/op_add_int_2addr.S b/runtime/interpreter/mterp/x86/op_add_int_2addr.S deleted file mode 100644 index b04ae4c57f..0000000000 --- a/runtime/interpreter/mterp/x86/op_add_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_int_2addr(): -% binop2addr(instr="addl %eax, (rFP,%ecx,4)") diff --git a/runtime/interpreter/mterp/x86/op_add_int_lit16.S b/runtime/interpreter/mterp/x86/op_add_int_lit16.S deleted file mode 100644 index a43103019e..0000000000 --- a/runtime/interpreter/mterp/x86/op_add_int_lit16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_int_lit16(): -% binopLit16(instr="addl %ecx, %eax") diff --git a/runtime/interpreter/mterp/x86/op_add_int_lit8.S b/runtime/interpreter/mterp/x86/op_add_int_lit8.S deleted file mode 100644 index 3205aee0cb..0000000000 --- a/runtime/interpreter/mterp/x86/op_add_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_int_lit8(): -% binopLit8(instr="addl %ecx, %eax") diff --git a/runtime/interpreter/mterp/x86/op_add_long.S b/runtime/interpreter/mterp/x86/op_add_long.S deleted file mode 100644 index 24a922601f..0000000000 --- a/runtime/interpreter/mterp/x86/op_add_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_long(): -% binopWide(instr1="addl (rFP,%ecx,4), rIBASE", instr2="adcl 4(rFP,%ecx,4), %eax") diff --git a/runtime/interpreter/mterp/x86/op_add_long_2addr.S b/runtime/interpreter/mterp/x86/op_add_long_2addr.S deleted file mode 100644 index e020714a74..0000000000 --- a/runtime/interpreter/mterp/x86/op_add_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_long_2addr(): -% binopWide2addr(instr1="addl %eax, (rFP,rINST,4)", instr2="adcl %ecx, 4(rFP,rINST,4)") diff --git a/runtime/interpreter/mterp/x86/op_aget.S b/runtime/interpreter/mterp/x86/op_aget.S deleted file mode 100644 index fc57a91146..0000000000 --- a/runtime/interpreter/mterp/x86/op_aget.S +++ /dev/null @@ -1,19 +0,0 @@ -%def op_aget(load="movl", shift="4", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"): -/* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - */ - /* op vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB (array object) - GET_VREG %ecx, %ecx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - $load $data_offset(%eax,%ecx,$shift), %eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_aget_boolean.S b/runtime/interpreter/mterp/x86/op_aget_boolean.S deleted file mode 100644 index 279e6fc739..0000000000 --- a/runtime/interpreter/mterp/x86/op_aget_boolean.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aget_boolean(): -% op_aget(load="movzbl", shift="1", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/x86/op_aget_byte.S b/runtime/interpreter/mterp/x86/op_aget_byte.S deleted file mode 100644 index 1989450743..0000000000 --- a/runtime/interpreter/mterp/x86/op_aget_byte.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aget_byte(): -% op_aget(load="movsbl", shift="1", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/x86/op_aget_char.S b/runtime/interpreter/mterp/x86/op_aget_char.S deleted file mode 100644 index a35269bd65..0000000000 --- a/runtime/interpreter/mterp/x86/op_aget_char.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aget_char(): -% op_aget(load="movzwl", shift="2", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/x86/op_aget_object.S b/runtime/interpreter/mterp/x86/op_aget_object.S deleted file mode 100644 index 4cf90e94a4..0000000000 --- a/runtime/interpreter/mterp/x86/op_aget_object.S +++ /dev/null @@ -1,21 +0,0 @@ -%def op_aget_object(): -/* - * Array object get. vAA <- vBB[vCC]. - * - * for: aget-object - */ - /* op vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB (array object) - GET_VREG %ecx, %ecx # ecs <- vCC (requested index) - EXPORT_PC - movl %eax, OUT_ARG0(%esp) - movl %ecx, OUT_ARG1(%esp) - call SYMBOL(artAGetObjectFromMterp) # (array, index) - movl rSELF, %ecx - RESTORE_IBASE_FROM_SELF %ecx - cmpl $$0, THREAD_EXCEPTION_OFFSET(%ecx) - jnz MterpException - SET_VREG_OBJECT %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_aget_short.S b/runtime/interpreter/mterp/x86/op_aget_short.S deleted file mode 100644 index ca51ec8052..0000000000 --- a/runtime/interpreter/mterp/x86/op_aget_short.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aget_short(): -% op_aget(load="movswl", shift="2", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/x86/op_aget_wide.S b/runtime/interpreter/mterp/x86/op_aget_wide.S deleted file mode 100644 index 03cf50a5b8..0000000000 --- a/runtime/interpreter/mterp/x86/op_aget_wide.S +++ /dev/null @@ -1,17 +0,0 @@ -%def op_aget_wide(): -/* - * Array get, 64 bits. vAA <- vBB[vCC]. - */ - /* aget-wide vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB (array object) - GET_VREG %ecx, %ecx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - leal MIRROR_WIDE_ARRAY_DATA_OFFSET(%eax,%ecx,8), %eax - movq (%eax), %xmm0 # xmm0 <- vBB[vCC] - SET_WIDE_FP_VREG %xmm0, rINST # vAA <- xmm0 - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_and_int.S b/runtime/interpreter/mterp/x86/op_and_int.S deleted file mode 100644 index ffa28d70fa..0000000000 --- a/runtime/interpreter/mterp/x86/op_and_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_and_int(): -% binop(instr="andl (rFP,%ecx,4), %eax") diff --git a/runtime/interpreter/mterp/x86/op_and_int_2addr.S b/runtime/interpreter/mterp/x86/op_and_int_2addr.S deleted file mode 100644 index 8648980c19..0000000000 --- a/runtime/interpreter/mterp/x86/op_and_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_and_int_2addr(): -% binop2addr(instr="andl %eax, (rFP,%ecx,4)") diff --git a/runtime/interpreter/mterp/x86/op_and_int_lit16.S b/runtime/interpreter/mterp/x86/op_and_int_lit16.S deleted file mode 100644 index d7752b1230..0000000000 --- a/runtime/interpreter/mterp/x86/op_and_int_lit16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_and_int_lit16(): -% binopLit16(instr="andl %ecx, %eax") diff --git a/runtime/interpreter/mterp/x86/op_and_int_lit8.S b/runtime/interpreter/mterp/x86/op_and_int_lit8.S deleted file mode 100644 index a353178a88..0000000000 --- a/runtime/interpreter/mterp/x86/op_and_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_and_int_lit8(): -% binopLit8(instr="andl %ecx, %eax") diff --git a/runtime/interpreter/mterp/x86/op_and_long.S b/runtime/interpreter/mterp/x86/op_and_long.S deleted file mode 100644 index 15164aee79..0000000000 --- a/runtime/interpreter/mterp/x86/op_and_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_and_long(): -% binopWide(instr1="andl (rFP,%ecx,4), rIBASE", instr2="andl 4(rFP,%ecx,4), %eax") diff --git a/runtime/interpreter/mterp/x86/op_and_long_2addr.S b/runtime/interpreter/mterp/x86/op_and_long_2addr.S deleted file mode 100644 index 173c159f98..0000000000 --- a/runtime/interpreter/mterp/x86/op_and_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_and_long_2addr(): -% binopWide2addr(instr1="andl %eax, (rFP,rINST,4)", instr2="andl %ecx, 4(rFP,rINST,4)") diff --git a/runtime/interpreter/mterp/x86/op_aput.S b/runtime/interpreter/mterp/x86/op_aput.S deleted file mode 100644 index 60bcc5027d..0000000000 --- a/runtime/interpreter/mterp/x86/op_aput.S +++ /dev/null @@ -1,20 +0,0 @@ -%def op_aput(reg="rINST", store="movl", shift="4", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"): -/* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - */ - /* op vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB (array object) - GET_VREG %ecx, %ecx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - leal $data_offset(%eax,%ecx,$shift), %eax - GET_VREG rINST, rINST - $store $reg, (%eax) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_aput_boolean.S b/runtime/interpreter/mterp/x86/op_aput_boolean.S deleted file mode 100644 index 8420b5af8f..0000000000 --- a/runtime/interpreter/mterp/x86/op_aput_boolean.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aput_boolean(): -% op_aput(reg="rINSTbl", store="movb", shift="1", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/x86/op_aput_byte.S b/runtime/interpreter/mterp/x86/op_aput_byte.S deleted file mode 100644 index 6c181a48d9..0000000000 --- a/runtime/interpreter/mterp/x86/op_aput_byte.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aput_byte(): -% op_aput(reg="rINSTbl", store="movb", shift="1", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/x86/op_aput_char.S b/runtime/interpreter/mterp/x86/op_aput_char.S deleted file mode 100644 index 3f4602a7f4..0000000000 --- a/runtime/interpreter/mterp/x86/op_aput_char.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aput_char(): -% op_aput(reg="rINSTw", store="movw", shift="2", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/x86/op_aput_object.S b/runtime/interpreter/mterp/x86/op_aput_object.S deleted file mode 100644 index 5d0bb0b894..0000000000 --- a/runtime/interpreter/mterp/x86/op_aput_object.S +++ /dev/null @@ -1,16 +0,0 @@ -%def op_aput_object(): -/* - * Store an object into an array. vBB[vCC] <- vAA. - */ - /* op vAA, vBB, vCC */ - EXPORT_PC - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG0(%esp) - movl rPC, OUT_ARG1(%esp) - REFRESH_INST ${opnum} - movl rINST, OUT_ARG2(%esp) - call SYMBOL(MterpAputObject) # (array, index) - RESTORE_IBASE - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_aput_short.S b/runtime/interpreter/mterp/x86/op_aput_short.S deleted file mode 100644 index e76d83368b..0000000000 --- a/runtime/interpreter/mterp/x86/op_aput_short.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aput_short(): -% op_aput(reg="rINSTw", store="movw", shift="2", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/x86/op_aput_wide.S b/runtime/interpreter/mterp/x86/op_aput_wide.S deleted file mode 100644 index c59f7b37ae..0000000000 --- a/runtime/interpreter/mterp/x86/op_aput_wide.S +++ /dev/null @@ -1,18 +0,0 @@ -%def op_aput_wide(): -/* - * Array put, 64 bits. vBB[vCC] <- vAA. - * - */ - /* aput-wide vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB (array object) - GET_VREG %ecx, %ecx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - leal MIRROR_WIDE_ARRAY_DATA_OFFSET(%eax,%ecx,8), %eax - GET_WIDE_FP_VREG %xmm0, rINST # xmm0 <- vAA - movq %xmm0, (%eax) # vBB[vCC] <- xmm0 - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_array_length.S b/runtime/interpreter/mterp/x86/op_array_length.S deleted file mode 100644 index c9d8930643..0000000000 --- a/runtime/interpreter/mterp/x86/op_array_length.S +++ /dev/null @@ -1,13 +0,0 @@ -%def op_array_length(): -/* - * Return the length of an array. - */ - mov rINST, %eax # eax <- BA - sarl $$4, rINST # rINST <- B - GET_VREG %ecx, rINST # ecx <- vB (object ref) - testl %ecx, %ecx # is null? - je common_errNullObject - andb $$0xf, %al # eax <- A - movl MIRROR_ARRAY_LENGTH_OFFSET(%ecx), rINST - SET_VREG rINST, %eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/op_check_cast.S b/runtime/interpreter/mterp/x86/op_check_cast.S deleted file mode 100644 index 12f8543777..0000000000 --- a/runtime/interpreter/mterp/x86/op_check_cast.S +++ /dev/null @@ -1,19 +0,0 @@ -%def op_check_cast(): -/* - * Check to see if a cast from one class to another is allowed. - */ - /* check-cast vAA, class@BBBB */ - EXPORT_PC - movzwl 2(rPC), %eax # eax <- BBBB - movl %eax, OUT_ARG0(%esp) - leal VREG_ADDRESS(rINST), %ecx - movl %ecx, OUT_ARG1(%esp) - movl OFF_FP_METHOD(rFP),%eax - movl %eax, OUT_ARG2(%esp) - movl rSELF, %ecx - movl %ecx, OUT_ARG3(%esp) - call SYMBOL(MterpCheckCast) # (index, &obj, method, self) - RESTORE_IBASE - testb %al, %al - jnz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_cmp_long.S b/runtime/interpreter/mterp/x86/op_cmp_long.S deleted file mode 100644 index 0e33874a33..0000000000 --- a/runtime/interpreter/mterp/x86/op_cmp_long.S +++ /dev/null @@ -1,28 +0,0 @@ -%def op_cmp_long(): -/* - * Compare two 64-bit values. Puts 0, 1, or -1 into the destination - * register based on the results of the comparison. - */ - /* cmp-long vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG_HIGH %eax, %eax # eax <- v[BB+1], BB is clobbered - cmpl VREG_HIGH_ADDRESS(%ecx), %eax - jl .L${opcode}_smaller - jg .L${opcode}_bigger - movzbl 2(rPC), %eax # eax <- BB, restore BB - GET_VREG %eax, %eax # eax <- v[BB] - sub VREG_ADDRESS(%ecx), %eax - ja .L${opcode}_bigger - jb .L${opcode}_smaller -.L${opcode}_finish: - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -.L${opcode}_bigger: - movl $$1, %eax - jmp .L${opcode}_finish - -.L${opcode}_smaller: - movl $$-1, %eax - jmp .L${opcode}_finish diff --git a/runtime/interpreter/mterp/x86/op_cmpg_double.S b/runtime/interpreter/mterp/x86/op_cmpg_double.S deleted file mode 100644 index 1c04e997f1..0000000000 --- a/runtime/interpreter/mterp/x86/op_cmpg_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_cmpg_double(): -% fpcmp(suff="d", nanval="pos") diff --git a/runtime/interpreter/mterp/x86/op_cmpg_float.S b/runtime/interpreter/mterp/x86/op_cmpg_float.S deleted file mode 100644 index 797c3d52d7..0000000000 --- a/runtime/interpreter/mterp/x86/op_cmpg_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_cmpg_float(): -% fpcmp(suff="s", nanval="pos") diff --git a/runtime/interpreter/mterp/x86/op_cmpl_double.S b/runtime/interpreter/mterp/x86/op_cmpl_double.S deleted file mode 100644 index cbe8db713b..0000000000 --- a/runtime/interpreter/mterp/x86/op_cmpl_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_cmpl_double(): -% fpcmp(suff="d", nanval="neg") diff --git a/runtime/interpreter/mterp/x86/op_cmpl_float.S b/runtime/interpreter/mterp/x86/op_cmpl_float.S deleted file mode 100644 index 068f4cb5c1..0000000000 --- a/runtime/interpreter/mterp/x86/op_cmpl_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_cmpl_float(): -% fpcmp(suff="s", nanval="neg") diff --git a/runtime/interpreter/mterp/x86/op_const.S b/runtime/interpreter/mterp/x86/op_const.S deleted file mode 100644 index dc4342f571..0000000000 --- a/runtime/interpreter/mterp/x86/op_const.S +++ /dev/null @@ -1,5 +0,0 @@ -%def op_const(): - /* const vAA, #+BBBBbbbb */ - movl 2(rPC), %eax # grab all 32 bits at once - SET_VREG %eax, rINST # vAA<- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 diff --git a/runtime/interpreter/mterp/x86/op_const_16.S b/runtime/interpreter/mterp/x86/op_const_16.S deleted file mode 100644 index 84678ae2a9..0000000000 --- a/runtime/interpreter/mterp/x86/op_const_16.S +++ /dev/null @@ -1,5 +0,0 @@ -%def op_const_16(): - /* const/16 vAA, #+BBBB */ - movswl 2(rPC), %ecx # ecx <- ssssBBBB - SET_VREG %ecx, rINST # vAA <- ssssBBBB - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_const_4.S b/runtime/interpreter/mterp/x86/op_const_4.S deleted file mode 100644 index 8cfd9c096d..0000000000 --- a/runtime/interpreter/mterp/x86/op_const_4.S +++ /dev/null @@ -1,8 +0,0 @@ -%def op_const_4(): - /* const/4 vA, #+B */ - movsx rINSTbl, %eax # eax <-ssssssBx - movl $$0xf, rINST - andl %eax, rINST # rINST <- A - sarl $$4, %eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/op_const_class.S b/runtime/interpreter/mterp/x86/op_const_class.S deleted file mode 100644 index db12ec3141..0000000000 --- a/runtime/interpreter/mterp/x86/op_const_class.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_const_class(): -% const(helper="MterpConstClass") diff --git a/runtime/interpreter/mterp/x86/op_const_high16.S b/runtime/interpreter/mterp/x86/op_const_high16.S deleted file mode 100644 index 5252ba21ba..0000000000 --- a/runtime/interpreter/mterp/x86/op_const_high16.S +++ /dev/null @@ -1,6 +0,0 @@ -%def op_const_high16(): - /* const/high16 vAA, #+BBBB0000 */ - movzwl 2(rPC), %eax # eax <- 0000BBBB - sall $$16, %eax # eax <- BBBB0000 - SET_VREG %eax, rINST # vAA <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_const_method_handle.S b/runtime/interpreter/mterp/x86/op_const_method_handle.S deleted file mode 100644 index 2680c17aad..0000000000 --- a/runtime/interpreter/mterp/x86/op_const_method_handle.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_const_method_handle(): -% const(helper="MterpConstMethodHandle") diff --git a/runtime/interpreter/mterp/x86/op_const_method_type.S b/runtime/interpreter/mterp/x86/op_const_method_type.S deleted file mode 100644 index ea814bf648..0000000000 --- a/runtime/interpreter/mterp/x86/op_const_method_type.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_const_method_type(): -% const(helper="MterpConstMethodType") diff --git a/runtime/interpreter/mterp/x86/op_const_string.S b/runtime/interpreter/mterp/x86/op_const_string.S deleted file mode 100644 index 41376f8703..0000000000 --- a/runtime/interpreter/mterp/x86/op_const_string.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_const_string(): -% const(helper="MterpConstString") diff --git a/runtime/interpreter/mterp/x86/op_const_string_jumbo.S b/runtime/interpreter/mterp/x86/op_const_string_jumbo.S deleted file mode 100644 index dc70c255ce..0000000000 --- a/runtime/interpreter/mterp/x86/op_const_string_jumbo.S +++ /dev/null @@ -1,15 +0,0 @@ -%def op_const_string_jumbo(): - /* const/string vAA, String@BBBBBBBB */ - EXPORT_PC - movl 2(rPC), %eax # eax <- BBBB - movl %eax, OUT_ARG0(%esp) - movl rINST, OUT_ARG1(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) - call SYMBOL(MterpConstString) # (index, tgt_reg, shadow_frame, self) - RESTORE_IBASE - testb %al, %al - jnz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 diff --git a/runtime/interpreter/mterp/x86/op_const_wide.S b/runtime/interpreter/mterp/x86/op_const_wide.S deleted file mode 100644 index d076e837aa..0000000000 --- a/runtime/interpreter/mterp/x86/op_const_wide.S +++ /dev/null @@ -1,8 +0,0 @@ -%def op_const_wide(): - /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ - movl 2(rPC), %eax # eax <- lsw - movzbl rINSTbl, %ecx # ecx <- AA - movl 6(rPC), rINST # rINST <- msw - SET_VREG %eax, %ecx - SET_VREG_HIGH rINST, %ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 5 diff --git a/runtime/interpreter/mterp/x86/op_const_wide_16.S b/runtime/interpreter/mterp/x86/op_const_wide_16.S deleted file mode 100644 index 328cdeedce..0000000000 --- a/runtime/interpreter/mterp/x86/op_const_wide_16.S +++ /dev/null @@ -1,9 +0,0 @@ -%def op_const_wide_16(): - /* const-wide/16 vAA, #+BBBB */ - movswl 2(rPC), %eax # eax <- ssssBBBB - movl rIBASE, %ecx # preserve rIBASE (cltd trashes it) - cltd # rIBASE:eax <- ssssssssssssBBBB - SET_VREG_HIGH rIBASE, rINST # store msw - SET_VREG %eax, rINST # store lsw - movl %ecx, rIBASE # restore rIBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_const_wide_32.S b/runtime/interpreter/mterp/x86/op_const_wide_32.S deleted file mode 100644 index c4b5b6714d..0000000000 --- a/runtime/interpreter/mterp/x86/op_const_wide_32.S +++ /dev/null @@ -1,9 +0,0 @@ -%def op_const_wide_32(): - /* const-wide/32 vAA, #+BBBBbbbb */ - movl 2(rPC), %eax # eax <- BBBBbbbb - movl rIBASE, %ecx # preserve rIBASE (cltd trashes it) - cltd # rIBASE:eax <- ssssssssssssBBBB - SET_VREG_HIGH rIBASE, rINST # store msw - SET_VREG %eax, rINST # store lsw - movl %ecx, rIBASE # restore rIBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 diff --git a/runtime/interpreter/mterp/x86/op_const_wide_high16.S b/runtime/interpreter/mterp/x86/op_const_wide_high16.S deleted file mode 100644 index f99e674ce1..0000000000 --- a/runtime/interpreter/mterp/x86/op_const_wide_high16.S +++ /dev/null @@ -1,8 +0,0 @@ -%def op_const_wide_high16(): - /* const-wide/high16 vAA, #+BBBB000000000000 */ - movzwl 2(rPC), %eax # eax <- 0000BBBB - sall $$16, %eax # eax <- BBBB0000 - SET_VREG_HIGH %eax, rINST # v[AA+1] <- eax - xorl %eax, %eax - SET_VREG %eax, rINST # v[AA+0] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_div_double.S b/runtime/interpreter/mterp/x86/op_div_double.S deleted file mode 100644 index 6b342f89bf..0000000000 --- a/runtime/interpreter/mterp/x86/op_div_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_double(): -% sseBinop(instr="divs", suff="d") diff --git a/runtime/interpreter/mterp/x86/op_div_double_2addr.S b/runtime/interpreter/mterp/x86/op_div_double_2addr.S deleted file mode 100644 index 212c82547e..0000000000 --- a/runtime/interpreter/mterp/x86/op_div_double_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_double_2addr(): -% sseBinop2Addr(instr="divs", suff="d") diff --git a/runtime/interpreter/mterp/x86/op_div_float.S b/runtime/interpreter/mterp/x86/op_div_float.S deleted file mode 100644 index b6537d9d89..0000000000 --- a/runtime/interpreter/mterp/x86/op_div_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_float(): -% sseBinop(instr="divs", suff="s") diff --git a/runtime/interpreter/mterp/x86/op_div_float_2addr.S b/runtime/interpreter/mterp/x86/op_div_float_2addr.S deleted file mode 100644 index 19ae27d61a..0000000000 --- a/runtime/interpreter/mterp/x86/op_div_float_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_float_2addr(): -% sseBinop2Addr(instr="divs", suff="s") diff --git a/runtime/interpreter/mterp/x86/op_div_int.S b/runtime/interpreter/mterp/x86/op_div_int.S deleted file mode 100644 index 4df3b927b4..0000000000 --- a/runtime/interpreter/mterp/x86/op_div_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_int(): -% bindiv(result="%eax", special="$0x80000000", rem="0") diff --git a/runtime/interpreter/mterp/x86/op_div_int_2addr.S b/runtime/interpreter/mterp/x86/op_div_int_2addr.S deleted file mode 100644 index d43135f0dd..0000000000 --- a/runtime/interpreter/mterp/x86/op_div_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_int_2addr(): -% bindiv2addr(result="%eax", special="$0x80000000") diff --git a/runtime/interpreter/mterp/x86/op_div_int_lit16.S b/runtime/interpreter/mterp/x86/op_div_int_lit16.S deleted file mode 100644 index e561eae38e..0000000000 --- a/runtime/interpreter/mterp/x86/op_div_int_lit16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_int_lit16(): -% bindivLit16(result="%eax", special="$0x80000000") diff --git a/runtime/interpreter/mterp/x86/op_div_int_lit8.S b/runtime/interpreter/mterp/x86/op_div_int_lit8.S deleted file mode 100644 index 5facee247e..0000000000 --- a/runtime/interpreter/mterp/x86/op_div_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_int_lit8(): -% bindivLit8(result="%eax", special="$0x80000000") diff --git a/runtime/interpreter/mterp/x86/op_div_long.S b/runtime/interpreter/mterp/x86/op_div_long.S deleted file mode 100644 index 2fdf6ad1bf..0000000000 --- a/runtime/interpreter/mterp/x86/op_div_long.S +++ /dev/null @@ -1,23 +0,0 @@ -%def op_div_long(routine="art_quick_ldiv"): -/* art_quick_* methods has quick abi, - * so use eax, ecx, edx, ebx for args - */ - /* div vAA, vBB, vCC */ - .extern $routine - mov rIBASE, LOCAL0(%esp) # save rIBASE/%edx - mov rINST, LOCAL1(%esp) # save rINST/%ebx - movzbl 3(rPC), %eax # eax <- CC - GET_VREG %ecx, %eax - GET_VREG_HIGH %ebx, %eax - movl %ecx, %edx - orl %ebx, %ecx - jz common_errDivideByZero - movzbl 2(rPC), %eax # eax <- BB - GET_VREG_HIGH %ecx, %eax - GET_VREG %eax, %eax - call SYMBOL($routine) - mov LOCAL1(%esp), rINST # restore rINST/%ebx - SET_VREG_HIGH rIBASE, rINST - SET_VREG %eax, rINST - mov LOCAL0(%esp), rIBASE # restore rIBASE/%edx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_div_long_2addr.S b/runtime/interpreter/mterp/x86/op_div_long_2addr.S deleted file mode 100644 index b3d81a4580..0000000000 --- a/runtime/interpreter/mterp/x86/op_div_long_2addr.S +++ /dev/null @@ -1,25 +0,0 @@ -%def op_div_long_2addr(routine="art_quick_ldiv"): -/* art_quick_* methods has quick abi, - * so use eax, ecx, edx, ebx for args - */ - /* div/2addr vA, vB */ - .extern $routine - mov rIBASE, LOCAL0(%esp) # save rIBASE/%edx - movzbl rINSTbl, %eax - shrl $$4, %eax # eax <- B - andb $$0xf, rINSTbl # rINST <- A - mov rINST, LOCAL1(%esp) # save rINST/%ebx - movl %ebx, %ecx - GET_VREG %edx, %eax - GET_VREG_HIGH %ebx, %eax - movl %edx, %eax - orl %ebx, %eax - jz common_errDivideByZero - GET_VREG %eax, %ecx - GET_VREG_HIGH %ecx, %ecx - call SYMBOL($routine) - mov LOCAL1(%esp), rINST # restore rINST/%ebx - SET_VREG_HIGH rIBASE, rINST - SET_VREG %eax, rINST - mov LOCAL0(%esp), rIBASE # restore rIBASE/%edx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/op_double_to_float.S b/runtime/interpreter/mterp/x86/op_double_to_float.S deleted file mode 100644 index a52b505368..0000000000 --- a/runtime/interpreter/mterp/x86/op_double_to_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_double_to_float(): -% fpcvt(load="fldl", store="fstps") diff --git a/runtime/interpreter/mterp/x86/op_double_to_int.S b/runtime/interpreter/mterp/x86/op_double_to_int.S deleted file mode 100644 index 65c31fbf5e..0000000000 --- a/runtime/interpreter/mterp/x86/op_double_to_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_double_to_int(): -% cvtfp_int(srcdouble="1", tgtlong="0") diff --git a/runtime/interpreter/mterp/x86/op_double_to_long.S b/runtime/interpreter/mterp/x86/op_double_to_long.S deleted file mode 100644 index 1eb74bf539..0000000000 --- a/runtime/interpreter/mterp/x86/op_double_to_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_double_to_long(): -% cvtfp_int(srcdouble="1", tgtlong="1") diff --git a/runtime/interpreter/mterp/x86/op_fill_array_data.S b/runtime/interpreter/mterp/x86/op_fill_array_data.S deleted file mode 100644 index f121787f62..0000000000 --- a/runtime/interpreter/mterp/x86/op_fill_array_data.S +++ /dev/null @@ -1,13 +0,0 @@ -%def op_fill_array_data(): - /* fill-array-data vAA, +BBBBBBBB */ - EXPORT_PC - movl 2(rPC), %ecx # ecx <- BBBBbbbb - leal (rPC,%ecx,2), %ecx # ecx <- PC + BBBBbbbb*2 - GET_VREG %eax, rINST # eax <- vAA (array object) - movl %eax, OUT_ARG0(%esp) - movl %ecx, OUT_ARG1(%esp) - call SYMBOL(MterpFillArrayData) # (obj, payload) - REFRESH_IBASE - testb %al, %al # 0 means an exception is thrown - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 diff --git a/runtime/interpreter/mterp/x86/op_filled_new_array.S b/runtime/interpreter/mterp/x86/op_filled_new_array.S deleted file mode 100644 index 8e5bd03978..0000000000 --- a/runtime/interpreter/mterp/x86/op_filled_new_array.S +++ /dev/null @@ -1,20 +0,0 @@ -%def op_filled_new_array(helper="MterpFilledNewArray"): -/* - * Create a new array with elements filled from registers. - * - * for: filled-new-array, filled-new-array/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ - .extern $helper - EXPORT_PC - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG0(%esp) - movl rPC, OUT_ARG1(%esp) - movl rSELF, %ecx - movl %ecx, OUT_ARG2(%esp) - call SYMBOL($helper) - REFRESH_IBASE - testb %al, %al # 0 means an exception is thrown - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 diff --git a/runtime/interpreter/mterp/x86/op_filled_new_array_range.S b/runtime/interpreter/mterp/x86/op_filled_new_array_range.S deleted file mode 100644 index 1667de149a..0000000000 --- a/runtime/interpreter/mterp/x86/op_filled_new_array_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_filled_new_array_range(): -% op_filled_new_array(helper="MterpFilledNewArrayRange") diff --git a/runtime/interpreter/mterp/x86/op_float_to_double.S b/runtime/interpreter/mterp/x86/op_float_to_double.S deleted file mode 100644 index 152bb00859..0000000000 --- a/runtime/interpreter/mterp/x86/op_float_to_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_float_to_double(): -% fpcvt(load="flds", store="fstpl", wide="1") diff --git a/runtime/interpreter/mterp/x86/op_float_to_int.S b/runtime/interpreter/mterp/x86/op_float_to_int.S deleted file mode 100644 index 1f8e5cc1e5..0000000000 --- a/runtime/interpreter/mterp/x86/op_float_to_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_float_to_int(): -% cvtfp_int(srcdouble="0", tgtlong="0") diff --git a/runtime/interpreter/mterp/x86/op_float_to_long.S b/runtime/interpreter/mterp/x86/op_float_to_long.S deleted file mode 100644 index a0567691c2..0000000000 --- a/runtime/interpreter/mterp/x86/op_float_to_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_float_to_long(): -% cvtfp_int(srcdouble="0", tgtlong="1") diff --git a/runtime/interpreter/mterp/x86/op_goto.S b/runtime/interpreter/mterp/x86/op_goto.S deleted file mode 100644 index b6236fe9a8..0000000000 --- a/runtime/interpreter/mterp/x86/op_goto.S +++ /dev/null @@ -1,11 +0,0 @@ -%def op_goto(): -/* - * Unconditional branch, 8-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto +AA */ - movsbl rINSTbl, rINST # rINST <- ssssssAA - testl rINST, rINST - jmp MterpCommonTakenBranch diff --git a/runtime/interpreter/mterp/x86/op_goto_16.S b/runtime/interpreter/mterp/x86/op_goto_16.S deleted file mode 100644 index a8c2bf590d..0000000000 --- a/runtime/interpreter/mterp/x86/op_goto_16.S +++ /dev/null @@ -1,11 +0,0 @@ -%def op_goto_16(): -/* - * Unconditional branch, 16-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto/16 +AAAA */ - movswl 2(rPC), rINST # rINST <- ssssAAAA - testl rINST, rINST - jmp MterpCommonTakenBranch diff --git a/runtime/interpreter/mterp/x86/op_goto_32.S b/runtime/interpreter/mterp/x86/op_goto_32.S deleted file mode 100644 index 87d0e338e0..0000000000 --- a/runtime/interpreter/mterp/x86/op_goto_32.S +++ /dev/null @@ -1,16 +0,0 @@ -%def op_goto_32(): -/* - * Unconditional branch, 32-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - * - * Unlike most opcodes, this one is allowed to branch to itself, so - * our "backward branch" test must be "<=0" instead of "<0". Because - * we need the V bit set, we'll use an adds to convert from Dalvik - * offset to byte offset. - */ - /* goto/32 +AAAAAAAA */ - movl 2(rPC), rINST # rINST <- AAAAAAAA - testl rINST, rINST - jmp MterpCommonTakenBranch diff --git a/runtime/interpreter/mterp/x86/op_if_eq.S b/runtime/interpreter/mterp/x86/op_if_eq.S deleted file mode 100644 index 4d1f6a54d2..0000000000 --- a/runtime/interpreter/mterp/x86/op_if_eq.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_eq(): -% bincmp(revcmp="ne") diff --git a/runtime/interpreter/mterp/x86/op_if_eqz.S b/runtime/interpreter/mterp/x86/op_if_eqz.S deleted file mode 100644 index 12de558550..0000000000 --- a/runtime/interpreter/mterp/x86/op_if_eqz.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_eqz(): -% zcmp(revcmp="ne") diff --git a/runtime/interpreter/mterp/x86/op_if_ge.S b/runtime/interpreter/mterp/x86/op_if_ge.S deleted file mode 100644 index 684902776f..0000000000 --- a/runtime/interpreter/mterp/x86/op_if_ge.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_ge(): -% bincmp(revcmp="l") diff --git a/runtime/interpreter/mterp/x86/op_if_gez.S b/runtime/interpreter/mterp/x86/op_if_gez.S deleted file mode 100644 index 87bdcbfa32..0000000000 --- a/runtime/interpreter/mterp/x86/op_if_gez.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_gez(): -% zcmp(revcmp="l") diff --git a/runtime/interpreter/mterp/x86/op_if_gt.S b/runtime/interpreter/mterp/x86/op_if_gt.S deleted file mode 100644 index 4a521006b3..0000000000 --- a/runtime/interpreter/mterp/x86/op_if_gt.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_gt(): -% bincmp(revcmp="le") diff --git a/runtime/interpreter/mterp/x86/op_if_gtz.S b/runtime/interpreter/mterp/x86/op_if_gtz.S deleted file mode 100644 index a0b2e3a35b..0000000000 --- a/runtime/interpreter/mterp/x86/op_if_gtz.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_gtz(): -% zcmp(revcmp="le") diff --git a/runtime/interpreter/mterp/x86/op_if_le.S b/runtime/interpreter/mterp/x86/op_if_le.S deleted file mode 100644 index 69e94db79f..0000000000 --- a/runtime/interpreter/mterp/x86/op_if_le.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_le(): -% bincmp(revcmp="g") diff --git a/runtime/interpreter/mterp/x86/op_if_lez.S b/runtime/interpreter/mterp/x86/op_if_lez.S deleted file mode 100644 index 42e69d969a..0000000000 --- a/runtime/interpreter/mterp/x86/op_if_lez.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_lez(): -% zcmp(revcmp="g") diff --git a/runtime/interpreter/mterp/x86/op_if_lt.S b/runtime/interpreter/mterp/x86/op_if_lt.S deleted file mode 100644 index 052aabe1e7..0000000000 --- a/runtime/interpreter/mterp/x86/op_if_lt.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_lt(): -% bincmp(revcmp="ge") diff --git a/runtime/interpreter/mterp/x86/op_if_ltz.S b/runtime/interpreter/mterp/x86/op_if_ltz.S deleted file mode 100644 index 8e13e48c2a..0000000000 --- a/runtime/interpreter/mterp/x86/op_if_ltz.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_ltz(): -% zcmp(revcmp="ge") diff --git a/runtime/interpreter/mterp/x86/op_if_ne.S b/runtime/interpreter/mterp/x86/op_if_ne.S deleted file mode 100644 index 2cfd8a9a1e..0000000000 --- a/runtime/interpreter/mterp/x86/op_if_ne.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_ne(): -% bincmp(revcmp="e") diff --git a/runtime/interpreter/mterp/x86/op_if_nez.S b/runtime/interpreter/mterp/x86/op_if_nez.S deleted file mode 100644 index 261a173a38..0000000000 --- a/runtime/interpreter/mterp/x86/op_if_nez.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_nez(): -% zcmp(revcmp="e") diff --git a/runtime/interpreter/mterp/x86/op_iget.S b/runtime/interpreter/mterp/x86/op_iget.S deleted file mode 100644 index d09edc0a17..0000000000 --- a/runtime/interpreter/mterp/x86/op_iget.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget(is_object="0", helper="MterpIGetU32"): -% field(helper=helper) diff --git a/runtime/interpreter/mterp/x86/op_iget_boolean.S b/runtime/interpreter/mterp/x86/op_iget_boolean.S deleted file mode 100644 index cb8edeec77..0000000000 --- a/runtime/interpreter/mterp/x86/op_iget_boolean.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_boolean(): -% op_iget(helper="MterpIGetU8") diff --git a/runtime/interpreter/mterp/x86/op_iget_boolean_quick.S b/runtime/interpreter/mterp/x86/op_iget_boolean_quick.S deleted file mode 100644 index 4e1676844b..0000000000 --- a/runtime/interpreter/mterp/x86/op_iget_boolean_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_boolean_quick(): -% op_iget_quick(load="movsbl") diff --git a/runtime/interpreter/mterp/x86/op_iget_byte.S b/runtime/interpreter/mterp/x86/op_iget_byte.S deleted file mode 100644 index 2b87fb16b5..0000000000 --- a/runtime/interpreter/mterp/x86/op_iget_byte.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_byte(): -% op_iget(helper="MterpIGetI8") diff --git a/runtime/interpreter/mterp/x86/op_iget_byte_quick.S b/runtime/interpreter/mterp/x86/op_iget_byte_quick.S deleted file mode 100644 index b92936c28d..0000000000 --- a/runtime/interpreter/mterp/x86/op_iget_byte_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_byte_quick(): -% op_iget_quick(load="movsbl") diff --git a/runtime/interpreter/mterp/x86/op_iget_char.S b/runtime/interpreter/mterp/x86/op_iget_char.S deleted file mode 100644 index 001bd03e2b..0000000000 --- a/runtime/interpreter/mterp/x86/op_iget_char.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_char(): -% op_iget(helper="MterpIGetU16") diff --git a/runtime/interpreter/mterp/x86/op_iget_char_quick.S b/runtime/interpreter/mterp/x86/op_iget_char_quick.S deleted file mode 100644 index d6f836b28e..0000000000 --- a/runtime/interpreter/mterp/x86/op_iget_char_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_char_quick(): -% op_iget_quick(load="movzwl") diff --git a/runtime/interpreter/mterp/x86/op_iget_object.S b/runtime/interpreter/mterp/x86/op_iget_object.S deleted file mode 100644 index 4e5f769547..0000000000 --- a/runtime/interpreter/mterp/x86/op_iget_object.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_object(): -% op_iget(is_object="1", helper="MterpIGetObj") diff --git a/runtime/interpreter/mterp/x86/op_iget_object_quick.S b/runtime/interpreter/mterp/x86/op_iget_object_quick.S deleted file mode 100644 index 66340e91d2..0000000000 --- a/runtime/interpreter/mterp/x86/op_iget_object_quick.S +++ /dev/null @@ -1,18 +0,0 @@ -%def op_iget_object_quick(): - /* For: iget-object-quick */ - /* op vA, vB, offset@CCCC */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $$4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # vB (object we're operating on) - movzwl 2(rPC), %eax # eax <- field byte offset - movl %ecx, OUT_ARG0(%esp) - movl %eax, OUT_ARG1(%esp) - EXPORT_PC - call SYMBOL(artIGetObjectFromMterp) # (obj, offset) - movl rSELF, %ecx - RESTORE_IBASE_FROM_SELF %ecx - cmpl $$0, THREAD_EXCEPTION_OFFSET(%ecx) - jnz MterpException # bail out - andb $$0xf,rINSTbl # rINST <- A - SET_VREG_OBJECT %eax, rINST # fp[A] <- value - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_iget_quick.S b/runtime/interpreter/mterp/x86/op_iget_quick.S deleted file mode 100644 index 8ca2c86f3f..0000000000 --- a/runtime/interpreter/mterp/x86/op_iget_quick.S +++ /dev/null @@ -1,13 +0,0 @@ -%def op_iget_quick(load="movl"): - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset@CCCC */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $$4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # vB (object we're operating on) - movzwl 2(rPC), %eax # eax <- field byte offset - testl %ecx, %ecx # is object null? - je common_errNullObject - ${load} (%ecx,%eax,1), %eax - andb $$0xf,rINSTbl # rINST <- A - SET_VREG %eax, rINST # fp[A] <- value - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_iget_short.S b/runtime/interpreter/mterp/x86/op_iget_short.S deleted file mode 100644 index a62c4d998f..0000000000 --- a/runtime/interpreter/mterp/x86/op_iget_short.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_short(): -% op_iget(helper="MterpIGetI16") diff --git a/runtime/interpreter/mterp/x86/op_iget_short_quick.S b/runtime/interpreter/mterp/x86/op_iget_short_quick.S deleted file mode 100644 index f5e48d621a..0000000000 --- a/runtime/interpreter/mterp/x86/op_iget_short_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_short_quick(): -% op_iget_quick(load="movswl") diff --git a/runtime/interpreter/mterp/x86/op_iget_wide.S b/runtime/interpreter/mterp/x86/op_iget_wide.S deleted file mode 100644 index 9643cc3403..0000000000 --- a/runtime/interpreter/mterp/x86/op_iget_wide.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_wide(): -% op_iget(helper="MterpIGetU64") diff --git a/runtime/interpreter/mterp/x86/op_iget_wide_quick.S b/runtime/interpreter/mterp/x86/op_iget_wide_quick.S deleted file mode 100644 index c1a13269f3..0000000000 --- a/runtime/interpreter/mterp/x86/op_iget_wide_quick.S +++ /dev/null @@ -1,12 +0,0 @@ -%def op_iget_wide_quick(): - /* iget-wide-quick vA, vB, offset@CCCC */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $$4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # vB (object we're operating on) - movzwl 2(rPC), %eax # eax <- field byte offset - testl %ecx, %ecx # is object null? - je common_errNullObject - movq (%ecx,%eax,1), %xmm0 - andb $$0xf, rINSTbl # rINST <- A - SET_WIDE_FP_VREG %xmm0, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_instance_of.S b/runtime/interpreter/mterp/x86/op_instance_of.S deleted file mode 100644 index ae1afae855..0000000000 --- a/runtime/interpreter/mterp/x86/op_instance_of.S +++ /dev/null @@ -1,27 +0,0 @@ -%def op_instance_of(): -/* - * Check to see if an object reference is an instance of a class. - * - * Most common situation is a non-null object, being compared against - * an already-resolved class. - */ - /* instance-of vA, vB, class@CCCC */ - EXPORT_PC - movzwl 2(rPC), %eax # eax <- BBBB - movl %eax, OUT_ARG0(%esp) - movl rINST, %eax # eax <- BA - sarl $$4, %eax # eax <- B - leal VREG_ADDRESS(%eax), %ecx # Get object address - movl %ecx, OUT_ARG1(%esp) - movl OFF_FP_METHOD(rFP),%eax - movl %eax, OUT_ARG2(%esp) - movl rSELF, %ecx - movl %ecx, OUT_ARG3(%esp) - call SYMBOL(MterpInstanceOf) # (index, &obj, method, self) - movl rSELF, %ecx - RESTORE_IBASE_FROM_SELF %ecx - cmpl $$0, THREAD_EXCEPTION_OFFSET(%ecx) - jnz MterpException - andb $$0xf, rINSTbl # rINSTbl <- A - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_int_to_byte.S b/runtime/interpreter/mterp/x86/op_int_to_byte.S deleted file mode 100644 index 80e4d5c310..0000000000 --- a/runtime/interpreter/mterp/x86/op_int_to_byte.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_int_to_byte(): -% unop(instr="movsbl %al, %eax") diff --git a/runtime/interpreter/mterp/x86/op_int_to_char.S b/runtime/interpreter/mterp/x86/op_int_to_char.S deleted file mode 100644 index 83e9868ef3..0000000000 --- a/runtime/interpreter/mterp/x86/op_int_to_char.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_int_to_char(): -% unop(instr="movzwl %ax,%eax") diff --git a/runtime/interpreter/mterp/x86/op_int_to_double.S b/runtime/interpreter/mterp/x86/op_int_to_double.S deleted file mode 100644 index e304d8eaf5..0000000000 --- a/runtime/interpreter/mterp/x86/op_int_to_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_int_to_double(): -% fpcvt(load="fildl", store="fstpl", wide="1") diff --git a/runtime/interpreter/mterp/x86/op_int_to_float.S b/runtime/interpreter/mterp/x86/op_int_to_float.S deleted file mode 100644 index fe00097c69..0000000000 --- a/runtime/interpreter/mterp/x86/op_int_to_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_int_to_float(): -% fpcvt(load="fildl", store="fstps") diff --git a/runtime/interpreter/mterp/x86/op_int_to_long.S b/runtime/interpreter/mterp/x86/op_int_to_long.S deleted file mode 100644 index 849197382f..0000000000 --- a/runtime/interpreter/mterp/x86/op_int_to_long.S +++ /dev/null @@ -1,13 +0,0 @@ -%def op_int_to_long(): - /* int to long vA, vB */ - movzbl rINSTbl, %eax # eax <- +A - sarl $$4, %eax # eax <- B - GET_VREG %eax, %eax # eax <- vB - andb $$0xf, rINSTbl # rINST <- A - movl rIBASE, %ecx # cltd trashes rIBASE/edx - cltd # rINST:eax<- sssssssBBBBBBBB - SET_VREG_HIGH rIBASE, rINST # v[A+1] <- rIBASE - SET_VREG %eax, rINST # v[A+0] <- %eax - movl %ecx, rIBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - diff --git a/runtime/interpreter/mterp/x86/op_int_to_short.S b/runtime/interpreter/mterp/x86/op_int_to_short.S deleted file mode 100644 index e4db90b801..0000000000 --- a/runtime/interpreter/mterp/x86/op_int_to_short.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_int_to_short(): -% unop(instr="movswl %ax, %eax") diff --git a/runtime/interpreter/mterp/x86/op_invoke_custom.S b/runtime/interpreter/mterp/x86/op_invoke_custom.S deleted file mode 100644 index 4bba9ee524..0000000000 --- a/runtime/interpreter/mterp/x86/op_invoke_custom.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_custom(): -% invoke(helper="MterpInvokeCustom") diff --git a/runtime/interpreter/mterp/x86/op_invoke_custom_range.S b/runtime/interpreter/mterp/x86/op_invoke_custom_range.S deleted file mode 100644 index 57e61af1fa..0000000000 --- a/runtime/interpreter/mterp/x86/op_invoke_custom_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_custom_range(): -% invoke(helper="MterpInvokeCustomRange") diff --git a/runtime/interpreter/mterp/x86/op_invoke_direct.S b/runtime/interpreter/mterp/x86/op_invoke_direct.S deleted file mode 100644 index d3139cf39b..0000000000 --- a/runtime/interpreter/mterp/x86/op_invoke_direct.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_direct(): -% invoke(helper="MterpInvokeDirect") diff --git a/runtime/interpreter/mterp/x86/op_invoke_direct_range.S b/runtime/interpreter/mterp/x86/op_invoke_direct_range.S deleted file mode 100644 index b4a161f48b..0000000000 --- a/runtime/interpreter/mterp/x86/op_invoke_direct_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_direct_range(): -% invoke(helper="MterpInvokeDirectRange") diff --git a/runtime/interpreter/mterp/x86/op_invoke_interface.S b/runtime/interpreter/mterp/x86/op_invoke_interface.S deleted file mode 100644 index 559b9768d9..0000000000 --- a/runtime/interpreter/mterp/x86/op_invoke_interface.S +++ /dev/null @@ -1,9 +0,0 @@ -%def op_invoke_interface(): -% invoke(helper="MterpInvokeInterface") -/* - * Handle an interface method call. - * - * for: invoke-interface, invoke-interface/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ diff --git a/runtime/interpreter/mterp/x86/op_invoke_interface_range.S b/runtime/interpreter/mterp/x86/op_invoke_interface_range.S deleted file mode 100644 index 2989115377..0000000000 --- a/runtime/interpreter/mterp/x86/op_invoke_interface_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_interface_range(): -% invoke(helper="MterpInvokeInterfaceRange") diff --git a/runtime/interpreter/mterp/x86/op_invoke_polymorphic.S b/runtime/interpreter/mterp/x86/op_invoke_polymorphic.S deleted file mode 100644 index ce61f5aa0e..0000000000 --- a/runtime/interpreter/mterp/x86/op_invoke_polymorphic.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_polymorphic(): -% invoke_polymorphic(helper="MterpInvokePolymorphic") diff --git a/runtime/interpreter/mterp/x86/op_invoke_polymorphic_range.S b/runtime/interpreter/mterp/x86/op_invoke_polymorphic_range.S deleted file mode 100644 index 16731bdb40..0000000000 --- a/runtime/interpreter/mterp/x86/op_invoke_polymorphic_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_polymorphic_range(): -% invoke_polymorphic(helper="MterpInvokePolymorphicRange") diff --git a/runtime/interpreter/mterp/x86/op_invoke_static.S b/runtime/interpreter/mterp/x86/op_invoke_static.S deleted file mode 100644 index 3e38d36a27..0000000000 --- a/runtime/interpreter/mterp/x86/op_invoke_static.S +++ /dev/null @@ -1,3 +0,0 @@ -%def op_invoke_static(): -% invoke(helper="MterpInvokeStatic") - diff --git a/runtime/interpreter/mterp/x86/op_invoke_static_range.S b/runtime/interpreter/mterp/x86/op_invoke_static_range.S deleted file mode 100644 index e0a546c92b..0000000000 --- a/runtime/interpreter/mterp/x86/op_invoke_static_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_static_range(): -% invoke(helper="MterpInvokeStaticRange") diff --git a/runtime/interpreter/mterp/x86/op_invoke_super.S b/runtime/interpreter/mterp/x86/op_invoke_super.S deleted file mode 100644 index 5b2055010e..0000000000 --- a/runtime/interpreter/mterp/x86/op_invoke_super.S +++ /dev/null @@ -1,9 +0,0 @@ -%def op_invoke_super(): -% invoke(helper="MterpInvokeSuper") -/* - * Handle a "super" method call. - * - * for: invoke-super, invoke-super/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ diff --git a/runtime/interpreter/mterp/x86/op_invoke_super_range.S b/runtime/interpreter/mterp/x86/op_invoke_super_range.S deleted file mode 100644 index caeafaa13c..0000000000 --- a/runtime/interpreter/mterp/x86/op_invoke_super_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_super_range(): -% invoke(helper="MterpInvokeSuperRange") diff --git a/runtime/interpreter/mterp/x86/op_invoke_virtual.S b/runtime/interpreter/mterp/x86/op_invoke_virtual.S deleted file mode 100644 index e27eeedacc..0000000000 --- a/runtime/interpreter/mterp/x86/op_invoke_virtual.S +++ /dev/null @@ -1,9 +0,0 @@ -%def op_invoke_virtual(): -% invoke(helper="MterpInvokeVirtual") -/* - * Handle a virtual method call. - * - * for: invoke-virtual, invoke-virtual/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ diff --git a/runtime/interpreter/mterp/x86/op_invoke_virtual_quick.S b/runtime/interpreter/mterp/x86/op_invoke_virtual_quick.S deleted file mode 100644 index ea72c171ec..0000000000 --- a/runtime/interpreter/mterp/x86/op_invoke_virtual_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_virtual_quick(): -% invoke(helper="MterpInvokeVirtualQuick") diff --git a/runtime/interpreter/mterp/x86/op_invoke_virtual_range.S b/runtime/interpreter/mterp/x86/op_invoke_virtual_range.S deleted file mode 100644 index baa0779593..0000000000 --- a/runtime/interpreter/mterp/x86/op_invoke_virtual_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_virtual_range(): -% invoke(helper="MterpInvokeVirtualRange") diff --git a/runtime/interpreter/mterp/x86/op_invoke_virtual_range_quick.S b/runtime/interpreter/mterp/x86/op_invoke_virtual_range_quick.S deleted file mode 100644 index 1d961a0781..0000000000 --- a/runtime/interpreter/mterp/x86/op_invoke_virtual_range_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_virtual_range_quick(): -% invoke(helper="MterpInvokeVirtualQuickRange") diff --git a/runtime/interpreter/mterp/x86/op_iput.S b/runtime/interpreter/mterp/x86/op_iput.S deleted file mode 100644 index e5351baf55..0000000000 --- a/runtime/interpreter/mterp/x86/op_iput.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput(is_object="0", helper="MterpIPutU32"): -% field(helper=helper) diff --git a/runtime/interpreter/mterp/x86/op_iput_boolean.S b/runtime/interpreter/mterp/x86/op_iput_boolean.S deleted file mode 100644 index 9eb849877b..0000000000 --- a/runtime/interpreter/mterp/x86/op_iput_boolean.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_boolean(): -% op_iput(helper="MterpIPutU8") diff --git a/runtime/interpreter/mterp/x86/op_iput_boolean_quick.S b/runtime/interpreter/mterp/x86/op_iput_boolean_quick.S deleted file mode 100644 index c304c76b51..0000000000 --- a/runtime/interpreter/mterp/x86/op_iput_boolean_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_boolean_quick(): -% op_iput_quick(reg="rINSTbl", store="movb") diff --git a/runtime/interpreter/mterp/x86/op_iput_byte.S b/runtime/interpreter/mterp/x86/op_iput_byte.S deleted file mode 100644 index 4b74f9fb0e..0000000000 --- a/runtime/interpreter/mterp/x86/op_iput_byte.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_byte(): -% op_iput(helper="MterpIPutI8") diff --git a/runtime/interpreter/mterp/x86/op_iput_byte_quick.S b/runtime/interpreter/mterp/x86/op_iput_byte_quick.S deleted file mode 100644 index dac18e63cc..0000000000 --- a/runtime/interpreter/mterp/x86/op_iput_byte_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_byte_quick(): -% op_iput_quick(reg="rINSTbl", store="movb") diff --git a/runtime/interpreter/mterp/x86/op_iput_char.S b/runtime/interpreter/mterp/x86/op_iput_char.S deleted file mode 100644 index 64a249fc12..0000000000 --- a/runtime/interpreter/mterp/x86/op_iput_char.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_char(): -% op_iput(helper="MterpIPutU16") diff --git a/runtime/interpreter/mterp/x86/op_iput_char_quick.S b/runtime/interpreter/mterp/x86/op_iput_char_quick.S deleted file mode 100644 index 21a25812b1..0000000000 --- a/runtime/interpreter/mterp/x86/op_iput_char_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_char_quick(): -% op_iput_quick(reg="rINSTw", store="movw") diff --git a/runtime/interpreter/mterp/x86/op_iput_object.S b/runtime/interpreter/mterp/x86/op_iput_object.S deleted file mode 100644 index 131edd5dbd..0000000000 --- a/runtime/interpreter/mterp/x86/op_iput_object.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_object(): -% op_iput(is_object="1", helper="MterpIPutObj") diff --git a/runtime/interpreter/mterp/x86/op_iput_object_quick.S b/runtime/interpreter/mterp/x86/op_iput_object_quick.S deleted file mode 100644 index 6b6fb2d553..0000000000 --- a/runtime/interpreter/mterp/x86/op_iput_object_quick.S +++ /dev/null @@ -1,12 +0,0 @@ -%def op_iput_object_quick(): - EXPORT_PC - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG0(%esp) - movl rPC, OUT_ARG1(%esp) - REFRESH_INST ${opnum} - movl rINST, OUT_ARG2(%esp) - call SYMBOL(MterpIputObjectQuick) - testb %al, %al - jz MterpException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_iput_quick.S b/runtime/interpreter/mterp/x86/op_iput_quick.S deleted file mode 100644 index 5198cfe5dc..0000000000 --- a/runtime/interpreter/mterp/x86/op_iput_quick.S +++ /dev/null @@ -1,13 +0,0 @@ -%def op_iput_quick(reg="rINST", store="movl"): - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $$4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # vB (object we're operating on) - testl %ecx, %ecx # is object null? - je common_errNullObject - andb $$0xf, rINSTbl # rINST <- A - GET_VREG rINST, rINST # rINST <- v[A] - movzwl 2(rPC), %eax # eax <- field byte offset - ${store} ${reg}, (%ecx,%eax,1) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_iput_short.S b/runtime/interpreter/mterp/x86/op_iput_short.S deleted file mode 100644 index e631a3b259..0000000000 --- a/runtime/interpreter/mterp/x86/op_iput_short.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_short(): -% op_iput(helper="MterpIPutI16") diff --git a/runtime/interpreter/mterp/x86/op_iput_short_quick.S b/runtime/interpreter/mterp/x86/op_iput_short_quick.S deleted file mode 100644 index 5eb28d6922..0000000000 --- a/runtime/interpreter/mterp/x86/op_iput_short_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_short_quick(): -% op_iput_quick(reg="rINSTw", store="movw") diff --git a/runtime/interpreter/mterp/x86/op_iput_wide.S b/runtime/interpreter/mterp/x86/op_iput_wide.S deleted file mode 100644 index 2f34fd39f9..0000000000 --- a/runtime/interpreter/mterp/x86/op_iput_wide.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_wide(): -% op_iput(helper="MterpIPutU64") diff --git a/runtime/interpreter/mterp/x86/op_iput_wide_quick.S b/runtime/interpreter/mterp/x86/op_iput_wide_quick.S deleted file mode 100644 index 6e1feefffc..0000000000 --- a/runtime/interpreter/mterp/x86/op_iput_wide_quick.S +++ /dev/null @@ -1,13 +0,0 @@ -%def op_iput_wide_quick(): - /* iput-wide-quick vA, vB, offset@CCCC */ - movzbl rINSTbl, %ecx # ecx<- BA - sarl $$4, %ecx # ecx<- B - GET_VREG %ecx, %ecx # vB (object we're operating on) - testl %ecx, %ecx # is object null? - je common_errNullObject - movzwl 2(rPC), %eax # eax<- field byte offset - leal (%ecx,%eax,1), %ecx # ecx<- Address of 64-bit target - andb $$0xf, rINSTbl # rINST<- A - GET_WIDE_FP_VREG %xmm0, rINST # xmm0<- fp[A]/fp[A+1] - movq %xmm0, (%ecx) # obj.field<- r0/r1 - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_long_to_double.S b/runtime/interpreter/mterp/x86/op_long_to_double.S deleted file mode 100644 index 858cb2e6b5..0000000000 --- a/runtime/interpreter/mterp/x86/op_long_to_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_long_to_double(): -% fpcvt(load="fildll", store="fstpl", wide="1") diff --git a/runtime/interpreter/mterp/x86/op_long_to_float.S b/runtime/interpreter/mterp/x86/op_long_to_float.S deleted file mode 100644 index b26085af31..0000000000 --- a/runtime/interpreter/mterp/x86/op_long_to_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_long_to_float(): -% fpcvt(load="fildll", store="fstps") diff --git a/runtime/interpreter/mterp/x86/op_long_to_int.S b/runtime/interpreter/mterp/x86/op_long_to_int.S deleted file mode 100644 index eacb8f59ec..0000000000 --- a/runtime/interpreter/mterp/x86/op_long_to_int.S +++ /dev/null @@ -1,3 +0,0 @@ -%def op_long_to_int(): -/* we ignore the high word, making this equivalent to a 32-bit reg move */ -% op_move() diff --git a/runtime/interpreter/mterp/x86/op_monitor_enter.S b/runtime/interpreter/mterp/x86/op_monitor_enter.S deleted file mode 100644 index d28ab4c307..0000000000 --- a/runtime/interpreter/mterp/x86/op_monitor_enter.S +++ /dev/null @@ -1,15 +0,0 @@ -%def op_monitor_enter(): -/* - * Synchronize on an object. - */ - /* monitor-enter vAA */ - EXPORT_PC - GET_VREG %ecx, rINST - movl %ecx, OUT_ARG0(%esp) - movl rSELF, %eax - movl %eax, OUT_ARG1(%esp) - call SYMBOL(artLockObjectFromCode) # (object, self) - RESTORE_IBASE - testb %al, %al - jnz MterpException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/op_monitor_exit.S b/runtime/interpreter/mterp/x86/op_monitor_exit.S deleted file mode 100644 index 63a8287519..0000000000 --- a/runtime/interpreter/mterp/x86/op_monitor_exit.S +++ /dev/null @@ -1,19 +0,0 @@ -%def op_monitor_exit(): -/* - * Unlock an object. - * - * Exceptions that occur when unlocking a monitor need to appear as - * if they happened at the following instruction. See the Dalvik - * instruction spec. - */ - /* monitor-exit vAA */ - EXPORT_PC - GET_VREG %ecx, rINST - movl %ecx, OUT_ARG0(%esp) - movl rSELF, %eax - movl %eax, OUT_ARG1(%esp) - call SYMBOL(artUnlockObjectFromCode) # (object, self) - RESTORE_IBASE - testb %al, %al - jnz MterpException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/op_move.S b/runtime/interpreter/mterp/x86/op_move.S deleted file mode 100644 index e02375596a..0000000000 --- a/runtime/interpreter/mterp/x86/op_move.S +++ /dev/null @@ -1,13 +0,0 @@ -%def op_move(is_object="0"): - /* for move, move-object, long-to-int */ - /* op vA, vB */ - movzbl rINSTbl, %eax # eax <- BA - andb $$0xf, %al # eax <- A - shrl $$4, rINST # rINST <- B - GET_VREG rINST, rINST - .if $is_object - SET_VREG_OBJECT rINST, %eax # fp[A] <- fp[B] - .else - SET_VREG rINST, %eax # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/op_move_16.S b/runtime/interpreter/mterp/x86/op_move_16.S deleted file mode 100644 index 0b4f8396f4..0000000000 --- a/runtime/interpreter/mterp/x86/op_move_16.S +++ /dev/null @@ -1,12 +0,0 @@ -%def op_move_16(is_object="0"): - /* for: move/16, move-object/16 */ - /* op vAAAA, vBBBB */ - movzwl 4(rPC), %ecx # ecx <- BBBB - movzwl 2(rPC), %eax # eax <- AAAA - GET_VREG rINST, %ecx - .if $is_object - SET_VREG_OBJECT rINST, %eax # fp[A] <- fp[B] - .else - SET_VREG rINST, %eax # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 diff --git a/runtime/interpreter/mterp/x86/op_move_exception.S b/runtime/interpreter/mterp/x86/op_move_exception.S deleted file mode 100644 index cadce40350..0000000000 --- a/runtime/interpreter/mterp/x86/op_move_exception.S +++ /dev/null @@ -1,7 +0,0 @@ -%def op_move_exception(): - /* move-exception vAA */ - movl rSELF, %ecx - movl THREAD_EXCEPTION_OFFSET(%ecx), %eax - SET_VREG_OBJECT %eax, rINST # fp[AA] <- exception object - movl $$0, THREAD_EXCEPTION_OFFSET(%ecx) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/op_move_from16.S b/runtime/interpreter/mterp/x86/op_move_from16.S deleted file mode 100644 index b8a9c8bceb..0000000000 --- a/runtime/interpreter/mterp/x86/op_move_from16.S +++ /dev/null @@ -1,12 +0,0 @@ -%def op_move_from16(is_object="0"): - /* for: move/from16, move-object/from16 */ - /* op vAA, vBBBB */ - movzx rINSTbl, %eax # eax <- AA - movw 2(rPC), rINSTw # rINSTw <- BBBB - GET_VREG rINST, rINST # rINST <- fp[BBBB] - .if $is_object - SET_VREG_OBJECT rINST, %eax # fp[A] <- fp[B] - .else - SET_VREG rINST, %eax # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_move_object.S b/runtime/interpreter/mterp/x86/op_move_object.S deleted file mode 100644 index dbb4d59710..0000000000 --- a/runtime/interpreter/mterp/x86/op_move_object.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_move_object(): -% op_move(is_object="1") diff --git a/runtime/interpreter/mterp/x86/op_move_object_16.S b/runtime/interpreter/mterp/x86/op_move_object_16.S deleted file mode 100644 index 40120379d5..0000000000 --- a/runtime/interpreter/mterp/x86/op_move_object_16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_move_object_16(): -% op_move_16(is_object="1") diff --git a/runtime/interpreter/mterp/x86/op_move_object_from16.S b/runtime/interpreter/mterp/x86/op_move_object_from16.S deleted file mode 100644 index c82698e81e..0000000000 --- a/runtime/interpreter/mterp/x86/op_move_object_from16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_move_object_from16(): -% op_move_from16(is_object="1") diff --git a/runtime/interpreter/mterp/x86/op_move_result.S b/runtime/interpreter/mterp/x86/op_move_result.S deleted file mode 100644 index c287faadf5..0000000000 --- a/runtime/interpreter/mterp/x86/op_move_result.S +++ /dev/null @@ -1,11 +0,0 @@ -%def op_move_result(is_object="0"): - /* for: move-result, move-result-object */ - /* op vAA */ - movl OFF_FP_RESULT_REGISTER(rFP), %eax # get pointer to result JType. - movl (%eax), %eax # r0 <- result.i. - .if $is_object - SET_VREG_OBJECT %eax, rINST # fp[A] <- fp[B] - .else - SET_VREG %eax, rINST # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/op_move_result_object.S b/runtime/interpreter/mterp/x86/op_move_result_object.S deleted file mode 100644 index 87aea2646a..0000000000 --- a/runtime/interpreter/mterp/x86/op_move_result_object.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_move_result_object(): -% op_move_result(is_object="1") diff --git a/runtime/interpreter/mterp/x86/op_move_result_wide.S b/runtime/interpreter/mterp/x86/op_move_result_wide.S deleted file mode 100644 index 68b1d803b0..0000000000 --- a/runtime/interpreter/mterp/x86/op_move_result_wide.S +++ /dev/null @@ -1,8 +0,0 @@ -%def op_move_result_wide(): - /* move-result-wide vAA */ - movl OFF_FP_RESULT_REGISTER(rFP), %eax # get pointer to result JType. - movl 4(%eax), %ecx # Get high - movl (%eax), %eax # Get low - SET_VREG %eax, rINST # v[AA+0] <- eax - SET_VREG_HIGH %ecx, rINST # v[AA+1] <- ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/op_move_wide.S b/runtime/interpreter/mterp/x86/op_move_wide.S deleted file mode 100644 index 0559d01f87..0000000000 --- a/runtime/interpreter/mterp/x86/op_move_wide.S +++ /dev/null @@ -1,9 +0,0 @@ -%def op_move_wide(): - /* move-wide vA, vB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $$4, rINST # rINST <- B - andb $$0xf, %cl # ecx <- A - GET_WIDE_FP_VREG %xmm0, rINST # xmm0 <- v[B] - SET_WIDE_FP_VREG %xmm0, %ecx # v[A] <- xmm0 - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/op_move_wide_16.S b/runtime/interpreter/mterp/x86/op_move_wide_16.S deleted file mode 100644 index 13a5e0d83a..0000000000 --- a/runtime/interpreter/mterp/x86/op_move_wide_16.S +++ /dev/null @@ -1,8 +0,0 @@ -%def op_move_wide_16(): - /* move-wide/16 vAAAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - movzwl 4(rPC), %ecx # ecx<- BBBB - movzwl 2(rPC), %eax # eax<- AAAA - GET_WIDE_FP_VREG %xmm0, %ecx # xmm0 <- v[B] - SET_WIDE_FP_VREG %xmm0, %eax # v[A] <- xmm0 - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 diff --git a/runtime/interpreter/mterp/x86/op_move_wide_from16.S b/runtime/interpreter/mterp/x86/op_move_wide_from16.S deleted file mode 100644 index 5380a8fa8a..0000000000 --- a/runtime/interpreter/mterp/x86/op_move_wide_from16.S +++ /dev/null @@ -1,8 +0,0 @@ -%def op_move_wide_from16(): - /* move-wide/from16 vAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - movzwl 2(rPC), %ecx # ecx <- BBBB - movzbl rINSTbl, %eax # eax <- AAAA - GET_WIDE_FP_VREG %xmm0, %ecx # xmm0 <- v[B] - SET_WIDE_FP_VREG %xmm0, %eax # v[A] <- xmm0 - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_mul_double.S b/runtime/interpreter/mterp/x86/op_mul_double.S deleted file mode 100644 index 5353028798..0000000000 --- a/runtime/interpreter/mterp/x86/op_mul_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_mul_double(): -% sseBinop(instr="muls", suff="d") diff --git a/runtime/interpreter/mterp/x86/op_mul_double_2addr.S b/runtime/interpreter/mterp/x86/op_mul_double_2addr.S deleted file mode 100644 index 7a6dcd0cb8..0000000000 --- a/runtime/interpreter/mterp/x86/op_mul_double_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_mul_double_2addr(): -% sseBinop2Addr(instr="muls", suff="d") diff --git a/runtime/interpreter/mterp/x86/op_mul_float.S b/runtime/interpreter/mterp/x86/op_mul_float.S deleted file mode 100644 index b9eeeeeb69..0000000000 --- a/runtime/interpreter/mterp/x86/op_mul_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_mul_float(): -% sseBinop(instr="muls", suff="s") diff --git a/runtime/interpreter/mterp/x86/op_mul_float_2addr.S b/runtime/interpreter/mterp/x86/op_mul_float_2addr.S deleted file mode 100644 index 949af7b254..0000000000 --- a/runtime/interpreter/mterp/x86/op_mul_float_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_mul_float_2addr(): -% sseBinop2Addr(instr="muls", suff="s") diff --git a/runtime/interpreter/mterp/x86/op_mul_int.S b/runtime/interpreter/mterp/x86/op_mul_int.S deleted file mode 100644 index 93884860d6..0000000000 --- a/runtime/interpreter/mterp/x86/op_mul_int.S +++ /dev/null @@ -1,13 +0,0 @@ -%def op_mul_int(): - /* - * 32-bit binary multiplication. - */ - /* mul vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB - mov rIBASE, LOCAL0(%esp) - imull (rFP,%ecx,4), %eax # trashes rIBASE/edx - mov LOCAL0(%esp), rIBASE - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_mul_int_2addr.S b/runtime/interpreter/mterp/x86/op_mul_int_2addr.S deleted file mode 100644 index 34e9b31bc6..0000000000 --- a/runtime/interpreter/mterp/x86/op_mul_int_2addr.S +++ /dev/null @@ -1,11 +0,0 @@ -%def op_mul_int_2addr(): - /* mul vA, vB */ - movzx rINSTbl, %ecx # ecx <- A+ - sarl $$4, rINST # rINST <- B - GET_VREG %eax, rINST # eax <- vB - andb $$0xf, %cl # ecx <- A - movl rIBASE, rINST - imull (rFP,%ecx,4), %eax # trashes rIBASE/edx - movl rINST, rIBASE - SET_VREG %eax, %ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/op_mul_int_lit16.S b/runtime/interpreter/mterp/x86/op_mul_int_lit16.S deleted file mode 100644 index 491fde41b0..0000000000 --- a/runtime/interpreter/mterp/x86/op_mul_int_lit16.S +++ /dev/null @@ -1,13 +0,0 @@ -%def op_mul_int_lit16(): - /* mul/lit16 vA, vB, #+CCCC */ - /* Need A in rINST, ssssCCCC in ecx, vB in eax */ - movzbl rINSTbl, %eax # eax <- 000000BA - sarl $$4, %eax # eax <- B - GET_VREG %eax, %eax # eax <- vB - movl rIBASE, %ecx - movswl 2(rPC), rIBASE # rIBASE <- ssssCCCC - andb $$0xf, rINSTbl # rINST <- A - imull rIBASE, %eax # trashes rIBASE/edx - movl %ecx, rIBASE - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_mul_int_lit8.S b/runtime/interpreter/mterp/x86/op_mul_int_lit8.S deleted file mode 100644 index d76973c776..0000000000 --- a/runtime/interpreter/mterp/x86/op_mul_int_lit8.S +++ /dev/null @@ -1,10 +0,0 @@ -%def op_mul_int_lit8(): - /* mul/lit8 vAA, vBB, #+CC */ - movzbl 2(rPC), %eax # eax <- BB - movl rIBASE, %ecx - GET_VREG %eax, %eax # eax <- rBB - movsbl 3(rPC), rIBASE # rIBASE <- ssssssCC - imull rIBASE, %eax # trashes rIBASE/edx - movl %ecx, rIBASE - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_mul_long.S b/runtime/interpreter/mterp/x86/op_mul_long.S deleted file mode 100644 index 0359272521..0000000000 --- a/runtime/interpreter/mterp/x86/op_mul_long.S +++ /dev/null @@ -1,34 +0,0 @@ -%def op_mul_long(): -/* - * Signed 64-bit integer multiply. - * - * We could definately use more free registers for - * this code. We spill rINSTw (ebx), - * giving us eax, ebc, ecx and edx as computational - * temps. On top of that, we'll spill edi (rFP) - * for use as the vB pointer and esi (rPC) for use - * as the vC pointer. Yuck. - * - */ - /* mul-long vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- B - movzbl 3(rPC), %ecx # ecx <- C - mov rPC, LOCAL0(%esp) # save Interpreter PC - mov rFP, LOCAL1(%esp) # save FP - mov rIBASE, LOCAL2(%esp) # save rIBASE - leal (rFP,%eax,4), %esi # esi <- &v[B] - leal (rFP,%ecx,4), rFP # rFP <- &v[C] - movl 4(%esi), %ecx # ecx <- Bmsw - imull (rFP), %ecx # ecx <- (Bmsw*Clsw) - movl 4(rFP), %eax # eax <- Cmsw - imull (%esi), %eax # eax <- (Cmsw*Blsw) - addl %eax, %ecx # ecx <- (Bmsw*Clsw)+(Cmsw*Blsw) - movl (rFP), %eax # eax <- Clsw - mull (%esi) # eax <- (Clsw*Alsw) - mov LOCAL0(%esp), rPC # restore Interpreter PC - mov LOCAL1(%esp), rFP # restore FP - leal (%ecx,rIBASE), rIBASE # full result now in rIBASE:%eax - SET_VREG_HIGH rIBASE, rINST # v[B+1] <- rIBASE - mov LOCAL2(%esp), rIBASE # restore IBASE - SET_VREG %eax, rINST # v[B] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_mul_long_2addr.S b/runtime/interpreter/mterp/x86/op_mul_long_2addr.S deleted file mode 100644 index b48f58d298..0000000000 --- a/runtime/interpreter/mterp/x86/op_mul_long_2addr.S +++ /dev/null @@ -1,36 +0,0 @@ -%def op_mul_long_2addr(): -/* - * Signed 64-bit integer multiply, 2-addr version - * - * We could definately use more free registers for - * this code. We must spill %edx (rIBASE) because it - * is used by imul. We'll also spill rINST (ebx), - * giving us eax, ebc, ecx and rIBASE as computational - * temps. On top of that, we'll spill %esi (edi) - * for use as the vA pointer and rFP (esi) for use - * as the vB pointer. Yuck. - */ - /* mul-long/2addr vA, vB */ - movzbl rINSTbl, %eax # eax <- BA - andb $$0xf, %al # eax <- A - CLEAR_WIDE_REF %eax # clear refs in advance - sarl $$4, rINST # rINST <- B - mov rPC, LOCAL0(%esp) # save Interpreter PC - mov rFP, LOCAL1(%esp) # save FP - mov rIBASE, LOCAL2(%esp) # save rIBASE - leal (rFP,%eax,4), %esi # esi <- &v[A] - leal (rFP,rINST,4), rFP # rFP <- &v[B] - movl 4(%esi), %ecx # ecx <- Amsw - imull (rFP), %ecx # ecx <- (Amsw*Blsw) - movl 4(rFP), %eax # eax <- Bmsw - imull (%esi), %eax # eax <- (Bmsw*Alsw) - addl %eax, %ecx # ecx <- (Amsw*Blsw)+(Bmsw*Alsw) - movl (rFP), %eax # eax <- Blsw - mull (%esi) # eax <- (Blsw*Alsw) - leal (%ecx,rIBASE), rIBASE # full result now in %edx:%eax - movl rIBASE, 4(%esi) # v[A+1] <- rIBASE - movl %eax, (%esi) # v[A] <- %eax - mov LOCAL0(%esp), rPC # restore Interpreter PC - mov LOCAL2(%esp), rIBASE # restore IBASE - mov LOCAL1(%esp), rFP # restore FP - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/op_neg_double.S b/runtime/interpreter/mterp/x86/op_neg_double.S deleted file mode 100644 index df290535e2..0000000000 --- a/runtime/interpreter/mterp/x86/op_neg_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_neg_double(): -% fpcvt(instr="fchs", load="fldl", store="fstpl", wide="1") diff --git a/runtime/interpreter/mterp/x86/op_neg_float.S b/runtime/interpreter/mterp/x86/op_neg_float.S deleted file mode 100644 index 0abe45c7cc..0000000000 --- a/runtime/interpreter/mterp/x86/op_neg_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_neg_float(): -% fpcvt(instr="fchs", load="flds", store="fstps") diff --git a/runtime/interpreter/mterp/x86/op_neg_int.S b/runtime/interpreter/mterp/x86/op_neg_int.S deleted file mode 100644 index 24604a9b0c..0000000000 --- a/runtime/interpreter/mterp/x86/op_neg_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_neg_int(): -% unop(instr="negl %eax") diff --git a/runtime/interpreter/mterp/x86/op_neg_long.S b/runtime/interpreter/mterp/x86/op_neg_long.S deleted file mode 100644 index 75f32798f4..0000000000 --- a/runtime/interpreter/mterp/x86/op_neg_long.S +++ /dev/null @@ -1,14 +0,0 @@ -%def op_neg_long(): - /* unop vA, vB */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $$4, %ecx # ecx <- B - andb $$0xf, rINSTbl # rINST <- A - GET_VREG %eax, %ecx # eax <- v[B+0] - GET_VREG_HIGH %ecx, %ecx # ecx <- v[B+1] - negl %eax - adcl $$0, %ecx - negl %ecx - SET_VREG %eax, rINST # v[A+0] <- eax - SET_VREG_HIGH %ecx, rINST # v[A+1] <- ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - diff --git a/runtime/interpreter/mterp/x86/op_new_array.S b/runtime/interpreter/mterp/x86/op_new_array.S deleted file mode 100644 index e59e106103..0000000000 --- a/runtime/interpreter/mterp/x86/op_new_array.S +++ /dev/null @@ -1,22 +0,0 @@ -%def op_new_array(): -/* - * Allocate an array of objects, specified with the array class - * and a count. - * - * The verifier guarantees that this is an array class, so we don't - * check for it here. - */ - /* new-array vA, vB, class@CCCC */ - EXPORT_PC - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG0(%esp) - movl rPC, OUT_ARG1(%esp) - REFRESH_INST ${opnum} - movl rINST, OUT_ARG2(%esp) - movl rSELF, %ecx - movl %ecx, OUT_ARG3(%esp) - call SYMBOL(MterpNewArray) - RESTORE_IBASE - testb %al, %al # 0 means an exception is thrown - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_new_instance.S b/runtime/interpreter/mterp/x86/op_new_instance.S deleted file mode 100644 index 81631c6ae7..0000000000 --- a/runtime/interpreter/mterp/x86/op_new_instance.S +++ /dev/null @@ -1,17 +0,0 @@ -%def op_new_instance(): -/* - * Create a new instance of a class. - */ - /* new-instance vAA, class@BBBB */ - EXPORT_PC - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG0(%esp) - movl rSELF, %ecx - movl %ecx, OUT_ARG1(%esp) - REFRESH_INST ${opnum} - movl rINST, OUT_ARG2(%esp) - call SYMBOL(MterpNewInstance) - RESTORE_IBASE - testb %al, %al # 0 means an exception is thrown - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_nop.S b/runtime/interpreter/mterp/x86/op_nop.S deleted file mode 100644 index aa4a843ab5..0000000000 --- a/runtime/interpreter/mterp/x86/op_nop.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_nop(): - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/op_not_int.S b/runtime/interpreter/mterp/x86/op_not_int.S deleted file mode 100644 index c95ac08d18..0000000000 --- a/runtime/interpreter/mterp/x86/op_not_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_not_int(): -% unop(instr="notl %eax") diff --git a/runtime/interpreter/mterp/x86/op_not_long.S b/runtime/interpreter/mterp/x86/op_not_long.S deleted file mode 100644 index c79f9d02f9..0000000000 --- a/runtime/interpreter/mterp/x86/op_not_long.S +++ /dev/null @@ -1,12 +0,0 @@ -%def op_not_long(): - /* unop vA, vB */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $$4, %ecx # ecx <- B - andb $$0xf, rINSTbl # rINST <- A - GET_VREG %eax, %ecx # eax <- v[B+0] - GET_VREG_HIGH %ecx, %ecx # ecx <- v[B+1] - notl %eax - notl %ecx - SET_VREG %eax, rINST # v[A+0] <- eax - SET_VREG_HIGH %ecx, rINST # v[A+1] <- ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/op_or_int.S b/runtime/interpreter/mterp/x86/op_or_int.S deleted file mode 100644 index f44ac0d604..0000000000 --- a/runtime/interpreter/mterp/x86/op_or_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_or_int(): -% binop(instr="orl (rFP,%ecx,4), %eax") diff --git a/runtime/interpreter/mterp/x86/op_or_int_2addr.S b/runtime/interpreter/mterp/x86/op_or_int_2addr.S deleted file mode 100644 index f0f278c3ce..0000000000 --- a/runtime/interpreter/mterp/x86/op_or_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_or_int_2addr(): -% binop2addr(instr="orl %eax, (rFP,%ecx,4)") diff --git a/runtime/interpreter/mterp/x86/op_or_int_lit16.S b/runtime/interpreter/mterp/x86/op_or_int_lit16.S deleted file mode 100644 index ba9b6bff18..0000000000 --- a/runtime/interpreter/mterp/x86/op_or_int_lit16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_or_int_lit16(): -% binopLit16(instr="orl %ecx, %eax") diff --git a/runtime/interpreter/mterp/x86/op_or_int_lit8.S b/runtime/interpreter/mterp/x86/op_or_int_lit8.S deleted file mode 100644 index 758109bc05..0000000000 --- a/runtime/interpreter/mterp/x86/op_or_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_or_int_lit8(): -% binopLit8(instr="orl %ecx, %eax") diff --git a/runtime/interpreter/mterp/x86/op_or_long.S b/runtime/interpreter/mterp/x86/op_or_long.S deleted file mode 100644 index 389081d6fb..0000000000 --- a/runtime/interpreter/mterp/x86/op_or_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_or_long(): -% binopWide(instr1="orl (rFP,%ecx,4), rIBASE", instr2="orl 4(rFP,%ecx,4), %eax") diff --git a/runtime/interpreter/mterp/x86/op_or_long_2addr.S b/runtime/interpreter/mterp/x86/op_or_long_2addr.S deleted file mode 100644 index 5beb9a2e01..0000000000 --- a/runtime/interpreter/mterp/x86/op_or_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_or_long_2addr(): -% binopWide2addr(instr1="orl %eax, (rFP,rINST,4)", instr2="orl %ecx, 4(rFP,rINST,4)") diff --git a/runtime/interpreter/mterp/x86/op_packed_switch.S b/runtime/interpreter/mterp/x86/op_packed_switch.S deleted file mode 100644 index b4c393fb84..0000000000 --- a/runtime/interpreter/mterp/x86/op_packed_switch.S +++ /dev/null @@ -1,21 +0,0 @@ -%def op_packed_switch(func="MterpDoPackedSwitch"): -/* - * Handle a packed-switch or sparse-switch instruction. In both cases - * we decode it and hand it off to a helper function. - * - * We don't really expect backward branches in a switch statement, but - * they're perfectly legal, so we check for them here. - * - * for: packed-switch, sparse-switch - */ - /* op vAA, +BBBB */ - movl 2(rPC), %ecx # ecx <- BBBBbbbb - GET_VREG %eax, rINST # eax <- vAA - leal (rPC,%ecx,2), %ecx # ecx <- PC + BBBBbbbb*2 - movl %eax, OUT_ARG1(%esp) # ARG1 <- vAA - movl %ecx, OUT_ARG0(%esp) # ARG0 <- switchData - call SYMBOL($func) - REFRESH_IBASE - testl %eax, %eax - movl %eax, rINST - jmp MterpCommonTakenBranch diff --git a/runtime/interpreter/mterp/x86/op_rem_double.S b/runtime/interpreter/mterp/x86/op_rem_double.S deleted file mode 100644 index df7b740576..0000000000 --- a/runtime/interpreter/mterp/x86/op_rem_double.S +++ /dev/null @@ -1,15 +0,0 @@ -%def op_rem_double(): - /* rem_double vAA, vBB, vCC */ - movzbl 3(rPC), %ecx # ecx <- BB - movzbl 2(rPC), %eax # eax <- CC - fldl VREG_ADDRESS(%ecx) # %st1 <- fp[vBB] - fldl VREG_ADDRESS(%eax) # %st0 <- fp[vCC] -1: - fprem - fstsw %ax - sahf - jp 1b - fstp %st(1) - fstpl VREG_ADDRESS(rINST) # fp[vAA] <- %st - CLEAR_WIDE_REF rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_rem_double_2addr.S b/runtime/interpreter/mterp/x86/op_rem_double_2addr.S deleted file mode 100644 index fb4e393700..0000000000 --- a/runtime/interpreter/mterp/x86/op_rem_double_2addr.S +++ /dev/null @@ -1,16 +0,0 @@ -%def op_rem_double_2addr(): - /* rem_double/2addr vA, vB */ - movzx rINSTbl, %ecx # ecx <- A+ - sarl $$4, rINST # rINST <- B - fldl VREG_ADDRESS(rINST) # vB to fp stack - andb $$0xf, %cl # ecx <- A - fldl VREG_ADDRESS(%ecx) # vA to fp stack -1: - fprem - fstsw %ax - sahf - jp 1b - fstp %st(1) - fstpl VREG_ADDRESS(%ecx) # %st to vA - CLEAR_WIDE_REF %ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/op_rem_float.S b/runtime/interpreter/mterp/x86/op_rem_float.S deleted file mode 100644 index 9b436f2759..0000000000 --- a/runtime/interpreter/mterp/x86/op_rem_float.S +++ /dev/null @@ -1,15 +0,0 @@ -%def op_rem_float(): - /* rem_float vAA, vBB, vCC */ - movzbl 3(rPC), %ecx # ecx <- BB - movzbl 2(rPC), %eax # eax <- CC - flds VREG_ADDRESS(%ecx) # vBB to fp stack - flds VREG_ADDRESS(%eax) # vCC to fp stack -1: - fprem - fstsw %ax - sahf - jp 1b - fstp %st(1) - fstps VREG_ADDRESS(rINST) # %st to vAA - CLEAR_REF rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_rem_float_2addr.S b/runtime/interpreter/mterp/x86/op_rem_float_2addr.S deleted file mode 100644 index 81d44c8b14..0000000000 --- a/runtime/interpreter/mterp/x86/op_rem_float_2addr.S +++ /dev/null @@ -1,16 +0,0 @@ -%def op_rem_float_2addr(): - /* rem_float/2addr vA, vB */ - movzx rINSTbl, %ecx # ecx <- A+ - sarl $$4, rINST # rINST <- B - flds VREG_ADDRESS(rINST) # vB to fp stack - andb $$0xf, %cl # ecx <- A - flds VREG_ADDRESS(%ecx) # vA to fp stack -1: - fprem - fstsw %ax - sahf - jp 1b - fstp %st(1) - fstps VREG_ADDRESS(%ecx) # %st to vA - CLEAR_REF %ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/op_rem_int.S b/runtime/interpreter/mterp/x86/op_rem_int.S deleted file mode 100644 index 71da7b81db..0000000000 --- a/runtime/interpreter/mterp/x86/op_rem_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_rem_int(): -% bindiv(result="rIBASE", special="$0", rem="1") diff --git a/runtime/interpreter/mterp/x86/op_rem_int_2addr.S b/runtime/interpreter/mterp/x86/op_rem_int_2addr.S deleted file mode 100644 index f58f4ac73f..0000000000 --- a/runtime/interpreter/mterp/x86/op_rem_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_rem_int_2addr(): -% bindiv2addr(result="rIBASE", special="$0") diff --git a/runtime/interpreter/mterp/x86/op_rem_int_lit16.S b/runtime/interpreter/mterp/x86/op_rem_int_lit16.S deleted file mode 100644 index 8915740c04..0000000000 --- a/runtime/interpreter/mterp/x86/op_rem_int_lit16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_rem_int_lit16(): -% bindivLit16(result="rIBASE", special="$0") diff --git a/runtime/interpreter/mterp/x86/op_rem_int_lit8.S b/runtime/interpreter/mterp/x86/op_rem_int_lit8.S deleted file mode 100644 index 88369def7f..0000000000 --- a/runtime/interpreter/mterp/x86/op_rem_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_rem_int_lit8(): -% bindivLit8(result="rIBASE", special="$0") diff --git a/runtime/interpreter/mterp/x86/op_rem_long.S b/runtime/interpreter/mterp/x86/op_rem_long.S deleted file mode 100644 index ef23c05ed8..0000000000 --- a/runtime/interpreter/mterp/x86/op_rem_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_rem_long(): -% op_div_long(routine="art_quick_lmod") diff --git a/runtime/interpreter/mterp/x86/op_rem_long_2addr.S b/runtime/interpreter/mterp/x86/op_rem_long_2addr.S deleted file mode 100644 index f6a8ec36a2..0000000000 --- a/runtime/interpreter/mterp/x86/op_rem_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_rem_long_2addr(): -% op_div_long_2addr(routine="art_quick_lmod") diff --git a/runtime/interpreter/mterp/x86/op_return.S b/runtime/interpreter/mterp/x86/op_return.S deleted file mode 100644 index 0fdd6f51c8..0000000000 --- a/runtime/interpreter/mterp/x86/op_return.S +++ /dev/null @@ -1,18 +0,0 @@ -%def op_return(): -/* - * Return a 32-bit value. - * - * for: return, return-object - */ - /* op vAA */ - .extern MterpThreadFenceForConstructor - call SYMBOL(MterpThreadFenceForConstructor) - movl rSELF, %eax - testl $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(%eax) - jz 1f - movl %eax, OUT_ARG0(%esp) - call SYMBOL(MterpSuspendCheck) -1: - GET_VREG %eax, rINST # eax <- vAA - xorl %ecx, %ecx - jmp MterpReturn diff --git a/runtime/interpreter/mterp/x86/op_return_object.S b/runtime/interpreter/mterp/x86/op_return_object.S deleted file mode 100644 index 2eeec0b948..0000000000 --- a/runtime/interpreter/mterp/x86/op_return_object.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_return_object(): -% op_return() diff --git a/runtime/interpreter/mterp/x86/op_return_void.S b/runtime/interpreter/mterp/x86/op_return_void.S deleted file mode 100644 index 3eb5b6602e..0000000000 --- a/runtime/interpreter/mterp/x86/op_return_void.S +++ /dev/null @@ -1,12 +0,0 @@ -%def op_return_void(): - .extern MterpThreadFenceForConstructor - call SYMBOL(MterpThreadFenceForConstructor) - movl rSELF, %eax - testl $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(%eax) - jz 1f - movl %eax, OUT_ARG0(%esp) - call SYMBOL(MterpSuspendCheck) -1: - xorl %eax, %eax - xorl %ecx, %ecx - jmp MterpReturn diff --git a/runtime/interpreter/mterp/x86/op_return_void_no_barrier.S b/runtime/interpreter/mterp/x86/op_return_void_no_barrier.S deleted file mode 100644 index eadd522299..0000000000 --- a/runtime/interpreter/mterp/x86/op_return_void_no_barrier.S +++ /dev/null @@ -1,10 +0,0 @@ -%def op_return_void_no_barrier(): - movl rSELF, %eax - testl $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(%eax) - jz 1f - movl %eax, OUT_ARG0(%esp) - call SYMBOL(MterpSuspendCheck) -1: - xorl %eax, %eax - xorl %ecx, %ecx - jmp MterpReturn diff --git a/runtime/interpreter/mterp/x86/op_return_wide.S b/runtime/interpreter/mterp/x86/op_return_wide.S deleted file mode 100644 index 67a103dac6..0000000000 --- a/runtime/interpreter/mterp/x86/op_return_wide.S +++ /dev/null @@ -1,16 +0,0 @@ -%def op_return_wide(): -/* - * Return a 64-bit value. - */ - /* return-wide vAA */ - .extern MterpThreadFenceForConstructor - call SYMBOL(MterpThreadFenceForConstructor) - movl rSELF, %eax - testl $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(%eax) - jz 1f - movl %eax, OUT_ARG0(%esp) - call SYMBOL(MterpSuspendCheck) -1: - GET_VREG %eax, rINST # eax <- v[AA+0] - GET_VREG_HIGH %ecx, rINST # ecx <- v[AA+1] - jmp MterpReturn diff --git a/runtime/interpreter/mterp/x86/op_rsub_int.S b/runtime/interpreter/mterp/x86/op_rsub_int.S deleted file mode 100644 index 05ba130f2f..0000000000 --- a/runtime/interpreter/mterp/x86/op_rsub_int.S +++ /dev/null @@ -1,3 +0,0 @@ -%def op_rsub_int(): -/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ -% binopLit16(instr="subl %eax, %ecx", result="%ecx") diff --git a/runtime/interpreter/mterp/x86/op_rsub_int_lit8.S b/runtime/interpreter/mterp/x86/op_rsub_int_lit8.S deleted file mode 100644 index d0230476d7..0000000000 --- a/runtime/interpreter/mterp/x86/op_rsub_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_rsub_int_lit8(): -% binopLit8(instr="subl %eax, %ecx", result="%ecx") diff --git a/runtime/interpreter/mterp/x86/op_sget.S b/runtime/interpreter/mterp/x86/op_sget.S deleted file mode 100644 index 8a6a66ab60..0000000000 --- a/runtime/interpreter/mterp/x86/op_sget.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sget(is_object="0", helper="MterpSGetU32"): -% field(helper=helper) diff --git a/runtime/interpreter/mterp/x86/op_sget_boolean.S b/runtime/interpreter/mterp/x86/op_sget_boolean.S deleted file mode 100644 index d9c12c9b28..0000000000 --- a/runtime/interpreter/mterp/x86/op_sget_boolean.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sget_boolean(): -% op_sget(helper="MterpSGetU8") diff --git a/runtime/interpreter/mterp/x86/op_sget_byte.S b/runtime/interpreter/mterp/x86/op_sget_byte.S deleted file mode 100644 index 37c6879cd4..0000000000 --- a/runtime/interpreter/mterp/x86/op_sget_byte.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sget_byte(): -% op_sget(helper="MterpSGetI8") diff --git a/runtime/interpreter/mterp/x86/op_sget_char.S b/runtime/interpreter/mterp/x86/op_sget_char.S deleted file mode 100644 index 003bcd1683..0000000000 --- a/runtime/interpreter/mterp/x86/op_sget_char.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sget_char(): -% op_sget(helper="MterpSGetU16") diff --git a/runtime/interpreter/mterp/x86/op_sget_object.S b/runtime/interpreter/mterp/x86/op_sget_object.S deleted file mode 100644 index 7cf3597f44..0000000000 --- a/runtime/interpreter/mterp/x86/op_sget_object.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sget_object(): -% op_sget(is_object="1", helper="MterpSGetObj") diff --git a/runtime/interpreter/mterp/x86/op_sget_short.S b/runtime/interpreter/mterp/x86/op_sget_short.S deleted file mode 100644 index afacb578d9..0000000000 --- a/runtime/interpreter/mterp/x86/op_sget_short.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sget_short(): -% op_sget(helper="MterpSGetI16") diff --git a/runtime/interpreter/mterp/x86/op_sget_wide.S b/runtime/interpreter/mterp/x86/op_sget_wide.S deleted file mode 100644 index fff2be6945..0000000000 --- a/runtime/interpreter/mterp/x86/op_sget_wide.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sget_wide(): -% op_sget(helper="MterpSGetU64") diff --git a/runtime/interpreter/mterp/x86/op_shl_int.S b/runtime/interpreter/mterp/x86/op_shl_int.S deleted file mode 100644 index a98b256120..0000000000 --- a/runtime/interpreter/mterp/x86/op_shl_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shl_int(): -% binop1(instr="sall %cl, %eax") diff --git a/runtime/interpreter/mterp/x86/op_shl_int_2addr.S b/runtime/interpreter/mterp/x86/op_shl_int_2addr.S deleted file mode 100644 index 987c7d1e28..0000000000 --- a/runtime/interpreter/mterp/x86/op_shl_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shl_int_2addr(): -% shop2addr(instr="sall %cl, %eax") diff --git a/runtime/interpreter/mterp/x86/op_shl_int_lit8.S b/runtime/interpreter/mterp/x86/op_shl_int_lit8.S deleted file mode 100644 index ee1a15e696..0000000000 --- a/runtime/interpreter/mterp/x86/op_shl_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shl_int_lit8(): -% binopLit8(instr="sall %cl, %eax") diff --git a/runtime/interpreter/mterp/x86/op_shl_long.S b/runtime/interpreter/mterp/x86/op_shl_long.S deleted file mode 100644 index d45705a6ad..0000000000 --- a/runtime/interpreter/mterp/x86/op_shl_long.S +++ /dev/null @@ -1,30 +0,0 @@ -%def op_shl_long(): -/* - * Long integer shift. This is different from the generic 32/64-bit - * binary operations because vAA/vBB are 64-bit but vCC (the shift - * distance) is 32-bit. Also, Dalvik requires us to mask off the low - * 6 bits of the shift distance. x86 shifts automatically mask off - * the low 5 bits of %cl, so have to handle the 64 > shiftcount > 31 - * case specially. - */ - /* shl-long vAA, vBB, vCC */ - /* ecx gets shift count */ - /* Need to spill rINST */ - /* rINSTw gets AA */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - movl rIBASE, LOCAL0(%esp) - GET_VREG_HIGH rIBASE, %eax # ecx <- v[BB+1] - GET_VREG %ecx, %ecx # ecx <- vCC - GET_VREG %eax, %eax # eax <- v[BB+0] - shldl %eax,rIBASE - sall %cl, %eax - testb $$32, %cl - je 2f - movl %eax, rIBASE - xorl %eax, %eax -2: - SET_VREG_HIGH rIBASE, rINST # v[AA+1] <- rIBASE - movl LOCAL0(%esp), rIBASE - SET_VREG %eax, rINST # v[AA+0] <- %eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_shl_long_2addr.S b/runtime/interpreter/mterp/x86/op_shl_long_2addr.S deleted file mode 100644 index 7d40f56cc0..0000000000 --- a/runtime/interpreter/mterp/x86/op_shl_long_2addr.S +++ /dev/null @@ -1,27 +0,0 @@ -%def op_shl_long_2addr(): -/* - * Long integer shift, 2addr version. vA is 64-bit value/result, vB is - * 32-bit shift distance. - */ - /* shl-long/2addr vA, vB */ - /* ecx gets shift count */ - /* Need to spill rIBASE */ - /* rINSTw gets AA */ - movzbl rINSTbl, %ecx # ecx <- BA - andb $$0xf, rINSTbl # rINST <- A - GET_VREG %eax, rINST # eax <- v[AA+0] - sarl $$4, %ecx # ecx <- B - movl rIBASE, LOCAL0(%esp) - GET_VREG_HIGH rIBASE, rINST # rIBASE <- v[AA+1] - GET_VREG %ecx, %ecx # ecx <- vBB - shldl %eax, rIBASE - sall %cl, %eax - testb $$32, %cl - je 2f - movl %eax, rIBASE - xorl %eax, %eax -2: - SET_VREG_HIGH rIBASE, rINST # v[AA+1] <- rIBASE - movl LOCAL0(%esp), rIBASE - SET_VREG %eax, rINST # v[AA+0] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/op_shr_int.S b/runtime/interpreter/mterp/x86/op_shr_int.S deleted file mode 100644 index 4d4d79cc09..0000000000 --- a/runtime/interpreter/mterp/x86/op_shr_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shr_int(): -% binop1(instr="sarl %cl, %eax") diff --git a/runtime/interpreter/mterp/x86/op_shr_int_2addr.S b/runtime/interpreter/mterp/x86/op_shr_int_2addr.S deleted file mode 100644 index 8e4b055e15..0000000000 --- a/runtime/interpreter/mterp/x86/op_shr_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shr_int_2addr(): -% shop2addr(instr="sarl %cl, %eax") diff --git a/runtime/interpreter/mterp/x86/op_shr_int_lit8.S b/runtime/interpreter/mterp/x86/op_shr_int_lit8.S deleted file mode 100644 index a7acf5f384..0000000000 --- a/runtime/interpreter/mterp/x86/op_shr_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shr_int_lit8(): -% binopLit8(instr="sarl %cl, %eax") diff --git a/runtime/interpreter/mterp/x86/op_shr_long.S b/runtime/interpreter/mterp/x86/op_shr_long.S deleted file mode 100644 index 3b859411ae..0000000000 --- a/runtime/interpreter/mterp/x86/op_shr_long.S +++ /dev/null @@ -1,30 +0,0 @@ -%def op_shr_long(): -/* - * Long integer shift. This is different from the generic 32/64-bit - * binary operations because vAA/vBB are 64-bit but vCC (the shift - * distance) is 32-bit. Also, Dalvik requires us to mask off the low - * 6 bits of the shift distance. x86 shifts automatically mask off - * the low 5 bits of %cl, so have to handle the 64 > shiftcount > 31 - * case specially. - */ - /* shr-long vAA, vBB, vCC */ - /* ecx gets shift count */ - /* Need to spill rIBASE */ - /* rINSTw gets AA */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - movl rIBASE, LOCAL0(%esp) - GET_VREG_HIGH rIBASE, %eax # rIBASE<- v[BB+1] - GET_VREG %ecx, %ecx # ecx <- vCC - GET_VREG %eax, %eax # eax <- v[BB+0] - shrdl rIBASE, %eax - sarl %cl, rIBASE - testb $$32, %cl - je 2f - movl rIBASE, %eax - sarl $$31, rIBASE -2: - SET_VREG_HIGH rIBASE, rINST # v[AA+1] <- rIBASE - movl LOCAL0(%esp), rIBASE - SET_VREG %eax, rINST # v[AA+0] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_shr_long_2addr.S b/runtime/interpreter/mterp/x86/op_shr_long_2addr.S deleted file mode 100644 index 6427dedbf4..0000000000 --- a/runtime/interpreter/mterp/x86/op_shr_long_2addr.S +++ /dev/null @@ -1,27 +0,0 @@ -%def op_shr_long_2addr(): -/* - * Long integer shift, 2addr version. vA is 64-bit value/result, vB is - * 32-bit shift distance. - */ - /* shl-long/2addr vA, vB */ - /* ecx gets shift count */ - /* Need to spill rIBASE */ - /* rINSTw gets AA */ - movzbl rINSTbl, %ecx # ecx <- BA - andb $$0xf, rINSTbl # rINST <- A - GET_VREG %eax, rINST # eax <- v[AA+0] - sarl $$4, %ecx # ecx <- B - movl rIBASE, LOCAL0(%esp) - GET_VREG_HIGH rIBASE, rINST # rIBASE <- v[AA+1] - GET_VREG %ecx, %ecx # ecx <- vBB - shrdl rIBASE, %eax - sarl %cl, rIBASE - testb $$32, %cl - je 2f - movl rIBASE, %eax - sarl $$31, rIBASE -2: - SET_VREG_HIGH rIBASE, rINST # v[AA+1] <- rIBASE - movl LOCAL0(%esp), rIBASE - SET_VREG %eax, rINST # v[AA+0] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/op_sparse_switch.S b/runtime/interpreter/mterp/x86/op_sparse_switch.S deleted file mode 100644 index b74d7da816..0000000000 --- a/runtime/interpreter/mterp/x86/op_sparse_switch.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sparse_switch(): -% op_packed_switch(func="MterpDoSparseSwitch") diff --git a/runtime/interpreter/mterp/x86/op_sput.S b/runtime/interpreter/mterp/x86/op_sput.S deleted file mode 100644 index cbd6ee96d3..0000000000 --- a/runtime/interpreter/mterp/x86/op_sput.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sput(is_object="0", helper="MterpSPutU32"): -% field(helper=helper) diff --git a/runtime/interpreter/mterp/x86/op_sput_boolean.S b/runtime/interpreter/mterp/x86/op_sput_boolean.S deleted file mode 100644 index 36fba8448b..0000000000 --- a/runtime/interpreter/mterp/x86/op_sput_boolean.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sput_boolean(): -% op_sput(helper="MterpSPutU8") diff --git a/runtime/interpreter/mterp/x86/op_sput_byte.S b/runtime/interpreter/mterp/x86/op_sput_byte.S deleted file mode 100644 index 84ad4a0ff8..0000000000 --- a/runtime/interpreter/mterp/x86/op_sput_byte.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sput_byte(): -% op_sput(helper="MterpSPutI8") diff --git a/runtime/interpreter/mterp/x86/op_sput_char.S b/runtime/interpreter/mterp/x86/op_sput_char.S deleted file mode 100644 index 9b8eeba578..0000000000 --- a/runtime/interpreter/mterp/x86/op_sput_char.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sput_char(): -% op_sput(helper="MterpSPutU16") diff --git a/runtime/interpreter/mterp/x86/op_sput_object.S b/runtime/interpreter/mterp/x86/op_sput_object.S deleted file mode 100644 index 081360c40f..0000000000 --- a/runtime/interpreter/mterp/x86/op_sput_object.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sput_object(): -% op_sput(is_object="1", helper="MterpSPutObj") diff --git a/runtime/interpreter/mterp/x86/op_sput_short.S b/runtime/interpreter/mterp/x86/op_sput_short.S deleted file mode 100644 index ee16513486..0000000000 --- a/runtime/interpreter/mterp/x86/op_sput_short.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sput_short(): -% op_sput(helper="MterpSPutI16") diff --git a/runtime/interpreter/mterp/x86/op_sput_wide.S b/runtime/interpreter/mterp/x86/op_sput_wide.S deleted file mode 100644 index 44c1a188ed..0000000000 --- a/runtime/interpreter/mterp/x86/op_sput_wide.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sput_wide(): -% op_sput(helper="MterpSPutU64") diff --git a/runtime/interpreter/mterp/x86/op_sub_double.S b/runtime/interpreter/mterp/x86/op_sub_double.S deleted file mode 100644 index 64a28c376b..0000000000 --- a/runtime/interpreter/mterp/x86/op_sub_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_double(): -% sseBinop(instr="subs", suff="d") diff --git a/runtime/interpreter/mterp/x86/op_sub_double_2addr.S b/runtime/interpreter/mterp/x86/op_sub_double_2addr.S deleted file mode 100644 index 753074bd37..0000000000 --- a/runtime/interpreter/mterp/x86/op_sub_double_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_double_2addr(): -% sseBinop2Addr(instr="subs", suff="d") diff --git a/runtime/interpreter/mterp/x86/op_sub_float.S b/runtime/interpreter/mterp/x86/op_sub_float.S deleted file mode 100644 index 1a1966dba2..0000000000 --- a/runtime/interpreter/mterp/x86/op_sub_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_float(): -% sseBinop(instr="subs", suff="s") diff --git a/runtime/interpreter/mterp/x86/op_sub_float_2addr.S b/runtime/interpreter/mterp/x86/op_sub_float_2addr.S deleted file mode 100644 index 9557907bd2..0000000000 --- a/runtime/interpreter/mterp/x86/op_sub_float_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_float_2addr(): -% sseBinop2Addr(instr="subs", suff="s") diff --git a/runtime/interpreter/mterp/x86/op_sub_int.S b/runtime/interpreter/mterp/x86/op_sub_int.S deleted file mode 100644 index 289d241acc..0000000000 --- a/runtime/interpreter/mterp/x86/op_sub_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_int(): -% binop(instr="subl (rFP,%ecx,4), %eax") diff --git a/runtime/interpreter/mterp/x86/op_sub_int_2addr.S b/runtime/interpreter/mterp/x86/op_sub_int_2addr.S deleted file mode 100644 index b55f8874d9..0000000000 --- a/runtime/interpreter/mterp/x86/op_sub_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_int_2addr(): -% binop2addr(instr="subl %eax, (rFP,%ecx,4)") diff --git a/runtime/interpreter/mterp/x86/op_sub_long.S b/runtime/interpreter/mterp/x86/op_sub_long.S deleted file mode 100644 index d45c9a7846..0000000000 --- a/runtime/interpreter/mterp/x86/op_sub_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_long(): -% binopWide(instr1="subl (rFP,%ecx,4), rIBASE", instr2="sbbl 4(rFP,%ecx,4), %eax") diff --git a/runtime/interpreter/mterp/x86/op_sub_long_2addr.S b/runtime/interpreter/mterp/x86/op_sub_long_2addr.S deleted file mode 100644 index 615b535ef4..0000000000 --- a/runtime/interpreter/mterp/x86/op_sub_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_long_2addr(): -% binopWide2addr(instr1="subl %eax, (rFP,rINST,4)", instr2="sbbl %ecx, 4(rFP,rINST,4)") diff --git a/runtime/interpreter/mterp/x86/op_throw.S b/runtime/interpreter/mterp/x86/op_throw.S deleted file mode 100644 index fa4a9d02a7..0000000000 --- a/runtime/interpreter/mterp/x86/op_throw.S +++ /dev/null @@ -1,12 +0,0 @@ -%def op_throw(): -/* - * Throw an exception object in the current thread. - */ - /* throw vAA */ - EXPORT_PC - GET_VREG %eax, rINST # eax<- vAA (exception object) - testl %eax, %eax - jz common_errNullObject - movl rSELF,%ecx - movl %eax, THREAD_EXCEPTION_OFFSET(%ecx) - jmp MterpException diff --git a/runtime/interpreter/mterp/x86/op_unused_3e.S b/runtime/interpreter/mterp/x86/op_unused_3e.S deleted file mode 100644 index d889f1a5fb..0000000000 --- a/runtime/interpreter/mterp/x86/op_unused_3e.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_3e(): -% unused() diff --git a/runtime/interpreter/mterp/x86/op_unused_3f.S b/runtime/interpreter/mterp/x86/op_unused_3f.S deleted file mode 100644 index b3ebcfaeaa..0000000000 --- a/runtime/interpreter/mterp/x86/op_unused_3f.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_3f(): -% unused() diff --git a/runtime/interpreter/mterp/x86/op_unused_40.S b/runtime/interpreter/mterp/x86/op_unused_40.S deleted file mode 100644 index 7920fb350f..0000000000 --- a/runtime/interpreter/mterp/x86/op_unused_40.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_40(): -% unused() diff --git a/runtime/interpreter/mterp/x86/op_unused_41.S b/runtime/interpreter/mterp/x86/op_unused_41.S deleted file mode 100644 index 5ed03b8506..0000000000 --- a/runtime/interpreter/mterp/x86/op_unused_41.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_41(): -% unused() diff --git a/runtime/interpreter/mterp/x86/op_unused_42.S b/runtime/interpreter/mterp/x86/op_unused_42.S deleted file mode 100644 index ac32521add..0000000000 --- a/runtime/interpreter/mterp/x86/op_unused_42.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_42(): -% unused() diff --git a/runtime/interpreter/mterp/x86/op_unused_43.S b/runtime/interpreter/mterp/x86/op_unused_43.S deleted file mode 100644 index 33e2aa10f8..0000000000 --- a/runtime/interpreter/mterp/x86/op_unused_43.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_43(): -% unused() diff --git a/runtime/interpreter/mterp/x86/op_unused_79.S b/runtime/interpreter/mterp/x86/op_unused_79.S deleted file mode 100644 index 3c6dafc789..0000000000 --- a/runtime/interpreter/mterp/x86/op_unused_79.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_79(): -% unused() diff --git a/runtime/interpreter/mterp/x86/op_unused_7a.S b/runtime/interpreter/mterp/x86/op_unused_7a.S deleted file mode 100644 index 9c03cd5535..0000000000 --- a/runtime/interpreter/mterp/x86/op_unused_7a.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_7a(): -% unused() diff --git a/runtime/interpreter/mterp/x86/op_unused_f3.S b/runtime/interpreter/mterp/x86/op_unused_f3.S deleted file mode 100644 index ab10b78be2..0000000000 --- a/runtime/interpreter/mterp/x86/op_unused_f3.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_f3(): -% unused() diff --git a/runtime/interpreter/mterp/x86/op_unused_f4.S b/runtime/interpreter/mterp/x86/op_unused_f4.S deleted file mode 100644 index 09229d6d99..0000000000 --- a/runtime/interpreter/mterp/x86/op_unused_f4.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_f4(): -% unused() diff --git a/runtime/interpreter/mterp/x86/op_unused_f5.S b/runtime/interpreter/mterp/x86/op_unused_f5.S deleted file mode 100644 index 0d6149b5fd..0000000000 --- a/runtime/interpreter/mterp/x86/op_unused_f5.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_f5(): -% unused() diff --git a/runtime/interpreter/mterp/x86/op_unused_f6.S b/runtime/interpreter/mterp/x86/op_unused_f6.S deleted file mode 100644 index 117b03de6d..0000000000 --- a/runtime/interpreter/mterp/x86/op_unused_f6.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_f6(): -% unused() diff --git a/runtime/interpreter/mterp/x86/op_unused_f7.S b/runtime/interpreter/mterp/x86/op_unused_f7.S deleted file mode 100644 index 4e3a0f3c9a..0000000000 --- a/runtime/interpreter/mterp/x86/op_unused_f7.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_f7(): -% unused() diff --git a/runtime/interpreter/mterp/x86/op_unused_f8.S b/runtime/interpreter/mterp/x86/op_unused_f8.S deleted file mode 100644 index d1220752d7..0000000000 --- a/runtime/interpreter/mterp/x86/op_unused_f8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_f8(): -% unused() diff --git a/runtime/interpreter/mterp/x86/op_unused_f9.S b/runtime/interpreter/mterp/x86/op_unused_f9.S deleted file mode 100644 index 7d09a0ebcf..0000000000 --- a/runtime/interpreter/mterp/x86/op_unused_f9.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_f9(): -% unused() diff --git a/runtime/interpreter/mterp/x86/op_unused_fc.S b/runtime/interpreter/mterp/x86/op_unused_fc.S deleted file mode 100644 index 06978191eb..0000000000 --- a/runtime/interpreter/mterp/x86/op_unused_fc.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_fc(): -% unused() diff --git a/runtime/interpreter/mterp/x86/op_unused_fd.S b/runtime/interpreter/mterp/x86/op_unused_fd.S deleted file mode 100644 index 4bc2b4bdb6..0000000000 --- a/runtime/interpreter/mterp/x86/op_unused_fd.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_fd(): -% unused() diff --git a/runtime/interpreter/mterp/x86/op_ushr_int.S b/runtime/interpreter/mterp/x86/op_ushr_int.S deleted file mode 100644 index 38c8782ca9..0000000000 --- a/runtime/interpreter/mterp/x86/op_ushr_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_ushr_int(): -% binop1(instr="shrl %cl, %eax") diff --git a/runtime/interpreter/mterp/x86/op_ushr_int_2addr.S b/runtime/interpreter/mterp/x86/op_ushr_int_2addr.S deleted file mode 100644 index f1da71a47a..0000000000 --- a/runtime/interpreter/mterp/x86/op_ushr_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_ushr_int_2addr(): -% shop2addr(instr="shrl %cl, %eax") diff --git a/runtime/interpreter/mterp/x86/op_ushr_int_lit8.S b/runtime/interpreter/mterp/x86/op_ushr_int_lit8.S deleted file mode 100644 index 4298d36c3d..0000000000 --- a/runtime/interpreter/mterp/x86/op_ushr_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_ushr_int_lit8(): -% binopLit8(instr="shrl %cl, %eax") diff --git a/runtime/interpreter/mterp/x86/op_ushr_long.S b/runtime/interpreter/mterp/x86/op_ushr_long.S deleted file mode 100644 index 5837a9a792..0000000000 --- a/runtime/interpreter/mterp/x86/op_ushr_long.S +++ /dev/null @@ -1,30 +0,0 @@ -%def op_ushr_long(): -/* - * Long integer shift. This is different from the generic 32/64-bit - * binary operations because vAA/vBB are 64-bit but vCC (the shift - * distance) is 32-bit. Also, Dalvik requires us to mask off the low - * 6 bits of the shift distance. x86 shifts automatically mask off - * the low 5 bits of %cl, so have to handle the 64 > shiftcount > 31 - * case specially. - */ - /* shr-long vAA, vBB, vCC */ - /* ecx gets shift count */ - /* Need to spill rIBASE */ - /* rINSTw gets AA */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - movl rIBASE, LOCAL0(%esp) - GET_VREG_HIGH rIBASE, %eax # rIBASE <- v[BB+1] - GET_VREG %ecx, %ecx # ecx <- vCC - GET_VREG %eax, %eax # eax <- v[BB+0] - shrdl rIBASE, %eax - shrl %cl, rIBASE - testb $$32, %cl - je 2f - movl rIBASE, %eax - xorl rIBASE, rIBASE -2: - SET_VREG_HIGH rIBASE, rINST # v[AA+1] <- rIBASE - movl LOCAL0(%esp), rIBASE - SET_VREG %eax, rINST # v[BB+0] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_ushr_long_2addr.S b/runtime/interpreter/mterp/x86/op_ushr_long_2addr.S deleted file mode 100644 index f07318aeb9..0000000000 --- a/runtime/interpreter/mterp/x86/op_ushr_long_2addr.S +++ /dev/null @@ -1,27 +0,0 @@ -%def op_ushr_long_2addr(): -/* - * Long integer shift, 2addr version. vA is 64-bit value/result, vB is - * 32-bit shift distance. - */ - /* shl-long/2addr vA, vB */ - /* ecx gets shift count */ - /* Need to spill rIBASE */ - /* rINSTw gets AA */ - movzbl rINSTbl, %ecx # ecx <- BA - andb $$0xf, rINSTbl # rINST <- A - GET_VREG %eax, rINST # eax <- v[AA+0] - sarl $$4, %ecx # ecx <- B - movl rIBASE, LOCAL0(%esp) - GET_VREG_HIGH rIBASE, rINST # rIBASE <- v[AA+1] - GET_VREG %ecx, %ecx # ecx <- vBB - shrdl rIBASE, %eax - shrl %cl, rIBASE - testb $$32, %cl - je 2f - movl rIBASE, %eax - xorl rIBASE, rIBASE -2: - SET_VREG_HIGH rIBASE, rINST # v[AA+1] <- rIBASE - movl LOCAL0(%esp), rIBASE - SET_VREG %eax, rINST # v[AA+0] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/op_xor_int.S b/runtime/interpreter/mterp/x86/op_xor_int.S deleted file mode 100644 index 351d73ae9d..0000000000 --- a/runtime/interpreter/mterp/x86/op_xor_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_xor_int(): -% binop(instr="xorl (rFP,%ecx,4), %eax") diff --git a/runtime/interpreter/mterp/x86/op_xor_int_2addr.S b/runtime/interpreter/mterp/x86/op_xor_int_2addr.S deleted file mode 100644 index daeebed866..0000000000 --- a/runtime/interpreter/mterp/x86/op_xor_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_xor_int_2addr(): -% binop2addr(instr="xorl %eax, (rFP,%ecx,4)") diff --git a/runtime/interpreter/mterp/x86/op_xor_int_lit16.S b/runtime/interpreter/mterp/x86/op_xor_int_lit16.S deleted file mode 100644 index f5dc00e074..0000000000 --- a/runtime/interpreter/mterp/x86/op_xor_int_lit16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_xor_int_lit16(): -% binopLit16(instr="xorl %ecx, %eax") diff --git a/runtime/interpreter/mterp/x86/op_xor_int_lit8.S b/runtime/interpreter/mterp/x86/op_xor_int_lit8.S deleted file mode 100644 index 98a1a432dd..0000000000 --- a/runtime/interpreter/mterp/x86/op_xor_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_xor_int_lit8(): -% binopLit8(instr="xorl %ecx, %eax") diff --git a/runtime/interpreter/mterp/x86/op_xor_long.S b/runtime/interpreter/mterp/x86/op_xor_long.S deleted file mode 100644 index cc749e66c7..0000000000 --- a/runtime/interpreter/mterp/x86/op_xor_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_xor_long(): -% binopWide(instr1="xorl (rFP,%ecx,4), rIBASE", instr2="xorl 4(rFP,%ecx,4), %eax") diff --git a/runtime/interpreter/mterp/x86/op_xor_long_2addr.S b/runtime/interpreter/mterp/x86/op_xor_long_2addr.S deleted file mode 100644 index 3aa92357a9..0000000000 --- a/runtime/interpreter/mterp/x86/op_xor_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_xor_long_2addr(): -% binopWide2addr(instr1="xorl %eax, (rFP,rINST,4)", instr2="xorl %ecx, 4(rFP,rINST,4)") diff --git a/runtime/interpreter/mterp/x86/other.S b/runtime/interpreter/mterp/x86/other.S new file mode 100644 index 0000000000..5de33813b8 --- /dev/null +++ b/runtime/interpreter/mterp/x86/other.S @@ -0,0 +1,318 @@ +%def const(helper="UndefinedConstHandler"): + /* const/class vAA, type@BBBB */ + /* const/method-handle vAA, method_handle@BBBB */ + /* const/method-type vAA, proto@BBBB */ + /* const/string vAA, string@@BBBB */ + .extern $helper + EXPORT_PC + movzwl 2(rPC), %eax # eax <- BBBB + movl %eax, OUT_ARG0(%esp) + movl rINST, OUT_ARG1(%esp) + leal OFF_FP_SHADOWFRAME(rFP), %eax + movl %eax, OUT_ARG2(%esp) + movl rSELF, %eax + movl %eax, OUT_ARG3(%esp) + call SYMBOL($helper) # (index, tgt_reg, shadow_frame, self) + RESTORE_IBASE + testb %al, %al + jnz MterpPossibleException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def unused(): +/* + * Bail to reference interpreter to throw. + */ + jmp MterpFallback + +%def op_const(): + /* const vAA, #+BBBBbbbb */ + movl 2(rPC), %eax # grab all 32 bits at once + SET_VREG %eax, rINST # vAA<- eax + ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 + +%def op_const_16(): + /* const/16 vAA, #+BBBB */ + movswl 2(rPC), %ecx # ecx <- ssssBBBB + SET_VREG %ecx, rINST # vAA <- ssssBBBB + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_const_4(): + /* const/4 vA, #+B */ + movsx rINSTbl, %eax # eax <-ssssssBx + movl $$0xf, rINST + andl %eax, rINST # rINST <- A + sarl $$4, %eax + SET_VREG %eax, rINST + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_const_class(): +% const(helper="MterpConstClass") + +%def op_const_high16(): + /* const/high16 vAA, #+BBBB0000 */ + movzwl 2(rPC), %eax # eax <- 0000BBBB + sall $$16, %eax # eax <- BBBB0000 + SET_VREG %eax, rINST # vAA <- eax + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_const_method_handle(): +% const(helper="MterpConstMethodHandle") + +%def op_const_method_type(): +% const(helper="MterpConstMethodType") + +%def op_const_string(): +% const(helper="MterpConstString") + +%def op_const_string_jumbo(): + /* const/string vAA, String@BBBBBBBB */ + EXPORT_PC + movl 2(rPC), %eax # eax <- BBBB + movl %eax, OUT_ARG0(%esp) + movl rINST, OUT_ARG1(%esp) + leal OFF_FP_SHADOWFRAME(rFP), %eax + movl %eax, OUT_ARG2(%esp) + movl rSELF, %eax + movl %eax, OUT_ARG3(%esp) + call SYMBOL(MterpConstString) # (index, tgt_reg, shadow_frame, self) + RESTORE_IBASE + testb %al, %al + jnz MterpPossibleException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 + +%def op_const_wide(): + /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ + movl 2(rPC), %eax # eax <- lsw + movzbl rINSTbl, %ecx # ecx <- AA + movl 6(rPC), rINST # rINST <- msw + SET_VREG %eax, %ecx + SET_VREG_HIGH rINST, %ecx + ADVANCE_PC_FETCH_AND_GOTO_NEXT 5 + +%def op_const_wide_16(): + /* const-wide/16 vAA, #+BBBB */ + movswl 2(rPC), %eax # eax <- ssssBBBB + movl rIBASE, %ecx # preserve rIBASE (cltd trashes it) + cltd # rIBASE:eax <- ssssssssssssBBBB + SET_VREG_HIGH rIBASE, rINST # store msw + SET_VREG %eax, rINST # store lsw + movl %ecx, rIBASE # restore rIBASE + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_const_wide_32(): + /* const-wide/32 vAA, #+BBBBbbbb */ + movl 2(rPC), %eax # eax <- BBBBbbbb + movl rIBASE, %ecx # preserve rIBASE (cltd trashes it) + cltd # rIBASE:eax <- ssssssssssssBBBB + SET_VREG_HIGH rIBASE, rINST # store msw + SET_VREG %eax, rINST # store lsw + movl %ecx, rIBASE # restore rIBASE + ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 + +%def op_const_wide_high16(): + /* const-wide/high16 vAA, #+BBBB000000000000 */ + movzwl 2(rPC), %eax # eax <- 0000BBBB + sall $$16, %eax # eax <- BBBB0000 + SET_VREG_HIGH %eax, rINST # v[AA+1] <- eax + xorl %eax, %eax + SET_VREG %eax, rINST # v[AA+0] <- eax + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_monitor_enter(): +/* + * Synchronize on an object. + */ + /* monitor-enter vAA */ + EXPORT_PC + GET_VREG %ecx, rINST + movl %ecx, OUT_ARG0(%esp) + movl rSELF, %eax + movl %eax, OUT_ARG1(%esp) + call SYMBOL(artLockObjectFromCode) # (object, self) + RESTORE_IBASE + testb %al, %al + jnz MterpException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_monitor_exit(): +/* + * Unlock an object. + * + * Exceptions that occur when unlocking a monitor need to appear as + * if they happened at the following instruction. See the Dalvik + * instruction spec. + */ + /* monitor-exit vAA */ + EXPORT_PC + GET_VREG %ecx, rINST + movl %ecx, OUT_ARG0(%esp) + movl rSELF, %eax + movl %eax, OUT_ARG1(%esp) + call SYMBOL(artUnlockObjectFromCode) # (object, self) + RESTORE_IBASE + testb %al, %al + jnz MterpException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_move(is_object="0"): + /* for move, move-object, long-to-int */ + /* op vA, vB */ + movzbl rINSTbl, %eax # eax <- BA + andb $$0xf, %al # eax <- A + shrl $$4, rINST # rINST <- B + GET_VREG rINST, rINST + .if $is_object + SET_VREG_OBJECT rINST, %eax # fp[A] <- fp[B] + .else + SET_VREG rINST, %eax # fp[A] <- fp[B] + .endif + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_move_16(is_object="0"): + /* for: move/16, move-object/16 */ + /* op vAAAA, vBBBB */ + movzwl 4(rPC), %ecx # ecx <- BBBB + movzwl 2(rPC), %eax # eax <- AAAA + GET_VREG rINST, %ecx + .if $is_object + SET_VREG_OBJECT rINST, %eax # fp[A] <- fp[B] + .else + SET_VREG rINST, %eax # fp[A] <- fp[B] + .endif + ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 + +%def op_move_exception(): + /* move-exception vAA */ + movl rSELF, %ecx + movl THREAD_EXCEPTION_OFFSET(%ecx), %eax + SET_VREG_OBJECT %eax, rINST # fp[AA] <- exception object + movl $$0, THREAD_EXCEPTION_OFFSET(%ecx) + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_move_from16(is_object="0"): + /* for: move/from16, move-object/from16 */ + /* op vAA, vBBBB */ + movzx rINSTbl, %eax # eax <- AA + movw 2(rPC), rINSTw # rINSTw <- BBBB + GET_VREG rINST, rINST # rINST <- fp[BBBB] + .if $is_object + SET_VREG_OBJECT rINST, %eax # fp[A] <- fp[B] + .else + SET_VREG rINST, %eax # fp[A] <- fp[B] + .endif + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_move_object(): +% op_move(is_object="1") + +%def op_move_object_16(): +% op_move_16(is_object="1") + +%def op_move_object_from16(): +% op_move_from16(is_object="1") + +%def op_move_result(is_object="0"): + /* for: move-result, move-result-object */ + /* op vAA */ + movl OFF_FP_RESULT_REGISTER(rFP), %eax # get pointer to result JType. + movl (%eax), %eax # r0 <- result.i. + .if $is_object + SET_VREG_OBJECT %eax, rINST # fp[A] <- fp[B] + .else + SET_VREG %eax, rINST # fp[A] <- fp[B] + .endif + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_move_result_object(): +% op_move_result(is_object="1") + +%def op_move_result_wide(): + /* move-result-wide vAA */ + movl OFF_FP_RESULT_REGISTER(rFP), %eax # get pointer to result JType. + movl 4(%eax), %ecx # Get high + movl (%eax), %eax # Get low + SET_VREG %eax, rINST # v[AA+0] <- eax + SET_VREG_HIGH %ecx, rINST # v[AA+1] <- ecx + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_move_wide(): + /* move-wide vA, vB */ + /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ + movzbl rINSTbl, %ecx # ecx <- BA + sarl $$4, rINST # rINST <- B + andb $$0xf, %cl # ecx <- A + GET_WIDE_FP_VREG %xmm0, rINST # xmm0 <- v[B] + SET_WIDE_FP_VREG %xmm0, %ecx # v[A] <- xmm0 + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_move_wide_16(): + /* move-wide/16 vAAAA, vBBBB */ + /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ + movzwl 4(rPC), %ecx # ecx<- BBBB + movzwl 2(rPC), %eax # eax<- AAAA + GET_WIDE_FP_VREG %xmm0, %ecx # xmm0 <- v[B] + SET_WIDE_FP_VREG %xmm0, %eax # v[A] <- xmm0 + ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 + +%def op_move_wide_from16(): + /* move-wide/from16 vAA, vBBBB */ + /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ + movzwl 2(rPC), %ecx # ecx <- BBBB + movzbl rINSTbl, %eax # eax <- AAAA + GET_WIDE_FP_VREG %xmm0, %ecx # xmm0 <- v[B] + SET_WIDE_FP_VREG %xmm0, %eax # v[A] <- xmm0 + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_nop(): + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_unused_3e(): +% unused() + +%def op_unused_3f(): +% unused() + +%def op_unused_40(): +% unused() + +%def op_unused_41(): +% unused() + +%def op_unused_42(): +% unused() + +%def op_unused_43(): +% unused() + +%def op_unused_79(): +% unused() + +%def op_unused_7a(): +% unused() + +%def op_unused_f3(): +% unused() + +%def op_unused_f4(): +% unused() + +%def op_unused_f5(): +% unused() + +%def op_unused_f6(): +% unused() + +%def op_unused_f7(): +% unused() + +%def op_unused_f8(): +% unused() + +%def op_unused_f9(): +% unused() + +%def op_unused_fc(): +% unused() + +%def op_unused_fd(): +% unused() diff --git a/runtime/interpreter/mterp/x86/shop2addr.S b/runtime/interpreter/mterp/x86/shop2addr.S deleted file mode 100644 index 9a57677832..0000000000 --- a/runtime/interpreter/mterp/x86/shop2addr.S +++ /dev/null @@ -1,13 +0,0 @@ -%def shop2addr(result="%eax", instr=""): -/* - * Generic 32-bit "shift/2addr" operation. - */ - /* shift/2addr vA, vB */ - movzx rINSTbl, %ecx # eax <- BA - sarl $$4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # eax <- vBB - andb $$0xf, rINSTbl # rINST <- A - GET_VREG %eax, rINST # eax <- vAA - $instr # ex: sarl %cl, %eax - SET_VREG $result, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/sseBinop.S b/runtime/interpreter/mterp/x86/sseBinop.S deleted file mode 100644 index a20db7cc2b..0000000000 --- a/runtime/interpreter/mterp/x86/sseBinop.S +++ /dev/null @@ -1,9 +0,0 @@ -%def sseBinop(instr="", suff=""): - movzbl 2(rPC), %ecx # ecx <- BB - movzbl 3(rPC), %eax # eax <- CC - movs${suff} VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src - ${instr}${suff} VREG_ADDRESS(%eax), %xmm0 - movs${suff} %xmm0, VREG_ADDRESS(rINST) # vAA <- %xmm0 - pxor %xmm0, %xmm0 - movs${suff} %xmm0, VREG_REF_ADDRESS(rINST) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/sseBinop2Addr.S b/runtime/interpreter/mterp/x86/sseBinop2Addr.S deleted file mode 100644 index 1186fb7c2c..0000000000 --- a/runtime/interpreter/mterp/x86/sseBinop2Addr.S +++ /dev/null @@ -1,10 +0,0 @@ -%def sseBinop2Addr(instr="", suff=""): - movzx rINSTbl, %ecx # ecx <- A+ - andl $$0xf, %ecx # ecx <- A - movs${suff} VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src - sarl $$4, rINST # rINST<- B - ${instr}${suff} VREG_ADDRESS(rINST), %xmm0 - movs${suff} %xmm0, VREG_ADDRESS(%ecx) # vAA<- %xmm0 - pxor %xmm0, %xmm0 - movs${suff} %xmm0, VREG_REF_ADDRESS(rINST) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/unop.S b/runtime/interpreter/mterp/x86/unop.S deleted file mode 100644 index 5594cb9e1b..0000000000 --- a/runtime/interpreter/mterp/x86/unop.S +++ /dev/null @@ -1,13 +0,0 @@ -%def unop(instr=""): -/* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op eax". - */ - /* unop vA, vB */ - movzbl rINSTbl,%ecx # ecx <- A+ - sarl $$4,rINST # rINST <- B - GET_VREG %eax, rINST # eax <- vB - andb $$0xf,%cl # ecx <- A - $instr - SET_VREG %eax, %ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/unused.S b/runtime/interpreter/mterp/x86/unused.S deleted file mode 100644 index ef35b6e73f..0000000000 --- a/runtime/interpreter/mterp/x86/unused.S +++ /dev/null @@ -1,5 +0,0 @@ -%def unused(): -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback diff --git a/runtime/interpreter/mterp/x86/zcmp.S b/runtime/interpreter/mterp/x86/zcmp.S deleted file mode 100644 index 120f1ed949..0000000000 --- a/runtime/interpreter/mterp/x86/zcmp.S +++ /dev/null @@ -1,18 +0,0 @@ -%def zcmp(revcmp=""): -/* - * Generic one-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - cmpl $$0, VREG_ADDRESS(rINST) # compare (vA, 0) - j${revcmp} 1f - movswl 2(rPC), rINST # fetch signed displacement - testl rINST, rINST - jmp MterpCommonTakenBranch -1: - cmpw $$JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/alt_stub.S b/runtime/interpreter/mterp/x86_64/alt_stub.S deleted file mode 100644 index 0c71716e22..0000000000 --- a/runtime/interpreter/mterp/x86_64/alt_stub.S +++ /dev/null @@ -1,18 +0,0 @@ -%def alt_stub(): -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(${opnum}*${handler_size_bytes}) diff --git a/runtime/interpreter/mterp/x86_64/arithmetic.S b/runtime/interpreter/mterp/x86_64/arithmetic.S new file mode 100644 index 0000000000..ffe2008993 --- /dev/null +++ b/runtime/interpreter/mterp/x86_64/arithmetic.S @@ -0,0 +1,575 @@ +%def bindiv(result="", second="", wide="", suffix="", rem="0", ext="cdq"): +/* + * 32-bit binary div/rem operation. Handles special case of op1=-1. + */ + /* div/rem vAA, vBB, vCC */ + movzbq 2(rPC), %rax # rax <- BB + movzbq 3(rPC), %rcx # rcx <- CC + .if $wide + GET_WIDE_VREG %rax, %rax # eax <- vBB + GET_WIDE_VREG $second, %rcx # ecx <- vCC + .else + GET_VREG %eax, %rax # eax <- vBB + GET_VREG $second, %rcx # ecx <- vCC + .endif + test${suffix} $second, $second + jz common_errDivideByZero + cmp${suffix} $$-1, $second + je 2f + $ext # rdx:rax <- sign-extended of rax + idiv${suffix} $second +1: + .if $wide + SET_WIDE_VREG $result, rINSTq # eax <- vBB + .else + SET_VREG $result, rINSTq # eax <- vBB + .endif + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 +2: + .if $rem + xor${suffix} $result, $result + .else + neg${suffix} $result + .endif + jmp 1b + +%def bindiv2addr(result="", second="", wide="", suffix="", rem="0", ext="cdq"): +/* + * 32-bit binary div/rem operation. Handles special case of op1=-1. + */ + /* div/rem/2addr vA, vB */ + movl rINST, %ecx # rcx <- BA + sarl $$4, %ecx # rcx <- B + andb $$0xf, rINSTbl # rINST <- A + .if $wide + GET_WIDE_VREG %rax, rINSTq # eax <- vA + GET_WIDE_VREG $second, %rcx # ecx <- vB + .else + GET_VREG %eax, rINSTq # eax <- vA + GET_VREG $second, %rcx # ecx <- vB + .endif + test${suffix} $second, $second + jz common_errDivideByZero + cmp${suffix} $$-1, $second + je 2f + $ext # rdx:rax <- sign-extended of rax + idiv${suffix} $second +1: + .if $wide + SET_WIDE_VREG $result, rINSTq # vA <- result + .else + SET_VREG $result, rINSTq # vA <- result + .endif + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 +2: + .if $rem + xor${suffix} $result, $result + .else + neg${suffix} $result + .endif + jmp 1b + +%def bindivLit16(result="", rem="0"): +/* + * 32-bit binary div/rem operation. Handles special case of op1=-1. + */ + /* div/rem/lit16 vA, vB, #+CCCC */ + /* Need A in rINST, ssssCCCC in ecx, vB in eax */ + movl rINST, %eax # rax <- 000000BA + sarl $$4, %eax # eax <- B + GET_VREG %eax, %rax # eax <- vB + movswl 2(rPC), %ecx # ecx <- ssssCCCC + andb $$0xf, rINSTbl # rINST <- A + testl %ecx, %ecx + jz common_errDivideByZero + cmpl $$-1, %ecx + je 2f + cdq # rax <- sign-extended of eax + idivl %ecx +1: + SET_VREG $result, rINSTq # vA <- result + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 +2: + .if $rem + xorl $result, $result + .else + negl $result + .endif + jmp 1b + +%def bindivLit8(result="", rem="0"): +/* + * 32-bit div/rem "lit8" binary operation. Handles special case of + * op0=minint & op1=-1 + */ + /* div/rem/lit8 vAA, vBB, #+CC */ + movzbq 2(rPC), %rax # eax <- BB + movsbl 3(rPC), %ecx # ecx <- ssssssCC + GET_VREG %eax, %rax # eax <- rBB + testl %ecx, %ecx + je common_errDivideByZero + cmpl $$-1, %ecx + je 2f + cdq # rax <- sign-extended of eax + idivl %ecx +1: + SET_VREG $result, rINSTq # vA <- result + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 +2: + .if $rem + xorl $result, $result + .else + negl $result + .endif + jmp 1b + +%def binop(result="%eax", instr=""): +/* + * Generic 32-bit binary operation. Provide an "instr" line that + * specifies an instruction that performs "result = eax op (rFP,%ecx,4)". + * This could be an x86 instruction or a function call. (If the result + * comes back in a register other than eax, you can override "result".) + * + * For: add-int, sub-int, and-int, or-int, + * xor-int, shl-int, shr-int, ushr-int + */ + /* binop vAA, vBB, vCC */ + movzbq 2(rPC), %rax # rax <- BB + movzbq 3(rPC), %rcx # rcx <- CC + GET_VREG %eax, %rax # eax <- vBB + $instr # ex: addl (rFP,%rcx,4),%eax + SET_VREG $result, rINSTq + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def binop1(wide="0", instr=""): +/* + * Generic 32-bit binary operation in which both operands loaded to + * registers (op0 in eax, op1 in ecx). + */ + /* binop vAA, vBB, vCC */ + movzbq 2(rPC), %rax # eax <- BB + movzbq 3(rPC), %rcx # ecx <- CC + GET_VREG %ecx, %rcx # eax <- vCC + .if $wide + GET_WIDE_VREG %rax, %rax # rax <- vBB + $instr # ex: addl %ecx,%eax + SET_WIDE_VREG %rax, rINSTq + .else + GET_VREG %eax, %rax # eax <- vBB + $instr # ex: addl %ecx,%eax + SET_VREG %eax, rINSTq + .endif + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def binop2addr(result="%eax", instr=""): +/* + * Generic 32-bit "/2addr" binary operation. Provide an "instr" line + * that specifies an instruction that performs "result = r0 op r1". + * This could be an instruction or a function call. + * + * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, + * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, + * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, + * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr + */ + /* binop/2addr vA, vB */ + movl rINST, %ecx # rcx <- A+ + sarl $$4, rINST # rINST <- B + andb $$0xf, %cl # ecx <- A + GET_VREG %eax, rINSTq # eax <- vB + $instr # for ex: addl %eax,(rFP,%ecx,4) + CLEAR_REF %rcx + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def binopLit16(result="%eax", instr=""): +/* + * Generic 32-bit "lit16" binary operation. Provide an "instr" line + * that specifies an instruction that performs "result = eax op ecx". + * This could be an x86 instruction or a function call. (If the result + * comes back in a register other than eax, you can override "result".) + * + * For: add-int/lit16, rsub-int, + * and-int/lit16, or-int/lit16, xor-int/lit16 + */ + /* binop/lit16 vA, vB, #+CCCC */ + movl rINST, %eax # rax <- 000000BA + sarl $$4, %eax # eax <- B + GET_VREG %eax, %rax # eax <- vB + andb $$0xf, rINSTbl # rINST <- A + movswl 2(rPC), %ecx # ecx <- ssssCCCC + $instr # for example: addl %ecx, %eax + SET_VREG $result, rINSTq + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def binopLit8(result="%eax", instr=""): +/* + * Generic 32-bit "lit8" binary operation. Provide an "instr" line + * that specifies an instruction that performs "result = eax op ecx". + * This could be an x86 instruction or a function call. (If the result + * comes back in a register other than r0, you can override "result".) + * + * For: add-int/lit8, rsub-int/lit8 + * and-int/lit8, or-int/lit8, xor-int/lit8, + * shl-int/lit8, shr-int/lit8, ushr-int/lit8 + */ + /* binop/lit8 vAA, vBB, #+CC */ + movzbq 2(rPC), %rax # rax <- BB + movsbl 3(rPC), %ecx # rcx <- ssssssCC + GET_VREG %eax, %rax # eax <- rBB + $instr # ex: addl %ecx,%eax + SET_VREG $result, rINSTq + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def binopWide(instr=""): +/* + * Generic 64-bit binary operation. + */ + /* binop vAA, vBB, vCC */ + movzbq 2(rPC), %rax # eax <- BB + movzbq 3(rPC), %rcx # ecx <- CC + GET_WIDE_VREG %rax, %rax # rax <- v[BB] + $instr # ex: addq (rFP,%rcx,4),%rax + SET_WIDE_VREG %rax, rINSTq # v[AA] <- rax + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def binopWide2addr(instr=""): +/* + * Generic 64-bit binary operation. + */ + /* binop/2addr vA, vB */ + movl rINST, %ecx # rcx <- A+ + sarl $$4, rINST # rINST <- B + andb $$0xf, %cl # ecx <- A + GET_WIDE_VREG %rax, rINSTq # rax <- vB + $instr # for ex: addq %rax,(rFP,%rcx,4) + CLEAR_WIDE_REF %rcx + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def cvtfp_int(fp_suffix="", i_suffix="", max_const="", result_reg="", wide=""): +/* On fp to int conversions, Java requires that + * if the result > maxint, it should be clamped to maxint. If it is less + * than minint, it should be clamped to minint. If it is a nan, the result + * should be zero. Further, the rounding mode is to truncate. + */ + /* float/double to int/long vA, vB */ + movl rINST, %ecx # rcx <- A+ + sarl $$4, rINST # rINST <- B + andb $$0xf, %cl # ecx <- A + movs${fp_suffix} VREG_ADDRESS(rINSTq), %xmm0 + mov${i_suffix} ${max_const}, ${result_reg} + cvtsi2s${fp_suffix}${i_suffix} ${result_reg}, %xmm1 + comis${fp_suffix} %xmm1, %xmm0 + jae 1f + jp 2f + cvtts${fp_suffix}2si${i_suffix} %xmm0, ${result_reg} + jmp 1f +2: + xor${i_suffix} ${result_reg}, ${result_reg} +1: + .if $wide + SET_WIDE_VREG ${result_reg}, %rcx + .else + SET_VREG ${result_reg}, %rcx + .endif + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def shop2addr(wide="0", instr=""): +/* + * Generic 32-bit "shift/2addr" operation. + */ + /* shift/2addr vA, vB */ + movl rINST, %ecx # ecx <- BA + sarl $$4, %ecx # ecx <- B + GET_VREG %ecx, %rcx # ecx <- vBB + andb $$0xf, rINSTbl # rINST <- A + .if $wide + GET_WIDE_VREG %rax, rINSTq # rax <- vAA + $instr # ex: sarl %cl, %eax + SET_WIDE_VREG %rax, rINSTq + .else + GET_VREG %eax, rINSTq # eax <- vAA + $instr # ex: sarl %cl, %eax + SET_VREG %eax, rINSTq + .endif + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def unop(preinstr="", instr="", wide="0"): +/* + * Generic 32/64-bit unary operation. Provide an "instr" line that + * specifies an instruction that performs "result = op eax". + */ + /* unop vA, vB */ + movl rINST, %ecx # rcx <- A+ + sarl $$4,rINST # rINST <- B + .if ${wide} + GET_WIDE_VREG %rax, rINSTq # rax <- vB + .else + GET_VREG %eax, rINSTq # eax <- vB + .endif + andb $$0xf,%cl # ecx <- A +$preinstr +$instr + .if ${wide} + SET_WIDE_VREG %rax, %rcx + .else + SET_VREG %eax, %rcx + .endif + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_add_int(): +% binop(instr="addl (rFP,%rcx,4), %eax") + +%def op_add_int_2addr(): +% binop2addr(instr="addl %eax, (rFP,%rcx,4)") + +%def op_add_int_lit16(): +% binopLit16(instr="addl %ecx, %eax") + +%def op_add_int_lit8(): +% binopLit8(instr="addl %ecx, %eax") + +%def op_add_long(): +% binopWide(instr="addq (rFP,%rcx,4), %rax") + +%def op_add_long_2addr(): +% binopWide2addr(instr="addq %rax, (rFP,%rcx,4)") + +%def op_and_int(): +% binop(instr="andl (rFP,%rcx,4), %eax") + +%def op_and_int_2addr(): +% binop2addr(instr="andl %eax, (rFP,%rcx,4)") + +%def op_and_int_lit16(): +% binopLit16(instr="andl %ecx, %eax") + +%def op_and_int_lit8(): +% binopLit8(instr="andl %ecx, %eax") + +%def op_and_long(): +% binopWide(instr="andq (rFP,%rcx,4), %rax") + +%def op_and_long_2addr(): +% binopWide2addr(instr="andq %rax, (rFP,%rcx,4)") + +%def op_cmp_long(): +/* + * Compare two 64-bit values. Puts 0, 1, or -1 into the destination + * register based on the results of the comparison. + */ + /* cmp-long vAA, vBB, vCC */ + movzbq 2(rPC), %rdx # edx <- BB + movzbq 3(rPC), %rcx # ecx <- CC + GET_WIDE_VREG %rdx, %rdx # rdx <- v[BB] + xorl %eax, %eax + xorl %edi, %edi + addb $$1, %al + movl $$-1, %esi + cmpq VREG_ADDRESS(%rcx), %rdx + cmovl %esi, %edi + cmovg %eax, %edi + SET_VREG %edi, rINSTq + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_div_int(): +% bindiv(result="%eax", second="%ecx", wide="0", suffix="l") + +%def op_div_int_2addr(): +% bindiv2addr(result="%eax", second="%ecx", wide="0", suffix="l") + +%def op_div_int_lit16(): +% bindivLit16(result="%eax") + +%def op_div_int_lit8(): +% bindivLit8(result="%eax") + +%def op_div_long(): +% bindiv(result="%rax", second="%rcx", wide="1", suffix="q", ext="cqo") + +%def op_div_long_2addr(): +% bindiv2addr(result="%rax", second="%rcx", wide="1", suffix="q", ext="cqo") + +%def op_int_to_byte(): +% unop(instr="movsbl %al, %eax") + +%def op_int_to_char(): +% unop(instr="movzwl %ax,%eax") + +%def op_int_to_long(): + /* int to long vA, vB */ + movzbq rINSTbl, %rax # rax <- +A + sarl $$4, %eax # eax <- B + andb $$0xf, rINSTbl # rINST <- A + movslq VREG_ADDRESS(%rax), %rax + SET_WIDE_VREG %rax, rINSTq # v[A] <- %rax + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + + +%def op_int_to_short(): +% unop(instr="movswl %ax, %eax") + +%def op_long_to_int(): +/* we ignore the high word, making this equivalent to a 32-bit reg move */ +% op_move() + +%def op_mul_int(): +% binop(instr="imull (rFP,%rcx,4), %eax") + +%def op_mul_int_2addr(): + /* mul vA, vB */ + movl rINST, %ecx # rcx <- A+ + sarl $$4, rINST # rINST <- B + andb $$0xf, %cl # ecx <- A + GET_VREG %eax, %rcx # eax <- vA + imull (rFP,rINSTq,4), %eax + SET_VREG %eax, %rcx + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_mul_int_lit16(): +% binopLit16(instr="imull %ecx, %eax") + +%def op_mul_int_lit8(): +% binopLit8(instr="imull %ecx, %eax") + +%def op_mul_long(): +% binopWide(instr="imulq (rFP,%rcx,4), %rax") + +%def op_mul_long_2addr(): + /* mul vA, vB */ + movl rINST, %ecx # rcx <- A+ + sarl $$4, rINST # rINST <- B + andb $$0xf, %cl # ecx <- A + GET_WIDE_VREG %rax, %rcx # rax <- vA + imulq (rFP,rINSTq,4), %rax + SET_WIDE_VREG %rax, %rcx + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_neg_int(): +% unop(instr=" negl %eax") + +%def op_neg_long(): +% unop(instr=" negq %rax", wide="1") + +%def op_not_int(): +% unop(instr=" notl %eax") + +%def op_not_long(): +% unop(instr=" notq %rax", wide="1") + +%def op_or_int(): +% binop(instr="orl (rFP,%rcx,4), %eax") + +%def op_or_int_2addr(): +% binop2addr(instr="orl %eax, (rFP,%rcx,4)") + +%def op_or_int_lit16(): +% binopLit16(instr="orl %ecx, %eax") + +%def op_or_int_lit8(): +% binopLit8(instr="orl %ecx, %eax") + +%def op_or_long(): +% binopWide(instr="orq (rFP,%rcx,4), %rax") + +%def op_or_long_2addr(): +% binopWide2addr(instr="orq %rax, (rFP,%rcx,4)") + +%def op_rem_int(): +% bindiv(result="%edx", second="%ecx", wide="0", suffix="l", rem="1") + +%def op_rem_int_2addr(): +% bindiv2addr(result="%edx", second="%ecx", wide="0", suffix="l", rem="1") + +%def op_rem_int_lit16(): +% bindivLit16(result="%edx", rem="1") + +%def op_rem_int_lit8(): +% bindivLit8(result="%edx", rem="1") + +%def op_rem_long(): +% bindiv(result="%rdx", second="%rcx", wide="1", suffix="q", ext="cqo", rem="1") + +%def op_rem_long_2addr(): +% bindiv2addr(result="%rdx", second="%rcx", wide="1", suffix="q", rem="1", ext="cqo") + +%def op_rsub_int(): +/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ +% binopLit16(instr="subl %eax, %ecx", result="%ecx") + +%def op_rsub_int_lit8(): +% binopLit8(instr="subl %eax, %ecx", result="%ecx") + +%def op_shl_int(): +% binop1(instr="sall %cl, %eax") + +%def op_shl_int_2addr(): +% shop2addr(instr="sall %cl, %eax") + +%def op_shl_int_lit8(): +% binopLit8(instr="sall %cl, %eax") + +%def op_shl_long(): +% binop1(instr="salq %cl, %rax", wide="1") + +%def op_shl_long_2addr(): +% shop2addr(instr="salq %cl, %rax", wide="1") + +%def op_shr_int(): +% binop1(instr="sarl %cl, %eax") + +%def op_shr_int_2addr(): +% shop2addr(instr="sarl %cl, %eax") + +%def op_shr_int_lit8(): +% binopLit8(instr="sarl %cl, %eax") + +%def op_shr_long(): +% binop1(instr="sarq %cl, %rax", wide="1") + +%def op_shr_long_2addr(): +% shop2addr(instr="sarq %cl, %rax", wide="1") + +%def op_sub_int(): +% binop(instr="subl (rFP,%rcx,4), %eax") + +%def op_sub_int_2addr(): +% binop2addr(instr="subl %eax, (rFP,%rcx,4)") + +%def op_sub_long(): +% binopWide(instr="subq (rFP,%rcx,4), %rax") + +%def op_sub_long_2addr(): +% binopWide2addr(instr="subq %rax, (rFP,%rcx,4)") + +%def op_ushr_int(): +% binop1(instr="shrl %cl, %eax") + +%def op_ushr_int_2addr(): +% shop2addr(instr="shrl %cl, %eax") + +%def op_ushr_int_lit8(): +% binopLit8(instr="shrl %cl, %eax") + +%def op_ushr_long(): +% binop1(instr="shrq %cl, %rax", wide="1") + +%def op_ushr_long_2addr(): +% shop2addr(instr="shrq %cl, %rax", wide="1") + +%def op_xor_int(): +% binop(instr="xorl (rFP,%rcx,4), %eax") + +%def op_xor_int_2addr(): +% binop2addr(instr="xorl %eax, (rFP,%rcx,4)") + +%def op_xor_int_lit16(): +% binopLit16(instr="xorl %ecx, %eax") + +%def op_xor_int_lit8(): +% binopLit8(instr="xorl %ecx, %eax") + +%def op_xor_long(): +% binopWide(instr="xorq (rFP,%rcx,4), %rax") + +%def op_xor_long_2addr(): +% binopWide2addr(instr="xorq %rax, (rFP,%rcx,4)") diff --git a/runtime/interpreter/mterp/x86_64/array.S b/runtime/interpreter/mterp/x86_64/array.S new file mode 100644 index 0000000000..e49c09778c --- /dev/null +++ b/runtime/interpreter/mterp/x86_64/array.S @@ -0,0 +1,178 @@ +%def op_aget(load="movl", shift="4", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET", wide="0"): +/* + * Array get, 32 bits or less. vAA <- vBB[vCC]. + * + * for: aget, aget-boolean, aget-byte, aget-char, aget-short, aget-wide + * + */ + /* op vAA, vBB, vCC */ + movzbq 2(rPC), %rax # eax <- BB + movzbq 3(rPC), %rcx # ecx <- CC + GET_VREG %eax, %rax # eax <- vBB (array object) + GET_VREG %ecx, %rcx # ecx <- vCC (requested index) + testl %eax, %eax # null array object? + je common_errNullObject # bail if so + cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx + jae common_errArrayIndex # index >= length, bail. + .if $wide + movq $data_offset(%rax,%rcx,8), %rax + SET_WIDE_VREG %rax, rINSTq + .else + $load $data_offset(%rax,%rcx,$shift), %eax + SET_VREG %eax, rINSTq + .endif + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_aget_boolean(): +% op_aget(load="movzbl", shift="1", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") + +%def op_aget_byte(): +% op_aget(load="movsbl", shift="1", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") + +%def op_aget_char(): +% op_aget(load="movzwl", shift="2", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") + +%def op_aget_object(): +/* + * Array object get. vAA <- vBB[vCC]. + * + * for: aget-object + */ + /* op vAA, vBB, vCC */ + movzbq 2(rPC), %rax # rax <- BB + movzbq 3(rPC), %rcx # rcx <- CC + GET_VREG OUT_32_ARG0, %rax # eax <- vBB (array object) + GET_VREG OUT_32_ARG1, %rcx # ecx <- vCC (requested index) + EXPORT_PC + call SYMBOL(artAGetObjectFromMterp) # (array, index) + movq rSELF, %rcx + cmpq $$0, THREAD_EXCEPTION_OFFSET(%rcx) + jnz MterpException + SET_VREG_OBJECT %eax, rINSTq + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_aget_short(): +% op_aget(load="movswl", shift="2", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") + +%def op_aget_wide(): +% op_aget(load="movq", shift="8", data_offset="MIRROR_WIDE_ARRAY_DATA_OFFSET", wide="1") + +%def op_aput(reg="rINST", store="movl", shift="4", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET", wide="0"): +/* + * Array put, 32 bits or less. vBB[vCC] <- vAA. + * + * for: aput, aput-boolean, aput-byte, aput-char, aput-short, aput-wide + * + */ + /* op vAA, vBB, vCC */ + movzbq 2(rPC), %rax # rax <- BB + movzbq 3(rPC), %rcx # rcx <- CC + GET_VREG %eax, %rax # eax <- vBB (array object) + GET_VREG %ecx, %rcx # ecx <- vCC (requested index) + testl %eax, %eax # null array object? + je common_errNullObject # bail if so + cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx + jae common_errArrayIndex # index >= length, bail. + .if $wide + GET_WIDE_VREG rINSTq, rINSTq + .else + GET_VREG rINST, rINSTq + .endif + $store $reg, $data_offset(%rax,%rcx,$shift) + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_aput_boolean(): +% op_aput(reg="rINSTbl", store="movb", shift="1", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") + +%def op_aput_byte(): +% op_aput(reg="rINSTbl", store="movb", shift="1", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") + +%def op_aput_char(): +% op_aput(reg="rINSTw", store="movw", shift="2", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") + +%def op_aput_object(): +/* + * Store an object into an array. vBB[vCC] <- vAA. + */ + /* op vAA, vBB, vCC */ + EXPORT_PC + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG0 + movq rPC, OUT_ARG1 + REFRESH_INST ${opnum} + movq rINSTq, OUT_ARG2 + call SYMBOL(MterpAputObject) # (array, index) + testb %al, %al + jz MterpPossibleException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_aput_short(): +% op_aput(reg="rINSTw", store="movw", shift="2", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") + +%def op_aput_wide(): +% op_aput(reg="rINSTq", store="movq", shift="8", data_offset="MIRROR_WIDE_ARRAY_DATA_OFFSET", wide="1") + +%def op_array_length(): +/* + * Return the length of an array. + */ + movl rINST, %eax # eax <- BA + sarl $$4, rINST # rINST <- B + GET_VREG %ecx, rINSTq # ecx <- vB (object ref) + testl %ecx, %ecx # is null? + je common_errNullObject + andb $$0xf, %al # eax <- A + movl MIRROR_ARRAY_LENGTH_OFFSET(%rcx), rINST + SET_VREG rINST, %rax + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_fill_array_data(): + /* fill-array-data vAA, +BBBBBBBB */ + EXPORT_PC + movslq 2(rPC), %rcx # rcx <- ssssssssBBBBbbbb + leaq (rPC,%rcx,2), OUT_ARG1 # OUT_ARG1 <- PC + ssssssssBBBBbbbb*2 + GET_VREG OUT_32_ARG0, rINSTq # OUT_ARG0 <- vAA (array object) + call SYMBOL(MterpFillArrayData) # (obj, payload) + testb %al, %al # 0 means an exception is thrown + jz MterpPossibleException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 + +%def op_filled_new_array(helper="MterpFilledNewArray"): +/* + * Create a new array with elements filled from registers. + * + * for: filled-new-array, filled-new-array/range + */ + /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ + /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ + .extern $helper + EXPORT_PC + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG0 + movq rPC, OUT_ARG1 + movq rSELF, OUT_ARG2 + call SYMBOL($helper) + testb %al, %al # 0 means an exception is thrown + jz MterpPossibleException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 + +%def op_filled_new_array_range(): +% op_filled_new_array(helper="MterpFilledNewArrayRange") + +%def op_new_array(): +/* + * Allocate an array of objects, specified with the array class + * and a count. + * + * The verifier guarantees that this is an array class, so we don't + * check for it here. + */ + /* new-array vA, vB, class@CCCC */ + EXPORT_PC + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG0 + movq rPC, OUT_ARG1 + REFRESH_INST ${opnum} + movq rINSTq, OUT_ARG2 + movq rSELF, OUT_ARG3 + call SYMBOL(MterpNewArray) + testb %al, %al # 0 means an exception is thrown + jz MterpPossibleException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/bincmp.S b/runtime/interpreter/mterp/x86_64/bincmp.S deleted file mode 100644 index 64a118c103..0000000000 --- a/runtime/interpreter/mterp/x86_64/bincmp.S +++ /dev/null @@ -1,22 +0,0 @@ -%def bincmp(revcmp=""): -/* - * Generic two-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - movl rINST, %ecx # rcx <- A+ - sarl $$4, rINST # rINST <- B - andb $$0xf, %cl # rcx <- A - GET_VREG %eax, %rcx # eax <- vA - cmpl VREG_ADDRESS(rINSTq), %eax # compare (vA, vB) - j${revcmp} 1f - movswq 2(rPC), rINSTq # Get signed branch offset - testq rINSTq, rINSTq - jmp MterpCommonTakenBranch -1: - cmpl $$JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/bindiv.S b/runtime/interpreter/mterp/x86_64/bindiv.S deleted file mode 100644 index d7e5333af6..0000000000 --- a/runtime/interpreter/mterp/x86_64/bindiv.S +++ /dev/null @@ -1,34 +0,0 @@ -%def bindiv(result="", second="", wide="", suffix="", rem="0", ext="cdq"): -/* - * 32-bit binary div/rem operation. Handles special case of op1=-1. - */ - /* div/rem vAA, vBB, vCC */ - movzbq 2(rPC), %rax # rax <- BB - movzbq 3(rPC), %rcx # rcx <- CC - .if $wide - GET_WIDE_VREG %rax, %rax # eax <- vBB - GET_WIDE_VREG $second, %rcx # ecx <- vCC - .else - GET_VREG %eax, %rax # eax <- vBB - GET_VREG $second, %rcx # ecx <- vCC - .endif - test${suffix} $second, $second - jz common_errDivideByZero - cmp${suffix} $$-1, $second - je 2f - $ext # rdx:rax <- sign-extended of rax - idiv${suffix} $second -1: - .if $wide - SET_WIDE_VREG $result, rINSTq # eax <- vBB - .else - SET_VREG $result, rINSTq # eax <- vBB - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 -2: - .if $rem - xor${suffix} $result, $result - .else - neg${suffix} $result - .endif - jmp 1b diff --git a/runtime/interpreter/mterp/x86_64/bindiv2addr.S b/runtime/interpreter/mterp/x86_64/bindiv2addr.S deleted file mode 100644 index c55351ecb0..0000000000 --- a/runtime/interpreter/mterp/x86_64/bindiv2addr.S +++ /dev/null @@ -1,35 +0,0 @@ -%def bindiv2addr(result="", second="", wide="", suffix="", rem="0", ext="cdq"): -/* - * 32-bit binary div/rem operation. Handles special case of op1=-1. - */ - /* div/rem/2addr vA, vB */ - movl rINST, %ecx # rcx <- BA - sarl $$4, %ecx # rcx <- B - andb $$0xf, rINSTbl # rINST <- A - .if $wide - GET_WIDE_VREG %rax, rINSTq # eax <- vA - GET_WIDE_VREG $second, %rcx # ecx <- vB - .else - GET_VREG %eax, rINSTq # eax <- vA - GET_VREG $second, %rcx # ecx <- vB - .endif - test${suffix} $second, $second - jz common_errDivideByZero - cmp${suffix} $$-1, $second - je 2f - $ext # rdx:rax <- sign-extended of rax - idiv${suffix} $second -1: - .if $wide - SET_WIDE_VREG $result, rINSTq # vA <- result - .else - SET_VREG $result, rINSTq # vA <- result - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 -2: - .if $rem - xor${suffix} $result, $result - .else - neg${suffix} $result - .endif - jmp 1b diff --git a/runtime/interpreter/mterp/x86_64/bindivLit16.S b/runtime/interpreter/mterp/x86_64/bindivLit16.S deleted file mode 100644 index dbda834331..0000000000 --- a/runtime/interpreter/mterp/x86_64/bindivLit16.S +++ /dev/null @@ -1,27 +0,0 @@ -%def bindivLit16(result="", rem="0"): -/* - * 32-bit binary div/rem operation. Handles special case of op1=-1. - */ - /* div/rem/lit16 vA, vB, #+CCCC */ - /* Need A in rINST, ssssCCCC in ecx, vB in eax */ - movl rINST, %eax # rax <- 000000BA - sarl $$4, %eax # eax <- B - GET_VREG %eax, %rax # eax <- vB - movswl 2(rPC), %ecx # ecx <- ssssCCCC - andb $$0xf, rINSTbl # rINST <- A - testl %ecx, %ecx - jz common_errDivideByZero - cmpl $$-1, %ecx - je 2f - cdq # rax <- sign-extended of eax - idivl %ecx -1: - SET_VREG $result, rINSTq # vA <- result - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 -2: - .if $rem - xorl $result, $result - .else - negl $result - .endif - jmp 1b diff --git a/runtime/interpreter/mterp/x86_64/bindivLit8.S b/runtime/interpreter/mterp/x86_64/bindivLit8.S deleted file mode 100644 index a5164b5021..0000000000 --- a/runtime/interpreter/mterp/x86_64/bindivLit8.S +++ /dev/null @@ -1,25 +0,0 @@ -%def bindivLit8(result="", rem="0"): -/* - * 32-bit div/rem "lit8" binary operation. Handles special case of - * op0=minint & op1=-1 - */ - /* div/rem/lit8 vAA, vBB, #+CC */ - movzbq 2(rPC), %rax # eax <- BB - movsbl 3(rPC), %ecx # ecx <- ssssssCC - GET_VREG %eax, %rax # eax <- rBB - testl %ecx, %ecx - je common_errDivideByZero - cmpl $$-1, %ecx - je 2f - cdq # rax <- sign-extended of eax - idivl %ecx -1: - SET_VREG $result, rINSTq # vA <- result - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 -2: - .if $rem - xorl $result, $result - .else - negl $result - .endif - jmp 1b diff --git a/runtime/interpreter/mterp/x86_64/binop.S b/runtime/interpreter/mterp/x86_64/binop.S deleted file mode 100644 index fddeaa1826..0000000000 --- a/runtime/interpreter/mterp/x86_64/binop.S +++ /dev/null @@ -1,17 +0,0 @@ -%def binop(result="%eax", instr=""): -/* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = eax op (rFP,%ecx,4)". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int, sub-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - movzbq 2(rPC), %rax # rax <- BB - movzbq 3(rPC), %rcx # rcx <- CC - GET_VREG %eax, %rax # eax <- vBB - $instr # ex: addl (rFP,%rcx,4),%eax - SET_VREG $result, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/binop1.S b/runtime/interpreter/mterp/x86_64/binop1.S deleted file mode 100644 index 9915c32fbf..0000000000 --- a/runtime/interpreter/mterp/x86_64/binop1.S +++ /dev/null @@ -1,19 +0,0 @@ -%def binop1(wide="0", instr=""): -/* - * Generic 32-bit binary operation in which both operands loaded to - * registers (op0 in eax, op1 in ecx). - */ - /* binop vAA, vBB, vCC */ - movzbq 2(rPC), %rax # eax <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_VREG %ecx, %rcx # eax <- vCC - .if $wide - GET_WIDE_VREG %rax, %rax # rax <- vBB - $instr # ex: addl %ecx,%eax - SET_WIDE_VREG %rax, rINSTq - .else - GET_VREG %eax, %rax # eax <- vBB - $instr # ex: addl %ecx,%eax - SET_VREG %eax, rINSTq - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/binop2addr.S b/runtime/interpreter/mterp/x86_64/binop2addr.S deleted file mode 100644 index 1cdf7fd401..0000000000 --- a/runtime/interpreter/mterp/x86_64/binop2addr.S +++ /dev/null @@ -1,19 +0,0 @@ -%def binop2addr(result="%eax", instr=""): -/* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an instruction or a function call. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $$4, rINST # rINST <- B - andb $$0xf, %cl # ecx <- A - GET_VREG %eax, rINSTq # eax <- vB - $instr # for ex: addl %eax,(rFP,%ecx,4) - CLEAR_REF %rcx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86_64/binopLit16.S b/runtime/interpreter/mterp/x86_64/binopLit16.S deleted file mode 100644 index bb882cba75..0000000000 --- a/runtime/interpreter/mterp/x86_64/binopLit16.S +++ /dev/null @@ -1,19 +0,0 @@ -%def binopLit16(result="%eax", instr=""): -/* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int/lit16, rsub-int, - * and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - movl rINST, %eax # rax <- 000000BA - sarl $$4, %eax # eax <- B - GET_VREG %eax, %rax # eax <- vB - andb $$0xf, rINSTbl # rINST <- A - movswl 2(rPC), %ecx # ecx <- ssssCCCC - $instr # for example: addl %ecx, %eax - SET_VREG $result, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/binopLit8.S b/runtime/interpreter/mterp/x86_64/binopLit8.S deleted file mode 100644 index a30d2e8ed2..0000000000 --- a/runtime/interpreter/mterp/x86_64/binopLit8.S +++ /dev/null @@ -1,18 +0,0 @@ -%def binopLit8(result="%eax", instr=""): -/* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * For: add-int/lit8, rsub-int/lit8 - * and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - movzbq 2(rPC), %rax # rax <- BB - movsbl 3(rPC), %ecx # rcx <- ssssssCC - GET_VREG %eax, %rax # eax <- rBB - $instr # ex: addl %ecx,%eax - SET_VREG $result, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/binopWide.S b/runtime/interpreter/mterp/x86_64/binopWide.S deleted file mode 100644 index 015d9eef41..0000000000 --- a/runtime/interpreter/mterp/x86_64/binopWide.S +++ /dev/null @@ -1,11 +0,0 @@ -%def binopWide(instr=""): -/* - * Generic 64-bit binary operation. - */ - /* binop vAA, vBB, vCC */ - movzbq 2(rPC), %rax # eax <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_WIDE_VREG %rax, %rax # rax <- v[BB] - $instr # ex: addq (rFP,%rcx,4),%rax - SET_WIDE_VREG %rax, rINSTq # v[AA] <- rax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/binopWide2addr.S b/runtime/interpreter/mterp/x86_64/binopWide2addr.S deleted file mode 100644 index e4c1e4da73..0000000000 --- a/runtime/interpreter/mterp/x86_64/binopWide2addr.S +++ /dev/null @@ -1,12 +0,0 @@ -%def binopWide2addr(instr=""): -/* - * Generic 64-bit binary operation. - */ - /* binop/2addr vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $$4, rINST # rINST <- B - andb $$0xf, %cl # ecx <- A - GET_WIDE_VREG %rax, rINSTq # rax <- vB - $instr # for ex: addq %rax,(rFP,%rcx,4) - CLEAR_WIDE_REF %rcx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86_64/const.S b/runtime/interpreter/mterp/x86_64/const.S deleted file mode 100644 index fa98637a29..0000000000 --- a/runtime/interpreter/mterp/x86_64/const.S +++ /dev/null @@ -1,15 +0,0 @@ -%def const(helper="UndefinedConstHandler"): - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern $helper - EXPORT_PC - movzwq 2(rPC), OUT_ARG0 # eax <- OUT_ARG0 - movq rINSTq, OUT_ARG1 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 - movq rSELF, OUT_ARG3 - call SYMBOL($helper) # (index, tgt_reg, shadow_frame, self) - testb %al, %al - jnz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/control_flow.S b/runtime/interpreter/mterp/x86_64/control_flow.S new file mode 100644 index 0000000000..2f3b5e560f --- /dev/null +++ b/runtime/interpreter/mterp/x86_64/control_flow.S @@ -0,0 +1,206 @@ +%def bincmp(revcmp=""): +/* + * Generic two-operand compare-and-branch operation. Provide a "revcmp" + * fragment that specifies the *reverse* comparison to perform, e.g. + * for "if-le" you would use "gt". + * + * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le + */ + /* if-cmp vA, vB, +CCCC */ + movl rINST, %ecx # rcx <- A+ + sarl $$4, rINST # rINST <- B + andb $$0xf, %cl # rcx <- A + GET_VREG %eax, %rcx # eax <- vA + cmpl VREG_ADDRESS(rINSTq), %eax # compare (vA, vB) + j${revcmp} 1f + movswq 2(rPC), rINSTq # Get signed branch offset + testq rINSTq, rINSTq + jmp MterpCommonTakenBranch +1: + cmpl $$JIT_CHECK_OSR, rPROFILE + je .L_check_not_taken_osr + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def zcmp(revcmp=""): +/* + * Generic one-operand compare-and-branch operation. Provide a "revcmp" + * fragment that specifies the *reverse* comparison to perform, e.g. + * for "if-le" you would use "gt". + * + * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez + */ + /* if-cmp vAA, +BBBB */ + cmpl $$0, VREG_ADDRESS(rINSTq) # compare (vA, 0) + j${revcmp} 1f + movswq 2(rPC), rINSTq # fetch signed displacement + testq rINSTq, rINSTq + jmp MterpCommonTakenBranch +1: + cmpl $$JIT_CHECK_OSR, rPROFILE + je .L_check_not_taken_osr + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_goto(): +/* + * Unconditional branch, 8-bit offset. + * + * The branch distance is a signed code-unit offset, which we need to + * double to get a byte offset. + */ + /* goto +AA */ + movsbq rINSTbl, rINSTq # rINSTq <- ssssssAA + testq rINSTq, rINSTq + jmp MterpCommonTakenBranch + +%def op_goto_16(): +/* + * Unconditional branch, 16-bit offset. + * + * The branch distance is a signed code-unit offset, which we need to + * double to get a byte offset. + */ + /* goto/16 +AAAA */ + movswq 2(rPC), rINSTq # rINSTq <- ssssAAAA + testq rINSTq, rINSTq + jmp MterpCommonTakenBranch + +%def op_goto_32(): +/* + * Unconditional branch, 32-bit offset. + * + * The branch distance is a signed code-unit offset, which we need to + * double to get a byte offset. + * + * Because we need the SF bit set, we'll use an adds + * to convert from Dalvik offset to byte offset. + */ + /* goto/32 +AAAAAAAA */ + movslq 2(rPC), rINSTq # rINSTq <- AAAAAAAA + testq rINSTq, rINSTq + jmp MterpCommonTakenBranch + +%def op_if_eq(): +% bincmp(revcmp="ne") + +%def op_if_eqz(): +% zcmp(revcmp="ne") + +%def op_if_ge(): +% bincmp(revcmp="l") + +%def op_if_gez(): +% zcmp(revcmp="l") + +%def op_if_gt(): +% bincmp(revcmp="le") + +%def op_if_gtz(): +% zcmp(revcmp="le") + +%def op_if_le(): +% bincmp(revcmp="g") + +%def op_if_lez(): +% zcmp(revcmp="g") + +%def op_if_lt(): +% bincmp(revcmp="ge") + +%def op_if_ltz(): +% zcmp(revcmp="ge") + +%def op_if_ne(): +% bincmp(revcmp="e") + +%def op_if_nez(): +% zcmp(revcmp="e") + +%def op_packed_switch(func="MterpDoPackedSwitch"): +/* + * Handle a packed-switch or sparse-switch instruction. In both cases + * we decode it and hand it off to a helper function. + * + * We don't really expect backward branches in a switch statement, but + * they're perfectly legal, so we check for them here. + * + * for: packed-switch, sparse-switch + */ + /* op vAA, +BBBB */ + movslq 2(rPC), OUT_ARG0 # rcx <- ssssssssBBBBbbbb + leaq (rPC,OUT_ARG0,2), OUT_ARG0 # rcx <- PC + ssssssssBBBBbbbb*2 + GET_VREG OUT_32_ARG1, rINSTq # eax <- vAA + call SYMBOL($func) + testl %eax, %eax + movslq %eax, rINSTq + jmp MterpCommonTakenBranch + +%def op_return(): +/* + * Return a 32-bit value. + * + * for: return, return-object + */ + /* op vAA */ + .extern MterpThreadFenceForConstructor + call SYMBOL(MterpThreadFenceForConstructor) + movq rSELF, OUT_ARG0 + testl $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(OUT_ARG0) + jz 1f + call SYMBOL(MterpSuspendCheck) +1: + GET_VREG %eax, rINSTq # eax <- vAA + jmp MterpReturn + +%def op_return_object(): +% op_return() + +%def op_return_void(): + .extern MterpThreadFenceForConstructor + call SYMBOL(MterpThreadFenceForConstructor) + movq rSELF, OUT_ARG0 + testl $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(OUT_ARG0) + jz 1f + call SYMBOL(MterpSuspendCheck) +1: + xorq %rax, %rax + jmp MterpReturn + +%def op_return_void_no_barrier(): + movq rSELF, OUT_ARG0 + testl $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(OUT_ARG0) + jz 1f + call SYMBOL(MterpSuspendCheck) +1: + xorq %rax, %rax + jmp MterpReturn + +%def op_return_wide(): +/* + * Return a 64-bit value. + */ + /* return-wide vAA */ + .extern MterpThreadFenceForConstructor + call SYMBOL(MterpThreadFenceForConstructor) + movq rSELF, OUT_ARG0 + testl $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(OUT_ARG0) + jz 1f + call SYMBOL(MterpSuspendCheck) +1: + GET_WIDE_VREG %rax, rINSTq # eax <- v[AA] + jmp MterpReturn + +%def op_sparse_switch(): +% op_packed_switch(func="MterpDoSparseSwitch") + +%def op_throw(): +/* + * Throw an exception object in the current thread. + */ + /* throw vAA */ + EXPORT_PC + GET_VREG %eax, rINSTq # eax<- vAA (exception object) + testb %al, %al + jz common_errNullObject + movq rSELF, %rcx + movq %rax, THREAD_EXCEPTION_OFFSET(%rcx) + jmp MterpException diff --git a/runtime/interpreter/mterp/x86_64/cvtfp_int.S b/runtime/interpreter/mterp/x86_64/cvtfp_int.S deleted file mode 100644 index e18986f0db..0000000000 --- a/runtime/interpreter/mterp/x86_64/cvtfp_int.S +++ /dev/null @@ -1,27 +0,0 @@ -%def cvtfp_int(fp_suffix="", i_suffix="", max_const="", result_reg="", wide=""): -/* On fp to int conversions, Java requires that - * if the result > maxint, it should be clamped to maxint. If it is less - * than minint, it should be clamped to minint. If it is a nan, the result - * should be zero. Further, the rounding mode is to truncate. - */ - /* float/double to int/long vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $$4, rINST # rINST <- B - andb $$0xf, %cl # ecx <- A - movs${fp_suffix} VREG_ADDRESS(rINSTq), %xmm0 - mov${i_suffix} ${max_const}, ${result_reg} - cvtsi2s${fp_suffix}${i_suffix} ${result_reg}, %xmm1 - comis${fp_suffix} %xmm1, %xmm0 - jae 1f - jp 2f - cvtts${fp_suffix}2si${i_suffix} %xmm0, ${result_reg} - jmp 1f -2: - xor${i_suffix} ${result_reg}, ${result_reg} -1: - .if $wide - SET_WIDE_VREG ${result_reg}, %rcx - .else - SET_VREG ${result_reg}, %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86_64/entry.S b/runtime/interpreter/mterp/x86_64/entry.S deleted file mode 100644 index 515ffbc3ea..0000000000 --- a/runtime/interpreter/mterp/x86_64/entry.S +++ /dev/null @@ -1,80 +0,0 @@ -%def entry(): -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -/* - * Interpreter entry point. - */ - - .text - ASM_HIDDEN SYMBOL(ExecuteMterpImpl) - .global SYMBOL(ExecuteMterpImpl) - FUNCTION_TYPE(ExecuteMterpImpl) - -/* - * On entry: - * 0 Thread* self - * 1 insns_ - * 2 ShadowFrame - * 3 JValue* result_register - * - */ - -SYMBOL(ExecuteMterpImpl): - .cfi_startproc - .cfi_def_cfa rsp, 8 - - /* Spill callee save regs */ - PUSH %rbx - PUSH %rbp - PUSH %r12 - PUSH %r13 - PUSH %r14 - PUSH %r15 - - /* Allocate frame */ - subq $$FRAME_SIZE, %rsp - .cfi_adjust_cfa_offset FRAME_SIZE - - /* Remember the return register */ - movq IN_ARG3, SHADOWFRAME_RESULT_REGISTER_OFFSET(IN_ARG2) - - /* Remember the code_item */ - movq IN_ARG1, SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET(IN_ARG2) - - /* set up "named" registers */ - movl SHADOWFRAME_NUMBER_OF_VREGS_OFFSET(IN_ARG2), %eax - leaq SHADOWFRAME_VREGS_OFFSET(IN_ARG2), rFP - leaq (rFP, %rax, 4), rREFS - movl SHADOWFRAME_DEX_PC_OFFSET(IN_ARG2), %eax - leaq (IN_ARG1, %rax, 2), rPC - CFI_DEFINE_DEX_PC_WITH_OFFSET(CFI_TMP, CFI_DEX, 0) - EXPORT_PC - - /* Starting ibase */ - movq IN_ARG0, rSELF - REFRESH_IBASE_REG IN_ARG0 - - /* Set up for backwards branches & osr profiling */ - movq IN_ARG0, OUT_ARG2 /* Set up OUT_ARG2 before clobbering IN_ARG0 */ - movq OFF_FP_METHOD(rFP), OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - call SYMBOL(MterpSetUpHotnessCountdown) - movswl %ax, rPROFILE - - /* start executing the instruction at rPC */ - FETCH_INST - GOTO_NEXT - /* NOTE: no fallthrough */ diff --git a/runtime/interpreter/mterp/x86_64/fallback.S b/runtime/interpreter/mterp/x86_64/fallback.S deleted file mode 100644 index e3c2e2bd40..0000000000 --- a/runtime/interpreter/mterp/x86_64/fallback.S +++ /dev/null @@ -1,4 +0,0 @@ -%def fallback(): -/* Transfer stub to alternate interpreter */ - jmp MterpFallback - diff --git a/runtime/interpreter/mterp/x86_64/field.S b/runtime/interpreter/mterp/x86_64/field.S deleted file mode 100644 index f6c40eb224..0000000000 --- a/runtime/interpreter/mterp/x86_64/field.S +++ /dev/null @@ -1,14 +0,0 @@ -%def field(helper=""): - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern $helper - REFRESH_INST ${opnum} # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL($helper) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/floating_point.S b/runtime/interpreter/mterp/x86_64/floating_point.S new file mode 100644 index 0000000000..b40c0e632e --- /dev/null +++ b/runtime/interpreter/mterp/x86_64/floating_point.S @@ -0,0 +1,236 @@ +%def fpcmp(suff="d", nanval="pos"): +/* + * Compare two floating-point values. Puts 0, 1, or -1 into the + * destination register based on the results of the comparison. + * + * int compare(x, y) { + * if (x == y) { + * return 0; + * } else if (x < y) { + * return -1; + * } else if (x > y) { + * return 1; + * } else { + * return nanval ? 1 : -1; + * } + * } + */ + /* op vAA, vBB, vCC */ + movzbq 3(rPC), %rcx # ecx<- CC + movzbq 2(rPC), %rax # eax<- BB + movs${suff} VREG_ADDRESS(%rax), %xmm0 + xor %eax, %eax + ucomis${suff} VREG_ADDRESS(%rcx), %xmm0 + jp .L${opcode}_nan_is_${nanval} + je .L${opcode}_finish + jb .L${opcode}_less +.L${opcode}_nan_is_pos: + addb $$1, %al + jmp .L${opcode}_finish +.L${opcode}_nan_is_neg: +.L${opcode}_less: + movl $$-1, %eax +.L${opcode}_finish: + SET_VREG %eax, rINSTq + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def fpcvt(source_suffix="", dest_suffix="", wide=""): +/* + * Generic 32-bit FP conversion operation. + */ + /* unop vA, vB */ + movl rINST, %ecx # rcx <- A+ + sarl $$4, rINST # rINST <- B + andb $$0xf, %cl # ecx <- A + cvts${source_suffix}2s${dest_suffix} VREG_ADDRESS(rINSTq), %xmm0 + .if $wide + movsd %xmm0, VREG_ADDRESS(%rcx) + CLEAR_WIDE_REF %rcx + .else + movss %xmm0, VREG_ADDRESS(%rcx) + CLEAR_REF %rcx + .endif + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def sseBinop(instr="", suff=""): + movzbq 2(rPC), %rcx # ecx <- BB + movzbq 3(rPC), %rax # eax <- CC + movs${suff} VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src + ${instr}${suff} VREG_ADDRESS(%rax), %xmm0 + movs${suff} %xmm0, VREG_ADDRESS(rINSTq) # vAA <- %xmm0 + pxor %xmm0, %xmm0 + movs${suff} %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def sseBinop2Addr(instr="", suff=""): + movl rINST, %ecx # ecx <- A+ + andl $$0xf, %ecx # ecx <- A + movs${suff} VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src + sarl $$4, rINST # rINST<- B + ${instr}${suff} VREG_ADDRESS(rINSTq), %xmm0 + movs${suff} %xmm0, VREG_ADDRESS(%rcx) # vAA<- %xmm0 + pxor %xmm0, %xmm0 + movs${suff} %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_add_double(): +% sseBinop(instr="adds", suff="d") + +%def op_add_double_2addr(): +% sseBinop2Addr(instr="adds", suff="d") + +%def op_add_float(): +% sseBinop(instr="adds", suff="s") + +%def op_add_float_2addr(): +% sseBinop2Addr(instr="adds", suff="s") + +%def op_cmpg_double(): +% fpcmp(suff="d", nanval="pos") + +%def op_cmpg_float(): +% fpcmp(suff="s", nanval="pos") + +%def op_cmpl_double(): +% fpcmp(suff="d", nanval="neg") + +%def op_cmpl_float(): +% fpcmp(suff="s", nanval="neg") + +%def op_div_double(): +% sseBinop(instr="divs", suff="d") + +%def op_div_double_2addr(): +% sseBinop2Addr(instr="divs", suff="d") + +%def op_div_float(): +% sseBinop(instr="divs", suff="s") + +%def op_div_float_2addr(): +% sseBinop2Addr(instr="divs", suff="s") + +%def op_double_to_float(): +% fpcvt(source_suffix="d", dest_suffix="s", wide="0") + +%def op_double_to_int(): +% cvtfp_int(fp_suffix="d", i_suffix="l", max_const="$0x7fffffff", result_reg="%eax", wide="0") + +%def op_double_to_long(): +% cvtfp_int(fp_suffix="d", i_suffix="q", max_const="$0x7fffffffffffffff", result_reg="%rax", wide="1") + +%def op_float_to_double(): +% fpcvt(source_suffix="s", dest_suffix="d", wide="1") + +%def op_float_to_int(): +% cvtfp_int(fp_suffix="s", i_suffix="l", max_const="$0x7fffffff", result_reg="%eax", wide="0") + +%def op_float_to_long(): +% cvtfp_int(fp_suffix="s", i_suffix="q", max_const="$0x7fffffffffffffff", result_reg="%rax", wide="1") + +%def op_int_to_double(): +% fpcvt(source_suffix="i", dest_suffix="dl", wide="1") + +%def op_int_to_float(): +% fpcvt(source_suffix="i", dest_suffix="sl", wide="0") + +%def op_long_to_double(): +% fpcvt(source_suffix="i", dest_suffix="dq", wide="1") + +%def op_long_to_float(): +% fpcvt(source_suffix="i", dest_suffix="sq", wide="0") + +%def op_mul_double(): +% sseBinop(instr="muls", suff="d") + +%def op_mul_double_2addr(): +% sseBinop2Addr(instr="muls", suff="d") + +%def op_mul_float(): +% sseBinop(instr="muls", suff="s") + +%def op_mul_float_2addr(): +% sseBinop2Addr(instr="muls", suff="s") + +%def op_neg_double(): +% unop(preinstr=" movq $0x8000000000000000, %rsi", instr=" xorq %rsi, %rax", wide="1") + +%def op_neg_float(): +% unop(instr=" xorl $0x80000000, %eax") + +%def op_rem_double(): + /* rem_double vAA, vBB, vCC */ + movzbq 3(rPC), %rcx # ecx <- BB + movzbq 2(rPC), %rax # eax <- CC + fldl VREG_ADDRESS(%rcx) # %st1 <- fp[vBB] + fldl VREG_ADDRESS(%rax) # %st0 <- fp[vCC] +1: + fprem + fstsw %ax + sahf + jp 1b + fstp %st(1) + fstpl VREG_ADDRESS(rINSTq) # fp[vAA] <- %st + CLEAR_WIDE_REF rINSTq + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_rem_double_2addr(): + /* rem_double/2addr vA, vB */ + movzbq rINSTbl, %rcx # ecx <- A+ + sarl $$4, rINST # rINST <- B + fldl VREG_ADDRESS(rINSTq) # vB to fp stack + andb $$0xf, %cl # ecx <- A + fldl VREG_ADDRESS(%rcx) # vA to fp stack +1: + fprem + fstsw %ax + sahf + jp 1b + fstp %st(1) + fstpl VREG_ADDRESS(%rcx) # %st to vA + CLEAR_WIDE_REF %rcx + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_rem_float(): + /* rem_float vAA, vBB, vCC */ + movzbq 3(rPC), %rcx # ecx <- BB + movzbq 2(rPC), %rax # eax <- CC + flds VREG_ADDRESS(%rcx) # vBB to fp stack + flds VREG_ADDRESS(%rax) # vCC to fp stack +1: + fprem + fstsw %ax + sahf + jp 1b + fstp %st(1) + fstps VREG_ADDRESS(rINSTq) # %st to vAA + CLEAR_REF rINSTq + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_rem_float_2addr(): + /* rem_float/2addr vA, vB */ + movzbq rINSTbl, %rcx # ecx <- A+ + sarl $$4, rINST # rINST <- B + flds VREG_ADDRESS(rINSTq) # vB to fp stack + andb $$0xf, %cl # ecx <- A + flds VREG_ADDRESS(%rcx) # vA to fp stack +1: + fprem + fstsw %ax + sahf + jp 1b + fstp %st(1) + fstps VREG_ADDRESS(%rcx) # %st to vA + CLEAR_REF %rcx + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_sub_double(): +% sseBinop(instr="subs", suff="d") + +%def op_sub_double_2addr(): +% sseBinop2Addr(instr="subs", suff="d") + +%def op_sub_float(): +% sseBinop(instr="subs", suff="s") + +%def op_sub_float_2addr(): +% sseBinop2Addr(instr="subs", suff="s") diff --git a/runtime/interpreter/mterp/x86_64/footer.S b/runtime/interpreter/mterp/x86_64/footer.S deleted file mode 100644 index 140fbaed49..0000000000 --- a/runtime/interpreter/mterp/x86_64/footer.S +++ /dev/null @@ -1,298 +0,0 @@ -%def footer(): -/* - * =========================================================================== - * Common subroutines and data - * =========================================================================== - */ - - .text - .align 2 - -/* - * We've detected a condition that will result in an exception, but the exception - * has not yet been thrown. Just bail out to the reference interpreter to deal with it. - * TUNING: for consistency, we may want to just go ahead and handle these here. - */ -common_errDivideByZero: - EXPORT_PC -#if MTERP_LOGGING - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - call SYMBOL(MterpLogDivideByZeroException) -#endif - jmp MterpCommonFallback - -common_errArrayIndex: - EXPORT_PC -#if MTERP_LOGGING - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - call SYMBOL(MterpLogArrayIndexException) -#endif - jmp MterpCommonFallback - -common_errNegativeArraySize: - EXPORT_PC -#if MTERP_LOGGING - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - call SYMBOL(MterpLogNegativeArraySizeException) -#endif - jmp MterpCommonFallback - -common_errNoSuchMethod: - EXPORT_PC -#if MTERP_LOGGING - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - call SYMBOL(MterpLogNoSuchMethodException) -#endif - jmp MterpCommonFallback - -common_errNullObject: - EXPORT_PC -#if MTERP_LOGGING - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - call SYMBOL(MterpLogNullObjectException) -#endif - jmp MterpCommonFallback - -common_exceptionThrown: - EXPORT_PC -#if MTERP_LOGGING - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - call SYMBOL(MterpLogExceptionThrownException) -#endif - jmp MterpCommonFallback - -MterpSuspendFallback: - EXPORT_PC -#if MTERP_LOGGING - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movl THREAD_FLAGS_OFFSET(OUT_ARG0), OUT_32_ARG2 - call SYMBOL(MterpLogSuspendFallback) -#endif - jmp MterpCommonFallback - -/* - * If we're here, something is out of the ordinary. If there is a pending - * exception, handle it. Otherwise, roll back and retry with the reference - * interpreter. - */ -MterpPossibleException: - movq rSELF, %rcx - cmpq $$0, THREAD_EXCEPTION_OFFSET(%rcx) - jz MterpFallback - /* intentional fallthrough - handle pending exception. */ - -/* - * On return from a runtime helper routine, we've found a pending exception. - * Can we handle it here - or need to bail out to caller? - * - */ -MterpException: - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - call SYMBOL(MterpHandleException) - testb %al, %al - jz MterpExceptionReturn - movq OFF_FP_DEX_INSTRUCTIONS(rFP), %rax - mov OFF_FP_DEX_PC(rFP), %ecx - leaq (%rax, %rcx, 2), rPC - movq rPC, OFF_FP_DEX_PC_PTR(rFP) - /* Do we need to switch interpreters? */ - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - /* resume execution at catch block */ - REFRESH_IBASE - FETCH_INST - GOTO_NEXT - /* NOTE: no fallthrough */ - -/* - * Common handling for branches with support for Jit profiling. - * On entry: - * rINST <= signed offset - * rPROFILE <= signed hotness countdown (expanded to 32 bits) - * condition bits <= set to establish sign of offset (use "NoFlags" entry if not) - * - * We have quite a few different cases for branch profiling, OSR detection and - * suspend check support here. - * - * Taken backward branches: - * If profiling active, do hotness countdown and report if we hit zero. - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * Is there a pending suspend request? If so, suspend. - * - * Taken forward branches and not-taken backward branches: - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * - * Our most common case is expected to be a taken backward branch with active jit profiling, - * but no full OSR check and no pending suspend request. - * Next most common case is not-taken branch with no full OSR check. - * - */ -MterpCommonTakenBranch: - jg .L_forward_branch # don't add forward branches to hotness -/* - * We need to subtract 1 from positive values and we should not see 0 here, - * so we may use the result of the comparison with -1. - */ -#if JIT_CHECK_OSR != -1 -# error "JIT_CHECK_OSR must be -1." -#endif - cmpl $$JIT_CHECK_OSR, rPROFILE - je .L_osr_check - decl rPROFILE - je .L_add_batch # counted down to zero - report -.L_resume_backward_branch: - movq rSELF, %rax - testl $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(%rax) - REFRESH_IBASE_REG %rax - leaq (rPC, rINSTq, 2), rPC - FETCH_INST - jnz .L_suspend_request_pending - GOTO_NEXT - -.L_suspend_request_pending: - EXPORT_PC - movq rSELF, OUT_ARG0 - call SYMBOL(MterpSuspendCheck) # (self) - testb %al, %al - jnz MterpFallback - REFRESH_IBASE # might have changed during suspend - GOTO_NEXT - -.L_no_count_backwards: - cmpl $$JIT_CHECK_OSR, rPROFILE # possible OSR re-entry? - jne .L_resume_backward_branch -.L_osr_check: - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rINSTq, OUT_ARG2 - call SYMBOL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) - testb %al, %al - jz .L_resume_backward_branch - jmp MterpOnStackReplacement - -.L_forward_branch: - cmpl $$JIT_CHECK_OSR, rPROFILE # possible OSR re-entry? - je .L_check_osr_forward -.L_resume_forward_branch: - leaq (rPC, rINSTq, 2), rPC - FETCH_INST - GOTO_NEXT - -.L_check_osr_forward: - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rINSTq, OUT_ARG2 - call SYMBOL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) - testb %al, %al - jz .L_resume_forward_branch - jmp MterpOnStackReplacement - -.L_add_batch: - movl rPROFILE, %eax - movq OFF_FP_METHOD(rFP), OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movw %ax, OFF_FP_COUNTDOWN_OFFSET(rFP) - movq rSELF, OUT_ARG2 - call SYMBOL(MterpAddHotnessBatch) # (method, shadow_frame, self) - movswl %ax, rPROFILE - jmp .L_no_count_backwards - -/* - * Entered from the conditional branch handlers when OSR check request active on - * not-taken path. All Dalvik not-taken conditional branch offsets are 2. - */ -.L_check_not_taken_osr: - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movl $$2, OUT_32_ARG2 - call SYMBOL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) - testb %al, %al - jnz MterpOnStackReplacement - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* - * On-stack replacement has happened, and now we've returned from the compiled method. - */ -MterpOnStackReplacement: -#if MTERP_LOGGING - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movl rINST, OUT_32_ARG2 - call SYMBOL(MterpLogOSR) -#endif - movl $$1, %eax - jmp MterpDone - -/* - * Bail out to reference interpreter. - */ -MterpFallback: - EXPORT_PC -#if MTERP_LOGGING - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - call SYMBOL(MterpLogFallback) -#endif -MterpCommonFallback: - xorl %eax, %eax - jmp MterpDone - -/* - * On entry: - * uint32_t* rFP (should still be live, pointer to base of vregs) - */ -MterpExceptionReturn: - movl $$1, %eax - jmp MterpDone -MterpReturn: - movq OFF_FP_RESULT_REGISTER(rFP), %rdx - movq %rax, (%rdx) - movl $$1, %eax -MterpDone: -/* - * At this point, we expect rPROFILE to be non-zero. If negative, hotness is disabled or we're - * checking for OSR. If greater than zero, we might have unreported hotness to register - * (the difference between the ending rPROFILE and the cached hotness counter). rPROFILE - * should only reach zero immediately after a hotness decrement, and is then reset to either - * a negative special state or the new non-zero countdown value. - */ - testl rPROFILE, rPROFILE - jle MRestoreFrame # if > 0, we may have some counts to report. - - movl %eax, rINST # stash return value - /* Report cached hotness counts */ - movl rPROFILE, %eax - movq OFF_FP_METHOD(rFP), OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movw %ax, OFF_FP_COUNTDOWN_OFFSET(rFP) - movq rSELF, OUT_ARG2 - call SYMBOL(MterpAddHotnessBatch) # (method, shadow_frame, self) - movl rINST, %eax # restore return value - - /* pop up frame */ -MRestoreFrame: - addq $$FRAME_SIZE, %rsp - .cfi_adjust_cfa_offset -FRAME_SIZE - - /* Restore callee save register */ - POP %r15 - POP %r14 - POP %r13 - POP %r12 - POP %rbp - POP %rbx - ret - .cfi_endproc - SIZE(ExecuteMterpImpl,ExecuteMterpImpl) diff --git a/runtime/interpreter/mterp/x86_64/fpcmp.S b/runtime/interpreter/mterp/x86_64/fpcmp.S deleted file mode 100644 index 15161c8bf1..0000000000 --- a/runtime/interpreter/mterp/x86_64/fpcmp.S +++ /dev/null @@ -1,35 +0,0 @@ -%def fpcmp(suff="d", nanval="pos"): -/* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * int compare(x, y) { - * if (x == y) { - * return 0; - * } else if (x < y) { - * return -1; - * } else if (x > y) { - * return 1; - * } else { - * return nanval ? 1 : -1; - * } - * } - */ - /* op vAA, vBB, vCC */ - movzbq 3(rPC), %rcx # ecx<- CC - movzbq 2(rPC), %rax # eax<- BB - movs${suff} VREG_ADDRESS(%rax), %xmm0 - xor %eax, %eax - ucomis${suff} VREG_ADDRESS(%rcx), %xmm0 - jp .L${opcode}_nan_is_${nanval} - je .L${opcode}_finish - jb .L${opcode}_less -.L${opcode}_nan_is_pos: - addb $$1, %al - jmp .L${opcode}_finish -.L${opcode}_nan_is_neg: -.L${opcode}_less: - movl $$-1, %eax -.L${opcode}_finish: - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/fpcvt.S b/runtime/interpreter/mterp/x86_64/fpcvt.S deleted file mode 100644 index 6647ff369c..0000000000 --- a/runtime/interpreter/mterp/x86_64/fpcvt.S +++ /dev/null @@ -1,17 +0,0 @@ -%def fpcvt(source_suffix="", dest_suffix="", wide=""): -/* - * Generic 32-bit FP conversion operation. - */ - /* unop vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $$4, rINST # rINST <- B - andb $$0xf, %cl # ecx <- A - cvts${source_suffix}2s${dest_suffix} VREG_ADDRESS(rINSTq), %xmm0 - .if $wide - movsd %xmm0, VREG_ADDRESS(%rcx) - CLEAR_WIDE_REF %rcx - .else - movss %xmm0, VREG_ADDRESS(%rcx) - CLEAR_REF %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86_64/header.S b/runtime/interpreter/mterp/x86_64/header.S deleted file mode 100644 index 44ece2e42c..0000000000 --- a/runtime/interpreter/mterp/x86_64/header.S +++ /dev/null @@ -1,303 +0,0 @@ -%def header(): -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - Art assembly interpreter notes: - - First validate assembly code by implementing ExecuteXXXImpl() style body (doesn't - handle invoke, allows higher-level code to create frame & shadow frame. - - Once that's working, support direct entry code & eliminate shadow frame (and - excess locals allocation. - - Some (hopefully) temporary ugliness. We'll treat rFP as pointing to the - base of the vreg array within the shadow frame. Access the other fields, - dex_pc_, method_ and number_of_vregs_ via negative offsets. For now, we'll continue - the shadow frame mechanism of double-storing object references - via rFP & - number_of_vregs_. - - */ - -/* -x86_64 ABI general notes: - -Caller save set: - rax, rdx, rcx, rsi, rdi, r8-r11, st(0)-st(7) -Callee save set: - rbx, rbp, r12-r15 -Return regs: - 32-bit in eax - 64-bit in rax - fp on xmm0 - -First 8 fp parameters came in xmm0-xmm7. -First 6 non-fp parameters came in rdi, rsi, rdx, rcx, r8, r9. -Other parameters passed on stack, pushed right-to-left. On entry to target, first -param is at 8(%esp). Traditional entry code is: - -Stack must be 16-byte aligned to support SSE in native code. - -If we're not doing variable stack allocation (alloca), the frame pointer can be -eliminated and all arg references adjusted to be esp relative. -*/ - -/* -Mterp and x86_64 notes: - -Some key interpreter variables will be assigned to registers. - - nick reg purpose - rPROFILE rbp countdown register for jit profiling - rPC r12 interpreted program counter, used for fetching instructions - rFP r13 interpreted frame pointer, used for accessing locals and args - rINSTw bx first 16-bit code of current instruction - rINSTbl bl opcode portion of instruction word - rINSTbh bh high byte of inst word, usually contains src/tgt reg names - rIBASE r14 base of instruction handler table - rREFS r15 base of object references in shadow frame. - -Notes: - o High order 16 bits of ebx must be zero on entry to handler - o rPC, rFP, rINSTw/rINSTbl valid on handler entry and exit - o eax and ecx are scratch, rINSTw/ebx sometimes scratch - -Macros are provided for common operations. Each macro MUST emit only -one instruction to make instruction-counting easier. They MUST NOT alter -unspecified registers or condition codes. -*/ - -/* - * This is a #include, not a %include, because we want the C pre-processor - * to expand the macros into assembler assignment statements. - */ -#include "asm_support.h" -#include "interpreter/cfi_asm_support.h" - -/* - * Handle mac compiler specific - */ -#if defined(__APPLE__) - #define MACRO_LITERAL(value) $$(value) - #define FUNCTION_TYPE(name) - #define OBJECT_TYPE(name) - #define SIZE(start,end) - // Mac OS' symbols have an _ prefix. - #define SYMBOL(name) _ ## name - #define ASM_HIDDEN .private_extern -#else - #define MACRO_LITERAL(value) $$value - #define FUNCTION_TYPE(name) .type name, @function - #define OBJECT_TYPE(name) .type name, @object - #define SIZE(start,end) .size start, .-end - #define SYMBOL(name) name - #define ASM_HIDDEN .hidden -#endif - -.macro PUSH _reg - pushq \_reg - .cfi_adjust_cfa_offset 8 - .cfi_rel_offset \_reg, 0 -.endm - -.macro POP _reg - popq \_reg - .cfi_adjust_cfa_offset -8 - .cfi_restore \_reg -.endm - -/* - * Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs. So, - * to access other shadow frame fields, we need to use a backwards offset. Define those here. - */ -#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) -#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) -#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) -#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) -#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) -#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) -#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) -#define OFF_FP_DEX_INSTRUCTIONS OFF_FP(SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET) -#define OFF_FP_COUNTDOWN_OFFSET OFF_FP(SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET) -#define OFF_FP_SHADOWFRAME (-SHADOWFRAME_VREGS_OFFSET) - -/* Frame size must be 16-byte aligned. - * Remember about 8 bytes for return address + 6 * 8 for spills. - */ -#define FRAME_SIZE 8 - -/* Frame diagram while executing ExecuteMterpImpl, high to low addresses */ -#define IN_ARG3 %rcx -#define IN_ARG2 %rdx -#define IN_ARG1 %rsi -#define IN_ARG0 %rdi -/* Spill offsets relative to %esp */ -#define SELF_SPILL (FRAME_SIZE - 8) -/* Out Args */ -#define OUT_ARG3 %rcx -#define OUT_ARG2 %rdx -#define OUT_ARG1 %rsi -#define OUT_ARG0 %rdi -#define OUT_32_ARG3 %ecx -#define OUT_32_ARG2 %edx -#define OUT_32_ARG1 %esi -#define OUT_32_ARG0 %edi -#define OUT_FP_ARG1 %xmm1 -#define OUT_FP_ARG0 %xmm0 - -/* During bringup, we'll use the shadow frame model instead of rFP */ -/* single-purpose registers, given names for clarity */ -#define rSELF SELF_SPILL(%rsp) -#define rPC %r12 -#define CFI_DEX 12 // DWARF register number of the register holding dex-pc (rPC). -#define CFI_TMP 5 // DWARF register number of the first argument register (rdi). -#define rFP %r13 -#define rINST %ebx -#define rINSTq %rbx -#define rINSTw %bx -#define rINSTbh %bh -#define rINSTbl %bl -#define rIBASE %r14 -#define rREFS %r15 -#define rPROFILE %ebp - -#define MTERP_LOGGING 0 - -/* - * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must - * be done *before* something throws. - * - * It's okay to do this more than once. - * - * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped - * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction - * offset into the code_items_[] array. For effiency, we will "export" the - * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC - * to convert to a dex pc when needed. - */ -.macro EXPORT_PC - movq rPC, OFF_FP_DEX_PC_PTR(rFP) -.endm - -/* - * Refresh handler table. - * IBase handles uses the caller save register so we must restore it after each call. - * Also it is used as a result of some 64-bit operations (like imul) and we should - * restore it in such cases also. - * - */ -.macro REFRESH_IBASE_REG self_reg - movq THREAD_CURRENT_IBASE_OFFSET(\self_reg), rIBASE -.endm -.macro REFRESH_IBASE - movq rSELF, rIBASE - REFRESH_IBASE_REG rIBASE -.endm - -/* - * Refresh rINST. - * At enter to handler rINST does not contain the opcode number. - * However some utilities require the full value, so this macro - * restores the opcode number. - */ -.macro REFRESH_INST _opnum - movb rINSTbl, rINSTbh - movb $$\_opnum, rINSTbl -.endm - -/* - * Fetch the next instruction from rPC into rINSTw. Does not advance rPC. - */ -.macro FETCH_INST - movzwq (rPC), rINSTq -.endm - -/* - * Remove opcode from rINST, compute the address of handler and jump to it. - */ -.macro GOTO_NEXT - movzx rINSTbl,%eax - movzbl rINSTbh,rINST - shll MACRO_LITERAL(${handler_size_bits}), %eax - addq rIBASE, %rax - jmp *%rax -.endm - -/* - * Advance rPC by instruction count. - */ -.macro ADVANCE_PC _count - leaq 2*\_count(rPC), rPC -.endm - -/* - * Advance rPC by instruction count, fetch instruction and jump to handler. - */ -.macro ADVANCE_PC_FETCH_AND_GOTO_NEXT _count - ADVANCE_PC \_count - FETCH_INST - GOTO_NEXT -.endm - -/* - * Get/set the 32-bit value from a Dalvik register. - */ -#define VREG_ADDRESS(_vreg) (rFP,_vreg,4) -#define VREG_REF_ADDRESS(_vreg) (rREFS,_vreg,4) - -.macro GET_VREG _reg _vreg - movl (rFP,\_vreg,4), \_reg -.endm - -/* Read wide value. */ -.macro GET_WIDE_VREG _reg _vreg - movq (rFP,\_vreg,4), \_reg -.endm - -.macro SET_VREG _reg _vreg - movl \_reg, (rFP,\_vreg,4) - movl MACRO_LITERAL(0), (rREFS,\_vreg,4) -.endm - -/* Write wide value. reg is clobbered. */ -.macro SET_WIDE_VREG _reg _vreg - movq \_reg, (rFP,\_vreg,4) - xorq \_reg, \_reg - movq \_reg, (rREFS,\_vreg,4) -.endm - -.macro SET_VREG_OBJECT _reg _vreg - movl \_reg, (rFP,\_vreg,4) - movl \_reg, (rREFS,\_vreg,4) -.endm - -.macro GET_VREG_HIGH _reg _vreg - movl 4(rFP,\_vreg,4), \_reg -.endm - -.macro SET_VREG_HIGH _reg _vreg - movl \_reg, 4(rFP,\_vreg,4) - movl MACRO_LITERAL(0), 4(rREFS,\_vreg,4) -.endm - -.macro CLEAR_REF _vreg - movl MACRO_LITERAL(0), (rREFS,\_vreg,4) -.endm - -.macro CLEAR_WIDE_REF _vreg - movl MACRO_LITERAL(0), (rREFS,\_vreg,4) - movl MACRO_LITERAL(0), 4(rREFS,\_vreg,4) -.endm diff --git a/runtime/interpreter/mterp/x86_64/instruction_end.S b/runtime/interpreter/mterp/x86_64/instruction_end.S deleted file mode 100644 index 5a24b66dec..0000000000 --- a/runtime/interpreter/mterp/x86_64/instruction_end.S +++ /dev/null @@ -1,6 +0,0 @@ -%def instruction_end(): - - OBJECT_TYPE(artMterpAsmInstructionEnd) - ASM_HIDDEN SYMBOL(artMterpAsmInstructionEnd) - .global SYMBOL(artMterpAsmInstructionEnd) -SYMBOL(artMterpAsmInstructionEnd): diff --git a/runtime/interpreter/mterp/x86_64/instruction_end_alt.S b/runtime/interpreter/mterp/x86_64/instruction_end_alt.S deleted file mode 100644 index d037db988c..0000000000 --- a/runtime/interpreter/mterp/x86_64/instruction_end_alt.S +++ /dev/null @@ -1,6 +0,0 @@ -%def instruction_end_alt(): - - OBJECT_TYPE(artMterpAsmAltInstructionEnd) - ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionEnd) - .global SYMBOL(artMterpAsmAltInstructionEnd) -SYMBOL(artMterpAsmAltInstructionEnd): diff --git a/runtime/interpreter/mterp/x86_64/instruction_end_sister.S b/runtime/interpreter/mterp/x86_64/instruction_end_sister.S deleted file mode 100644 index 7b1ec89d60..0000000000 --- a/runtime/interpreter/mterp/x86_64/instruction_end_sister.S +++ /dev/null @@ -1,6 +0,0 @@ -%def instruction_end_sister(): - - OBJECT_TYPE(artMterpAsmSisterEnd) - ASM_HIDDEN SYMBOL(artMterpAsmSisterEnd) - .global SYMBOL(artMterpAsmSisterEnd) -SYMBOL(artMterpAsmSisterEnd): diff --git a/runtime/interpreter/mterp/x86_64/instruction_start.S b/runtime/interpreter/mterp/x86_64/instruction_start.S deleted file mode 100644 index dee581b60f..0000000000 --- a/runtime/interpreter/mterp/x86_64/instruction_start.S +++ /dev/null @@ -1,7 +0,0 @@ -%def instruction_start(): - - OBJECT_TYPE(artMterpAsmInstructionStart) - ASM_HIDDEN SYMBOL(artMterpAsmInstructionStart) - .global SYMBOL(artMterpAsmInstructionStart) -SYMBOL(artMterpAsmInstructionStart) = .L_op_nop - .text diff --git a/runtime/interpreter/mterp/x86_64/instruction_start_alt.S b/runtime/interpreter/mterp/x86_64/instruction_start_alt.S deleted file mode 100644 index 66650e7a6e..0000000000 --- a/runtime/interpreter/mterp/x86_64/instruction_start_alt.S +++ /dev/null @@ -1,7 +0,0 @@ -%def instruction_start_alt(): - - OBJECT_TYPE(artMterpAsmAltInstructionStart) - ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionStart) - .global SYMBOL(artMterpAsmAltInstructionStart) - .text -SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop diff --git a/runtime/interpreter/mterp/x86_64/instruction_start_sister.S b/runtime/interpreter/mterp/x86_64/instruction_start_sister.S deleted file mode 100644 index 8c156adf7e..0000000000 --- a/runtime/interpreter/mterp/x86_64/instruction_start_sister.S +++ /dev/null @@ -1,8 +0,0 @@ -%def instruction_start_sister(): - - OBJECT_TYPE(artMterpAsmSisterStart) - ASM_HIDDEN SYMBOL(artMterpAsmSisterStart) - .global SYMBOL(artMterpAsmSisterStart) - .text - .balign 4 -SYMBOL(artMterpAsmSisterStart): diff --git a/runtime/interpreter/mterp/x86_64/invoke.S b/runtime/interpreter/mterp/x86_64/invoke.S index 42b50f269e..63c233c4eb 100644 --- a/runtime/interpreter/mterp/x86_64/invoke.S +++ b/runtime/interpreter/mterp/x86_64/invoke.S @@ -20,3 +20,96 @@ jnz MterpFallback FETCH_INST GOTO_NEXT + +%def invoke_polymorphic(helper="UndefinedInvokeHandler"): + /* + * invoke-polymorphic handler wrapper. + */ + /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ + /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ + .extern $helper + EXPORT_PC + movq rSELF, OUT_ARG0 + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 + movq rPC, OUT_ARG2 + REFRESH_INST ${opnum} + movl rINST, OUT_32_ARG3 + call SYMBOL($helper) + testb %al, %al + jz MterpException + ADVANCE_PC 4 + call SYMBOL(MterpShouldSwitchInterpreters) + testb %al, %al + jnz MterpFallback + FETCH_INST + GOTO_NEXT + +%def op_invoke_custom(): +% invoke(helper="MterpInvokeCustom") + +%def op_invoke_custom_range(): +% invoke(helper="MterpInvokeCustomRange") + +%def op_invoke_direct(): +% invoke(helper="MterpInvokeDirect") + +%def op_invoke_direct_range(): +% invoke(helper="MterpInvokeDirectRange") + +%def op_invoke_interface(): +% invoke(helper="MterpInvokeInterface") +/* + * Handle an interface method call. + * + * for: invoke-interface, invoke-interface/range + */ + /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ + /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ + +%def op_invoke_interface_range(): +% invoke(helper="MterpInvokeInterfaceRange") + +%def op_invoke_polymorphic(): +% invoke_polymorphic(helper="MterpInvokePolymorphic") + +%def op_invoke_polymorphic_range(): +% invoke_polymorphic(helper="MterpInvokePolymorphicRange") + +%def op_invoke_static(): +% invoke(helper="MterpInvokeStatic") + + +%def op_invoke_static_range(): +% invoke(helper="MterpInvokeStaticRange") + +%def op_invoke_super(): +% invoke(helper="MterpInvokeSuper") +/* + * Handle a "super" method call. + * + * for: invoke-super, invoke-super/range + */ + /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ + /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ + +%def op_invoke_super_range(): +% invoke(helper="MterpInvokeSuperRange") + +%def op_invoke_virtual(): +% invoke(helper="MterpInvokeVirtual") +/* + * Handle a virtual method call. + * + * for: invoke-virtual, invoke-virtual/range + */ + /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ + /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ + +%def op_invoke_virtual_quick(): +% invoke(helper="MterpInvokeVirtualQuick") + +%def op_invoke_virtual_range(): +% invoke(helper="MterpInvokeVirtualRange") + +%def op_invoke_virtual_range_quick(): +% invoke(helper="MterpInvokeVirtualQuickRange") diff --git a/runtime/interpreter/mterp/x86_64/invoke_polymorphic.S b/runtime/interpreter/mterp/x86_64/invoke_polymorphic.S deleted file mode 100644 index 18fd5e6125..0000000000 --- a/runtime/interpreter/mterp/x86_64/invoke_polymorphic.S +++ /dev/null @@ -1,22 +0,0 @@ -%def invoke_polymorphic(helper="UndefinedInvokeHandler"): - /* - * invoke-polymorphic handler wrapper. - */ - /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ - .extern $helper - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - REFRESH_INST ${opnum} - movl rINST, OUT_32_ARG3 - call SYMBOL($helper) - testb %al, %al - jz MterpException - ADVANCE_PC 4 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - FETCH_INST - GOTO_NEXT diff --git a/runtime/interpreter/mterp/x86_64/main.S b/runtime/interpreter/mterp/x86_64/main.S new file mode 100644 index 0000000000..aa47c6de8a --- /dev/null +++ b/runtime/interpreter/mterp/x86_64/main.S @@ -0,0 +1,753 @@ +%def header(): +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + Art assembly interpreter notes: + + First validate assembly code by implementing ExecuteXXXImpl() style body (doesn't + handle invoke, allows higher-level code to create frame & shadow frame. + + Once that's working, support direct entry code & eliminate shadow frame (and + excess locals allocation. + + Some (hopefully) temporary ugliness. We'll treat rFP as pointing to the + base of the vreg array within the shadow frame. Access the other fields, + dex_pc_, method_ and number_of_vregs_ via negative offsets. For now, we'll continue + the shadow frame mechanism of double-storing object references - via rFP & + number_of_vregs_. + + */ + +/* +x86_64 ABI general notes: + +Caller save set: + rax, rdx, rcx, rsi, rdi, r8-r11, st(0)-st(7) +Callee save set: + rbx, rbp, r12-r15 +Return regs: + 32-bit in eax + 64-bit in rax + fp on xmm0 + +First 8 fp parameters came in xmm0-xmm7. +First 6 non-fp parameters came in rdi, rsi, rdx, rcx, r8, r9. +Other parameters passed on stack, pushed right-to-left. On entry to target, first +param is at 8(%esp). Traditional entry code is: + +Stack must be 16-byte aligned to support SSE in native code. + +If we're not doing variable stack allocation (alloca), the frame pointer can be +eliminated and all arg references adjusted to be esp relative. +*/ + +/* +Mterp and x86_64 notes: + +Some key interpreter variables will be assigned to registers. + + nick reg purpose + rPROFILE rbp countdown register for jit profiling + rPC r12 interpreted program counter, used for fetching instructions + rFP r13 interpreted frame pointer, used for accessing locals and args + rINSTw bx first 16-bit code of current instruction + rINSTbl bl opcode portion of instruction word + rINSTbh bh high byte of inst word, usually contains src/tgt reg names + rIBASE r14 base of instruction handler table + rREFS r15 base of object references in shadow frame. + +Notes: + o High order 16 bits of ebx must be zero on entry to handler + o rPC, rFP, rINSTw/rINSTbl valid on handler entry and exit + o eax and ecx are scratch, rINSTw/ebx sometimes scratch + +Macros are provided for common operations. Each macro MUST emit only +one instruction to make instruction-counting easier. They MUST NOT alter +unspecified registers or condition codes. +*/ + +/* + * This is a #include, not a %include, because we want the C pre-processor + * to expand the macros into assembler assignment statements. + */ +#include "asm_support.h" +#include "interpreter/cfi_asm_support.h" + +/* + * Handle mac compiler specific + */ +#if defined(__APPLE__) + #define MACRO_LITERAL(value) $$(value) + #define FUNCTION_TYPE(name) + #define OBJECT_TYPE(name) + #define SIZE(start,end) + // Mac OS' symbols have an _ prefix. + #define SYMBOL(name) _ ## name + #define ASM_HIDDEN .private_extern +#else + #define MACRO_LITERAL(value) $$value + #define FUNCTION_TYPE(name) .type name, @function + #define OBJECT_TYPE(name) .type name, @object + #define SIZE(start,end) .size start, .-end + #define SYMBOL(name) name + #define ASM_HIDDEN .hidden +#endif + +.macro PUSH _reg + pushq \_reg + .cfi_adjust_cfa_offset 8 + .cfi_rel_offset \_reg, 0 +.endm + +.macro POP _reg + popq \_reg + .cfi_adjust_cfa_offset -8 + .cfi_restore \_reg +.endm + +/* + * Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs. So, + * to access other shadow frame fields, we need to use a backwards offset. Define those here. + */ +#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) +#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) +#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) +#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) +#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) +#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) +#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) +#define OFF_FP_DEX_INSTRUCTIONS OFF_FP(SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET) +#define OFF_FP_COUNTDOWN_OFFSET OFF_FP(SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET) +#define OFF_FP_SHADOWFRAME (-SHADOWFRAME_VREGS_OFFSET) + +/* Frame size must be 16-byte aligned. + * Remember about 8 bytes for return address + 6 * 8 for spills. + */ +#define FRAME_SIZE 8 + +/* Frame diagram while executing ExecuteMterpImpl, high to low addresses */ +#define IN_ARG3 %rcx +#define IN_ARG2 %rdx +#define IN_ARG1 %rsi +#define IN_ARG0 %rdi +/* Spill offsets relative to %esp */ +#define SELF_SPILL (FRAME_SIZE - 8) +/* Out Args */ +#define OUT_ARG3 %rcx +#define OUT_ARG2 %rdx +#define OUT_ARG1 %rsi +#define OUT_ARG0 %rdi +#define OUT_32_ARG3 %ecx +#define OUT_32_ARG2 %edx +#define OUT_32_ARG1 %esi +#define OUT_32_ARG0 %edi +#define OUT_FP_ARG1 %xmm1 +#define OUT_FP_ARG0 %xmm0 + +/* During bringup, we'll use the shadow frame model instead of rFP */ +/* single-purpose registers, given names for clarity */ +#define rSELF SELF_SPILL(%rsp) +#define rPC %r12 +#define CFI_DEX 12 // DWARF register number of the register holding dex-pc (rPC). +#define CFI_TMP 5 // DWARF register number of the first argument register (rdi). +#define rFP %r13 +#define rINST %ebx +#define rINSTq %rbx +#define rINSTw %bx +#define rINSTbh %bh +#define rINSTbl %bl +#define rIBASE %r14 +#define rREFS %r15 +#define rPROFILE %ebp + +#define MTERP_LOGGING 0 + +/* + * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must + * be done *before* something throws. + * + * It's okay to do this more than once. + * + * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped + * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction + * offset into the code_items_[] array. For effiency, we will "export" the + * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC + * to convert to a dex pc when needed. + */ +.macro EXPORT_PC + movq rPC, OFF_FP_DEX_PC_PTR(rFP) +.endm + +/* + * Refresh handler table. + * IBase handles uses the caller save register so we must restore it after each call. + * Also it is used as a result of some 64-bit operations (like imul) and we should + * restore it in such cases also. + * + */ +.macro REFRESH_IBASE_REG self_reg + movq THREAD_CURRENT_IBASE_OFFSET(\self_reg), rIBASE +.endm +.macro REFRESH_IBASE + movq rSELF, rIBASE + REFRESH_IBASE_REG rIBASE +.endm + +/* + * Refresh rINST. + * At enter to handler rINST does not contain the opcode number. + * However some utilities require the full value, so this macro + * restores the opcode number. + */ +.macro REFRESH_INST _opnum + movb rINSTbl, rINSTbh + movb $$\_opnum, rINSTbl +.endm + +/* + * Fetch the next instruction from rPC into rINSTw. Does not advance rPC. + */ +.macro FETCH_INST + movzwq (rPC), rINSTq +.endm + +/* + * Remove opcode from rINST, compute the address of handler and jump to it. + */ +.macro GOTO_NEXT + movzx rINSTbl,%eax + movzbl rINSTbh,rINST + shll MACRO_LITERAL(${handler_size_bits}), %eax + addq rIBASE, %rax + jmp *%rax +.endm + +/* + * Advance rPC by instruction count. + */ +.macro ADVANCE_PC _count + leaq 2*\_count(rPC), rPC +.endm + +/* + * Advance rPC by instruction count, fetch instruction and jump to handler. + */ +.macro ADVANCE_PC_FETCH_AND_GOTO_NEXT _count + ADVANCE_PC \_count + FETCH_INST + GOTO_NEXT +.endm + +/* + * Get/set the 32-bit value from a Dalvik register. + */ +#define VREG_ADDRESS(_vreg) (rFP,_vreg,4) +#define VREG_REF_ADDRESS(_vreg) (rREFS,_vreg,4) + +.macro GET_VREG _reg _vreg + movl (rFP,\_vreg,4), \_reg +.endm + +/* Read wide value. */ +.macro GET_WIDE_VREG _reg _vreg + movq (rFP,\_vreg,4), \_reg +.endm + +.macro SET_VREG _reg _vreg + movl \_reg, (rFP,\_vreg,4) + movl MACRO_LITERAL(0), (rREFS,\_vreg,4) +.endm + +/* Write wide value. reg is clobbered. */ +.macro SET_WIDE_VREG _reg _vreg + movq \_reg, (rFP,\_vreg,4) + xorq \_reg, \_reg + movq \_reg, (rREFS,\_vreg,4) +.endm + +.macro SET_VREG_OBJECT _reg _vreg + movl \_reg, (rFP,\_vreg,4) + movl \_reg, (rREFS,\_vreg,4) +.endm + +.macro GET_VREG_HIGH _reg _vreg + movl 4(rFP,\_vreg,4), \_reg +.endm + +.macro SET_VREG_HIGH _reg _vreg + movl \_reg, 4(rFP,\_vreg,4) + movl MACRO_LITERAL(0), 4(rREFS,\_vreg,4) +.endm + +.macro CLEAR_REF _vreg + movl MACRO_LITERAL(0), (rREFS,\_vreg,4) +.endm + +.macro CLEAR_WIDE_REF _vreg + movl MACRO_LITERAL(0), (rREFS,\_vreg,4) + movl MACRO_LITERAL(0), 4(rREFS,\_vreg,4) +.endm + +%def entry(): +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* + * Interpreter entry point. + */ + + .text + ASM_HIDDEN SYMBOL(ExecuteMterpImpl) + .global SYMBOL(ExecuteMterpImpl) + FUNCTION_TYPE(ExecuteMterpImpl) + +/* + * On entry: + * 0 Thread* self + * 1 insns_ + * 2 ShadowFrame + * 3 JValue* result_register + * + */ + +SYMBOL(ExecuteMterpImpl): + .cfi_startproc + .cfi_def_cfa rsp, 8 + + /* Spill callee save regs */ + PUSH %rbx + PUSH %rbp + PUSH %r12 + PUSH %r13 + PUSH %r14 + PUSH %r15 + + /* Allocate frame */ + subq $$FRAME_SIZE, %rsp + .cfi_adjust_cfa_offset FRAME_SIZE + + /* Remember the return register */ + movq IN_ARG3, SHADOWFRAME_RESULT_REGISTER_OFFSET(IN_ARG2) + + /* Remember the code_item */ + movq IN_ARG1, SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET(IN_ARG2) + + /* set up "named" registers */ + movl SHADOWFRAME_NUMBER_OF_VREGS_OFFSET(IN_ARG2), %eax + leaq SHADOWFRAME_VREGS_OFFSET(IN_ARG2), rFP + leaq (rFP, %rax, 4), rREFS + movl SHADOWFRAME_DEX_PC_OFFSET(IN_ARG2), %eax + leaq (IN_ARG1, %rax, 2), rPC + CFI_DEFINE_DEX_PC_WITH_OFFSET(CFI_TMP, CFI_DEX, 0) + EXPORT_PC + + /* Starting ibase */ + movq IN_ARG0, rSELF + REFRESH_IBASE_REG IN_ARG0 + + /* Set up for backwards branches & osr profiling */ + movq IN_ARG0, OUT_ARG2 /* Set up OUT_ARG2 before clobbering IN_ARG0 */ + movq OFF_FP_METHOD(rFP), OUT_ARG0 + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 + call SYMBOL(MterpSetUpHotnessCountdown) + movswl %ax, rPROFILE + + /* start executing the instruction at rPC */ + FETCH_INST + GOTO_NEXT + /* NOTE: no fallthrough */ + +%def alt_stub(): +/* + * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle + * any interesting requests and then jump to the real instruction + * handler. Unlike the Arm handler, we can't do this as a tail call + * because rIBASE is caller save and we need to reload it. + * + * Note that unlike in the Arm implementation, we should never arrive + * here with a zero breakFlag because we always refresh rIBASE on + * return. + */ + .extern MterpCheckBefore + REFRESH_IBASE + movq rSELF, OUT_ARG0 + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 + movq rPC, OUT_ARG2 + call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) + jmp .L_op_nop+(${opnum}*${handler_size_bytes}) + +%def fallback(): +/* Transfer stub to alternate interpreter */ + jmp MterpFallback + + +%def footer(): +/* + * =========================================================================== + * Common subroutines and data + * =========================================================================== + */ + + .text + .align 2 + +/* + * We've detected a condition that will result in an exception, but the exception + * has not yet been thrown. Just bail out to the reference interpreter to deal with it. + * TUNING: for consistency, we may want to just go ahead and handle these here. + */ +common_errDivideByZero: + EXPORT_PC +#if MTERP_LOGGING + movq rSELF, OUT_ARG0 + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 + call SYMBOL(MterpLogDivideByZeroException) +#endif + jmp MterpCommonFallback + +common_errArrayIndex: + EXPORT_PC +#if MTERP_LOGGING + movq rSELF, OUT_ARG0 + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 + call SYMBOL(MterpLogArrayIndexException) +#endif + jmp MterpCommonFallback + +common_errNegativeArraySize: + EXPORT_PC +#if MTERP_LOGGING + movq rSELF, OUT_ARG0 + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 + call SYMBOL(MterpLogNegativeArraySizeException) +#endif + jmp MterpCommonFallback + +common_errNoSuchMethod: + EXPORT_PC +#if MTERP_LOGGING + movq rSELF, OUT_ARG0 + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 + call SYMBOL(MterpLogNoSuchMethodException) +#endif + jmp MterpCommonFallback + +common_errNullObject: + EXPORT_PC +#if MTERP_LOGGING + movq rSELF, OUT_ARG0 + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 + call SYMBOL(MterpLogNullObjectException) +#endif + jmp MterpCommonFallback + +common_exceptionThrown: + EXPORT_PC +#if MTERP_LOGGING + movq rSELF, OUT_ARG0 + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 + call SYMBOL(MterpLogExceptionThrownException) +#endif + jmp MterpCommonFallback + +MterpSuspendFallback: + EXPORT_PC +#if MTERP_LOGGING + movq rSELF, OUT_ARG0 + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 + movl THREAD_FLAGS_OFFSET(OUT_ARG0), OUT_32_ARG2 + call SYMBOL(MterpLogSuspendFallback) +#endif + jmp MterpCommonFallback + +/* + * If we're here, something is out of the ordinary. If there is a pending + * exception, handle it. Otherwise, roll back and retry with the reference + * interpreter. + */ +MterpPossibleException: + movq rSELF, %rcx + cmpq $$0, THREAD_EXCEPTION_OFFSET(%rcx) + jz MterpFallback + /* intentional fallthrough - handle pending exception. */ + +/* + * On return from a runtime helper routine, we've found a pending exception. + * Can we handle it here - or need to bail out to caller? + * + */ +MterpException: + movq rSELF, OUT_ARG0 + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 + call SYMBOL(MterpHandleException) + testb %al, %al + jz MterpExceptionReturn + movq OFF_FP_DEX_INSTRUCTIONS(rFP), %rax + mov OFF_FP_DEX_PC(rFP), %ecx + leaq (%rax, %rcx, 2), rPC + movq rPC, OFF_FP_DEX_PC_PTR(rFP) + /* Do we need to switch interpreters? */ + call SYMBOL(MterpShouldSwitchInterpreters) + testb %al, %al + jnz MterpFallback + /* resume execution at catch block */ + REFRESH_IBASE + FETCH_INST + GOTO_NEXT + /* NOTE: no fallthrough */ + +/* + * Common handling for branches with support for Jit profiling. + * On entry: + * rINST <= signed offset + * rPROFILE <= signed hotness countdown (expanded to 32 bits) + * condition bits <= set to establish sign of offset (use "NoFlags" entry if not) + * + * We have quite a few different cases for branch profiling, OSR detection and + * suspend check support here. + * + * Taken backward branches: + * If profiling active, do hotness countdown and report if we hit zero. + * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. + * Is there a pending suspend request? If so, suspend. + * + * Taken forward branches and not-taken backward branches: + * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. + * + * Our most common case is expected to be a taken backward branch with active jit profiling, + * but no full OSR check and no pending suspend request. + * Next most common case is not-taken branch with no full OSR check. + * + */ +MterpCommonTakenBranch: + jg .L_forward_branch # don't add forward branches to hotness +/* + * We need to subtract 1 from positive values and we should not see 0 here, + * so we may use the result of the comparison with -1. + */ +#if JIT_CHECK_OSR != -1 +# error "JIT_CHECK_OSR must be -1." +#endif + cmpl $$JIT_CHECK_OSR, rPROFILE + je .L_osr_check + decl rPROFILE + je .L_add_batch # counted down to zero - report +.L_resume_backward_branch: + movq rSELF, %rax + testl $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(%rax) + REFRESH_IBASE_REG %rax + leaq (rPC, rINSTq, 2), rPC + FETCH_INST + jnz .L_suspend_request_pending + GOTO_NEXT + +.L_suspend_request_pending: + EXPORT_PC + movq rSELF, OUT_ARG0 + call SYMBOL(MterpSuspendCheck) # (self) + testb %al, %al + jnz MterpFallback + REFRESH_IBASE # might have changed during suspend + GOTO_NEXT + +.L_no_count_backwards: + cmpl $$JIT_CHECK_OSR, rPROFILE # possible OSR re-entry? + jne .L_resume_backward_branch +.L_osr_check: + EXPORT_PC + movq rSELF, OUT_ARG0 + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 + movq rINSTq, OUT_ARG2 + call SYMBOL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) + testb %al, %al + jz .L_resume_backward_branch + jmp MterpOnStackReplacement + +.L_forward_branch: + cmpl $$JIT_CHECK_OSR, rPROFILE # possible OSR re-entry? + je .L_check_osr_forward +.L_resume_forward_branch: + leaq (rPC, rINSTq, 2), rPC + FETCH_INST + GOTO_NEXT + +.L_check_osr_forward: + EXPORT_PC + movq rSELF, OUT_ARG0 + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 + movq rINSTq, OUT_ARG2 + call SYMBOL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) + testb %al, %al + jz .L_resume_forward_branch + jmp MterpOnStackReplacement + +.L_add_batch: + movl rPROFILE, %eax + movq OFF_FP_METHOD(rFP), OUT_ARG0 + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 + movw %ax, OFF_FP_COUNTDOWN_OFFSET(rFP) + movq rSELF, OUT_ARG2 + call SYMBOL(MterpAddHotnessBatch) # (method, shadow_frame, self) + movswl %ax, rPROFILE + jmp .L_no_count_backwards + +/* + * Entered from the conditional branch handlers when OSR check request active on + * not-taken path. All Dalvik not-taken conditional branch offsets are 2. + */ +.L_check_not_taken_osr: + EXPORT_PC + movq rSELF, OUT_ARG0 + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 + movl $$2, OUT_32_ARG2 + call SYMBOL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) + testb %al, %al + jnz MterpOnStackReplacement + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +/* + * On-stack replacement has happened, and now we've returned from the compiled method. + */ +MterpOnStackReplacement: +#if MTERP_LOGGING + movq rSELF, OUT_ARG0 + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 + movl rINST, OUT_32_ARG2 + call SYMBOL(MterpLogOSR) +#endif + movl $$1, %eax + jmp MterpDone + +/* + * Bail out to reference interpreter. + */ +MterpFallback: + EXPORT_PC +#if MTERP_LOGGING + movq rSELF, OUT_ARG0 + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 + call SYMBOL(MterpLogFallback) +#endif +MterpCommonFallback: + xorl %eax, %eax + jmp MterpDone + +/* + * On entry: + * uint32_t* rFP (should still be live, pointer to base of vregs) + */ +MterpExceptionReturn: + movl $$1, %eax + jmp MterpDone +MterpReturn: + movq OFF_FP_RESULT_REGISTER(rFP), %rdx + movq %rax, (%rdx) + movl $$1, %eax +MterpDone: +/* + * At this point, we expect rPROFILE to be non-zero. If negative, hotness is disabled or we're + * checking for OSR. If greater than zero, we might have unreported hotness to register + * (the difference between the ending rPROFILE and the cached hotness counter). rPROFILE + * should only reach zero immediately after a hotness decrement, and is then reset to either + * a negative special state or the new non-zero countdown value. + */ + testl rPROFILE, rPROFILE + jle MRestoreFrame # if > 0, we may have some counts to report. + + movl %eax, rINST # stash return value + /* Report cached hotness counts */ + movl rPROFILE, %eax + movq OFF_FP_METHOD(rFP), OUT_ARG0 + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 + movw %ax, OFF_FP_COUNTDOWN_OFFSET(rFP) + movq rSELF, OUT_ARG2 + call SYMBOL(MterpAddHotnessBatch) # (method, shadow_frame, self) + movl rINST, %eax # restore return value + + /* pop up frame */ +MRestoreFrame: + addq $$FRAME_SIZE, %rsp + .cfi_adjust_cfa_offset -FRAME_SIZE + + /* Restore callee save register */ + POP %r15 + POP %r14 + POP %r13 + POP %r12 + POP %rbp + POP %rbx + ret + .cfi_endproc + SIZE(ExecuteMterpImpl,ExecuteMterpImpl) + +%def instruction_end(): + + OBJECT_TYPE(artMterpAsmInstructionEnd) + ASM_HIDDEN SYMBOL(artMterpAsmInstructionEnd) + .global SYMBOL(artMterpAsmInstructionEnd) +SYMBOL(artMterpAsmInstructionEnd): + +%def instruction_end_alt(): + + OBJECT_TYPE(artMterpAsmAltInstructionEnd) + ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionEnd) + .global SYMBOL(artMterpAsmAltInstructionEnd) +SYMBOL(artMterpAsmAltInstructionEnd): + +%def instruction_end_sister(): + + OBJECT_TYPE(artMterpAsmSisterEnd) + ASM_HIDDEN SYMBOL(artMterpAsmSisterEnd) + .global SYMBOL(artMterpAsmSisterEnd) +SYMBOL(artMterpAsmSisterEnd): + +%def instruction_start(): + + OBJECT_TYPE(artMterpAsmInstructionStart) + ASM_HIDDEN SYMBOL(artMterpAsmInstructionStart) + .global SYMBOL(artMterpAsmInstructionStart) +SYMBOL(artMterpAsmInstructionStart) = .L_op_nop + .text + +%def instruction_start_alt(): + + OBJECT_TYPE(artMterpAsmAltInstructionStart) + ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionStart) + .global SYMBOL(artMterpAsmAltInstructionStart) + .text +SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop + +%def instruction_start_sister(): + + OBJECT_TYPE(artMterpAsmSisterStart) + ASM_HIDDEN SYMBOL(artMterpAsmSisterStart) + .global SYMBOL(artMterpAsmSisterStart) + .text + .balign 4 +SYMBOL(artMterpAsmSisterStart): diff --git a/runtime/interpreter/mterp/x86_64/object.S b/runtime/interpreter/mterp/x86_64/object.S new file mode 100644 index 0000000000..fa85f69404 --- /dev/null +++ b/runtime/interpreter/mterp/x86_64/object.S @@ -0,0 +1,254 @@ +%def field(helper=""): + /* + * General field read / write (iget-* iput-* sget-* sput-*). + */ + .extern $helper + REFRESH_INST ${opnum} # fix rINST to include opcode + movq rPC, OUT_ARG0 # arg0: Instruction* inst + movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf + movq rSELF, OUT_ARG3 # arg3: Thread* self + call SYMBOL($helper) + testb %al, %al + jz MterpPossibleException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_check_cast(): +/* + * Check to see if a cast from one class to another is allowed. + */ + /* check-cast vAA, class@BBBB */ + EXPORT_PC + movzwq 2(rPC), OUT_ARG0 # OUT_ARG0 <- BBBB + leaq VREG_ADDRESS(rINSTq), OUT_ARG1 + movq OFF_FP_METHOD(rFP), OUT_ARG2 + movq rSELF, OUT_ARG3 + call SYMBOL(MterpCheckCast) # (index, &obj, method, self) + testb %al, %al + jnz MterpPossibleException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_iget(is_object="0", helper="MterpIGetU32"): +% field(helper=helper) + +%def op_iget_boolean(): +% op_iget(helper="MterpIGetU8") + +%def op_iget_boolean_quick(): +% op_iget_quick(load="movsbl") + +%def op_iget_byte(): +% op_iget(helper="MterpIGetI8") + +%def op_iget_byte_quick(): +% op_iget_quick(load="movsbl") + +%def op_iget_char(): +% op_iget(helper="MterpIGetU16") + +%def op_iget_char_quick(): +% op_iget_quick(load="movzwl") + +%def op_iget_object(): +% op_iget(is_object="1", helper="MterpIGetObj") + +%def op_iget_object_quick(): + /* For: iget-object-quick */ + /* op vA, vB, offset@CCCC */ + .extern artIGetObjectFromMterp + movzbq rINSTbl, %rcx # rcx <- BA + sarl $$4, %ecx # ecx <- B + GET_VREG OUT_32_ARG0, %rcx # vB (object we're operating on) + movzwl 2(rPC), OUT_32_ARG1 # eax <- field byte offset + EXPORT_PC + callq SYMBOL(artIGetObjectFromMterp) # (obj, offset) + movq rSELF, %rcx + cmpq $$0, THREAD_EXCEPTION_OFFSET(%rcx) + jnz MterpException # bail out + andb $$0xf, rINSTbl # rINST <- A + SET_VREG_OBJECT %eax, rINSTq # fp[A] <- value + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_iget_quick(load="movl", wide="0"): + /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick, iget-wide-quick */ + /* op vA, vB, offset@CCCC */ + movl rINST, %ecx # rcx <- BA + sarl $$4, %ecx # ecx <- B + GET_VREG %ecx, %rcx # vB (object we're operating on) + movzwq 2(rPC), %rax # eax <- field byte offset + testl %ecx, %ecx # is object null? + je common_errNullObject + andb $$0xf,rINSTbl # rINST <- A + .if $wide + movq (%rcx,%rax,1), %rax + SET_WIDE_VREG %rax, rINSTq # fp[A] <- value + .else + ${load} (%rcx,%rax,1), %eax + SET_VREG %eax, rINSTq # fp[A] <- value + .endif + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_iget_short(): +% op_iget(helper="MterpIGetI16") + +%def op_iget_short_quick(): +% op_iget_quick(load="movswl") + +%def op_iget_wide(): +% op_iget(helper="MterpIGetU64") + +%def op_iget_wide_quick(): +% op_iget_quick(load="movswl", wide="1") + +%def op_instance_of(): +/* + * Check to see if an object reference is an instance of a class. + * + * Most common situation is a non-null object, being compared against + * an already-resolved class. + */ + /* instance-of vA, vB, class@CCCC */ + EXPORT_PC + movzwl 2(rPC), OUT_32_ARG0 # OUT_32_ARG0 <- CCCC + movl rINST, %eax # eax <- BA + sarl $$4, %eax # eax <- B + leaq VREG_ADDRESS(%rax), OUT_ARG1 # Get object address + movq OFF_FP_METHOD(rFP), OUT_ARG2 + movq rSELF, OUT_ARG3 + call SYMBOL(MterpInstanceOf) # (index, &obj, method, self) + movsbl %al, %eax + movq rSELF, %rcx + cmpq $$0, THREAD_EXCEPTION_OFFSET(%rcx) + jnz MterpException + andb $$0xf, rINSTbl # rINSTbl <- A + SET_VREG %eax, rINSTq + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_iput(is_object="0", helper="MterpIPutU32"): +% field(helper=helper) + +%def op_iput_boolean(): +% op_iput(helper="MterpIPutU8") + +%def op_iput_boolean_quick(): +% op_iput_quick(reg="rINSTbl", store="movb") + +%def op_iput_byte(): +% op_iput(helper="MterpIPutI8") + +%def op_iput_byte_quick(): +% op_iput_quick(reg="rINSTbl", store="movb") + +%def op_iput_char(): +% op_iput(helper="MterpIPutU16") + +%def op_iput_char_quick(): +% op_iput_quick(reg="rINSTw", store="movw") + +%def op_iput_object(): +% op_iput(is_object="1", helper="MterpIPutObj") + +%def op_iput_object_quick(): + EXPORT_PC + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG0 + movq rPC, OUT_ARG1 + REFRESH_INST ${opnum} + movl rINST, OUT_32_ARG2 + call SYMBOL(MterpIputObjectQuick) + testb %al, %al + jz MterpException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_iput_quick(reg="rINST", store="movl"): + /* For: iput-quick, iput-object-quick */ + /* op vA, vB, offset@CCCC */ + movzbq rINSTbl, %rcx # rcx <- BA + sarl $$4, %ecx # ecx <- B + GET_VREG %ecx, %rcx # vB (object we're operating on) + testl %ecx, %ecx # is object null? + je common_errNullObject + andb $$0xf, rINSTbl # rINST <- A + GET_VREG rINST, rINSTq # rINST <- v[A] + movzwq 2(rPC), %rax # rax <- field byte offset + ${store} ${reg}, (%rcx,%rax,1) + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_iput_short(): +% op_iput(helper="MterpIPutI16") + +%def op_iput_short_quick(): +% op_iput_quick(reg="rINSTw", store="movw") + +%def op_iput_wide(): +% op_iput(helper="MterpIPutU64") + +%def op_iput_wide_quick(): + /* iput-wide-quick vA, vB, offset@CCCC */ + movzbq rINSTbl, %rcx # rcx<- BA + sarl $$4, %ecx # ecx<- B + GET_VREG %ecx, %rcx # vB (object we're operating on) + testl %ecx, %ecx # is object null? + je common_errNullObject + movzwq 2(rPC), %rax # rax<- field byte offset + leaq (%rcx,%rax,1), %rcx # ecx<- Address of 64-bit target + andb $$0xf, rINSTbl # rINST<- A + GET_WIDE_VREG %rax, rINSTq # rax<- fp[A]/fp[A+1] + movq %rax, (%rcx) # obj.field<- r0/r1 + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_new_instance(): +/* + * Create a new instance of a class. + */ + /* new-instance vAA, class@BBBB */ + EXPORT_PC + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG0 + movq rSELF, OUT_ARG1 + REFRESH_INST ${opnum} + movq rINSTq, OUT_ARG2 + call SYMBOL(MterpNewInstance) + testb %al, %al # 0 means an exception is thrown + jz MterpPossibleException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_sget(is_object="0", helper="MterpSGetU32"): +% field(helper=helper) + +%def op_sget_boolean(): +% op_sget(helper="MterpSGetU8") + +%def op_sget_byte(): +% op_sget(helper="MterpSGetI8") + +%def op_sget_char(): +% op_sget(helper="MterpSGetU16") + +%def op_sget_object(): +% op_sget(is_object="1", helper="MterpSGetObj") + +%def op_sget_short(): +% op_sget(helper="MterpSGetI16") + +%def op_sget_wide(): +% op_sget(helper="MterpSGetU64") + +%def op_sput(is_object="0", helper="MterpSPutU32"): +% field(helper=helper) + +%def op_sput_boolean(): +% op_sput(helper="MterpSPutU8") + +%def op_sput_byte(): +% op_sput(helper="MterpSPutI8") + +%def op_sput_char(): +% op_sput(helper="MterpSPutU16") + +%def op_sput_object(): +% op_sput(is_object="1", helper="MterpSPutObj") + +%def op_sput_short(): +% op_sput(helper="MterpSPutI16") + +%def op_sput_wide(): +% op_sput(helper="MterpSPutU64") diff --git a/runtime/interpreter/mterp/x86_64/op_add_double.S b/runtime/interpreter/mterp/x86_64/op_add_double.S deleted file mode 100644 index a00923928b..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_add_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_double(): -% sseBinop(instr="adds", suff="d") diff --git a/runtime/interpreter/mterp/x86_64/op_add_double_2addr.S b/runtime/interpreter/mterp/x86_64/op_add_double_2addr.S deleted file mode 100644 index 8cb45a9a20..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_add_double_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_double_2addr(): -% sseBinop2Addr(instr="adds", suff="d") diff --git a/runtime/interpreter/mterp/x86_64/op_add_float.S b/runtime/interpreter/mterp/x86_64/op_add_float.S deleted file mode 100644 index dee28c7b8b..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_add_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_float(): -% sseBinop(instr="adds", suff="s") diff --git a/runtime/interpreter/mterp/x86_64/op_add_float_2addr.S b/runtime/interpreter/mterp/x86_64/op_add_float_2addr.S deleted file mode 100644 index 4deb4451ce..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_add_float_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_float_2addr(): -% sseBinop2Addr(instr="adds", suff="s") diff --git a/runtime/interpreter/mterp/x86_64/op_add_int.S b/runtime/interpreter/mterp/x86_64/op_add_int.S deleted file mode 100644 index aaf0b35b57..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_add_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_int(): -% binop(instr="addl (rFP,%rcx,4), %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_add_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_add_int_2addr.S deleted file mode 100644 index 8ce26f6e71..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_add_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_int_2addr(): -% binop2addr(instr="addl %eax, (rFP,%rcx,4)") diff --git a/runtime/interpreter/mterp/x86_64/op_add_int_lit16.S b/runtime/interpreter/mterp/x86_64/op_add_int_lit16.S deleted file mode 100644 index a43103019e..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_add_int_lit16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_int_lit16(): -% binopLit16(instr="addl %ecx, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_add_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_add_int_lit8.S deleted file mode 100644 index 3205aee0cb..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_add_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_int_lit8(): -% binopLit8(instr="addl %ecx, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_add_long.S b/runtime/interpreter/mterp/x86_64/op_add_long.S deleted file mode 100644 index fac8163f4b..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_add_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_long(): -% binopWide(instr="addq (rFP,%rcx,4), %rax") diff --git a/runtime/interpreter/mterp/x86_64/op_add_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_add_long_2addr.S deleted file mode 100644 index 17684e6b2b..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_add_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_add_long_2addr(): -% binopWide2addr(instr="addq %rax, (rFP,%rcx,4)") diff --git a/runtime/interpreter/mterp/x86_64/op_aget.S b/runtime/interpreter/mterp/x86_64/op_aget.S deleted file mode 100644 index b45f43a9ab..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_aget.S +++ /dev/null @@ -1,24 +0,0 @@ -%def op_aget(load="movl", shift="4", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET", wide="0"): -/* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short, aget-wide - * - */ - /* op vAA, vBB, vCC */ - movzbq 2(rPC), %rax # eax <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_VREG %eax, %rax # eax <- vBB (array object) - GET_VREG %ecx, %rcx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - .if $wide - movq $data_offset(%rax,%rcx,8), %rax - SET_WIDE_VREG %rax, rINSTq - .else - $load $data_offset(%rax,%rcx,$shift), %eax - SET_VREG %eax, rINSTq - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_aget_boolean.S b/runtime/interpreter/mterp/x86_64/op_aget_boolean.S deleted file mode 100644 index 279e6fc739..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_aget_boolean.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aget_boolean(): -% op_aget(load="movzbl", shift="1", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/x86_64/op_aget_byte.S b/runtime/interpreter/mterp/x86_64/op_aget_byte.S deleted file mode 100644 index 1989450743..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_aget_byte.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aget_byte(): -% op_aget(load="movsbl", shift="1", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/x86_64/op_aget_char.S b/runtime/interpreter/mterp/x86_64/op_aget_char.S deleted file mode 100644 index a35269bd65..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_aget_char.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aget_char(): -% op_aget(load="movzwl", shift="2", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/x86_64/op_aget_object.S b/runtime/interpreter/mterp/x86_64/op_aget_object.S deleted file mode 100644 index fc099dc3a2..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_aget_object.S +++ /dev/null @@ -1,18 +0,0 @@ -%def op_aget_object(): -/* - * Array object get. vAA <- vBB[vCC]. - * - * for: aget-object - */ - /* op vAA, vBB, vCC */ - movzbq 2(rPC), %rax # rax <- BB - movzbq 3(rPC), %rcx # rcx <- CC - GET_VREG OUT_32_ARG0, %rax # eax <- vBB (array object) - GET_VREG OUT_32_ARG1, %rcx # ecx <- vCC (requested index) - EXPORT_PC - call SYMBOL(artAGetObjectFromMterp) # (array, index) - movq rSELF, %rcx - cmpq $$0, THREAD_EXCEPTION_OFFSET(%rcx) - jnz MterpException - SET_VREG_OBJECT %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_aget_short.S b/runtime/interpreter/mterp/x86_64/op_aget_short.S deleted file mode 100644 index ca51ec8052..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_aget_short.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aget_short(): -% op_aget(load="movswl", shift="2", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/x86_64/op_aget_wide.S b/runtime/interpreter/mterp/x86_64/op_aget_wide.S deleted file mode 100644 index 42513fc19a..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_aget_wide.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aget_wide(): -% op_aget(load="movq", shift="8", data_offset="MIRROR_WIDE_ARRAY_DATA_OFFSET", wide="1") diff --git a/runtime/interpreter/mterp/x86_64/op_and_int.S b/runtime/interpreter/mterp/x86_64/op_and_int.S deleted file mode 100644 index afe2d67047..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_and_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_and_int(): -% binop(instr="andl (rFP,%rcx,4), %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_and_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_and_int_2addr.S deleted file mode 100644 index ed9fc654b3..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_and_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_and_int_2addr(): -% binop2addr(instr="andl %eax, (rFP,%rcx,4)") diff --git a/runtime/interpreter/mterp/x86_64/op_and_int_lit16.S b/runtime/interpreter/mterp/x86_64/op_and_int_lit16.S deleted file mode 100644 index d7752b1230..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_and_int_lit16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_and_int_lit16(): -% binopLit16(instr="andl %ecx, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_and_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_and_int_lit8.S deleted file mode 100644 index a353178a88..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_and_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_and_int_lit8(): -% binopLit8(instr="andl %ecx, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_and_long.S b/runtime/interpreter/mterp/x86_64/op_and_long.S deleted file mode 100644 index 7375154bdc..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_and_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_and_long(): -% binopWide(instr="andq (rFP,%rcx,4), %rax") diff --git a/runtime/interpreter/mterp/x86_64/op_and_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_and_long_2addr.S deleted file mode 100644 index 41938ac4dc..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_and_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_and_long_2addr(): -% binopWide2addr(instr="andq %rax, (rFP,%rcx,4)") diff --git a/runtime/interpreter/mterp/x86_64/op_aput.S b/runtime/interpreter/mterp/x86_64/op_aput.S deleted file mode 100644 index bef2e2abe7..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_aput.S +++ /dev/null @@ -1,23 +0,0 @@ -%def op_aput(reg="rINST", store="movl", shift="4", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET", wide="0"): -/* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short, aput-wide - * - */ - /* op vAA, vBB, vCC */ - movzbq 2(rPC), %rax # rax <- BB - movzbq 3(rPC), %rcx # rcx <- CC - GET_VREG %eax, %rax # eax <- vBB (array object) - GET_VREG %ecx, %rcx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - .if $wide - GET_WIDE_VREG rINSTq, rINSTq - .else - GET_VREG rINST, rINSTq - .endif - $store $reg, $data_offset(%rax,%rcx,$shift) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_aput_boolean.S b/runtime/interpreter/mterp/x86_64/op_aput_boolean.S deleted file mode 100644 index 8420b5af8f..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_aput_boolean.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aput_boolean(): -% op_aput(reg="rINSTbl", store="movb", shift="1", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/x86_64/op_aput_byte.S b/runtime/interpreter/mterp/x86_64/op_aput_byte.S deleted file mode 100644 index 6c181a48d9..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_aput_byte.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aput_byte(): -% op_aput(reg="rINSTbl", store="movb", shift="1", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/x86_64/op_aput_char.S b/runtime/interpreter/mterp/x86_64/op_aput_char.S deleted file mode 100644 index 3f4602a7f4..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_aput_char.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aput_char(): -% op_aput(reg="rINSTw", store="movw", shift="2", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/x86_64/op_aput_object.S b/runtime/interpreter/mterp/x86_64/op_aput_object.S deleted file mode 100644 index cf4bdf1a09..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_aput_object.S +++ /dev/null @@ -1,14 +0,0 @@ -%def op_aput_object(): -/* - * Store an object into an array. vBB[vCC] <- vAA. - */ - /* op vAA, vBB, vCC */ - EXPORT_PC - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG0 - movq rPC, OUT_ARG1 - REFRESH_INST ${opnum} - movq rINSTq, OUT_ARG2 - call SYMBOL(MterpAputObject) # (array, index) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_aput_short.S b/runtime/interpreter/mterp/x86_64/op_aput_short.S deleted file mode 100644 index e76d83368b..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_aput_short.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aput_short(): -% op_aput(reg="rINSTw", store="movw", shift="2", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") diff --git a/runtime/interpreter/mterp/x86_64/op_aput_wide.S b/runtime/interpreter/mterp/x86_64/op_aput_wide.S deleted file mode 100644 index c1ca1ef81c..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_aput_wide.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_aput_wide(): -% op_aput(reg="rINSTq", store="movq", shift="8", data_offset="MIRROR_WIDE_ARRAY_DATA_OFFSET", wide="1") diff --git a/runtime/interpreter/mterp/x86_64/op_array_length.S b/runtime/interpreter/mterp/x86_64/op_array_length.S deleted file mode 100644 index 7e6c5c0b52..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_array_length.S +++ /dev/null @@ -1,13 +0,0 @@ -%def op_array_length(): -/* - * Return the length of an array. - */ - movl rINST, %eax # eax <- BA - sarl $$4, rINST # rINST <- B - GET_VREG %ecx, rINSTq # ecx <- vB (object ref) - testl %ecx, %ecx # is null? - je common_errNullObject - andb $$0xf, %al # eax <- A - movl MIRROR_ARRAY_LENGTH_OFFSET(%rcx), rINST - SET_VREG rINST, %rax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86_64/op_check_cast.S b/runtime/interpreter/mterp/x86_64/op_check_cast.S deleted file mode 100644 index ac7051b19b..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_check_cast.S +++ /dev/null @@ -1,14 +0,0 @@ -%def op_check_cast(): -/* - * Check to see if a cast from one class to another is allowed. - */ - /* check-cast vAA, class@BBBB */ - EXPORT_PC - movzwq 2(rPC), OUT_ARG0 # OUT_ARG0 <- BBBB - leaq VREG_ADDRESS(rINSTq), OUT_ARG1 - movq OFF_FP_METHOD(rFP), OUT_ARG2 - movq rSELF, OUT_ARG3 - call SYMBOL(MterpCheckCast) # (index, &obj, method, self) - testb %al, %al - jnz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_cmp_long.S b/runtime/interpreter/mterp/x86_64/op_cmp_long.S deleted file mode 100644 index f222813a02..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_cmp_long.S +++ /dev/null @@ -1,18 +0,0 @@ -%def op_cmp_long(): -/* - * Compare two 64-bit values. Puts 0, 1, or -1 into the destination - * register based on the results of the comparison. - */ - /* cmp-long vAA, vBB, vCC */ - movzbq 2(rPC), %rdx # edx <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_WIDE_VREG %rdx, %rdx # rdx <- v[BB] - xorl %eax, %eax - xorl %edi, %edi - addb $$1, %al - movl $$-1, %esi - cmpq VREG_ADDRESS(%rcx), %rdx - cmovl %esi, %edi - cmovg %eax, %edi - SET_VREG %edi, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_cmpg_double.S b/runtime/interpreter/mterp/x86_64/op_cmpg_double.S deleted file mode 100644 index 1c04e997f1..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_cmpg_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_cmpg_double(): -% fpcmp(suff="d", nanval="pos") diff --git a/runtime/interpreter/mterp/x86_64/op_cmpg_float.S b/runtime/interpreter/mterp/x86_64/op_cmpg_float.S deleted file mode 100644 index 797c3d52d7..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_cmpg_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_cmpg_float(): -% fpcmp(suff="s", nanval="pos") diff --git a/runtime/interpreter/mterp/x86_64/op_cmpl_double.S b/runtime/interpreter/mterp/x86_64/op_cmpl_double.S deleted file mode 100644 index cbe8db713b..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_cmpl_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_cmpl_double(): -% fpcmp(suff="d", nanval="neg") diff --git a/runtime/interpreter/mterp/x86_64/op_cmpl_float.S b/runtime/interpreter/mterp/x86_64/op_cmpl_float.S deleted file mode 100644 index 068f4cb5c1..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_cmpl_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_cmpl_float(): -% fpcmp(suff="s", nanval="neg") diff --git a/runtime/interpreter/mterp/x86_64/op_const.S b/runtime/interpreter/mterp/x86_64/op_const.S deleted file mode 100644 index 36220952bc..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_const.S +++ /dev/null @@ -1,5 +0,0 @@ -%def op_const(): - /* const vAA, #+BBBBbbbb */ - movl 2(rPC), %eax # grab all 32 bits at once - SET_VREG %eax, rINSTq # vAA<- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 diff --git a/runtime/interpreter/mterp/x86_64/op_const_16.S b/runtime/interpreter/mterp/x86_64/op_const_16.S deleted file mode 100644 index fa86060906..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_const_16.S +++ /dev/null @@ -1,5 +0,0 @@ -%def op_const_16(): - /* const/16 vAA, #+BBBB */ - movswl 2(rPC), %ecx # ecx <- ssssBBBB - SET_VREG %ecx, rINSTq # vAA <- ssssBBBB - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_const_4.S b/runtime/interpreter/mterp/x86_64/op_const_4.S deleted file mode 100644 index 9f39ceec49..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_const_4.S +++ /dev/null @@ -1,8 +0,0 @@ -%def op_const_4(): - /* const/4 vA, #+B */ - movsbl rINSTbl, %eax # eax <-ssssssBx - movl $$0xf, rINST - andl %eax, rINST # rINST <- A - sarl $$4, %eax - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86_64/op_const_class.S b/runtime/interpreter/mterp/x86_64/op_const_class.S deleted file mode 100644 index db12ec3141..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_const_class.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_const_class(): -% const(helper="MterpConstClass") diff --git a/runtime/interpreter/mterp/x86_64/op_const_high16.S b/runtime/interpreter/mterp/x86_64/op_const_high16.S deleted file mode 100644 index e1e61e387a..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_const_high16.S +++ /dev/null @@ -1,6 +0,0 @@ -%def op_const_high16(): - /* const/high16 vAA, #+BBBB0000 */ - movzwl 2(rPC), %eax # eax <- 0000BBBB - sall $$16, %eax # eax <- BBBB0000 - SET_VREG %eax, rINSTq # vAA <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_const_method_handle.S b/runtime/interpreter/mterp/x86_64/op_const_method_handle.S deleted file mode 100644 index 2680c17aad..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_const_method_handle.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_const_method_handle(): -% const(helper="MterpConstMethodHandle") diff --git a/runtime/interpreter/mterp/x86_64/op_const_method_type.S b/runtime/interpreter/mterp/x86_64/op_const_method_type.S deleted file mode 100644 index ea814bf648..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_const_method_type.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_const_method_type(): -% const(helper="MterpConstMethodType") diff --git a/runtime/interpreter/mterp/x86_64/op_const_string.S b/runtime/interpreter/mterp/x86_64/op_const_string.S deleted file mode 100644 index 41376f8703..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_const_string.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_const_string(): -% const(helper="MterpConstString") diff --git a/runtime/interpreter/mterp/x86_64/op_const_string_jumbo.S b/runtime/interpreter/mterp/x86_64/op_const_string_jumbo.S deleted file mode 100644 index c12abb114f..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_const_string_jumbo.S +++ /dev/null @@ -1,11 +0,0 @@ -%def op_const_string_jumbo(): - /* const/string vAA, String@BBBBBBBB */ - EXPORT_PC - movl 2(rPC), OUT_32_ARG0 # OUT_32_ARG0 <- BBBB - movq rINSTq, OUT_ARG1 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 - movq rSELF, OUT_ARG3 - call SYMBOL(MterpConstString) # (index, tgt_reg, shadow_frame, self) - testb %al, %al - jnz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 diff --git a/runtime/interpreter/mterp/x86_64/op_const_wide.S b/runtime/interpreter/mterp/x86_64/op_const_wide.S deleted file mode 100644 index f7a74c218a..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_const_wide.S +++ /dev/null @@ -1,5 +0,0 @@ -%def op_const_wide(): - /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ - movq 2(rPC), %rax # rax <- HHHHhhhhBBBBbbbb - SET_WIDE_VREG %rax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 5 diff --git a/runtime/interpreter/mterp/x86_64/op_const_wide_16.S b/runtime/interpreter/mterp/x86_64/op_const_wide_16.S deleted file mode 100644 index 8d1e17c906..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_const_wide_16.S +++ /dev/null @@ -1,5 +0,0 @@ -%def op_const_wide_16(): - /* const-wide/16 vAA, #+BBBB */ - movswq 2(rPC), %rax # rax <- ssssBBBB - SET_WIDE_VREG %rax, rINSTq # store - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_const_wide_32.S b/runtime/interpreter/mterp/x86_64/op_const_wide_32.S deleted file mode 100644 index 22b807477c..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_const_wide_32.S +++ /dev/null @@ -1,5 +0,0 @@ -%def op_const_wide_32(): - /* const-wide/32 vAA, #+BBBBbbbb */ - movslq 2(rPC), %rax # eax <- ssssssssBBBBbbbb - SET_WIDE_VREG %rax, rINSTq # store - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 diff --git a/runtime/interpreter/mterp/x86_64/op_const_wide_high16.S b/runtime/interpreter/mterp/x86_64/op_const_wide_high16.S deleted file mode 100644 index d41b02a6b4..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_const_wide_high16.S +++ /dev/null @@ -1,6 +0,0 @@ -%def op_const_wide_high16(): - /* const-wide/high16 vAA, #+BBBB000000000000 */ - movzwq 2(rPC), %rax # eax <- 0000BBBB - salq $$48, %rax # eax <- BBBB0000 - SET_WIDE_VREG %rax, rINSTq # v[AA+0] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_div_double.S b/runtime/interpreter/mterp/x86_64/op_div_double.S deleted file mode 100644 index 6b342f89bf..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_div_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_double(): -% sseBinop(instr="divs", suff="d") diff --git a/runtime/interpreter/mterp/x86_64/op_div_double_2addr.S b/runtime/interpreter/mterp/x86_64/op_div_double_2addr.S deleted file mode 100644 index 212c82547e..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_div_double_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_double_2addr(): -% sseBinop2Addr(instr="divs", suff="d") diff --git a/runtime/interpreter/mterp/x86_64/op_div_float.S b/runtime/interpreter/mterp/x86_64/op_div_float.S deleted file mode 100644 index b6537d9d89..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_div_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_float(): -% sseBinop(instr="divs", suff="s") diff --git a/runtime/interpreter/mterp/x86_64/op_div_float_2addr.S b/runtime/interpreter/mterp/x86_64/op_div_float_2addr.S deleted file mode 100644 index 19ae27d61a..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_div_float_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_float_2addr(): -% sseBinop2Addr(instr="divs", suff="s") diff --git a/runtime/interpreter/mterp/x86_64/op_div_int.S b/runtime/interpreter/mterp/x86_64/op_div_int.S deleted file mode 100644 index cd7f3db914..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_div_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_int(): -% bindiv(result="%eax", second="%ecx", wide="0", suffix="l") diff --git a/runtime/interpreter/mterp/x86_64/op_div_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_div_int_2addr.S deleted file mode 100644 index 3a734dbf88..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_div_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_int_2addr(): -% bindiv2addr(result="%eax", second="%ecx", wide="0", suffix="l") diff --git a/runtime/interpreter/mterp/x86_64/op_div_int_lit16.S b/runtime/interpreter/mterp/x86_64/op_div_int_lit16.S deleted file mode 100644 index cdcee2d774..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_div_int_lit16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_int_lit16(): -% bindivLit16(result="%eax") diff --git a/runtime/interpreter/mterp/x86_64/op_div_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_div_int_lit8.S deleted file mode 100644 index 7d258c80db..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_div_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_int_lit8(): -% bindivLit8(result="%eax") diff --git a/runtime/interpreter/mterp/x86_64/op_div_long.S b/runtime/interpreter/mterp/x86_64/op_div_long.S deleted file mode 100644 index 59f9073087..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_div_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_long(): -% bindiv(result="%rax", second="%rcx", wide="1", suffix="q", ext="cqo") diff --git a/runtime/interpreter/mterp/x86_64/op_div_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_div_long_2addr.S deleted file mode 100644 index d7a46f540c..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_div_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_div_long_2addr(): -% bindiv2addr(result="%rax", second="%rcx", wide="1", suffix="q", ext="cqo") diff --git a/runtime/interpreter/mterp/x86_64/op_double_to_float.S b/runtime/interpreter/mterp/x86_64/op_double_to_float.S deleted file mode 100644 index e62aa4d2a6..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_double_to_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_double_to_float(): -% fpcvt(source_suffix="d", dest_suffix="s", wide="0") diff --git a/runtime/interpreter/mterp/x86_64/op_double_to_int.S b/runtime/interpreter/mterp/x86_64/op_double_to_int.S deleted file mode 100644 index 24fca631b7..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_double_to_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_double_to_int(): -% cvtfp_int(fp_suffix="d", i_suffix="l", max_const="$0x7fffffff", result_reg="%eax", wide="0") diff --git a/runtime/interpreter/mterp/x86_64/op_double_to_long.S b/runtime/interpreter/mterp/x86_64/op_double_to_long.S deleted file mode 100644 index 8f042c0ca1..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_double_to_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_double_to_long(): -% cvtfp_int(fp_suffix="d", i_suffix="q", max_const="$0x7fffffffffffffff", result_reg="%rax", wide="1") diff --git a/runtime/interpreter/mterp/x86_64/op_fill_array_data.S b/runtime/interpreter/mterp/x86_64/op_fill_array_data.S deleted file mode 100644 index 694ee79bf8..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_fill_array_data.S +++ /dev/null @@ -1,10 +0,0 @@ -%def op_fill_array_data(): - /* fill-array-data vAA, +BBBBBBBB */ - EXPORT_PC - movslq 2(rPC), %rcx # rcx <- ssssssssBBBBbbbb - leaq (rPC,%rcx,2), OUT_ARG1 # OUT_ARG1 <- PC + ssssssssBBBBbbbb*2 - GET_VREG OUT_32_ARG0, rINSTq # OUT_ARG0 <- vAA (array object) - call SYMBOL(MterpFillArrayData) # (obj, payload) - testb %al, %al # 0 means an exception is thrown - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 diff --git a/runtime/interpreter/mterp/x86_64/op_filled_new_array.S b/runtime/interpreter/mterp/x86_64/op_filled_new_array.S deleted file mode 100644 index 0f8b20e6aa..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_filled_new_array.S +++ /dev/null @@ -1,17 +0,0 @@ -%def op_filled_new_array(helper="MterpFilledNewArray"): -/* - * Create a new array with elements filled from registers. - * - * for: filled-new-array, filled-new-array/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ - .extern $helper - EXPORT_PC - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG0 - movq rPC, OUT_ARG1 - movq rSELF, OUT_ARG2 - call SYMBOL($helper) - testb %al, %al # 0 means an exception is thrown - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 diff --git a/runtime/interpreter/mterp/x86_64/op_filled_new_array_range.S b/runtime/interpreter/mterp/x86_64/op_filled_new_array_range.S deleted file mode 100644 index 1667de149a..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_filled_new_array_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_filled_new_array_range(): -% op_filled_new_array(helper="MterpFilledNewArrayRange") diff --git a/runtime/interpreter/mterp/x86_64/op_float_to_double.S b/runtime/interpreter/mterp/x86_64/op_float_to_double.S deleted file mode 100644 index a7cf8d3345..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_float_to_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_float_to_double(): -% fpcvt(source_suffix="s", dest_suffix="d", wide="1") diff --git a/runtime/interpreter/mterp/x86_64/op_float_to_int.S b/runtime/interpreter/mterp/x86_64/op_float_to_int.S deleted file mode 100644 index 11955868a8..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_float_to_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_float_to_int(): -% cvtfp_int(fp_suffix="s", i_suffix="l", max_const="$0x7fffffff", result_reg="%eax", wide="0") diff --git a/runtime/interpreter/mterp/x86_64/op_float_to_long.S b/runtime/interpreter/mterp/x86_64/op_float_to_long.S deleted file mode 100644 index 4548d6a47f..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_float_to_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_float_to_long(): -% cvtfp_int(fp_suffix="s", i_suffix="q", max_const="$0x7fffffffffffffff", result_reg="%rax", wide="1") diff --git a/runtime/interpreter/mterp/x86_64/op_goto.S b/runtime/interpreter/mterp/x86_64/op_goto.S deleted file mode 100644 index 0659bbc0e6..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_goto.S +++ /dev/null @@ -1,11 +0,0 @@ -%def op_goto(): -/* - * Unconditional branch, 8-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto +AA */ - movsbq rINSTbl, rINSTq # rINSTq <- ssssssAA - testq rINSTq, rINSTq - jmp MterpCommonTakenBranch diff --git a/runtime/interpreter/mterp/x86_64/op_goto_16.S b/runtime/interpreter/mterp/x86_64/op_goto_16.S deleted file mode 100644 index 1193f70aec..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_goto_16.S +++ /dev/null @@ -1,11 +0,0 @@ -%def op_goto_16(): -/* - * Unconditional branch, 16-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto/16 +AAAA */ - movswq 2(rPC), rINSTq # rINSTq <- ssssAAAA - testq rINSTq, rINSTq - jmp MterpCommonTakenBranch diff --git a/runtime/interpreter/mterp/x86_64/op_goto_32.S b/runtime/interpreter/mterp/x86_64/op_goto_32.S deleted file mode 100644 index cd0b522274..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_goto_32.S +++ /dev/null @@ -1,14 +0,0 @@ -%def op_goto_32(): -/* - * Unconditional branch, 32-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - * - * Because we need the SF bit set, we'll use an adds - * to convert from Dalvik offset to byte offset. - */ - /* goto/32 +AAAAAAAA */ - movslq 2(rPC), rINSTq # rINSTq <- AAAAAAAA - testq rINSTq, rINSTq - jmp MterpCommonTakenBranch diff --git a/runtime/interpreter/mterp/x86_64/op_if_eq.S b/runtime/interpreter/mterp/x86_64/op_if_eq.S deleted file mode 100644 index 4d1f6a54d2..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_if_eq.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_eq(): -% bincmp(revcmp="ne") diff --git a/runtime/interpreter/mterp/x86_64/op_if_eqz.S b/runtime/interpreter/mterp/x86_64/op_if_eqz.S deleted file mode 100644 index 12de558550..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_if_eqz.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_eqz(): -% zcmp(revcmp="ne") diff --git a/runtime/interpreter/mterp/x86_64/op_if_ge.S b/runtime/interpreter/mterp/x86_64/op_if_ge.S deleted file mode 100644 index 684902776f..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_if_ge.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_ge(): -% bincmp(revcmp="l") diff --git a/runtime/interpreter/mterp/x86_64/op_if_gez.S b/runtime/interpreter/mterp/x86_64/op_if_gez.S deleted file mode 100644 index 87bdcbfa32..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_if_gez.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_gez(): -% zcmp(revcmp="l") diff --git a/runtime/interpreter/mterp/x86_64/op_if_gt.S b/runtime/interpreter/mterp/x86_64/op_if_gt.S deleted file mode 100644 index 4a521006b3..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_if_gt.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_gt(): -% bincmp(revcmp="le") diff --git a/runtime/interpreter/mterp/x86_64/op_if_gtz.S b/runtime/interpreter/mterp/x86_64/op_if_gtz.S deleted file mode 100644 index a0b2e3a35b..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_if_gtz.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_gtz(): -% zcmp(revcmp="le") diff --git a/runtime/interpreter/mterp/x86_64/op_if_le.S b/runtime/interpreter/mterp/x86_64/op_if_le.S deleted file mode 100644 index 69e94db79f..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_if_le.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_le(): -% bincmp(revcmp="g") diff --git a/runtime/interpreter/mterp/x86_64/op_if_lez.S b/runtime/interpreter/mterp/x86_64/op_if_lez.S deleted file mode 100644 index 42e69d969a..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_if_lez.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_lez(): -% zcmp(revcmp="g") diff --git a/runtime/interpreter/mterp/x86_64/op_if_lt.S b/runtime/interpreter/mterp/x86_64/op_if_lt.S deleted file mode 100644 index 052aabe1e7..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_if_lt.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_lt(): -% bincmp(revcmp="ge") diff --git a/runtime/interpreter/mterp/x86_64/op_if_ltz.S b/runtime/interpreter/mterp/x86_64/op_if_ltz.S deleted file mode 100644 index 8e13e48c2a..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_if_ltz.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_ltz(): -% zcmp(revcmp="ge") diff --git a/runtime/interpreter/mterp/x86_64/op_if_ne.S b/runtime/interpreter/mterp/x86_64/op_if_ne.S deleted file mode 100644 index 2cfd8a9a1e..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_if_ne.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_ne(): -% bincmp(revcmp="e") diff --git a/runtime/interpreter/mterp/x86_64/op_if_nez.S b/runtime/interpreter/mterp/x86_64/op_if_nez.S deleted file mode 100644 index 261a173a38..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_if_nez.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_if_nez(): -% zcmp(revcmp="e") diff --git a/runtime/interpreter/mterp/x86_64/op_iget.S b/runtime/interpreter/mterp/x86_64/op_iget.S deleted file mode 100644 index d09edc0a17..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_iget.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget(is_object="0", helper="MterpIGetU32"): -% field(helper=helper) diff --git a/runtime/interpreter/mterp/x86_64/op_iget_boolean.S b/runtime/interpreter/mterp/x86_64/op_iget_boolean.S deleted file mode 100644 index cb8edeec77..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_iget_boolean.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_boolean(): -% op_iget(helper="MterpIGetU8") diff --git a/runtime/interpreter/mterp/x86_64/op_iget_boolean_quick.S b/runtime/interpreter/mterp/x86_64/op_iget_boolean_quick.S deleted file mode 100644 index 4e1676844b..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_iget_boolean_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_boolean_quick(): -% op_iget_quick(load="movsbl") diff --git a/runtime/interpreter/mterp/x86_64/op_iget_byte.S b/runtime/interpreter/mterp/x86_64/op_iget_byte.S deleted file mode 100644 index 2b87fb16b5..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_iget_byte.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_byte(): -% op_iget(helper="MterpIGetI8") diff --git a/runtime/interpreter/mterp/x86_64/op_iget_byte_quick.S b/runtime/interpreter/mterp/x86_64/op_iget_byte_quick.S deleted file mode 100644 index b92936c28d..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_iget_byte_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_byte_quick(): -% op_iget_quick(load="movsbl") diff --git a/runtime/interpreter/mterp/x86_64/op_iget_char.S b/runtime/interpreter/mterp/x86_64/op_iget_char.S deleted file mode 100644 index 001bd03e2b..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_iget_char.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_char(): -% op_iget(helper="MterpIGetU16") diff --git a/runtime/interpreter/mterp/x86_64/op_iget_char_quick.S b/runtime/interpreter/mterp/x86_64/op_iget_char_quick.S deleted file mode 100644 index d6f836b28e..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_iget_char_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_char_quick(): -% op_iget_quick(load="movzwl") diff --git a/runtime/interpreter/mterp/x86_64/op_iget_object.S b/runtime/interpreter/mterp/x86_64/op_iget_object.S deleted file mode 100644 index 4e5f769547..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_iget_object.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_object(): -% op_iget(is_object="1", helper="MterpIGetObj") diff --git a/runtime/interpreter/mterp/x86_64/op_iget_object_quick.S b/runtime/interpreter/mterp/x86_64/op_iget_object_quick.S deleted file mode 100644 index 1969a25a0d..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_iget_object_quick.S +++ /dev/null @@ -1,16 +0,0 @@ -%def op_iget_object_quick(): - /* For: iget-object-quick */ - /* op vA, vB, offset@CCCC */ - .extern artIGetObjectFromMterp - movzbq rINSTbl, %rcx # rcx <- BA - sarl $$4, %ecx # ecx <- B - GET_VREG OUT_32_ARG0, %rcx # vB (object we're operating on) - movzwl 2(rPC), OUT_32_ARG1 # eax <- field byte offset - EXPORT_PC - callq SYMBOL(artIGetObjectFromMterp) # (obj, offset) - movq rSELF, %rcx - cmpq $$0, THREAD_EXCEPTION_OFFSET(%rcx) - jnz MterpException # bail out - andb $$0xf, rINSTbl # rINST <- A - SET_VREG_OBJECT %eax, rINSTq # fp[A] <- value - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_iget_quick.S b/runtime/interpreter/mterp/x86_64/op_iget_quick.S deleted file mode 100644 index ba9e8e40e7..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_iget_quick.S +++ /dev/null @@ -1,18 +0,0 @@ -%def op_iget_quick(load="movl", wide="0"): - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick, iget-wide-quick */ - /* op vA, vB, offset@CCCC */ - movl rINST, %ecx # rcx <- BA - sarl $$4, %ecx # ecx <- B - GET_VREG %ecx, %rcx # vB (object we're operating on) - movzwq 2(rPC), %rax # eax <- field byte offset - testl %ecx, %ecx # is object null? - je common_errNullObject - andb $$0xf,rINSTbl # rINST <- A - .if $wide - movq (%rcx,%rax,1), %rax - SET_WIDE_VREG %rax, rINSTq # fp[A] <- value - .else - ${load} (%rcx,%rax,1), %eax - SET_VREG %eax, rINSTq # fp[A] <- value - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_iget_short.S b/runtime/interpreter/mterp/x86_64/op_iget_short.S deleted file mode 100644 index a62c4d998f..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_iget_short.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_short(): -% op_iget(helper="MterpIGetI16") diff --git a/runtime/interpreter/mterp/x86_64/op_iget_short_quick.S b/runtime/interpreter/mterp/x86_64/op_iget_short_quick.S deleted file mode 100644 index f5e48d621a..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_iget_short_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_short_quick(): -% op_iget_quick(load="movswl") diff --git a/runtime/interpreter/mterp/x86_64/op_iget_wide.S b/runtime/interpreter/mterp/x86_64/op_iget_wide.S deleted file mode 100644 index 9643cc3403..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_iget_wide.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_wide(): -% op_iget(helper="MterpIGetU64") diff --git a/runtime/interpreter/mterp/x86_64/op_iget_wide_quick.S b/runtime/interpreter/mterp/x86_64/op_iget_wide_quick.S deleted file mode 100644 index 263ea8cff8..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_iget_wide_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iget_wide_quick(): -% op_iget_quick(load="movswl", wide="1") diff --git a/runtime/interpreter/mterp/x86_64/op_instance_of.S b/runtime/interpreter/mterp/x86_64/op_instance_of.S deleted file mode 100644 index 237dd39868..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_instance_of.S +++ /dev/null @@ -1,23 +0,0 @@ -%def op_instance_of(): -/* - * Check to see if an object reference is an instance of a class. - * - * Most common situation is a non-null object, being compared against - * an already-resolved class. - */ - /* instance-of vA, vB, class@CCCC */ - EXPORT_PC - movzwl 2(rPC), OUT_32_ARG0 # OUT_32_ARG0 <- CCCC - movl rINST, %eax # eax <- BA - sarl $$4, %eax # eax <- B - leaq VREG_ADDRESS(%rax), OUT_ARG1 # Get object address - movq OFF_FP_METHOD(rFP), OUT_ARG2 - movq rSELF, OUT_ARG3 - call SYMBOL(MterpInstanceOf) # (index, &obj, method, self) - movsbl %al, %eax - movq rSELF, %rcx - cmpq $$0, THREAD_EXCEPTION_OFFSET(%rcx) - jnz MterpException - andb $$0xf, rINSTbl # rINSTbl <- A - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_int_to_byte.S b/runtime/interpreter/mterp/x86_64/op_int_to_byte.S deleted file mode 100644 index 80e4d5c310..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_int_to_byte.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_int_to_byte(): -% unop(instr="movsbl %al, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_int_to_char.S b/runtime/interpreter/mterp/x86_64/op_int_to_char.S deleted file mode 100644 index 83e9868ef3..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_int_to_char.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_int_to_char(): -% unop(instr="movzwl %ax,%eax") diff --git a/runtime/interpreter/mterp/x86_64/op_int_to_double.S b/runtime/interpreter/mterp/x86_64/op_int_to_double.S deleted file mode 100644 index 74e91ecebf..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_int_to_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_int_to_double(): -% fpcvt(source_suffix="i", dest_suffix="dl", wide="1") diff --git a/runtime/interpreter/mterp/x86_64/op_int_to_float.S b/runtime/interpreter/mterp/x86_64/op_int_to_float.S deleted file mode 100644 index b57fc84d0d..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_int_to_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_int_to_float(): -% fpcvt(source_suffix="i", dest_suffix="sl", wide="0") diff --git a/runtime/interpreter/mterp/x86_64/op_int_to_long.S b/runtime/interpreter/mterp/x86_64/op_int_to_long.S deleted file mode 100644 index 473d6a2ab7..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_int_to_long.S +++ /dev/null @@ -1,9 +0,0 @@ -%def op_int_to_long(): - /* int to long vA, vB */ - movzbq rINSTbl, %rax # rax <- +A - sarl $$4, %eax # eax <- B - andb $$0xf, rINSTbl # rINST <- A - movslq VREG_ADDRESS(%rax), %rax - SET_WIDE_VREG %rax, rINSTq # v[A] <- %rax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - diff --git a/runtime/interpreter/mterp/x86_64/op_int_to_short.S b/runtime/interpreter/mterp/x86_64/op_int_to_short.S deleted file mode 100644 index e4db90b801..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_int_to_short.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_int_to_short(): -% unop(instr="movswl %ax, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_custom.S b/runtime/interpreter/mterp/x86_64/op_invoke_custom.S deleted file mode 100644 index 4bba9ee524..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_invoke_custom.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_custom(): -% invoke(helper="MterpInvokeCustom") diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_custom_range.S b/runtime/interpreter/mterp/x86_64/op_invoke_custom_range.S deleted file mode 100644 index 57e61af1fa..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_invoke_custom_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_custom_range(): -% invoke(helper="MterpInvokeCustomRange") diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_direct.S b/runtime/interpreter/mterp/x86_64/op_invoke_direct.S deleted file mode 100644 index d3139cf39b..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_invoke_direct.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_direct(): -% invoke(helper="MterpInvokeDirect") diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_direct_range.S b/runtime/interpreter/mterp/x86_64/op_invoke_direct_range.S deleted file mode 100644 index b4a161f48b..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_invoke_direct_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_direct_range(): -% invoke(helper="MterpInvokeDirectRange") diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_interface.S b/runtime/interpreter/mterp/x86_64/op_invoke_interface.S deleted file mode 100644 index 559b9768d9..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_invoke_interface.S +++ /dev/null @@ -1,9 +0,0 @@ -%def op_invoke_interface(): -% invoke(helper="MterpInvokeInterface") -/* - * Handle an interface method call. - * - * for: invoke-interface, invoke-interface/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_interface_range.S b/runtime/interpreter/mterp/x86_64/op_invoke_interface_range.S deleted file mode 100644 index 2989115377..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_invoke_interface_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_interface_range(): -% invoke(helper="MterpInvokeInterfaceRange") diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_polymorphic.S b/runtime/interpreter/mterp/x86_64/op_invoke_polymorphic.S deleted file mode 100644 index ce61f5aa0e..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_invoke_polymorphic.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_polymorphic(): -% invoke_polymorphic(helper="MterpInvokePolymorphic") diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_polymorphic_range.S b/runtime/interpreter/mterp/x86_64/op_invoke_polymorphic_range.S deleted file mode 100644 index 16731bdb40..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_invoke_polymorphic_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_polymorphic_range(): -% invoke_polymorphic(helper="MterpInvokePolymorphicRange") diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_static.S b/runtime/interpreter/mterp/x86_64/op_invoke_static.S deleted file mode 100644 index 3e38d36a27..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_invoke_static.S +++ /dev/null @@ -1,3 +0,0 @@ -%def op_invoke_static(): -% invoke(helper="MterpInvokeStatic") - diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_static_range.S b/runtime/interpreter/mterp/x86_64/op_invoke_static_range.S deleted file mode 100644 index e0a546c92b..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_invoke_static_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_static_range(): -% invoke(helper="MterpInvokeStaticRange") diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_super.S b/runtime/interpreter/mterp/x86_64/op_invoke_super.S deleted file mode 100644 index 5b2055010e..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_invoke_super.S +++ /dev/null @@ -1,9 +0,0 @@ -%def op_invoke_super(): -% invoke(helper="MterpInvokeSuper") -/* - * Handle a "super" method call. - * - * for: invoke-super, invoke-super/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_super_range.S b/runtime/interpreter/mterp/x86_64/op_invoke_super_range.S deleted file mode 100644 index caeafaa13c..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_invoke_super_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_super_range(): -% invoke(helper="MterpInvokeSuperRange") diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_virtual.S b/runtime/interpreter/mterp/x86_64/op_invoke_virtual.S deleted file mode 100644 index e27eeedacc..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_invoke_virtual.S +++ /dev/null @@ -1,9 +0,0 @@ -%def op_invoke_virtual(): -% invoke(helper="MterpInvokeVirtual") -/* - * Handle a virtual method call. - * - * for: invoke-virtual, invoke-virtual/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_virtual_quick.S b/runtime/interpreter/mterp/x86_64/op_invoke_virtual_quick.S deleted file mode 100644 index ea72c171ec..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_invoke_virtual_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_virtual_quick(): -% invoke(helper="MterpInvokeVirtualQuick") diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_virtual_range.S b/runtime/interpreter/mterp/x86_64/op_invoke_virtual_range.S deleted file mode 100644 index baa0779593..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_invoke_virtual_range.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_virtual_range(): -% invoke(helper="MterpInvokeVirtualRange") diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_virtual_range_quick.S b/runtime/interpreter/mterp/x86_64/op_invoke_virtual_range_quick.S deleted file mode 100644 index 1d961a0781..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_invoke_virtual_range_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_invoke_virtual_range_quick(): -% invoke(helper="MterpInvokeVirtualQuickRange") diff --git a/runtime/interpreter/mterp/x86_64/op_iput.S b/runtime/interpreter/mterp/x86_64/op_iput.S deleted file mode 100644 index e5351baf55..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_iput.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput(is_object="0", helper="MterpIPutU32"): -% field(helper=helper) diff --git a/runtime/interpreter/mterp/x86_64/op_iput_boolean.S b/runtime/interpreter/mterp/x86_64/op_iput_boolean.S deleted file mode 100644 index 9eb849877b..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_iput_boolean.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_boolean(): -% op_iput(helper="MterpIPutU8") diff --git a/runtime/interpreter/mterp/x86_64/op_iput_boolean_quick.S b/runtime/interpreter/mterp/x86_64/op_iput_boolean_quick.S deleted file mode 100644 index c304c76b51..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_iput_boolean_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_boolean_quick(): -% op_iput_quick(reg="rINSTbl", store="movb") diff --git a/runtime/interpreter/mterp/x86_64/op_iput_byte.S b/runtime/interpreter/mterp/x86_64/op_iput_byte.S deleted file mode 100644 index 4b74f9fb0e..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_iput_byte.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_byte(): -% op_iput(helper="MterpIPutI8") diff --git a/runtime/interpreter/mterp/x86_64/op_iput_byte_quick.S b/runtime/interpreter/mterp/x86_64/op_iput_byte_quick.S deleted file mode 100644 index dac18e63cc..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_iput_byte_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_byte_quick(): -% op_iput_quick(reg="rINSTbl", store="movb") diff --git a/runtime/interpreter/mterp/x86_64/op_iput_char.S b/runtime/interpreter/mterp/x86_64/op_iput_char.S deleted file mode 100644 index 64a249fc12..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_iput_char.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_char(): -% op_iput(helper="MterpIPutU16") diff --git a/runtime/interpreter/mterp/x86_64/op_iput_char_quick.S b/runtime/interpreter/mterp/x86_64/op_iput_char_quick.S deleted file mode 100644 index 21a25812b1..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_iput_char_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_char_quick(): -% op_iput_quick(reg="rINSTw", store="movw") diff --git a/runtime/interpreter/mterp/x86_64/op_iput_object.S b/runtime/interpreter/mterp/x86_64/op_iput_object.S deleted file mode 100644 index 131edd5dbd..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_iput_object.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_object(): -% op_iput(is_object="1", helper="MterpIPutObj") diff --git a/runtime/interpreter/mterp/x86_64/op_iput_object_quick.S b/runtime/interpreter/mterp/x86_64/op_iput_object_quick.S deleted file mode 100644 index e41540d5b7..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_iput_object_quick.S +++ /dev/null @@ -1,10 +0,0 @@ -%def op_iput_object_quick(): - EXPORT_PC - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG0 - movq rPC, OUT_ARG1 - REFRESH_INST ${opnum} - movl rINST, OUT_32_ARG2 - call SYMBOL(MterpIputObjectQuick) - testb %al, %al - jz MterpException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_iput_quick.S b/runtime/interpreter/mterp/x86_64/op_iput_quick.S deleted file mode 100644 index 3cbb7e99c3..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_iput_quick.S +++ /dev/null @@ -1,13 +0,0 @@ -%def op_iput_quick(reg="rINST", store="movl"): - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - movzbq rINSTbl, %rcx # rcx <- BA - sarl $$4, %ecx # ecx <- B - GET_VREG %ecx, %rcx # vB (object we're operating on) - testl %ecx, %ecx # is object null? - je common_errNullObject - andb $$0xf, rINSTbl # rINST <- A - GET_VREG rINST, rINSTq # rINST <- v[A] - movzwq 2(rPC), %rax # rax <- field byte offset - ${store} ${reg}, (%rcx,%rax,1) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_iput_short.S b/runtime/interpreter/mterp/x86_64/op_iput_short.S deleted file mode 100644 index e631a3b259..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_iput_short.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_short(): -% op_iput(helper="MterpIPutI16") diff --git a/runtime/interpreter/mterp/x86_64/op_iput_short_quick.S b/runtime/interpreter/mterp/x86_64/op_iput_short_quick.S deleted file mode 100644 index 5eb28d6922..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_iput_short_quick.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_short_quick(): -% op_iput_quick(reg="rINSTw", store="movw") diff --git a/runtime/interpreter/mterp/x86_64/op_iput_wide.S b/runtime/interpreter/mterp/x86_64/op_iput_wide.S deleted file mode 100644 index 2f34fd39f9..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_iput_wide.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_iput_wide(): -% op_iput(helper="MterpIPutU64") diff --git a/runtime/interpreter/mterp/x86_64/op_iput_wide_quick.S b/runtime/interpreter/mterp/x86_64/op_iput_wide_quick.S deleted file mode 100644 index a13a6340ef..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_iput_wide_quick.S +++ /dev/null @@ -1,13 +0,0 @@ -%def op_iput_wide_quick(): - /* iput-wide-quick vA, vB, offset@CCCC */ - movzbq rINSTbl, %rcx # rcx<- BA - sarl $$4, %ecx # ecx<- B - GET_VREG %ecx, %rcx # vB (object we're operating on) - testl %ecx, %ecx # is object null? - je common_errNullObject - movzwq 2(rPC), %rax # rax<- field byte offset - leaq (%rcx,%rax,1), %rcx # ecx<- Address of 64-bit target - andb $$0xf, rINSTbl # rINST<- A - GET_WIDE_VREG %rax, rINSTq # rax<- fp[A]/fp[A+1] - movq %rax, (%rcx) # obj.field<- r0/r1 - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_long_to_double.S b/runtime/interpreter/mterp/x86_64/op_long_to_double.S deleted file mode 100644 index 6b2d7bf574..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_long_to_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_long_to_double(): -% fpcvt(source_suffix="i", dest_suffix="dq", wide="1") diff --git a/runtime/interpreter/mterp/x86_64/op_long_to_float.S b/runtime/interpreter/mterp/x86_64/op_long_to_float.S deleted file mode 100644 index 7c2edfd613..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_long_to_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_long_to_float(): -% fpcvt(source_suffix="i", dest_suffix="sq", wide="0") diff --git a/runtime/interpreter/mterp/x86_64/op_long_to_int.S b/runtime/interpreter/mterp/x86_64/op_long_to_int.S deleted file mode 100644 index eacb8f59ec..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_long_to_int.S +++ /dev/null @@ -1,3 +0,0 @@ -%def op_long_to_int(): -/* we ignore the high word, making this equivalent to a 32-bit reg move */ -% op_move() diff --git a/runtime/interpreter/mterp/x86_64/op_monitor_enter.S b/runtime/interpreter/mterp/x86_64/op_monitor_enter.S deleted file mode 100644 index 7865156c25..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_monitor_enter.S +++ /dev/null @@ -1,12 +0,0 @@ -%def op_monitor_enter(): -/* - * Synchronize on an object. - */ - /* monitor-enter vAA */ - EXPORT_PC - GET_VREG OUT_32_ARG0, rINSTq - movq rSELF, OUT_ARG1 - call SYMBOL(artLockObjectFromCode) # (object, self) - testq %rax, %rax - jnz MterpException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86_64/op_monitor_exit.S b/runtime/interpreter/mterp/x86_64/op_monitor_exit.S deleted file mode 100644 index 6422bc8759..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_monitor_exit.S +++ /dev/null @@ -1,16 +0,0 @@ -%def op_monitor_exit(): -/* - * Unlock an object. - * - * Exceptions that occur when unlocking a monitor need to appear as - * if they happened at the following instruction. See the Dalvik - * instruction spec. - */ - /* monitor-exit vAA */ - EXPORT_PC - GET_VREG OUT_32_ARG0, rINSTq - movq rSELF, OUT_ARG1 - call SYMBOL(artUnlockObjectFromCode) # (object, self) - testq %rax, %rax - jnz MterpException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86_64/op_move.S b/runtime/interpreter/mterp/x86_64/op_move.S deleted file mode 100644 index 0ccf228ee8..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_move.S +++ /dev/null @@ -1,13 +0,0 @@ -%def op_move(is_object="0"): - /* for move, move-object, long-to-int */ - /* op vA, vB */ - movl rINST, %eax # eax <- BA - andb $$0xf, %al # eax <- A - shrl $$4, rINST # rINST <- B - GET_VREG %edx, rINSTq - .if $is_object - SET_VREG_OBJECT %edx, %rax # fp[A] <- fp[B] - .else - SET_VREG %edx, %rax # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86_64/op_move_16.S b/runtime/interpreter/mterp/x86_64/op_move_16.S deleted file mode 100644 index 238f089bef..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_move_16.S +++ /dev/null @@ -1,12 +0,0 @@ -%def op_move_16(is_object="0"): - /* for: move/16, move-object/16 */ - /* op vAAAA, vBBBB */ - movzwq 4(rPC), %rcx # ecx <- BBBB - movzwq 2(rPC), %rax # eax <- AAAA - GET_VREG %edx, %rcx - .if $is_object - SET_VREG_OBJECT %edx, %rax # fp[A] <- fp[B] - .else - SET_VREG %edx, %rax # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 diff --git a/runtime/interpreter/mterp/x86_64/op_move_exception.S b/runtime/interpreter/mterp/x86_64/op_move_exception.S deleted file mode 100644 index 9d87f7c8f7..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_move_exception.S +++ /dev/null @@ -1,7 +0,0 @@ -%def op_move_exception(): - /* move-exception vAA */ - movq rSELF, %rcx - movl THREAD_EXCEPTION_OFFSET(%rcx), %eax - SET_VREG_OBJECT %eax, rINSTq # fp[AA] <- exception object - movl $$0, THREAD_EXCEPTION_OFFSET(%rcx) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86_64/op_move_from16.S b/runtime/interpreter/mterp/x86_64/op_move_from16.S deleted file mode 100644 index 6163e6d37d..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_move_from16.S +++ /dev/null @@ -1,11 +0,0 @@ -%def op_move_from16(is_object="0"): - /* for: move/from16, move-object/from16 */ - /* op vAA, vBBBB */ - movzwq 2(rPC), %rax # eax <- BBBB - GET_VREG %edx, %rax # edx <- fp[BBBB] - .if $is_object - SET_VREG_OBJECT %edx, rINSTq # fp[A] <- fp[B] - .else - SET_VREG %edx, rINSTq # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_move_object.S b/runtime/interpreter/mterp/x86_64/op_move_object.S deleted file mode 100644 index dbb4d59710..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_move_object.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_move_object(): -% op_move(is_object="1") diff --git a/runtime/interpreter/mterp/x86_64/op_move_object_16.S b/runtime/interpreter/mterp/x86_64/op_move_object_16.S deleted file mode 100644 index 40120379d5..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_move_object_16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_move_object_16(): -% op_move_16(is_object="1") diff --git a/runtime/interpreter/mterp/x86_64/op_move_object_from16.S b/runtime/interpreter/mterp/x86_64/op_move_object_from16.S deleted file mode 100644 index c82698e81e..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_move_object_from16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_move_object_from16(): -% op_move_from16(is_object="1") diff --git a/runtime/interpreter/mterp/x86_64/op_move_result.S b/runtime/interpreter/mterp/x86_64/op_move_result.S deleted file mode 100644 index a089623bca..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_move_result.S +++ /dev/null @@ -1,11 +0,0 @@ -%def op_move_result(is_object="0"): - /* for: move-result, move-result-object */ - /* op vAA */ - movq OFF_FP_RESULT_REGISTER(rFP), %rax # get pointer to result JType. - movl (%rax), %eax # r0 <- result.i. - .if $is_object - SET_VREG_OBJECT %eax, rINSTq # fp[A] <- fp[B] - .else - SET_VREG %eax, rINSTq # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86_64/op_move_result_object.S b/runtime/interpreter/mterp/x86_64/op_move_result_object.S deleted file mode 100644 index 87aea2646a..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_move_result_object.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_move_result_object(): -% op_move_result(is_object="1") diff --git a/runtime/interpreter/mterp/x86_64/op_move_result_wide.S b/runtime/interpreter/mterp/x86_64/op_move_result_wide.S deleted file mode 100644 index 80f49aaa15..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_move_result_wide.S +++ /dev/null @@ -1,6 +0,0 @@ -%def op_move_result_wide(): - /* move-result-wide vAA */ - movq OFF_FP_RESULT_REGISTER(rFP), %rax # get pointer to result JType. - movq (%rax), %rdx # Get wide - SET_WIDE_VREG %rdx, rINSTq # v[AA] <- rdx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86_64/op_move_wide.S b/runtime/interpreter/mterp/x86_64/op_move_wide.S deleted file mode 100644 index afb67efd10..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_move_wide.S +++ /dev/null @@ -1,9 +0,0 @@ -%def op_move_wide(): - /* move-wide vA, vB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - movl rINST, %ecx # ecx <- BA - sarl $$4, rINST # rINST <- B - andb $$0xf, %cl # ecx <- A - GET_WIDE_VREG %rdx, rINSTq # rdx <- v[B] - SET_WIDE_VREG %rdx, %rcx # v[A] <- rdx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86_64/op_move_wide_16.S b/runtime/interpreter/mterp/x86_64/op_move_wide_16.S deleted file mode 100644 index b4de5206fd..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_move_wide_16.S +++ /dev/null @@ -1,8 +0,0 @@ -%def op_move_wide_16(): - /* move-wide/16 vAAAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - movzwq 4(rPC), %rcx # ecx<- BBBB - movzwq 2(rPC), %rax # eax<- AAAA - GET_WIDE_VREG %rdx, %rcx # rdx <- v[B] - SET_WIDE_VREG %rdx, %rax # v[A] <- rdx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 diff --git a/runtime/interpreter/mterp/x86_64/op_move_wide_from16.S b/runtime/interpreter/mterp/x86_64/op_move_wide_from16.S deleted file mode 100644 index c4389a4873..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_move_wide_from16.S +++ /dev/null @@ -1,7 +0,0 @@ -%def op_move_wide_from16(): - /* move-wide/from16 vAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - movzwl 2(rPC), %ecx # ecx <- BBBB - GET_WIDE_VREG %rdx, %rcx # rdx <- v[B] - SET_WIDE_VREG %rdx, rINSTq # v[A] <- rdx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_mul_double.S b/runtime/interpreter/mterp/x86_64/op_mul_double.S deleted file mode 100644 index 5353028798..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_mul_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_mul_double(): -% sseBinop(instr="muls", suff="d") diff --git a/runtime/interpreter/mterp/x86_64/op_mul_double_2addr.S b/runtime/interpreter/mterp/x86_64/op_mul_double_2addr.S deleted file mode 100644 index 7a6dcd0cb8..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_mul_double_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_mul_double_2addr(): -% sseBinop2Addr(instr="muls", suff="d") diff --git a/runtime/interpreter/mterp/x86_64/op_mul_float.S b/runtime/interpreter/mterp/x86_64/op_mul_float.S deleted file mode 100644 index b9eeeeeb69..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_mul_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_mul_float(): -% sseBinop(instr="muls", suff="s") diff --git a/runtime/interpreter/mterp/x86_64/op_mul_float_2addr.S b/runtime/interpreter/mterp/x86_64/op_mul_float_2addr.S deleted file mode 100644 index 949af7b254..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_mul_float_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_mul_float_2addr(): -% sseBinop2Addr(instr="muls", suff="s") diff --git a/runtime/interpreter/mterp/x86_64/op_mul_int.S b/runtime/interpreter/mterp/x86_64/op_mul_int.S deleted file mode 100644 index 51abae6294..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_mul_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_mul_int(): -% binop(instr="imull (rFP,%rcx,4), %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_mul_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_mul_int_2addr.S deleted file mode 100644 index fb2ec89245..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_mul_int_2addr.S +++ /dev/null @@ -1,9 +0,0 @@ -%def op_mul_int_2addr(): - /* mul vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $$4, rINST # rINST <- B - andb $$0xf, %cl # ecx <- A - GET_VREG %eax, %rcx # eax <- vA - imull (rFP,rINSTq,4), %eax - SET_VREG %eax, %rcx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86_64/op_mul_int_lit16.S b/runtime/interpreter/mterp/x86_64/op_mul_int_lit16.S deleted file mode 100644 index a0b1e714c6..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_mul_int_lit16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_mul_int_lit16(): -% binopLit16(instr="imull %ecx, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_mul_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_mul_int_lit8.S deleted file mode 100644 index e68e7f7e2f..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_mul_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_mul_int_lit8(): -% binopLit8(instr="imull %ecx, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_mul_long.S b/runtime/interpreter/mterp/x86_64/op_mul_long.S deleted file mode 100644 index e5bffa4035..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_mul_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_mul_long(): -% binopWide(instr="imulq (rFP,%rcx,4), %rax") diff --git a/runtime/interpreter/mterp/x86_64/op_mul_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_mul_long_2addr.S deleted file mode 100644 index 25ffc148a5..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_mul_long_2addr.S +++ /dev/null @@ -1,9 +0,0 @@ -%def op_mul_long_2addr(): - /* mul vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $$4, rINST # rINST <- B - andb $$0xf, %cl # ecx <- A - GET_WIDE_VREG %rax, %rcx # rax <- vA - imulq (rFP,rINSTq,4), %rax - SET_WIDE_VREG %rax, %rcx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86_64/op_neg_double.S b/runtime/interpreter/mterp/x86_64/op_neg_double.S deleted file mode 100644 index 56e38041b1..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_neg_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_neg_double(): -% unop(preinstr=" movq $0x8000000000000000, %rsi", instr=" xorq %rsi, %rax", wide="1") diff --git a/runtime/interpreter/mterp/x86_64/op_neg_float.S b/runtime/interpreter/mterp/x86_64/op_neg_float.S deleted file mode 100644 index 6a39444963..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_neg_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_neg_float(): -% unop(instr=" xorl $0x80000000, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_neg_int.S b/runtime/interpreter/mterp/x86_64/op_neg_int.S deleted file mode 100644 index 44790edd51..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_neg_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_neg_int(): -% unop(instr=" negl %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_neg_long.S b/runtime/interpreter/mterp/x86_64/op_neg_long.S deleted file mode 100644 index 2d296ee19d..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_neg_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_neg_long(): -% unop(instr=" negq %rax", wide="1") diff --git a/runtime/interpreter/mterp/x86_64/op_new_array.S b/runtime/interpreter/mterp/x86_64/op_new_array.S deleted file mode 100644 index de1b0016d2..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_new_array.S +++ /dev/null @@ -1,19 +0,0 @@ -%def op_new_array(): -/* - * Allocate an array of objects, specified with the array class - * and a count. - * - * The verifier guarantees that this is an array class, so we don't - * check for it here. - */ - /* new-array vA, vB, class@CCCC */ - EXPORT_PC - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG0 - movq rPC, OUT_ARG1 - REFRESH_INST ${opnum} - movq rINSTq, OUT_ARG2 - movq rSELF, OUT_ARG3 - call SYMBOL(MterpNewArray) - testb %al, %al # 0 means an exception is thrown - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_new_instance.S b/runtime/interpreter/mterp/x86_64/op_new_instance.S deleted file mode 100644 index cc3f31cb5e..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_new_instance.S +++ /dev/null @@ -1,14 +0,0 @@ -%def op_new_instance(): -/* - * Create a new instance of a class. - */ - /* new-instance vAA, class@BBBB */ - EXPORT_PC - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG0 - movq rSELF, OUT_ARG1 - REFRESH_INST ${opnum} - movq rINSTq, OUT_ARG2 - call SYMBOL(MterpNewInstance) - testb %al, %al # 0 means an exception is thrown - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_nop.S b/runtime/interpreter/mterp/x86_64/op_nop.S deleted file mode 100644 index aa4a843ab5..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_nop.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_nop(): - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86_64/op_not_int.S b/runtime/interpreter/mterp/x86_64/op_not_int.S deleted file mode 100644 index 55ac8a7ff3..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_not_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_not_int(): -% unop(instr=" notl %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_not_long.S b/runtime/interpreter/mterp/x86_64/op_not_long.S deleted file mode 100644 index c6c0f859c3..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_not_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_not_long(): -% unop(instr=" notq %rax", wide="1") diff --git a/runtime/interpreter/mterp/x86_64/op_or_int.S b/runtime/interpreter/mterp/x86_64/op_or_int.S deleted file mode 100644 index 0e6dd67c27..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_or_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_or_int(): -% binop(instr="orl (rFP,%rcx,4), %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_or_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_or_int_2addr.S deleted file mode 100644 index c722938c82..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_or_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_or_int_2addr(): -% binop2addr(instr="orl %eax, (rFP,%rcx,4)") diff --git a/runtime/interpreter/mterp/x86_64/op_or_int_lit16.S b/runtime/interpreter/mterp/x86_64/op_or_int_lit16.S deleted file mode 100644 index ba9b6bff18..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_or_int_lit16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_or_int_lit16(): -% binopLit16(instr="orl %ecx, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_or_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_or_int_lit8.S deleted file mode 100644 index 758109bc05..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_or_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_or_int_lit8(): -% binopLit8(instr="orl %ecx, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_or_long.S b/runtime/interpreter/mterp/x86_64/op_or_long.S deleted file mode 100644 index b9c9321b2e..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_or_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_or_long(): -% binopWide(instr="orq (rFP,%rcx,4), %rax") diff --git a/runtime/interpreter/mterp/x86_64/op_or_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_or_long_2addr.S deleted file mode 100644 index 616288e315..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_or_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_or_long_2addr(): -% binopWide2addr(instr="orq %rax, (rFP,%rcx,4)") diff --git a/runtime/interpreter/mterp/x86_64/op_packed_switch.S b/runtime/interpreter/mterp/x86_64/op_packed_switch.S deleted file mode 100644 index 8b2b18b8cd..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_packed_switch.S +++ /dev/null @@ -1,18 +0,0 @@ -%def op_packed_switch(func="MterpDoPackedSwitch"): -/* - * Handle a packed-switch or sparse-switch instruction. In both cases - * we decode it and hand it off to a helper function. - * - * We don't really expect backward branches in a switch statement, but - * they're perfectly legal, so we check for them here. - * - * for: packed-switch, sparse-switch - */ - /* op vAA, +BBBB */ - movslq 2(rPC), OUT_ARG0 # rcx <- ssssssssBBBBbbbb - leaq (rPC,OUT_ARG0,2), OUT_ARG0 # rcx <- PC + ssssssssBBBBbbbb*2 - GET_VREG OUT_32_ARG1, rINSTq # eax <- vAA - call SYMBOL($func) - testl %eax, %eax - movslq %eax, rINSTq - jmp MterpCommonTakenBranch diff --git a/runtime/interpreter/mterp/x86_64/op_rem_double.S b/runtime/interpreter/mterp/x86_64/op_rem_double.S deleted file mode 100644 index 9b1c0b4bdc..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_rem_double.S +++ /dev/null @@ -1,15 +0,0 @@ -%def op_rem_double(): - /* rem_double vAA, vBB, vCC */ - movzbq 3(rPC), %rcx # ecx <- BB - movzbq 2(rPC), %rax # eax <- CC - fldl VREG_ADDRESS(%rcx) # %st1 <- fp[vBB] - fldl VREG_ADDRESS(%rax) # %st0 <- fp[vCC] -1: - fprem - fstsw %ax - sahf - jp 1b - fstp %st(1) - fstpl VREG_ADDRESS(rINSTq) # fp[vAA] <- %st - CLEAR_WIDE_REF rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_rem_double_2addr.S b/runtime/interpreter/mterp/x86_64/op_rem_double_2addr.S deleted file mode 100644 index 0600e90dfb..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_rem_double_2addr.S +++ /dev/null @@ -1,16 +0,0 @@ -%def op_rem_double_2addr(): - /* rem_double/2addr vA, vB */ - movzbq rINSTbl, %rcx # ecx <- A+ - sarl $$4, rINST # rINST <- B - fldl VREG_ADDRESS(rINSTq) # vB to fp stack - andb $$0xf, %cl # ecx <- A - fldl VREG_ADDRESS(%rcx) # vA to fp stack -1: - fprem - fstsw %ax - sahf - jp 1b - fstp %st(1) - fstpl VREG_ADDRESS(%rcx) # %st to vA - CLEAR_WIDE_REF %rcx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86_64/op_rem_float.S b/runtime/interpreter/mterp/x86_64/op_rem_float.S deleted file mode 100644 index 28c1328e7c..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_rem_float.S +++ /dev/null @@ -1,15 +0,0 @@ -%def op_rem_float(): - /* rem_float vAA, vBB, vCC */ - movzbq 3(rPC), %rcx # ecx <- BB - movzbq 2(rPC), %rax # eax <- CC - flds VREG_ADDRESS(%rcx) # vBB to fp stack - flds VREG_ADDRESS(%rax) # vCC to fp stack -1: - fprem - fstsw %ax - sahf - jp 1b - fstp %st(1) - fstps VREG_ADDRESS(rINSTq) # %st to vAA - CLEAR_REF rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_rem_float_2addr.S b/runtime/interpreter/mterp/x86_64/op_rem_float_2addr.S deleted file mode 100644 index 8cfdca080a..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_rem_float_2addr.S +++ /dev/null @@ -1,16 +0,0 @@ -%def op_rem_float_2addr(): - /* rem_float/2addr vA, vB */ - movzbq rINSTbl, %rcx # ecx <- A+ - sarl $$4, rINST # rINST <- B - flds VREG_ADDRESS(rINSTq) # vB to fp stack - andb $$0xf, %cl # ecx <- A - flds VREG_ADDRESS(%rcx) # vA to fp stack -1: - fprem - fstsw %ax - sahf - jp 1b - fstp %st(1) - fstps VREG_ADDRESS(%rcx) # %st to vA - CLEAR_REF %rcx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86_64/op_rem_int.S b/runtime/interpreter/mterp/x86_64/op_rem_int.S deleted file mode 100644 index 1530f5f944..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_rem_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_rem_int(): -% bindiv(result="%edx", second="%ecx", wide="0", suffix="l", rem="1") diff --git a/runtime/interpreter/mterp/x86_64/op_rem_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_rem_int_2addr.S deleted file mode 100644 index 742213a468..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_rem_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_rem_int_2addr(): -% bindiv2addr(result="%edx", second="%ecx", wide="0", suffix="l", rem="1") diff --git a/runtime/interpreter/mterp/x86_64/op_rem_int_lit16.S b/runtime/interpreter/mterp/x86_64/op_rem_int_lit16.S deleted file mode 100644 index eaa44a4608..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_rem_int_lit16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_rem_int_lit16(): -% bindivLit16(result="%edx", rem="1") diff --git a/runtime/interpreter/mterp/x86_64/op_rem_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_rem_int_lit8.S deleted file mode 100644 index 3fef144d1f..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_rem_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_rem_int_lit8(): -% bindivLit8(result="%edx", rem="1") diff --git a/runtime/interpreter/mterp/x86_64/op_rem_long.S b/runtime/interpreter/mterp/x86_64/op_rem_long.S deleted file mode 100644 index 60bfd3d9df..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_rem_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_rem_long(): -% bindiv(result="%rdx", second="%rcx", wide="1", suffix="q", ext="cqo", rem="1") diff --git a/runtime/interpreter/mterp/x86_64/op_rem_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_rem_long_2addr.S deleted file mode 100644 index fc5a2d0cb9..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_rem_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_rem_long_2addr(): -% bindiv2addr(result="%rdx", second="%rcx", wide="1", suffix="q", rem="1", ext="cqo") diff --git a/runtime/interpreter/mterp/x86_64/op_return.S b/runtime/interpreter/mterp/x86_64/op_return.S deleted file mode 100644 index b838f18b7c..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_return.S +++ /dev/null @@ -1,16 +0,0 @@ -%def op_return(): -/* - * Return a 32-bit value. - * - * for: return, return-object - */ - /* op vAA */ - .extern MterpThreadFenceForConstructor - call SYMBOL(MterpThreadFenceForConstructor) - movq rSELF, OUT_ARG0 - testl $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(OUT_ARG0) - jz 1f - call SYMBOL(MterpSuspendCheck) -1: - GET_VREG %eax, rINSTq # eax <- vAA - jmp MterpReturn diff --git a/runtime/interpreter/mterp/x86_64/op_return_object.S b/runtime/interpreter/mterp/x86_64/op_return_object.S deleted file mode 100644 index 2eeec0b948..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_return_object.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_return_object(): -% op_return() diff --git a/runtime/interpreter/mterp/x86_64/op_return_void.S b/runtime/interpreter/mterp/x86_64/op_return_void.S deleted file mode 100644 index 301dc92822..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_return_void.S +++ /dev/null @@ -1,10 +0,0 @@ -%def op_return_void(): - .extern MterpThreadFenceForConstructor - call SYMBOL(MterpThreadFenceForConstructor) - movq rSELF, OUT_ARG0 - testl $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(OUT_ARG0) - jz 1f - call SYMBOL(MterpSuspendCheck) -1: - xorq %rax, %rax - jmp MterpReturn diff --git a/runtime/interpreter/mterp/x86_64/op_return_void_no_barrier.S b/runtime/interpreter/mterp/x86_64/op_return_void_no_barrier.S deleted file mode 100644 index cec739c381..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_return_void_no_barrier.S +++ /dev/null @@ -1,8 +0,0 @@ -%def op_return_void_no_barrier(): - movq rSELF, OUT_ARG0 - testl $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(OUT_ARG0) - jz 1f - call SYMBOL(MterpSuspendCheck) -1: - xorq %rax, %rax - jmp MterpReturn diff --git a/runtime/interpreter/mterp/x86_64/op_return_wide.S b/runtime/interpreter/mterp/x86_64/op_return_wide.S deleted file mode 100644 index 90e0a42d62..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_return_wide.S +++ /dev/null @@ -1,14 +0,0 @@ -%def op_return_wide(): -/* - * Return a 64-bit value. - */ - /* return-wide vAA */ - .extern MterpThreadFenceForConstructor - call SYMBOL(MterpThreadFenceForConstructor) - movq rSELF, OUT_ARG0 - testl $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(OUT_ARG0) - jz 1f - call SYMBOL(MterpSuspendCheck) -1: - GET_WIDE_VREG %rax, rINSTq # eax <- v[AA] - jmp MterpReturn diff --git a/runtime/interpreter/mterp/x86_64/op_rsub_int.S b/runtime/interpreter/mterp/x86_64/op_rsub_int.S deleted file mode 100644 index 05ba130f2f..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_rsub_int.S +++ /dev/null @@ -1,3 +0,0 @@ -%def op_rsub_int(): -/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ -% binopLit16(instr="subl %eax, %ecx", result="%ecx") diff --git a/runtime/interpreter/mterp/x86_64/op_rsub_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_rsub_int_lit8.S deleted file mode 100644 index d0230476d7..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_rsub_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_rsub_int_lit8(): -% binopLit8(instr="subl %eax, %ecx", result="%ecx") diff --git a/runtime/interpreter/mterp/x86_64/op_sget.S b/runtime/interpreter/mterp/x86_64/op_sget.S deleted file mode 100644 index 8a6a66ab60..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_sget.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sget(is_object="0", helper="MterpSGetU32"): -% field(helper=helper) diff --git a/runtime/interpreter/mterp/x86_64/op_sget_boolean.S b/runtime/interpreter/mterp/x86_64/op_sget_boolean.S deleted file mode 100644 index d9c12c9b28..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_sget_boolean.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sget_boolean(): -% op_sget(helper="MterpSGetU8") diff --git a/runtime/interpreter/mterp/x86_64/op_sget_byte.S b/runtime/interpreter/mterp/x86_64/op_sget_byte.S deleted file mode 100644 index 37c6879cd4..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_sget_byte.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sget_byte(): -% op_sget(helper="MterpSGetI8") diff --git a/runtime/interpreter/mterp/x86_64/op_sget_char.S b/runtime/interpreter/mterp/x86_64/op_sget_char.S deleted file mode 100644 index 003bcd1683..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_sget_char.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sget_char(): -% op_sget(helper="MterpSGetU16") diff --git a/runtime/interpreter/mterp/x86_64/op_sget_object.S b/runtime/interpreter/mterp/x86_64/op_sget_object.S deleted file mode 100644 index 7cf3597f44..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_sget_object.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sget_object(): -% op_sget(is_object="1", helper="MterpSGetObj") diff --git a/runtime/interpreter/mterp/x86_64/op_sget_short.S b/runtime/interpreter/mterp/x86_64/op_sget_short.S deleted file mode 100644 index afacb578d9..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_sget_short.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sget_short(): -% op_sget(helper="MterpSGetI16") diff --git a/runtime/interpreter/mterp/x86_64/op_sget_wide.S b/runtime/interpreter/mterp/x86_64/op_sget_wide.S deleted file mode 100644 index fff2be6945..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_sget_wide.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sget_wide(): -% op_sget(helper="MterpSGetU64") diff --git a/runtime/interpreter/mterp/x86_64/op_shl_int.S b/runtime/interpreter/mterp/x86_64/op_shl_int.S deleted file mode 100644 index a98b256120..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_shl_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shl_int(): -% binop1(instr="sall %cl, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_shl_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_shl_int_2addr.S deleted file mode 100644 index 987c7d1e28..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_shl_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shl_int_2addr(): -% shop2addr(instr="sall %cl, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_shl_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_shl_int_lit8.S deleted file mode 100644 index ee1a15e696..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_shl_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shl_int_lit8(): -% binopLit8(instr="sall %cl, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_shl_long.S b/runtime/interpreter/mterp/x86_64/op_shl_long.S deleted file mode 100644 index c288b36352..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_shl_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shl_long(): -% binop1(instr="salq %cl, %rax", wide="1") diff --git a/runtime/interpreter/mterp/x86_64/op_shl_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_shl_long_2addr.S deleted file mode 100644 index 820e703975..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_shl_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shl_long_2addr(): -% shop2addr(instr="salq %cl, %rax", wide="1") diff --git a/runtime/interpreter/mterp/x86_64/op_shr_int.S b/runtime/interpreter/mterp/x86_64/op_shr_int.S deleted file mode 100644 index 4d4d79cc09..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_shr_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shr_int(): -% binop1(instr="sarl %cl, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_shr_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_shr_int_2addr.S deleted file mode 100644 index 8e4b055e15..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_shr_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shr_int_2addr(): -% shop2addr(instr="sarl %cl, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_shr_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_shr_int_lit8.S deleted file mode 100644 index a7acf5f384..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_shr_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shr_int_lit8(): -% binopLit8(instr="sarl %cl, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_shr_long.S b/runtime/interpreter/mterp/x86_64/op_shr_long.S deleted file mode 100644 index ed3e504a55..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_shr_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shr_long(): -% binop1(instr="sarq %cl, %rax", wide="1") diff --git a/runtime/interpreter/mterp/x86_64/op_shr_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_shr_long_2addr.S deleted file mode 100644 index be6898d5a6..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_shr_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_shr_long_2addr(): -% shop2addr(instr="sarq %cl, %rax", wide="1") diff --git a/runtime/interpreter/mterp/x86_64/op_sparse_switch.S b/runtime/interpreter/mterp/x86_64/op_sparse_switch.S deleted file mode 100644 index b74d7da816..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_sparse_switch.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sparse_switch(): -% op_packed_switch(func="MterpDoSparseSwitch") diff --git a/runtime/interpreter/mterp/x86_64/op_sput.S b/runtime/interpreter/mterp/x86_64/op_sput.S deleted file mode 100644 index cbd6ee96d3..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_sput.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sput(is_object="0", helper="MterpSPutU32"): -% field(helper=helper) diff --git a/runtime/interpreter/mterp/x86_64/op_sput_boolean.S b/runtime/interpreter/mterp/x86_64/op_sput_boolean.S deleted file mode 100644 index 36fba8448b..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_sput_boolean.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sput_boolean(): -% op_sput(helper="MterpSPutU8") diff --git a/runtime/interpreter/mterp/x86_64/op_sput_byte.S b/runtime/interpreter/mterp/x86_64/op_sput_byte.S deleted file mode 100644 index 84ad4a0ff8..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_sput_byte.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sput_byte(): -% op_sput(helper="MterpSPutI8") diff --git a/runtime/interpreter/mterp/x86_64/op_sput_char.S b/runtime/interpreter/mterp/x86_64/op_sput_char.S deleted file mode 100644 index 9b8eeba578..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_sput_char.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sput_char(): -% op_sput(helper="MterpSPutU16") diff --git a/runtime/interpreter/mterp/x86_64/op_sput_object.S b/runtime/interpreter/mterp/x86_64/op_sput_object.S deleted file mode 100644 index 081360c40f..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_sput_object.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sput_object(): -% op_sput(is_object="1", helper="MterpSPutObj") diff --git a/runtime/interpreter/mterp/x86_64/op_sput_short.S b/runtime/interpreter/mterp/x86_64/op_sput_short.S deleted file mode 100644 index ee16513486..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_sput_short.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sput_short(): -% op_sput(helper="MterpSPutI16") diff --git a/runtime/interpreter/mterp/x86_64/op_sput_wide.S b/runtime/interpreter/mterp/x86_64/op_sput_wide.S deleted file mode 100644 index 44c1a188ed..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_sput_wide.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sput_wide(): -% op_sput(helper="MterpSPutU64") diff --git a/runtime/interpreter/mterp/x86_64/op_sub_double.S b/runtime/interpreter/mterp/x86_64/op_sub_double.S deleted file mode 100644 index 64a28c376b..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_sub_double.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_double(): -% sseBinop(instr="subs", suff="d") diff --git a/runtime/interpreter/mterp/x86_64/op_sub_double_2addr.S b/runtime/interpreter/mterp/x86_64/op_sub_double_2addr.S deleted file mode 100644 index 753074bd37..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_sub_double_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_double_2addr(): -% sseBinop2Addr(instr="subs", suff="d") diff --git a/runtime/interpreter/mterp/x86_64/op_sub_float.S b/runtime/interpreter/mterp/x86_64/op_sub_float.S deleted file mode 100644 index 1a1966dba2..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_sub_float.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_float(): -% sseBinop(instr="subs", suff="s") diff --git a/runtime/interpreter/mterp/x86_64/op_sub_float_2addr.S b/runtime/interpreter/mterp/x86_64/op_sub_float_2addr.S deleted file mode 100644 index 9557907bd2..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_sub_float_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_float_2addr(): -% sseBinop2Addr(instr="subs", suff="s") diff --git a/runtime/interpreter/mterp/x86_64/op_sub_int.S b/runtime/interpreter/mterp/x86_64/op_sub_int.S deleted file mode 100644 index ecab19d72b..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_sub_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_int(): -% binop(instr="subl (rFP,%rcx,4), %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_sub_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_sub_int_2addr.S deleted file mode 100644 index 61fc7a7b15..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_sub_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_int_2addr(): -% binop2addr(instr="subl %eax, (rFP,%rcx,4)") diff --git a/runtime/interpreter/mterp/x86_64/op_sub_long.S b/runtime/interpreter/mterp/x86_64/op_sub_long.S deleted file mode 100644 index 9c38f88951..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_sub_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_long(): -% binopWide(instr="subq (rFP,%rcx,4), %rax") diff --git a/runtime/interpreter/mterp/x86_64/op_sub_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_sub_long_2addr.S deleted file mode 100644 index ab31aaff8f..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_sub_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_sub_long_2addr(): -% binopWide2addr(instr="subq %rax, (rFP,%rcx,4)") diff --git a/runtime/interpreter/mterp/x86_64/op_throw.S b/runtime/interpreter/mterp/x86_64/op_throw.S deleted file mode 100644 index 09fc1ec6b8..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_throw.S +++ /dev/null @@ -1,12 +0,0 @@ -%def op_throw(): -/* - * Throw an exception object in the current thread. - */ - /* throw vAA */ - EXPORT_PC - GET_VREG %eax, rINSTq # eax<- vAA (exception object) - testb %al, %al - jz common_errNullObject - movq rSELF, %rcx - movq %rax, THREAD_EXCEPTION_OFFSET(%rcx) - jmp MterpException diff --git a/runtime/interpreter/mterp/x86_64/op_unused_3e.S b/runtime/interpreter/mterp/x86_64/op_unused_3e.S deleted file mode 100644 index d889f1a5fb..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_unused_3e.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_3e(): -% unused() diff --git a/runtime/interpreter/mterp/x86_64/op_unused_3f.S b/runtime/interpreter/mterp/x86_64/op_unused_3f.S deleted file mode 100644 index b3ebcfaeaa..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_unused_3f.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_3f(): -% unused() diff --git a/runtime/interpreter/mterp/x86_64/op_unused_40.S b/runtime/interpreter/mterp/x86_64/op_unused_40.S deleted file mode 100644 index 7920fb350f..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_unused_40.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_40(): -% unused() diff --git a/runtime/interpreter/mterp/x86_64/op_unused_41.S b/runtime/interpreter/mterp/x86_64/op_unused_41.S deleted file mode 100644 index 5ed03b8506..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_unused_41.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_41(): -% unused() diff --git a/runtime/interpreter/mterp/x86_64/op_unused_42.S b/runtime/interpreter/mterp/x86_64/op_unused_42.S deleted file mode 100644 index ac32521add..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_unused_42.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_42(): -% unused() diff --git a/runtime/interpreter/mterp/x86_64/op_unused_43.S b/runtime/interpreter/mterp/x86_64/op_unused_43.S deleted file mode 100644 index 33e2aa10f8..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_unused_43.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_43(): -% unused() diff --git a/runtime/interpreter/mterp/x86_64/op_unused_79.S b/runtime/interpreter/mterp/x86_64/op_unused_79.S deleted file mode 100644 index 3c6dafc789..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_unused_79.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_79(): -% unused() diff --git a/runtime/interpreter/mterp/x86_64/op_unused_7a.S b/runtime/interpreter/mterp/x86_64/op_unused_7a.S deleted file mode 100644 index 9c03cd5535..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_unused_7a.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_7a(): -% unused() diff --git a/runtime/interpreter/mterp/x86_64/op_unused_f3.S b/runtime/interpreter/mterp/x86_64/op_unused_f3.S deleted file mode 100644 index ab10b78be2..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_unused_f3.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_f3(): -% unused() diff --git a/runtime/interpreter/mterp/x86_64/op_unused_f4.S b/runtime/interpreter/mterp/x86_64/op_unused_f4.S deleted file mode 100644 index 09229d6d99..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_unused_f4.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_f4(): -% unused() diff --git a/runtime/interpreter/mterp/x86_64/op_unused_f5.S b/runtime/interpreter/mterp/x86_64/op_unused_f5.S deleted file mode 100644 index 0d6149b5fd..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_unused_f5.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_f5(): -% unused() diff --git a/runtime/interpreter/mterp/x86_64/op_unused_f6.S b/runtime/interpreter/mterp/x86_64/op_unused_f6.S deleted file mode 100644 index 117b03de6d..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_unused_f6.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_f6(): -% unused() diff --git a/runtime/interpreter/mterp/x86_64/op_unused_f7.S b/runtime/interpreter/mterp/x86_64/op_unused_f7.S deleted file mode 100644 index 4e3a0f3c9a..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_unused_f7.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_f7(): -% unused() diff --git a/runtime/interpreter/mterp/x86_64/op_unused_f8.S b/runtime/interpreter/mterp/x86_64/op_unused_f8.S deleted file mode 100644 index d1220752d7..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_unused_f8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_f8(): -% unused() diff --git a/runtime/interpreter/mterp/x86_64/op_unused_f9.S b/runtime/interpreter/mterp/x86_64/op_unused_f9.S deleted file mode 100644 index 7d09a0ebcf..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_unused_f9.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_f9(): -% unused() diff --git a/runtime/interpreter/mterp/x86_64/op_unused_fc.S b/runtime/interpreter/mterp/x86_64/op_unused_fc.S deleted file mode 100644 index 06978191eb..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_unused_fc.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_fc(): -% unused() diff --git a/runtime/interpreter/mterp/x86_64/op_unused_fd.S b/runtime/interpreter/mterp/x86_64/op_unused_fd.S deleted file mode 100644 index 4bc2b4bdb6..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_unused_fd.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_unused_fd(): -% unused() diff --git a/runtime/interpreter/mterp/x86_64/op_ushr_int.S b/runtime/interpreter/mterp/x86_64/op_ushr_int.S deleted file mode 100644 index 38c8782ca9..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_ushr_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_ushr_int(): -% binop1(instr="shrl %cl, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_ushr_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_ushr_int_2addr.S deleted file mode 100644 index f1da71a47a..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_ushr_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_ushr_int_2addr(): -% shop2addr(instr="shrl %cl, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_ushr_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_ushr_int_lit8.S deleted file mode 100644 index 4298d36c3d..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_ushr_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_ushr_int_lit8(): -% binopLit8(instr="shrl %cl, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_ushr_long.S b/runtime/interpreter/mterp/x86_64/op_ushr_long.S deleted file mode 100644 index a0b4daf14d..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_ushr_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_ushr_long(): -% binop1(instr="shrq %cl, %rax", wide="1") diff --git a/runtime/interpreter/mterp/x86_64/op_ushr_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_ushr_long_2addr.S deleted file mode 100644 index 2213cf3865..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_ushr_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_ushr_long_2addr(): -% shop2addr(instr="shrq %cl, %rax", wide="1") diff --git a/runtime/interpreter/mterp/x86_64/op_xor_int.S b/runtime/interpreter/mterp/x86_64/op_xor_int.S deleted file mode 100644 index 5dc2603735..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_xor_int.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_xor_int(): -% binop(instr="xorl (rFP,%rcx,4), %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_xor_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_xor_int_2addr.S deleted file mode 100644 index 2c847028c5..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_xor_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_xor_int_2addr(): -% binop2addr(instr="xorl %eax, (rFP,%rcx,4)") diff --git a/runtime/interpreter/mterp/x86_64/op_xor_int_lit16.S b/runtime/interpreter/mterp/x86_64/op_xor_int_lit16.S deleted file mode 100644 index f5dc00e074..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_xor_int_lit16.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_xor_int_lit16(): -% binopLit16(instr="xorl %ecx, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_xor_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_xor_int_lit8.S deleted file mode 100644 index 98a1a432dd..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_xor_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_xor_int_lit8(): -% binopLit8(instr="xorl %ecx, %eax") diff --git a/runtime/interpreter/mterp/x86_64/op_xor_long.S b/runtime/interpreter/mterp/x86_64/op_xor_long.S deleted file mode 100644 index 1c267930d4..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_xor_long.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_xor_long(): -% binopWide(instr="xorq (rFP,%rcx,4), %rax") diff --git a/runtime/interpreter/mterp/x86_64/op_xor_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_xor_long_2addr.S deleted file mode 100644 index c6496517f7..0000000000 --- a/runtime/interpreter/mterp/x86_64/op_xor_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -%def op_xor_long_2addr(): -% binopWide2addr(instr="xorq %rax, (rFP,%rcx,4)") diff --git a/runtime/interpreter/mterp/x86_64/other.S b/runtime/interpreter/mterp/x86_64/other.S new file mode 100644 index 0000000000..849155ca8f --- /dev/null +++ b/runtime/interpreter/mterp/x86_64/other.S @@ -0,0 +1,287 @@ +%def const(helper="UndefinedConstHandler"): + /* const/class vAA, type@BBBB */ + /* const/method-handle vAA, method_handle@BBBB */ + /* const/method-type vAA, proto@BBBB */ + /* const/string vAA, string@@BBBB */ + .extern $helper + EXPORT_PC + movzwq 2(rPC), OUT_ARG0 # eax <- OUT_ARG0 + movq rINSTq, OUT_ARG1 + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 + movq rSELF, OUT_ARG3 + call SYMBOL($helper) # (index, tgt_reg, shadow_frame, self) + testb %al, %al + jnz MterpPossibleException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def unused(): +/* + * Bail to reference interpreter to throw. + */ + jmp MterpFallback + +%def op_const(): + /* const vAA, #+BBBBbbbb */ + movl 2(rPC), %eax # grab all 32 bits at once + SET_VREG %eax, rINSTq # vAA<- eax + ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 + +%def op_const_16(): + /* const/16 vAA, #+BBBB */ + movswl 2(rPC), %ecx # ecx <- ssssBBBB + SET_VREG %ecx, rINSTq # vAA <- ssssBBBB + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_const_4(): + /* const/4 vA, #+B */ + movsbl rINSTbl, %eax # eax <-ssssssBx + movl $$0xf, rINST + andl %eax, rINST # rINST <- A + sarl $$4, %eax + SET_VREG %eax, rINSTq + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_const_class(): +% const(helper="MterpConstClass") + +%def op_const_high16(): + /* const/high16 vAA, #+BBBB0000 */ + movzwl 2(rPC), %eax # eax <- 0000BBBB + sall $$16, %eax # eax <- BBBB0000 + SET_VREG %eax, rINSTq # vAA <- eax + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_const_method_handle(): +% const(helper="MterpConstMethodHandle") + +%def op_const_method_type(): +% const(helper="MterpConstMethodType") + +%def op_const_string(): +% const(helper="MterpConstString") + +%def op_const_string_jumbo(): + /* const/string vAA, String@BBBBBBBB */ + EXPORT_PC + movl 2(rPC), OUT_32_ARG0 # OUT_32_ARG0 <- BBBB + movq rINSTq, OUT_ARG1 + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 + movq rSELF, OUT_ARG3 + call SYMBOL(MterpConstString) # (index, tgt_reg, shadow_frame, self) + testb %al, %al + jnz MterpPossibleException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 + +%def op_const_wide(): + /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ + movq 2(rPC), %rax # rax <- HHHHhhhhBBBBbbbb + SET_WIDE_VREG %rax, rINSTq + ADVANCE_PC_FETCH_AND_GOTO_NEXT 5 + +%def op_const_wide_16(): + /* const-wide/16 vAA, #+BBBB */ + movswq 2(rPC), %rax # rax <- ssssBBBB + SET_WIDE_VREG %rax, rINSTq # store + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_const_wide_32(): + /* const-wide/32 vAA, #+BBBBbbbb */ + movslq 2(rPC), %rax # eax <- ssssssssBBBBbbbb + SET_WIDE_VREG %rax, rINSTq # store + ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 + +%def op_const_wide_high16(): + /* const-wide/high16 vAA, #+BBBB000000000000 */ + movzwq 2(rPC), %rax # eax <- 0000BBBB + salq $$48, %rax # eax <- BBBB0000 + SET_WIDE_VREG %rax, rINSTq # v[AA+0] <- eax + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_monitor_enter(): +/* + * Synchronize on an object. + */ + /* monitor-enter vAA */ + EXPORT_PC + GET_VREG OUT_32_ARG0, rINSTq + movq rSELF, OUT_ARG1 + call SYMBOL(artLockObjectFromCode) # (object, self) + testq %rax, %rax + jnz MterpException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_monitor_exit(): +/* + * Unlock an object. + * + * Exceptions that occur when unlocking a monitor need to appear as + * if they happened at the following instruction. See the Dalvik + * instruction spec. + */ + /* monitor-exit vAA */ + EXPORT_PC + GET_VREG OUT_32_ARG0, rINSTq + movq rSELF, OUT_ARG1 + call SYMBOL(artUnlockObjectFromCode) # (object, self) + testq %rax, %rax + jnz MterpException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_move(is_object="0"): + /* for move, move-object, long-to-int */ + /* op vA, vB */ + movl rINST, %eax # eax <- BA + andb $$0xf, %al # eax <- A + shrl $$4, rINST # rINST <- B + GET_VREG %edx, rINSTq + .if $is_object + SET_VREG_OBJECT %edx, %rax # fp[A] <- fp[B] + .else + SET_VREG %edx, %rax # fp[A] <- fp[B] + .endif + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_move_16(is_object="0"): + /* for: move/16, move-object/16 */ + /* op vAAAA, vBBBB */ + movzwq 4(rPC), %rcx # ecx <- BBBB + movzwq 2(rPC), %rax # eax <- AAAA + GET_VREG %edx, %rcx + .if $is_object + SET_VREG_OBJECT %edx, %rax # fp[A] <- fp[B] + .else + SET_VREG %edx, %rax # fp[A] <- fp[B] + .endif + ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 + +%def op_move_exception(): + /* move-exception vAA */ + movq rSELF, %rcx + movl THREAD_EXCEPTION_OFFSET(%rcx), %eax + SET_VREG_OBJECT %eax, rINSTq # fp[AA] <- exception object + movl $$0, THREAD_EXCEPTION_OFFSET(%rcx) + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_move_from16(is_object="0"): + /* for: move/from16, move-object/from16 */ + /* op vAA, vBBBB */ + movzwq 2(rPC), %rax # eax <- BBBB + GET_VREG %edx, %rax # edx <- fp[BBBB] + .if $is_object + SET_VREG_OBJECT %edx, rINSTq # fp[A] <- fp[B] + .else + SET_VREG %edx, rINSTq # fp[A] <- fp[B] + .endif + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_move_object(): +% op_move(is_object="1") + +%def op_move_object_16(): +% op_move_16(is_object="1") + +%def op_move_object_from16(): +% op_move_from16(is_object="1") + +%def op_move_result(is_object="0"): + /* for: move-result, move-result-object */ + /* op vAA */ + movq OFF_FP_RESULT_REGISTER(rFP), %rax # get pointer to result JType. + movl (%rax), %eax # r0 <- result.i. + .if $is_object + SET_VREG_OBJECT %eax, rINSTq # fp[A] <- fp[B] + .else + SET_VREG %eax, rINSTq # fp[A] <- fp[B] + .endif + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_move_result_object(): +% op_move_result(is_object="1") + +%def op_move_result_wide(): + /* move-result-wide vAA */ + movq OFF_FP_RESULT_REGISTER(rFP), %rax # get pointer to result JType. + movq (%rax), %rdx # Get wide + SET_WIDE_VREG %rdx, rINSTq # v[AA] <- rdx + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_move_wide(): + /* move-wide vA, vB */ + /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ + movl rINST, %ecx # ecx <- BA + sarl $$4, rINST # rINST <- B + andb $$0xf, %cl # ecx <- A + GET_WIDE_VREG %rdx, rINSTq # rdx <- v[B] + SET_WIDE_VREG %rdx, %rcx # v[A] <- rdx + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_move_wide_16(): + /* move-wide/16 vAAAA, vBBBB */ + /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ + movzwq 4(rPC), %rcx # ecx<- BBBB + movzwq 2(rPC), %rax # eax<- AAAA + GET_WIDE_VREG %rdx, %rcx # rdx <- v[B] + SET_WIDE_VREG %rdx, %rax # v[A] <- rdx + ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 + +%def op_move_wide_from16(): + /* move-wide/from16 vAA, vBBBB */ + /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ + movzwl 2(rPC), %ecx # ecx <- BBBB + GET_WIDE_VREG %rdx, %rcx # rdx <- v[B] + SET_WIDE_VREG %rdx, rINSTq # v[A] <- rdx + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_nop(): + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_unused_3e(): +% unused() + +%def op_unused_3f(): +% unused() + +%def op_unused_40(): +% unused() + +%def op_unused_41(): +% unused() + +%def op_unused_42(): +% unused() + +%def op_unused_43(): +% unused() + +%def op_unused_79(): +% unused() + +%def op_unused_7a(): +% unused() + +%def op_unused_f3(): +% unused() + +%def op_unused_f4(): +% unused() + +%def op_unused_f5(): +% unused() + +%def op_unused_f6(): +% unused() + +%def op_unused_f7(): +% unused() + +%def op_unused_f8(): +% unused() + +%def op_unused_f9(): +% unused() + +%def op_unused_fc(): +% unused() + +%def op_unused_fd(): +% unused() diff --git a/runtime/interpreter/mterp/x86_64/shop2addr.S b/runtime/interpreter/mterp/x86_64/shop2addr.S deleted file mode 100644 index d0d838b880..0000000000 --- a/runtime/interpreter/mterp/x86_64/shop2addr.S +++ /dev/null @@ -1,19 +0,0 @@ -%def shop2addr(wide="0", instr=""): -/* - * Generic 32-bit "shift/2addr" operation. - */ - /* shift/2addr vA, vB */ - movl rINST, %ecx # ecx <- BA - sarl $$4, %ecx # ecx <- B - GET_VREG %ecx, %rcx # ecx <- vBB - andb $$0xf, rINSTbl # rINST <- A - .if $wide - GET_WIDE_VREG %rax, rINSTq # rax <- vAA - $instr # ex: sarl %cl, %eax - SET_WIDE_VREG %rax, rINSTq - .else - GET_VREG %eax, rINSTq # eax <- vAA - $instr # ex: sarl %cl, %eax - SET_VREG %eax, rINSTq - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86_64/sseBinop.S b/runtime/interpreter/mterp/x86_64/sseBinop.S deleted file mode 100644 index 638ea8ef56..0000000000 --- a/runtime/interpreter/mterp/x86_64/sseBinop.S +++ /dev/null @@ -1,9 +0,0 @@ -%def sseBinop(instr="", suff=""): - movzbq 2(rPC), %rcx # ecx <- BB - movzbq 3(rPC), %rax # eax <- CC - movs${suff} VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src - ${instr}${suff} VREG_ADDRESS(%rax), %xmm0 - movs${suff} %xmm0, VREG_ADDRESS(rINSTq) # vAA <- %xmm0 - pxor %xmm0, %xmm0 - movs${suff} %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/sseBinop2Addr.S b/runtime/interpreter/mterp/x86_64/sseBinop2Addr.S deleted file mode 100644 index 1292a36de3..0000000000 --- a/runtime/interpreter/mterp/x86_64/sseBinop2Addr.S +++ /dev/null @@ -1,10 +0,0 @@ -%def sseBinop2Addr(instr="", suff=""): - movl rINST, %ecx # ecx <- A+ - andl $$0xf, %ecx # ecx <- A - movs${suff} VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src - sarl $$4, rINST # rINST<- B - ${instr}${suff} VREG_ADDRESS(rINSTq), %xmm0 - movs${suff} %xmm0, VREG_ADDRESS(%rcx) # vAA<- %xmm0 - pxor %xmm0, %xmm0 - movs${suff} %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86_64/unop.S b/runtime/interpreter/mterp/x86_64/unop.S deleted file mode 100644 index 1dd12a31a1..0000000000 --- a/runtime/interpreter/mterp/x86_64/unop.S +++ /dev/null @@ -1,22 +0,0 @@ -%def unop(preinstr="", instr="", wide="0"): -/* - * Generic 32/64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op eax". - */ - /* unop vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $$4,rINST # rINST <- B - .if ${wide} - GET_WIDE_VREG %rax, rINSTq # rax <- vB - .else - GET_VREG %eax, rINSTq # eax <- vB - .endif - andb $$0xf,%cl # ecx <- A -$preinstr -$instr - .if ${wide} - SET_WIDE_VREG %rax, %rcx - .else - SET_VREG %eax, %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86_64/unused.S b/runtime/interpreter/mterp/x86_64/unused.S deleted file mode 100644 index ef35b6e73f..0000000000 --- a/runtime/interpreter/mterp/x86_64/unused.S +++ /dev/null @@ -1,5 +0,0 @@ -%def unused(): -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback diff --git a/runtime/interpreter/mterp/x86_64/zcmp.S b/runtime/interpreter/mterp/x86_64/zcmp.S deleted file mode 100644 index e794fb0e5b..0000000000 --- a/runtime/interpreter/mterp/x86_64/zcmp.S +++ /dev/null @@ -1,18 +0,0 @@ -%def zcmp(revcmp=""): -/* - * Generic one-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - cmpl $$0, VREG_ADDRESS(rINSTq) # compare (vA, 0) - j${revcmp} 1f - movswq 2(rPC), rINSTq # fetch signed displacement - testq rINSTq, rINSTq - jmp MterpCommonTakenBranch -1: - cmpl $$JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 -- GitLab From 596cfdf505b573efa404fd51ab32eb9cf47c75dc Mon Sep 17 00:00:00 2001 From: David Srbecky Date: Tue, 11 Sep 2018 11:25:39 +0100 Subject: [PATCH 3/4] Remove "sister" code from mterp. The feature is barely used. Rename the snippets to "helper", and place them in the final assembly explicitly. Test: test-art-host-gtest Change-Id: I5ed735f254f00338a5be54b76887bac5d6fd8512 --- .../interpreter/mterp/arm/floating_point.S | 4 +-- runtime/interpreter/mterp/arm/main.S | 20 +++---------- runtime/interpreter/mterp/arm64/main.S | 20 ++----------- runtime/interpreter/mterp/common/gen_setup.py | 14 ++-------- runtime/interpreter/mterp/gen_mterp.py | 23 --------------- runtime/interpreter/mterp/mips/arithmetic.S | 28 +++++++++---------- .../interpreter/mterp/mips/floating_point.S | 12 ++++---- runtime/interpreter/mterp/mips/main.S | 22 +++++++-------- runtime/interpreter/mterp/mips64/main.S | 17 +++-------- runtime/interpreter/mterp/out/mterp_arm.S | 12 -------- runtime/interpreter/mterp/out/mterp_arm64.S | 13 --------- runtime/interpreter/mterp/out/mterp_mips.S | 8 ------ runtime/interpreter/mterp/out/mterp_mips64.S | 9 ------ runtime/interpreter/mterp/out/mterp_x86.S | 12 -------- runtime/interpreter/mterp/out/mterp_x86_64.S | 13 --------- runtime/interpreter/mterp/x86/main.S | 18 ++---------- runtime/interpreter/mterp/x86_64/main.S | 19 ++----------- 17 files changed, 51 insertions(+), 213 deletions(-) diff --git a/runtime/interpreter/mterp/arm/floating_point.S b/runtime/interpreter/mterp/arm/floating_point.S index 583010acc1..9f72464db6 100644 --- a/runtime/interpreter/mterp/arm/floating_point.S +++ b/runtime/interpreter/mterp/arm/floating_point.S @@ -327,7 +327,7 @@ %def op_double_to_long(): % unopWide(instr="bl d2l_doconv") -%def op_double_to_long_sister_code(): +%def op_double_to_long_helper_code(): /* * Convert the double in r0/r1 to a long in r0/r1. * @@ -368,7 +368,7 @@ d2l_maybeNaN: %def op_float_to_long(): % unopWider(instr="bl f2l_doconv") -%def op_float_to_long_sister_code(): +%def op_float_to_long_helper_code(): /* * Convert the float in r0 to a long in r0/r1. * diff --git a/runtime/interpreter/mterp/arm/main.S b/runtime/interpreter/mterp/arm/main.S index 73d45c0cbf..dbccb465d1 100644 --- a/runtime/interpreter/mterp/arm/main.S +++ b/runtime/interpreter/mterp/arm/main.S @@ -410,6 +410,10 @@ ENTRY ExecuteMterpImpl b MterpFallback +%def helpers(): +% op_float_to_long_helper_code() +% op_double_to_long_helper_code() + %def footer(): /* * =========================================================================== @@ -723,13 +727,6 @@ artMterpAsmInstructionEnd: .global artMterpAsmAltInstructionEnd artMterpAsmAltInstructionEnd: -%def instruction_end_sister(): - - .type artMterpAsmSisterEnd, #object - .hidden artMterpAsmSisterEnd - .global artMterpAsmSisterEnd -artMterpAsmSisterEnd: - %def instruction_start(): .type artMterpAsmInstructionStart, #object @@ -745,12 +742,3 @@ artMterpAsmInstructionStart = .L_op_nop .global artMterpAsmAltInstructionStart artMterpAsmAltInstructionStart = .L_ALT_op_nop .text - -%def instruction_start_sister(): - - .type artMterpAsmSisterStart, #object - .hidden artMterpAsmSisterStart - .global artMterpAsmSisterStart - .text - .balign 4 -artMterpAsmSisterStart: diff --git a/runtime/interpreter/mterp/arm64/main.S b/runtime/interpreter/mterp/arm64/main.S index 37ed83d60f..963e724563 100644 --- a/runtime/interpreter/mterp/arm64/main.S +++ b/runtime/interpreter/mterp/arm64/main.S @@ -435,7 +435,7 @@ ENTRY ExecuteMterpImpl mov x2, xPC b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. -%def close_cfi(): +%def footer(): // Close out the cfi info. We're treating mterp as a single function. END ExecuteMterpImpl @@ -446,7 +446,7 @@ END ExecuteMterpImpl b MterpFallback -%def footer(): +%def helpers(): /* * =========================================================================== * Common subroutines and data @@ -766,13 +766,6 @@ artMterpAsmInstructionEnd: .global artMterpAsmAltInstructionEnd artMterpAsmAltInstructionEnd: -%def instruction_end_sister(): - - .type artMterpAsmSisterEnd, #object - .hidden artMterpAsmSisterEnd - .global artMterpAsmSisterEnd -artMterpAsmSisterEnd: - %def instruction_start(): .type artMterpAsmInstructionStart, #object @@ -788,12 +781,3 @@ artMterpAsmInstructionStart = .L_op_nop .global artMterpAsmAltInstructionStart artMterpAsmAltInstructionStart = .L_ALT_op_nop .text - -%def instruction_start_sister(): - - .type artMterpAsmSisterStart, #object - .hidden artMterpAsmSisterStart - .global artMterpAsmSisterStart - .text - .balign 4 -artMterpAsmSisterStart: diff --git a/runtime/interpreter/mterp/common/gen_setup.py b/runtime/interpreter/mterp/common/gen_setup.py index b2e62f6ea0..48417e80b8 100644 --- a/runtime/interpreter/mterp/common/gen_setup.py +++ b/runtime/interpreter/mterp/common/gen_setup.py @@ -58,24 +58,14 @@ def generate(): balign() instruction_end() - instruction_start_sister() - write_sister() - instruction_end_sister() - - # We need to footer sooner so that branch instruction can reach it. - # TODO: Clean up. - if arch == "arm64": - footer() + helpers() instruction_start_alt() opcodes(is_alt = True) balign() instruction_end_alt() - if arch == "arm64": - close_cfi() - else: - footer() + footer() out.seek(0) # Squash consequtive empty lines. diff --git a/runtime/interpreter/mterp/gen_mterp.py b/runtime/interpreter/mterp/gen_mterp.py index cf69bcecc3..98a98fcf6d 100755 --- a/runtime/interpreter/mterp/gen_mterp.py +++ b/runtime/interpreter/mterp/gen_mterp.py @@ -85,29 +85,6 @@ def generate_script(arch, setup_code): script.write("\n") f.close() - # TODO: Remove the concept of sister snippets. It is barely used. - script.write("def write_sister():\n") - if arch == "arm": - script.write(" op_float_to_long_sister_code()\n") - script.write(" op_double_to_long_sister_code()\n") - if arch == "mips": - script.write(" global opnum, opcode\n") - names = [ - "op_float_to_long", - "op_double_to_long", - "op_mul_long", - "op_shl_long", - "op_shr_long", - "op_ushr_long", - "op_shl_long_2addr", - "op_shr_long_2addr", - "op_ushr_long_2addr" - ] - for name in names: - script.write(' opcode = "' + name + '"\n') - script.write(" " + name + "_sister_code()\n") - script.write(" pass\n") - script.write('generate()\n') script.seek(0) return script.read() diff --git a/runtime/interpreter/mterp/mips/arithmetic.S b/runtime/interpreter/mterp/mips/arithmetic.S index 0743bdea76..9ae10f2ba9 100644 --- a/runtime/interpreter/mterp/mips/arithmetic.S +++ b/runtime/interpreter/mterp/mips/arithmetic.S @@ -441,9 +441,9 @@ GET_OPA(a0) # a0 <- AA FETCH_ADVANCE_INST(2) # advance rPC, load rINST b .L${opcode}_finish -%def op_mul_long_sister_code(): +%def op_mul_long_helper_code(): -.L${opcode}_finish: +.Lop_mul_long_finish: GET_INST_OPCODE(t0) # extract opcode from rINST SET_VREG64_GOTO(v0, v1, a0, t0) # vAA/vAA+1 <- v0(low)/v1(high) @@ -586,9 +586,9 @@ sll v1, a1, a2 # rhi<- ahi << (shift&31) or v1, a0 # rhi<- rhi | alo SET_VREG64_GOTO(v0, v1, t2, t0) # vAA/vAA+1 <- v0/v1 -%def op_shl_long_sister_code(): +%def op_shl_long_helper_code(): -.L${opcode}_finish: +.Lop_shl_long_finish: SET_VREG64_GOTO(zero, v0, t2, t0) # vAA/vAA+1 <- rlo/rhi %def op_shl_long_2addr(): @@ -615,9 +615,9 @@ sll v1, a1, a2 # rhi<- ahi << (shift&31) or v1, a0 # rhi<- rhi | alo SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vA/vA+1 <- v0/v1 -%def op_shl_long_2addr_sister_code(): +%def op_shl_long_2addr_helper_code(): -.L${opcode}_finish: +.Lop_shl_long_2addr_finish: SET_VREG64_GOTO(zero, v0, rOBJ, t0) # vA/vA+1 <- rlo/rhi %def op_shr_int(): @@ -656,9 +656,9 @@ sll a1, a0 # ahi<- ahi << (32-(shift&31)) or v0, a1 # rlo<- rlo | ahi SET_VREG64_GOTO(v0, v1, t3, t0) # vAA/VAA+1 <- v0/v1 -%def op_shr_long_sister_code(): +%def op_shr_long_helper_code(): -.L${opcode}_finish: +.Lop_shr_long_finish: sra a3, a1, 31 # a3<- sign(ah) SET_VREG64_GOTO(v1, a3, t3, t0) # vAA/VAA+1 <- rlo/rhi @@ -685,9 +685,9 @@ sll a1, a0 # ahi<- ahi << (32-(shift&31)) or v0, a1 # rlo<- rlo | ahi SET_VREG64_GOTO(v0, v1, t2, t0) # vA/vA+1 <- v0/v1 -%def op_shr_long_2addr_sister_code(): +%def op_shr_long_2addr_helper_code(): -.L${opcode}_finish: +.Lop_shr_long_2addr_finish: sra a3, a1, 31 # a3<- sign(ah) SET_VREG64_GOTO(v1, a3, t2, t0) # vA/vA+1 <- rlo/rhi @@ -750,9 +750,9 @@ sll a1, a0 # ahi<- ahi << (32-(shift&31)) or v0, a1 # rlo<- rlo | ahi SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vAA/vAA+1 <- v0/v1 -%def op_ushr_long_sister_code(): +%def op_ushr_long_helper_code(): -.L${opcode}_finish: +.Lop_ushr_long_finish: SET_VREG64_GOTO(v1, zero, rOBJ, t0) # vAA/vAA+1 <- rlo/rhi %def op_ushr_long_2addr(): @@ -779,9 +779,9 @@ sll a1, a0 # ahi<- ahi << (32-(shift&31)) or v0, a1 # rlo<- rlo | ahi SET_VREG64_GOTO(v0, v1, t3, t0) # vA/vA+1 <- v0/v1 -%def op_ushr_long_2addr_sister_code(): +%def op_ushr_long_2addr_helper_code(): -.L${opcode}_finish: +.Lop_ushr_long_2addr_finish: SET_VREG64_GOTO(v1, zero, t3, t0) # vA/vA+1 <- rlo/rhi %def op_xor_int(): diff --git a/runtime/interpreter/mterp/mips/floating_point.S b/runtime/interpreter/mterp/mips/floating_point.S index 6f0dda3dbc..20df51e292 100644 --- a/runtime/interpreter/mterp/mips/floating_point.S +++ b/runtime/interpreter/mterp/mips/floating_point.S @@ -332,12 +332,12 @@ GET_INST_OPCODE(t1) # extract opcode from rINST b .L${opcode}_set_vreg #endif -%def op_double_to_long_sister_code(): +%def op_double_to_long_helper_code(): #ifndef MIPS32REVGE6 -.L${opcode}_get_opcode: +.Lop_double_to_long_get_opcode: GET_INST_OPCODE(t1) # extract opcode from rINST -.L${opcode}_set_vreg: +.Lop_double_to_long_set_vreg: SET_VREG64_GOTO(rRESULT0, rRESULT1, rOBJ, t1) # vA/vA+1 <- v0/v1 #endif @@ -416,12 +416,12 @@ GET_INST_OPCODE(t1) # extract opcode from rINST b .L${opcode}_set_vreg #endif -%def op_float_to_long_sister_code(): +%def op_float_to_long_helper_code(): #ifndef MIPS32REVGE6 -.L${opcode}_get_opcode: +.Lop_float_to_long_get_opcode: GET_INST_OPCODE(t1) # extract opcode from rINST -.L${opcode}_set_vreg: +.Lop_float_to_long_set_vreg: SET_VREG64_GOTO(rRESULT0, rRESULT1, rOBJ, t1) # vA/vA+1 <- v0/v1 #endif diff --git a/runtime/interpreter/mterp/mips/main.S b/runtime/interpreter/mterp/mips/main.S index 6e91af8a70..02c59b13e0 100644 --- a/runtime/interpreter/mterp/mips/main.S +++ b/runtime/interpreter/mterp/mips/main.S @@ -822,6 +822,17 @@ ExecuteMterpImpl: /* Transfer stub to alternate interpreter */ b MterpFallback +%def helpers(): +% op_float_to_long_helper_code() +% op_double_to_long_helper_code() +% op_mul_long_helper_code() +% op_shl_long_helper_code() +% op_shr_long_helper_code() +% op_ushr_long_helper_code() +% op_shl_long_2addr_helper_code() +% op_shr_long_2addr_helper_code() +% op_ushr_long_2addr_helper_code() + %def footer(): /* * =========================================================================== @@ -1122,11 +1133,6 @@ artMterpAsmInstructionEnd: .global artMterpAsmAltInstructionEnd artMterpAsmAltInstructionEnd: -%def instruction_end_sister(): - - .global artMterpAsmSisterEnd -artMterpAsmSisterEnd: - %def instruction_start(): .global artMterpAsmInstructionStart @@ -1139,9 +1145,3 @@ artMterpAsmInstructionStart = .L_op_nop artMterpAsmAltInstructionStart = .L_ALT_op_nop .text -%def instruction_start_sister(): - - .global artMterpAsmSisterStart - .text - .balign 4 -artMterpAsmSisterStart: diff --git a/runtime/interpreter/mterp/mips64/main.S b/runtime/interpreter/mterp/mips64/main.S index c2c305ac76..517bddfa21 100644 --- a/runtime/interpreter/mterp/mips64/main.S +++ b/runtime/interpreter/mterp/mips64/main.S @@ -444,6 +444,9 @@ ExecuteMterpImpl: /* Transfer stub to alternate interpreter */ b MterpFallback +%def helpers(): +% pass + %def footer(): /* * We've detected a condition that will result in an exception, but the exception @@ -618,7 +621,7 @@ MterpCommonTakenBranchNoFlags: EXPORT_PC jal MterpMaybeDoOnStackReplacement # (self, shadow_frame, offset) bnezc v0, MterpOnStackReplacement - FETCH_ADVANCE_INST 2 + FETCH_ADVANCE_INST 2 GET_INST_OPCODE v0 # extract opcode from rINST GOTO_OPCODE v0 # jump to next instruction @@ -732,11 +735,6 @@ artMterpAsmInstructionEnd: .global artMterpAsmAltInstructionEnd artMterpAsmAltInstructionEnd: -%def instruction_end_sister(): - - .global artMterpAsmSisterEnd -artMterpAsmSisterEnd: - %def instruction_start(): .global artMterpAsmInstructionStart @@ -748,10 +746,3 @@ artMterpAsmInstructionStart = .L_op_nop .global artMterpAsmAltInstructionStart artMterpAsmAltInstructionStart = .L_ALT_op_nop .text - -%def instruction_start_sister(): - - .global artMterpAsmSisterStart - .text - .balign 4 -artMterpAsmSisterStart: diff --git a/runtime/interpreter/mterp/out/mterp_arm.S b/runtime/interpreter/mterp/out/mterp_arm.S index b0595648b2..6e2b1acc3d 100644 --- a/runtime/interpreter/mterp/out/mterp_arm.S +++ b/runtime/interpreter/mterp/out/mterp_arm.S @@ -6701,12 +6701,6 @@ constvalop_long_to_double: .global artMterpAsmInstructionEnd artMterpAsmInstructionEnd: - .type artMterpAsmSisterStart, #object - .hidden artMterpAsmSisterStart - .global artMterpAsmSisterStart - .text - .balign 4 -artMterpAsmSisterStart: /* * Convert the float in r0 to a long in r0/r1. * @@ -6767,17 +6761,11 @@ d2l_maybeNaN: mov r1, #0 bx lr @ return 0 for NaN - .type artMterpAsmSisterEnd, #object - .hidden artMterpAsmSisterEnd - .global artMterpAsmSisterEnd -artMterpAsmSisterEnd: - .type artMterpAsmAltInstructionStart, #object .hidden artMterpAsmAltInstructionStart .global artMterpAsmAltInstructionStart artMterpAsmAltInstructionStart = .L_ALT_op_nop .text - /* ------------------------------ */ .balign 128 .L_ALT_op_nop: /* 0x00 */ diff --git a/runtime/interpreter/mterp/out/mterp_arm64.S b/runtime/interpreter/mterp/out/mterp_arm64.S index d65019dcb6..24a2252d94 100644 --- a/runtime/interpreter/mterp/out/mterp_arm64.S +++ b/runtime/interpreter/mterp/out/mterp_arm64.S @@ -6226,18 +6226,6 @@ artMterpAsmInstructionStart = .L_op_nop .global artMterpAsmInstructionEnd artMterpAsmInstructionEnd: - .type artMterpAsmSisterStart, #object - .hidden artMterpAsmSisterStart - .global artMterpAsmSisterStart - .text - .balign 4 -artMterpAsmSisterStart: - - .type artMterpAsmSisterEnd, #object - .hidden artMterpAsmSisterEnd - .global artMterpAsmSisterEnd -artMterpAsmSisterEnd: - /* * =========================================================================== * Common subroutines and data @@ -6547,7 +6535,6 @@ MterpProfileActive: .global artMterpAsmAltInstructionStart artMterpAsmAltInstructionStart = .L_ALT_op_nop .text - /* ------------------------------ */ .balign 128 .L_ALT_op_nop: /* 0x00 */ diff --git a/runtime/interpreter/mterp/out/mterp_mips.S b/runtime/interpreter/mterp/out/mterp_mips.S index 91d4ca113b..ff2605dfcd 100644 --- a/runtime/interpreter/mterp/out/mterp_mips.S +++ b/runtime/interpreter/mterp/out/mterp_mips.S @@ -6708,11 +6708,6 @@ TODO .global artMterpAsmInstructionEnd artMterpAsmInstructionEnd: - .global artMterpAsmSisterStart - .text - .balign 4 -artMterpAsmSisterStart: - #ifndef MIPS32REVGE6 .Lop_float_to_long_get_opcode: GET_INST_OPCODE(t1) # extract opcode from rINST @@ -6751,9 +6746,6 @@ artMterpAsmSisterStart: .Lop_ushr_long_2addr_finish: SET_VREG64_GOTO(v1, zero, t3, t0) # vA/vA+1 <- rlo/rhi - .global artMterpAsmSisterEnd -artMterpAsmSisterEnd: - .global artMterpAsmAltInstructionStart artMterpAsmAltInstructionStart = .L_ALT_op_nop .text diff --git a/runtime/interpreter/mterp/out/mterp_mips64.S b/runtime/interpreter/mterp/out/mterp_mips64.S index 86b16a1ca8..fa0744259c 100644 --- a/runtime/interpreter/mterp/out/mterp_mips64.S +++ b/runtime/interpreter/mterp/out/mterp_mips64.S @@ -6068,18 +6068,9 @@ TODO .global artMterpAsmInstructionEnd artMterpAsmInstructionEnd: - .global artMterpAsmSisterStart - .text - .balign 4 -artMterpAsmSisterStart: - - .global artMterpAsmSisterEnd -artMterpAsmSisterEnd: - .global artMterpAsmAltInstructionStart artMterpAsmAltInstructionStart = .L_ALT_op_nop .text - /* ------------------------------ */ .balign 128 .L_ALT_op_nop: /* 0x00 */ diff --git a/runtime/interpreter/mterp/out/mterp_x86.S b/runtime/interpreter/mterp/out/mterp_x86.S index fb182fdf4d..e2793ba2bf 100644 --- a/runtime/interpreter/mterp/out/mterp_x86.S +++ b/runtime/interpreter/mterp/out/mterp_x86.S @@ -5660,18 +5660,6 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .global SYMBOL(artMterpAsmInstructionEnd) SYMBOL(artMterpAsmInstructionEnd): - OBJECT_TYPE(artMterpAsmSisterStart) - ASM_HIDDEN SYMBOL(artMterpAsmSisterStart) - .global SYMBOL(artMterpAsmSisterStart) - .text - .balign 4 -SYMBOL(artMterpAsmSisterStart): - - OBJECT_TYPE(artMterpAsmSisterEnd) - ASM_HIDDEN SYMBOL(artMterpAsmSisterEnd) - .global SYMBOL(artMterpAsmSisterEnd) -SYMBOL(artMterpAsmSisterEnd): - OBJECT_TYPE(artMterpAsmAltInstructionStart) ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionStart) .global SYMBOL(artMterpAsmAltInstructionStart) diff --git a/runtime/interpreter/mterp/out/mterp_x86_64.S b/runtime/interpreter/mterp/out/mterp_x86_64.S index abb8986efb..96f5204063 100644 --- a/runtime/interpreter/mterp/out/mterp_x86_64.S +++ b/runtime/interpreter/mterp/out/mterp_x86_64.S @@ -5352,24 +5352,11 @@ movswl %ax, %eax .global SYMBOL(artMterpAsmInstructionEnd) SYMBOL(artMterpAsmInstructionEnd): - OBJECT_TYPE(artMterpAsmSisterStart) - ASM_HIDDEN SYMBOL(artMterpAsmSisterStart) - .global SYMBOL(artMterpAsmSisterStart) - .text - .balign 4 -SYMBOL(artMterpAsmSisterStart): - - OBJECT_TYPE(artMterpAsmSisterEnd) - ASM_HIDDEN SYMBOL(artMterpAsmSisterEnd) - .global SYMBOL(artMterpAsmSisterEnd) -SYMBOL(artMterpAsmSisterEnd): - OBJECT_TYPE(artMterpAsmAltInstructionStart) ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionStart) .global SYMBOL(artMterpAsmAltInstructionStart) .text SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop - /* ------------------------------ */ .balign 128 .L_ALT_op_nop: /* 0x00 */ diff --git a/runtime/interpreter/mterp/x86/main.S b/runtime/interpreter/mterp/x86/main.S index 2dec6b4774..ac0bb20fcb 100644 --- a/runtime/interpreter/mterp/x86/main.S +++ b/runtime/interpreter/mterp/x86/main.S @@ -427,6 +427,9 @@ SYMBOL(ExecuteMterpImpl): jmp MterpFallback +%def helpers(): +% pass + %def footer(): /* * =========================================================================== @@ -768,13 +771,6 @@ SYMBOL(artMterpAsmInstructionEnd): .global SYMBOL(artMterpAsmAltInstructionEnd) SYMBOL(artMterpAsmAltInstructionEnd): -%def instruction_end_sister(): - - OBJECT_TYPE(artMterpAsmSisterEnd) - ASM_HIDDEN SYMBOL(artMterpAsmSisterEnd) - .global SYMBOL(artMterpAsmSisterEnd) -SYMBOL(artMterpAsmSisterEnd): - %def instruction_start(): OBJECT_TYPE(artMterpAsmInstructionStart) @@ -791,11 +787,3 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .text SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop -%def instruction_start_sister(): - - OBJECT_TYPE(artMterpAsmSisterStart) - ASM_HIDDEN SYMBOL(artMterpAsmSisterStart) - .global SYMBOL(artMterpAsmSisterStart) - .text - .balign 4 -SYMBOL(artMterpAsmSisterStart): diff --git a/runtime/interpreter/mterp/x86_64/main.S b/runtime/interpreter/mterp/x86_64/main.S index aa47c6de8a..83dc27f319 100644 --- a/runtime/interpreter/mterp/x86_64/main.S +++ b/runtime/interpreter/mterp/x86_64/main.S @@ -407,6 +407,9 @@ SYMBOL(ExecuteMterpImpl): jmp MterpFallback +%def helpers(): +% pass + %def footer(): /* * =========================================================================== @@ -720,13 +723,6 @@ SYMBOL(artMterpAsmInstructionEnd): .global SYMBOL(artMterpAsmAltInstructionEnd) SYMBOL(artMterpAsmAltInstructionEnd): -%def instruction_end_sister(): - - OBJECT_TYPE(artMterpAsmSisterEnd) - ASM_HIDDEN SYMBOL(artMterpAsmSisterEnd) - .global SYMBOL(artMterpAsmSisterEnd) -SYMBOL(artMterpAsmSisterEnd): - %def instruction_start(): OBJECT_TYPE(artMterpAsmInstructionStart) @@ -742,12 +738,3 @@ SYMBOL(artMterpAsmInstructionStart) = .L_op_nop .global SYMBOL(artMterpAsmAltInstructionStart) .text SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop - -%def instruction_start_sister(): - - OBJECT_TYPE(artMterpAsmSisterStart) - ASM_HIDDEN SYMBOL(artMterpAsmSisterStart) - .global SYMBOL(artMterpAsmSisterStart) - .text - .balign 4 -SYMBOL(artMterpAsmSisterStart): -- GitLab From bfbc6547d732a984d43addc2869dbf32d61dab2f Mon Sep 17 00:00:00 2001 From: David Srbecky Date: Tue, 11 Sep 2018 13:34:57 +0100 Subject: [PATCH 4/4] Remove intermediate mterp files from the repository. Generate them in the build system properly. Bug: 33375800 Test: check that the generated files are still identical Change-Id: I6058c2d8d28586414f28dc024a3c0199d993552b --- runtime/Android.bp | 60 +- runtime/interpreter/mterp/common/gen_setup.py | 4 +- runtime/interpreter/mterp/gen_mterp.py | 50 +- runtime/interpreter/mterp/out/mterp_arm.S | 11424 --------------- runtime/interpreter/mterp/out/mterp_arm64.S | 10644 -------------- runtime/interpreter/mterp/out/mterp_mips.S | 11398 --------------- runtime/interpreter/mterp/out/mterp_mips64.S | 10963 -------------- runtime/interpreter/mterp/out/mterp_x86.S | 11889 ---------------- runtime/interpreter/mterp/out/mterp_x86_64.S | 11040 -------------- 9 files changed, 81 insertions(+), 67391 deletions(-) delete mode 100644 runtime/interpreter/mterp/out/mterp_arm.S delete mode 100644 runtime/interpreter/mterp/out/mterp_arm64.S delete mode 100644 runtime/interpreter/mterp/out/mterp_mips.S delete mode 100644 runtime/interpreter/mterp/out/mterp_mips64.S delete mode 100644 runtime/interpreter/mterp/out/mterp_x86.S delete mode 100644 runtime/interpreter/mterp/out/mterp_x86_64.S diff --git a/runtime/Android.bp b/runtime/Android.bp index 1cebb06570..15ccb70df0 100644 --- a/runtime/Android.bp +++ b/runtime/Android.bp @@ -246,7 +246,7 @@ libart_cc_defaults { arm: { srcs: [ "interpreter/mterp/mterp.cc", - "interpreter/mterp/out/mterp_arm.S", + ":libart_mterp.arm", "arch/arm/context_arm.cc", "arch/arm/entrypoints_init_arm.cc", "arch/arm/instruction_set_features_assembly_tests.S", @@ -261,7 +261,7 @@ libart_cc_defaults { arm64: { srcs: [ "interpreter/mterp/mterp.cc", - "interpreter/mterp/out/mterp_arm64.S", + ":libart_mterp.arm64", "arch/arm64/context_arm64.cc", "arch/arm64/entrypoints_init_arm64.cc", "arch/arm64/jni_entrypoints_arm64.S", @@ -275,7 +275,7 @@ libart_cc_defaults { x86: { srcs: [ "interpreter/mterp/mterp.cc", - "interpreter/mterp/out/mterp_x86.S", + ":libart_mterp.x86", "arch/x86/context_x86.cc", "arch/x86/entrypoints_init_x86.cc", "arch/x86/jni_entrypoints_x86.S", @@ -290,7 +290,7 @@ libart_cc_defaults { // Note that the fault_handler_x86.cc is not a mistake. This file is // shared between the x86 and x86_64 architectures. "interpreter/mterp/mterp.cc", - "interpreter/mterp/out/mterp_x86_64.S", + ":libart_mterp.x86_64", "arch/x86_64/context_x86_64.cc", "arch/x86_64/entrypoints_init_x86_64.cc", "arch/x86_64/jni_entrypoints_x86_64.S", @@ -304,7 +304,7 @@ libart_cc_defaults { mips: { srcs: [ "interpreter/mterp/mterp.cc", - "interpreter/mterp/out/mterp_mips.S", + ":libart_mterp.mips", "arch/mips/context_mips.cc", "arch/mips/entrypoints_init_mips.cc", "arch/mips/jni_entrypoints_mips.S", @@ -317,7 +317,7 @@ libart_cc_defaults { mips64: { srcs: [ "interpreter/mterp/mterp.cc", - "interpreter/mterp/out/mterp_mips64.S", + ":libart_mterp.mips64", "arch/mips64/context_mips64.cc", "arch/mips64/entrypoints_init_mips64.cc", "arch/mips64/jni_entrypoints_mips64.S", @@ -669,3 +669,51 @@ cc_library_headers { host_supported: true, export_include_dirs: ["."], } + +genrule { + name: "libart_mterp.arm", + out: ["mterp_arm.S"], + srcs: ["interpreter/mterp/arm/*.S"], + tool_files: ["interpreter/mterp/gen_mterp.py", "interpreter/mterp/common/gen_setup.py"], + cmd: "$(location interpreter/mterp/gen_mterp.py) $(out) $(in)", +} + +genrule { + name: "libart_mterp.arm64", + out: ["mterp_arm64.S"], + srcs: ["interpreter/mterp/arm64/*.S"], + tool_files: ["interpreter/mterp/gen_mterp.py", "interpreter/mterp/common/gen_setup.py"], + cmd: "$(location interpreter/mterp/gen_mterp.py) $(out) $(in)", +} + +genrule { + name: "libart_mterp.mips", + out: ["mterp_mips.S"], + srcs: ["interpreter/mterp/mips/*.S"], + tool_files: ["interpreter/mterp/gen_mterp.py", "interpreter/mterp/common/gen_setup.py"], + cmd: "$(location interpreter/mterp/gen_mterp.py) $(out) $(in)", +} + +genrule { + name: "libart_mterp.mips64", + out: ["mterp_mips64.S"], + srcs: ["interpreter/mterp/mips64/*.S"], + tool_files: ["interpreter/mterp/gen_mterp.py", "interpreter/mterp/common/gen_setup.py"], + cmd: "$(location interpreter/mterp/gen_mterp.py) $(out) $(in)", +} + +genrule { + name: "libart_mterp.x86", + out: ["mterp_x86.S"], + srcs: ["interpreter/mterp/x86/*.S"], + tool_files: ["interpreter/mterp/gen_mterp.py", "interpreter/mterp/common/gen_setup.py"], + cmd: "$(location interpreter/mterp/gen_mterp.py) $(out) $(in)", +} + +genrule { + name: "libart_mterp.x86_64", + out: ["mterp_x86_64.S"], + srcs: ["interpreter/mterp/x86_64/*.S"], + tool_files: ["interpreter/mterp/gen_mterp.py", "interpreter/mterp/common/gen_setup.py"], + cmd: "$(location interpreter/mterp/gen_mterp.py) $(out) $(in)", +} diff --git a/runtime/interpreter/mterp/common/gen_setup.py b/runtime/interpreter/mterp/common/gen_setup.py index 48417e80b8..5790a94b35 100644 --- a/runtime/interpreter/mterp/common/gen_setup.py +++ b/runtime/interpreter/mterp/common/gen_setup.py @@ -46,7 +46,7 @@ def write_opcode(num, name, write_method, is_alt): write_line("") opnum, opcode = None, None -def generate(): +def generate(output_filename): out.seek(0) out.truncate() write_line("/* DO NOT EDIT: This file was generated by gen-mterp.py. */") @@ -70,6 +70,6 @@ def generate(): out.seek(0) # Squash consequtive empty lines. text = re.sub(r"(\n\n)(\n)+", r"\1", out.read()) - with open('out/mterp_' + arch + '.S', 'w') as output_file: + with open(output_filename, 'w') as output_file: output_file.write(text) diff --git a/runtime/interpreter/mterp/gen_mterp.py b/runtime/interpreter/mterp/gen_mterp.py index 98a98fcf6d..ad6e836177 100755 --- a/runtime/interpreter/mterp/gen_mterp.py +++ b/runtime/interpreter/mterp/gen_mterp.py @@ -14,14 +14,13 @@ # See the License for the specific language governing permissions and # limitations under the License. -import sys, re -from os import listdir +import sys, re, os from cStringIO import StringIO +SCRIPT_DIR = os.path.dirname(sys.argv[0]) # This file is included verbatim at the start of the in-memory python script. -SCRIPT_SETUP_CODE = "common/gen_setup.py" - -INTERP_DEFS_FILE = "../../../libdexfile/dex/dex_instruction_list.h" # need opcode list +SCRIPT_SETUP_CODE = SCRIPT_DIR + "/common/gen_setup.py" +INTERP_DEFS_FILE = SCRIPT_DIR + "/../../../libdexfile/dex/dex_instruction_list.h" NUM_PACKED_OPCODES = 256 # Extract an ordered list of instructions from the VM sources. We use the @@ -54,23 +53,20 @@ escape_re = re.compile(r''' (?(1)\}) # Expect } if and only if { was present. ''', re.VERBOSE) -def generate_script(arch, setup_code): +def generate_script(output_filename, input_filenames): # Create new python script and write the initial setup code. script = StringIO() # File-like in-memory buffer. script.write("# DO NOT EDIT: This file was generated by gen-mterp.py.\n") - script.write('arch = "' + arch + '"\n') - script.write(setup_code) - opcodes = getOpcodeList() + script.write(open(SCRIPT_SETUP_CODE, "r").read()) script.write("def opcodes(is_alt):\n") - for i in xrange(NUM_PACKED_OPCODES): - script.write(' write_opcode({0}, "{1}", {1}, is_alt)\n'.format(i, opcodes[i])) + for i, opcode in enumerate(getOpcodeList()): + script.write(' write_opcode({0}, "{1}", {1}, is_alt)\n'.format(i, opcode)) - # Find all template files and translate them into python code. - files = listdir(arch) - for file in sorted(files): - f = open(arch + "/" + file, "r") + # Read all template files and translate them into python code. + for input_filename in sorted(input_filenames): + lines = open(input_filename, "r").readlines() indent = "" - for line in f.readlines(): + for line in lines: line = line.rstrip() if line.startswith("%"): script.write(line.lstrip("%") + "\n") @@ -83,16 +79,20 @@ def generate_script(arch, setup_code): line = line.replace("$$", "$") script.write(indent + "write_line('''" + line + "''')\n") script.write("\n") - f.close() - script.write('generate()\n') + script.write("generate('''" + output_filename + "''')\n") script.seek(0) return script.read() -# Generate the script for each architecture and execute it. -for arch in ["arm", "arm64", "mips", "mips64", "x86", "x86_64"]: - with open(SCRIPT_SETUP_CODE, "r") as setup_code_file: - script = generate_script(arch, setup_code_file.read()) - filename = "out/mterp_" + arch + ".py" # Name to report in error messages. - # open(filename, "w").write(script) # Write the script to disk for debugging. - exec(compile(script, filename, mode='exec')) +if len(sys.argv) <= 3: + print("Usage: output_file input_file(s)") + sys.exit(1) + +# Generate the script and execute it. +output_filename = sys.argv[1] +input_filenames = sys.argv[2:] +script_filename = output_filename + ".py" +script = generate_script(output_filename, input_filenames) +with open(script_filename, "w") as script_file: + script_file.write(script) # Write to disk for debugging. +exec(compile(script, script_filename, mode='exec')) diff --git a/runtime/interpreter/mterp/out/mterp_arm.S b/runtime/interpreter/mterp/out/mterp_arm.S deleted file mode 100644 index 6e2b1acc3d..0000000000 --- a/runtime/interpreter/mterp/out/mterp_arm.S +++ /dev/null @@ -1,11424 +0,0 @@ -/* DO NOT EDIT: This file was generated by gen-mterp.py. */ -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - Art assembly interpreter notes: - - First validate assembly code by implementing ExecuteXXXImpl() style body (doesn't - handle invoke, allows higher-level code to create frame & shadow frame. - - Once that's working, support direct entry code & eliminate shadow frame (and - excess locals allocation. - - Some (hopefully) temporary ugliness. We'll treat rFP as pointing to the - base of the vreg array within the shadow frame. Access the other fields, - dex_pc_, method_ and number_of_vregs_ via negative offsets. For now, we'll continue - the shadow frame mechanism of double-storing object references - via rFP & - number_of_vregs_. - - */ - -/* -ARM EABI general notes: - -r0-r3 hold first 4 args to a method; they are not preserved across method calls -r4-r8 are available for general use -r9 is given special treatment in some situations, but not for us -r10 (sl) seems to be generally available -r11 (fp) is used by gcc (unless -fomit-frame-pointer is set) -r12 (ip) is scratch -- not preserved across method calls -r13 (sp) should be managed carefully in case a signal arrives -r14 (lr) must be preserved -r15 (pc) can be tinkered with directly - -r0 holds returns of <= 4 bytes -r0-r1 hold returns of 8 bytes, low word in r0 - -Callee must save/restore r4+ (except r12) if it modifies them. If VFP -is present, registers s16-s31 (a/k/a d8-d15, a/k/a q4-q7) must be preserved, -s0-s15 (d0-d7, q0-a3) do not need to be. - -Stack is "full descending". Only the arguments that don't fit in the first 4 -registers are placed on the stack. "sp" points at the first stacked argument -(i.e. the 5th arg). - -VFP: single-precision results in s0, double-precision results in d0. - -In the EABI, "sp" must be 64-bit aligned on entry to a function, and any -64-bit quantities (long long, double) must be 64-bit aligned. -*/ - -/* -Mterp and ARM notes: - -The following registers have fixed assignments: - - reg nick purpose - r4 rPC interpreted program counter, used for fetching instructions - r5 rFP interpreted frame pointer, used for accessing locals and args - r6 rSELF self (Thread) pointer - r7 rINST first 16-bit code unit of current instruction - r8 rIBASE interpreted instruction base pointer, used for computed goto - r10 rPROFILE branch profiling countdown - r11 rREFS base of object references in shadow frame (ideally, we'll get rid of this later). - -Macros are provided for common operations. Each macro MUST emit only -one instruction to make instruction-counting easier. They MUST NOT alter -unspecified registers or condition codes. -*/ - -/* - * This is a #include, not a %include, because we want the C pre-processor - * to expand the macros into assembler assignment statements. - */ -#include "asm_support.h" -#include "interpreter/cfi_asm_support.h" - -#define MTERP_PROFILE_BRANCHES 1 -#define MTERP_LOGGING 0 - -/* During bringup, we'll use the shadow frame model instead of rFP */ -/* single-purpose registers, given names for clarity */ -#define rPC r4 -#define CFI_DEX 4 // DWARF register number of the register holding dex-pc (xPC). -#define CFI_TMP 0 // DWARF register number of the first argument register (r0). -#define rFP r5 -#define rSELF r6 -#define rINST r7 -#define rIBASE r8 -#define rPROFILE r10 -#define rREFS r11 - -/* - * Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs. So, - * to access other shadow frame fields, we need to use a backwards offset. Define those here. - */ -#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) -#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) -#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) -#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) -#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) -#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) -#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) -#define OFF_FP_DEX_INSTRUCTIONS OFF_FP(SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET) -#define OFF_FP_SHADOWFRAME OFF_FP(0) - -/* - * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must - * be done *before* something throws. - * - * It's okay to do this more than once. - * - * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped - * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction - * offset into the code_items_[] array. For effiency, we will "export" the - * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC - * to convert to a dex pc when needed. - */ -.macro EXPORT_PC - str rPC, [rFP, #OFF_FP_DEX_PC_PTR] -.endm - -.macro EXPORT_DEX_PC tmp - ldr \tmp, [rFP, #OFF_FP_DEX_INSTRUCTIONS] - str rPC, [rFP, #OFF_FP_DEX_PC_PTR] - sub \tmp, rPC, \tmp - asr \tmp, #1 - str \tmp, [rFP, #OFF_FP_DEX_PC] -.endm - -/* - * Fetch the next instruction from rPC into rINST. Does not advance rPC. - */ -.macro FETCH_INST - ldrh rINST, [rPC] -.endm - -/* - * Fetch the next instruction from the specified offset. Advances rPC - * to point to the next instruction. "_count" is in 16-bit code units. - * - * Because of the limited size of immediate constants on ARM, this is only - * suitable for small forward movements (i.e. don't try to implement "goto" - * with this). - * - * This must come AFTER anything that can throw an exception, or the - * exception catch may miss. (This also implies that it must come after - * EXPORT_PC.) - */ -.macro FETCH_ADVANCE_INST count - ldrh rINST, [rPC, #((\count)*2)]! -.endm - -/* - * The operation performed here is similar to FETCH_ADVANCE_INST, except the - * src and dest registers are parameterized (not hard-wired to rPC and rINST). - */ -.macro PREFETCH_ADVANCE_INST dreg, sreg, count - ldrh \dreg, [\sreg, #((\count)*2)]! -.endm - -/* - * Similar to FETCH_ADVANCE_INST, but does not update rPC. Used to load - * rINST ahead of possible exception point. Be sure to manually advance rPC - * later. - */ -.macro PREFETCH_INST count - ldrh rINST, [rPC, #((\count)*2)] -.endm - -/* Advance rPC by some number of code units. */ -.macro ADVANCE count - add rPC, #((\count)*2) -.endm - -/* - * Fetch the next instruction from an offset specified by _reg. Updates - * rPC to point to the next instruction. "_reg" must specify the distance - * in bytes, *not* 16-bit code units, and may be a signed value. - * - * We want to write "ldrh rINST, [rPC, _reg, lsl #1]!", but some of the - * bits that hold the shift distance are used for the half/byte/sign flags. - * In some cases we can pre-double _reg for free, so we require a byte offset - * here. - */ -.macro FETCH_ADVANCE_INST_RB reg - ldrh rINST, [rPC, \reg]! -.endm - -/* - * Fetch a half-word code unit from an offset past the current PC. The - * "_count" value is in 16-bit code units. Does not advance rPC. - * - * The "_S" variant works the same but treats the value as signed. - */ -.macro FETCH reg, count - ldrh \reg, [rPC, #((\count)*2)] -.endm - -.macro FETCH_S reg, count - ldrsh \reg, [rPC, #((\count)*2)] -.endm - -/* - * Fetch one byte from an offset past the current PC. Pass in the same - * "_count" as you would for FETCH, and an additional 0/1 indicating which - * byte of the halfword you want (lo/hi). - */ -.macro FETCH_B reg, count, byte - ldrb \reg, [rPC, #((\count)*2+(\byte))] -.endm - -/* - * Put the instruction's opcode field into the specified register. - */ -.macro GET_INST_OPCODE reg - and \reg, rINST, #255 -.endm - -/* - * Put the prefetched instruction's opcode field into the specified register. - */ -.macro GET_PREFETCHED_OPCODE oreg, ireg - and \oreg, \ireg, #255 -.endm - -/* - * Begin executing the opcode in _reg. Because this only jumps within the - * interpreter, we don't have to worry about pre-ARMv5 THUMB interwork. - */ -.macro GOTO_OPCODE reg - add pc, rIBASE, \reg, lsl #7 -.endm -.macro GOTO_OPCODE_BASE base,reg - add pc, \base, \reg, lsl #7 -.endm - -/* - * Get/set the 32-bit value from a Dalvik register. - */ -.macro GET_VREG reg, vreg - ldr \reg, [rFP, \vreg, lsl #2] -.endm -.macro SET_VREG reg, vreg - str \reg, [rFP, \vreg, lsl #2] - mov \reg, #0 - str \reg, [rREFS, \vreg, lsl #2] -.endm -.macro SET_VREG_OBJECT reg, vreg, tmpreg - str \reg, [rFP, \vreg, lsl #2] - str \reg, [rREFS, \vreg, lsl #2] -.endm -.macro SET_VREG_SHADOW reg, vreg - str \reg, [rREFS, \vreg, lsl #2] -.endm - -/* - * Clear the corresponding shadow regs for a vreg pair - */ -.macro CLEAR_SHADOW_PAIR vreg, tmp1, tmp2 - mov \tmp1, #0 - add \tmp2, \vreg, #1 - SET_VREG_SHADOW \tmp1, \vreg - SET_VREG_SHADOW \tmp1, \tmp2 -.endm - -/* - * Convert a virtual register index into an address. - */ -.macro VREG_INDEX_TO_ADDR reg, vreg - add \reg, rFP, \vreg, lsl #2 /* WARNING/FIXME: handle shadow frame vreg zero if store */ -.endm - -/* - * Refresh handler table. - */ -.macro REFRESH_IBASE - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] -.endm - -/* - * cfi support macros. - */ -.macro ENTRY name - .arm - .type \name, #function - .hidden \name // Hide this as a global symbol, so we do not incur plt calls. - .global \name - /* Cache alignment for function entry */ - .balign 16 -\name: - .cfi_startproc - .fnstart -.endm - -.macro END name - .fnend - .cfi_endproc - .size \name, .-\name -.endm - -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -/* - * Interpreter entry point. - */ - - .text - .align 2 - -/* - * On entry: - * r0 Thread* self/ - * r1 insns_ - * r2 ShadowFrame - * r3 JValue* result_register - * - */ - -ENTRY ExecuteMterpImpl - stmfd sp!, {r3-r10,fp,lr} @ save 10 regs, (r3 just to align 64) - .cfi_adjust_cfa_offset 40 - .cfi_rel_offset r3, 0 - .cfi_rel_offset r4, 4 - .cfi_rel_offset r5, 8 - .cfi_rel_offset r6, 12 - .cfi_rel_offset r7, 16 - .cfi_rel_offset r8, 20 - .cfi_rel_offset r9, 24 - .cfi_rel_offset r10, 28 - .cfi_rel_offset fp, 32 - .cfi_rel_offset lr, 36 - - /* Remember the return register */ - str r3, [r2, #SHADOWFRAME_RESULT_REGISTER_OFFSET] - - /* Remember the dex instruction pointer */ - str r1, [r2, #SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET] - - /* set up "named" registers */ - mov rSELF, r0 - ldr r0, [r2, #SHADOWFRAME_NUMBER_OF_VREGS_OFFSET] - add rFP, r2, #SHADOWFRAME_VREGS_OFFSET @ point to vregs. - VREG_INDEX_TO_ADDR rREFS, r0 @ point to reference array in shadow frame - ldr r0, [r2, #SHADOWFRAME_DEX_PC_OFFSET] @ Get starting dex_pc. - add rPC, r1, r0, lsl #1 @ Create direct pointer to 1st dex opcode - CFI_DEFINE_DEX_PC_WITH_OFFSET(CFI_TMP, CFI_DEX, 0) - EXPORT_PC - - /* Starting ibase */ - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] - - /* Set up for backwards branches & osr profiling */ - ldr r0, [rFP, #OFF_FP_METHOD] - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rSELF - bl MterpSetUpHotnessCountdown - mov rPROFILE, r0 @ Starting hotness countdown to rPROFILE - - /* start executing the instruction at rPC */ - FETCH_INST @ load rINST from rPC - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - /* NOTE: no fallthrough */ - - .type artMterpAsmInstructionStart, #object - .hidden artMterpAsmInstructionStart - .global artMterpAsmInstructionStart -artMterpAsmInstructionStart = .L_op_nop - .text - -/* ------------------------------ */ - .balign 128 -.L_op_nop: /* 0x00 */ - FETCH_ADVANCE_INST 1 @ advance to next instr, load rINST - GET_INST_OPCODE ip @ ip<- opcode from rINST - GOTO_OPCODE ip @ execute it - -/* ------------------------------ */ - .balign 128 -.L_op_move: /* 0x01 */ - /* for move, move-object, long-to-int */ - /* op vA, vB */ - mov r1, rINST, lsr #12 @ r1<- B from 15:12 - ubfx r0, rINST, #8, #4 @ r0<- A from 11:8 - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - GET_VREG r2, r1 @ r2<- fp[B] - GET_INST_OPCODE ip @ ip<- opcode from rINST - .if 0 - SET_VREG_OBJECT r2, r0 @ fp[A]<- r2 - .else - SET_VREG r2, r0 @ fp[A]<- r2 - .endif - GOTO_OPCODE ip @ execute next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_from16: /* 0x02 */ - /* for: move/from16, move-object/from16 */ - /* op vAA, vBBBB */ - FETCH r1, 1 @ r1<- BBBB - mov r0, rINST, lsr #8 @ r0<- AA - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - GET_VREG r2, r1 @ r2<- fp[BBBB] - GET_INST_OPCODE ip @ extract opcode from rINST - .if 0 - SET_VREG_OBJECT r2, r0 @ fp[AA]<- r2 - .else - SET_VREG r2, r0 @ fp[AA]<- r2 - .endif - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_16: /* 0x03 */ - /* for: move/16, move-object/16 */ - /* op vAAAA, vBBBB */ - FETCH r1, 2 @ r1<- BBBB - FETCH r0, 1 @ r0<- AAAA - FETCH_ADVANCE_INST 3 @ advance rPC, load rINST - GET_VREG r2, r1 @ r2<- fp[BBBB] - GET_INST_OPCODE ip @ extract opcode from rINST - .if 0 - SET_VREG_OBJECT r2, r0 @ fp[AAAA]<- r2 - .else - SET_VREG r2, r0 @ fp[AAAA]<- r2 - .endif - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_wide: /* 0x04 */ - /* move-wide vA, vB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx rINST, rINST, #8, #4 @ rINST<- A - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] - VREG_INDEX_TO_ADDR r2, rINST @ r2<- &fp[A] - ldmia r3, {r0-r1} @ r0/r1<- fp[B] - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r2, {r0-r1} @ fp[A]<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_wide_from16: /* 0x05 */ - /* move-wide/from16 vAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - FETCH r3, 1 @ r3<- BBBB - mov rINST, rINST, lsr #8 @ rINST<- AA - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[BBBB] - VREG_INDEX_TO_ADDR r2, rINST @ r2<- &fp[AA] - ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r2, {r0-r1} @ fp[AA]<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_wide_16: /* 0x06 */ - /* move-wide/16 vAAAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - FETCH r3, 2 @ r3<- BBBB - FETCH r2, 1 @ r2<- AAAA - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[BBBB] - VREG_INDEX_TO_ADDR lr, r2 @ r2<- &fp[AAAA] - ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] - FETCH_ADVANCE_INST 3 @ advance rPC, load rINST - CLEAR_SHADOW_PAIR r2, r3, ip @ Zero out the shadow regs - stmia lr, {r0-r1} @ fp[AAAA]<- r0/r1 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_object: /* 0x07 */ - /* for move, move-object, long-to-int */ - /* op vA, vB */ - mov r1, rINST, lsr #12 @ r1<- B from 15:12 - ubfx r0, rINST, #8, #4 @ r0<- A from 11:8 - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - GET_VREG r2, r1 @ r2<- fp[B] - GET_INST_OPCODE ip @ ip<- opcode from rINST - .if 1 - SET_VREG_OBJECT r2, r0 @ fp[A]<- r2 - .else - SET_VREG r2, r0 @ fp[A]<- r2 - .endif - GOTO_OPCODE ip @ execute next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_object_from16: /* 0x08 */ - /* for: move/from16, move-object/from16 */ - /* op vAA, vBBBB */ - FETCH r1, 1 @ r1<- BBBB - mov r0, rINST, lsr #8 @ r0<- AA - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - GET_VREG r2, r1 @ r2<- fp[BBBB] - GET_INST_OPCODE ip @ extract opcode from rINST - .if 1 - SET_VREG_OBJECT r2, r0 @ fp[AA]<- r2 - .else - SET_VREG r2, r0 @ fp[AA]<- r2 - .endif - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_object_16: /* 0x09 */ - /* for: move/16, move-object/16 */ - /* op vAAAA, vBBBB */ - FETCH r1, 2 @ r1<- BBBB - FETCH r0, 1 @ r0<- AAAA - FETCH_ADVANCE_INST 3 @ advance rPC, load rINST - GET_VREG r2, r1 @ r2<- fp[BBBB] - GET_INST_OPCODE ip @ extract opcode from rINST - .if 1 - SET_VREG_OBJECT r2, r0 @ fp[AAAA]<- r2 - .else - SET_VREG r2, r0 @ fp[AAAA]<- r2 - .endif - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_result: /* 0x0a */ - /* for: move-result, move-result-object */ - /* op vAA */ - mov r2, rINST, lsr #8 @ r2<- AA - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - ldr r0, [rFP, #OFF_FP_RESULT_REGISTER] @ get pointer to result JType. - ldr r0, [r0] @ r0 <- result.i. - GET_INST_OPCODE ip @ extract opcode from rINST - .if 0 - SET_VREG_OBJECT r0, r2, r1 @ fp[AA]<- r0 - .else - SET_VREG r0, r2 @ fp[AA]<- r0 - .endif - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_result_wide: /* 0x0b */ - /* move-result-wide vAA */ - mov rINST, rINST, lsr #8 @ rINST<- AA - ldr r3, [rFP, #OFF_FP_RESULT_REGISTER] - VREG_INDEX_TO_ADDR r2, rINST @ r2<- &fp[AA] - ldmia r3, {r0-r1} @ r0/r1<- retval.j - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - stmia r2, {r0-r1} @ fp[AA]<- r0/r1 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_result_object: /* 0x0c */ - /* for: move-result, move-result-object */ - /* op vAA */ - mov r2, rINST, lsr #8 @ r2<- AA - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - ldr r0, [rFP, #OFF_FP_RESULT_REGISTER] @ get pointer to result JType. - ldr r0, [r0] @ r0 <- result.i. - GET_INST_OPCODE ip @ extract opcode from rINST - .if 1 - SET_VREG_OBJECT r0, r2, r1 @ fp[AA]<- r0 - .else - SET_VREG r0, r2 @ fp[AA]<- r0 - .endif - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_exception: /* 0x0d */ - /* move-exception vAA */ - mov r2, rINST, lsr #8 @ r2<- AA - ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] - mov r1, #0 @ r1<- 0 - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - SET_VREG_OBJECT r3, r2 @ fp[AA]<- exception obj - GET_INST_OPCODE ip @ extract opcode from rINST - str r1, [rSELF, #THREAD_EXCEPTION_OFFSET] @ clear exception - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_return_void: /* 0x0e */ - .extern MterpThreadFenceForConstructor - bl MterpThreadFenceForConstructor - ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] - mov r0, rSELF - ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - blne MterpSuspendCheck @ (self) - mov r0, #0 - mov r1, #0 - b MterpReturn - -/* ------------------------------ */ - .balign 128 -.L_op_return: /* 0x0f */ - /* - * Return a 32-bit value. - * - * for: return, return-object - */ - /* op vAA */ - .extern MterpThreadFenceForConstructor - bl MterpThreadFenceForConstructor - ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] - mov r0, rSELF - ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - blne MterpSuspendCheck @ (self) - mov r2, rINST, lsr #8 @ r2<- AA - GET_VREG r0, r2 @ r0<- vAA - mov r1, #0 - b MterpReturn - -/* ------------------------------ */ - .balign 128 -.L_op_return_wide: /* 0x10 */ - /* - * Return a 64-bit value. - */ - /* return-wide vAA */ - .extern MterpThreadFenceForConstructor - bl MterpThreadFenceForConstructor - ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] - mov r0, rSELF - ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - blne MterpSuspendCheck @ (self) - mov r2, rINST, lsr #8 @ r2<- AA - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[AA] - ldmia r2, {r0-r1} @ r0/r1 <- vAA/vAA+1 - b MterpReturn - -/* ------------------------------ */ - .balign 128 -.L_op_return_object: /* 0x11 */ - /* - * Return a 32-bit value. - * - * for: return, return-object - */ - /* op vAA */ - .extern MterpThreadFenceForConstructor - bl MterpThreadFenceForConstructor - ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] - mov r0, rSELF - ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - blne MterpSuspendCheck @ (self) - mov r2, rINST, lsr #8 @ r2<- AA - GET_VREG r0, r2 @ r0<- vAA - mov r1, #0 - b MterpReturn - -/* ------------------------------ */ - .balign 128 -.L_op_const_4: /* 0x12 */ - /* const/4 vA, #+B */ - sbfx r1, rINST, #12, #4 @ r1<- sssssssB (sign-extended) - ubfx r0, rINST, #8, #4 @ r0<- A - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - GET_INST_OPCODE ip @ ip<- opcode from rINST - SET_VREG r1, r0 @ fp[A]<- r1 - GOTO_OPCODE ip @ execute next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_16: /* 0x13 */ - /* const/16 vAA, #+BBBB */ - FETCH_S r0, 1 @ r0<- ssssBBBB (sign-extended) - mov r3, rINST, lsr #8 @ r3<- AA - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - SET_VREG r0, r3 @ vAA<- r0 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const: /* 0x14 */ - /* const vAA, #+BBBBbbbb */ - mov r3, rINST, lsr #8 @ r3<- AA - FETCH r0, 1 @ r0<- bbbb (low) - FETCH r1, 2 @ r1<- BBBB (high) - FETCH_ADVANCE_INST 3 @ advance rPC, load rINST - orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r3 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_high16: /* 0x15 */ - /* const/high16 vAA, #+BBBB0000 */ - FETCH r0, 1 @ r0<- 0000BBBB (zero-extended) - mov r3, rINST, lsr #8 @ r3<- AA - mov r0, r0, lsl #16 @ r0<- BBBB0000 - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - SET_VREG r0, r3 @ vAA<- r0 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_wide_16: /* 0x16 */ - /* const-wide/16 vAA, #+BBBB */ - FETCH_S r0, 1 @ r0<- ssssBBBB (sign-extended) - mov r3, rINST, lsr #8 @ r3<- AA - mov r1, r0, asr #31 @ r1<- ssssssss - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - CLEAR_SHADOW_PAIR r3, r2, lr @ Zero out the shadow regs - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[AA] - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r3, {r0-r1} @ vAA<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_wide_32: /* 0x17 */ - /* const-wide/32 vAA, #+BBBBbbbb */ - FETCH r0, 1 @ r0<- 0000bbbb (low) - mov r3, rINST, lsr #8 @ r3<- AA - FETCH_S r2, 2 @ r2<- ssssBBBB (high) - FETCH_ADVANCE_INST 3 @ advance rPC, load rINST - orr r0, r0, r2, lsl #16 @ r0<- BBBBbbbb - CLEAR_SHADOW_PAIR r3, r2, lr @ Zero out the shadow regs - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[AA] - mov r1, r0, asr #31 @ r1<- ssssssss - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r3, {r0-r1} @ vAA<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_wide: /* 0x18 */ - /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ - FETCH r0, 1 @ r0<- bbbb (low) - FETCH r1, 2 @ r1<- BBBB (low middle) - FETCH r2, 3 @ r2<- hhhh (high middle) - orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb (low word) - FETCH r3, 4 @ r3<- HHHH (high) - mov r9, rINST, lsr #8 @ r9<- AA - orr r1, r2, r3, lsl #16 @ r1<- HHHHhhhh (high word) - CLEAR_SHADOW_PAIR r9, r2, r3 @ Zero out the shadow regs - FETCH_ADVANCE_INST 5 @ advance rPC, load rINST - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vAA<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_wide_high16: /* 0x19 */ - /* const-wide/high16 vAA, #+BBBB000000000000 */ - FETCH r1, 1 @ r1<- 0000BBBB (zero-extended) - mov r3, rINST, lsr #8 @ r3<- AA - mov r0, #0 @ r0<- 00000000 - mov r1, r1, lsl #16 @ r1<- BBBB0000 - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - CLEAR_SHADOW_PAIR r3, r0, r2 @ Zero shadow regs - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[AA] - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r3, {r0-r1} @ vAA<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_string: /* 0x1a */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstString - EXPORT_PC - FETCH r0, 1 @ r0<- BBBB - mov r1, rINST, lsr #8 @ r1<- AA - add r2, rFP, #OFF_FP_SHADOWFRAME - mov r3, rSELF - bl MterpConstString @ (index, tgt_reg, shadow_frame, self) - PREFETCH_INST 2 @ load rINST - cmp r0, #0 @ fail? - bne MterpPossibleException @ let reference interpreter deal with it. - ADVANCE 2 @ advance rPC - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_string_jumbo: /* 0x1b */ - /* const/string vAA, String@BBBBBBBB */ - EXPORT_PC - FETCH r0, 1 @ r0<- bbbb (low) - FETCH r2, 2 @ r2<- BBBB (high) - mov r1, rINST, lsr #8 @ r1<- AA - orr r0, r0, r2, lsl #16 @ r1<- BBBBbbbb - add r2, rFP, #OFF_FP_SHADOWFRAME - mov r3, rSELF - bl MterpConstString @ (index, tgt_reg, shadow_frame, self) - PREFETCH_INST 3 @ advance rPC - cmp r0, #0 @ fail? - bne MterpPossibleException @ let reference interpreter deal with it. - ADVANCE 3 @ advance rPC - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_class: /* 0x1c */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstClass - EXPORT_PC - FETCH r0, 1 @ r0<- BBBB - mov r1, rINST, lsr #8 @ r1<- AA - add r2, rFP, #OFF_FP_SHADOWFRAME - mov r3, rSELF - bl MterpConstClass @ (index, tgt_reg, shadow_frame, self) - PREFETCH_INST 2 @ load rINST - cmp r0, #0 @ fail? - bne MterpPossibleException @ let reference interpreter deal with it. - ADVANCE 2 @ advance rPC - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_monitor_enter: /* 0x1d */ - /* - * Synchronize on an object. - */ - /* monitor-enter vAA */ - EXPORT_PC - mov r2, rINST, lsr #8 @ r2<- AA - GET_VREG r0, r2 @ r0<- vAA (object) - mov r1, rSELF @ r1<- self - bl artLockObjectFromCode - cmp r0, #0 - bne MterpException - FETCH_ADVANCE_INST 1 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_monitor_exit: /* 0x1e */ - /* - * Unlock an object. - * - * Exceptions that occur when unlocking a monitor need to appear as - * if they happened at the following instruction. See the Dalvik - * instruction spec. - */ - /* monitor-exit vAA */ - EXPORT_PC - mov r2, rINST, lsr #8 @ r2<- AA - GET_VREG r0, r2 @ r0<- vAA (object) - mov r1, rSELF @ r0<- self - bl artUnlockObjectFromCode @ r0<- success for unlock(self, obj) - cmp r0, #0 @ failed? - bne MterpException - FETCH_ADVANCE_INST 1 @ before throw: advance rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_check_cast: /* 0x1f */ - /* - * Check to see if a cast from one class to another is allowed. - */ - /* check-cast vAA, class@BBBB */ - EXPORT_PC - FETCH r0, 1 @ r0<- BBBB - mov r1, rINST, lsr #8 @ r1<- AA - VREG_INDEX_TO_ADDR r1, r1 @ r1<- &object - ldr r2, [rFP, #OFF_FP_METHOD] @ r2<- method - mov r3, rSELF @ r3<- self - bl MterpCheckCast @ (index, &obj, method, self) - PREFETCH_INST 2 - cmp r0, #0 - bne MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_instance_of: /* 0x20 */ - /* - * Check to see if an object reference is an instance of a class. - * - * Most common situation is a non-null object, being compared against - * an already-resolved class. - */ - /* instance-of vA, vB, class@CCCC */ - EXPORT_PC - FETCH r0, 1 @ r0<- CCCC - mov r1, rINST, lsr #12 @ r1<- B - VREG_INDEX_TO_ADDR r1, r1 @ r1<- &object - ldr r2, [rFP, #OFF_FP_METHOD] @ r2<- method - mov r3, rSELF @ r3<- self - bl MterpInstanceOf @ (index, &obj, method, self) - ldr r1, [rSELF, #THREAD_EXCEPTION_OFFSET] - ubfx r9, rINST, #8, #4 @ r9<- A - PREFETCH_INST 2 - cmp r1, #0 @ exception pending? - bne MterpException - ADVANCE 2 @ advance rPC - SET_VREG r0, r9 @ vA<- r0 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_array_length: /* 0x21 */ - /* - * Return the length of an array. - */ - mov r1, rINST, lsr #12 @ r1<- B - ubfx r2, rINST, #8, #4 @ r2<- A - GET_VREG r0, r1 @ r0<- vB (object ref) - cmp r0, #0 @ is object null? - beq common_errNullObject @ yup, fail - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- array length - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r3, r2 @ vB<- length - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_new_instance: /* 0x22 */ - /* - * Create a new instance of a class. - */ - /* new-instance vAA, class@BBBB */ - EXPORT_PC - add r0, rFP, #OFF_FP_SHADOWFRAME - mov r1, rSELF - mov r2, rINST - bl MterpNewInstance @ (shadow_frame, self, inst_data) - cmp r0, #0 - beq MterpPossibleException - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_new_array: /* 0x23 */ - /* - * Allocate an array of objects, specified with the array class - * and a count. - * - * The verifier guarantees that this is an array class, so we don't - * check for it here. - */ - /* new-array vA, vB, class@CCCC */ - EXPORT_PC - add r0, rFP, #OFF_FP_SHADOWFRAME - mov r1, rPC - mov r2, rINST - mov r3, rSELF - bl MterpNewArray - cmp r0, #0 - beq MterpPossibleException - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_filled_new_array: /* 0x24 */ - /* - * Create a new array with elements filled from registers. - * - * for: filled-new-array, filled-new-array/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ - .extern MterpFilledNewArray - EXPORT_PC - add r0, rFP, #OFF_FP_SHADOWFRAME - mov r1, rPC - mov r2, rSELF - bl MterpFilledNewArray - cmp r0, #0 - beq MterpPossibleException - FETCH_ADVANCE_INST 3 @ advance rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_filled_new_array_range: /* 0x25 */ - /* - * Create a new array with elements filled from registers. - * - * for: filled-new-array, filled-new-array/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ - .extern MterpFilledNewArrayRange - EXPORT_PC - add r0, rFP, #OFF_FP_SHADOWFRAME - mov r1, rPC - mov r2, rSELF - bl MterpFilledNewArrayRange - cmp r0, #0 - beq MterpPossibleException - FETCH_ADVANCE_INST 3 @ advance rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_fill_array_data: /* 0x26 */ - /* fill-array-data vAA, +BBBBBBBB */ - EXPORT_PC - FETCH r0, 1 @ r0<- bbbb (lo) - FETCH r1, 2 @ r1<- BBBB (hi) - mov r3, rINST, lsr #8 @ r3<- AA - orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb - GET_VREG r0, r3 @ r0<- vAA (array object) - add r1, rPC, r1, lsl #1 @ r1<- PC + BBBBbbbb*2 (array data off.) - bl MterpFillArrayData @ (obj, payload) - cmp r0, #0 @ 0 means an exception is thrown - beq MterpPossibleException @ exception? - FETCH_ADVANCE_INST 3 @ advance rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_throw: /* 0x27 */ - /* - * Throw an exception object in the current thread. - */ - /* throw vAA */ - EXPORT_PC - mov r2, rINST, lsr #8 @ r2<- AA - GET_VREG r1, r2 @ r1<- vAA (exception object) - cmp r1, #0 @ null object? - beq common_errNullObject @ yes, throw an NPE instead - str r1, [rSELF, #THREAD_EXCEPTION_OFFSET] @ thread->exception<- obj - b MterpException - -/* ------------------------------ */ - .balign 128 -.L_op_goto: /* 0x28 */ - /* - * Unconditional branch, 8-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto +AA */ - sbfx rINST, rINST, #8, #8 @ rINST<- ssssssAA (sign-extended) - b MterpCommonTakenBranchNoFlags - -/* ------------------------------ */ - .balign 128 -.L_op_goto_16: /* 0x29 */ - /* - * Unconditional branch, 16-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto/16 +AAAA */ - FETCH_S rINST, 1 @ rINST<- ssssAAAA (sign-extended) - b MterpCommonTakenBranchNoFlags - -/* ------------------------------ */ - .balign 128 -.L_op_goto_32: /* 0x2a */ - /* - * Unconditional branch, 32-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - * - * Unlike most opcodes, this one is allowed to branch to itself, so - * our "backward branch" test must be "<=0" instead of "<0". Because - * we need the V bit set, we'll use an adds to convert from Dalvik - * offset to byte offset. - */ - /* goto/32 +AAAAAAAA */ - FETCH r0, 1 @ r0<- aaaa (lo) - FETCH r3, 2 @ r1<- AAAA (hi) - orrs rINST, r0, r3, lsl #16 @ rINST<- AAAAaaaa - b MterpCommonTakenBranch - -/* ------------------------------ */ - .balign 128 -.L_op_packed_switch: /* 0x2b */ - /* - * Handle a packed-switch or sparse-switch instruction. In both cases - * we decode it and hand it off to a helper function. - * - * We don't really expect backward branches in a switch statement, but - * they're perfectly legal, so we check for them here. - * - * for: packed-switch, sparse-switch - */ - /* op vAA, +BBBB */ - FETCH r0, 1 @ r0<- bbbb (lo) - FETCH r1, 2 @ r1<- BBBB (hi) - mov r3, rINST, lsr #8 @ r3<- AA - orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb - GET_VREG r1, r3 @ r1<- vAA - add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 - bl MterpDoPackedSwitch @ r0<- code-unit branch offset - movs rINST, r0 - b MterpCommonTakenBranch - -/* ------------------------------ */ - .balign 128 -.L_op_sparse_switch: /* 0x2c */ - /* - * Handle a packed-switch or sparse-switch instruction. In both cases - * we decode it and hand it off to a helper function. - * - * We don't really expect backward branches in a switch statement, but - * they're perfectly legal, so we check for them here. - * - * for: packed-switch, sparse-switch - */ - /* op vAA, +BBBB */ - FETCH r0, 1 @ r0<- bbbb (lo) - FETCH r1, 2 @ r1<- BBBB (hi) - mov r3, rINST, lsr #8 @ r3<- AA - orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb - GET_VREG r1, r3 @ r1<- vAA - add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 - bl MterpDoSparseSwitch @ r0<- code-unit branch offset - movs rINST, r0 - b MterpCommonTakenBranch - -/* ------------------------------ */ - .balign 128 -.L_op_cmpl_float: /* 0x2d */ - /* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * int compare(x, y) { - * if (x == y) { - * return 0; - * } else if (x > y) { - * return 1; - * } else if (x < y) { - * return -1; - * } else { - * return -1; - * } - * } - */ - /* op vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC - flds s0, [r2] @ s0<- vBB - flds s1, [r3] @ s1<- vCC - vcmpe.f32 s0, s1 @ compare (vBB, vCC) - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - mvn r0, #0 @ r0<- -1 (default) - GET_INST_OPCODE ip @ extract opcode from rINST - fmstat @ export status flags - movgt r0, #1 @ (greater than) r1<- 1 - moveq r0, #0 @ (equal) r1<- 0 - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_cmpg_float: /* 0x2e */ - /* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * int compare(x, y) { - * if (x == y) { - * return 0; - * } else if (x < y) { - * return -1; - * } else if (x > y) { - * return 1; - * } else { - * return 1; - * } - * } - */ - /* op vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC - flds s0, [r2] @ s0<- vBB - flds s1, [r3] @ s1<- vCC - vcmpe.f32 s0, s1 @ compare (vBB, vCC) - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - mov r0, #1 @ r0<- 1 (default) - GET_INST_OPCODE ip @ extract opcode from rINST - fmstat @ export status flags - mvnmi r0, #0 @ (less than) r1<- -1 - moveq r0, #0 @ (equal) r1<- 0 - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_cmpl_double: /* 0x2f */ - /* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * int compare(x, y) { - * if (x == y) { - * return 0; - * } else if (x > y) { - * return 1; - * } else if (x < y) { - * return -1; - * } else { - * return -1; - * } - * } - */ - /* op vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC - fldd d0, [r2] @ d0<- vBB - fldd d1, [r3] @ d1<- vCC - vcmpe.f64 d0, d1 @ compare (vBB, vCC) - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - mvn r0, #0 @ r0<- -1 (default) - GET_INST_OPCODE ip @ extract opcode from rINST - fmstat @ export status flags - movgt r0, #1 @ (greater than) r1<- 1 - moveq r0, #0 @ (equal) r1<- 0 - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_cmpg_double: /* 0x30 */ - /* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * int compare(x, y) { - * if (x == y) { - * return 0; - * } else if (x < y) { - * return -1; - * } else if (x > y) { - * return 1; - * } else { - * return 1; - * } - * } - */ - /* op vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC - fldd d0, [r2] @ d0<- vBB - fldd d1, [r3] @ d1<- vCC - vcmpe.f64 d0, d1 @ compare (vBB, vCC) - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - mov r0, #1 @ r0<- 1 (default) - GET_INST_OPCODE ip @ extract opcode from rINST - fmstat @ export status flags - mvnmi r0, #0 @ (less than) r1<- -1 - moveq r0, #0 @ (equal) r1<- 0 - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_cmp_long: /* 0x31 */ - /* - * Compare two 64-bit values. Puts 0, 1, or -1 into the destination - * register based on the results of the comparison. - */ - /* cmp-long vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] - ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 - ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 - cmp r0, r2 - sbcs ip, r1, r3 @ Sets correct CCs for checking LT (but not EQ/NE) - mov ip, #0 - mvnlt ip, #0 @ -1 - cmpeq r0, r2 @ For correct EQ/NE, we may need to repeat the first CMP - orrne ip, #1 - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - SET_VREG ip, r9 @ vAA<- ip - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_eq: /* 0x32 */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - mov r1, rINST, lsr #12 @ r1<- B - ubfx r0, rINST, #8, #4 @ r0<- A - GET_VREG r3, r1 @ r3<- vB - GET_VREG r0, r0 @ r0<- vA - FETCH_S rINST, 1 @ rINST<- branch offset, in code units - cmp r0, r3 @ compare (vA, vB) - beq MterpCommonTakenBranchNoFlags - cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? - beq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_ne: /* 0x33 */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - mov r1, rINST, lsr #12 @ r1<- B - ubfx r0, rINST, #8, #4 @ r0<- A - GET_VREG r3, r1 @ r3<- vB - GET_VREG r0, r0 @ r0<- vA - FETCH_S rINST, 1 @ rINST<- branch offset, in code units - cmp r0, r3 @ compare (vA, vB) - bne MterpCommonTakenBranchNoFlags - cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? - beq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_lt: /* 0x34 */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - mov r1, rINST, lsr #12 @ r1<- B - ubfx r0, rINST, #8, #4 @ r0<- A - GET_VREG r3, r1 @ r3<- vB - GET_VREG r0, r0 @ r0<- vA - FETCH_S rINST, 1 @ rINST<- branch offset, in code units - cmp r0, r3 @ compare (vA, vB) - blt MterpCommonTakenBranchNoFlags - cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? - beq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_ge: /* 0x35 */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - mov r1, rINST, lsr #12 @ r1<- B - ubfx r0, rINST, #8, #4 @ r0<- A - GET_VREG r3, r1 @ r3<- vB - GET_VREG r0, r0 @ r0<- vA - FETCH_S rINST, 1 @ rINST<- branch offset, in code units - cmp r0, r3 @ compare (vA, vB) - bge MterpCommonTakenBranchNoFlags - cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? - beq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_gt: /* 0x36 */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - mov r1, rINST, lsr #12 @ r1<- B - ubfx r0, rINST, #8, #4 @ r0<- A - GET_VREG r3, r1 @ r3<- vB - GET_VREG r0, r0 @ r0<- vA - FETCH_S rINST, 1 @ rINST<- branch offset, in code units - cmp r0, r3 @ compare (vA, vB) - bgt MterpCommonTakenBranchNoFlags - cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? - beq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_le: /* 0x37 */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - mov r1, rINST, lsr #12 @ r1<- B - ubfx r0, rINST, #8, #4 @ r0<- A - GET_VREG r3, r1 @ r3<- vB - GET_VREG r0, r0 @ r0<- vA - FETCH_S rINST, 1 @ rINST<- branch offset, in code units - cmp r0, r3 @ compare (vA, vB) - ble MterpCommonTakenBranchNoFlags - cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? - beq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_eqz: /* 0x38 */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - mov r0, rINST, lsr #8 @ r0<- AA - GET_VREG r0, r0 @ r0<- vAA - FETCH_S rINST, 1 @ rINST<- branch offset, in code units - cmp r0, #0 @ compare (vA, 0) - beq MterpCommonTakenBranchNoFlags - cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? - beq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_nez: /* 0x39 */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - mov r0, rINST, lsr #8 @ r0<- AA - GET_VREG r0, r0 @ r0<- vAA - FETCH_S rINST, 1 @ rINST<- branch offset, in code units - cmp r0, #0 @ compare (vA, 0) - bne MterpCommonTakenBranchNoFlags - cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? - beq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_ltz: /* 0x3a */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - mov r0, rINST, lsr #8 @ r0<- AA - GET_VREG r0, r0 @ r0<- vAA - FETCH_S rINST, 1 @ rINST<- branch offset, in code units - cmp r0, #0 @ compare (vA, 0) - blt MterpCommonTakenBranchNoFlags - cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? - beq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_gez: /* 0x3b */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - mov r0, rINST, lsr #8 @ r0<- AA - GET_VREG r0, r0 @ r0<- vAA - FETCH_S rINST, 1 @ rINST<- branch offset, in code units - cmp r0, #0 @ compare (vA, 0) - bge MterpCommonTakenBranchNoFlags - cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? - beq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_gtz: /* 0x3c */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - mov r0, rINST, lsr #8 @ r0<- AA - GET_VREG r0, r0 @ r0<- vAA - FETCH_S rINST, 1 @ rINST<- branch offset, in code units - cmp r0, #0 @ compare (vA, 0) - bgt MterpCommonTakenBranchNoFlags - cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? - beq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_lez: /* 0x3d */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - mov r0, rINST, lsr #8 @ r0<- AA - GET_VREG r0, r0 @ r0<- vAA - FETCH_S rINST, 1 @ rINST<- branch offset, in code units - cmp r0, #0 @ compare (vA, 0) - ble MterpCommonTakenBranchNoFlags - cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? - beq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_unused_3e: /* 0x3e */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_3f: /* 0x3f */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_40: /* 0x40 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_41: /* 0x41 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_42: /* 0x42 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_43: /* 0x43 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_aget: /* 0x44 */ - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B r2, 1, 0 @ r2<- BB - mov r9, rINST, lsr #8 @ r9<- AA - FETCH_B r3, 1, 1 @ r3<- CC - GET_VREG r0, r2 @ r0<- vBB (array object) - GET_VREG r1, r3 @ r1<- vCC (requested index) - cmp r0, #0 @ null array object? - beq common_errNullObject @ yes, bail - ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length - add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width - cmp r1, r3 @ compare unsigned index, length - bcs common_errArrayIndex @ index >= length, bail - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - ldr r2, [r0, #MIRROR_INT_ARRAY_DATA_OFFSET] @ r2<- vBB[vCC] - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r2, r9 @ vAA<- r2 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aget_wide: /* 0x45 */ - /* - * Array get, 64 bits. vAA <- vBB[vCC]. - * - * Arrays of long/double are 64-bit aligned, so it's okay to use LDRD. - */ - /* aget-wide vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - GET_VREG r0, r2 @ r0<- vBB (array object) - GET_VREG r1, r3 @ r1<- vCC (requested index) - cmp r0, #0 @ null array object? - beq common_errNullObject @ yes, bail - ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length - add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width - cmp r1, r3 @ compare unsigned index, length - bcs common_errArrayIndex @ index >= length, bail - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs - ldrd r2, [r0, #MIRROR_WIDE_ARRAY_DATA_OFFSET] @ r2/r3<- vBB[vCC] - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r2-r3} @ vAA/vAA+1<- r2/r3 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aget_object: /* 0x46 */ - /* - * Array object get. vAA <- vBB[vCC]. - * - * for: aget-object - */ - /* op vAA, vBB, vCC */ - FETCH_B r2, 1, 0 @ r2<- BB - mov r9, rINST, lsr #8 @ r9<- AA - FETCH_B r3, 1, 1 @ r3<- CC - EXPORT_PC - GET_VREG r0, r2 @ r0<- vBB (array object) - GET_VREG r1, r3 @ r1<- vCC (requested index) - bl artAGetObjectFromMterp @ (array, index) - ldr r1, [rSELF, #THREAD_EXCEPTION_OFFSET] - PREFETCH_INST 2 - cmp r1, #0 - bne MterpException - SET_VREG_OBJECT r0, r9 - ADVANCE 2 - GET_INST_OPCODE ip - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aget_boolean: /* 0x47 */ - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B r2, 1, 0 @ r2<- BB - mov r9, rINST, lsr #8 @ r9<- AA - FETCH_B r3, 1, 1 @ r3<- CC - GET_VREG r0, r2 @ r0<- vBB (array object) - GET_VREG r1, r3 @ r1<- vCC (requested index) - cmp r0, #0 @ null array object? - beq common_errNullObject @ yes, bail - ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length - add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width - cmp r1, r3 @ compare unsigned index, length - bcs common_errArrayIndex @ index >= length, bail - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - ldrb r2, [r0, #MIRROR_BOOLEAN_ARRAY_DATA_OFFSET] @ r2<- vBB[vCC] - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r2, r9 @ vAA<- r2 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aget_byte: /* 0x48 */ - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B r2, 1, 0 @ r2<- BB - mov r9, rINST, lsr #8 @ r9<- AA - FETCH_B r3, 1, 1 @ r3<- CC - GET_VREG r0, r2 @ r0<- vBB (array object) - GET_VREG r1, r3 @ r1<- vCC (requested index) - cmp r0, #0 @ null array object? - beq common_errNullObject @ yes, bail - ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length - add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width - cmp r1, r3 @ compare unsigned index, length - bcs common_errArrayIndex @ index >= length, bail - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - ldrsb r2, [r0, #MIRROR_BYTE_ARRAY_DATA_OFFSET] @ r2<- vBB[vCC] - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r2, r9 @ vAA<- r2 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aget_char: /* 0x49 */ - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B r2, 1, 0 @ r2<- BB - mov r9, rINST, lsr #8 @ r9<- AA - FETCH_B r3, 1, 1 @ r3<- CC - GET_VREG r0, r2 @ r0<- vBB (array object) - GET_VREG r1, r3 @ r1<- vCC (requested index) - cmp r0, #0 @ null array object? - beq common_errNullObject @ yes, bail - ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length - add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width - cmp r1, r3 @ compare unsigned index, length - bcs common_errArrayIndex @ index >= length, bail - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - ldrh r2, [r0, #MIRROR_CHAR_ARRAY_DATA_OFFSET] @ r2<- vBB[vCC] - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r2, r9 @ vAA<- r2 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aget_short: /* 0x4a */ - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B r2, 1, 0 @ r2<- BB - mov r9, rINST, lsr #8 @ r9<- AA - FETCH_B r3, 1, 1 @ r3<- CC - GET_VREG r0, r2 @ r0<- vBB (array object) - GET_VREG r1, r3 @ r1<- vCC (requested index) - cmp r0, #0 @ null array object? - beq common_errNullObject @ yes, bail - ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length - add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width - cmp r1, r3 @ compare unsigned index, length - bcs common_errArrayIndex @ index >= length, bail - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - ldrsh r2, [r0, #MIRROR_SHORT_ARRAY_DATA_OFFSET] @ r2<- vBB[vCC] - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r2, r9 @ vAA<- r2 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aput: /* 0x4b */ - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B r2, 1, 0 @ r2<- BB - mov r9, rINST, lsr #8 @ r9<- AA - FETCH_B r3, 1, 1 @ r3<- CC - GET_VREG r0, r2 @ r0<- vBB (array object) - GET_VREG r1, r3 @ r1<- vCC (requested index) - cmp r0, #0 @ null array object? - beq common_errNullObject @ yes, bail - ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length - add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width - cmp r1, r3 @ compare unsigned index, length - bcs common_errArrayIndex @ index >= length, bail - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - GET_VREG r2, r9 @ r2<- vAA - GET_INST_OPCODE ip @ extract opcode from rINST - str r2, [r0, #MIRROR_INT_ARRAY_DATA_OFFSET] @ vBB[vCC]<- r2 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aput_wide: /* 0x4c */ - /* - * Array put, 64 bits. vBB[vCC] <- vAA. - * - * Arrays of long/double are 64-bit aligned, so it's okay to use STRD. - */ - /* aput-wide vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - GET_VREG r0, r2 @ r0<- vBB (array object) - GET_VREG r1, r3 @ r1<- vCC (requested index) - cmp r0, #0 @ null array object? - beq common_errNullObject @ yes, bail - ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length - add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width - cmp r1, r3 @ compare unsigned index, length - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] - bcs common_errArrayIndex @ index >= length, bail - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - ldmia r9, {r2-r3} @ r2/r3<- vAA/vAA+1 - GET_INST_OPCODE ip @ extract opcode from rINST - strd r2, [r0, #MIRROR_WIDE_ARRAY_DATA_OFFSET] @ r2/r3<- vBB[vCC] - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aput_object: /* 0x4d */ - /* - * Store an object into an array. vBB[vCC] <- vAA. - */ - /* op vAA, vBB, vCC */ - EXPORT_PC - add r0, rFP, #OFF_FP_SHADOWFRAME - mov r1, rPC - mov r2, rINST - bl MterpAputObject - cmp r0, #0 - beq MterpPossibleException - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aput_boolean: /* 0x4e */ - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B r2, 1, 0 @ r2<- BB - mov r9, rINST, lsr #8 @ r9<- AA - FETCH_B r3, 1, 1 @ r3<- CC - GET_VREG r0, r2 @ r0<- vBB (array object) - GET_VREG r1, r3 @ r1<- vCC (requested index) - cmp r0, #0 @ null array object? - beq common_errNullObject @ yes, bail - ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length - add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width - cmp r1, r3 @ compare unsigned index, length - bcs common_errArrayIndex @ index >= length, bail - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - GET_VREG r2, r9 @ r2<- vAA - GET_INST_OPCODE ip @ extract opcode from rINST - strb r2, [r0, #MIRROR_BOOLEAN_ARRAY_DATA_OFFSET] @ vBB[vCC]<- r2 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aput_byte: /* 0x4f */ - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B r2, 1, 0 @ r2<- BB - mov r9, rINST, lsr #8 @ r9<- AA - FETCH_B r3, 1, 1 @ r3<- CC - GET_VREG r0, r2 @ r0<- vBB (array object) - GET_VREG r1, r3 @ r1<- vCC (requested index) - cmp r0, #0 @ null array object? - beq common_errNullObject @ yes, bail - ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length - add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width - cmp r1, r3 @ compare unsigned index, length - bcs common_errArrayIndex @ index >= length, bail - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - GET_VREG r2, r9 @ r2<- vAA - GET_INST_OPCODE ip @ extract opcode from rINST - strb r2, [r0, #MIRROR_BYTE_ARRAY_DATA_OFFSET] @ vBB[vCC]<- r2 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aput_char: /* 0x50 */ - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B r2, 1, 0 @ r2<- BB - mov r9, rINST, lsr #8 @ r9<- AA - FETCH_B r3, 1, 1 @ r3<- CC - GET_VREG r0, r2 @ r0<- vBB (array object) - GET_VREG r1, r3 @ r1<- vCC (requested index) - cmp r0, #0 @ null array object? - beq common_errNullObject @ yes, bail - ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length - add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width - cmp r1, r3 @ compare unsigned index, length - bcs common_errArrayIndex @ index >= length, bail - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - GET_VREG r2, r9 @ r2<- vAA - GET_INST_OPCODE ip @ extract opcode from rINST - strh r2, [r0, #MIRROR_CHAR_ARRAY_DATA_OFFSET] @ vBB[vCC]<- r2 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aput_short: /* 0x51 */ - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B r2, 1, 0 @ r2<- BB - mov r9, rINST, lsr #8 @ r9<- AA - FETCH_B r3, 1, 1 @ r3<- CC - GET_VREG r0, r2 @ r0<- vBB (array object) - GET_VREG r1, r3 @ r1<- vCC (requested index) - cmp r0, #0 @ null array object? - beq common_errNullObject @ yes, bail - ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length - add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width - cmp r1, r3 @ compare unsigned index, length - bcs common_errArrayIndex @ index >= length, bail - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - GET_VREG r2, r9 @ r2<- vAA - GET_INST_OPCODE ip @ extract opcode from rINST - strh r2, [r0, #MIRROR_SHORT_ARRAY_DATA_OFFSET] @ vBB[vCC]<- r2 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iget: /* 0x52 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetU32 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpIGetU32 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iget_wide: /* 0x53 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetU64 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpIGetU64 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iget_object: /* 0x54 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetObj - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpIGetObj - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iget_boolean: /* 0x55 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetU8 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpIGetU8 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iget_byte: /* 0x56 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetI8 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpIGetI8 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iget_char: /* 0x57 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetU16 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpIGetU16 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iget_short: /* 0x58 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetI16 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpIGetI16 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput: /* 0x59 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutU32 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpIPutU32 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_wide: /* 0x5a */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutU64 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpIPutU64 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_object: /* 0x5b */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutObj - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpIPutObj - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_boolean: /* 0x5c */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutU8 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpIPutU8 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_byte: /* 0x5d */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutI8 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpIPutI8 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_char: /* 0x5e */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutU16 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpIPutU16 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_short: /* 0x5f */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutI16 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpIPutI16 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_sget: /* 0x60 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetU32 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpSGetU32 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_sget_wide: /* 0x61 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetU64 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpSGetU64 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_sget_object: /* 0x62 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetObj - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpSGetObj - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_sget_boolean: /* 0x63 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetU8 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpSGetU8 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_sget_byte: /* 0x64 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetI8 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpSGetI8 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_sget_char: /* 0x65 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetU16 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpSGetU16 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_sget_short: /* 0x66 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetI16 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpSGetI16 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_sput: /* 0x67 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutU32 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpSPutU32 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_sput_wide: /* 0x68 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutU64 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpSPutU64 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_sput_object: /* 0x69 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutObj - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpSPutObj - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_sput_boolean: /* 0x6a */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutU8 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpSPutU8 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_sput_byte: /* 0x6b */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutI8 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpSPutI8 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_sput_char: /* 0x6c */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutU16 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpSPutU16 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_sput_short: /* 0x6d */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutI16 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpSPutI16 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual: /* 0x6e */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtual - EXPORT_PC - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - mov r3, rINST - bl MterpInvokeVirtual - cmp r0, #0 - beq MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cmp r0, #0 - bne MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - - /* - * Handle a virtual method call. - * - * for: invoke-virtual, invoke-virtual/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_super: /* 0x6f */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeSuper - EXPORT_PC - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - mov r3, rINST - bl MterpInvokeSuper - cmp r0, #0 - beq MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cmp r0, #0 - bne MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - - /* - * Handle a "super" method call. - * - * for: invoke-super, invoke-super/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_direct: /* 0x70 */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeDirect - EXPORT_PC - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - mov r3, rINST - bl MterpInvokeDirect - cmp r0, #0 - beq MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cmp r0, #0 - bne MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_static: /* 0x71 */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeStatic - EXPORT_PC - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - mov r3, rINST - bl MterpInvokeStatic - cmp r0, #0 - beq MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cmp r0, #0 - bne MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_interface: /* 0x72 */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeInterface - EXPORT_PC - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - mov r3, rINST - bl MterpInvokeInterface - cmp r0, #0 - beq MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cmp r0, #0 - bne MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - - /* - * Handle an interface method call. - * - * for: invoke-interface, invoke-interface/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - -/* ------------------------------ */ - .balign 128 -.L_op_return_void_no_barrier: /* 0x73 */ - ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] - mov r0, rSELF - ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - blne MterpSuspendCheck @ (self) - mov r0, #0 - mov r1, #0 - b MterpReturn - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual_range: /* 0x74 */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtualRange - EXPORT_PC - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - mov r3, rINST - bl MterpInvokeVirtualRange - cmp r0, #0 - beq MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cmp r0, #0 - bne MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_super_range: /* 0x75 */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeSuperRange - EXPORT_PC - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - mov r3, rINST - bl MterpInvokeSuperRange - cmp r0, #0 - beq MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cmp r0, #0 - bne MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_direct_range: /* 0x76 */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeDirectRange - EXPORT_PC - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - mov r3, rINST - bl MterpInvokeDirectRange - cmp r0, #0 - beq MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cmp r0, #0 - bne MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_static_range: /* 0x77 */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeStaticRange - EXPORT_PC - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - mov r3, rINST - bl MterpInvokeStaticRange - cmp r0, #0 - beq MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cmp r0, #0 - bne MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_interface_range: /* 0x78 */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeInterfaceRange - EXPORT_PC - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - mov r3, rINST - bl MterpInvokeInterfaceRange - cmp r0, #0 - beq MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cmp r0, #0 - bne MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - -/* ------------------------------ */ - .balign 128 -.L_op_unused_79: /* 0x79 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_7a: /* 0x7a */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_neg_int: /* 0x7b */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op r0". - * This could be an ARM instruction or a function call. - * - * for: neg-int, not-int, neg-float, int-to-float, float-to-int, - * int-to-byte, int-to-char, int-to-short - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r0, r3 @ r0<- vB - @ optional op; may set condition codes - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - rsb r0, r0, #0 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 8-9 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_not_int: /* 0x7c */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op r0". - * This could be an ARM instruction or a function call. - * - * for: neg-int, not-int, neg-float, int-to-float, float-to-int, - * int-to-byte, int-to-char, int-to-short - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r0, r3 @ r0<- vB - @ optional op; may set condition codes - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - mvn r0, r0 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 8-9 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_neg_long: /* 0x7d */ - /* - * Generic 64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op r0/r1". - * This could be an ARM instruction or a function call. - * - * For: neg-long, not-long, neg-double, long-to-double, double-to-long - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx rINST, rINST, #8, #4 @ rINST<- A - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] - ldmia r3, {r0-r1} @ r0/r1<- vAA - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - rsbs r0, r0, #0 @ optional op; may set condition codes - rsc r1, r1, #0 @ r0/r1<- op, r2-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vAA<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 10-11 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_not_long: /* 0x7e */ - /* - * Generic 64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op r0/r1". - * This could be an ARM instruction or a function call. - * - * For: neg-long, not-long, neg-double, long-to-double, double-to-long - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx rINST, rINST, #8, #4 @ rINST<- A - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] - ldmia r3, {r0-r1} @ r0/r1<- vAA - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - mvn r0, r0 @ optional op; may set condition codes - mvn r1, r1 @ r0/r1<- op, r2-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vAA<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 10-11 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_neg_float: /* 0x7f */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op r0". - * This could be an ARM instruction or a function call. - * - * for: neg-int, not-int, neg-float, int-to-float, float-to-int, - * int-to-byte, int-to-char, int-to-short - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r0, r3 @ r0<- vB - @ optional op; may set condition codes - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - add r0, r0, #0x80000000 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 8-9 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_neg_double: /* 0x80 */ - /* - * Generic 64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op r0/r1". - * This could be an ARM instruction or a function call. - * - * For: neg-long, not-long, neg-double, long-to-double, double-to-long - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx rINST, rINST, #8, #4 @ rINST<- A - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] - ldmia r3, {r0-r1} @ r0/r1<- vAA - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - @ optional op; may set condition codes - add r1, r1, #0x80000000 @ r0/r1<- op, r2-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vAA<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 10-11 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_long: /* 0x81 */ - /* - * Generic 32bit-to-64bit unary operation. Provide an "instr" line - * that specifies an instruction that performs "result = op r0", where - * "result" is a 64-bit quantity in r0/r1. - * - * For: int-to-long, int-to-double, float-to-long, float-to-double - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx rINST, rINST, #8, #4 @ rINST<- A - GET_VREG r0, r3 @ r0<- vB - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] - @ optional op; may set condition codes - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - mov r1, r0, asr #31 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 9-10 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_float: /* 0x82 */ - /* - * Generic 32-bit unary floating-point operation. Provide an "instr" - * line that specifies an instruction that performs "s1 = op s0". - * - * for: int-to-float, float-to-int - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB - flds s0, [r3] @ s0<- vB - ubfx r9, rINST, #8, #4 @ r9<- A - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - fsitos s1, s0 @ s1<- op - GET_INST_OPCODE ip @ extract opcode from rINST - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA - fsts s1, [r9] @ vA<- s1 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_double: /* 0x83 */ - /* - * Generic 32bit-to-64bit floating point unary operation. Provide an - * "instr" line that specifies an instruction that performs "d0 = op s0". - * - * For: int-to-double, float-to-double - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB - flds s0, [r3] @ s0<- vB - ubfx r9, rINST, #8, #4 @ r9<- A - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - fsitod d0, s0 @ d0<- op - CLEAR_SHADOW_PAIR r9, ip, lr @ Zero shadow regs - GET_INST_OPCODE ip @ extract opcode from rINST - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA - fstd d0, [r9] @ vA<- d0 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_long_to_int: /* 0x84 */ -/* we ignore the high word, making this equivalent to a 32-bit reg move */ - /* for move, move-object, long-to-int */ - /* op vA, vB */ - mov r1, rINST, lsr #12 @ r1<- B from 15:12 - ubfx r0, rINST, #8, #4 @ r0<- A from 11:8 - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - GET_VREG r2, r1 @ r2<- fp[B] - GET_INST_OPCODE ip @ ip<- opcode from rINST - .if 0 - SET_VREG_OBJECT r2, r0 @ fp[A]<- r2 - .else - SET_VREG r2, r0 @ fp[A]<- r2 - .endif - GOTO_OPCODE ip @ execute next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_long_to_float: /* 0x85 */ - /* - * Generic 64bit-to-32bit unary operation. Provide an "instr" line - * that specifies an instruction that performs "result = op r0/r1", where - * "result" is a 32-bit quantity in r0. - * - * For: long-to-float, double-to-int, double-to-float - * - * (This would work for long-to-int, but that instruction is actually - * an exact match for op_move.) - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] - ldmia r3, {r0-r1} @ r0/r1<- vB/vB+1 - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - @ optional op; may set condition codes - bl __aeabi_l2f @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 9-10 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_long_to_double: /* 0x86 */ - /* - * Specialised 64-bit floating point operation. - * - * Note: The result will be returned in d2. - * - * For: long-to-double - */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[A] - vldr d0, [r3] @ d0<- vAA - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - - vcvt.f64.s32 d1, s1 @ d1<- (double)(vAAh) - vcvt.f64.u32 d2, s0 @ d2<- (double)(vAAl) - vldr d3, constvalop_long_to_double - vmla.f64 d2, d1, d3 @ d2<- vAAh*2^32 + vAAl - - GET_INST_OPCODE ip @ extract opcode from rINST - vstr.64 d2, [r9] @ vAA<- d2 - GOTO_OPCODE ip @ jump to next instruction - - /* literal pool helper */ -constvalop_long_to_double: - .8byte 0x41f0000000000000 - -/* ------------------------------ */ - .balign 128 -.L_op_float_to_int: /* 0x87 */ - /* - * Generic 32-bit unary floating-point operation. Provide an "instr" - * line that specifies an instruction that performs "s1 = op s0". - * - * for: int-to-float, float-to-int - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB - flds s0, [r3] @ s0<- vB - ubfx r9, rINST, #8, #4 @ r9<- A - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - ftosizs s1, s0 @ s1<- op - GET_INST_OPCODE ip @ extract opcode from rINST - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA - fsts s1, [r9] @ vA<- s1 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_float_to_long: /* 0x88 */ - /* - * Generic 32bit-to-64bit unary operation. Provide an "instr" line - * that specifies an instruction that performs "result = op r0", where - * "result" is a 64-bit quantity in r0/r1. - * - * For: int-to-long, int-to-double, float-to-long, float-to-double - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx rINST, rINST, #8, #4 @ rINST<- A - GET_VREG r0, r3 @ r0<- vB - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] - @ optional op; may set condition codes - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - bl f2l_doconv @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 9-10 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_float_to_double: /* 0x89 */ - /* - * Generic 32bit-to-64bit floating point unary operation. Provide an - * "instr" line that specifies an instruction that performs "d0 = op s0". - * - * For: int-to-double, float-to-double - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB - flds s0, [r3] @ s0<- vB - ubfx r9, rINST, #8, #4 @ r9<- A - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - vcvt.f64.f32 d0, s0 @ d0<- op - CLEAR_SHADOW_PAIR r9, ip, lr @ Zero shadow regs - GET_INST_OPCODE ip @ extract opcode from rINST - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA - fstd d0, [r9] @ vA<- d0 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_double_to_int: /* 0x8a */ - /* - * Generic 64bit-to-32bit unary floating point operation. Provide an - * "instr" line that specifies an instruction that performs "s0 = op d0". - * - * For: double-to-int, double-to-float - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB - fldd d0, [r3] @ d0<- vB - ubfx r9, rINST, #8, #4 @ r9<- A - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - ftosizd s0, d0 @ s0<- op - GET_INST_OPCODE ip @ extract opcode from rINST - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA - fsts s0, [r9] @ vA<- s0 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_double_to_long: /* 0x8b */ - /* - * Generic 64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op r0/r1". - * This could be an ARM instruction or a function call. - * - * For: neg-long, not-long, neg-double, long-to-double, double-to-long - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx rINST, rINST, #8, #4 @ rINST<- A - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] - ldmia r3, {r0-r1} @ r0/r1<- vAA - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - @ optional op; may set condition codes - bl d2l_doconv @ r0/r1<- op, r2-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vAA<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 10-11 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_double_to_float: /* 0x8c */ - /* - * Generic 64bit-to-32bit unary floating point operation. Provide an - * "instr" line that specifies an instruction that performs "s0 = op d0". - * - * For: double-to-int, double-to-float - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB - fldd d0, [r3] @ d0<- vB - ubfx r9, rINST, #8, #4 @ r9<- A - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - vcvt.f32.f64 s0, d0 @ s0<- op - GET_INST_OPCODE ip @ extract opcode from rINST - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA - fsts s0, [r9] @ vA<- s0 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_byte: /* 0x8d */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op r0". - * This could be an ARM instruction or a function call. - * - * for: neg-int, not-int, neg-float, int-to-float, float-to-int, - * int-to-byte, int-to-char, int-to-short - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r0, r3 @ r0<- vB - @ optional op; may set condition codes - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - sxtb r0, r0 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 8-9 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_char: /* 0x8e */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op r0". - * This could be an ARM instruction or a function call. - * - * for: neg-int, not-int, neg-float, int-to-float, float-to-int, - * int-to-byte, int-to-char, int-to-short - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r0, r3 @ r0<- vB - @ optional op; may set condition codes - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - uxth r0, r0 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 8-9 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_short: /* 0x8f */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op r0". - * This could be an ARM instruction or a function call. - * - * for: neg-int, not-int, neg-float, int-to-float, float-to-int, - * int-to-byte, int-to-char, int-to-short - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r0, r3 @ r0<- vB - @ optional op; may set condition codes - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - sxth r0, r0 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 8-9 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_add_int: /* 0x90 */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - GET_VREG r1, r3 @ r1<- vCC - GET_VREG r0, r2 @ r0<- vBB - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - @ optional op; may set condition codes - add r0, r0, r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 11-14 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_sub_int: /* 0x91 */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - GET_VREG r1, r3 @ r1<- vCC - GET_VREG r0, r2 @ r0<- vBB - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - @ optional op; may set condition codes - sub r0, r0, r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 11-14 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int: /* 0x92 */ -/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - GET_VREG r1, r3 @ r1<- vCC - GET_VREG r0, r2 @ r0<- vBB - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - @ optional op; may set condition codes - mul r0, r1, r0 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 11-14 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_div_int: /* 0x93 */ - /* - * Specialized 32-bit binary operation - * - * Performs "r0 = r0 div r1". The selection between sdiv or the gcc helper - * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for - * ARMv7 CPUs that have hardware division support). - * - * div-int - * - */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - GET_VREG r1, r3 @ r1<- vCC - GET_VREG r0, r2 @ r0<- vBB - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST -#ifdef __ARM_ARCH_EXT_IDIV__ - sdiv r0, r0, r1 @ r0<- op -#else - bl __aeabi_idiv @ r0<- op, r0-r3 changed -#endif - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 11-14 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int: /* 0x94 */ - /* - * Specialized 32-bit binary operation - * - * Performs "r1 = r0 rem r1". The selection between sdiv block or the gcc helper - * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for - * ARMv7 CPUs that have hardware division support). - * - * NOTE: idivmod returns quotient in r0 and remainder in r1 - * - * rem-int - * - */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - GET_VREG r1, r3 @ r1<- vCC - GET_VREG r0, r2 @ r0<- vBB - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST -#ifdef __ARM_ARCH_EXT_IDIV__ - sdiv r2, r0, r1 - mls r1, r1, r2, r0 @ r1<- op, r0-r2 changed -#else - bl __aeabi_idivmod @ r1<- op, r0-r3 changed -#endif - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r1, r9 @ vAA<- r1 - GOTO_OPCODE ip @ jump to next instruction - /* 11-14 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_and_int: /* 0x95 */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - GET_VREG r1, r3 @ r1<- vCC - GET_VREG r0, r2 @ r0<- vBB - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - @ optional op; may set condition codes - and r0, r0, r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 11-14 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_or_int: /* 0x96 */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - GET_VREG r1, r3 @ r1<- vCC - GET_VREG r0, r2 @ r0<- vBB - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - @ optional op; may set condition codes - orr r0, r0, r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 11-14 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int: /* 0x97 */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - GET_VREG r1, r3 @ r1<- vCC - GET_VREG r0, r2 @ r0<- vBB - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - @ optional op; may set condition codes - eor r0, r0, r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 11-14 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_shl_int: /* 0x98 */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - GET_VREG r1, r3 @ r1<- vCC - GET_VREG r0, r2 @ r0<- vBB - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - and r1, r1, #31 @ optional op; may set condition codes - mov r0, r0, asl r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 11-14 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_shr_int: /* 0x99 */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - GET_VREG r1, r3 @ r1<- vCC - GET_VREG r0, r2 @ r0<- vBB - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - and r1, r1, #31 @ optional op; may set condition codes - mov r0, r0, asr r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 11-14 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_int: /* 0x9a */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - GET_VREG r1, r3 @ r1<- vCC - GET_VREG r0, r2 @ r0<- vBB - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - and r1, r1, #31 @ optional op; may set condition codes - mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 11-14 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_add_long: /* 0x9b */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = r0-r1 op r2-r3". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * for: add-long, sub-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, - * rem-double - * - * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. - */ - /* binop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov rINST, rINST, lsr #8 @ rINST<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[AA] - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] - ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 - ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 - .if 0 - orrs ip, r2, r3 @ second arg (r2-r3) is zero? - beq common_errDivideByZero - .endif - CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - adds r0, r0, r2 @ optional op; may set condition codes - adc r1, r1, r3 @ result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 14-17 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_sub_long: /* 0x9c */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = r0-r1 op r2-r3". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * for: add-long, sub-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, - * rem-double - * - * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. - */ - /* binop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov rINST, rINST, lsr #8 @ rINST<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[AA] - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] - ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 - ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 - .if 0 - orrs ip, r2, r3 @ second arg (r2-r3) is zero? - beq common_errDivideByZero - .endif - CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - subs r0, r0, r2 @ optional op; may set condition codes - sbc r1, r1, r3 @ result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 14-17 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_mul_long: /* 0x9d */ - /* - * Signed 64-bit integer multiply. - * - * Consider WXxYZ (r1r0 x r3r2) with a long multiply: - * WX - * x YZ - * -------- - * ZW ZX - * YW YX - * - * The low word of the result holds ZX, the high word holds - * (ZW+YX) + (the high overflow from ZX). YW doesn't matter because - * it doesn't fit in the low 64 bits. - * - * Unlike most ARM math operations, multiply instructions have - * restrictions on using the same register more than once (Rd and Rm - * cannot be the same). - */ - /* mul-long vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] - ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 - ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 - mul ip, r2, r1 @ ip<- ZxW - umull r1, lr, r2, r0 @ r1/lr <- ZxX - mla r2, r0, r3, ip @ r2<- YxX + (ZxW) - mov r0, rINST, lsr #8 @ r0<- AA - add r2, r2, lr @ r2<- lr + low(ZxW + (YxX)) - CLEAR_SHADOW_PAIR r0, lr, ip @ Zero out the shadow regs - VREG_INDEX_TO_ADDR r0, r0 @ r0<- &fp[AA] - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r0, {r1-r2 } @ vAA/vAA+1<- r1/r2 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_div_long: /* 0x9e */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = r0-r1 op r2-r3". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * for: add-long, sub-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, - * rem-double - * - * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. - */ - /* binop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov rINST, rINST, lsr #8 @ rINST<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[AA] - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] - ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 - ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 - .if 1 - orrs ip, r2, r3 @ second arg (r2-r3) is zero? - beq common_errDivideByZero - .endif - CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - @ optional op; may set condition codes - bl __aeabi_ldivmod @ result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 14-17 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_rem_long: /* 0x9f */ -/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = r0-r1 op r2-r3". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * for: add-long, sub-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, - * rem-double - * - * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. - */ - /* binop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov rINST, rINST, lsr #8 @ rINST<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[AA] - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] - ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 - ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 - .if 1 - orrs ip, r2, r3 @ second arg (r2-r3) is zero? - beq common_errDivideByZero - .endif - CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - @ optional op; may set condition codes - bl __aeabi_ldivmod @ result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3 - GOTO_OPCODE ip @ jump to next instruction - /* 14-17 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_and_long: /* 0xa0 */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = r0-r1 op r2-r3". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * for: add-long, sub-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, - * rem-double - * - * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. - */ - /* binop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov rINST, rINST, lsr #8 @ rINST<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[AA] - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] - ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 - ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 - .if 0 - orrs ip, r2, r3 @ second arg (r2-r3) is zero? - beq common_errDivideByZero - .endif - CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - and r0, r0, r2 @ optional op; may set condition codes - and r1, r1, r3 @ result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 14-17 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_or_long: /* 0xa1 */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = r0-r1 op r2-r3". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * for: add-long, sub-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, - * rem-double - * - * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. - */ - /* binop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov rINST, rINST, lsr #8 @ rINST<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[AA] - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] - ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 - ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 - .if 0 - orrs ip, r2, r3 @ second arg (r2-r3) is zero? - beq common_errDivideByZero - .endif - CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - orr r0, r0, r2 @ optional op; may set condition codes - orr r1, r1, r3 @ result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 14-17 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_xor_long: /* 0xa2 */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = r0-r1 op r2-r3". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * for: add-long, sub-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, - * rem-double - * - * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. - */ - /* binop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov rINST, rINST, lsr #8 @ rINST<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[AA] - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] - ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 - ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 - .if 0 - orrs ip, r2, r3 @ second arg (r2-r3) is zero? - beq common_errDivideByZero - .endif - CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - eor r0, r0, r2 @ optional op; may set condition codes - eor r1, r1, r3 @ result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 14-17 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_shl_long: /* 0xa3 */ - /* - * Long integer shift. This is different from the generic 32/64-bit - * binary operations because vAA/vBB are 64-bit but vCC (the shift - * distance) is 32-bit. Also, Dalvik requires us to mask off the low - * 6 bits of the shift distance. - */ - /* shl-long vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - and r3, r0, #255 @ r3<- BB - mov r0, r0, lsr #8 @ r0<- CC - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[BB] - GET_VREG r2, r0 @ r2<- vCC - ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 - CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs - and r2, r2, #63 @ r2<- r2 & 0x3f - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] - mov r1, r1, asl r2 @ r1<- r1 << r2 - rsb r3, r2, #32 @ r3<- 32 - r2 - orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) - subs ip, r2, #32 @ ip<- r2 - 32 - movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - mov r0, r0, asl r2 @ r0<- r0 << r2 - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_shr_long: /* 0xa4 */ - /* - * Long integer shift. This is different from the generic 32/64-bit - * binary operations because vAA/vBB are 64-bit but vCC (the shift - * distance) is 32-bit. Also, Dalvik requires us to mask off the low - * 6 bits of the shift distance. - */ - /* shr-long vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - and r3, r0, #255 @ r3<- BB - mov r0, r0, lsr #8 @ r0<- CC - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[BB] - GET_VREG r2, r0 @ r2<- vCC - ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 - CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs - and r2, r2, #63 @ r0<- r0 & 0x3f - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] - mov r0, r0, lsr r2 @ r0<- r2 >> r2 - rsb r3, r2, #32 @ r3<- 32 - r2 - orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) - subs ip, r2, #32 @ ip<- r2 - 32 - movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - mov r1, r1, asr r2 @ r1<- r1 >> r2 - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_long: /* 0xa5 */ - /* - * Long integer shift. This is different from the generic 32/64-bit - * binary operations because vAA/vBB are 64-bit but vCC (the shift - * distance) is 32-bit. Also, Dalvik requires us to mask off the low - * 6 bits of the shift distance. - */ - /* ushr-long vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - and r3, r0, #255 @ r3<- BB - mov r0, r0, lsr #8 @ r0<- CC - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[BB] - GET_VREG r2, r0 @ r2<- vCC - ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 - CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs - and r2, r2, #63 @ r0<- r0 & 0x3f - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] - mov r0, r0, lsr r2 @ r0<- r2 >> r2 - rsb r3, r2, #32 @ r3<- 32 - r2 - orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) - subs ip, r2, #32 @ ip<- r2 - 32 - movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - mov r1, r1, lsr r2 @ r1<- r1 >>> r2 - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_add_float: /* 0xa6 */ - /* - * Generic 32-bit floating-point operation. Provide an "instr" line that - * specifies an instruction that performs "s2 = s0 op s1". Because we - * use the "softfp" ABI, this must be an instruction, not a function call. - * - * For: add-float, sub-float, mul-float, div-float - */ - /* floatop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB - flds s1, [r3] @ s1<- vCC - flds s0, [r2] @ s0<- vBB - - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - fadds s2, s0, s1 @ s2<- op - GET_INST_OPCODE ip @ extract opcode from rINST - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA - fsts s2, [r9] @ vAA<- s2 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_sub_float: /* 0xa7 */ - /* - * Generic 32-bit floating-point operation. Provide an "instr" line that - * specifies an instruction that performs "s2 = s0 op s1". Because we - * use the "softfp" ABI, this must be an instruction, not a function call. - * - * For: add-float, sub-float, mul-float, div-float - */ - /* floatop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB - flds s1, [r3] @ s1<- vCC - flds s0, [r2] @ s0<- vBB - - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - fsubs s2, s0, s1 @ s2<- op - GET_INST_OPCODE ip @ extract opcode from rINST - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA - fsts s2, [r9] @ vAA<- s2 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_mul_float: /* 0xa8 */ - /* - * Generic 32-bit floating-point operation. Provide an "instr" line that - * specifies an instruction that performs "s2 = s0 op s1". Because we - * use the "softfp" ABI, this must be an instruction, not a function call. - * - * For: add-float, sub-float, mul-float, div-float - */ - /* floatop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB - flds s1, [r3] @ s1<- vCC - flds s0, [r2] @ s0<- vBB - - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - fmuls s2, s0, s1 @ s2<- op - GET_INST_OPCODE ip @ extract opcode from rINST - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA - fsts s2, [r9] @ vAA<- s2 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_div_float: /* 0xa9 */ - /* - * Generic 32-bit floating-point operation. Provide an "instr" line that - * specifies an instruction that performs "s2 = s0 op s1". Because we - * use the "softfp" ABI, this must be an instruction, not a function call. - * - * For: add-float, sub-float, mul-float, div-float - */ - /* floatop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB - flds s1, [r3] @ s1<- vCC - flds s0, [r2] @ s0<- vBB - - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - fdivs s2, s0, s1 @ s2<- op - GET_INST_OPCODE ip @ extract opcode from rINST - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA - fsts s2, [r9] @ vAA<- s2 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_rem_float: /* 0xaa */ -/* EABI doesn't define a float remainder function, but libm does */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - GET_VREG r1, r3 @ r1<- vCC - GET_VREG r0, r2 @ r0<- vBB - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - @ optional op; may set condition codes - bl fmodf @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 11-14 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_add_double: /* 0xab */ - /* - * Generic 64-bit double-precision floating point binary operation. - * Provide an "instr" line that specifies an instruction that performs - * "d2 = d0 op d1". - * - * for: add-double, sub-double, mul-double, div-double - */ - /* doubleop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB - fldd d1, [r3] @ d1<- vCC - fldd d0, [r2] @ d0<- vBB - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - faddd d2, d0, d1 @ s2<- op - CLEAR_SHADOW_PAIR r9, ip, lr @ Zero shadow regs - GET_INST_OPCODE ip @ extract opcode from rINST - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA - fstd d2, [r9] @ vAA<- d2 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_sub_double: /* 0xac */ - /* - * Generic 64-bit double-precision floating point binary operation. - * Provide an "instr" line that specifies an instruction that performs - * "d2 = d0 op d1". - * - * for: add-double, sub-double, mul-double, div-double - */ - /* doubleop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB - fldd d1, [r3] @ d1<- vCC - fldd d0, [r2] @ d0<- vBB - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - fsubd d2, d0, d1 @ s2<- op - CLEAR_SHADOW_PAIR r9, ip, lr @ Zero shadow regs - GET_INST_OPCODE ip @ extract opcode from rINST - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA - fstd d2, [r9] @ vAA<- d2 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_mul_double: /* 0xad */ - /* - * Generic 64-bit double-precision floating point binary operation. - * Provide an "instr" line that specifies an instruction that performs - * "d2 = d0 op d1". - * - * for: add-double, sub-double, mul-double, div-double - */ - /* doubleop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB - fldd d1, [r3] @ d1<- vCC - fldd d0, [r2] @ d0<- vBB - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - fmuld d2, d0, d1 @ s2<- op - CLEAR_SHADOW_PAIR r9, ip, lr @ Zero shadow regs - GET_INST_OPCODE ip @ extract opcode from rINST - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA - fstd d2, [r9] @ vAA<- d2 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_div_double: /* 0xae */ - /* - * Generic 64-bit double-precision floating point binary operation. - * Provide an "instr" line that specifies an instruction that performs - * "d2 = d0 op d1". - * - * for: add-double, sub-double, mul-double, div-double - */ - /* doubleop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB - fldd d1, [r3] @ d1<- vCC - fldd d0, [r2] @ d0<- vBB - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - fdivd d2, d0, d1 @ s2<- op - CLEAR_SHADOW_PAIR r9, ip, lr @ Zero shadow regs - GET_INST_OPCODE ip @ extract opcode from rINST - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA - fstd d2, [r9] @ vAA<- d2 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_rem_double: /* 0xaf */ -/* EABI doesn't define a double remainder function, but libm does */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = r0-r1 op r2-r3". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * for: add-long, sub-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, - * rem-double - * - * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. - */ - /* binop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov rINST, rINST, lsr #8 @ rINST<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[AA] - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] - ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 - ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 - .if 0 - orrs ip, r2, r3 @ second arg (r2-r3) is zero? - beq common_errDivideByZero - .endif - CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - @ optional op; may set condition codes - bl fmod @ result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 14-17 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_add_int_2addr: /* 0xb0 */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r1, r3 @ r1<- vB - GET_VREG r0, r9 @ r0<- vA - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - - @ optional op; may set condition codes - add r0, r0, r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_sub_int_2addr: /* 0xb1 */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r1, r3 @ r1<- vB - GET_VREG r0, r9 @ r0<- vA - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - - @ optional op; may set condition codes - sub r0, r0, r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int_2addr: /* 0xb2 */ -/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r1, r3 @ r1<- vB - GET_VREG r0, r9 @ r0<- vA - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - - @ optional op; may set condition codes - mul r0, r1, r0 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_div_int_2addr: /* 0xb3 */ - /* - * Specialized 32-bit binary operation - * - * Performs "r0 = r0 div r1". The selection between sdiv or the gcc helper - * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for - * ARMv7 CPUs that have hardware division support). - * - * div-int/2addr - * - */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r1, r3 @ r1<- vB - GET_VREG r0, r9 @ r0<- vA - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - -#ifdef __ARM_ARCH_EXT_IDIV__ - sdiv r0, r0, r1 @ r0<- op -#else - bl __aeabi_idiv @ r0<- op, r0-r3 changed -#endif - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int_2addr: /* 0xb4 */ - /* - * Specialized 32-bit binary operation - * - * Performs "r1 = r0 rem r1". The selection between sdiv block or the gcc helper - * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for - * ARMv7 CPUs that have hardware division support). - * - * NOTE: idivmod returns quotient in r0 and remainder in r1 - * - * rem-int/2addr - * - */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r1, r3 @ r1<- vB - GET_VREG r0, r9 @ r0<- vA - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - -#ifdef __ARM_ARCH_EXT_IDIV__ - sdiv r2, r0, r1 - mls r1, r1, r2, r0 @ r1<- op -#else - bl __aeabi_idivmod @ r1<- op, r0-r3 changed -#endif - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r1, r9 @ vAA<- r1 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_and_int_2addr: /* 0xb5 */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r1, r3 @ r1<- vB - GET_VREG r0, r9 @ r0<- vA - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - - @ optional op; may set condition codes - and r0, r0, r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_or_int_2addr: /* 0xb6 */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r1, r3 @ r1<- vB - GET_VREG r0, r9 @ r0<- vA - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - - @ optional op; may set condition codes - orr r0, r0, r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int_2addr: /* 0xb7 */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r1, r3 @ r1<- vB - GET_VREG r0, r9 @ r0<- vA - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - - @ optional op; may set condition codes - eor r0, r0, r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_shl_int_2addr: /* 0xb8 */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r1, r3 @ r1<- vB - GET_VREG r0, r9 @ r0<- vA - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - - and r1, r1, #31 @ optional op; may set condition codes - mov r0, r0, asl r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_shr_int_2addr: /* 0xb9 */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r1, r3 @ r1<- vB - GET_VREG r0, r9 @ r0<- vA - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - - and r1, r1, #31 @ optional op; may set condition codes - mov r0, r0, asr r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_int_2addr: /* 0xba */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r1, r3 @ r1<- vB - GET_VREG r0, r9 @ r0<- vA - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - - and r1, r1, #31 @ optional op; may set condition codes - mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_add_long_2addr: /* 0xbb */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0-r1 op r2-r3". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, - * rem-double/2addr - */ - /* binop/2addr vA, vB */ - mov r1, rINST, lsr #12 @ r1<- B - ubfx rINST, rINST, #8, #4 @ rINST<- A - VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] - ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 - ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 - .if 0 - orrs ip, r2, r3 @ second arg (r2-r3) is zero? - beq common_errDivideByZero - .endif - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - adds r0, r0, r2 @ optional op; may set condition codes - adc r1, r1, r3 @ result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 12-15 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_sub_long_2addr: /* 0xbc */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0-r1 op r2-r3". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, - * rem-double/2addr - */ - /* binop/2addr vA, vB */ - mov r1, rINST, lsr #12 @ r1<- B - ubfx rINST, rINST, #8, #4 @ rINST<- A - VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] - ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 - ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 - .if 0 - orrs ip, r2, r3 @ second arg (r2-r3) is zero? - beq common_errDivideByZero - .endif - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - subs r0, r0, r2 @ optional op; may set condition codes - sbc r1, r1, r3 @ result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 12-15 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_mul_long_2addr: /* 0xbd */ - /* - * Signed 64-bit integer multiply, "/2addr" version. - * - * See op_mul_long for an explanation. - * - * We get a little tight on registers, so to avoid looking up &fp[A] - * again we stuff it into rINST. - */ - /* mul-long/2addr vA, vB */ - mov r1, rINST, lsr #12 @ r1<- B - ubfx r9, rINST, #8, #4 @ r9<- A - VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] - VREG_INDEX_TO_ADDR rINST, r9 @ rINST<- &fp[A] - ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 - ldmia rINST, {r0-r1} @ r0/r1<- vAA/vAA+1 - mul ip, r2, r1 @ ip<- ZxW - umull r1, lr, r2, r0 @ r1/lr <- ZxX - mla r2, r0, r3, ip @ r2<- YxX + (ZxW) - mov r0, rINST @ r0<- &fp[A] (free up rINST) - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - add r2, r2, lr @ r2<- r2 + low(ZxW + (YxX)) - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r0, {r1-r2} @ vAA/vAA+1<- r1/r2 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_div_long_2addr: /* 0xbe */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0-r1 op r2-r3". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, - * rem-double/2addr - */ - /* binop/2addr vA, vB */ - mov r1, rINST, lsr #12 @ r1<- B - ubfx rINST, rINST, #8, #4 @ rINST<- A - VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] - ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 - ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 - .if 1 - orrs ip, r2, r3 @ second arg (r2-r3) is zero? - beq common_errDivideByZero - .endif - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - @ optional op; may set condition codes - bl __aeabi_ldivmod @ result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 12-15 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_rem_long_2addr: /* 0xbf */ -/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0-r1 op r2-r3". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, - * rem-double/2addr - */ - /* binop/2addr vA, vB */ - mov r1, rINST, lsr #12 @ r1<- B - ubfx rINST, rINST, #8, #4 @ rINST<- A - VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] - ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 - ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 - .if 1 - orrs ip, r2, r3 @ second arg (r2-r3) is zero? - beq common_errDivideByZero - .endif - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - @ optional op; may set condition codes - bl __aeabi_ldivmod @ result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3 - GOTO_OPCODE ip @ jump to next instruction - /* 12-15 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_and_long_2addr: /* 0xc0 */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0-r1 op r2-r3". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, - * rem-double/2addr - */ - /* binop/2addr vA, vB */ - mov r1, rINST, lsr #12 @ r1<- B - ubfx rINST, rINST, #8, #4 @ rINST<- A - VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] - ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 - ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 - .if 0 - orrs ip, r2, r3 @ second arg (r2-r3) is zero? - beq common_errDivideByZero - .endif - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - and r0, r0, r2 @ optional op; may set condition codes - and r1, r1, r3 @ result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 12-15 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_or_long_2addr: /* 0xc1 */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0-r1 op r2-r3". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, - * rem-double/2addr - */ - /* binop/2addr vA, vB */ - mov r1, rINST, lsr #12 @ r1<- B - ubfx rINST, rINST, #8, #4 @ rINST<- A - VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] - ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 - ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 - .if 0 - orrs ip, r2, r3 @ second arg (r2-r3) is zero? - beq common_errDivideByZero - .endif - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - orr r0, r0, r2 @ optional op; may set condition codes - orr r1, r1, r3 @ result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 12-15 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_xor_long_2addr: /* 0xc2 */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0-r1 op r2-r3". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, - * rem-double/2addr - */ - /* binop/2addr vA, vB */ - mov r1, rINST, lsr #12 @ r1<- B - ubfx rINST, rINST, #8, #4 @ rINST<- A - VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] - ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 - ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 - .if 0 - orrs ip, r2, r3 @ second arg (r2-r3) is zero? - beq common_errDivideByZero - .endif - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - eor r0, r0, r2 @ optional op; may set condition codes - eor r1, r1, r3 @ result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 12-15 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_shl_long_2addr: /* 0xc3 */ - /* - * Long integer shift, 2addr version. vA is 64-bit value/result, vB is - * 32-bit shift distance. - */ - /* shl-long/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r2, r3 @ r2<- vB - CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[A] - and r2, r2, #63 @ r2<- r2 & 0x3f - ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 - mov r1, r1, asl r2 @ r1<- r1 << r2 - rsb r3, r2, #32 @ r3<- 32 - r2 - orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) - subs ip, r2, #32 @ ip<- r2 - 32 - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) - mov r0, r0, asl r2 @ r0<- r0 << r2 - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_shr_long_2addr: /* 0xc4 */ - /* - * Long integer shift, 2addr version. vA is 64-bit value/result, vB is - * 32-bit shift distance. - */ - /* shr-long/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r2, r3 @ r2<- vB - CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[A] - and r2, r2, #63 @ r2<- r2 & 0x3f - ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 - mov r0, r0, lsr r2 @ r0<- r2 >> r2 - rsb r3, r2, #32 @ r3<- 32 - r2 - orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) - subs ip, r2, #32 @ ip<- r2 - 32 - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) - mov r1, r1, asr r2 @ r1<- r1 >> r2 - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_long_2addr: /* 0xc5 */ - /* - * Long integer shift, 2addr version. vA is 64-bit value/result, vB is - * 32-bit shift distance. - */ - /* ushr-long/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r2, r3 @ r2<- vB - CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[A] - and r2, r2, #63 @ r2<- r2 & 0x3f - ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 - mov r0, r0, lsr r2 @ r0<- r2 >> r2 - rsb r3, r2, #32 @ r3<- 32 - r2 - orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) - subs ip, r2, #32 @ ip<- r2 - 32 - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) - mov r1, r1, lsr r2 @ r1<- r1 >>> r2 - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_add_float_2addr: /* 0xc6 */ - /* - * Generic 32-bit floating point "/2addr" binary operation. Provide - * an "instr" line that specifies an instruction that performs - * "s2 = s0 op s1". - * - * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr - */ - /* binop/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA - flds s1, [r3] @ s1<- vB - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - flds s0, [r9] @ s0<- vA - fadds s2, s0, s1 @ s2<- op - GET_INST_OPCODE ip @ extract opcode from rINST - fsts s2, [r9] @ vAA<- s2 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_sub_float_2addr: /* 0xc7 */ - /* - * Generic 32-bit floating point "/2addr" binary operation. Provide - * an "instr" line that specifies an instruction that performs - * "s2 = s0 op s1". - * - * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr - */ - /* binop/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA - flds s1, [r3] @ s1<- vB - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - flds s0, [r9] @ s0<- vA - fsubs s2, s0, s1 @ s2<- op - GET_INST_OPCODE ip @ extract opcode from rINST - fsts s2, [r9] @ vAA<- s2 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_mul_float_2addr: /* 0xc8 */ - /* - * Generic 32-bit floating point "/2addr" binary operation. Provide - * an "instr" line that specifies an instruction that performs - * "s2 = s0 op s1". - * - * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr - */ - /* binop/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA - flds s1, [r3] @ s1<- vB - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - flds s0, [r9] @ s0<- vA - fmuls s2, s0, s1 @ s2<- op - GET_INST_OPCODE ip @ extract opcode from rINST - fsts s2, [r9] @ vAA<- s2 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_div_float_2addr: /* 0xc9 */ - /* - * Generic 32-bit floating point "/2addr" binary operation. Provide - * an "instr" line that specifies an instruction that performs - * "s2 = s0 op s1". - * - * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr - */ - /* binop/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA - flds s1, [r3] @ s1<- vB - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - flds s0, [r9] @ s0<- vA - fdivs s2, s0, s1 @ s2<- op - GET_INST_OPCODE ip @ extract opcode from rINST - fsts s2, [r9] @ vAA<- s2 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_rem_float_2addr: /* 0xca */ -/* EABI doesn't define a float remainder function, but libm does */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r1, r3 @ r1<- vB - GET_VREG r0, r9 @ r0<- vA - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - - @ optional op; may set condition codes - bl fmodf @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_add_double_2addr: /* 0xcb */ - /* - * Generic 64-bit floating point "/2addr" binary operation. Provide - * an "instr" line that specifies an instruction that performs - * "d2 = d0 op d1". - * - * For: add-double/2addr, sub-double/2addr, mul-double/2addr, - * div-double/2addr - */ - /* binop/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB - CLEAR_SHADOW_PAIR r9, ip, r0 @ Zero out shadow regs - fldd d1, [r3] @ d1<- vB - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - fldd d0, [r9] @ d0<- vA - faddd d2, d0, d1 @ d2<- op - GET_INST_OPCODE ip @ extract opcode from rINST - fstd d2, [r9] @ vAA<- d2 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_sub_double_2addr: /* 0xcc */ - /* - * Generic 64-bit floating point "/2addr" binary operation. Provide - * an "instr" line that specifies an instruction that performs - * "d2 = d0 op d1". - * - * For: add-double/2addr, sub-double/2addr, mul-double/2addr, - * div-double/2addr - */ - /* binop/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB - CLEAR_SHADOW_PAIR r9, ip, r0 @ Zero out shadow regs - fldd d1, [r3] @ d1<- vB - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - fldd d0, [r9] @ d0<- vA - fsubd d2, d0, d1 @ d2<- op - GET_INST_OPCODE ip @ extract opcode from rINST - fstd d2, [r9] @ vAA<- d2 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_mul_double_2addr: /* 0xcd */ - /* - * Generic 64-bit floating point "/2addr" binary operation. Provide - * an "instr" line that specifies an instruction that performs - * "d2 = d0 op d1". - * - * For: add-double/2addr, sub-double/2addr, mul-double/2addr, - * div-double/2addr - */ - /* binop/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB - CLEAR_SHADOW_PAIR r9, ip, r0 @ Zero out shadow regs - fldd d1, [r3] @ d1<- vB - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - fldd d0, [r9] @ d0<- vA - fmuld d2, d0, d1 @ d2<- op - GET_INST_OPCODE ip @ extract opcode from rINST - fstd d2, [r9] @ vAA<- d2 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_div_double_2addr: /* 0xce */ - /* - * Generic 64-bit floating point "/2addr" binary operation. Provide - * an "instr" line that specifies an instruction that performs - * "d2 = d0 op d1". - * - * For: add-double/2addr, sub-double/2addr, mul-double/2addr, - * div-double/2addr - */ - /* binop/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB - CLEAR_SHADOW_PAIR r9, ip, r0 @ Zero out shadow regs - fldd d1, [r3] @ d1<- vB - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - fldd d0, [r9] @ d0<- vA - fdivd d2, d0, d1 @ d2<- op - GET_INST_OPCODE ip @ extract opcode from rINST - fstd d2, [r9] @ vAA<- d2 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_rem_double_2addr: /* 0xcf */ -/* EABI doesn't define a double remainder function, but libm does */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0-r1 op r2-r3". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, - * rem-double/2addr - */ - /* binop/2addr vA, vB */ - mov r1, rINST, lsr #12 @ r1<- B - ubfx rINST, rINST, #8, #4 @ rINST<- A - VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] - ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 - ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 - .if 0 - orrs ip, r2, r3 @ second arg (r2-r3) is zero? - beq common_errDivideByZero - .endif - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - @ optional op; may set condition codes - bl fmod @ result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 12-15 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_add_int_lit16: /* 0xd0 */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) - mov r2, rINST, lsr #12 @ r2<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r0, r2 @ r0<- vB - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - - add r0, r0, r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_rsub_int: /* 0xd1 */ -/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) - mov r2, rINST, lsr #12 @ r2<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r0, r2 @ r0<- vB - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - - rsb r0, r0, r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int_lit16: /* 0xd2 */ -/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) - mov r2, rINST, lsr #12 @ r2<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r0, r2 @ r0<- vB - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - - mul r0, r1, r0 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_div_int_lit16: /* 0xd3 */ - /* - * Specialized 32-bit binary operation - * - * Performs "r0 = r0 div r1". The selection between sdiv or the gcc helper - * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for - * ARMv7 CPUs that have hardware division support). - * - * div-int/lit16 - * - */ - FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) - mov r2, rINST, lsr #12 @ r2<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r0, r2 @ r0<- vB - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - -#ifdef __ARM_ARCH_EXT_IDIV__ - sdiv r0, r0, r1 @ r0<- op -#else - bl __aeabi_idiv @ r0<- op, r0-r3 changed -#endif - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int_lit16: /* 0xd4 */ - /* - * Specialized 32-bit binary operation - * - * Performs "r1 = r0 rem r1". The selection between sdiv block or the gcc helper - * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for - * ARMv7 CPUs that have hardware division support). - * - * NOTE: idivmod returns quotient in r0 and remainder in r1 - * - * rem-int/lit16 - * - */ - FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) - mov r2, rINST, lsr #12 @ r2<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r0, r2 @ r0<- vB - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - -#ifdef __ARM_ARCH_EXT_IDIV__ - sdiv r2, r0, r1 - mls r1, r1, r2, r0 @ r1<- op -#else - bl __aeabi_idivmod @ r1<- op, r0-r3 changed -#endif - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r1, r9 @ vAA<- r1 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_and_int_lit16: /* 0xd5 */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) - mov r2, rINST, lsr #12 @ r2<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r0, r2 @ r0<- vB - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - - and r0, r0, r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_or_int_lit16: /* 0xd6 */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) - mov r2, rINST, lsr #12 @ r2<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r0, r2 @ r0<- vB - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - - orr r0, r0, r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int_lit16: /* 0xd7 */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) - mov r2, rINST, lsr #12 @ r2<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r0, r2 @ r0<- vB - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - - eor r0, r0, r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_add_int_lit8: /* 0xd8 */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from r3 to r1 is not the default "asr r1, r3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r3, #255 @ r2<- BB - GET_VREG r0, r2 @ r0<- vBB - @ optional; typically r1<- ssssssCC (sign extended) - .if 0 - @cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - - add r0, r0, r3, asr #8 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-12 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_rsub_int_lit8: /* 0xd9 */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from r3 to r1 is not the default "asr r1, r3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r3, #255 @ r2<- BB - GET_VREG r0, r2 @ r0<- vBB - @ optional; typically r1<- ssssssCC (sign extended) - .if 0 - @cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - - rsb r0, r0, r3, asr #8 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-12 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int_lit8: /* 0xda */ -/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from r3 to r1 is not the default "asr r1, r3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r3, #255 @ r2<- BB - GET_VREG r0, r2 @ r0<- vBB - asr r1, r3, #8 @ optional; typically r1<- ssssssCC (sign extended) - .if 0 - @cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - - mul r0, r1, r0 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-12 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_div_int_lit8: /* 0xdb */ - /* - * Specialized 32-bit binary operation - * - * Performs "r0 = r0 div r1". The selection between sdiv or the gcc helper - * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for - * ARMv7 CPUs that have hardware division support). - * - * div-int/lit8 - * - */ - FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r3, #255 @ r2<- BB - GET_VREG r0, r2 @ r0<- vBB - movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) - @cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - -#ifdef __ARM_ARCH_EXT_IDIV__ - sdiv r0, r0, r1 @ r0<- op -#else - bl __aeabi_idiv @ r0<- op, r0-r3 changed -#endif - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-12 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int_lit8: /* 0xdc */ - /* - * Specialized 32-bit binary operation - * - * Performs "r1 = r0 rem r1". The selection between sdiv block or the gcc helper - * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for - * ARMv7 CPUs that have hardware division support). - * - * NOTE: idivmod returns quotient in r0 and remainder in r1 - * - * rem-int/lit8 - * - */ - FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r3, #255 @ r2<- BB - GET_VREG r0, r2 @ r0<- vBB - movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) - @cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - -#ifdef __ARM_ARCH_EXT_IDIV__ - sdiv r2, r0, r1 - mls r1, r1, r2, r0 @ r1<- op -#else - bl __aeabi_idivmod @ r1<- op, r0-r3 changed -#endif - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r1, r9 @ vAA<- r1 - GOTO_OPCODE ip @ jump to next instruction - /* 10-12 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_and_int_lit8: /* 0xdd */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from r3 to r1 is not the default "asr r1, r3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r3, #255 @ r2<- BB - GET_VREG r0, r2 @ r0<- vBB - @ optional; typically r1<- ssssssCC (sign extended) - .if 0 - @cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - - and r0, r0, r3, asr #8 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-12 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_or_int_lit8: /* 0xde */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from r3 to r1 is not the default "asr r1, r3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r3, #255 @ r2<- BB - GET_VREG r0, r2 @ r0<- vBB - @ optional; typically r1<- ssssssCC (sign extended) - .if 0 - @cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - - orr r0, r0, r3, asr #8 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-12 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int_lit8: /* 0xdf */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from r3 to r1 is not the default "asr r1, r3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r3, #255 @ r2<- BB - GET_VREG r0, r2 @ r0<- vBB - @ optional; typically r1<- ssssssCC (sign extended) - .if 0 - @cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - - eor r0, r0, r3, asr #8 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-12 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_shl_int_lit8: /* 0xe0 */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from r3 to r1 is not the default "asr r1, r3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r3, #255 @ r2<- BB - GET_VREG r0, r2 @ r0<- vBB - ubfx r1, r3, #8, #5 @ optional; typically r1<- ssssssCC (sign extended) - .if 0 - @cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - - mov r0, r0, asl r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-12 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_shr_int_lit8: /* 0xe1 */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from r3 to r1 is not the default "asr r1, r3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r3, #255 @ r2<- BB - GET_VREG r0, r2 @ r0<- vBB - ubfx r1, r3, #8, #5 @ optional; typically r1<- ssssssCC (sign extended) - .if 0 - @cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - - mov r0, r0, asr r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-12 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_int_lit8: /* 0xe2 */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from r3 to r1 is not the default "asr r1, r3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r3, #255 @ r2<- BB - GET_VREG r0, r2 @ r0<- vBB - ubfx r1, r3, #8, #5 @ optional; typically r1<- ssssssCC (sign extended) - .if 0 - @cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - - mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-12 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_iget_quick: /* 0xe3 */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset@CCCC */ - mov r2, rINST, lsr #12 @ r2<- B - FETCH r1, 1 @ r1<- field byte offset - GET_VREG r3, r2 @ r3<- object we're operating on - ubfx r2, rINST, #8, #4 @ r2<- A - cmp r3, #0 @ check object for null - beq common_errNullObject @ object was null - ldr r0, [r3, r1] @ r0<- obj.field - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - SET_VREG r0, r2 @ fp[A]<- r0 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iget_wide_quick: /* 0xe4 */ - /* iget-wide-quick vA, vB, offset@CCCC */ - mov r2, rINST, lsr #12 @ r2<- B - FETCH ip, 1 @ ip<- field byte offset - GET_VREG r3, r2 @ r3<- object we're operating on - ubfx r2, rINST, #8, #4 @ r2<- A - cmp r3, #0 @ check object for null - beq common_errNullObject @ object was null - ldrd r0, [r3, ip] @ r0<- obj.field (64 bits, aligned) - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - VREG_INDEX_TO_ADDR r3, r2 @ r3<- &fp[A] - CLEAR_SHADOW_PAIR r2, ip, lr @ Zero out the shadow regs - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r3, {r0-r1} @ fp[A]<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iget_object_quick: /* 0xe5 */ - /* For: iget-object-quick */ - /* op vA, vB, offset@CCCC */ - mov r2, rINST, lsr #12 @ r2<- B - FETCH r1, 1 @ r1<- field byte offset - EXPORT_PC - GET_VREG r0, r2 @ r0<- object we're operating on - bl artIGetObjectFromMterp @ (obj, offset) - ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] - ubfx r2, rINST, #8, #4 @ r2<- A - PREFETCH_INST 2 - cmp r3, #0 - bne MterpPossibleException @ bail out - SET_VREG_OBJECT r0, r2 @ fp[A]<- r0 - ADVANCE 2 @ advance rPC - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_quick: /* 0xe6 */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - mov r2, rINST, lsr #12 @ r2<- B - FETCH r1, 1 @ r1<- field byte offset - GET_VREG r3, r2 @ r3<- fp[B], the object pointer - ubfx r2, rINST, #8, #4 @ r2<- A - cmp r3, #0 @ check object for null - beq common_errNullObject @ object was null - GET_VREG r0, r2 @ r0<- fp[A] - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - str r0, [r3, r1] @ obj.field<- r0 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_wide_quick: /* 0xe7 */ - /* iput-wide-quick vA, vB, offset@CCCC */ - mov r2, rINST, lsr #12 @ r2<- B - FETCH r3, 1 @ r3<- field byte offset - GET_VREG r2, r2 @ r2<- fp[B], the object pointer - ubfx r0, rINST, #8, #4 @ r0<- A - cmp r2, #0 @ check object for null - beq common_errNullObject @ object was null - VREG_INDEX_TO_ADDR r0, r0 @ r0<- &fp[A] - ldmia r0, {r0-r1} @ r0/r1<- fp[A]/fp[A+1] - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - strd r0, [r2, r3] @ obj.field<- r0/r1 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_object_quick: /* 0xe8 */ - EXPORT_PC - add r0, rFP, #OFF_FP_SHADOWFRAME - mov r1, rPC - mov r2, rINST - bl MterpIputObjectQuick - cmp r0, #0 - beq MterpException - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual_quick: /* 0xe9 */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtualQuick - EXPORT_PC - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - mov r3, rINST - bl MterpInvokeVirtualQuick - cmp r0, #0 - beq MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cmp r0, #0 - bne MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual_range_quick: /* 0xea */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtualQuickRange - EXPORT_PC - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - mov r3, rINST - bl MterpInvokeVirtualQuickRange - cmp r0, #0 - beq MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cmp r0, #0 - bne MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - -/* ------------------------------ */ - .balign 128 -.L_op_iput_boolean_quick: /* 0xeb */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - mov r2, rINST, lsr #12 @ r2<- B - FETCH r1, 1 @ r1<- field byte offset - GET_VREG r3, r2 @ r3<- fp[B], the object pointer - ubfx r2, rINST, #8, #4 @ r2<- A - cmp r3, #0 @ check object for null - beq common_errNullObject @ object was null - GET_VREG r0, r2 @ r0<- fp[A] - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - strb r0, [r3, r1] @ obj.field<- r0 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_byte_quick: /* 0xec */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - mov r2, rINST, lsr #12 @ r2<- B - FETCH r1, 1 @ r1<- field byte offset - GET_VREG r3, r2 @ r3<- fp[B], the object pointer - ubfx r2, rINST, #8, #4 @ r2<- A - cmp r3, #0 @ check object for null - beq common_errNullObject @ object was null - GET_VREG r0, r2 @ r0<- fp[A] - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - strb r0, [r3, r1] @ obj.field<- r0 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_char_quick: /* 0xed */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - mov r2, rINST, lsr #12 @ r2<- B - FETCH r1, 1 @ r1<- field byte offset - GET_VREG r3, r2 @ r3<- fp[B], the object pointer - ubfx r2, rINST, #8, #4 @ r2<- A - cmp r3, #0 @ check object for null - beq common_errNullObject @ object was null - GET_VREG r0, r2 @ r0<- fp[A] - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - strh r0, [r3, r1] @ obj.field<- r0 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_short_quick: /* 0xee */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - mov r2, rINST, lsr #12 @ r2<- B - FETCH r1, 1 @ r1<- field byte offset - GET_VREG r3, r2 @ r3<- fp[B], the object pointer - ubfx r2, rINST, #8, #4 @ r2<- A - cmp r3, #0 @ check object for null - beq common_errNullObject @ object was null - GET_VREG r0, r2 @ r0<- fp[A] - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - strh r0, [r3, r1] @ obj.field<- r0 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iget_boolean_quick: /* 0xef */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset@CCCC */ - mov r2, rINST, lsr #12 @ r2<- B - FETCH r1, 1 @ r1<- field byte offset - GET_VREG r3, r2 @ r3<- object we're operating on - ubfx r2, rINST, #8, #4 @ r2<- A - cmp r3, #0 @ check object for null - beq common_errNullObject @ object was null - ldrb r0, [r3, r1] @ r0<- obj.field - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - SET_VREG r0, r2 @ fp[A]<- r0 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iget_byte_quick: /* 0xf0 */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset@CCCC */ - mov r2, rINST, lsr #12 @ r2<- B - FETCH r1, 1 @ r1<- field byte offset - GET_VREG r3, r2 @ r3<- object we're operating on - ubfx r2, rINST, #8, #4 @ r2<- A - cmp r3, #0 @ check object for null - beq common_errNullObject @ object was null - ldrsb r0, [r3, r1] @ r0<- obj.field - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - SET_VREG r0, r2 @ fp[A]<- r0 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iget_char_quick: /* 0xf1 */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset@CCCC */ - mov r2, rINST, lsr #12 @ r2<- B - FETCH r1, 1 @ r1<- field byte offset - GET_VREG r3, r2 @ r3<- object we're operating on - ubfx r2, rINST, #8, #4 @ r2<- A - cmp r3, #0 @ check object for null - beq common_errNullObject @ object was null - ldrh r0, [r3, r1] @ r0<- obj.field - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - SET_VREG r0, r2 @ fp[A]<- r0 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iget_short_quick: /* 0xf2 */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset@CCCC */ - mov r2, rINST, lsr #12 @ r2<- B - FETCH r1, 1 @ r1<- field byte offset - GET_VREG r3, r2 @ r3<- object we're operating on - ubfx r2, rINST, #8, #4 @ r2<- A - cmp r3, #0 @ check object for null - beq common_errNullObject @ object was null - ldrsh r0, [r3, r1] @ r0<- obj.field - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - SET_VREG r0, r2 @ fp[A]<- r0 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f3: /* 0xf3 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f4: /* 0xf4 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f5: /* 0xf5 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f6: /* 0xf6 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f7: /* 0xf7 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f8: /* 0xf8 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f9: /* 0xf9 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_polymorphic: /* 0xfa */ - /* - * invoke-polymorphic handler wrapper. - */ - /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ - .extern MterpInvokePolymorphic - EXPORT_PC - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - mov r3, rINST - bl MterpInvokePolymorphic - cmp r0, #0 - beq MterpException - FETCH_ADVANCE_INST 4 - bl MterpShouldSwitchInterpreters - cmp r0, #0 - bne MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_polymorphic_range: /* 0xfb */ - /* - * invoke-polymorphic handler wrapper. - */ - /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ - .extern MterpInvokePolymorphicRange - EXPORT_PC - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - mov r3, rINST - bl MterpInvokePolymorphicRange - cmp r0, #0 - beq MterpException - FETCH_ADVANCE_INST 4 - bl MterpShouldSwitchInterpreters - cmp r0, #0 - bne MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_custom: /* 0xfc */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeCustom - EXPORT_PC - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - mov r3, rINST - bl MterpInvokeCustom - cmp r0, #0 - beq MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cmp r0, #0 - bne MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - - /* - * Handle an invoke-custom invocation. - * - * for: invoke-custom, invoke-custom/range - */ - /* op vB, {vD, vE, vF, vG, vA}, call_site@BBBB */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, call_site@BBBB */ - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_custom_range: /* 0xfd */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeCustomRange - EXPORT_PC - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - mov r3, rINST - bl MterpInvokeCustomRange - cmp r0, #0 - beq MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cmp r0, #0 - bne MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - -/* ------------------------------ */ - .balign 128 -.L_op_const_method_handle: /* 0xfe */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstMethodHandle - EXPORT_PC - FETCH r0, 1 @ r0<- BBBB - mov r1, rINST, lsr #8 @ r1<- AA - add r2, rFP, #OFF_FP_SHADOWFRAME - mov r3, rSELF - bl MterpConstMethodHandle @ (index, tgt_reg, shadow_frame, self) - PREFETCH_INST 2 @ load rINST - cmp r0, #0 @ fail? - bne MterpPossibleException @ let reference interpreter deal with it. - ADVANCE 2 @ advance rPC - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_method_type: /* 0xff */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstMethodType - EXPORT_PC - FETCH r0, 1 @ r0<- BBBB - mov r1, rINST, lsr #8 @ r1<- AA - add r2, rFP, #OFF_FP_SHADOWFRAME - mov r3, rSELF - bl MterpConstMethodType @ (index, tgt_reg, shadow_frame, self) - PREFETCH_INST 2 @ load rINST - cmp r0, #0 @ fail? - bne MterpPossibleException @ let reference interpreter deal with it. - ADVANCE 2 @ advance rPC - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - .balign 128 - - .type artMterpAsmInstructionEnd, #object - .hidden artMterpAsmInstructionEnd - .global artMterpAsmInstructionEnd -artMterpAsmInstructionEnd: - -/* - * Convert the float in r0 to a long in r0/r1. - * - * We have to clip values to long min/max per the specification. The - * expected common case is a "reasonable" value that converts directly - * to modest integer. The EABI convert function isn't doing this for us. - */ -f2l_doconv: - ubfx r2, r0, #23, #8 @ grab the exponent - cmp r2, #0xbe @ MININT < x > MAXINT? - bhs f2l_special_cases - b __aeabi_f2lz @ tail call to convert float to long -f2l_special_cases: - cmp r2, #0xff @ NaN or infinity? - beq f2l_maybeNaN -f2l_notNaN: - adds r0, r0, r0 @ sign bit to carry - mov r0, #0xffffffff @ assume maxlong for lsw - mov r1, #0x7fffffff @ assume maxlong for msw - adc r0, r0, #0 - adc r1, r1, #0 @ convert maxlong to minlong if exp negative - bx lr @ return -f2l_maybeNaN: - lsls r3, r0, #9 - beq f2l_notNaN @ if fraction is non-zero, it's a NaN - mov r0, #0 - mov r1, #0 - bx lr @ return 0 for NaN - -/* - * Convert the double in r0/r1 to a long in r0/r1. - * - * We have to clip values to long min/max per the specification. The - * expected common case is a "reasonable" value that converts directly - * to modest integer. The EABI convert function isn't doing this for us. - */ -d2l_doconv: - ubfx r2, r1, #20, #11 @ grab the exponent - movw r3, #0x43e - cmp r2, r3 @ MINLONG < x > MAXLONG? - bhs d2l_special_cases - b __aeabi_d2lz @ tail call to convert double to long -d2l_special_cases: - movw r3, #0x7ff - cmp r2, r3 - beq d2l_maybeNaN @ NaN? -d2l_notNaN: - adds r1, r1, r1 @ sign bit to carry - mov r0, #0xffffffff @ assume maxlong for lsw - mov r1, #0x7fffffff @ assume maxlong for msw - adc r0, r0, #0 - adc r1, r1, #0 @ convert maxlong to minlong if exp negative - bx lr @ return -d2l_maybeNaN: - orrs r3, r0, r1, lsl #12 - beq d2l_notNaN @ if fraction is non-zero, it's a NaN - mov r0, #0 - mov r1, #0 - bx lr @ return 0 for NaN - - .type artMterpAsmAltInstructionStart, #object - .hidden artMterpAsmAltInstructionStart - .global artMterpAsmAltInstructionStart -artMterpAsmAltInstructionStart = .L_ALT_op_nop - .text -/* ------------------------------ */ - .balign 128 -.L_ALT_op_nop: /* 0x00 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_nop - sub lr, lr, #(.L_ALT_op_nop - .L_op_nop) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move: /* 0x01 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_move - sub lr, lr, #(.L_ALT_op_move - .L_op_move) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_from16: /* 0x02 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_move_from16 - sub lr, lr, #(.L_ALT_op_move_from16 - .L_op_move_from16) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_16: /* 0x03 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_move_16 - sub lr, lr, #(.L_ALT_op_move_16 - .L_op_move_16) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_wide: /* 0x04 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_move_wide - sub lr, lr, #(.L_ALT_op_move_wide - .L_op_move_wide) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_wide_from16: /* 0x05 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_move_wide_from16 - sub lr, lr, #(.L_ALT_op_move_wide_from16 - .L_op_move_wide_from16) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_wide_16: /* 0x06 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_move_wide_16 - sub lr, lr, #(.L_ALT_op_move_wide_16 - .L_op_move_wide_16) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_object: /* 0x07 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_move_object - sub lr, lr, #(.L_ALT_op_move_object - .L_op_move_object) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_object_from16: /* 0x08 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_move_object_from16 - sub lr, lr, #(.L_ALT_op_move_object_from16 - .L_op_move_object_from16) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_object_16: /* 0x09 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_move_object_16 - sub lr, lr, #(.L_ALT_op_move_object_16 - .L_op_move_object_16) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_result: /* 0x0a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_move_result - sub lr, lr, #(.L_ALT_op_move_result - .L_op_move_result) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_result_wide: /* 0x0b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_move_result_wide - sub lr, lr, #(.L_ALT_op_move_result_wide - .L_op_move_result_wide) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_result_object: /* 0x0c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_move_result_object - sub lr, lr, #(.L_ALT_op_move_result_object - .L_op_move_result_object) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_exception: /* 0x0d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_move_exception - sub lr, lr, #(.L_ALT_op_move_exception - .L_op_move_exception) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_void: /* 0x0e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_return_void - sub lr, lr, #(.L_ALT_op_return_void - .L_op_return_void) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return: /* 0x0f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_return - sub lr, lr, #(.L_ALT_op_return - .L_op_return) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_wide: /* 0x10 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_return_wide - sub lr, lr, #(.L_ALT_op_return_wide - .L_op_return_wide) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_object: /* 0x11 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_return_object - sub lr, lr, #(.L_ALT_op_return_object - .L_op_return_object) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_4: /* 0x12 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_const_4 - sub lr, lr, #(.L_ALT_op_const_4 - .L_op_const_4) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_16: /* 0x13 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_const_16 - sub lr, lr, #(.L_ALT_op_const_16 - .L_op_const_16) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const: /* 0x14 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_const - sub lr, lr, #(.L_ALT_op_const - .L_op_const) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_high16: /* 0x15 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_const_high16 - sub lr, lr, #(.L_ALT_op_const_high16 - .L_op_const_high16) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide_16: /* 0x16 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_const_wide_16 - sub lr, lr, #(.L_ALT_op_const_wide_16 - .L_op_const_wide_16) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide_32: /* 0x17 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_const_wide_32 - sub lr, lr, #(.L_ALT_op_const_wide_32 - .L_op_const_wide_32) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide: /* 0x18 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_const_wide - sub lr, lr, #(.L_ALT_op_const_wide - .L_op_const_wide) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide_high16: /* 0x19 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_const_wide_high16 - sub lr, lr, #(.L_ALT_op_const_wide_high16 - .L_op_const_wide_high16) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_string: /* 0x1a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_const_string - sub lr, lr, #(.L_ALT_op_const_string - .L_op_const_string) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_string_jumbo: /* 0x1b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_const_string_jumbo - sub lr, lr, #(.L_ALT_op_const_string_jumbo - .L_op_const_string_jumbo) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_class: /* 0x1c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_const_class - sub lr, lr, #(.L_ALT_op_const_class - .L_op_const_class) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_monitor_enter: /* 0x1d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_monitor_enter - sub lr, lr, #(.L_ALT_op_monitor_enter - .L_op_monitor_enter) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_monitor_exit: /* 0x1e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_monitor_exit - sub lr, lr, #(.L_ALT_op_monitor_exit - .L_op_monitor_exit) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_check_cast: /* 0x1f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_check_cast - sub lr, lr, #(.L_ALT_op_check_cast - .L_op_check_cast) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_instance_of: /* 0x20 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_instance_of - sub lr, lr, #(.L_ALT_op_instance_of - .L_op_instance_of) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_array_length: /* 0x21 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_array_length - sub lr, lr, #(.L_ALT_op_array_length - .L_op_array_length) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_new_instance: /* 0x22 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_new_instance - sub lr, lr, #(.L_ALT_op_new_instance - .L_op_new_instance) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_new_array: /* 0x23 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_new_array - sub lr, lr, #(.L_ALT_op_new_array - .L_op_new_array) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_filled_new_array: /* 0x24 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_filled_new_array - sub lr, lr, #(.L_ALT_op_filled_new_array - .L_op_filled_new_array) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_filled_new_array_range: /* 0x25 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_filled_new_array_range - sub lr, lr, #(.L_ALT_op_filled_new_array_range - .L_op_filled_new_array_range) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_fill_array_data: /* 0x26 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_fill_array_data - sub lr, lr, #(.L_ALT_op_fill_array_data - .L_op_fill_array_data) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_throw: /* 0x27 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_throw - sub lr, lr, #(.L_ALT_op_throw - .L_op_throw) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_goto: /* 0x28 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_goto - sub lr, lr, #(.L_ALT_op_goto - .L_op_goto) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_goto_16: /* 0x29 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_goto_16 - sub lr, lr, #(.L_ALT_op_goto_16 - .L_op_goto_16) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_goto_32: /* 0x2a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_goto_32 - sub lr, lr, #(.L_ALT_op_goto_32 - .L_op_goto_32) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_packed_switch: /* 0x2b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_packed_switch - sub lr, lr, #(.L_ALT_op_packed_switch - .L_op_packed_switch) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sparse_switch: /* 0x2c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sparse_switch - sub lr, lr, #(.L_ALT_op_sparse_switch - .L_op_sparse_switch) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpl_float: /* 0x2d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_cmpl_float - sub lr, lr, #(.L_ALT_op_cmpl_float - .L_op_cmpl_float) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpg_float: /* 0x2e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_cmpg_float - sub lr, lr, #(.L_ALT_op_cmpg_float - .L_op_cmpg_float) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpl_double: /* 0x2f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_cmpl_double - sub lr, lr, #(.L_ALT_op_cmpl_double - .L_op_cmpl_double) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpg_double: /* 0x30 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_cmpg_double - sub lr, lr, #(.L_ALT_op_cmpg_double - .L_op_cmpg_double) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmp_long: /* 0x31 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_cmp_long - sub lr, lr, #(.L_ALT_op_cmp_long - .L_op_cmp_long) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_eq: /* 0x32 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_if_eq - sub lr, lr, #(.L_ALT_op_if_eq - .L_op_if_eq) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_ne: /* 0x33 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_if_ne - sub lr, lr, #(.L_ALT_op_if_ne - .L_op_if_ne) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_lt: /* 0x34 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_if_lt - sub lr, lr, #(.L_ALT_op_if_lt - .L_op_if_lt) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_ge: /* 0x35 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_if_ge - sub lr, lr, #(.L_ALT_op_if_ge - .L_op_if_ge) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_gt: /* 0x36 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_if_gt - sub lr, lr, #(.L_ALT_op_if_gt - .L_op_if_gt) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_le: /* 0x37 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_if_le - sub lr, lr, #(.L_ALT_op_if_le - .L_op_if_le) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_eqz: /* 0x38 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_if_eqz - sub lr, lr, #(.L_ALT_op_if_eqz - .L_op_if_eqz) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_nez: /* 0x39 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_if_nez - sub lr, lr, #(.L_ALT_op_if_nez - .L_op_if_nez) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_ltz: /* 0x3a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_if_ltz - sub lr, lr, #(.L_ALT_op_if_ltz - .L_op_if_ltz) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_gez: /* 0x3b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_if_gez - sub lr, lr, #(.L_ALT_op_if_gez - .L_op_if_gez) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_gtz: /* 0x3c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_if_gtz - sub lr, lr, #(.L_ALT_op_if_gtz - .L_op_if_gtz) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_lez: /* 0x3d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_if_lez - sub lr, lr, #(.L_ALT_op_if_lez - .L_op_if_lez) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_3e: /* 0x3e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_unused_3e - sub lr, lr, #(.L_ALT_op_unused_3e - .L_op_unused_3e) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_3f: /* 0x3f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_unused_3f - sub lr, lr, #(.L_ALT_op_unused_3f - .L_op_unused_3f) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_40: /* 0x40 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_unused_40 - sub lr, lr, #(.L_ALT_op_unused_40 - .L_op_unused_40) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_41: /* 0x41 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_unused_41 - sub lr, lr, #(.L_ALT_op_unused_41 - .L_op_unused_41) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_42: /* 0x42 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_unused_42 - sub lr, lr, #(.L_ALT_op_unused_42 - .L_op_unused_42) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_43: /* 0x43 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_unused_43 - sub lr, lr, #(.L_ALT_op_unused_43 - .L_op_unused_43) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget: /* 0x44 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_aget - sub lr, lr, #(.L_ALT_op_aget - .L_op_aget) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_wide: /* 0x45 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_aget_wide - sub lr, lr, #(.L_ALT_op_aget_wide - .L_op_aget_wide) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_object: /* 0x46 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_aget_object - sub lr, lr, #(.L_ALT_op_aget_object - .L_op_aget_object) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_boolean: /* 0x47 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_aget_boolean - sub lr, lr, #(.L_ALT_op_aget_boolean - .L_op_aget_boolean) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_byte: /* 0x48 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_aget_byte - sub lr, lr, #(.L_ALT_op_aget_byte - .L_op_aget_byte) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_char: /* 0x49 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_aget_char - sub lr, lr, #(.L_ALT_op_aget_char - .L_op_aget_char) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_short: /* 0x4a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_aget_short - sub lr, lr, #(.L_ALT_op_aget_short - .L_op_aget_short) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput: /* 0x4b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_aput - sub lr, lr, #(.L_ALT_op_aput - .L_op_aput) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_wide: /* 0x4c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_aput_wide - sub lr, lr, #(.L_ALT_op_aput_wide - .L_op_aput_wide) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_object: /* 0x4d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_aput_object - sub lr, lr, #(.L_ALT_op_aput_object - .L_op_aput_object) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_boolean: /* 0x4e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_aput_boolean - sub lr, lr, #(.L_ALT_op_aput_boolean - .L_op_aput_boolean) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_byte: /* 0x4f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_aput_byte - sub lr, lr, #(.L_ALT_op_aput_byte - .L_op_aput_byte) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_char: /* 0x50 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_aput_char - sub lr, lr, #(.L_ALT_op_aput_char - .L_op_aput_char) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_short: /* 0x51 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_aput_short - sub lr, lr, #(.L_ALT_op_aput_short - .L_op_aput_short) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget: /* 0x52 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iget - sub lr, lr, #(.L_ALT_op_iget - .L_op_iget) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_wide: /* 0x53 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iget_wide - sub lr, lr, #(.L_ALT_op_iget_wide - .L_op_iget_wide) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_object: /* 0x54 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iget_object - sub lr, lr, #(.L_ALT_op_iget_object - .L_op_iget_object) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_boolean: /* 0x55 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iget_boolean - sub lr, lr, #(.L_ALT_op_iget_boolean - .L_op_iget_boolean) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_byte: /* 0x56 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iget_byte - sub lr, lr, #(.L_ALT_op_iget_byte - .L_op_iget_byte) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_char: /* 0x57 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iget_char - sub lr, lr, #(.L_ALT_op_iget_char - .L_op_iget_char) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_short: /* 0x58 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iget_short - sub lr, lr, #(.L_ALT_op_iget_short - .L_op_iget_short) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput: /* 0x59 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iput - sub lr, lr, #(.L_ALT_op_iput - .L_op_iput) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_wide: /* 0x5a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iput_wide - sub lr, lr, #(.L_ALT_op_iput_wide - .L_op_iput_wide) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_object: /* 0x5b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iput_object - sub lr, lr, #(.L_ALT_op_iput_object - .L_op_iput_object) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_boolean: /* 0x5c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iput_boolean - sub lr, lr, #(.L_ALT_op_iput_boolean - .L_op_iput_boolean) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_byte: /* 0x5d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iput_byte - sub lr, lr, #(.L_ALT_op_iput_byte - .L_op_iput_byte) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_char: /* 0x5e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iput_char - sub lr, lr, #(.L_ALT_op_iput_char - .L_op_iput_char) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_short: /* 0x5f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iput_short - sub lr, lr, #(.L_ALT_op_iput_short - .L_op_iput_short) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget: /* 0x60 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sget - sub lr, lr, #(.L_ALT_op_sget - .L_op_sget) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_wide: /* 0x61 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sget_wide - sub lr, lr, #(.L_ALT_op_sget_wide - .L_op_sget_wide) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_object: /* 0x62 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sget_object - sub lr, lr, #(.L_ALT_op_sget_object - .L_op_sget_object) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_boolean: /* 0x63 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sget_boolean - sub lr, lr, #(.L_ALT_op_sget_boolean - .L_op_sget_boolean) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_byte: /* 0x64 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sget_byte - sub lr, lr, #(.L_ALT_op_sget_byte - .L_op_sget_byte) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_char: /* 0x65 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sget_char - sub lr, lr, #(.L_ALT_op_sget_char - .L_op_sget_char) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_short: /* 0x66 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sget_short - sub lr, lr, #(.L_ALT_op_sget_short - .L_op_sget_short) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput: /* 0x67 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sput - sub lr, lr, #(.L_ALT_op_sput - .L_op_sput) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_wide: /* 0x68 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sput_wide - sub lr, lr, #(.L_ALT_op_sput_wide - .L_op_sput_wide) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_object: /* 0x69 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sput_object - sub lr, lr, #(.L_ALT_op_sput_object - .L_op_sput_object) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_boolean: /* 0x6a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sput_boolean - sub lr, lr, #(.L_ALT_op_sput_boolean - .L_op_sput_boolean) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_byte: /* 0x6b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sput_byte - sub lr, lr, #(.L_ALT_op_sput_byte - .L_op_sput_byte) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_char: /* 0x6c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sput_char - sub lr, lr, #(.L_ALT_op_sput_char - .L_op_sput_char) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_short: /* 0x6d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sput_short - sub lr, lr, #(.L_ALT_op_sput_short - .L_op_sput_short) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual: /* 0x6e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_invoke_virtual - sub lr, lr, #(.L_ALT_op_invoke_virtual - .L_op_invoke_virtual) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_super: /* 0x6f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_invoke_super - sub lr, lr, #(.L_ALT_op_invoke_super - .L_op_invoke_super) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_direct: /* 0x70 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_invoke_direct - sub lr, lr, #(.L_ALT_op_invoke_direct - .L_op_invoke_direct) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_static: /* 0x71 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_invoke_static - sub lr, lr, #(.L_ALT_op_invoke_static - .L_op_invoke_static) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_interface: /* 0x72 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_invoke_interface - sub lr, lr, #(.L_ALT_op_invoke_interface - .L_op_invoke_interface) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_void_no_barrier: /* 0x73 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_return_void_no_barrier - sub lr, lr, #(.L_ALT_op_return_void_no_barrier - .L_op_return_void_no_barrier) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual_range: /* 0x74 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_invoke_virtual_range - sub lr, lr, #(.L_ALT_op_invoke_virtual_range - .L_op_invoke_virtual_range) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_super_range: /* 0x75 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_invoke_super_range - sub lr, lr, #(.L_ALT_op_invoke_super_range - .L_op_invoke_super_range) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_direct_range: /* 0x76 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_invoke_direct_range - sub lr, lr, #(.L_ALT_op_invoke_direct_range - .L_op_invoke_direct_range) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_static_range: /* 0x77 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_invoke_static_range - sub lr, lr, #(.L_ALT_op_invoke_static_range - .L_op_invoke_static_range) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_interface_range: /* 0x78 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_invoke_interface_range - sub lr, lr, #(.L_ALT_op_invoke_interface_range - .L_op_invoke_interface_range) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_79: /* 0x79 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_unused_79 - sub lr, lr, #(.L_ALT_op_unused_79 - .L_op_unused_79) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_7a: /* 0x7a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_unused_7a - sub lr, lr, #(.L_ALT_op_unused_7a - .L_op_unused_7a) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_int: /* 0x7b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_neg_int - sub lr, lr, #(.L_ALT_op_neg_int - .L_op_neg_int) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_not_int: /* 0x7c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_not_int - sub lr, lr, #(.L_ALT_op_not_int - .L_op_not_int) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_long: /* 0x7d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_neg_long - sub lr, lr, #(.L_ALT_op_neg_long - .L_op_neg_long) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_not_long: /* 0x7e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_not_long - sub lr, lr, #(.L_ALT_op_not_long - .L_op_not_long) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_float: /* 0x7f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_neg_float - sub lr, lr, #(.L_ALT_op_neg_float - .L_op_neg_float) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_double: /* 0x80 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_neg_double - sub lr, lr, #(.L_ALT_op_neg_double - .L_op_neg_double) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_long: /* 0x81 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_int_to_long - sub lr, lr, #(.L_ALT_op_int_to_long - .L_op_int_to_long) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_float: /* 0x82 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_int_to_float - sub lr, lr, #(.L_ALT_op_int_to_float - .L_op_int_to_float) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_double: /* 0x83 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_int_to_double - sub lr, lr, #(.L_ALT_op_int_to_double - .L_op_int_to_double) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_long_to_int: /* 0x84 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_long_to_int - sub lr, lr, #(.L_ALT_op_long_to_int - .L_op_long_to_int) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_long_to_float: /* 0x85 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_long_to_float - sub lr, lr, #(.L_ALT_op_long_to_float - .L_op_long_to_float) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_long_to_double: /* 0x86 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_long_to_double - sub lr, lr, #(.L_ALT_op_long_to_double - .L_op_long_to_double) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_float_to_int: /* 0x87 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_float_to_int - sub lr, lr, #(.L_ALT_op_float_to_int - .L_op_float_to_int) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_float_to_long: /* 0x88 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_float_to_long - sub lr, lr, #(.L_ALT_op_float_to_long - .L_op_float_to_long) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_float_to_double: /* 0x89 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_float_to_double - sub lr, lr, #(.L_ALT_op_float_to_double - .L_op_float_to_double) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_double_to_int: /* 0x8a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_double_to_int - sub lr, lr, #(.L_ALT_op_double_to_int - .L_op_double_to_int) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_double_to_long: /* 0x8b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_double_to_long - sub lr, lr, #(.L_ALT_op_double_to_long - .L_op_double_to_long) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_double_to_float: /* 0x8c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_double_to_float - sub lr, lr, #(.L_ALT_op_double_to_float - .L_op_double_to_float) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_byte: /* 0x8d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_int_to_byte - sub lr, lr, #(.L_ALT_op_int_to_byte - .L_op_int_to_byte) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_char: /* 0x8e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_int_to_char - sub lr, lr, #(.L_ALT_op_int_to_char - .L_op_int_to_char) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_short: /* 0x8f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_int_to_short - sub lr, lr, #(.L_ALT_op_int_to_short - .L_op_int_to_short) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int: /* 0x90 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_add_int - sub lr, lr, #(.L_ALT_op_add_int - .L_op_add_int) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_int: /* 0x91 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sub_int - sub lr, lr, #(.L_ALT_op_sub_int - .L_op_sub_int) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int: /* 0x92 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_mul_int - sub lr, lr, #(.L_ALT_op_mul_int - .L_op_mul_int) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int: /* 0x93 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_div_int - sub lr, lr, #(.L_ALT_op_div_int - .L_op_div_int) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int: /* 0x94 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_rem_int - sub lr, lr, #(.L_ALT_op_rem_int - .L_op_rem_int) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int: /* 0x95 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_and_int - sub lr, lr, #(.L_ALT_op_and_int - .L_op_and_int) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int: /* 0x96 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_or_int - sub lr, lr, #(.L_ALT_op_or_int - .L_op_or_int) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int: /* 0x97 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_xor_int - sub lr, lr, #(.L_ALT_op_xor_int - .L_op_xor_int) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_int: /* 0x98 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_shl_int - sub lr, lr, #(.L_ALT_op_shl_int - .L_op_shl_int) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_int: /* 0x99 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_shr_int - sub lr, lr, #(.L_ALT_op_shr_int - .L_op_shr_int) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_int: /* 0x9a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_ushr_int - sub lr, lr, #(.L_ALT_op_ushr_int - .L_op_ushr_int) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_long: /* 0x9b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_add_long - sub lr, lr, #(.L_ALT_op_add_long - .L_op_add_long) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_long: /* 0x9c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sub_long - sub lr, lr, #(.L_ALT_op_sub_long - .L_op_sub_long) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_long: /* 0x9d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_mul_long - sub lr, lr, #(.L_ALT_op_mul_long - .L_op_mul_long) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_long: /* 0x9e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_div_long - sub lr, lr, #(.L_ALT_op_div_long - .L_op_div_long) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_long: /* 0x9f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_rem_long - sub lr, lr, #(.L_ALT_op_rem_long - .L_op_rem_long) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_long: /* 0xa0 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_and_long - sub lr, lr, #(.L_ALT_op_and_long - .L_op_and_long) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_long: /* 0xa1 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_or_long - sub lr, lr, #(.L_ALT_op_or_long - .L_op_or_long) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_long: /* 0xa2 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_xor_long - sub lr, lr, #(.L_ALT_op_xor_long - .L_op_xor_long) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_long: /* 0xa3 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_shl_long - sub lr, lr, #(.L_ALT_op_shl_long - .L_op_shl_long) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_long: /* 0xa4 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_shr_long - sub lr, lr, #(.L_ALT_op_shr_long - .L_op_shr_long) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_long: /* 0xa5 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_ushr_long - sub lr, lr, #(.L_ALT_op_ushr_long - .L_op_ushr_long) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_float: /* 0xa6 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_add_float - sub lr, lr, #(.L_ALT_op_add_float - .L_op_add_float) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_float: /* 0xa7 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sub_float - sub lr, lr, #(.L_ALT_op_sub_float - .L_op_sub_float) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_float: /* 0xa8 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_mul_float - sub lr, lr, #(.L_ALT_op_mul_float - .L_op_mul_float) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_float: /* 0xa9 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_div_float - sub lr, lr, #(.L_ALT_op_div_float - .L_op_div_float) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_float: /* 0xaa */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_rem_float - sub lr, lr, #(.L_ALT_op_rem_float - .L_op_rem_float) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_double: /* 0xab */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_add_double - sub lr, lr, #(.L_ALT_op_add_double - .L_op_add_double) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_double: /* 0xac */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sub_double - sub lr, lr, #(.L_ALT_op_sub_double - .L_op_sub_double) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_double: /* 0xad */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_mul_double - sub lr, lr, #(.L_ALT_op_mul_double - .L_op_mul_double) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_double: /* 0xae */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_div_double - sub lr, lr, #(.L_ALT_op_div_double - .L_op_div_double) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_double: /* 0xaf */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_rem_double - sub lr, lr, #(.L_ALT_op_rem_double - .L_op_rem_double) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int_2addr: /* 0xb0 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_add_int_2addr - sub lr, lr, #(.L_ALT_op_add_int_2addr - .L_op_add_int_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_int_2addr: /* 0xb1 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sub_int_2addr - sub lr, lr, #(.L_ALT_op_sub_int_2addr - .L_op_sub_int_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int_2addr: /* 0xb2 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_mul_int_2addr - sub lr, lr, #(.L_ALT_op_mul_int_2addr - .L_op_mul_int_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int_2addr: /* 0xb3 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_div_int_2addr - sub lr, lr, #(.L_ALT_op_div_int_2addr - .L_op_div_int_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int_2addr: /* 0xb4 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_rem_int_2addr - sub lr, lr, #(.L_ALT_op_rem_int_2addr - .L_op_rem_int_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int_2addr: /* 0xb5 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_and_int_2addr - sub lr, lr, #(.L_ALT_op_and_int_2addr - .L_op_and_int_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int_2addr: /* 0xb6 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_or_int_2addr - sub lr, lr, #(.L_ALT_op_or_int_2addr - .L_op_or_int_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int_2addr: /* 0xb7 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_xor_int_2addr - sub lr, lr, #(.L_ALT_op_xor_int_2addr - .L_op_xor_int_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_int_2addr: /* 0xb8 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_shl_int_2addr - sub lr, lr, #(.L_ALT_op_shl_int_2addr - .L_op_shl_int_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_int_2addr: /* 0xb9 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_shr_int_2addr - sub lr, lr, #(.L_ALT_op_shr_int_2addr - .L_op_shr_int_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_int_2addr: /* 0xba */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_ushr_int_2addr - sub lr, lr, #(.L_ALT_op_ushr_int_2addr - .L_op_ushr_int_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_long_2addr: /* 0xbb */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_add_long_2addr - sub lr, lr, #(.L_ALT_op_add_long_2addr - .L_op_add_long_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_long_2addr: /* 0xbc */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sub_long_2addr - sub lr, lr, #(.L_ALT_op_sub_long_2addr - .L_op_sub_long_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_long_2addr: /* 0xbd */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_mul_long_2addr - sub lr, lr, #(.L_ALT_op_mul_long_2addr - .L_op_mul_long_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_long_2addr: /* 0xbe */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_div_long_2addr - sub lr, lr, #(.L_ALT_op_div_long_2addr - .L_op_div_long_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_long_2addr: /* 0xbf */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_rem_long_2addr - sub lr, lr, #(.L_ALT_op_rem_long_2addr - .L_op_rem_long_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_long_2addr: /* 0xc0 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_and_long_2addr - sub lr, lr, #(.L_ALT_op_and_long_2addr - .L_op_and_long_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_long_2addr: /* 0xc1 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_or_long_2addr - sub lr, lr, #(.L_ALT_op_or_long_2addr - .L_op_or_long_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_long_2addr: /* 0xc2 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_xor_long_2addr - sub lr, lr, #(.L_ALT_op_xor_long_2addr - .L_op_xor_long_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_long_2addr: /* 0xc3 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_shl_long_2addr - sub lr, lr, #(.L_ALT_op_shl_long_2addr - .L_op_shl_long_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_long_2addr: /* 0xc4 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_shr_long_2addr - sub lr, lr, #(.L_ALT_op_shr_long_2addr - .L_op_shr_long_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_long_2addr: /* 0xc5 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_ushr_long_2addr - sub lr, lr, #(.L_ALT_op_ushr_long_2addr - .L_op_ushr_long_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_float_2addr: /* 0xc6 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_add_float_2addr - sub lr, lr, #(.L_ALT_op_add_float_2addr - .L_op_add_float_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_float_2addr: /* 0xc7 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sub_float_2addr - sub lr, lr, #(.L_ALT_op_sub_float_2addr - .L_op_sub_float_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_float_2addr: /* 0xc8 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_mul_float_2addr - sub lr, lr, #(.L_ALT_op_mul_float_2addr - .L_op_mul_float_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_float_2addr: /* 0xc9 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_div_float_2addr - sub lr, lr, #(.L_ALT_op_div_float_2addr - .L_op_div_float_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_float_2addr: /* 0xca */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_rem_float_2addr - sub lr, lr, #(.L_ALT_op_rem_float_2addr - .L_op_rem_float_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_double_2addr: /* 0xcb */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_add_double_2addr - sub lr, lr, #(.L_ALT_op_add_double_2addr - .L_op_add_double_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_double_2addr: /* 0xcc */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sub_double_2addr - sub lr, lr, #(.L_ALT_op_sub_double_2addr - .L_op_sub_double_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_double_2addr: /* 0xcd */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_mul_double_2addr - sub lr, lr, #(.L_ALT_op_mul_double_2addr - .L_op_mul_double_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_double_2addr: /* 0xce */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_div_double_2addr - sub lr, lr, #(.L_ALT_op_div_double_2addr - .L_op_div_double_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_double_2addr: /* 0xcf */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_rem_double_2addr - sub lr, lr, #(.L_ALT_op_rem_double_2addr - .L_op_rem_double_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int_lit16: /* 0xd0 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_add_int_lit16 - sub lr, lr, #(.L_ALT_op_add_int_lit16 - .L_op_add_int_lit16) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rsub_int: /* 0xd1 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_rsub_int - sub lr, lr, #(.L_ALT_op_rsub_int - .L_op_rsub_int) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int_lit16: /* 0xd2 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_mul_int_lit16 - sub lr, lr, #(.L_ALT_op_mul_int_lit16 - .L_op_mul_int_lit16) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int_lit16: /* 0xd3 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_div_int_lit16 - sub lr, lr, #(.L_ALT_op_div_int_lit16 - .L_op_div_int_lit16) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int_lit16: /* 0xd4 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_rem_int_lit16 - sub lr, lr, #(.L_ALT_op_rem_int_lit16 - .L_op_rem_int_lit16) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int_lit16: /* 0xd5 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_and_int_lit16 - sub lr, lr, #(.L_ALT_op_and_int_lit16 - .L_op_and_int_lit16) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int_lit16: /* 0xd6 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_or_int_lit16 - sub lr, lr, #(.L_ALT_op_or_int_lit16 - .L_op_or_int_lit16) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int_lit16: /* 0xd7 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_xor_int_lit16 - sub lr, lr, #(.L_ALT_op_xor_int_lit16 - .L_op_xor_int_lit16) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int_lit8: /* 0xd8 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_add_int_lit8 - sub lr, lr, #(.L_ALT_op_add_int_lit8 - .L_op_add_int_lit8) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rsub_int_lit8: /* 0xd9 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_rsub_int_lit8 - sub lr, lr, #(.L_ALT_op_rsub_int_lit8 - .L_op_rsub_int_lit8) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int_lit8: /* 0xda */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_mul_int_lit8 - sub lr, lr, #(.L_ALT_op_mul_int_lit8 - .L_op_mul_int_lit8) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int_lit8: /* 0xdb */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_div_int_lit8 - sub lr, lr, #(.L_ALT_op_div_int_lit8 - .L_op_div_int_lit8) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int_lit8: /* 0xdc */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_rem_int_lit8 - sub lr, lr, #(.L_ALT_op_rem_int_lit8 - .L_op_rem_int_lit8) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int_lit8: /* 0xdd */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_and_int_lit8 - sub lr, lr, #(.L_ALT_op_and_int_lit8 - .L_op_and_int_lit8) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int_lit8: /* 0xde */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_or_int_lit8 - sub lr, lr, #(.L_ALT_op_or_int_lit8 - .L_op_or_int_lit8) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int_lit8: /* 0xdf */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_xor_int_lit8 - sub lr, lr, #(.L_ALT_op_xor_int_lit8 - .L_op_xor_int_lit8) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_int_lit8: /* 0xe0 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_shl_int_lit8 - sub lr, lr, #(.L_ALT_op_shl_int_lit8 - .L_op_shl_int_lit8) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_int_lit8: /* 0xe1 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_shr_int_lit8 - sub lr, lr, #(.L_ALT_op_shr_int_lit8 - .L_op_shr_int_lit8) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_int_lit8: /* 0xe2 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_ushr_int_lit8 - sub lr, lr, #(.L_ALT_op_ushr_int_lit8 - .L_op_ushr_int_lit8) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_quick: /* 0xe3 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iget_quick - sub lr, lr, #(.L_ALT_op_iget_quick - .L_op_iget_quick) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_wide_quick: /* 0xe4 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iget_wide_quick - sub lr, lr, #(.L_ALT_op_iget_wide_quick - .L_op_iget_wide_quick) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_object_quick: /* 0xe5 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iget_object_quick - sub lr, lr, #(.L_ALT_op_iget_object_quick - .L_op_iget_object_quick) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_quick: /* 0xe6 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iput_quick - sub lr, lr, #(.L_ALT_op_iput_quick - .L_op_iput_quick) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_wide_quick: /* 0xe7 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iput_wide_quick - sub lr, lr, #(.L_ALT_op_iput_wide_quick - .L_op_iput_wide_quick) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_object_quick: /* 0xe8 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iput_object_quick - sub lr, lr, #(.L_ALT_op_iput_object_quick - .L_op_iput_object_quick) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual_quick: /* 0xe9 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_invoke_virtual_quick - sub lr, lr, #(.L_ALT_op_invoke_virtual_quick - .L_op_invoke_virtual_quick) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual_range_quick: /* 0xea */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_invoke_virtual_range_quick - sub lr, lr, #(.L_ALT_op_invoke_virtual_range_quick - .L_op_invoke_virtual_range_quick) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_boolean_quick: /* 0xeb */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iput_boolean_quick - sub lr, lr, #(.L_ALT_op_iput_boolean_quick - .L_op_iput_boolean_quick) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_byte_quick: /* 0xec */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iput_byte_quick - sub lr, lr, #(.L_ALT_op_iput_byte_quick - .L_op_iput_byte_quick) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_char_quick: /* 0xed */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iput_char_quick - sub lr, lr, #(.L_ALT_op_iput_char_quick - .L_op_iput_char_quick) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_short_quick: /* 0xee */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iput_short_quick - sub lr, lr, #(.L_ALT_op_iput_short_quick - .L_op_iput_short_quick) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_boolean_quick: /* 0xef */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iget_boolean_quick - sub lr, lr, #(.L_ALT_op_iget_boolean_quick - .L_op_iget_boolean_quick) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_byte_quick: /* 0xf0 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iget_byte_quick - sub lr, lr, #(.L_ALT_op_iget_byte_quick - .L_op_iget_byte_quick) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_char_quick: /* 0xf1 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iget_char_quick - sub lr, lr, #(.L_ALT_op_iget_char_quick - .L_op_iget_char_quick) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_short_quick: /* 0xf2 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iget_short_quick - sub lr, lr, #(.L_ALT_op_iget_short_quick - .L_op_iget_short_quick) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f3: /* 0xf3 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_unused_f3 - sub lr, lr, #(.L_ALT_op_unused_f3 - .L_op_unused_f3) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f4: /* 0xf4 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_unused_f4 - sub lr, lr, #(.L_ALT_op_unused_f4 - .L_op_unused_f4) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f5: /* 0xf5 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_unused_f5 - sub lr, lr, #(.L_ALT_op_unused_f5 - .L_op_unused_f5) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f6: /* 0xf6 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_unused_f6 - sub lr, lr, #(.L_ALT_op_unused_f6 - .L_op_unused_f6) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f7: /* 0xf7 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_unused_f7 - sub lr, lr, #(.L_ALT_op_unused_f7 - .L_op_unused_f7) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f8: /* 0xf8 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_unused_f8 - sub lr, lr, #(.L_ALT_op_unused_f8 - .L_op_unused_f8) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f9: /* 0xf9 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_unused_f9 - sub lr, lr, #(.L_ALT_op_unused_f9 - .L_op_unused_f9) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_polymorphic: /* 0xfa */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_invoke_polymorphic - sub lr, lr, #(.L_ALT_op_invoke_polymorphic - .L_op_invoke_polymorphic) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_polymorphic_range: /* 0xfb */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_invoke_polymorphic_range - sub lr, lr, #(.L_ALT_op_invoke_polymorphic_range - .L_op_invoke_polymorphic_range) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_custom: /* 0xfc */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_invoke_custom - sub lr, lr, #(.L_ALT_op_invoke_custom - .L_op_invoke_custom) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_custom_range: /* 0xfd */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_invoke_custom_range - sub lr, lr, #(.L_ALT_op_invoke_custom_range - .L_op_invoke_custom_range) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_method_handle: /* 0xfe */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_const_method_handle - sub lr, lr, #(.L_ALT_op_const_method_handle - .L_op_const_method_handle) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_method_type: /* 0xff */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_const_method_type - sub lr, lr, #(.L_ALT_op_const_method_type - .L_op_const_method_type) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - - .balign 128 - - .type artMterpAsmAltInstructionEnd, #object - .hidden artMterpAsmAltInstructionEnd - .global artMterpAsmAltInstructionEnd -artMterpAsmAltInstructionEnd: - -/* - * =========================================================================== - * Common subroutines and data - * =========================================================================== - */ - - .text - .align 2 - -/* - * We've detected a condition that will result in an exception, but the exception - * has not yet been thrown. Just bail out to the reference interpreter to deal with it. - * TUNING: for consistency, we may want to just go ahead and handle these here. - */ -common_errDivideByZero: - EXPORT_PC -#if MTERP_LOGGING - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - bl MterpLogDivideByZeroException -#endif - b MterpCommonFallback - -common_errArrayIndex: - EXPORT_PC -#if MTERP_LOGGING - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - bl MterpLogArrayIndexException -#endif - b MterpCommonFallback - -common_errNegativeArraySize: - EXPORT_PC -#if MTERP_LOGGING - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - bl MterpLogNegativeArraySizeException -#endif - b MterpCommonFallback - -common_errNoSuchMethod: - EXPORT_PC -#if MTERP_LOGGING - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - bl MterpLogNoSuchMethodException -#endif - b MterpCommonFallback - -common_errNullObject: - EXPORT_PC -#if MTERP_LOGGING - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - bl MterpLogNullObjectException -#endif - b MterpCommonFallback - -common_exceptionThrown: - EXPORT_PC -#if MTERP_LOGGING - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - bl MterpLogExceptionThrownException -#endif - b MterpCommonFallback - -MterpSuspendFallback: - EXPORT_PC -#if MTERP_LOGGING - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - ldr r2, [rSELF, #THREAD_FLAGS_OFFSET] - bl MterpLogSuspendFallback -#endif - b MterpCommonFallback - -/* - * If we're here, something is out of the ordinary. If there is a pending - * exception, handle it. Otherwise, roll back and retry with the reference - * interpreter. - */ -MterpPossibleException: - ldr r0, [rSELF, #THREAD_EXCEPTION_OFFSET] - cmp r0, #0 @ Exception pending? - beq MterpFallback @ If not, fall back to reference interpreter. - /* intentional fallthrough - handle pending exception. */ -/* - * On return from a runtime helper routine, we've found a pending exception. - * Can we handle it here - or need to bail out to caller? - * - */ -MterpException: - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - bl MterpHandleException @ (self, shadow_frame) - cmp r0, #0 - beq MterpExceptionReturn @ no local catch, back to caller. - ldr r0, [rFP, #OFF_FP_DEX_INSTRUCTIONS] - ldr r1, [rFP, #OFF_FP_DEX_PC] - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] - add rPC, r0, r1, lsl #1 @ generate new dex_pc_ptr - /* Do we need to switch interpreters? */ - bl MterpShouldSwitchInterpreters - cmp r0, #0 - bne MterpFallback - /* resume execution at catch block */ - EXPORT_PC - FETCH_INST - GET_INST_OPCODE ip - GOTO_OPCODE ip - /* NOTE: no fallthrough */ - -/* - * Common handling for branches with support for Jit profiling. - * On entry: - * rINST <= signed offset - * rPROFILE <= signed hotness countdown (expanded to 32 bits) - * condition bits <= set to establish sign of offset (use "NoFlags" entry if not) - * - * We have quite a few different cases for branch profiling, OSR detection and - * suspend check support here. - * - * Taken backward branches: - * If profiling active, do hotness countdown and report if we hit zero. - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * Is there a pending suspend request? If so, suspend. - * - * Taken forward branches and not-taken backward branches: - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * - * Our most common case is expected to be a taken backward branch with active jit profiling, - * but no full OSR check and no pending suspend request. - * Next most common case is not-taken branch with no full OSR check. - * - */ -MterpCommonTakenBranchNoFlags: - cmp rINST, #0 -MterpCommonTakenBranch: - bgt .L_forward_branch @ don't add forward branches to hotness -/* - * We need to subtract 1 from positive values and we should not see 0 here, - * so we may use the result of the comparison with -1. - */ -#if JIT_CHECK_OSR != -1 -# error "JIT_CHECK_OSR must be -1." -#endif - cmp rPROFILE, #JIT_CHECK_OSR - beq .L_osr_check - subsgt rPROFILE, #1 - beq .L_add_batch @ counted down to zero - report -.L_resume_backward_branch: - ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] - REFRESH_IBASE - add r2, rINST, rINST @ r2<- byte offset - FETCH_ADVANCE_INST_RB r2 @ update rPC, load rINST - ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - bne .L_suspend_request_pending - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -.L_suspend_request_pending: - EXPORT_PC - mov r0, rSELF - bl MterpSuspendCheck @ (self) - cmp r0, #0 - bne MterpFallback - REFRESH_IBASE @ might have changed during suspend - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -.L_no_count_backwards: - cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? - bne .L_resume_backward_branch -.L_osr_check: - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rINST - EXPORT_PC - bl MterpMaybeDoOnStackReplacement @ (self, shadow_frame, offset) - cmp r0, #0 - bne MterpOnStackReplacement - b .L_resume_backward_branch - -.L_forward_branch: - cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? - beq .L_check_osr_forward -.L_resume_forward_branch: - add r2, rINST, rINST @ r2<- byte offset - FETCH_ADVANCE_INST_RB r2 @ update rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -.L_check_osr_forward: - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rINST - EXPORT_PC - bl MterpMaybeDoOnStackReplacement @ (self, shadow_frame, offset) - cmp r0, #0 - bne MterpOnStackReplacement - b .L_resume_forward_branch - -.L_add_batch: - add r1, rFP, #OFF_FP_SHADOWFRAME - strh rPROFILE, [r1, #SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET] - ldr r0, [rFP, #OFF_FP_METHOD] - mov r2, rSELF - bl MterpAddHotnessBatch @ (method, shadow_frame, self) - mov rPROFILE, r0 @ restore new hotness countdown to rPROFILE - b .L_no_count_backwards - -/* - * Entered from the conditional branch handlers when OSR check request active on - * not-taken path. All Dalvik not-taken conditional branch offsets are 2. - */ -.L_check_not_taken_osr: - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, #2 - EXPORT_PC - bl MterpMaybeDoOnStackReplacement @ (self, shadow_frame, offset) - cmp r0, #0 - bne MterpOnStackReplacement - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* - * On-stack replacement has happened, and now we've returned from the compiled method. - */ -MterpOnStackReplacement: -#if MTERP_LOGGING - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rINST - bl MterpLogOSR -#endif - mov r0, #1 @ Signal normal return - b MterpDone - -/* - * Bail out to reference interpreter. - */ -MterpFallback: - EXPORT_PC -#if MTERP_LOGGING - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - bl MterpLogFallback -#endif -MterpCommonFallback: - mov r0, #0 @ signal retry with reference interpreter. - b MterpDone - -/* - * We pushed some registers on the stack in ExecuteMterpImpl, then saved - * SP and LR. Here we restore SP, restore the registers, and then restore - * LR to PC. - * - * On entry: - * uint32_t* rFP (should still be live, pointer to base of vregs) - */ -MterpExceptionReturn: - mov r0, #1 @ signal return to caller. - b MterpDone -MterpReturn: - ldr r2, [rFP, #OFF_FP_RESULT_REGISTER] - str r0, [r2] - str r1, [r2, #4] - mov r0, #1 @ signal return to caller. -MterpDone: -/* - * At this point, we expect rPROFILE to be non-zero. If negative, hotness is disabled or we're - * checking for OSR. If greater than zero, we might have unreported hotness to register - * (the difference between the ending rPROFILE and the cached hotness counter). rPROFILE - * should only reach zero immediately after a hotness decrement, and is then reset to either - * a negative special state or the new non-zero countdown value. - */ - cmp rPROFILE, #0 - bgt MterpProfileActive @ if > 0, we may have some counts to report. - ldmfd sp!, {r3-r10,fp,pc} @ restore 10 regs and return - -MterpProfileActive: - mov rINST, r0 @ stash return value - /* Report cached hotness counts */ - ldr r0, [rFP, #OFF_FP_METHOD] - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rSELF - strh rPROFILE, [r1, #SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET] - bl MterpAddHotnessBatch @ (method, shadow_frame, self) - mov r0, rINST @ restore return value - ldmfd sp!, {r3-r10,fp,pc} @ restore 10 regs and return - - END ExecuteMterpImpl - diff --git a/runtime/interpreter/mterp/out/mterp_arm64.S b/runtime/interpreter/mterp/out/mterp_arm64.S deleted file mode 100644 index 24a2252d94..0000000000 --- a/runtime/interpreter/mterp/out/mterp_arm64.S +++ /dev/null @@ -1,10644 +0,0 @@ -/* DO NOT EDIT: This file was generated by gen-mterp.py. */ -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - Art assembly interpreter notes: - - First validate assembly code by implementing ExecuteXXXImpl() style body (doesn't - handle invoke, allows higher-level code to create frame & shadow frame. - - Once that's working, support direct entry code & eliminate shadow frame (and - excess locals allocation. - - Some (hopefully) temporary ugliness. We'll treat xFP as pointing to the - base of the vreg array within the shadow frame. Access the other fields, - dex_pc_, method_ and number_of_vregs_ via negative offsets. For now, we'll continue - the shadow frame mechanism of double-storing object references - via xFP & - number_of_vregs_. - - */ - -/* -ARM64 Runtime register usage conventions. - - r0 : w0 is 32-bit return register and x0 is 64-bit. - r0-r7 : Argument registers. - r8-r15 : Caller save registers (used as temporary registers). - r16-r17: Also known as ip0-ip1, respectively. Used as scratch registers by - the linker, by the trampolines and other stubs (the backend uses - these as temporary registers). - r18 : Caller save register (used as temporary register). - r19 : Pointer to thread-local storage. - r20-r29: Callee save registers. - r30 : (lr) is reserved (the link register). - rsp : (sp) is reserved (the stack pointer). - rzr : (zr) is reserved (the zero register). - - Floating-point registers - v0-v31 - - v0 : s0 is return register for singles (32-bit) and d0 for doubles (64-bit). - This is analogous to the C/C++ (hard-float) calling convention. - v0-v7 : Floating-point argument registers in both Dalvik and C/C++ conventions. - Also used as temporary and codegen scratch registers. - - v0-v7 and v16-v31 : trashed across C calls. - v8-v15 : bottom 64-bits preserved across C calls (d8-d15 are preserved). - - v16-v31: Used as codegen temp/scratch. - v8-v15 : Can be used for promotion. - - Must maintain 16-byte stack alignment. - -Mterp notes: - -The following registers have fixed assignments: - - reg nick purpose - x20 xPC interpreted program counter, used for fetching instructions - x21 xFP interpreted frame pointer, used for accessing locals and args - x22 xSELF self (Thread) pointer - x23 xINST first 16-bit code unit of current instruction - x24 xIBASE interpreted instruction base pointer, used for computed goto - x25 xREFS base of object references in shadow frame (ideally, we'll get rid of this later). - x26 wPROFILE jit profile hotness countdown - x16 ip scratch reg - x17 ip2 scratch reg (used by macros) - -Macros are provided for common operations. They MUST NOT alter unspecified registers or condition -codes. -*/ - -/* - * This is a #include, not a %include, because we want the C pre-processor - * to expand the macros into assembler assignment statements. - */ -#include "asm_support.h" -#include "interpreter/cfi_asm_support.h" - -#define MTERP_PROFILE_BRANCHES 1 -#define MTERP_LOGGING 0 - -/* During bringup, we'll use the shadow frame model instead of xFP */ -/* single-purpose registers, given names for clarity */ -#define xPC x20 -#define CFI_DEX 20 // DWARF register number of the register holding dex-pc (xPC). -#define CFI_TMP 0 // DWARF register number of the first argument register (r0). -#define xFP x21 -#define xSELF x22 -#define xINST x23 -#define wINST w23 -#define xIBASE x24 -#define xREFS x25 -#define wPROFILE w26 -#define xPROFILE x26 -#define ip x16 -#define ip2 x17 - -/* - * Instead of holding a pointer to the shadow frame, we keep xFP at the base of the vregs. So, - * to access other shadow frame fields, we need to use a backwards offset. Define those here. - */ -#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) -#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) -#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) -#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) -#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) -#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) -#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) -#define OFF_FP_DEX_INSTRUCTIONS OFF_FP(SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET) -#define OFF_FP_SHADOWFRAME OFF_FP(0) - -/* - * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must - * be done *before* something throws. - * - * It's okay to do this more than once. - * - * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped - * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction - * offset into the code_items_[] array. For effiency, we will "export" the - * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC - * to convert to a dex pc when needed. - */ -.macro EXPORT_PC - str xPC, [xFP, #OFF_FP_DEX_PC_PTR] -.endm - -/* - * Fetch the next instruction from xPC into wINST. Does not advance xPC. - */ -.macro FETCH_INST - ldrh wINST, [xPC] -.endm - -/* - * Fetch the next instruction from the specified offset. Advances xPC - * to point to the next instruction. "_count" is in 16-bit code units. - * - * Because of the limited size of immediate constants on ARM, this is only - * suitable for small forward movements (i.e. don't try to implement "goto" - * with this). - * - * This must come AFTER anything that can throw an exception, or the - * exception catch may miss. (This also implies that it must come after - * EXPORT_PC.) - */ -.macro FETCH_ADVANCE_INST count - ldrh wINST, [xPC, #((\count)*2)]! -.endm - -/* - * The operation performed here is similar to FETCH_ADVANCE_INST, except the - * src and dest registers are parameterized (not hard-wired to xPC and xINST). - */ -.macro PREFETCH_ADVANCE_INST dreg, sreg, count - ldrh \dreg, [\sreg, #((\count)*2)]! -.endm - -/* - * Similar to FETCH_ADVANCE_INST, but does not update xPC. Used to load - * xINST ahead of possible exception point. Be sure to manually advance xPC - * later. - */ -.macro PREFETCH_INST count - ldrh wINST, [xPC, #((\count)*2)] -.endm - -/* Advance xPC by some number of code units. */ -.macro ADVANCE count - add xPC, xPC, #((\count)*2) -.endm - -/* - * Fetch the next instruction from an offset specified by _reg and advance xPC. - * xPC to point to the next instruction. "_reg" must specify the distance - * in bytes, *not* 16-bit code units, and may be a signed value. Must not set flags. - * - */ -.macro FETCH_ADVANCE_INST_RB reg - add xPC, xPC, \reg, sxtw - ldrh wINST, [xPC] -.endm - -/* - * Fetch a half-word code unit from an offset past the current PC. The - * "_count" value is in 16-bit code units. Does not advance xPC. - * - * The "_S" variant works the same but treats the value as signed. - */ -.macro FETCH reg, count - ldrh \reg, [xPC, #((\count)*2)] -.endm - -.macro FETCH_S reg, count - ldrsh \reg, [xPC, #((\count)*2)] -.endm - -/* - * Fetch one byte from an offset past the current PC. Pass in the same - * "_count" as you would for FETCH, and an additional 0/1 indicating which - * byte of the halfword you want (lo/hi). - */ -.macro FETCH_B reg, count, byte - ldrb \reg, [xPC, #((\count)*2+(\byte))] -.endm - -/* - * Put the instruction's opcode field into the specified register. - */ -.macro GET_INST_OPCODE reg - and \reg, xINST, #255 -.endm - -/* - * Put the prefetched instruction's opcode field into the specified register. - */ -.macro GET_PREFETCHED_OPCODE oreg, ireg - and \oreg, \ireg, #255 -.endm - -/* - * Begin executing the opcode in _reg. Clobbers reg - */ - -.macro GOTO_OPCODE reg - add \reg, xIBASE, \reg, lsl #7 - br \reg -.endm -.macro GOTO_OPCODE_BASE base,reg - add \reg, \base, \reg, lsl #7 - br \reg -.endm - -/* - * Get/set the 32-bit value from a Dalvik register. - */ -.macro GET_VREG reg, vreg - ldr \reg, [xFP, \vreg, uxtw #2] -.endm -.macro SET_VREG reg, vreg - str \reg, [xFP, \vreg, uxtw #2] - str wzr, [xREFS, \vreg, uxtw #2] -.endm -.macro SET_VREG_OBJECT reg, vreg, tmpreg - str \reg, [xFP, \vreg, uxtw #2] - str \reg, [xREFS, \vreg, uxtw #2] -.endm - -/* - * Get/set the 64-bit value from a Dalvik register. - * TUNING: can we do better here? - */ -.macro GET_VREG_WIDE reg, vreg - add ip2, xFP, \vreg, lsl #2 - ldr \reg, [ip2] -.endm -.macro SET_VREG_WIDE reg, vreg - add ip2, xFP, \vreg, lsl #2 - str \reg, [ip2] - add ip2, xREFS, \vreg, lsl #2 - str xzr, [ip2] -.endm - -/* - * Get the 32-bit value from a Dalvik register and sign-extend to 64-bit. - * Used to avoid an extra instruction in int-to-long. - */ -.macro GET_VREG_S reg, vreg - ldrsw \reg, [xFP, \vreg, uxtw #2] -.endm - -/* - * Convert a virtual register index into an address. - */ -.macro VREG_INDEX_TO_ADDR reg, vreg - add \reg, xFP, \vreg, lsl #2 /* WARNING: handle shadow frame vreg zero if store */ -.endm - -/* - * Refresh handler table. - */ -.macro REFRESH_IBASE - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] -.endm - -/* - * Save two registers to the stack. - */ -.macro SAVE_TWO_REGS reg1, reg2, offset - stp \reg1, \reg2, [sp, #(\offset)] - .cfi_rel_offset \reg1, (\offset) - .cfi_rel_offset \reg2, (\offset) + 8 -.endm - -/* - * Restore two registers from the stack. - */ -.macro RESTORE_TWO_REGS reg1, reg2, offset - ldp \reg1, \reg2, [sp, #(\offset)] - .cfi_restore \reg1 - .cfi_restore \reg2 -.endm - -/* - * Increase frame size and save two registers to the bottom of the stack. - */ -.macro SAVE_TWO_REGS_INCREASE_FRAME reg1, reg2, frame_adjustment - stp \reg1, \reg2, [sp, #-(\frame_adjustment)]! - .cfi_adjust_cfa_offset (\frame_adjustment) - .cfi_rel_offset \reg1, 0 - .cfi_rel_offset \reg2, 8 -.endm - -/* - * Restore two registers from the bottom of the stack and decrease frame size. - */ -.macro RESTORE_TWO_REGS_DECREASE_FRAME reg1, reg2, frame_adjustment - ldp \reg1, \reg2, [sp], #(\frame_adjustment) - .cfi_restore \reg1 - .cfi_restore \reg2 - .cfi_adjust_cfa_offset -(\frame_adjustment) -.endm - -/* - * cfi support macros. - */ -.macro ENTRY name - .type \name, #function - .hidden \name // Hide this as a global symbol, so we do not incur plt calls. - .global \name - /* Cache alignment for function entry */ - .balign 16 -\name: - .cfi_startproc -.endm - -.macro END name - .cfi_endproc - .size \name, .-\name -.endm - -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - .text - -/* - * Interpreter entry point. - * On entry: - * x0 Thread* self/ - * x1 insns_ - * x2 ShadowFrame - * x3 JValue* result_register - * - */ -ENTRY ExecuteMterpImpl - SAVE_TWO_REGS_INCREASE_FRAME xPROFILE, x27, 80 - SAVE_TWO_REGS xIBASE, xREFS, 16 - SAVE_TWO_REGS xSELF, xINST, 32 - SAVE_TWO_REGS xPC, xFP, 48 - SAVE_TWO_REGS fp, lr, 64 - add fp, sp, #64 - - /* Remember the return register */ - str x3, [x2, #SHADOWFRAME_RESULT_REGISTER_OFFSET] - - /* Remember the dex instruction pointer */ - str x1, [x2, #SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET] - - /* set up "named" registers */ - mov xSELF, x0 - ldr w0, [x2, #SHADOWFRAME_NUMBER_OF_VREGS_OFFSET] - add xFP, x2, #SHADOWFRAME_VREGS_OFFSET // point to vregs. - add xREFS, xFP, w0, lsl #2 // point to reference array in shadow frame - ldr w0, [x2, #SHADOWFRAME_DEX_PC_OFFSET] // Get starting dex_pc. - add xPC, x1, w0, lsl #1 // Create direct pointer to 1st dex opcode - CFI_DEFINE_DEX_PC_WITH_OFFSET(CFI_TMP, CFI_DEX, 0) - EXPORT_PC - - /* Starting ibase */ - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] - - /* Set up for backwards branches & osr profiling */ - ldr x0, [xFP, #OFF_FP_METHOD] - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xSELF - bl MterpSetUpHotnessCountdown - mov wPROFILE, w0 // Starting hotness countdown to xPROFILE - - /* start executing the instruction at rPC */ - FETCH_INST // load wINST from rPC - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - /* NOTE: no fallthrough */ - - .type artMterpAsmInstructionStart, #object - .hidden artMterpAsmInstructionStart - .global artMterpAsmInstructionStart -artMterpAsmInstructionStart = .L_op_nop - .text - -/* ------------------------------ */ - .balign 128 -.L_op_nop: /* 0x00 */ - FETCH_ADVANCE_INST 1 // advance to next instr, load rINST - GET_INST_OPCODE ip // ip<- opcode from rINST - GOTO_OPCODE ip // execute it - -/* ------------------------------ */ - .balign 128 -.L_op_move: /* 0x01 */ - /* for move, move-object, long-to-int */ - /* op vA, vB */ - lsr w1, wINST, #12 // x1<- B from 15:12 - ubfx w0, wINST, #8, #4 // x0<- A from 11:8 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - GET_VREG w2, w1 // x2<- fp[B] - GET_INST_OPCODE ip // ip<- opcode from wINST - .if 0 - SET_VREG_OBJECT w2, w0 // fp[A]<- x2 - .else - SET_VREG w2, w0 // fp[A]<- x2 - .endif - GOTO_OPCODE ip // execute next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_from16: /* 0x02 */ - /* for: move/from16, move-object/from16 */ - /* op vAA, vBBBB */ - FETCH w1, 1 // r1<- BBBB - lsr w0, wINST, #8 // r0<- AA - FETCH_ADVANCE_INST 2 // advance rPC, load wINST - GET_VREG w2, w1 // r2<- fp[BBBB] - GET_INST_OPCODE ip // extract opcode from wINST - .if 0 - SET_VREG_OBJECT w2, w0 // fp[AA]<- r2 - .else - SET_VREG w2, w0 // fp[AA]<- r2 - .endif - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_16: /* 0x03 */ - /* for: move/16, move-object/16 */ - /* op vAAAA, vBBBB */ - FETCH w1, 2 // w1<- BBBB - FETCH w0, 1 // w0<- AAAA - FETCH_ADVANCE_INST 3 // advance xPC, load xINST - GET_VREG w2, w1 // w2<- fp[BBBB] - GET_INST_OPCODE ip // extract opcode from xINST - .if 0 - SET_VREG_OBJECT w2, w0 // fp[AAAA]<- w2 - .else - SET_VREG w2, w0 // fp[AAAA]<- w2 - .endif - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_wide: /* 0x04 */ - /* move-wide vA, vB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - lsr w3, wINST, #12 // w3<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG_WIDE x3, w3 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG_WIDE x3, w2 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_wide_from16: /* 0x05 */ - /* move-wide/from16 vAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - FETCH w3, 1 // w3<- BBBB - lsr w2, wINST, #8 // w2<- AA - GET_VREG_WIDE x3, w3 - FETCH_ADVANCE_INST 2 // advance rPC, load wINST - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG_WIDE x3, w2 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_wide_16: /* 0x06 */ - /* move-wide/16 vAAAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - FETCH w3, 2 // w3<- BBBB - FETCH w2, 1 // w2<- AAAA - GET_VREG_WIDE x3, w3 - FETCH_ADVANCE_INST 3 // advance rPC, load rINST - SET_VREG_WIDE x3, w2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_object: /* 0x07 */ - /* for move, move-object, long-to-int */ - /* op vA, vB */ - lsr w1, wINST, #12 // x1<- B from 15:12 - ubfx w0, wINST, #8, #4 // x0<- A from 11:8 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - GET_VREG w2, w1 // x2<- fp[B] - GET_INST_OPCODE ip // ip<- opcode from wINST - .if 1 - SET_VREG_OBJECT w2, w0 // fp[A]<- x2 - .else - SET_VREG w2, w0 // fp[A]<- x2 - .endif - GOTO_OPCODE ip // execute next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_object_from16: /* 0x08 */ - /* for: move/from16, move-object/from16 */ - /* op vAA, vBBBB */ - FETCH w1, 1 // r1<- BBBB - lsr w0, wINST, #8 // r0<- AA - FETCH_ADVANCE_INST 2 // advance rPC, load wINST - GET_VREG w2, w1 // r2<- fp[BBBB] - GET_INST_OPCODE ip // extract opcode from wINST - .if 1 - SET_VREG_OBJECT w2, w0 // fp[AA]<- r2 - .else - SET_VREG w2, w0 // fp[AA]<- r2 - .endif - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_object_16: /* 0x09 */ - /* for: move/16, move-object/16 */ - /* op vAAAA, vBBBB */ - FETCH w1, 2 // w1<- BBBB - FETCH w0, 1 // w0<- AAAA - FETCH_ADVANCE_INST 3 // advance xPC, load xINST - GET_VREG w2, w1 // w2<- fp[BBBB] - GET_INST_OPCODE ip // extract opcode from xINST - .if 1 - SET_VREG_OBJECT w2, w0 // fp[AAAA]<- w2 - .else - SET_VREG w2, w0 // fp[AAAA]<- w2 - .endif - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_result: /* 0x0a */ - /* for: move-result, move-result-object */ - /* op vAA */ - lsr w2, wINST, #8 // r2<- AA - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - ldr x0, [xFP, #OFF_FP_RESULT_REGISTER] // get pointer to result JType. - ldr w0, [x0] // r0 <- result.i. - GET_INST_OPCODE ip // extract opcode from wINST - .if 0 - SET_VREG_OBJECT w0, w2, w1 // fp[AA]<- r0 - .else - SET_VREG w0, w2 // fp[AA]<- r0 - .endif - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_result_wide: /* 0x0b */ - /* for: move-result-wide */ - /* op vAA */ - lsr w2, wINST, #8 // r2<- AA - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - ldr x0, [xFP, #OFF_FP_RESULT_REGISTER] // get pointer to result JType. - ldr x0, [x0] // r0 <- result.i. - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG_WIDE x0, x2 // fp[AA]<- r0 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_result_object: /* 0x0c */ - /* for: move-result, move-result-object */ - /* op vAA */ - lsr w2, wINST, #8 // r2<- AA - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - ldr x0, [xFP, #OFF_FP_RESULT_REGISTER] // get pointer to result JType. - ldr w0, [x0] // r0 <- result.i. - GET_INST_OPCODE ip // extract opcode from wINST - .if 1 - SET_VREG_OBJECT w0, w2, w1 // fp[AA]<- r0 - .else - SET_VREG w0, w2 // fp[AA]<- r0 - .endif - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_exception: /* 0x0d */ - /* move-exception vAA */ - lsr w2, wINST, #8 // w2<- AA - ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] - mov x1, #0 // w1<- 0 - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - SET_VREG_OBJECT w3, w2 // fp[AA]<- exception obj - GET_INST_OPCODE ip // extract opcode from rINST - str x1, [xSELF, #THREAD_EXCEPTION_OFFSET] // clear exception - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_return_void: /* 0x0e */ - .extern MterpThreadFenceForConstructor - bl MterpThreadFenceForConstructor - ldr w7, [xSELF, #THREAD_FLAGS_OFFSET] - mov x0, xSELF - ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - b.ne .Lop_return_void_check -.Lop_return_void_return: - mov x0, #0 - b MterpReturn -.Lop_return_void_check: - bl MterpSuspendCheck // (self) - b .Lop_return_void_return - -/* ------------------------------ */ - .balign 128 -.L_op_return: /* 0x0f */ - /* - * Return a 32-bit value. - * - * for: return, return-object - */ - /* op vAA */ - .extern MterpThreadFenceForConstructor - bl MterpThreadFenceForConstructor - ldr w7, [xSELF, #THREAD_FLAGS_OFFSET] - mov x0, xSELF - ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - b.ne .Lop_return_check -.Lop_return_return: - lsr w2, wINST, #8 // r2<- AA - GET_VREG w0, w2 // r0<- vAA - b MterpReturn -.Lop_return_check: - bl MterpSuspendCheck // (self) - b .Lop_return_return - -/* ------------------------------ */ - .balign 128 -.L_op_return_wide: /* 0x10 */ - /* - * Return a 64-bit value. - */ - /* return-wide vAA */ - /* op vAA */ - .extern MterpThreadFenceForConstructor - bl MterpThreadFenceForConstructor - ldr w7, [xSELF, #THREAD_FLAGS_OFFSET] - mov x0, xSELF - ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - b.ne .Lop_return_wide_check -.Lop_return_wide_return: - lsr w2, wINST, #8 // w2<- AA - GET_VREG_WIDE x0, w2 // x0<- vAA - b MterpReturn -.Lop_return_wide_check: - bl MterpSuspendCheck // (self) - b .Lop_return_wide_return - -/* ------------------------------ */ - .balign 128 -.L_op_return_object: /* 0x11 */ - /* - * Return a 32-bit value. - * - * for: return, return-object - */ - /* op vAA */ - .extern MterpThreadFenceForConstructor - bl MterpThreadFenceForConstructor - ldr w7, [xSELF, #THREAD_FLAGS_OFFSET] - mov x0, xSELF - ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - b.ne .Lop_return_object_check -.Lop_return_object_return: - lsr w2, wINST, #8 // r2<- AA - GET_VREG w0, w2 // r0<- vAA - b MterpReturn -.Lop_return_object_check: - bl MterpSuspendCheck // (self) - b .Lop_return_object_return - -/* ------------------------------ */ - .balign 128 -.L_op_const_4: /* 0x12 */ - /* const/4 vA, #+B */ - sbfx w1, wINST, #12, #4 // w1<- sssssssB - ubfx w0, wINST, #8, #4 // w0<- A - FETCH_ADVANCE_INST 1 // advance xPC, load wINST - GET_INST_OPCODE ip // ip<- opcode from xINST - SET_VREG w1, w0 // fp[A]<- w1 - GOTO_OPCODE ip // execute next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_16: /* 0x13 */ - /* const/16 vAA, #+BBBB */ - FETCH_S w0, 1 // w0<- ssssBBBB (sign-extended) - lsr w3, wINST, #8 // w3<- AA - FETCH_ADVANCE_INST 2 // advance xPC, load wINST - SET_VREG w0, w3 // vAA<- w0 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const: /* 0x14 */ - /* const vAA, #+BBBBbbbb */ - lsr w3, wINST, #8 // w3<- AA - FETCH w0, 1 // w0<- bbbb (low - FETCH w1, 2 // w1<- BBBB (high - FETCH_ADVANCE_INST 3 // advance rPC, load wINST - orr w0, w0, w1, lsl #16 // w0<- BBBBbbbb - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG w0, w3 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_high16: /* 0x15 */ - /* const/high16 vAA, #+BBBB0000 */ - FETCH w0, 1 // r0<- 0000BBBB (zero-extended) - lsr w3, wINST, #8 // r3<- AA - lsl w0, w0, #16 // r0<- BBBB0000 - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - SET_VREG w0, w3 // vAA<- r0 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_wide_16: /* 0x16 */ - /* const-wide/16 vAA, #+BBBB */ - FETCH_S x0, 1 // x0<- ssssssssssssBBBB (sign-extended) - lsr w3, wINST, #8 // w3<- AA - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w3 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_wide_32: /* 0x17 */ - /* const-wide/32 vAA, #+BBBBbbbb */ - FETCH w0, 1 // x0<- 000000000000bbbb (low) - lsr w3, wINST, #8 // w3<- AA - FETCH_S x2, 2 // x2<- ssssssssssssBBBB (high) - FETCH_ADVANCE_INST 3 // advance rPC, load wINST - GET_INST_OPCODE ip // extract opcode from wINST - orr x0, x0, x2, lsl #16 // x0<- ssssssssBBBBbbbb - SET_VREG_WIDE x0, w3 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_wide: /* 0x18 */ - /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ - FETCH w0, 1 // w0<- bbbb (low) - FETCH w1, 2 // w1<- BBBB (low middle) - FETCH w2, 3 // w2<- hhhh (high middle) - FETCH w3, 4 // w3<- HHHH (high) - lsr w4, wINST, #8 // r4<- AA - FETCH_ADVANCE_INST 5 // advance rPC, load wINST - GET_INST_OPCODE ip // extract opcode from wINST - orr w0, w0, w1, lsl #16 // w0<- BBBBbbbb - orr x0, x0, x2, lsl #32 // w0<- hhhhBBBBbbbb - orr x0, x0, x3, lsl #48 // w0<- HHHHhhhhBBBBbbbb - SET_VREG_WIDE x0, w4 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_wide_high16: /* 0x19 */ - /* const-wide/high16 vAA, #+BBBB000000000000 */ - FETCH w0, 1 // w0<- 0000BBBB (zero-extended) - lsr w1, wINST, #8 // w1<- AA - FETCH_ADVANCE_INST 2 // advance rPC, load wINST - lsl x0, x0, #48 - SET_VREG_WIDE x0, w1 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_string: /* 0x1a */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstString - EXPORT_PC - FETCH w0, 1 // w0<- BBBB - lsr w1, wINST, #8 // w1<- AA - add x2, xFP, #OFF_FP_SHADOWFRAME - mov x3, xSELF - bl MterpConstString // (index, tgt_reg, shadow_frame, self) - PREFETCH_INST 2 // load rINST - cbnz w0, MterpPossibleException // let reference interpreter deal with it. - ADVANCE 2 // advance rPC - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_string_jumbo: /* 0x1b */ - /* const/string vAA, String//BBBBBBBB */ - EXPORT_PC - FETCH w0, 1 // w0<- bbbb (low - FETCH w2, 2 // w2<- BBBB (high - lsr w1, wINST, #8 // w1<- AA - orr w0, w0, w2, lsl #16 // w1<- BBBBbbbb - add x2, xFP, #OFF_FP_SHADOWFRAME - mov x3, xSELF - bl MterpConstString // (index, tgt_reg, shadow_frame, self) - PREFETCH_INST 3 // advance rPC - cbnz w0, MterpPossibleException // let reference interpreter deal with it. - ADVANCE 3 // advance rPC - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_class: /* 0x1c */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstClass - EXPORT_PC - FETCH w0, 1 // w0<- BBBB - lsr w1, wINST, #8 // w1<- AA - add x2, xFP, #OFF_FP_SHADOWFRAME - mov x3, xSELF - bl MterpConstClass // (index, tgt_reg, shadow_frame, self) - PREFETCH_INST 2 // load rINST - cbnz w0, MterpPossibleException // let reference interpreter deal with it. - ADVANCE 2 // advance rPC - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_monitor_enter: /* 0x1d */ - /* - * Synchronize on an object. - */ - /* monitor-enter vAA */ - EXPORT_PC - lsr w2, wINST, #8 // w2<- AA - GET_VREG w0, w2 // w0<- vAA (object) - mov x1, xSELF // w1<- self - bl artLockObjectFromCode - cbnz w0, MterpException - FETCH_ADVANCE_INST 1 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_monitor_exit: /* 0x1e */ - /* - * Unlock an object. - * - * Exceptions that occur when unlocking a monitor need to appear as - * if they happened at the following instruction. See the Dalvik - * instruction spec. - */ - /* monitor-exit vAA */ - EXPORT_PC - lsr w2, wINST, #8 // w2<- AA - GET_VREG w0, w2 // w0<- vAA (object) - mov x1, xSELF // w0<- self - bl artUnlockObjectFromCode // w0<- success for unlock(self, obj) - cbnz w0, MterpException - FETCH_ADVANCE_INST 1 // before throw: advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_check_cast: /* 0x1f */ - /* - * Check to see if a cast from one class to another is allowed. - */ - /* check-cast vAA, class//BBBB */ - EXPORT_PC - FETCH w0, 1 // w0<- BBBB - lsr w1, wINST, #8 // w1<- AA - VREG_INDEX_TO_ADDR x1, w1 // w1<- &object - ldr x2, [xFP, #OFF_FP_METHOD] // w2<- method - mov x3, xSELF // w3<- self - bl MterpCheckCast // (index, &obj, method, self) - PREFETCH_INST 2 - cbnz w0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_instance_of: /* 0x20 */ - /* - * Check to see if an object reference is an instance of a class. - * - * Most common situation is a non-null object, being compared against - * an already-resolved class. - */ - /* instance-of vA, vB, class//CCCC */ - EXPORT_PC - FETCH w0, 1 // w0<- CCCC - lsr w1, wINST, #12 // w1<- B - VREG_INDEX_TO_ADDR x1, w1 // w1<- &object - ldr x2, [xFP, #OFF_FP_METHOD] // w2<- method - mov x3, xSELF // w3<- self - bl MterpInstanceOf // (index, &obj, method, self) - ldr x1, [xSELF, #THREAD_EXCEPTION_OFFSET] - ubfx w2, wINST, #8, #4 // w2<- A - PREFETCH_INST 2 - cbnz x1, MterpException - ADVANCE 2 // advance rPC - SET_VREG w0, w2 // vA<- w0 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_array_length: /* 0x21 */ - /* - * Return the length of an array. - */ - lsr w1, wINST, #12 // w1<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG w0, w1 // w0<- vB (object ref) - cbz w0, common_errNullObject // yup, fail - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- array length - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w3, w2 // vB<- length - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_new_instance: /* 0x22 */ - /* - * Create a new instance of a class. - */ - /* new-instance vAA, class//BBBB */ - EXPORT_PC - add x0, xFP, #OFF_FP_SHADOWFRAME - mov x1, xSELF - mov w2, wINST - bl MterpNewInstance // (shadow_frame, self, inst_data) - cbz w0, MterpPossibleException - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_new_array: /* 0x23 */ - /* - * Allocate an array of objects, specified with the array class - * and a count. - * - * The verifier guarantees that this is an array class, so we don't - * check for it here. - */ - /* new-array vA, vB, class//CCCC */ - EXPORT_PC - add x0, xFP, #OFF_FP_SHADOWFRAME - mov x1, xPC - mov w2, wINST - mov x3, xSELF - bl MterpNewArray - cbz w0, MterpPossibleException - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_filled_new_array: /* 0x24 */ - /* - * Create a new array with elements filled from registers. - * - * for: filled-new-array, filled-new-array/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class//CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, type//BBBB */ - .extern MterpFilledNewArray - EXPORT_PC - add x0, xFP, #OFF_FP_SHADOWFRAME - mov x1, xPC - mov x2, xSELF - bl MterpFilledNewArray - cbz w0, MterpPossibleException - FETCH_ADVANCE_INST 3 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_filled_new_array_range: /* 0x25 */ - /* - * Create a new array with elements filled from registers. - * - * for: filled-new-array, filled-new-array/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class//CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, type//BBBB */ - .extern MterpFilledNewArrayRange - EXPORT_PC - add x0, xFP, #OFF_FP_SHADOWFRAME - mov x1, xPC - mov x2, xSELF - bl MterpFilledNewArrayRange - cbz w0, MterpPossibleException - FETCH_ADVANCE_INST 3 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_fill_array_data: /* 0x26 */ - /* fill-array-data vAA, +BBBBBBBB */ - EXPORT_PC - FETCH w0, 1 // x0<- 000000000000bbbb (lo) - FETCH_S x1, 2 // x1<- ssssssssssssBBBB (hi) - lsr w3, wINST, #8 // w3<- AA - orr x1, x0, x1, lsl #16 // x1<- ssssssssBBBBbbbb - GET_VREG w0, w3 // w0<- vAA (array object) - add x1, xPC, x1, lsl #1 // x1<- PC + ssssssssBBBBbbbb*2 (array data off.) - bl MterpFillArrayData // (obj, payload) - cbz w0, MterpPossibleException // exception? - FETCH_ADVANCE_INST 3 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_throw: /* 0x27 */ - /* - * Throw an exception object in the current thread. - */ - /* throw vAA */ - EXPORT_PC - lsr w2, wINST, #8 // r2<- AA - GET_VREG w1, w2 // r1<- vAA (exception object) - cbz w1, common_errNullObject - str x1, [xSELF, #THREAD_EXCEPTION_OFFSET] // thread->exception<- obj - b MterpException - -/* ------------------------------ */ - .balign 128 -.L_op_goto: /* 0x28 */ - /* - * Unconditional branch, 8-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto +AA */ - sbfx wINST, wINST, #8, #8 // wINST<- ssssssAA (sign-extended) - b MterpCommonTakenBranchNoFlags - -/* ------------------------------ */ - .balign 128 -.L_op_goto_16: /* 0x29 */ - /* - * Unconditional branch, 16-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto/16 +AAAA */ - FETCH_S wINST, 1 // wINST<- ssssAAAA (sign-extended) - b MterpCommonTakenBranchNoFlags - -/* ------------------------------ */ - .balign 128 -.L_op_goto_32: /* 0x2a */ - /* - * Unconditional branch, 32-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - * - * Unlike most opcodes, this one is allowed to branch to itself, so - * our "backward branch" test must be "<=0" instead of "<0". Because - * we need the V bit set, we'll use an adds to convert from Dalvik - * offset to byte offset. - */ - /* goto/32 +AAAAAAAA */ - FETCH w0, 1 // w0<- aaaa (lo) - FETCH w1, 2 // w1<- AAAA (hi) - orr wINST, w0, w1, lsl #16 // wINST<- AAAAaaaa - b MterpCommonTakenBranchNoFlags - -/* ------------------------------ */ - .balign 128 -.L_op_packed_switch: /* 0x2b */ - /* - * Handle a packed-switch or sparse-switch instruction. In both cases - * we decode it and hand it off to a helper function. - * - * We don't really expect backward branches in a switch statement, but - * they're perfectly legal, so we check for them here. - * - * for: packed-switch, sparse-switch - */ - /* op vAA, +BBBB */ - FETCH w0, 1 // x0<- 000000000000bbbb (lo) - FETCH_S x1, 2 // x1<- ssssssssssssBBBB (hi) - lsr w3, wINST, #8 // w3<- AA - orr x0, x0, x1, lsl #16 // x0<- ssssssssBBBBbbbb - GET_VREG w1, w3 // w1<- vAA - add x0, xPC, x0, lsl #1 // x0<- PC + ssssssssBBBBbbbb*2 - bl MterpDoPackedSwitch // w0<- code-unit branch offset - sxtw xINST, w0 - b MterpCommonTakenBranchNoFlags - -/* ------------------------------ */ - .balign 128 -.L_op_sparse_switch: /* 0x2c */ - /* - * Handle a packed-switch or sparse-switch instruction. In both cases - * we decode it and hand it off to a helper function. - * - * We don't really expect backward branches in a switch statement, but - * they're perfectly legal, so we check for them here. - * - * for: packed-switch, sparse-switch - */ - /* op vAA, +BBBB */ - FETCH w0, 1 // x0<- 000000000000bbbb (lo) - FETCH_S x1, 2 // x1<- ssssssssssssBBBB (hi) - lsr w3, wINST, #8 // w3<- AA - orr x0, x0, x1, lsl #16 // x0<- ssssssssBBBBbbbb - GET_VREG w1, w3 // w1<- vAA - add x0, xPC, x0, lsl #1 // x0<- PC + ssssssssBBBBbbbb*2 - bl MterpDoSparseSwitch // w0<- code-unit branch offset - sxtw xINST, w0 - b MterpCommonTakenBranchNoFlags - -/* ------------------------------ */ - .balign 128 -.L_op_cmpl_float: /* 0x2d */ - /* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - */ - /* op vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - and w2, w0, #255 // w2<- BB - lsr w3, w0, #8 // w3<- CC - GET_VREG s1, w2 - GET_VREG s2, w3 - fcmp s1, s2 - cset w0, ne - cneg w0, w0, lt - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w4 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_cmpg_float: /* 0x2e */ - /* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - */ - /* op vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - and w2, w0, #255 // w2<- BB - lsr w3, w0, #8 // w3<- CC - GET_VREG s1, w2 - GET_VREG s2, w3 - fcmp s1, s2 - cset w0, ne - cneg w0, w0, cc - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w4 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_cmpl_double: /* 0x2f */ - /* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - */ - /* op vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - and w2, w0, #255 // w2<- BB - lsr w3, w0, #8 // w3<- CC - GET_VREG_WIDE d1, w2 - GET_VREG_WIDE d2, w3 - fcmp d1, d2 - cset w0, ne - cneg w0, w0, lt - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w4 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_cmpg_double: /* 0x30 */ - /* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - */ - /* op vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - and w2, w0, #255 // w2<- BB - lsr w3, w0, #8 // w3<- CC - GET_VREG_WIDE d1, w2 - GET_VREG_WIDE d2, w3 - fcmp d1, d2 - cset w0, ne - cneg w0, w0, cc - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w4 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_cmp_long: /* 0x31 */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - and w2, w0, #255 // w2<- BB - lsr w3, w0, #8 // w3<- CC - GET_VREG_WIDE x1, w2 - GET_VREG_WIDE x2, w3 - cmp x1, x2 - cset w0, ne - cneg w0, w0, lt - FETCH_ADVANCE_INST 2 // advance rPC, load wINST - SET_VREG w0, w4 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_eq: /* 0x32 */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - lsr w1, wINST, #12 // w1<- B - ubfx w0, wINST, #8, #4 // w0<- A - GET_VREG w3, w1 // w3<- vB - GET_VREG w2, w0 // w2<- vA - FETCH_S wINST, 1 // wINST<- branch offset, in code units - cmp w2, w3 // compare (vA, vB) - b.eq MterpCommonTakenBranchNoFlags - cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? - b.eq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_ne: /* 0x33 */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - lsr w1, wINST, #12 // w1<- B - ubfx w0, wINST, #8, #4 // w0<- A - GET_VREG w3, w1 // w3<- vB - GET_VREG w2, w0 // w2<- vA - FETCH_S wINST, 1 // wINST<- branch offset, in code units - cmp w2, w3 // compare (vA, vB) - b.ne MterpCommonTakenBranchNoFlags - cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? - b.eq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_lt: /* 0x34 */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - lsr w1, wINST, #12 // w1<- B - ubfx w0, wINST, #8, #4 // w0<- A - GET_VREG w3, w1 // w3<- vB - GET_VREG w2, w0 // w2<- vA - FETCH_S wINST, 1 // wINST<- branch offset, in code units - cmp w2, w3 // compare (vA, vB) - b.lt MterpCommonTakenBranchNoFlags - cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? - b.eq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_ge: /* 0x35 */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - lsr w1, wINST, #12 // w1<- B - ubfx w0, wINST, #8, #4 // w0<- A - GET_VREG w3, w1 // w3<- vB - GET_VREG w2, w0 // w2<- vA - FETCH_S wINST, 1 // wINST<- branch offset, in code units - cmp w2, w3 // compare (vA, vB) - b.ge MterpCommonTakenBranchNoFlags - cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? - b.eq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_gt: /* 0x36 */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - lsr w1, wINST, #12 // w1<- B - ubfx w0, wINST, #8, #4 // w0<- A - GET_VREG w3, w1 // w3<- vB - GET_VREG w2, w0 // w2<- vA - FETCH_S wINST, 1 // wINST<- branch offset, in code units - cmp w2, w3 // compare (vA, vB) - b.gt MterpCommonTakenBranchNoFlags - cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? - b.eq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_le: /* 0x37 */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - lsr w1, wINST, #12 // w1<- B - ubfx w0, wINST, #8, #4 // w0<- A - GET_VREG w3, w1 // w3<- vB - GET_VREG w2, w0 // w2<- vA - FETCH_S wINST, 1 // wINST<- branch offset, in code units - cmp w2, w3 // compare (vA, vB) - b.le MterpCommonTakenBranchNoFlags - cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? - b.eq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_eqz: /* 0x38 */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - lsr w0, wINST, #8 // w0<- AA - GET_VREG w2, w0 // w2<- vAA - FETCH_S wINST, 1 // w1<- branch offset, in code units - .if 0 - cmp w2, #0 // compare (vA, 0) - .endif - cbz w2, MterpCommonTakenBranchNoFlags - cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? - b.eq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_nez: /* 0x39 */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - lsr w0, wINST, #8 // w0<- AA - GET_VREG w2, w0 // w2<- vAA - FETCH_S wINST, 1 // w1<- branch offset, in code units - .if 0 - cmp w2, #0 // compare (vA, 0) - .endif - cbnz w2, MterpCommonTakenBranchNoFlags - cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? - b.eq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_ltz: /* 0x3a */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - lsr w0, wINST, #8 // w0<- AA - GET_VREG w2, w0 // w2<- vAA - FETCH_S wINST, 1 // w1<- branch offset, in code units - .if 0 - cmp w2, #0 // compare (vA, 0) - .endif - tbnz w2, #31, MterpCommonTakenBranchNoFlags - cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? - b.eq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_gez: /* 0x3b */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - lsr w0, wINST, #8 // w0<- AA - GET_VREG w2, w0 // w2<- vAA - FETCH_S wINST, 1 // w1<- branch offset, in code units - .if 0 - cmp w2, #0 // compare (vA, 0) - .endif - tbz w2, #31, MterpCommonTakenBranchNoFlags - cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? - b.eq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_gtz: /* 0x3c */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - lsr w0, wINST, #8 // w0<- AA - GET_VREG w2, w0 // w2<- vAA - FETCH_S wINST, 1 // w1<- branch offset, in code units - .if 1 - cmp w2, #0 // compare (vA, 0) - .endif - b.gt MterpCommonTakenBranchNoFlags - cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? - b.eq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_lez: /* 0x3d */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - lsr w0, wINST, #8 // w0<- AA - GET_VREG w2, w0 // w2<- vAA - FETCH_S wINST, 1 // w1<- branch offset, in code units - .if 1 - cmp w2, #0 // compare (vA, 0) - .endif - b.le MterpCommonTakenBranchNoFlags - cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? - b.eq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_unused_3e: /* 0x3e */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_3f: /* 0x3f */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_40: /* 0x40 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_41: /* 0x41 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_42: /* 0x42 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_43: /* 0x43 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_aget: /* 0x44 */ - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B w2, 1, 0 // w2<- BB - lsr w9, wINST, #8 // w9<- AA - FETCH_B w3, 1, 1 // w3<- CC - GET_VREG w0, w2 // w0<- vBB (array object) - GET_VREG w1, w3 // w1<- vCC (requested index) - cbz x0, common_errNullObject // bail if null array object. - ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length - add x0, x0, w1, uxtw #2 // w0<- arrayObj + index*width - cmp w1, w3 // compare unsigned index, length - bcs common_errArrayIndex // index >= length, bail - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - ldr w2, [x0, #MIRROR_INT_ARRAY_DATA_OFFSET] // w2<- vBB[vCC] - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w2, w9 // vAA<- w2 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aget_wide: /* 0x45 */ - /* - * Array get, 64 bits. vAA <- vBB[vCC]. - * - */ - /* aget-wide vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - and w2, w0, #255 // w2<- BB - lsr w3, w0, #8 // w3<- CC - GET_VREG w0, w2 // w0<- vBB (array object) - GET_VREG w1, w3 // w1<- vCC (requested index) - cbz w0, common_errNullObject // yes, bail - ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length - add x0, x0, w1, lsl #3 // w0<- arrayObj + index*width - cmp w1, w3 // compare unsigned index, length - bcs common_errArrayIndex // index >= length, bail - FETCH_ADVANCE_INST 2 // advance rPC, load wINST - ldr x2, [x0, #MIRROR_WIDE_ARRAY_DATA_OFFSET] // x2<- vBB[vCC] - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG_WIDE x2, w4 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aget_object: /* 0x46 */ - /* - * Array object get. vAA <- vBB[vCC]. - * - * for: aget-object - */ - /* op vAA, vBB, vCC */ - FETCH_B w2, 1, 0 // w2<- BB - FETCH_B w3, 1, 1 // w3<- CC - EXPORT_PC - GET_VREG w0, w2 // w0<- vBB (array object) - GET_VREG w1, w3 // w1<- vCC (requested index) - bl artAGetObjectFromMterp // (array, index) - ldr x1, [xSELF, #THREAD_EXCEPTION_OFFSET] - lsr w2, wINST, #8 // w9<- AA - PREFETCH_INST 2 - cbnz w1, MterpException - SET_VREG_OBJECT w0, w2 - ADVANCE 2 - GET_INST_OPCODE ip - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aget_boolean: /* 0x47 */ - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B w2, 1, 0 // w2<- BB - lsr w9, wINST, #8 // w9<- AA - FETCH_B w3, 1, 1 // w3<- CC - GET_VREG w0, w2 // w0<- vBB (array object) - GET_VREG w1, w3 // w1<- vCC (requested index) - cbz x0, common_errNullObject // bail if null array object. - ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length - add x0, x0, w1, uxtw #0 // w0<- arrayObj + index*width - cmp w1, w3 // compare unsigned index, length - bcs common_errArrayIndex // index >= length, bail - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - ldrb w2, [x0, #MIRROR_BOOLEAN_ARRAY_DATA_OFFSET] // w2<- vBB[vCC] - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w2, w9 // vAA<- w2 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aget_byte: /* 0x48 */ - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B w2, 1, 0 // w2<- BB - lsr w9, wINST, #8 // w9<- AA - FETCH_B w3, 1, 1 // w3<- CC - GET_VREG w0, w2 // w0<- vBB (array object) - GET_VREG w1, w3 // w1<- vCC (requested index) - cbz x0, common_errNullObject // bail if null array object. - ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length - add x0, x0, w1, uxtw #0 // w0<- arrayObj + index*width - cmp w1, w3 // compare unsigned index, length - bcs common_errArrayIndex // index >= length, bail - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - ldrsb w2, [x0, #MIRROR_BYTE_ARRAY_DATA_OFFSET] // w2<- vBB[vCC] - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w2, w9 // vAA<- w2 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aget_char: /* 0x49 */ - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B w2, 1, 0 // w2<- BB - lsr w9, wINST, #8 // w9<- AA - FETCH_B w3, 1, 1 // w3<- CC - GET_VREG w0, w2 // w0<- vBB (array object) - GET_VREG w1, w3 // w1<- vCC (requested index) - cbz x0, common_errNullObject // bail if null array object. - ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length - add x0, x0, w1, uxtw #1 // w0<- arrayObj + index*width - cmp w1, w3 // compare unsigned index, length - bcs common_errArrayIndex // index >= length, bail - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - ldrh w2, [x0, #MIRROR_CHAR_ARRAY_DATA_OFFSET] // w2<- vBB[vCC] - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w2, w9 // vAA<- w2 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aget_short: /* 0x4a */ - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B w2, 1, 0 // w2<- BB - lsr w9, wINST, #8 // w9<- AA - FETCH_B w3, 1, 1 // w3<- CC - GET_VREG w0, w2 // w0<- vBB (array object) - GET_VREG w1, w3 // w1<- vCC (requested index) - cbz x0, common_errNullObject // bail if null array object. - ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length - add x0, x0, w1, uxtw #1 // w0<- arrayObj + index*width - cmp w1, w3 // compare unsigned index, length - bcs common_errArrayIndex // index >= length, bail - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - ldrsh w2, [x0, #MIRROR_SHORT_ARRAY_DATA_OFFSET] // w2<- vBB[vCC] - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w2, w9 // vAA<- w2 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aput: /* 0x4b */ - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B w2, 1, 0 // w2<- BB - lsr w9, wINST, #8 // w9<- AA - FETCH_B w3, 1, 1 // w3<- CC - GET_VREG w0, w2 // w0<- vBB (array object) - GET_VREG w1, w3 // w1<- vCC (requested index) - cbz w0, common_errNullObject // bail if null - ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length - add x0, x0, w1, lsl #2 // w0<- arrayObj + index*width - cmp w1, w3 // compare unsigned index, length - bcs common_errArrayIndex // index >= length, bail - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_VREG w2, w9 // w2<- vAA - GET_INST_OPCODE ip // extract opcode from rINST - str w2, [x0, #MIRROR_INT_ARRAY_DATA_OFFSET] // vBB[vCC]<- w2 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aput_wide: /* 0x4c */ - /* - * Array put, 64 bits. vBB[vCC] <- vAA. - * - */ - /* aput-wide vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - and w2, w0, #255 // w2<- BB - lsr w3, w0, #8 // w3<- CC - GET_VREG w0, w2 // w0<- vBB (array object) - GET_VREG w1, w3 // w1<- vCC (requested index) - cbz w0, common_errNullObject // bail if null - ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length - add x0, x0, w1, lsl #3 // w0<- arrayObj + index*width - cmp w1, w3 // compare unsigned index, length - bcs common_errArrayIndex // index >= length, bail - GET_VREG_WIDE x1, w4 - FETCH_ADVANCE_INST 2 // advance rPC, load wINST - GET_INST_OPCODE ip // extract opcode from wINST - str x1, [x0, #MIRROR_WIDE_ARRAY_DATA_OFFSET] - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aput_object: /* 0x4d */ - /* - * Store an object into an array. vBB[vCC] <- vAA. - */ - /* op vAA, vBB, vCC */ - EXPORT_PC - add x0, xFP, #OFF_FP_SHADOWFRAME - mov x1, xPC - mov w2, wINST - bl MterpAputObject - cbz w0, MterpPossibleException - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aput_boolean: /* 0x4e */ - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B w2, 1, 0 // w2<- BB - lsr w9, wINST, #8 // w9<- AA - FETCH_B w3, 1, 1 // w3<- CC - GET_VREG w0, w2 // w0<- vBB (array object) - GET_VREG w1, w3 // w1<- vCC (requested index) - cbz w0, common_errNullObject // bail if null - ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length - add x0, x0, w1, lsl #0 // w0<- arrayObj + index*width - cmp w1, w3 // compare unsigned index, length - bcs common_errArrayIndex // index >= length, bail - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_VREG w2, w9 // w2<- vAA - GET_INST_OPCODE ip // extract opcode from rINST - strb w2, [x0, #MIRROR_BOOLEAN_ARRAY_DATA_OFFSET] // vBB[vCC]<- w2 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aput_byte: /* 0x4f */ - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B w2, 1, 0 // w2<- BB - lsr w9, wINST, #8 // w9<- AA - FETCH_B w3, 1, 1 // w3<- CC - GET_VREG w0, w2 // w0<- vBB (array object) - GET_VREG w1, w3 // w1<- vCC (requested index) - cbz w0, common_errNullObject // bail if null - ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length - add x0, x0, w1, lsl #0 // w0<- arrayObj + index*width - cmp w1, w3 // compare unsigned index, length - bcs common_errArrayIndex // index >= length, bail - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_VREG w2, w9 // w2<- vAA - GET_INST_OPCODE ip // extract opcode from rINST - strb w2, [x0, #MIRROR_BYTE_ARRAY_DATA_OFFSET] // vBB[vCC]<- w2 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aput_char: /* 0x50 */ - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B w2, 1, 0 // w2<- BB - lsr w9, wINST, #8 // w9<- AA - FETCH_B w3, 1, 1 // w3<- CC - GET_VREG w0, w2 // w0<- vBB (array object) - GET_VREG w1, w3 // w1<- vCC (requested index) - cbz w0, common_errNullObject // bail if null - ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length - add x0, x0, w1, lsl #1 // w0<- arrayObj + index*width - cmp w1, w3 // compare unsigned index, length - bcs common_errArrayIndex // index >= length, bail - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_VREG w2, w9 // w2<- vAA - GET_INST_OPCODE ip // extract opcode from rINST - strh w2, [x0, #MIRROR_CHAR_ARRAY_DATA_OFFSET] // vBB[vCC]<- w2 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aput_short: /* 0x51 */ - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B w2, 1, 0 // w2<- BB - lsr w9, wINST, #8 // w9<- AA - FETCH_B w3, 1, 1 // w3<- CC - GET_VREG w0, w2 // w0<- vBB (array object) - GET_VREG w1, w3 // w1<- vCC (requested index) - cbz w0, common_errNullObject // bail if null - ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length - add x0, x0, w1, lsl #1 // w0<- arrayObj + index*width - cmp w1, w3 // compare unsigned index, length - bcs common_errArrayIndex // index >= length, bail - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_VREG w2, w9 // w2<- vAA - GET_INST_OPCODE ip // extract opcode from rINST - strh w2, [x0, #MIRROR_SHORT_ARRAY_DATA_OFFSET] // vBB[vCC]<- w2 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iget: /* 0x52 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetU32 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpIGetU32 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iget_wide: /* 0x53 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetU64 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpIGetU64 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iget_object: /* 0x54 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetObj - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpIGetObj - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iget_boolean: /* 0x55 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetU8 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpIGetU8 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iget_byte: /* 0x56 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetI8 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpIGetI8 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iget_char: /* 0x57 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetU16 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpIGetU16 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iget_short: /* 0x58 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetI16 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpIGetI16 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput: /* 0x59 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutU32 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpIPutU32 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_wide: /* 0x5a */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutU64 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpIPutU64 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_object: /* 0x5b */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutObj - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpIPutObj - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_boolean: /* 0x5c */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutU8 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpIPutU8 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_byte: /* 0x5d */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutI8 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpIPutI8 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_char: /* 0x5e */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutU16 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpIPutU16 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_short: /* 0x5f */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutI16 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpIPutI16 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_sget: /* 0x60 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetU32 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpSGetU32 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_sget_wide: /* 0x61 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetU64 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpSGetU64 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_sget_object: /* 0x62 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetObj - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpSGetObj - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_sget_boolean: /* 0x63 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetU8 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpSGetU8 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_sget_byte: /* 0x64 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetI8 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpSGetI8 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_sget_char: /* 0x65 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetU16 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpSGetU16 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_sget_short: /* 0x66 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetI16 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpSGetI16 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_sput: /* 0x67 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutU32 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpSPutU32 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_sput_wide: /* 0x68 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutU64 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpSPutU64 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_sput_object: /* 0x69 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutObj - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpSPutObj - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_sput_boolean: /* 0x6a */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutU8 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpSPutU8 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_sput_byte: /* 0x6b */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutI8 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpSPutI8 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_sput_char: /* 0x6c */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutU16 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpSPutU16 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_sput_short: /* 0x6d */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutI16 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpSPutI16 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual: /* 0x6e */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtual - EXPORT_PC - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - mov x3, xINST - bl MterpInvokeVirtual - cbz w0, MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cbnz w0, MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - - /* - * Handle a virtual method call. - * - * for: invoke-virtual, invoke-virtual/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_super: /* 0x6f */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeSuper - EXPORT_PC - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - mov x3, xINST - bl MterpInvokeSuper - cbz w0, MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cbnz w0, MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - - /* - * Handle a "super" method call. - * - * for: invoke-super, invoke-super/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_direct: /* 0x70 */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeDirect - EXPORT_PC - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - mov x3, xINST - bl MterpInvokeDirect - cbz w0, MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cbnz w0, MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_static: /* 0x71 */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeStatic - EXPORT_PC - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - mov x3, xINST - bl MterpInvokeStatic - cbz w0, MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cbnz w0, MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_interface: /* 0x72 */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeInterface - EXPORT_PC - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - mov x3, xINST - bl MterpInvokeInterface - cbz w0, MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cbnz w0, MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - - /* - * Handle an interface method call. - * - * for: invoke-interface, invoke-interface/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - -/* ------------------------------ */ - .balign 128 -.L_op_return_void_no_barrier: /* 0x73 */ - ldr w7, [xSELF, #THREAD_FLAGS_OFFSET] - mov x0, xSELF - ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - b.ne .Lop_return_void_no_barrier_check -.Lop_return_void_no_barrier_return: - mov x0, #0 - b MterpReturn -.Lop_return_void_no_barrier_check: - bl MterpSuspendCheck // (self) - b .Lop_return_void_no_barrier_return - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual_range: /* 0x74 */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtualRange - EXPORT_PC - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - mov x3, xINST - bl MterpInvokeVirtualRange - cbz w0, MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cbnz w0, MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_super_range: /* 0x75 */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeSuperRange - EXPORT_PC - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - mov x3, xINST - bl MterpInvokeSuperRange - cbz w0, MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cbnz w0, MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_direct_range: /* 0x76 */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeDirectRange - EXPORT_PC - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - mov x3, xINST - bl MterpInvokeDirectRange - cbz w0, MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cbnz w0, MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_static_range: /* 0x77 */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeStaticRange - EXPORT_PC - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - mov x3, xINST - bl MterpInvokeStaticRange - cbz w0, MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cbnz w0, MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_interface_range: /* 0x78 */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeInterfaceRange - EXPORT_PC - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - mov x3, xINST - bl MterpInvokeInterfaceRange - cbz w0, MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cbnz w0, MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - -/* ------------------------------ */ - .balign 128 -.L_op_unused_79: /* 0x79 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_7a: /* 0x7a */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_neg_int: /* 0x7b */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op w0". - * This could be an ARM instruction or a function call. - * - * for: neg-int, not-int, neg-float, int-to-float, float-to-int, - * int-to-byte, int-to-char, int-to-short - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - GET_VREG w0, w3 // w0<- vB - ubfx w9, wINST, #8, #4 // w9<- A - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - sub w0, wzr, w0 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 8-9 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_not_int: /* 0x7c */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op w0". - * This could be an ARM instruction or a function call. - * - * for: neg-int, not-int, neg-float, int-to-float, float-to-int, - * int-to-byte, int-to-char, int-to-short - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - GET_VREG w0, w3 // w0<- vB - ubfx w9, wINST, #8, #4 // w9<- A - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - mvn w0, w0 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 8-9 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_neg_long: /* 0x7d */ - /* - * Generic 64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op x0". - * - * For: neg-long, not-long - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w4, wINST, #8, #4 // w4<- A - GET_VREG_WIDE x0, w3 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - sub x0, xzr, x0 - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG_WIDE x0, w4 - GOTO_OPCODE ip // jump to next instruction - /* 10-11 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_not_long: /* 0x7e */ - /* - * Generic 64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op x0". - * - * For: neg-long, not-long - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w4, wINST, #8, #4 // w4<- A - GET_VREG_WIDE x0, w3 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - mvn x0, x0 - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG_WIDE x0, w4 - GOTO_OPCODE ip // jump to next instruction - /* 10-11 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_neg_float: /* 0x7f */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op w0". - * This could be an ARM instruction or a function call. - * - * for: neg-int, not-int, neg-float, int-to-float, float-to-int, - * int-to-byte, int-to-char, int-to-short - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - GET_VREG w0, w3 // w0<- vB - ubfx w9, wINST, #8, #4 // w9<- A - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - eor w0, w0, #0x80000000 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 8-9 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_neg_double: /* 0x80 */ - /* - * Generic 64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op x0". - * - * For: neg-long, not-long - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w4, wINST, #8, #4 // w4<- A - GET_VREG_WIDE x0, w3 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - eor x0, x0, #0x8000000000000000 - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG_WIDE x0, w4 - GOTO_OPCODE ip // jump to next instruction - /* 10-11 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_long: /* 0x81 */ - /* int-to-long vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w4, wINST, #8, #4 // w4<- A - GET_VREG_S x0, w3 // x0<- sign_extend(fp[B]) - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG_WIDE x0, w4 // fp[A]<- x0 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_float: /* 0x82 */ - /* - * Generic 32bit-to-32bit floating point unary operation. Provide an - * "instr" line that specifies an instruction that performs "s0 = op w0". - * - * For: int-to-float, float-to-int - * TODO: refactor all of the conversions - parameterize width and use same template. - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w4, wINST, #8, #4 // w4<- A - GET_VREG w0, w3 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - scvtf s0, w0 // d0<- op - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG s0, w4 // vA<- d0 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_double: /* 0x83 */ - /* - * Generic 32bit-to-64bit floating point unary operation. Provide an - * "instr" line that specifies an instruction that performs "d0 = op w0". - * - * For: int-to-double, float-to-double, float-to-long - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w4, wINST, #8, #4 // w4<- A - GET_VREG w0, w3 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - scvtf d0, w0 // d0<- op - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG_WIDE d0, w4 // vA<- d0 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_long_to_int: /* 0x84 */ -/* we ignore the high word, making this equivalent to a 32-bit reg move */ - /* for move, move-object, long-to-int */ - /* op vA, vB */ - lsr w1, wINST, #12 // x1<- B from 15:12 - ubfx w0, wINST, #8, #4 // x0<- A from 11:8 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - GET_VREG w2, w1 // x2<- fp[B] - GET_INST_OPCODE ip // ip<- opcode from wINST - .if 0 - SET_VREG_OBJECT w2, w0 // fp[A]<- x2 - .else - SET_VREG w2, w0 // fp[A]<- x2 - .endif - GOTO_OPCODE ip // execute next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_long_to_float: /* 0x85 */ - /* - * Generic 64bit-to-32bit floating point unary operation. Provide an - * "instr" line that specifies an instruction that performs "s0 = op x0". - * - * For: int-to-double, float-to-double, float-to-long - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w4, wINST, #8, #4 // w4<- A - GET_VREG_WIDE x0, w3 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - scvtf s0, x0 // d0<- op - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG s0, w4 // vA<- d0 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_long_to_double: /* 0x86 */ - /* - * Generic 64bit-to-64bit floating point unary operation. Provide an - * "instr" line that specifies an instruction that performs "d0 = op x0". - * - * For: long-to-double, double-to-long - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w4, wINST, #8, #4 // w4<- A - GET_VREG_WIDE x0, w3 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - scvtf d0, x0 // d0<- op - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG_WIDE d0, w4 // vA<- d0 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_float_to_int: /* 0x87 */ - /* - * Generic 32bit-to-32bit floating point unary operation. Provide an - * "instr" line that specifies an instruction that performs "w0 = op s0". - * - * For: int-to-float, float-to-int - * TODO: refactor all of the conversions - parameterize width and use same template. - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w4, wINST, #8, #4 // w4<- A - GET_VREG s0, w3 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - fcvtzs w0, s0 // d0<- op - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG w0, w4 // vA<- d0 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_float_to_long: /* 0x88 */ - /* - * Generic 32bit-to-64bit floating point unary operation. Provide an - * "instr" line that specifies an instruction that performs "x0 = op s0". - * - * For: int-to-double, float-to-double, float-to-long - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w4, wINST, #8, #4 // w4<- A - GET_VREG s0, w3 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - fcvtzs x0, s0 // d0<- op - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG_WIDE x0, w4 // vA<- d0 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_float_to_double: /* 0x89 */ - /* - * Generic 32bit-to-64bit floating point unary operation. Provide an - * "instr" line that specifies an instruction that performs "d0 = op s0". - * - * For: int-to-double, float-to-double, float-to-long - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w4, wINST, #8, #4 // w4<- A - GET_VREG s0, w3 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - fcvt d0, s0 // d0<- op - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG_WIDE d0, w4 // vA<- d0 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_double_to_int: /* 0x8a */ - /* - * Generic 64bit-to-32bit floating point unary operation. Provide an - * "instr" line that specifies an instruction that performs "w0 = op d0". - * - * For: int-to-double, float-to-double, float-to-long - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w4, wINST, #8, #4 // w4<- A - GET_VREG_WIDE d0, w3 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - fcvtzs w0, d0 // d0<- op - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG w0, w4 // vA<- d0 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_double_to_long: /* 0x8b */ - /* - * Generic 64bit-to-64bit floating point unary operation. Provide an - * "instr" line that specifies an instruction that performs "x0 = op d0". - * - * For: long-to-double, double-to-long - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w4, wINST, #8, #4 // w4<- A - GET_VREG_WIDE d0, w3 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - fcvtzs x0, d0 // d0<- op - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG_WIDE x0, w4 // vA<- d0 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_double_to_float: /* 0x8c */ - /* - * Generic 64bit-to-32bit floating point unary operation. Provide an - * "instr" line that specifies an instruction that performs "s0 = op d0". - * - * For: int-to-double, float-to-double, float-to-long - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w4, wINST, #8, #4 // w4<- A - GET_VREG_WIDE d0, w3 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - fcvt s0, d0 // d0<- op - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG s0, w4 // vA<- d0 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_byte: /* 0x8d */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op w0". - * This could be an ARM instruction or a function call. - * - * for: neg-int, not-int, neg-float, int-to-float, float-to-int, - * int-to-byte, int-to-char, int-to-short - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - GET_VREG w0, w3 // w0<- vB - ubfx w9, wINST, #8, #4 // w9<- A - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - sxtb w0, w0 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 8-9 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_char: /* 0x8e */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op w0". - * This could be an ARM instruction or a function call. - * - * for: neg-int, not-int, neg-float, int-to-float, float-to-int, - * int-to-byte, int-to-char, int-to-short - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - GET_VREG w0, w3 // w0<- vB - ubfx w9, wINST, #8, #4 // w9<- A - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - uxth w0, w0 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 8-9 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_short: /* 0x8f */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op w0". - * This could be an ARM instruction or a function call. - * - * for: neg-int, not-int, neg-float, int-to-float, float-to-int, - * int-to-byte, int-to-char, int-to-short - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - GET_VREG w0, w3 // w0<- vB - ubfx w9, wINST, #8, #4 // w9<- A - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - sxth w0, w0 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 8-9 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_add_int: /* 0x90 */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w9, wINST, #8 // w9<- AA - lsr w3, w0, #8 // w3<- CC - and w2, w0, #255 // w2<- BB - GET_VREG w1, w3 // w1<- vCC - GET_VREG w0, w2 // w0<- vBB - .if 0 - cbz w1, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - // optional op; may set condition codes - add w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_sub_int: /* 0x91 */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w9, wINST, #8 // w9<- AA - lsr w3, w0, #8 // w3<- CC - and w2, w0, #255 // w2<- BB - GET_VREG w1, w3 // w1<- vCC - GET_VREG w0, w2 // w0<- vBB - .if 0 - cbz w1, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - // optional op; may set condition codes - sub w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int: /* 0x92 */ -/* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w9, wINST, #8 // w9<- AA - lsr w3, w0, #8 // w3<- CC - and w2, w0, #255 // w2<- BB - GET_VREG w1, w3 // w1<- vCC - GET_VREG w0, w2 // w0<- vBB - .if 0 - cbz w1, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - // optional op; may set condition codes - mul w0, w1, w0 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_div_int: /* 0x93 */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w9, wINST, #8 // w9<- AA - lsr w3, w0, #8 // w3<- CC - and w2, w0, #255 // w2<- BB - GET_VREG w1, w3 // w1<- vCC - GET_VREG w0, w2 // w0<- vBB - .if 1 - cbz w1, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - // optional op; may set condition codes - sdiv w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int: /* 0x94 */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w9, wINST, #8 // w9<- AA - lsr w3, w0, #8 // w3<- CC - and w2, w0, #255 // w2<- BB - GET_VREG w1, w3 // w1<- vCC - GET_VREG w0, w2 // w0<- vBB - .if 1 - cbz w1, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - sdiv w2, w0, w1 // optional op; may set condition codes - msub w0, w2, w1, w0 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_and_int: /* 0x95 */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w9, wINST, #8 // w9<- AA - lsr w3, w0, #8 // w3<- CC - and w2, w0, #255 // w2<- BB - GET_VREG w1, w3 // w1<- vCC - GET_VREG w0, w2 // w0<- vBB - .if 0 - cbz w1, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - // optional op; may set condition codes - and w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_or_int: /* 0x96 */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w9, wINST, #8 // w9<- AA - lsr w3, w0, #8 // w3<- CC - and w2, w0, #255 // w2<- BB - GET_VREG w1, w3 // w1<- vCC - GET_VREG w0, w2 // w0<- vBB - .if 0 - cbz w1, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - // optional op; may set condition codes - orr w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int: /* 0x97 */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w9, wINST, #8 // w9<- AA - lsr w3, w0, #8 // w3<- CC - and w2, w0, #255 // w2<- BB - GET_VREG w1, w3 // w1<- vCC - GET_VREG w0, w2 // w0<- vBB - .if 0 - cbz w1, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - // optional op; may set condition codes - eor w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_shl_int: /* 0x98 */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w9, wINST, #8 // w9<- AA - lsr w3, w0, #8 // w3<- CC - and w2, w0, #255 // w2<- BB - GET_VREG w1, w3 // w1<- vCC - GET_VREG w0, w2 // w0<- vBB - .if 0 - cbz w1, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - // optional op; may set condition codes - lsl w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_shr_int: /* 0x99 */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w9, wINST, #8 // w9<- AA - lsr w3, w0, #8 // w3<- CC - and w2, w0, #255 // w2<- BB - GET_VREG w1, w3 // w1<- vCC - GET_VREG w0, w2 // w0<- vBB - .if 0 - cbz w1, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - // optional op; may set condition codes - asr w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_int: /* 0x9a */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w9, wINST, #8 // w9<- AA - lsr w3, w0, #8 // w3<- CC - and w2, w0, #255 // w2<- BB - GET_VREG w1, w3 // w1<- vCC - GET_VREG w0, w2 // w0<- vBB - .if 0 - cbz w1, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - // optional op; may set condition codes - lsr w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_add_long: /* 0x9b */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = x1 op x2". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than x0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, rem-double - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - lsr w2, w0, #8 // w2<- CC - and w1, w0, #255 // w1<- BB - GET_VREG_WIDE x2, w2 // w2<- vCC - GET_VREG_WIDE x1, w1 // w1<- vBB - .if 0 - cbz x2, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - add x0, x1, x2 // x0<- op, w0-w4 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w4 // vAA<- x0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_sub_long: /* 0x9c */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = x1 op x2". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than x0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, rem-double - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - lsr w2, w0, #8 // w2<- CC - and w1, w0, #255 // w1<- BB - GET_VREG_WIDE x2, w2 // w2<- vCC - GET_VREG_WIDE x1, w1 // w1<- vBB - .if 0 - cbz x2, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - sub x0, x1, x2 // x0<- op, w0-w4 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w4 // vAA<- x0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_mul_long: /* 0x9d */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = x1 op x2". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than x0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, rem-double - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - lsr w2, w0, #8 // w2<- CC - and w1, w0, #255 // w1<- BB - GET_VREG_WIDE x2, w2 // w2<- vCC - GET_VREG_WIDE x1, w1 // w1<- vBB - .if 0 - cbz x2, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - mul x0, x1, x2 // x0<- op, w0-w4 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w4 // vAA<- x0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_div_long: /* 0x9e */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = x1 op x2". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than x0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, rem-double - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - lsr w2, w0, #8 // w2<- CC - and w1, w0, #255 // w1<- BB - GET_VREG_WIDE x2, w2 // w2<- vCC - GET_VREG_WIDE x1, w1 // w1<- vBB - .if 1 - cbz x2, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - sdiv x0, x1, x2 // x0<- op, w0-w4 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w4 // vAA<- x0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_rem_long: /* 0x9f */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = x1 op x2". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than x0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, rem-double - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - lsr w2, w0, #8 // w2<- CC - and w1, w0, #255 // w1<- BB - GET_VREG_WIDE x2, w2 // w2<- vCC - GET_VREG_WIDE x1, w1 // w1<- vBB - .if 1 - cbz x2, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - sdiv x3, x1, x2 - msub x0, x3, x2, x1 // x0<- op, w0-w4 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w4 // vAA<- x0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_and_long: /* 0xa0 */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = x1 op x2". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than x0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, rem-double - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - lsr w2, w0, #8 // w2<- CC - and w1, w0, #255 // w1<- BB - GET_VREG_WIDE x2, w2 // w2<- vCC - GET_VREG_WIDE x1, w1 // w1<- vBB - .if 0 - cbz x2, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - and x0, x1, x2 // x0<- op, w0-w4 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w4 // vAA<- x0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_or_long: /* 0xa1 */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = x1 op x2". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than x0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, rem-double - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - lsr w2, w0, #8 // w2<- CC - and w1, w0, #255 // w1<- BB - GET_VREG_WIDE x2, w2 // w2<- vCC - GET_VREG_WIDE x1, w1 // w1<- vBB - .if 0 - cbz x2, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - orr x0, x1, x2 // x0<- op, w0-w4 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w4 // vAA<- x0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_xor_long: /* 0xa2 */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = x1 op x2". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than x0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, rem-double - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - lsr w2, w0, #8 // w2<- CC - and w1, w0, #255 // w1<- BB - GET_VREG_WIDE x2, w2 // w2<- vCC - GET_VREG_WIDE x1, w1 // w1<- vBB - .if 0 - cbz x2, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - eor x0, x1, x2 // x0<- op, w0-w4 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w4 // vAA<- x0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_shl_long: /* 0xa3 */ - /* - * 64-bit shift operation. - * - * For: shl-long, shr-long, ushr-long - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w3, wINST, #8 // w3<- AA - lsr w2, w0, #8 // w2<- CC - GET_VREG w2, w2 // w2<- vCC (shift count) - and w1, w0, #255 // w1<- BB - GET_VREG_WIDE x1, w1 // x1<- vBB - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - lsl x0, x1, x2 // Do the shift. Only low 6 bits of x2 are used. - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w3 // vAA<- x0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_shr_long: /* 0xa4 */ - /* - * 64-bit shift operation. - * - * For: shl-long, shr-long, ushr-long - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w3, wINST, #8 // w3<- AA - lsr w2, w0, #8 // w2<- CC - GET_VREG w2, w2 // w2<- vCC (shift count) - and w1, w0, #255 // w1<- BB - GET_VREG_WIDE x1, w1 // x1<- vBB - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - asr x0, x1, x2 // Do the shift. Only low 6 bits of x2 are used. - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w3 // vAA<- x0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_long: /* 0xa5 */ - /* - * 64-bit shift operation. - * - * For: shl-long, shr-long, ushr-long - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w3, wINST, #8 // w3<- AA - lsr w2, w0, #8 // w2<- CC - GET_VREG w2, w2 // w2<- vCC (shift count) - and w1, w0, #255 // w1<- BB - GET_VREG_WIDE x1, w1 // x1<- vBB - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - lsr x0, x1, x2 // Do the shift. Only low 6 bits of x2 are used. - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w3 // vAA<- x0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_add_float: /* 0xa6 */ - /*: - * Generic 32-bit floating-point operation. - * - * For: add-float, sub-float, mul-float, div-float - * form: s0, s0, s1 - */ - /* floatop vAA, vBB, vCC */ - FETCH w0, 1 // r0<- CCBB - lsr w1, w0, #8 // r2<- CC - and w0, w0, #255 // r1<- BB - GET_VREG s1, w1 - GET_VREG s0, w0 - fadd s0, s0, s1 // s0<- op - lsr w1, wINST, #8 // r1<- AA - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG s0, w1 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_sub_float: /* 0xa7 */ - /*: - * Generic 32-bit floating-point operation. - * - * For: add-float, sub-float, mul-float, div-float - * form: s0, s0, s1 - */ - /* floatop vAA, vBB, vCC */ - FETCH w0, 1 // r0<- CCBB - lsr w1, w0, #8 // r2<- CC - and w0, w0, #255 // r1<- BB - GET_VREG s1, w1 - GET_VREG s0, w0 - fsub s0, s0, s1 // s0<- op - lsr w1, wINST, #8 // r1<- AA - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG s0, w1 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_mul_float: /* 0xa8 */ - /*: - * Generic 32-bit floating-point operation. - * - * For: add-float, sub-float, mul-float, div-float - * form: s0, s0, s1 - */ - /* floatop vAA, vBB, vCC */ - FETCH w0, 1 // r0<- CCBB - lsr w1, w0, #8 // r2<- CC - and w0, w0, #255 // r1<- BB - GET_VREG s1, w1 - GET_VREG s0, w0 - fmul s0, s0, s1 // s0<- op - lsr w1, wINST, #8 // r1<- AA - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG s0, w1 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_div_float: /* 0xa9 */ - /*: - * Generic 32-bit floating-point operation. - * - * For: add-float, sub-float, mul-float, div-float - * form: s0, s0, s1 - */ - /* floatop vAA, vBB, vCC */ - FETCH w0, 1 // r0<- CCBB - lsr w1, w0, #8 // r2<- CC - and w0, w0, #255 // r1<- BB - GET_VREG s1, w1 - GET_VREG s0, w0 - fdiv s0, s0, s1 // s0<- op - lsr w1, wINST, #8 // r1<- AA - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG s0, w1 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_rem_float: /* 0xaa */ -/* EABI doesn't define a float remainder function, but libm does */ - /*: - * Generic 32-bit floating-point operation. - * - * For: add-float, sub-float, mul-float, div-float - * form: s0, s0, s1 - */ - /* floatop vAA, vBB, vCC */ - FETCH w0, 1 // r0<- CCBB - lsr w1, w0, #8 // r2<- CC - and w0, w0, #255 // r1<- BB - GET_VREG s1, w1 - GET_VREG s0, w0 - bl fmodf // s0<- op - lsr w1, wINST, #8 // r1<- AA - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG s0, w1 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_add_double: /* 0xab */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = x1 op x2". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than x0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, rem-double - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - lsr w2, w0, #8 // w2<- CC - and w1, w0, #255 // w1<- BB - GET_VREG_WIDE d2, w2 // w2<- vCC - GET_VREG_WIDE d1, w1 // w1<- vBB - .if 0 - cbz d2, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - fadd d0, d1, d2 // d0<- op, w0-w4 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE d0, w4 // vAA<- d0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_sub_double: /* 0xac */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = x1 op x2". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than x0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, rem-double - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - lsr w2, w0, #8 // w2<- CC - and w1, w0, #255 // w1<- BB - GET_VREG_WIDE d2, w2 // w2<- vCC - GET_VREG_WIDE d1, w1 // w1<- vBB - .if 0 - cbz d2, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - fsub d0, d1, d2 // d0<- op, w0-w4 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE d0, w4 // vAA<- d0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_mul_double: /* 0xad */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = x1 op x2". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than x0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, rem-double - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - lsr w2, w0, #8 // w2<- CC - and w1, w0, #255 // w1<- BB - GET_VREG_WIDE d2, w2 // w2<- vCC - GET_VREG_WIDE d1, w1 // w1<- vBB - .if 0 - cbz d2, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - fmul d0, d1, d2 // d0<- op, w0-w4 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE d0, w4 // vAA<- d0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_div_double: /* 0xae */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = x1 op x2". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than x0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, rem-double - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - lsr w2, w0, #8 // w2<- CC - and w1, w0, #255 // w1<- BB - GET_VREG_WIDE d2, w2 // w2<- vCC - GET_VREG_WIDE d1, w1 // w1<- vBB - .if 0 - cbz d2, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - fdiv d0, d1, d2 // d0<- op, w0-w4 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE d0, w4 // vAA<- d0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_rem_double: /* 0xaf */ - /* rem vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w2, w0, #8 // w2<- CC - and w1, w0, #255 // w1<- BB - GET_VREG_WIDE d1, w2 // d1<- vCC - GET_VREG_WIDE d0, w1 // d0<- vBB - bl fmod - lsr w4, wINST, #8 // w4<- AA - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE d0, w4 // vAA<- result - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_add_int_2addr: /* 0xb0 */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG w1, w3 // w1<- vB - GET_VREG w0, w9 // w0<- vA - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - // optional op; may set condition codes - add w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_sub_int_2addr: /* 0xb1 */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG w1, w3 // w1<- vB - GET_VREG w0, w9 // w0<- vA - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - // optional op; may set condition codes - sub w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int_2addr: /* 0xb2 */ -/* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG w1, w3 // w1<- vB - GET_VREG w0, w9 // w0<- vA - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - // optional op; may set condition codes - mul w0, w1, w0 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_div_int_2addr: /* 0xb3 */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG w1, w3 // w1<- vB - GET_VREG w0, w9 // w0<- vA - .if 1 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - // optional op; may set condition codes - sdiv w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int_2addr: /* 0xb4 */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG w1, w3 // w1<- vB - GET_VREG w0, w9 // w0<- vA - .if 1 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - sdiv w2, w0, w1 // optional op; may set condition codes - msub w0, w2, w1, w0 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_and_int_2addr: /* 0xb5 */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG w1, w3 // w1<- vB - GET_VREG w0, w9 // w0<- vA - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - // optional op; may set condition codes - and w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_or_int_2addr: /* 0xb6 */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG w1, w3 // w1<- vB - GET_VREG w0, w9 // w0<- vA - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - // optional op; may set condition codes - orr w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int_2addr: /* 0xb7 */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG w1, w3 // w1<- vB - GET_VREG w0, w9 // w0<- vA - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - // optional op; may set condition codes - eor w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_shl_int_2addr: /* 0xb8 */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG w1, w3 // w1<- vB - GET_VREG w0, w9 // w0<- vA - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - // optional op; may set condition codes - lsl w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_shr_int_2addr: /* 0xb9 */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG w1, w3 // w1<- vB - GET_VREG w0, w9 // w0<- vA - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - // optional op; may set condition codes - asr w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_int_2addr: /* 0xba */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG w1, w3 // w1<- vB - GET_VREG w0, w9 // w0<- vA - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - // optional op; may set condition codes - lsr w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_add_long_2addr: /* 0xbb */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "x0 = x0 op x1". - * This must not be a function call, as we keep w2 live across it. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr - */ - /* binop/2addr vA, vB */ - lsr w1, wINST, #12 // w1<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG_WIDE x1, w1 // x1<- vB - GET_VREG_WIDE x0, w2 // x0<- vA - .if 0 - cbz x1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - - add x0, x0, x1 // result<- op - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w2 // vAA<- result - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_sub_long_2addr: /* 0xbc */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "x0 = x0 op x1". - * This must not be a function call, as we keep w2 live across it. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr - */ - /* binop/2addr vA, vB */ - lsr w1, wINST, #12 // w1<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG_WIDE x1, w1 // x1<- vB - GET_VREG_WIDE x0, w2 // x0<- vA - .if 0 - cbz x1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - - sub x0, x0, x1 // result<- op - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w2 // vAA<- result - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_mul_long_2addr: /* 0xbd */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "x0 = x0 op x1". - * This must not be a function call, as we keep w2 live across it. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr - */ - /* binop/2addr vA, vB */ - lsr w1, wINST, #12 // w1<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG_WIDE x1, w1 // x1<- vB - GET_VREG_WIDE x0, w2 // x0<- vA - .if 0 - cbz x1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - - mul x0, x0, x1 // result<- op - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w2 // vAA<- result - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_div_long_2addr: /* 0xbe */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "x0 = x0 op x1". - * This must not be a function call, as we keep w2 live across it. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr - */ - /* binop/2addr vA, vB */ - lsr w1, wINST, #12 // w1<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG_WIDE x1, w1 // x1<- vB - GET_VREG_WIDE x0, w2 // x0<- vA - .if 1 - cbz x1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - - sdiv x0, x0, x1 // result<- op - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w2 // vAA<- result - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_rem_long_2addr: /* 0xbf */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "x0 = x0 op x1". - * This must not be a function call, as we keep w2 live across it. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr - */ - /* binop/2addr vA, vB */ - lsr w1, wINST, #12 // w1<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG_WIDE x1, w1 // x1<- vB - GET_VREG_WIDE x0, w2 // x0<- vA - .if 1 - cbz x1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - sdiv x3, x0, x1 - msub x0, x3, x1, x0 // result<- op - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w2 // vAA<- result - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_and_long_2addr: /* 0xc0 */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "x0 = x0 op x1". - * This must not be a function call, as we keep w2 live across it. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr - */ - /* binop/2addr vA, vB */ - lsr w1, wINST, #12 // w1<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG_WIDE x1, w1 // x1<- vB - GET_VREG_WIDE x0, w2 // x0<- vA - .if 0 - cbz x1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - - and x0, x0, x1 // result<- op - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w2 // vAA<- result - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_or_long_2addr: /* 0xc1 */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "x0 = x0 op x1". - * This must not be a function call, as we keep w2 live across it. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr - */ - /* binop/2addr vA, vB */ - lsr w1, wINST, #12 // w1<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG_WIDE x1, w1 // x1<- vB - GET_VREG_WIDE x0, w2 // x0<- vA - .if 0 - cbz x1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - - orr x0, x0, x1 // result<- op - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w2 // vAA<- result - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_xor_long_2addr: /* 0xc2 */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "x0 = x0 op x1". - * This must not be a function call, as we keep w2 live across it. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr - */ - /* binop/2addr vA, vB */ - lsr w1, wINST, #12 // w1<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG_WIDE x1, w1 // x1<- vB - GET_VREG_WIDE x0, w2 // x0<- vA - .if 0 - cbz x1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - - eor x0, x0, x1 // result<- op - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w2 // vAA<- result - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_shl_long_2addr: /* 0xc3 */ - /* - * Generic 64-bit shift operation. - */ - /* binop/2addr vA, vB */ - lsr w1, wINST, #12 // w1<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG w1, w1 // x1<- vB - GET_VREG_WIDE x0, w2 // x0<- vA - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - lsl x0, x0, x1 // Do the shift. Only low 6 bits of x1 are used. - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w2 // vAA<- result - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_shr_long_2addr: /* 0xc4 */ - /* - * Generic 64-bit shift operation. - */ - /* binop/2addr vA, vB */ - lsr w1, wINST, #12 // w1<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG w1, w1 // x1<- vB - GET_VREG_WIDE x0, w2 // x0<- vA - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - asr x0, x0, x1 // Do the shift. Only low 6 bits of x1 are used. - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w2 // vAA<- result - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_long_2addr: /* 0xc5 */ - /* - * Generic 64-bit shift operation. - */ - /* binop/2addr vA, vB */ - lsr w1, wINST, #12 // w1<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG w1, w1 // x1<- vB - GET_VREG_WIDE x0, w2 // x0<- vA - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - lsr x0, x0, x1 // Do the shift. Only low 6 bits of x1 are used. - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w2 // vAA<- result - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_add_float_2addr: /* 0xc6 */ - /* - * Generic 32-bit floating point "/2addr" binary operation. Provide - * an "instr" line that specifies an instruction that performs - * "s2 = s0 op s1". - * - * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr - */ - /* binop/2addr vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG s1, w3 - GET_VREG s0, w9 - fadd s2, s0, s1 // s2<- op - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG s2, w9 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_sub_float_2addr: /* 0xc7 */ - /* - * Generic 32-bit floating point "/2addr" binary operation. Provide - * an "instr" line that specifies an instruction that performs - * "s2 = s0 op s1". - * - * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr - */ - /* binop/2addr vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG s1, w3 - GET_VREG s0, w9 - fsub s2, s0, s1 // s2<- op - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG s2, w9 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_mul_float_2addr: /* 0xc8 */ - /* - * Generic 32-bit floating point "/2addr" binary operation. Provide - * an "instr" line that specifies an instruction that performs - * "s2 = s0 op s1". - * - * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr - */ - /* binop/2addr vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG s1, w3 - GET_VREG s0, w9 - fmul s2, s0, s1 // s2<- op - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG s2, w9 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_div_float_2addr: /* 0xc9 */ - /* - * Generic 32-bit floating point "/2addr" binary operation. Provide - * an "instr" line that specifies an instruction that performs - * "s2 = s0 op s1". - * - * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr - */ - /* binop/2addr vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG s1, w3 - GET_VREG s0, w9 - fdiv s2, s0, s1 // s2<- op - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG s2, w9 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_rem_float_2addr: /* 0xca */ - /* rem vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG s1, w3 - GET_VREG s0, w9 - bl fmodf - ubfx w9, wINST, #8, #4 // w9<- A - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG s0, w9 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_add_double_2addr: /* 0xcb */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "x0 = x0 op x1". - * This must not be a function call, as we keep w2 live across it. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr - */ - /* binop/2addr vA, vB */ - lsr w1, wINST, #12 // w1<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG_WIDE d1, w1 // x1<- vB - GET_VREG_WIDE d0, w2 // x0<- vA - .if 0 - cbz d1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - - fadd d0, d0, d1 // result<- op - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE d0, w2 // vAA<- result - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_sub_double_2addr: /* 0xcc */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "x0 = x0 op x1". - * This must not be a function call, as we keep w2 live across it. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr - */ - /* binop/2addr vA, vB */ - lsr w1, wINST, #12 // w1<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG_WIDE d1, w1 // x1<- vB - GET_VREG_WIDE d0, w2 // x0<- vA - .if 0 - cbz d1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - - fsub d0, d0, d1 // result<- op - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE d0, w2 // vAA<- result - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_mul_double_2addr: /* 0xcd */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "x0 = x0 op x1". - * This must not be a function call, as we keep w2 live across it. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr - */ - /* binop/2addr vA, vB */ - lsr w1, wINST, #12 // w1<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG_WIDE d1, w1 // x1<- vB - GET_VREG_WIDE d0, w2 // x0<- vA - .if 0 - cbz d1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - - fmul d0, d0, d1 // result<- op - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE d0, w2 // vAA<- result - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_div_double_2addr: /* 0xce */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "x0 = x0 op x1". - * This must not be a function call, as we keep w2 live across it. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr - */ - /* binop/2addr vA, vB */ - lsr w1, wINST, #12 // w1<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG_WIDE d1, w1 // x1<- vB - GET_VREG_WIDE d0, w2 // x0<- vA - .if 0 - cbz d1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - - fdiv d0, d0, d1 // result<- op - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE d0, w2 // vAA<- result - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_rem_double_2addr: /* 0xcf */ - /* rem vA, vB */ - lsr w1, wINST, #12 // w1<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG_WIDE d1, w1 // d1<- vB - GET_VREG_WIDE d0, w2 // d0<- vA - bl fmod - ubfx w2, wINST, #8, #4 // w2<- A (need to reload - killed across call) - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE d0, w2 // vAA<- result - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_add_int_lit16: /* 0xd0 */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - FETCH_S w1, 1 // w1<- ssssCCCC (sign-extended) - lsr w2, wINST, #12 // w2<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG w0, w2 // w0<- vB - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - add w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_rsub_int: /* 0xd1 */ -/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - FETCH_S w1, 1 // w1<- ssssCCCC (sign-extended) - lsr w2, wINST, #12 // w2<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG w0, w2 // w0<- vB - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - sub w0, w1, w0 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int_lit16: /* 0xd2 */ -/* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - FETCH_S w1, 1 // w1<- ssssCCCC (sign-extended) - lsr w2, wINST, #12 // w2<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG w0, w2 // w0<- vB - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - mul w0, w1, w0 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_div_int_lit16: /* 0xd3 */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - FETCH_S w1, 1 // w1<- ssssCCCC (sign-extended) - lsr w2, wINST, #12 // w2<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG w0, w2 // w0<- vB - .if 1 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - sdiv w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int_lit16: /* 0xd4 */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - FETCH_S w1, 1 // w1<- ssssCCCC (sign-extended) - lsr w2, wINST, #12 // w2<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG w0, w2 // w0<- vB - .if 1 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - sdiv w3, w0, w1 - msub w0, w3, w1, w0 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_and_int_lit16: /* 0xd5 */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - FETCH_S w1, 1 // w1<- ssssCCCC (sign-extended) - lsr w2, wINST, #12 // w2<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG w0, w2 // w0<- vB - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - and w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_or_int_lit16: /* 0xd6 */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - FETCH_S w1, 1 // w1<- ssssCCCC (sign-extended) - lsr w2, wINST, #12 // w2<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG w0, w2 // w0<- vB - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - orr w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int_lit16: /* 0xd7 */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - FETCH_S w1, 1 // w1<- ssssCCCC (sign-extended) - lsr w2, wINST, #12 // w2<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG w0, w2 // w0<- vB - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - eor w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_add_int_lit8: /* 0xd8 */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from w3 to w1 is not the default "asr w1, w3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC) - lsr w9, wINST, #8 // w9<- AA - and w2, w3, #255 // w2<- BB - GET_VREG w0, w2 // w0<- vBB - // optional; typically w1<- ssssssCC (sign extended) - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - // optional op; may set condition codes - add w0, w0, w3, asr #8 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-12 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_rsub_int_lit8: /* 0xd9 */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from w3 to w1 is not the default "asr w1, w3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC) - lsr w9, wINST, #8 // w9<- AA - and w2, w3, #255 // w2<- BB - GET_VREG w0, w2 // w0<- vBB - asr w1, w3, #8 // optional; typically w1<- ssssssCC (sign extended) - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - // optional op; may set condition codes - sub w0, w1, w0 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-12 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int_lit8: /* 0xda */ -/* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from w3 to w1 is not the default "asr w1, w3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC) - lsr w9, wINST, #8 // w9<- AA - and w2, w3, #255 // w2<- BB - GET_VREG w0, w2 // w0<- vBB - asr w1, w3, #8 // optional; typically w1<- ssssssCC (sign extended) - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - // optional op; may set condition codes - mul w0, w1, w0 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-12 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_div_int_lit8: /* 0xdb */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from w3 to w1 is not the default "asr w1, w3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC) - lsr w9, wINST, #8 // w9<- AA - and w2, w3, #255 // w2<- BB - GET_VREG w0, w2 // w0<- vBB - asr w1, w3, #8 // optional; typically w1<- ssssssCC (sign extended) - .if 1 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - // optional op; may set condition codes - sdiv w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-12 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int_lit8: /* 0xdc */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from w3 to w1 is not the default "asr w1, w3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC) - lsr w9, wINST, #8 // w9<- AA - and w2, w3, #255 // w2<- BB - GET_VREG w0, w2 // w0<- vBB - asr w1, w3, #8 // optional; typically w1<- ssssssCC (sign extended) - .if 1 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - sdiv w3, w0, w1 // optional op; may set condition codes - msub w0, w3, w1, w0 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-12 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_and_int_lit8: /* 0xdd */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from w3 to w1 is not the default "asr w1, w3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC) - lsr w9, wINST, #8 // w9<- AA - and w2, w3, #255 // w2<- BB - GET_VREG w0, w2 // w0<- vBB - // optional; typically w1<- ssssssCC (sign extended) - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - // optional op; may set condition codes - and w0, w0, w3, asr #8 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-12 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_or_int_lit8: /* 0xde */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from w3 to w1 is not the default "asr w1, w3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC) - lsr w9, wINST, #8 // w9<- AA - and w2, w3, #255 // w2<- BB - GET_VREG w0, w2 // w0<- vBB - // optional; typically w1<- ssssssCC (sign extended) - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - // optional op; may set condition codes - orr w0, w0, w3, asr #8 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-12 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int_lit8: /* 0xdf */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from w3 to w1 is not the default "asr w1, w3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC) - lsr w9, wINST, #8 // w9<- AA - and w2, w3, #255 // w2<- BB - GET_VREG w0, w2 // w0<- vBB - // optional; typically w1<- ssssssCC (sign extended) - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - // optional op; may set condition codes - eor w0, w0, w3, asr #8 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-12 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_shl_int_lit8: /* 0xe0 */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from w3 to w1 is not the default "asr w1, w3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC) - lsr w9, wINST, #8 // w9<- AA - and w2, w3, #255 // w2<- BB - GET_VREG w0, w2 // w0<- vBB - ubfx w1, w3, #8, #5 // optional; typically w1<- ssssssCC (sign extended) - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - // optional op; may set condition codes - lsl w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-12 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_shr_int_lit8: /* 0xe1 */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from w3 to w1 is not the default "asr w1, w3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC) - lsr w9, wINST, #8 // w9<- AA - and w2, w3, #255 // w2<- BB - GET_VREG w0, w2 // w0<- vBB - ubfx w1, w3, #8, #5 // optional; typically w1<- ssssssCC (sign extended) - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - // optional op; may set condition codes - asr w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-12 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_int_lit8: /* 0xe2 */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from w3 to w1 is not the default "asr w1, w3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC) - lsr w9, wINST, #8 // w9<- AA - and w2, w3, #255 // w2<- BB - GET_VREG w0, w2 // w0<- vBB - ubfx w1, w3, #8, #5 // optional; typically w1<- ssssssCC (sign extended) - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - // optional op; may set condition codes - lsr w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-12 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_iget_quick: /* 0xe3 */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset//CCCC */ - lsr w2, wINST, #12 // w2<- B - FETCH w1, 1 // w1<- field byte offset - GET_VREG w3, w2 // w3<- object we're operating on - ubfx w2, wINST, #8, #4 // w2<- A - cbz w3, common_errNullObject // object was null - ldr w0, [x3, x1] // w0<- obj.field - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - SET_VREG w0, w2 // fp[A]<- w0 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iget_wide_quick: /* 0xe4 */ - /* iget-wide-quick vA, vB, offset//CCCC */ - lsr w2, wINST, #12 // w2<- B - FETCH w4, 1 // w4<- field byte offset - GET_VREG w3, w2 // w3<- object we're operating on - ubfx w2, wINST, #8, #4 // w2<- A - cbz w3, common_errNullObject // object was null - ldr x0, [x3, x4] // x0<- obj.field - FETCH_ADVANCE_INST 2 // advance rPC, load wINST - SET_VREG_WIDE x0, w2 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iget_object_quick: /* 0xe5 */ - /* For: iget-object-quick */ - /* op vA, vB, offset//CCCC */ - lsr w2, wINST, #12 // w2<- B - FETCH w1, 1 // w1<- field byte offset - EXPORT_PC - GET_VREG w0, w2 // w0<- object we're operating on - bl artIGetObjectFromMterp // (obj, offset) - ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] - ubfx w2, wINST, #8, #4 // w2<- A - PREFETCH_INST 2 - cbnz w3, MterpPossibleException // bail out - SET_VREG_OBJECT w0, w2 // fp[A]<- w0 - ADVANCE 2 // advance rPC - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_quick: /* 0xe6 */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset//CCCC */ - lsr w2, wINST, #12 // w2<- B - FETCH w1, 1 // w1<- field byte offset - GET_VREG w3, w2 // w3<- fp[B], the object pointer - ubfx w2, wINST, #8, #4 // w2<- A - cbz w3, common_errNullObject // object was null - GET_VREG w0, w2 // w0<- fp[A] - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - str w0, [x3, x1] // obj.field<- w0 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_wide_quick: /* 0xe7 */ - /* iput-wide-quick vA, vB, offset//CCCC */ - lsr w2, wINST, #12 // w2<- B - FETCH w3, 1 // w3<- field byte offset - GET_VREG w2, w2 // w2<- fp[B], the object pointer - ubfx w0, wINST, #8, #4 // w0<- A - cbz w2, common_errNullObject // object was null - GET_VREG_WIDE x0, w0 // x0<- fp[A] - FETCH_ADVANCE_INST 2 // advance rPC, load wINST - str x0, [x2, x3] // obj.field<- x0 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_object_quick: /* 0xe8 */ - EXPORT_PC - add x0, xFP, #OFF_FP_SHADOWFRAME - mov x1, xPC - mov w2, wINST - bl MterpIputObjectQuick - cbz w0, MterpException - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual_quick: /* 0xe9 */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtualQuick - EXPORT_PC - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - mov x3, xINST - bl MterpInvokeVirtualQuick - cbz w0, MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cbnz w0, MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual_range_quick: /* 0xea */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtualQuickRange - EXPORT_PC - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - mov x3, xINST - bl MterpInvokeVirtualQuickRange - cbz w0, MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cbnz w0, MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - -/* ------------------------------ */ - .balign 128 -.L_op_iput_boolean_quick: /* 0xeb */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset//CCCC */ - lsr w2, wINST, #12 // w2<- B - FETCH w1, 1 // w1<- field byte offset - GET_VREG w3, w2 // w3<- fp[B], the object pointer - ubfx w2, wINST, #8, #4 // w2<- A - cbz w3, common_errNullObject // object was null - GET_VREG w0, w2 // w0<- fp[A] - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - strb w0, [x3, x1] // obj.field<- w0 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_byte_quick: /* 0xec */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset//CCCC */ - lsr w2, wINST, #12 // w2<- B - FETCH w1, 1 // w1<- field byte offset - GET_VREG w3, w2 // w3<- fp[B], the object pointer - ubfx w2, wINST, #8, #4 // w2<- A - cbz w3, common_errNullObject // object was null - GET_VREG w0, w2 // w0<- fp[A] - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - strb w0, [x3, x1] // obj.field<- w0 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_char_quick: /* 0xed */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset//CCCC */ - lsr w2, wINST, #12 // w2<- B - FETCH w1, 1 // w1<- field byte offset - GET_VREG w3, w2 // w3<- fp[B], the object pointer - ubfx w2, wINST, #8, #4 // w2<- A - cbz w3, common_errNullObject // object was null - GET_VREG w0, w2 // w0<- fp[A] - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - strh w0, [x3, x1] // obj.field<- w0 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_short_quick: /* 0xee */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset//CCCC */ - lsr w2, wINST, #12 // w2<- B - FETCH w1, 1 // w1<- field byte offset - GET_VREG w3, w2 // w3<- fp[B], the object pointer - ubfx w2, wINST, #8, #4 // w2<- A - cbz w3, common_errNullObject // object was null - GET_VREG w0, w2 // w0<- fp[A] - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - strh w0, [x3, x1] // obj.field<- w0 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iget_boolean_quick: /* 0xef */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset//CCCC */ - lsr w2, wINST, #12 // w2<- B - FETCH w1, 1 // w1<- field byte offset - GET_VREG w3, w2 // w3<- object we're operating on - ubfx w2, wINST, #8, #4 // w2<- A - cbz w3, common_errNullObject // object was null - ldrb w0, [x3, x1] // w0<- obj.field - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - SET_VREG w0, w2 // fp[A]<- w0 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iget_byte_quick: /* 0xf0 */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset//CCCC */ - lsr w2, wINST, #12 // w2<- B - FETCH w1, 1 // w1<- field byte offset - GET_VREG w3, w2 // w3<- object we're operating on - ubfx w2, wINST, #8, #4 // w2<- A - cbz w3, common_errNullObject // object was null - ldrsb w0, [x3, x1] // w0<- obj.field - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - SET_VREG w0, w2 // fp[A]<- w0 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iget_char_quick: /* 0xf1 */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset//CCCC */ - lsr w2, wINST, #12 // w2<- B - FETCH w1, 1 // w1<- field byte offset - GET_VREG w3, w2 // w3<- object we're operating on - ubfx w2, wINST, #8, #4 // w2<- A - cbz w3, common_errNullObject // object was null - ldrh w0, [x3, x1] // w0<- obj.field - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - SET_VREG w0, w2 // fp[A]<- w0 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iget_short_quick: /* 0xf2 */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset//CCCC */ - lsr w2, wINST, #12 // w2<- B - FETCH w1, 1 // w1<- field byte offset - GET_VREG w3, w2 // w3<- object we're operating on - ubfx w2, wINST, #8, #4 // w2<- A - cbz w3, common_errNullObject // object was null - ldrsh w0, [x3, x1] // w0<- obj.field - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - SET_VREG w0, w2 // fp[A]<- w0 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f3: /* 0xf3 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f4: /* 0xf4 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f5: /* 0xf5 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f6: /* 0xf6 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f7: /* 0xf7 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f8: /* 0xf8 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f9: /* 0xf9 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_polymorphic: /* 0xfa */ - /* - * invoke-polymorphic handler wrapper. - */ - /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ - .extern MterpInvokePolymorphic - EXPORT_PC - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - mov x3, xINST - bl MterpInvokePolymorphic - cbz w0, MterpException - FETCH_ADVANCE_INST 4 - bl MterpShouldSwitchInterpreters - cbnz w0, MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_polymorphic_range: /* 0xfb */ - /* - * invoke-polymorphic handler wrapper. - */ - /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ - .extern MterpInvokePolymorphicRange - EXPORT_PC - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - mov x3, xINST - bl MterpInvokePolymorphicRange - cbz w0, MterpException - FETCH_ADVANCE_INST 4 - bl MterpShouldSwitchInterpreters - cbnz w0, MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_custom: /* 0xfc */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeCustom - EXPORT_PC - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - mov x3, xINST - bl MterpInvokeCustom - cbz w0, MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cbnz w0, MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_custom_range: /* 0xfd */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeCustomRange - EXPORT_PC - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - mov x3, xINST - bl MterpInvokeCustomRange - cbz w0, MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cbnz w0, MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - -/* ------------------------------ */ - .balign 128 -.L_op_const_method_handle: /* 0xfe */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstMethodHandle - EXPORT_PC - FETCH w0, 1 // w0<- BBBB - lsr w1, wINST, #8 // w1<- AA - add x2, xFP, #OFF_FP_SHADOWFRAME - mov x3, xSELF - bl MterpConstMethodHandle // (index, tgt_reg, shadow_frame, self) - PREFETCH_INST 2 // load rINST - cbnz w0, MterpPossibleException // let reference interpreter deal with it. - ADVANCE 2 // advance rPC - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_method_type: /* 0xff */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstMethodType - EXPORT_PC - FETCH w0, 1 // w0<- BBBB - lsr w1, wINST, #8 // w1<- AA - add x2, xFP, #OFF_FP_SHADOWFRAME - mov x3, xSELF - bl MterpConstMethodType // (index, tgt_reg, shadow_frame, self) - PREFETCH_INST 2 // load rINST - cbnz w0, MterpPossibleException // let reference interpreter deal with it. - ADVANCE 2 // advance rPC - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - - .balign 128 - - .type artMterpAsmInstructionEnd, #object - .hidden artMterpAsmInstructionEnd - .global artMterpAsmInstructionEnd -artMterpAsmInstructionEnd: - -/* - * =========================================================================== - * Common subroutines and data - * =========================================================================== - */ - -/* - * We've detected a condition that will result in an exception, but the exception - * has not yet been thrown. Just bail out to the reference interpreter to deal with it. - * TUNING: for consistency, we may want to just go ahead and handle these here. - */ -common_errDivideByZero: - EXPORT_PC -#if MTERP_LOGGING - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - bl MterpLogDivideByZeroException -#endif - b MterpCommonFallback - -common_errArrayIndex: - EXPORT_PC -#if MTERP_LOGGING - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - bl MterpLogArrayIndexException -#endif - b MterpCommonFallback - -common_errNegativeArraySize: - EXPORT_PC -#if MTERP_LOGGING - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - bl MterpLogNegativeArraySizeException -#endif - b MterpCommonFallback - -common_errNoSuchMethod: - EXPORT_PC -#if MTERP_LOGGING - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - bl MterpLogNoSuchMethodException -#endif - b MterpCommonFallback - -common_errNullObject: - EXPORT_PC -#if MTERP_LOGGING - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - bl MterpLogNullObjectException -#endif - b MterpCommonFallback - -common_exceptionThrown: - EXPORT_PC -#if MTERP_LOGGING - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - bl MterpLogExceptionThrownException -#endif - b MterpCommonFallback - -MterpSuspendFallback: - EXPORT_PC -#if MTERP_LOGGING - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - ldr x2, [xSELF, #THREAD_FLAGS_OFFSET] - bl MterpLogSuspendFallback -#endif - b MterpCommonFallback - -/* - * If we're here, something is out of the ordinary. If there is a pending - * exception, handle it. Otherwise, roll back and retry with the reference - * interpreter. - */ -MterpPossibleException: - ldr x0, [xSELF, #THREAD_EXCEPTION_OFFSET] - cbz x0, MterpFallback // If not, fall back to reference interpreter. - /* intentional fallthrough - handle pending exception. */ -/* - * On return from a runtime helper routine, we've found a pending exception. - * Can we handle it here - or need to bail out to caller? - * - */ -MterpException: - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - bl MterpHandleException // (self, shadow_frame) - cbz w0, MterpExceptionReturn // no local catch, back to caller. - ldr x0, [xFP, #OFF_FP_DEX_INSTRUCTIONS] - ldr w1, [xFP, #OFF_FP_DEX_PC] - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] - add xPC, x0, x1, lsl #1 // generate new dex_pc_ptr - /* Do we need to switch interpreters? */ - bl MterpShouldSwitchInterpreters - cbnz w0, MterpFallback - /* resume execution at catch block */ - EXPORT_PC - FETCH_INST - GET_INST_OPCODE ip - GOTO_OPCODE ip - /* NOTE: no fallthrough */ -/* - * Common handling for branches with support for Jit profiling. - * On entry: - * wINST <= signed offset - * wPROFILE <= signed hotness countdown (expanded to 32 bits) - * condition bits <= set to establish sign of offset (use "NoFlags" entry if not) - * - * We have quite a few different cases for branch profiling, OSR detection and - * suspend check support here. - * - * Taken backward branches: - * If profiling active, do hotness countdown and report if we hit zero. - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * Is there a pending suspend request? If so, suspend. - * - * Taken forward branches and not-taken backward branches: - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * - * Our most common case is expected to be a taken backward branch with active jit profiling, - * but no full OSR check and no pending suspend request. - * Next most common case is not-taken branch with no full OSR check. - * - */ -MterpCommonTakenBranchNoFlags: - cmp wINST, #0 - b.gt .L_forward_branch // don't add forward branches to hotness - tbnz wPROFILE, #31, .L_no_count_backwards // go if negative - subs wPROFILE, wPROFILE, #1 // countdown - b.eq .L_add_batch // counted down to zero - report -.L_resume_backward_branch: - ldr lr, [xSELF, #THREAD_FLAGS_OFFSET] - add w2, wINST, wINST // w2<- byte offset - FETCH_ADVANCE_INST_RB w2 // update rPC, load wINST - REFRESH_IBASE - ands lr, lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - b.ne .L_suspend_request_pending - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - -.L_suspend_request_pending: - EXPORT_PC - mov x0, xSELF - bl MterpSuspendCheck // (self) - cbnz x0, MterpFallback - REFRESH_IBASE // might have changed during suspend - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - -.L_no_count_backwards: - cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? - b.ne .L_resume_backward_branch - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xINST - EXPORT_PC - bl MterpMaybeDoOnStackReplacement // (self, shadow_frame, offset) - cbnz x0, MterpOnStackReplacement - b .L_resume_backward_branch - -.L_forward_branch: - cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? - b.eq .L_check_osr_forward -.L_resume_forward_branch: - add w2, wINST, wINST // w2<- byte offset - FETCH_ADVANCE_INST_RB w2 // update rPC, load wINST - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - -.L_check_osr_forward: - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xINST - EXPORT_PC - bl MterpMaybeDoOnStackReplacement // (self, shadow_frame, offset) - cbnz x0, MterpOnStackReplacement - b .L_resume_forward_branch - -.L_add_batch: - add x1, xFP, #OFF_FP_SHADOWFRAME - strh wPROFILE, [x1, #SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET] - ldr x0, [xFP, #OFF_FP_METHOD] - mov x2, xSELF - bl MterpAddHotnessBatch // (method, shadow_frame, self) - mov wPROFILE, w0 // restore new hotness countdown to wPROFILE - b .L_no_count_backwards - -/* - * Entered from the conditional branch handlers when OSR check request active on - * not-taken path. All Dalvik not-taken conditional branch offsets are 2. - */ -.L_check_not_taken_osr: - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, #2 - EXPORT_PC - bl MterpMaybeDoOnStackReplacement // (self, shadow_frame, offset) - cbnz x0, MterpOnStackReplacement - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - -/* - * Check for suspend check request. Assumes wINST already loaded, xPC advanced and - * still needs to get the opcode and branch to it, and flags are in lr. - */ -MterpCheckSuspendAndContinue: - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh xIBASE - ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - b.ne check1 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction -check1: - EXPORT_PC - mov x0, xSELF - bl MterpSuspendCheck // (self) - cbnz x0, MterpFallback // Something in the environment changed, switch interpreters - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - -/* - * On-stack replacement has happened, and now we've returned from the compiled method. - */ -MterpOnStackReplacement: -#if MTERP_LOGGING - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - sxtw x2, wINST - bl MterpLogOSR -#endif - mov x0, #1 // Signal normal return - b MterpDone - -/* - * Bail out to reference interpreter. - */ -MterpFallback: - EXPORT_PC -#if MTERP_LOGGING - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - bl MterpLogFallback -#endif -MterpCommonFallback: - mov x0, #0 // signal retry with reference interpreter. - b MterpDone - -/* - * We pushed some registers on the stack in ExecuteMterpImpl, then saved - * SP and LR. Here we restore SP, restore the registers, and then restore - * LR to PC. - * - * On entry: - * uint32_t* xFP (should still be live, pointer to base of vregs) - */ -MterpExceptionReturn: - mov x0, #1 // signal return to caller. - b MterpDone -MterpReturn: - ldr x2, [xFP, #OFF_FP_RESULT_REGISTER] - str x0, [x2] - mov x0, #1 // signal return to caller. -MterpDone: -/* - * At this point, we expect wPROFILE to be non-zero. If negative, hotness is disabled or we're - * checking for OSR. If greater than zero, we might have unreported hotness to register - * (the difference between the ending wPROFILE and the cached hotness counter). wPROFILE - * should only reach zero immediately after a hotness decrement, and is then reset to either - * a negative special state or the new non-zero countdown value. - */ - cmp wPROFILE, #0 - bgt MterpProfileActive // if > 0, we may have some counts to report. - .cfi_remember_state - RESTORE_TWO_REGS fp, lr, 64 - RESTORE_TWO_REGS xPC, xFP, 48 - RESTORE_TWO_REGS xSELF, xINST, 32 - RESTORE_TWO_REGS xIBASE, xREFS, 16 - RESTORE_TWO_REGS_DECREASE_FRAME xPROFILE, x27, 80 - ret - .cfi_restore_state // Reset unwind info so following code unwinds. - .cfi_def_cfa_offset 80 // workaround for clang bug: 31975598 - -MterpProfileActive: - mov xINST, x0 // stash return value - /* Report cached hotness counts */ - ldr x0, [xFP, #OFF_FP_METHOD] - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xSELF - strh wPROFILE, [x1, #SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET] - bl MterpAddHotnessBatch // (method, shadow_frame, self) - mov x0, xINST // restore return value - RESTORE_TWO_REGS fp, lr, 64 - RESTORE_TWO_REGS xPC, xFP, 48 - RESTORE_TWO_REGS xSELF, xINST, 32 - RESTORE_TWO_REGS xIBASE, xREFS, 16 - RESTORE_TWO_REGS_DECREASE_FRAME xPROFILE, x27, 80 - ret - - .type artMterpAsmAltInstructionStart, #object - .hidden artMterpAsmAltInstructionStart - .global artMterpAsmAltInstructionStart -artMterpAsmAltInstructionStart = .L_ALT_op_nop - .text -/* ------------------------------ */ - .balign 128 -.L_ALT_op_nop: /* 0x00 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (0 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move: /* 0x01 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (1 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_from16: /* 0x02 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (2 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_16: /* 0x03 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (3 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_wide: /* 0x04 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (4 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_wide_from16: /* 0x05 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (5 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_wide_16: /* 0x06 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (6 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_object: /* 0x07 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (7 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_object_from16: /* 0x08 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (8 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_object_16: /* 0x09 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (9 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_result: /* 0x0a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (10 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_result_wide: /* 0x0b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (11 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_result_object: /* 0x0c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (12 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_exception: /* 0x0d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (13 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_void: /* 0x0e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (14 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return: /* 0x0f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (15 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_wide: /* 0x10 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (16 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_object: /* 0x11 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (17 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_4: /* 0x12 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (18 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_16: /* 0x13 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (19 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const: /* 0x14 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (20 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_high16: /* 0x15 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (21 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide_16: /* 0x16 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (22 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide_32: /* 0x17 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (23 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide: /* 0x18 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (24 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide_high16: /* 0x19 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (25 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_string: /* 0x1a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (26 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_string_jumbo: /* 0x1b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (27 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_class: /* 0x1c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (28 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_monitor_enter: /* 0x1d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (29 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_monitor_exit: /* 0x1e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (30 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_check_cast: /* 0x1f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (31 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_instance_of: /* 0x20 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (32 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_array_length: /* 0x21 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (33 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_new_instance: /* 0x22 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (34 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_new_array: /* 0x23 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (35 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_filled_new_array: /* 0x24 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (36 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_filled_new_array_range: /* 0x25 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (37 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_fill_array_data: /* 0x26 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (38 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_throw: /* 0x27 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (39 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_goto: /* 0x28 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (40 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_goto_16: /* 0x29 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (41 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_goto_32: /* 0x2a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (42 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_packed_switch: /* 0x2b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (43 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sparse_switch: /* 0x2c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (44 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpl_float: /* 0x2d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (45 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpg_float: /* 0x2e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (46 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpl_double: /* 0x2f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (47 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpg_double: /* 0x30 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (48 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmp_long: /* 0x31 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (49 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_eq: /* 0x32 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (50 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_ne: /* 0x33 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (51 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_lt: /* 0x34 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (52 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_ge: /* 0x35 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (53 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_gt: /* 0x36 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (54 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_le: /* 0x37 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (55 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_eqz: /* 0x38 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (56 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_nez: /* 0x39 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (57 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_ltz: /* 0x3a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (58 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_gez: /* 0x3b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (59 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_gtz: /* 0x3c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (60 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_lez: /* 0x3d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (61 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_3e: /* 0x3e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (62 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_3f: /* 0x3f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (63 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_40: /* 0x40 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (64 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_41: /* 0x41 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (65 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_42: /* 0x42 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (66 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_43: /* 0x43 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (67 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget: /* 0x44 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (68 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_wide: /* 0x45 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (69 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_object: /* 0x46 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (70 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_boolean: /* 0x47 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (71 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_byte: /* 0x48 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (72 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_char: /* 0x49 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (73 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_short: /* 0x4a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (74 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput: /* 0x4b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (75 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_wide: /* 0x4c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (76 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_object: /* 0x4d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (77 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_boolean: /* 0x4e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (78 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_byte: /* 0x4f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (79 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_char: /* 0x50 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (80 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_short: /* 0x51 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (81 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget: /* 0x52 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (82 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_wide: /* 0x53 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (83 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_object: /* 0x54 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (84 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_boolean: /* 0x55 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (85 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_byte: /* 0x56 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (86 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_char: /* 0x57 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (87 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_short: /* 0x58 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (88 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput: /* 0x59 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (89 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_wide: /* 0x5a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (90 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_object: /* 0x5b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (91 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_boolean: /* 0x5c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (92 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_byte: /* 0x5d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (93 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_char: /* 0x5e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (94 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_short: /* 0x5f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (95 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget: /* 0x60 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (96 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_wide: /* 0x61 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (97 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_object: /* 0x62 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (98 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_boolean: /* 0x63 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (99 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_byte: /* 0x64 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (100 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_char: /* 0x65 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (101 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_short: /* 0x66 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (102 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput: /* 0x67 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (103 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_wide: /* 0x68 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (104 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_object: /* 0x69 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (105 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_boolean: /* 0x6a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (106 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_byte: /* 0x6b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (107 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_char: /* 0x6c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (108 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_short: /* 0x6d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (109 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual: /* 0x6e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (110 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_super: /* 0x6f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (111 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_direct: /* 0x70 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (112 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_static: /* 0x71 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (113 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_interface: /* 0x72 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (114 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_void_no_barrier: /* 0x73 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (115 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual_range: /* 0x74 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (116 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_super_range: /* 0x75 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (117 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_direct_range: /* 0x76 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (118 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_static_range: /* 0x77 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (119 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_interface_range: /* 0x78 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (120 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_79: /* 0x79 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (121 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_7a: /* 0x7a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (122 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_int: /* 0x7b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (123 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_not_int: /* 0x7c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (124 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_long: /* 0x7d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (125 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_not_long: /* 0x7e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (126 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_float: /* 0x7f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (127 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_double: /* 0x80 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (128 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_long: /* 0x81 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (129 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_float: /* 0x82 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (130 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_double: /* 0x83 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (131 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_long_to_int: /* 0x84 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (132 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_long_to_float: /* 0x85 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (133 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_long_to_double: /* 0x86 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (134 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_float_to_int: /* 0x87 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (135 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_float_to_long: /* 0x88 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (136 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_float_to_double: /* 0x89 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (137 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_double_to_int: /* 0x8a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (138 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_double_to_long: /* 0x8b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (139 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_double_to_float: /* 0x8c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (140 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_byte: /* 0x8d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (141 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_char: /* 0x8e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (142 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_short: /* 0x8f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (143 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int: /* 0x90 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (144 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_int: /* 0x91 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (145 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int: /* 0x92 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (146 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int: /* 0x93 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (147 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int: /* 0x94 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (148 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int: /* 0x95 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (149 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int: /* 0x96 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (150 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int: /* 0x97 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (151 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_int: /* 0x98 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (152 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_int: /* 0x99 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (153 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_int: /* 0x9a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (154 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_long: /* 0x9b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (155 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_long: /* 0x9c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (156 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_long: /* 0x9d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (157 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_long: /* 0x9e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (158 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_long: /* 0x9f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (159 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_long: /* 0xa0 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (160 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_long: /* 0xa1 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (161 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_long: /* 0xa2 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (162 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_long: /* 0xa3 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (163 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_long: /* 0xa4 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (164 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_long: /* 0xa5 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (165 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_float: /* 0xa6 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (166 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_float: /* 0xa7 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (167 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_float: /* 0xa8 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (168 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_float: /* 0xa9 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (169 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_float: /* 0xaa */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (170 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_double: /* 0xab */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (171 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_double: /* 0xac */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (172 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_double: /* 0xad */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (173 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_double: /* 0xae */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (174 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_double: /* 0xaf */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (175 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int_2addr: /* 0xb0 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (176 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_int_2addr: /* 0xb1 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (177 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int_2addr: /* 0xb2 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (178 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int_2addr: /* 0xb3 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (179 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int_2addr: /* 0xb4 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (180 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int_2addr: /* 0xb5 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (181 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int_2addr: /* 0xb6 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (182 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int_2addr: /* 0xb7 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (183 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_int_2addr: /* 0xb8 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (184 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_int_2addr: /* 0xb9 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (185 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_int_2addr: /* 0xba */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (186 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_long_2addr: /* 0xbb */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (187 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_long_2addr: /* 0xbc */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (188 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_long_2addr: /* 0xbd */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (189 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_long_2addr: /* 0xbe */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (190 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_long_2addr: /* 0xbf */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (191 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_long_2addr: /* 0xc0 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (192 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_long_2addr: /* 0xc1 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (193 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_long_2addr: /* 0xc2 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (194 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_long_2addr: /* 0xc3 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (195 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_long_2addr: /* 0xc4 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (196 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_long_2addr: /* 0xc5 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (197 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_float_2addr: /* 0xc6 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (198 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_float_2addr: /* 0xc7 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (199 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_float_2addr: /* 0xc8 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (200 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_float_2addr: /* 0xc9 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (201 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_float_2addr: /* 0xca */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (202 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_double_2addr: /* 0xcb */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (203 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_double_2addr: /* 0xcc */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (204 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_double_2addr: /* 0xcd */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (205 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_double_2addr: /* 0xce */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (206 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_double_2addr: /* 0xcf */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (207 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int_lit16: /* 0xd0 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (208 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rsub_int: /* 0xd1 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (209 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int_lit16: /* 0xd2 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (210 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int_lit16: /* 0xd3 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (211 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int_lit16: /* 0xd4 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (212 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int_lit16: /* 0xd5 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (213 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int_lit16: /* 0xd6 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (214 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int_lit16: /* 0xd7 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (215 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int_lit8: /* 0xd8 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (216 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rsub_int_lit8: /* 0xd9 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (217 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int_lit8: /* 0xda */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (218 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int_lit8: /* 0xdb */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (219 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int_lit8: /* 0xdc */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (220 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int_lit8: /* 0xdd */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (221 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int_lit8: /* 0xde */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (222 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int_lit8: /* 0xdf */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (223 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_int_lit8: /* 0xe0 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (224 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_int_lit8: /* 0xe1 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (225 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_int_lit8: /* 0xe2 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (226 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_quick: /* 0xe3 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (227 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_wide_quick: /* 0xe4 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (228 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_object_quick: /* 0xe5 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (229 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_quick: /* 0xe6 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (230 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_wide_quick: /* 0xe7 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (231 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_object_quick: /* 0xe8 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (232 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual_quick: /* 0xe9 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (233 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual_range_quick: /* 0xea */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (234 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_boolean_quick: /* 0xeb */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (235 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_byte_quick: /* 0xec */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (236 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_char_quick: /* 0xed */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (237 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_short_quick: /* 0xee */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (238 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_boolean_quick: /* 0xef */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (239 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_byte_quick: /* 0xf0 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (240 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_char_quick: /* 0xf1 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (241 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_short_quick: /* 0xf2 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (242 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f3: /* 0xf3 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (243 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f4: /* 0xf4 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (244 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f5: /* 0xf5 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (245 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f6: /* 0xf6 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (246 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f7: /* 0xf7 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (247 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f8: /* 0xf8 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (248 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f9: /* 0xf9 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (249 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_polymorphic: /* 0xfa */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (250 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_polymorphic_range: /* 0xfb */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (251 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_custom: /* 0xfc */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (252 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_custom_range: /* 0xfd */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (253 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_method_handle: /* 0xfe */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (254 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_method_type: /* 0xff */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (255 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - - .balign 128 - - .type artMterpAsmAltInstructionEnd, #object - .hidden artMterpAsmAltInstructionEnd - .global artMterpAsmAltInstructionEnd -artMterpAsmAltInstructionEnd: - -// Close out the cfi info. We're treating mterp as a single function. - -END ExecuteMterpImpl - diff --git a/runtime/interpreter/mterp/out/mterp_mips.S b/runtime/interpreter/mterp/out/mterp_mips.S deleted file mode 100644 index ff2605dfcd..0000000000 --- a/runtime/interpreter/mterp/out/mterp_mips.S +++ /dev/null @@ -1,11398 +0,0 @@ -/* DO NOT EDIT: This file was generated by gen-mterp.py. */ -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - Art assembly interpreter notes: - - First validate assembly code by implementing ExecuteXXXImpl() style body (doesn't - handle invoke, allows higher-level code to create frame & shadow frame. - - Once that's working, support direct entry code & eliminate shadow frame (and - excess locals allocation. - - Some (hopefully) temporary ugliness. We'll treat rFP as pointing to the - base of the vreg array within the shadow frame. Access the other fields, - dex_pc_, method_ and number_of_vregs_ via negative offsets. For now, we'll continue - the shadow frame mechanism of double-storing object references - via rFP & - number_of_vregs_. - - */ - -#include "asm_support.h" -#include "interpreter/cfi_asm_support.h" - -#if (__mips==32) && (__mips_isa_rev>=2) -#define MIPS32REVGE2 /* mips32r2 and greater */ -#if (__mips==32) && (__mips_isa_rev>=5) -#define FPU64 /* 64 bit FPU */ -#if (__mips==32) && (__mips_isa_rev>=6) -#define MIPS32REVGE6 /* mips32r6 and greater */ -#endif -#endif -#endif - -/* MIPS definitions and declarations - - reg nick purpose - s0 rPC interpreted program counter, used for fetching instructions - s1 rFP interpreted frame pointer, used for accessing locals and args - s2 rSELF self (Thread) pointer - s3 rIBASE interpreted instruction base pointer, used for computed goto - s4 rINST first 16-bit code unit of current instruction - s5 rOBJ object pointer - s6 rREFS base of object references in shadow frame (ideally, we'll get rid of this later). - s7 rTEMP used as temp storage that can survive a function call - s8 rPROFILE branch profiling countdown - -*/ - -/* single-purpose registers, given names for clarity */ -#define rPC s0 -#define CFI_DEX 16 // DWARF register number of the register holding dex-pc (s0). -#define CFI_TMP 4 // DWARF register number of the first argument register (a0). -#define rFP s1 -#define rSELF s2 -#define rIBASE s3 -#define rINST s4 -#define rOBJ s5 -#define rREFS s6 -#define rTEMP s7 -#define rPROFILE s8 - -#define rARG0 a0 -#define rARG1 a1 -#define rARG2 a2 -#define rARG3 a3 -#define rRESULT0 v0 -#define rRESULT1 v1 - -/* GP register definitions */ -#define zero $0 /* always zero */ -#define AT $at /* assembler temp */ -#define v0 $2 /* return value */ -#define v1 $3 -#define a0 $4 /* argument registers */ -#define a1 $5 -#define a2 $6 -#define a3 $7 -#define t0 $8 /* temp registers (not saved across subroutine calls) */ -#define t1 $9 -#define t2 $10 -#define t3 $11 -#define t4 $12 -#define t5 $13 -#define t6 $14 -#define t7 $15 -#define ta0 $12 /* alias */ -#define ta1 $13 -#define ta2 $14 -#define ta3 $15 -#define s0 $16 /* saved across subroutine calls (callee saved) */ -#define s1 $17 -#define s2 $18 -#define s3 $19 -#define s4 $20 -#define s5 $21 -#define s6 $22 -#define s7 $23 -#define t8 $24 /* two more temp registers */ -#define t9 $25 -#define k0 $26 /* kernel temporary */ -#define k1 $27 -#define gp $28 /* global pointer */ -#define sp $29 /* stack pointer */ -#define s8 $30 /* one more callee saved */ -#define ra $31 /* return address */ - -/* FP register definitions */ -#define fv0 $f0 -#define fv0f $f1 -#define fv1 $f2 -#define fv1f $f3 -#define fa0 $f12 -#define fa0f $f13 -#define fa1 $f14 -#define fa1f $f15 -#define ft0 $f4 -#define ft0f $f5 -#define ft1 $f6 -#define ft1f $f7 -#define ft2 $f8 -#define ft2f $f9 -#define ft3 $f10 -#define ft3f $f11 -#define ft4 $f16 -#define ft4f $f17 -#define ft5 $f18 -#define ft5f $f19 -#define fs0 $f20 -#define fs0f $f21 -#define fs1 $f22 -#define fs1f $f23 -#define fs2 $f24 -#define fs2f $f25 -#define fs3 $f26 -#define fs3f $f27 -#define fs4 $f28 -#define fs4f $f29 -#define fs5 $f30 -#define fs5f $f31 - -#ifndef MIPS32REVGE6 -#define fcc0 $fcc0 -#define fcc1 $fcc1 -#endif - -#ifdef MIPS32REVGE2 -#define SEB(rd, rt) \ - seb rd, rt -#define SEH(rd, rt) \ - seh rd, rt -#define INSERT_HIGH_HALF(rd_lo, rt_hi) \ - ins rd_lo, rt_hi, 16, 16 -#else -#define SEB(rd, rt) \ - sll rd, rt, 24; \ - sra rd, rd, 24 -#define SEH(rd, rt) \ - sll rd, rt, 16; \ - sra rd, rd, 16 -/* Clobbers rt_hi on pre-R2. */ -#define INSERT_HIGH_HALF(rd_lo, rt_hi) \ - sll rt_hi, rt_hi, 16; \ - or rd_lo, rt_hi -#endif - -#ifdef FPU64 -#define MOVE_TO_FPU_HIGH(r, flo, fhi) \ - mthc1 r, flo -#else -#define MOVE_TO_FPU_HIGH(r, flo, fhi) \ - mtc1 r, fhi -#endif - -#ifdef MIPS32REVGE6 -#define JR(rt) \ - jic rt, 0 -#define LSA(rd, rs, rt, sa) \ - .if sa; \ - lsa rd, rs, rt, sa; \ - .else; \ - addu rd, rs, rt; \ - .endif -#else -#define JR(rt) \ - jalr zero, rt -#define LSA(rd, rs, rt, sa) \ - .if sa; \ - .set push; \ - .set noat; \ - sll AT, rs, sa; \ - addu rd, AT, rt; \ - .set pop; \ - .else; \ - addu rd, rs, rt; \ - .endif -#endif - -/* - * Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs. So, - * to access other shadow frame fields, we need to use a backwards offset. Define those here. - */ -#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) -#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) -#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) -#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) -#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) -#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) -#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) -#define OFF_FP_DEX_INSTRUCTIONS OFF_FP(SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET) -#define OFF_FP_SHADOWFRAME OFF_FP(0) - -#define MTERP_PROFILE_BRANCHES 1 -#define MTERP_LOGGING 0 - -/* - * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must - * be done *before* something throws. - * - * It's okay to do this more than once. - * - * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped - * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction - * offset into the code_items_[] array. For effiency, we will "export" the - * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC - * to convert to a dex pc when needed. - */ -#define EXPORT_PC() \ - sw rPC, OFF_FP_DEX_PC_PTR(rFP) - -#define EXPORT_DEX_PC(tmp) \ - lw tmp, OFF_FP_DEX_INSTRUCTIONS(rFP); \ - sw rPC, OFF_FP_DEX_PC_PTR(rFP); \ - subu tmp, rPC, tmp; \ - sra tmp, tmp, 1; \ - sw tmp, OFF_FP_DEX_PC(rFP) - -/* - * Fetch the next instruction from rPC into rINST. Does not advance rPC. - */ -#define FETCH_INST() lhu rINST, (rPC) - -/* - * Fetch the next instruction from the specified offset. Advances rPC - * to point to the next instruction. "_count" is in 16-bit code units. - * - * This must come AFTER anything that can throw an exception, or the - * exception catch may miss. (This also implies that it must come after - * EXPORT_PC().) - */ -#define FETCH_ADVANCE_INST(_count) \ - lhu rINST, ((_count)*2)(rPC); \ - addu rPC, rPC, ((_count) * 2) - -/* - * Similar to FETCH_ADVANCE_INST, but does not update rPC. Used to load - * rINST ahead of possible exception point. Be sure to manually advance rPC - * later. - */ -#define PREFETCH_INST(_count) lhu rINST, ((_count)*2)(rPC) - -/* Advance rPC by some number of code units. */ -#define ADVANCE(_count) addu rPC, rPC, ((_count) * 2) - -/* - * Fetch the next instruction from an offset specified by rd. Updates - * rPC to point to the next instruction. "rd" must specify the distance - * in bytes, *not* 16-bit code units, and may be a signed value. - */ -#define FETCH_ADVANCE_INST_RB(rd) \ - addu rPC, rPC, rd; \ - lhu rINST, (rPC) - -/* - * Fetch a half-word code unit from an offset past the current PC. The - * "_count" value is in 16-bit code units. Does not advance rPC. - * - * The "_S" variant works the same but treats the value as signed. - */ -#define FETCH(rd, _count) lhu rd, ((_count) * 2)(rPC) -#define FETCH_S(rd, _count) lh rd, ((_count) * 2)(rPC) - -/* - * Fetch one byte from an offset past the current PC. Pass in the same - * "_count" as you would for FETCH, and an additional 0/1 indicating which - * byte of the halfword you want (lo/hi). - */ -#define FETCH_B(rd, _count, _byte) lbu rd, ((_count) * 2 + _byte)(rPC) - -/* - * Put the instruction's opcode field into the specified register. - */ -#define GET_INST_OPCODE(rd) and rd, rINST, 0xFF - -/* - * Transform opcode into branch target address. - */ -#define GET_OPCODE_TARGET(rd) \ - sll rd, rd, 7; \ - addu rd, rIBASE, rd - -/* - * Begin executing the opcode in rd. - */ -#define GOTO_OPCODE(rd) \ - GET_OPCODE_TARGET(rd); \ - JR(rd) - -/* - * Get/set the 32-bit value from a Dalvik register. - */ -#define GET_VREG(rd, rix) LOAD_eas2(rd, rFP, rix) - -#define GET_VREG_F(rd, rix) \ - .set noat; \ - EAS2(AT, rFP, rix); \ - l.s rd, (AT); \ - .set at - -#ifdef MIPS32REVGE6 -#define SET_VREG(rd, rix) \ - lsa t8, rix, rFP, 2; \ - sw rd, 0(t8); \ - lsa t8, rix, rREFS, 2; \ - sw zero, 0(t8) -#else -#define SET_VREG(rd, rix) \ - .set noat; \ - sll AT, rix, 2; \ - addu t8, rFP, AT; \ - sw rd, 0(t8); \ - addu t8, rREFS, AT; \ - .set at; \ - sw zero, 0(t8) -#endif - -#ifdef MIPS32REVGE6 -#define SET_VREG_OBJECT(rd, rix) \ - lsa t8, rix, rFP, 2; \ - sw rd, 0(t8); \ - lsa t8, rix, rREFS, 2; \ - sw rd, 0(t8) -#else -#define SET_VREG_OBJECT(rd, rix) \ - .set noat; \ - sll AT, rix, 2; \ - addu t8, rFP, AT; \ - sw rd, 0(t8); \ - addu t8, rREFS, AT; \ - .set at; \ - sw rd, 0(t8) -#endif - -#ifdef MIPS32REVGE6 -#define SET_VREG64(rlo, rhi, rix) \ - lsa t8, rix, rFP, 2; \ - sw rlo, 0(t8); \ - sw rhi, 4(t8); \ - lsa t8, rix, rREFS, 2; \ - sw zero, 0(t8); \ - sw zero, 4(t8) -#else -#define SET_VREG64(rlo, rhi, rix) \ - .set noat; \ - sll AT, rix, 2; \ - addu t8, rFP, AT; \ - sw rlo, 0(t8); \ - sw rhi, 4(t8); \ - addu t8, rREFS, AT; \ - .set at; \ - sw zero, 0(t8); \ - sw zero, 4(t8) -#endif - -#ifdef MIPS32REVGE6 -#define SET_VREG_F(rd, rix) \ - lsa t8, rix, rFP, 2; \ - s.s rd, 0(t8); \ - lsa t8, rix, rREFS, 2; \ - sw zero, 0(t8) -#else -#define SET_VREG_F(rd, rix) \ - .set noat; \ - sll AT, rix, 2; \ - addu t8, rFP, AT; \ - s.s rd, 0(t8); \ - addu t8, rREFS, AT; \ - .set at; \ - sw zero, 0(t8) -#endif - -#ifdef MIPS32REVGE6 -#define SET_VREG64_F(rlo, rhi, rix) \ - lsa t8, rix, rFP, 2; \ - .set noat; \ - mfhc1 AT, rlo; \ - s.s rlo, 0(t8); \ - sw AT, 4(t8); \ - .set at; \ - lsa t8, rix, rREFS, 2; \ - sw zero, 0(t8); \ - sw zero, 4(t8) -#elif defined(FPU64) -#define SET_VREG64_F(rlo, rhi, rix) \ - .set noat; \ - sll AT, rix, 2; \ - addu t8, rREFS, AT; \ - sw zero, 0(t8); \ - sw zero, 4(t8); \ - addu t8, rFP, AT; \ - mfhc1 AT, rlo; \ - sw AT, 4(t8); \ - .set at; \ - s.s rlo, 0(t8) -#else -#define SET_VREG64_F(rlo, rhi, rix) \ - .set noat; \ - sll AT, rix, 2; \ - addu t8, rFP, AT; \ - s.s rlo, 0(t8); \ - s.s rhi, 4(t8); \ - addu t8, rREFS, AT; \ - .set at; \ - sw zero, 0(t8); \ - sw zero, 4(t8) -#endif - -/* Combination of the SET_VREG and GOTO_OPCODE functions to save 1 instruction */ -#ifdef MIPS32REVGE6 -#define SET_VREG_GOTO(rd, rix, dst) \ - .set noreorder; \ - GET_OPCODE_TARGET(dst); \ - lsa t8, rix, rFP, 2; \ - sw rd, 0(t8); \ - lsa t8, rix, rREFS, 2; \ - jalr zero, dst; \ - sw zero, 0(t8); \ - .set reorder -#else -#define SET_VREG_GOTO(rd, rix, dst) \ - .set noreorder; \ - GET_OPCODE_TARGET(dst); \ - .set noat; \ - sll AT, rix, 2; \ - addu t8, rFP, AT; \ - sw rd, 0(t8); \ - addu t8, rREFS, AT; \ - .set at; \ - jalr zero, dst; \ - sw zero, 0(t8); \ - .set reorder -#endif - -/* Combination of the SET_VREG_OBJECT and GOTO_OPCODE functions to save 1 instruction */ -#ifdef MIPS32REVGE6 -#define SET_VREG_OBJECT_GOTO(rd, rix, dst) \ - .set noreorder; \ - GET_OPCODE_TARGET(dst); \ - lsa t8, rix, rFP, 2; \ - sw rd, 0(t8); \ - lsa t8, rix, rREFS, 2; \ - jalr zero, dst; \ - sw rd, 0(t8); \ - .set reorder -#else -#define SET_VREG_OBJECT_GOTO(rd, rix, dst) \ - .set noreorder; \ - GET_OPCODE_TARGET(dst); \ - .set noat; \ - sll AT, rix, 2; \ - addu t8, rFP, AT; \ - sw rd, 0(t8); \ - addu t8, rREFS, AT; \ - .set at; \ - jalr zero, dst; \ - sw rd, 0(t8); \ - .set reorder -#endif - -/* Combination of the SET_VREG64 and GOTO_OPCODE functions to save 1 instruction */ -#ifdef MIPS32REVGE6 -#define SET_VREG64_GOTO(rlo, rhi, rix, dst) \ - .set noreorder; \ - GET_OPCODE_TARGET(dst); \ - lsa t8, rix, rFP, 2; \ - sw rlo, 0(t8); \ - sw rhi, 4(t8); \ - lsa t8, rix, rREFS, 2; \ - sw zero, 0(t8); \ - jalr zero, dst; \ - sw zero, 4(t8); \ - .set reorder -#else -#define SET_VREG64_GOTO(rlo, rhi, rix, dst) \ - .set noreorder; \ - GET_OPCODE_TARGET(dst); \ - .set noat; \ - sll AT, rix, 2; \ - addu t8, rFP, AT; \ - sw rlo, 0(t8); \ - sw rhi, 4(t8); \ - addu t8, rREFS, AT; \ - .set at; \ - sw zero, 0(t8); \ - jalr zero, dst; \ - sw zero, 4(t8); \ - .set reorder -#endif - -/* Combination of the SET_VREG_F and GOTO_OPCODE functions to save 1 instruction */ -#ifdef MIPS32REVGE6 -#define SET_VREG_F_GOTO(rd, rix, dst) \ - .set noreorder; \ - GET_OPCODE_TARGET(dst); \ - lsa t8, rix, rFP, 2; \ - s.s rd, 0(t8); \ - lsa t8, rix, rREFS, 2; \ - jalr zero, dst; \ - sw zero, 0(t8); \ - .set reorder -#else -#define SET_VREG_F_GOTO(rd, rix, dst) \ - .set noreorder; \ - GET_OPCODE_TARGET(dst); \ - .set noat; \ - sll AT, rix, 2; \ - addu t8, rFP, AT; \ - s.s rd, 0(t8); \ - addu t8, rREFS, AT; \ - .set at; \ - jalr zero, dst; \ - sw zero, 0(t8); \ - .set reorder -#endif - -/* Combination of the SET_VREG64_F and GOTO_OPCODE functions to save 1 instruction */ -#ifdef MIPS32REVGE6 -#define SET_VREG64_F_GOTO(rlo, rhi, rix, dst) \ - .set noreorder; \ - GET_OPCODE_TARGET(dst); \ - lsa t8, rix, rFP, 2; \ - .set noat; \ - mfhc1 AT, rlo; \ - s.s rlo, 0(t8); \ - sw AT, 4(t8); \ - .set at; \ - lsa t8, rix, rREFS, 2; \ - sw zero, 0(t8); \ - jalr zero, dst; \ - sw zero, 4(t8); \ - .set reorder -#elif defined(FPU64) -#define SET_VREG64_F_GOTO(rlo, rhi, rix, dst) \ - .set noreorder; \ - GET_OPCODE_TARGET(dst); \ - .set noat; \ - sll AT, rix, 2; \ - addu t8, rREFS, AT; \ - sw zero, 0(t8); \ - sw zero, 4(t8); \ - addu t8, rFP, AT; \ - mfhc1 AT, rlo; \ - sw AT, 4(t8); \ - .set at; \ - jalr zero, dst; \ - s.s rlo, 0(t8); \ - .set reorder -#else -#define SET_VREG64_F_GOTO(rlo, rhi, rix, dst) \ - .set noreorder; \ - GET_OPCODE_TARGET(dst); \ - .set noat; \ - sll AT, rix, 2; \ - addu t8, rFP, AT; \ - s.s rlo, 0(t8); \ - s.s rhi, 4(t8); \ - addu t8, rREFS, AT; \ - .set at; \ - sw zero, 0(t8); \ - jalr zero, dst; \ - sw zero, 4(t8); \ - .set reorder -#endif - -#define GET_OPA(rd) srl rd, rINST, 8 -#ifdef MIPS32REVGE2 -#define GET_OPA4(rd) ext rd, rINST, 8, 4 -#else -#define GET_OPA4(rd) GET_OPA(rd); and rd, 0xf -#endif -#define GET_OPB(rd) srl rd, rINST, 12 - -/* - * Form an Effective Address rd = rbase + roff<exception <- obj - b MterpException - -/* ------------------------------ */ - .balign 128 -.L_op_goto: /* 0x28 */ - /* - * Unconditional branch, 8-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto +AA */ - sll a0, rINST, 16 # a0 <- AAxx0000 - sra rINST, a0, 24 # rINST <- ssssssAA (sign-extended) - b MterpCommonTakenBranchNoFlags - -/* ------------------------------ */ - .balign 128 -.L_op_goto_16: /* 0x29 */ - /* - * Unconditional branch, 16-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto/16 +AAAA */ - FETCH_S(rINST, 1) # rINST <- ssssAAAA (sign-extended) - b MterpCommonTakenBranchNoFlags - -/* ------------------------------ */ - .balign 128 -.L_op_goto_32: /* 0x2a */ - /* - * Unconditional branch, 32-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - * - * Unlike most opcodes, this one is allowed to branch to itself, so - * our "backward branch" test must be "<=0" instead of "<0". - */ - /* goto/32 +AAAAAAAA */ - FETCH(rINST, 1) # rINST <- aaaa (lo) - FETCH(a1, 2) # a1 <- AAAA (hi) - INSERT_HIGH_HALF(rINST, a1) # rINST <- AAAAaaaa - b MterpCommonTakenBranchNoFlags - -/* ------------------------------ */ - .balign 128 -.L_op_packed_switch: /* 0x2b */ - /* - * Handle a packed-switch or sparse-switch instruction. In both cases - * we decode it and hand it off to a helper function. - * - * We don't really expect backward branches in a switch statement, but - * they're perfectly legal, so we check for them here. - * - * for: packed-switch, sparse-switch - */ - /* op vAA, +BBBB */ - FETCH(a0, 1) # a0 <- bbbb (lo) - FETCH(a1, 2) # a1 <- BBBB (hi) - GET_OPA(a3) # a3 <- AA - INSERT_HIGH_HALF(a0, a1) # a0 <- BBBBbbbb - GET_VREG(a1, a3) # a1 <- vAA - EAS1(a0, rPC, a0) # a0 <- PC + BBBBbbbb*2 - JAL(MterpDoPackedSwitch) # a0 <- code-unit branch offset - move rINST, v0 - b MterpCommonTakenBranchNoFlags - -/* ------------------------------ */ - .balign 128 -.L_op_sparse_switch: /* 0x2c */ - /* - * Handle a packed-switch or sparse-switch instruction. In both cases - * we decode it and hand it off to a helper function. - * - * We don't really expect backward branches in a switch statement, but - * they're perfectly legal, so we check for them here. - * - * for: packed-switch, sparse-switch - */ - /* op vAA, +BBBB */ - FETCH(a0, 1) # a0 <- bbbb (lo) - FETCH(a1, 2) # a1 <- BBBB (hi) - GET_OPA(a3) # a3 <- AA - INSERT_HIGH_HALF(a0, a1) # a0 <- BBBBbbbb - GET_VREG(a1, a3) # a1 <- vAA - EAS1(a0, rPC, a0) # a0 <- PC + BBBBbbbb*2 - JAL(MterpDoSparseSwitch) # a0 <- code-unit branch offset - move rINST, v0 - b MterpCommonTakenBranchNoFlags - -/* ------------------------------ */ - .balign 128 -.L_op_cmpl_float: /* 0x2d */ - /* - * Compare two floating-point values. Puts 0(==), 1(>), or -1(<) - * into the destination register based on the comparison results. - * - * for: cmpl-float, cmpg-float - */ - /* op vAA, vBB, vCC */ - - FETCH(a0, 1) # a0 <- CCBB - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 - GET_VREG_F(ft0, a2) - GET_VREG_F(ft1, a3) -#ifdef MIPS32REVGE6 - cmp.eq.s ft2, ft0, ft1 - li rTEMP, 0 - bc1nez ft2, 1f # done if vBB == vCC (ordered) - .if 0 - cmp.lt.s ft2, ft0, ft1 - li rTEMP, -1 - bc1nez ft2, 1f # done if vBB < vCC (ordered) - li rTEMP, 1 # vBB > vCC or unordered - .else - cmp.lt.s ft2, ft1, ft0 - li rTEMP, 1 - bc1nez ft2, 1f # done if vBB > vCC (ordered) - li rTEMP, -1 # vBB < vCC or unordered - .endif -#else - c.eq.s fcc0, ft0, ft1 - li rTEMP, 0 - bc1t fcc0, 1f # done if vBB == vCC (ordered) - .if 0 - c.olt.s fcc0, ft0, ft1 - li rTEMP, -1 - bc1t fcc0, 1f # done if vBB < vCC (ordered) - li rTEMP, 1 # vBB > vCC or unordered - .else - c.olt.s fcc0, ft1, ft0 - li rTEMP, 1 - bc1t fcc0, 1f # done if vBB > vCC (ordered) - li rTEMP, -1 # vBB < vCC or unordered - .endif -#endif -1: - GET_OPA(rOBJ) - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(rTEMP, rOBJ, t0) # vAA <- rTEMP - -/* ------------------------------ */ - .balign 128 -.L_op_cmpg_float: /* 0x2e */ - /* - * Compare two floating-point values. Puts 0(==), 1(>), or -1(<) - * into the destination register based on the comparison results. - * - * for: cmpl-float, cmpg-float - */ - /* op vAA, vBB, vCC */ - - FETCH(a0, 1) # a0 <- CCBB - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 - GET_VREG_F(ft0, a2) - GET_VREG_F(ft1, a3) -#ifdef MIPS32REVGE6 - cmp.eq.s ft2, ft0, ft1 - li rTEMP, 0 - bc1nez ft2, 1f # done if vBB == vCC (ordered) - .if 1 - cmp.lt.s ft2, ft0, ft1 - li rTEMP, -1 - bc1nez ft2, 1f # done if vBB < vCC (ordered) - li rTEMP, 1 # vBB > vCC or unordered - .else - cmp.lt.s ft2, ft1, ft0 - li rTEMP, 1 - bc1nez ft2, 1f # done if vBB > vCC (ordered) - li rTEMP, -1 # vBB < vCC or unordered - .endif -#else - c.eq.s fcc0, ft0, ft1 - li rTEMP, 0 - bc1t fcc0, 1f # done if vBB == vCC (ordered) - .if 1 - c.olt.s fcc0, ft0, ft1 - li rTEMP, -1 - bc1t fcc0, 1f # done if vBB < vCC (ordered) - li rTEMP, 1 # vBB > vCC or unordered - .else - c.olt.s fcc0, ft1, ft0 - li rTEMP, 1 - bc1t fcc0, 1f # done if vBB > vCC (ordered) - li rTEMP, -1 # vBB < vCC or unordered - .endif -#endif -1: - GET_OPA(rOBJ) - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(rTEMP, rOBJ, t0) # vAA <- rTEMP - -/* ------------------------------ */ - .balign 128 -.L_op_cmpl_double: /* 0x2f */ - /* - * Compare two floating-point values. Puts 0(==), 1(>), or -1(<) - * into the destination register based on the comparison results. - * - * For: cmpl-double, cmpg-double - */ - /* op vAA, vBB, vCC */ - - FETCH(a0, 1) # a0 <- CCBB - and rOBJ, a0, 255 # rOBJ <- BB - srl t0, a0, 8 # t0 <- CC - EAS2(rOBJ, rFP, rOBJ) # rOBJ <- &fp[BB] - EAS2(t0, rFP, t0) # t0 <- &fp[CC] - LOAD64_F(ft0, ft0f, rOBJ) - LOAD64_F(ft1, ft1f, t0) -#ifdef MIPS32REVGE6 - cmp.eq.d ft2, ft0, ft1 - li rTEMP, 0 - bc1nez ft2, 1f # done if vBB == vCC (ordered) - .if 0 - cmp.lt.d ft2, ft0, ft1 - li rTEMP, -1 - bc1nez ft2, 1f # done if vBB < vCC (ordered) - li rTEMP, 1 # vBB > vCC or unordered - .else - cmp.lt.d ft2, ft1, ft0 - li rTEMP, 1 - bc1nez ft2, 1f # done if vBB > vCC (ordered) - li rTEMP, -1 # vBB < vCC or unordered - .endif -#else - c.eq.d fcc0, ft0, ft1 - li rTEMP, 0 - bc1t fcc0, 1f # done if vBB == vCC (ordered) - .if 0 - c.olt.d fcc0, ft0, ft1 - li rTEMP, -1 - bc1t fcc0, 1f # done if vBB < vCC (ordered) - li rTEMP, 1 # vBB > vCC or unordered - .else - c.olt.d fcc0, ft1, ft0 - li rTEMP, 1 - bc1t fcc0, 1f # done if vBB > vCC (ordered) - li rTEMP, -1 # vBB < vCC or unordered - .endif -#endif -1: - GET_OPA(rOBJ) - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(rTEMP, rOBJ, t0) # vAA <- rTEMP - -/* ------------------------------ */ - .balign 128 -.L_op_cmpg_double: /* 0x30 */ - /* - * Compare two floating-point values. Puts 0(==), 1(>), or -1(<) - * into the destination register based on the comparison results. - * - * For: cmpl-double, cmpg-double - */ - /* op vAA, vBB, vCC */ - - FETCH(a0, 1) # a0 <- CCBB - and rOBJ, a0, 255 # rOBJ <- BB - srl t0, a0, 8 # t0 <- CC - EAS2(rOBJ, rFP, rOBJ) # rOBJ <- &fp[BB] - EAS2(t0, rFP, t0) # t0 <- &fp[CC] - LOAD64_F(ft0, ft0f, rOBJ) - LOAD64_F(ft1, ft1f, t0) -#ifdef MIPS32REVGE6 - cmp.eq.d ft2, ft0, ft1 - li rTEMP, 0 - bc1nez ft2, 1f # done if vBB == vCC (ordered) - .if 1 - cmp.lt.d ft2, ft0, ft1 - li rTEMP, -1 - bc1nez ft2, 1f # done if vBB < vCC (ordered) - li rTEMP, 1 # vBB > vCC or unordered - .else - cmp.lt.d ft2, ft1, ft0 - li rTEMP, 1 - bc1nez ft2, 1f # done if vBB > vCC (ordered) - li rTEMP, -1 # vBB < vCC or unordered - .endif -#else - c.eq.d fcc0, ft0, ft1 - li rTEMP, 0 - bc1t fcc0, 1f # done if vBB == vCC (ordered) - .if 1 - c.olt.d fcc0, ft0, ft1 - li rTEMP, -1 - bc1t fcc0, 1f # done if vBB < vCC (ordered) - li rTEMP, 1 # vBB > vCC or unordered - .else - c.olt.d fcc0, ft1, ft0 - li rTEMP, 1 - bc1t fcc0, 1f # done if vBB > vCC (ordered) - li rTEMP, -1 # vBB < vCC or unordered - .endif -#endif -1: - GET_OPA(rOBJ) - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(rTEMP, rOBJ, t0) # vAA <- rTEMP - -/* ------------------------------ */ - .balign 128 -.L_op_cmp_long: /* 0x31 */ - /* - * Compare two 64-bit values - * x = y return 0 - * x < y return -1 - * x > y return 1 - * - * I think I can improve on the ARM code by the following observation - * slt t0, x.hi, y.hi; # (x.hi < y.hi) ? 1:0 - * sgt t1, x.hi, y.hi; # (y.hi > x.hi) ? 1:0 - * subu v0, t0, t1 # v0= -1:1:0 for [ < > = ] - */ - /* cmp-long vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 # a3 <- CC - EAS2(a2, rFP, a2) # a2 <- &fp[BB] - EAS2(a3, rFP, a3) # a3 <- &fp[CC] - LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 - LOAD64(a2, a3, a3) # a2/a3 <- vCC/vCC+1 - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - slt t0, a1, a3 # compare hi - sgt t1, a1, a3 - subu v0, t1, t0 # v0 <- (-1, 1, 0) - bnez v0, .Lop_cmp_long_finish - # at this point x.hi==y.hi - sltu t0, a0, a2 # compare lo - sgtu t1, a0, a2 - subu v0, t1, t0 # v0 <- (-1, 1, 0) for [< > =] - -.Lop_cmp_long_finish: - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(v0, rOBJ, t0) # vAA <- v0 - -/* ------------------------------ */ - .balign 128 -.L_op_if_eq: /* 0x32 */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - GET_OPA4(a0) # a0 <- A+ - GET_OPB(a1) # a1 <- B - GET_VREG(a3, a1) # a3 <- vB - GET_VREG(a0, a0) # a0 <- vA - FETCH_S(rINST, 1) # rINST<- branch offset, in code units - beq a0, a3, MterpCommonTakenBranchNoFlags # compare (vA, vB) - li t0, JIT_CHECK_OSR - beq rPROFILE, t0, .L_check_not_taken_osr - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_ne: /* 0x33 */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - GET_OPA4(a0) # a0 <- A+ - GET_OPB(a1) # a1 <- B - GET_VREG(a3, a1) # a3 <- vB - GET_VREG(a0, a0) # a0 <- vA - FETCH_S(rINST, 1) # rINST<- branch offset, in code units - bne a0, a3, MterpCommonTakenBranchNoFlags # compare (vA, vB) - li t0, JIT_CHECK_OSR - beq rPROFILE, t0, .L_check_not_taken_osr - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_lt: /* 0x34 */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - GET_OPA4(a0) # a0 <- A+ - GET_OPB(a1) # a1 <- B - GET_VREG(a3, a1) # a3 <- vB - GET_VREG(a0, a0) # a0 <- vA - FETCH_S(rINST, 1) # rINST<- branch offset, in code units - blt a0, a3, MterpCommonTakenBranchNoFlags # compare (vA, vB) - li t0, JIT_CHECK_OSR - beq rPROFILE, t0, .L_check_not_taken_osr - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_ge: /* 0x35 */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - GET_OPA4(a0) # a0 <- A+ - GET_OPB(a1) # a1 <- B - GET_VREG(a3, a1) # a3 <- vB - GET_VREG(a0, a0) # a0 <- vA - FETCH_S(rINST, 1) # rINST<- branch offset, in code units - bge a0, a3, MterpCommonTakenBranchNoFlags # compare (vA, vB) - li t0, JIT_CHECK_OSR - beq rPROFILE, t0, .L_check_not_taken_osr - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_gt: /* 0x36 */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - GET_OPA4(a0) # a0 <- A+ - GET_OPB(a1) # a1 <- B - GET_VREG(a3, a1) # a3 <- vB - GET_VREG(a0, a0) # a0 <- vA - FETCH_S(rINST, 1) # rINST<- branch offset, in code units - bgt a0, a3, MterpCommonTakenBranchNoFlags # compare (vA, vB) - li t0, JIT_CHECK_OSR - beq rPROFILE, t0, .L_check_not_taken_osr - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_le: /* 0x37 */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - GET_OPA4(a0) # a0 <- A+ - GET_OPB(a1) # a1 <- B - GET_VREG(a3, a1) # a3 <- vB - GET_VREG(a0, a0) # a0 <- vA - FETCH_S(rINST, 1) # rINST<- branch offset, in code units - ble a0, a3, MterpCommonTakenBranchNoFlags # compare (vA, vB) - li t0, JIT_CHECK_OSR - beq rPROFILE, t0, .L_check_not_taken_osr - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_eqz: /* 0x38 */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - GET_OPA(a0) # a0 <- AA - GET_VREG(a0, a0) # a0 <- vAA - FETCH_S(rINST, 1) # rINST <- branch offset, in code units - beq a0, zero, MterpCommonTakenBranchNoFlags - li t0, JIT_CHECK_OSR # possible OSR re-entry? - beq rPROFILE, t0, .L_check_not_taken_osr - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_nez: /* 0x39 */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - GET_OPA(a0) # a0 <- AA - GET_VREG(a0, a0) # a0 <- vAA - FETCH_S(rINST, 1) # rINST <- branch offset, in code units - bne a0, zero, MterpCommonTakenBranchNoFlags - li t0, JIT_CHECK_OSR # possible OSR re-entry? - beq rPROFILE, t0, .L_check_not_taken_osr - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_ltz: /* 0x3a */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - GET_OPA(a0) # a0 <- AA - GET_VREG(a0, a0) # a0 <- vAA - FETCH_S(rINST, 1) # rINST <- branch offset, in code units - blt a0, zero, MterpCommonTakenBranchNoFlags - li t0, JIT_CHECK_OSR # possible OSR re-entry? - beq rPROFILE, t0, .L_check_not_taken_osr - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_gez: /* 0x3b */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - GET_OPA(a0) # a0 <- AA - GET_VREG(a0, a0) # a0 <- vAA - FETCH_S(rINST, 1) # rINST <- branch offset, in code units - bge a0, zero, MterpCommonTakenBranchNoFlags - li t0, JIT_CHECK_OSR # possible OSR re-entry? - beq rPROFILE, t0, .L_check_not_taken_osr - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_gtz: /* 0x3c */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - GET_OPA(a0) # a0 <- AA - GET_VREG(a0, a0) # a0 <- vAA - FETCH_S(rINST, 1) # rINST <- branch offset, in code units - bgt a0, zero, MterpCommonTakenBranchNoFlags - li t0, JIT_CHECK_OSR # possible OSR re-entry? - beq rPROFILE, t0, .L_check_not_taken_osr - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_lez: /* 0x3d */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - GET_OPA(a0) # a0 <- AA - GET_VREG(a0, a0) # a0 <- vAA - FETCH_S(rINST, 1) # rINST <- branch offset, in code units - ble a0, zero, MterpCommonTakenBranchNoFlags - li t0, JIT_CHECK_OSR # possible OSR re-entry? - beq rPROFILE, t0, .L_check_not_taken_osr - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_unused_3e: /* 0x3e */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_3f: /* 0x3f */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_40: /* 0x40 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_41: /* 0x41 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_42: /* 0x42 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_43: /* 0x43 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_aget: /* 0x44 */ - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B(a2, 1, 0) # a2 <- BB - GET_OPA(rOBJ) # rOBJ <- AA - FETCH_B(a3, 1, 1) # a3 <- CC - GET_VREG(a0, a2) # a0 <- vBB (array object) - GET_VREG(a1, a3) # a1 <- vCC (requested index) - # null array object? - beqz a0, common_errNullObject # yes, bail - LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length - EASN(a0, a0, a1, 2) # a0 <- arrayObj + index*width - # a1 >= a3; compare unsigned index - bgeu a1, a3, common_errArrayIndex # index >= length, bail - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - lw a2, MIRROR_INT_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a2, rOBJ, t0) # vAA <- a2 - -/* ------------------------------ */ - .balign 128 -.L_op_aget_wide: /* 0x45 */ - /* - * Array get, 64 bits. vAA <- vBB[vCC]. - * - * Arrays of long/double are 64-bit aligned. - */ - /* aget-wide vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 # a3 <- CC - GET_VREG(a0, a2) # a0 <- vBB (array object) - GET_VREG(a1, a3) # a1 <- vCC (requested index) - # null array object? - beqz a0, common_errNullObject # yes, bail - LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length - EAS3(a0, a0, a1) # a0 <- arrayObj + index*width - bgeu a1, a3, common_errArrayIndex # index >= length, bail - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - LOAD64_off(a2, a3, a0, MIRROR_WIDE_ARRAY_DATA_OFFSET) - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(a2, a3, rOBJ, t0) # vAA/vAA+1 <- a2/a3 - -/* ------------------------------ */ - .balign 128 -.L_op_aget_object: /* 0x46 */ - /* - * Array object get. vAA <- vBB[vCC]. - * - * for: aget-object - */ - /* op vAA, vBB, vCC */ - FETCH_B(a2, 1, 0) # a2 <- BB - GET_OPA(rOBJ) # rOBJ <- AA - FETCH_B(a3, 1, 1) # a3 <- CC - EXPORT_PC() - GET_VREG(a0, a2) # a0 <- vBB (array object) - GET_VREG(a1, a3) # a1 <- vCC (requested index) - JAL(artAGetObjectFromMterp) # v0 <- GetObj(array, index) - lw a1, THREAD_EXCEPTION_OFFSET(rSELF) - PREFETCH_INST(2) # load rINST - bnez a1, MterpException - ADVANCE(2) # advance rPC - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_OBJECT_GOTO(v0, rOBJ, t0) # vAA <- v0 - -/* ------------------------------ */ - .balign 128 -.L_op_aget_boolean: /* 0x47 */ - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B(a2, 1, 0) # a2 <- BB - GET_OPA(rOBJ) # rOBJ <- AA - FETCH_B(a3, 1, 1) # a3 <- CC - GET_VREG(a0, a2) # a0 <- vBB (array object) - GET_VREG(a1, a3) # a1 <- vCC (requested index) - # null array object? - beqz a0, common_errNullObject # yes, bail - LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length - EASN(a0, a0, a1, 0) # a0 <- arrayObj + index*width - # a1 >= a3; compare unsigned index - bgeu a1, a3, common_errArrayIndex # index >= length, bail - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - lbu a2, MIRROR_BOOLEAN_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a2, rOBJ, t0) # vAA <- a2 - -/* ------------------------------ */ - .balign 128 -.L_op_aget_byte: /* 0x48 */ - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B(a2, 1, 0) # a2 <- BB - GET_OPA(rOBJ) # rOBJ <- AA - FETCH_B(a3, 1, 1) # a3 <- CC - GET_VREG(a0, a2) # a0 <- vBB (array object) - GET_VREG(a1, a3) # a1 <- vCC (requested index) - # null array object? - beqz a0, common_errNullObject # yes, bail - LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length - EASN(a0, a0, a1, 0) # a0 <- arrayObj + index*width - # a1 >= a3; compare unsigned index - bgeu a1, a3, common_errArrayIndex # index >= length, bail - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - lb a2, MIRROR_BYTE_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a2, rOBJ, t0) # vAA <- a2 - -/* ------------------------------ */ - .balign 128 -.L_op_aget_char: /* 0x49 */ - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B(a2, 1, 0) # a2 <- BB - GET_OPA(rOBJ) # rOBJ <- AA - FETCH_B(a3, 1, 1) # a3 <- CC - GET_VREG(a0, a2) # a0 <- vBB (array object) - GET_VREG(a1, a3) # a1 <- vCC (requested index) - # null array object? - beqz a0, common_errNullObject # yes, bail - LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length - EASN(a0, a0, a1, 1) # a0 <- arrayObj + index*width - # a1 >= a3; compare unsigned index - bgeu a1, a3, common_errArrayIndex # index >= length, bail - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - lhu a2, MIRROR_CHAR_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a2, rOBJ, t0) # vAA <- a2 - -/* ------------------------------ */ - .balign 128 -.L_op_aget_short: /* 0x4a */ - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B(a2, 1, 0) # a2 <- BB - GET_OPA(rOBJ) # rOBJ <- AA - FETCH_B(a3, 1, 1) # a3 <- CC - GET_VREG(a0, a2) # a0 <- vBB (array object) - GET_VREG(a1, a3) # a1 <- vCC (requested index) - # null array object? - beqz a0, common_errNullObject # yes, bail - LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length - EASN(a0, a0, a1, 1) # a0 <- arrayObj + index*width - # a1 >= a3; compare unsigned index - bgeu a1, a3, common_errArrayIndex # index >= length, bail - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - lh a2, MIRROR_SHORT_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a2, rOBJ, t0) # vAA <- a2 - -/* ------------------------------ */ - .balign 128 -.L_op_aput: /* 0x4b */ - - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B(a2, 1, 0) # a2 <- BB - GET_OPA(rOBJ) # rOBJ <- AA - FETCH_B(a3, 1, 1) # a3 <- CC - GET_VREG(a0, a2) # a0 <- vBB (array object) - GET_VREG(a1, a3) # a1 <- vCC (requested index) - # null array object? - beqz a0, common_errNullObject # yes, bail - LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length - EASN(a0, a0, a1, 2) # a0 <- arrayObj + index*width - bgeu a1, a3, common_errArrayIndex # index >= length, bail - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_VREG(a2, rOBJ) # a2 <- vAA - GET_INST_OPCODE(t0) # extract opcode from rINST - GET_OPCODE_TARGET(t0) - sw a2, MIRROR_INT_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 - JR(t0) # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aput_wide: /* 0x4c */ - /* - * Array put, 64 bits. vBB[vCC] <- vAA. - */ - /* aput-wide vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(t0) # t0 <- AA - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 # a3 <- CC - GET_VREG(a0, a2) # a0 <- vBB (array object) - GET_VREG(a1, a3) # a1 <- vCC (requested index) - # null array object? - beqz a0, common_errNullObject # yes, bail - LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length - EAS3(a0, a0, a1) # a0 <- arrayObj + index*width - EAS2(rOBJ, rFP, t0) # rOBJ <- &fp[AA] - # compare unsigned index, length - bgeu a1, a3, common_errArrayIndex # index >= length, bail - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - LOAD64(a2, a3, rOBJ) # a2/a3 <- vAA/vAA+1 - GET_INST_OPCODE(t0) # extract opcode from rINST - GET_OPCODE_TARGET(t0) - STORE64_off(a2, a3, a0, MIRROR_WIDE_ARRAY_DATA_OFFSET) # a2/a3 <- vBB[vCC] - JR(t0) # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aput_object: /* 0x4d */ - /* - * Store an object into an array. vBB[vCC] <- vAA. - * - */ - /* op vAA, vBB, vCC */ - EXPORT_PC() - addu a0, rFP, OFF_FP_SHADOWFRAME - move a1, rPC - move a2, rINST - JAL(MterpAputObject) - beqz v0, MterpPossibleException - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aput_boolean: /* 0x4e */ - - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B(a2, 1, 0) # a2 <- BB - GET_OPA(rOBJ) # rOBJ <- AA - FETCH_B(a3, 1, 1) # a3 <- CC - GET_VREG(a0, a2) # a0 <- vBB (array object) - GET_VREG(a1, a3) # a1 <- vCC (requested index) - # null array object? - beqz a0, common_errNullObject # yes, bail - LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length - EASN(a0, a0, a1, 0) # a0 <- arrayObj + index*width - bgeu a1, a3, common_errArrayIndex # index >= length, bail - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_VREG(a2, rOBJ) # a2 <- vAA - GET_INST_OPCODE(t0) # extract opcode from rINST - GET_OPCODE_TARGET(t0) - sb a2, MIRROR_BOOLEAN_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 - JR(t0) # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aput_byte: /* 0x4f */ - - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B(a2, 1, 0) # a2 <- BB - GET_OPA(rOBJ) # rOBJ <- AA - FETCH_B(a3, 1, 1) # a3 <- CC - GET_VREG(a0, a2) # a0 <- vBB (array object) - GET_VREG(a1, a3) # a1 <- vCC (requested index) - # null array object? - beqz a0, common_errNullObject # yes, bail - LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length - EASN(a0, a0, a1, 0) # a0 <- arrayObj + index*width - bgeu a1, a3, common_errArrayIndex # index >= length, bail - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_VREG(a2, rOBJ) # a2 <- vAA - GET_INST_OPCODE(t0) # extract opcode from rINST - GET_OPCODE_TARGET(t0) - sb a2, MIRROR_BYTE_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 - JR(t0) # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aput_char: /* 0x50 */ - - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B(a2, 1, 0) # a2 <- BB - GET_OPA(rOBJ) # rOBJ <- AA - FETCH_B(a3, 1, 1) # a3 <- CC - GET_VREG(a0, a2) # a0 <- vBB (array object) - GET_VREG(a1, a3) # a1 <- vCC (requested index) - # null array object? - beqz a0, common_errNullObject # yes, bail - LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length - EASN(a0, a0, a1, 1) # a0 <- arrayObj + index*width - bgeu a1, a3, common_errArrayIndex # index >= length, bail - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_VREG(a2, rOBJ) # a2 <- vAA - GET_INST_OPCODE(t0) # extract opcode from rINST - GET_OPCODE_TARGET(t0) - sh a2, MIRROR_CHAR_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 - JR(t0) # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aput_short: /* 0x51 */ - - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B(a2, 1, 0) # a2 <- BB - GET_OPA(rOBJ) # rOBJ <- AA - FETCH_B(a3, 1, 1) # a3 <- CC - GET_VREG(a0, a2) # a0 <- vBB (array object) - GET_VREG(a1, a3) # a1 <- vCC (requested index) - # null array object? - beqz a0, common_errNullObject # yes, bail - LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length - EASN(a0, a0, a1, 1) # a0 <- arrayObj + index*width - bgeu a1, a3, common_errArrayIndex # index >= length, bail - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_VREG(a2, rOBJ) # a2 <- vAA - GET_INST_OPCODE(t0) # extract opcode from rINST - GET_OPCODE_TARGET(t0) - sh a2, MIRROR_SHORT_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 - JR(t0) # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iget: /* 0x52 */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_iget_wide: /* 0x53 */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_iget_object: /* 0x54 */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_iget_boolean: /* 0x55 */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_iget_byte: /* 0x56 */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_iget_char: /* 0x57 */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_iget_short: /* 0x58 */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_iput: /* 0x59 */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_iput_wide: /* 0x5a */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_iput_object: /* 0x5b */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_iput_boolean: /* 0x5c */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_iput_byte: /* 0x5d */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_iput_char: /* 0x5e */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_iput_short: /* 0x5f */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_sget: /* 0x60 */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_sget_wide: /* 0x61 */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_sget_object: /* 0x62 */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_sget_boolean: /* 0x63 */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_sget_byte: /* 0x64 */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_sget_char: /* 0x65 */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_sget_short: /* 0x66 */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_sput: /* 0x67 */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_sput_wide: /* 0x68 */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_sput_object: /* 0x69 */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_sput_boolean: /* 0x6a */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_sput_byte: /* 0x6b */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_sput_char: /* 0x6c */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_sput_short: /* 0x6d */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual: /* 0x6e */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtual - EXPORT_PC() - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - JAL(MterpInvokeVirtual) - beqz v0, MterpException - FETCH_ADVANCE_INST(3) - JAL(MterpShouldSwitchInterpreters) - bnez v0, MterpFallback - GET_INST_OPCODE(t0) - GOTO_OPCODE(t0) - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_super: /* 0x6f */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeSuper - EXPORT_PC() - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - JAL(MterpInvokeSuper) - beqz v0, MterpException - FETCH_ADVANCE_INST(3) - JAL(MterpShouldSwitchInterpreters) - bnez v0, MterpFallback - GET_INST_OPCODE(t0) - GOTO_OPCODE(t0) - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_direct: /* 0x70 */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeDirect - EXPORT_PC() - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - JAL(MterpInvokeDirect) - beqz v0, MterpException - FETCH_ADVANCE_INST(3) - JAL(MterpShouldSwitchInterpreters) - bnez v0, MterpFallback - GET_INST_OPCODE(t0) - GOTO_OPCODE(t0) - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_static: /* 0x71 */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeStatic - EXPORT_PC() - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - JAL(MterpInvokeStatic) - beqz v0, MterpException - FETCH_ADVANCE_INST(3) - JAL(MterpShouldSwitchInterpreters) - bnez v0, MterpFallback - GET_INST_OPCODE(t0) - GOTO_OPCODE(t0) - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_interface: /* 0x72 */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeInterface - EXPORT_PC() - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - JAL(MterpInvokeInterface) - beqz v0, MterpException - FETCH_ADVANCE_INST(3) - JAL(MterpShouldSwitchInterpreters) - bnez v0, MterpFallback - GET_INST_OPCODE(t0) - GOTO_OPCODE(t0) - -/* ------------------------------ */ - .balign 128 -.L_op_return_void_no_barrier: /* 0x73 */ - lw ra, THREAD_FLAGS_OFFSET(rSELF) - move a0, rSELF - and ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - beqz ra, 1f - JAL(MterpSuspendCheck) # (self) -1: - move v0, zero - move v1, zero - b MterpReturn - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual_range: /* 0x74 */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtualRange - EXPORT_PC() - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - JAL(MterpInvokeVirtualRange) - beqz v0, MterpException - FETCH_ADVANCE_INST(3) - JAL(MterpShouldSwitchInterpreters) - bnez v0, MterpFallback - GET_INST_OPCODE(t0) - GOTO_OPCODE(t0) - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_super_range: /* 0x75 */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeSuperRange - EXPORT_PC() - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - JAL(MterpInvokeSuperRange) - beqz v0, MterpException - FETCH_ADVANCE_INST(3) - JAL(MterpShouldSwitchInterpreters) - bnez v0, MterpFallback - GET_INST_OPCODE(t0) - GOTO_OPCODE(t0) - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_direct_range: /* 0x76 */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeDirectRange - EXPORT_PC() - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - JAL(MterpInvokeDirectRange) - beqz v0, MterpException - FETCH_ADVANCE_INST(3) - JAL(MterpShouldSwitchInterpreters) - bnez v0, MterpFallback - GET_INST_OPCODE(t0) - GOTO_OPCODE(t0) - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_static_range: /* 0x77 */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeStaticRange - EXPORT_PC() - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - JAL(MterpInvokeStaticRange) - beqz v0, MterpException - FETCH_ADVANCE_INST(3) - JAL(MterpShouldSwitchInterpreters) - bnez v0, MterpFallback - GET_INST_OPCODE(t0) - GOTO_OPCODE(t0) - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_interface_range: /* 0x78 */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeInterfaceRange - EXPORT_PC() - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - JAL(MterpInvokeInterfaceRange) - beqz v0, MterpException - FETCH_ADVANCE_INST(3) - JAL(MterpShouldSwitchInterpreters) - bnez v0, MterpFallback - GET_INST_OPCODE(t0) - GOTO_OPCODE(t0) - -/* ------------------------------ */ - .balign 128 -.L_op_unused_79: /* 0x79 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_7a: /* 0x7a */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_neg_int: /* 0x7b */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result0 = op a0". - * This could be a MIPS instruction or a function call. - * - * for: int-to-byte, int-to-char, int-to-short, - * neg-int, not-int, neg-float - */ - /* unop vA, vB */ - GET_OPB(a3) # a3 <- B - GET_OPA4(t0) # t0 <- A+ - GET_VREG(a0, a3) # a0 <- vB - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - # optional op - negu a0, a0 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t1) # extract opcode from rINST - SET_VREG_GOTO(a0, t0, t1) # vA <- result0 - -/* ------------------------------ */ - .balign 128 -.L_op_not_int: /* 0x7c */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result0 = op a0". - * This could be a MIPS instruction or a function call. - * - * for: int-to-byte, int-to-char, int-to-short, - * neg-int, not-int, neg-float - */ - /* unop vA, vB */ - GET_OPB(a3) # a3 <- B - GET_OPA4(t0) # t0 <- A+ - GET_VREG(a0, a3) # a0 <- vB - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - # optional op - not a0, a0 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t1) # extract opcode from rINST - SET_VREG_GOTO(a0, t0, t1) # vA <- result0 - -/* ------------------------------ */ - .balign 128 -.L_op_neg_long: /* 0x7d */ - /* - * Generic 64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result0/result1 = op a0/a1". - * This could be MIPS instruction or a function call. - * - * For: neg-long, not-long, neg-double, - */ - /* unop vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - EAS2(a3, rFP, a3) # a3 <- &fp[B] - LOAD64(a0, a1, a3) # a0/a1 <- vA - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - negu v0, a0 # optional op - negu v1, a1; sltu a0, zero, v0; subu v1, v1, a0 # a0/a1 <- op, a2-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vA/vA+1 <- a0/a1 - -/* ------------------------------ */ - .balign 128 -.L_op_not_long: /* 0x7e */ - /* - * Generic 64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result0/result1 = op a0/a1". - * This could be MIPS instruction or a function call. - * - * For: neg-long, not-long, neg-double, - */ - /* unop vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - EAS2(a3, rFP, a3) # a3 <- &fp[B] - LOAD64(a0, a1, a3) # a0/a1 <- vA - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - not a0, a0 # optional op - not a1, a1 # a0/a1 <- op, a2-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vA/vA+1 <- a0/a1 - -/* ------------------------------ */ - .balign 128 -.L_op_neg_float: /* 0x7f */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result0 = op a0". - * This could be a MIPS instruction or a function call. - * - * for: int-to-byte, int-to-char, int-to-short, - * neg-int, not-int, neg-float - */ - /* unop vA, vB */ - GET_OPB(a3) # a3 <- B - GET_OPA4(t0) # t0 <- A+ - GET_VREG(a0, a3) # a0 <- vB - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - # optional op - addu a0, a0, 0x80000000 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t1) # extract opcode from rINST - SET_VREG_GOTO(a0, t0, t1) # vA <- result0 - -/* ------------------------------ */ - .balign 128 -.L_op_neg_double: /* 0x80 */ - /* - * Generic 64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result0/result1 = op a0/a1". - * This could be MIPS instruction or a function call. - * - * For: neg-long, not-long, neg-double, - */ - /* unop vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - EAS2(a3, rFP, a3) # a3 <- &fp[B] - LOAD64(a0, a1, a3) # a0/a1 <- vA - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - # optional op - addu a1, a1, 0x80000000 # a0/a1 <- op, a2-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vA/vA+1 <- a0/a1 - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_long: /* 0x81 */ - /* - * Generic 32bit-to-64bit unary operation. Provide an "instr" line - * that specifies an instruction that performs "result0/result1 = op a0". - * - * For: int-to-long - */ - /* unop vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a0, a3) # a0 <- vB - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - # optional op - sra a1, a0, 31 # result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vA/vA+1 <- a0/a1 - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_float: /* 0x82 */ - /* - * Generic 32-bit floating-point unary operation. Provide an "instr" - * line that specifies an instruction that performs "fv0 = op fa0". - * This could be a MIPS instruction or a function call. - * - * for: int-to-float - */ - /* unop vA, vB */ - GET_OPB(a3) # a3 <- B - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_VREG_F(fa0, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - cvt.s.w fv0, fa0 - GET_INST_OPCODE(t1) # extract opcode from rINST - SET_VREG_F_GOTO(fv0, rOBJ, t1) # vA <- fv0 - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_double: /* 0x83 */ - /* - * Generic 32bit-to-64bit floating-point unary operation. Provide an "instr" - * line that specifies an instruction that performs "fv0 = op fa0". - * - * For: int-to-double, float-to-double - */ - /* unop vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG_F(fa0, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - cvt.d.w fv0, fa0 - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vA/vA+1 <- fv0 - -/* ------------------------------ */ - .balign 128 -.L_op_long_to_int: /* 0x84 */ -/* we ignore the high word, making this equivalent to a 32-bit reg move */ - /* for move, move-object, long-to-int */ - /* op vA, vB */ - GET_OPB(a1) # a1 <- B from 15:12 - GET_OPA4(a0) # a0 <- A from 11:8 - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - GET_VREG(a2, a1) # a2 <- fp[B] - GET_INST_OPCODE(t0) # t0 <- opcode from rINST - .if 0 - SET_VREG_OBJECT_GOTO(a2, a0, t0) # fp[A] <- a2 - .else - SET_VREG_GOTO(a2, a0, t0) # fp[A] <- a2 - .endif - -/* ------------------------------ */ - .balign 128 -.L_op_long_to_float: /* 0x85 */ - /* - * long-to-float - */ - /* unop vA, vB */ - GET_OPB(a3) # a3 <- B - GET_OPA4(rOBJ) # rOBJ <- A+ - EAS2(a3, rFP, a3) # a3 <- &fp[B] - -#ifdef MIPS32REVGE6 - LOAD64_F(fv0, fv0f, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - cvt.s.l fv0, fv0 -#else - LOAD64(rARG0, rARG1, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - JAL(__floatdisf) -#endif - - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_F_GOTO(fv0, rOBJ, t0) # vA <- fv0 - -/* ------------------------------ */ - .balign 128 -.L_op_long_to_double: /* 0x86 */ - /* - * long-to-double - */ - /* unop vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - EAS2(a3, rFP, a3) # a3 <- &fp[B] - -#ifdef MIPS32REVGE6 - LOAD64_F(fv0, fv0f, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - cvt.d.l fv0, fv0 -#else - LOAD64(rARG0, rARG1, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - JAL(__floatdidf) # a0/a1 <- op, a2-a3 changed -#endif - - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vA/vA+1 <- result - -/* ------------------------------ */ - .balign 128 -.L_op_float_to_int: /* 0x87 */ - /* - * float-to-int - * - * We have to clip values to int min/max per the specification. The - * expected common case is a "reasonable" value that converts directly - * to modest integer. The EABI convert function isn't doing this for us - * for pre-R6. - */ - /* unop vA, vB */ - GET_OPB(a3) # a3 <- B - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_VREG_F(fa0, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - -#ifndef MIPS32REVGE6 - li t0, INT_MIN_AS_FLOAT - mtc1 t0, fa1 - c.ole.s fcc0, fa1, fa0 -#endif - GET_INST_OPCODE(t1) # extract opcode from rINST -#ifndef MIPS32REVGE6 - bc1t fcc0, 1f # if INT_MIN <= vB, proceed to truncation - c.eq.s fcc0, fa0, fa0 - mtc1 zero, fa0 - movt.s fa0, fa1, fcc0 # fa0 = ordered(vB) ? INT_MIN_AS_FLOAT : 0 -1: -#endif - trunc.w.s fa0, fa0 - SET_VREG_F_GOTO(fa0, rOBJ, t1) # vA <- result - -/* ------------------------------ */ - .balign 128 -.L_op_float_to_long: /* 0x88 */ - /* - * float-to-long - * - * We have to clip values to long min/max per the specification. The - * expected common case is a "reasonable" value that converts directly - * to modest integer. The EABI convert function isn't doing this for us - * for pre-R6. - */ - /* unop vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG_F(fa0, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - -#ifdef MIPS32REVGE6 - GET_INST_OPCODE(t1) # extract opcode from rINST - trunc.l.s fa0, fa0 - SET_VREG64_F_GOTO(fa0, fa0f, rOBJ, t1) # vA <- result -#else - c.eq.s fcc0, fa0, fa0 - li rRESULT0, 0 - li rRESULT1, 0 - bc1f fcc0, .Lop_float_to_long_get_opcode - - li t0, LONG_MIN_AS_FLOAT - mtc1 t0, fa1 - c.ole.s fcc0, fa0, fa1 - li rRESULT1, LONG_MIN_HIGH - bc1t fcc0, .Lop_float_to_long_get_opcode - - neg.s fa1, fa1 - c.ole.s fcc0, fa1, fa0 - nor rRESULT0, rRESULT0, zero - nor rRESULT1, rRESULT1, zero - bc1t fcc0, .Lop_float_to_long_get_opcode - - JAL(__fixsfdi) - GET_INST_OPCODE(t1) # extract opcode from rINST - b .Lop_float_to_long_set_vreg -#endif - -/* ------------------------------ */ - .balign 128 -.L_op_float_to_double: /* 0x89 */ - /* - * Generic 32bit-to-64bit floating-point unary operation. Provide an "instr" - * line that specifies an instruction that performs "fv0 = op fa0". - * - * For: int-to-double, float-to-double - */ - /* unop vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG_F(fa0, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - cvt.d.s fv0, fa0 - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vA/vA+1 <- fv0 - -/* ------------------------------ */ - .balign 128 -.L_op_double_to_int: /* 0x8a */ - /* - * double-to-int - * - * We have to clip values to int min/max per the specification. The - * expected common case is a "reasonable" value that converts directly - * to modest integer. The EABI convert function isn't doing this for us - * for pre-R6. - */ - /* unop vA, vB */ - GET_OPB(a3) # a3 <- B - GET_OPA4(rOBJ) # rOBJ <- A+ - EAS2(a3, rFP, a3) # a3 <- &fp[B] - LOAD64_F(fa0, fa0f, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST -#ifndef MIPS32REVGE6 - li t0, INT_MIN_AS_DOUBLE_HIGH - mtc1 zero, fa1 - MOVE_TO_FPU_HIGH(t0, fa1, fa1f) - c.ole.d fcc0, fa1, fa0 -#endif - GET_INST_OPCODE(t1) # extract opcode from rINST -#ifndef MIPS32REVGE6 - bc1t fcc0, 1f # if INT_MIN <= vB, proceed to truncation - c.eq.d fcc0, fa0, fa0 - mtc1 zero, fa0 - MOVE_TO_FPU_HIGH(zero, fa0, fa0f) - movt.d fa0, fa1, fcc0 # fa0 = ordered(vB) ? INT_MIN_AS_DOUBLE : 0 -1: -#endif - trunc.w.d fa0, fa0 - SET_VREG_F_GOTO(fa0, rOBJ, t1) # vA <- result - -/* ------------------------------ */ - .balign 128 -.L_op_double_to_long: /* 0x8b */ - /* - * double-to-long - * - * We have to clip values to long min/max per the specification. The - * expected common case is a "reasonable" value that converts directly - * to modest integer. The EABI convert function isn't doing this for us - * for pre-R6. - */ - /* unop vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - EAS2(a3, rFP, a3) # a3 <- &fp[B] - LOAD64_F(fa0, fa0f, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - -#ifdef MIPS32REVGE6 - GET_INST_OPCODE(t1) # extract opcode from rINST - trunc.l.d fa0, fa0 - SET_VREG64_F_GOTO(fa0, fa0f, rOBJ, t1) # vA <- result -#else - c.eq.d fcc0, fa0, fa0 - li rRESULT0, 0 - li rRESULT1, 0 - bc1f fcc0, .Lop_double_to_long_get_opcode - - li t0, LONG_MIN_AS_DOUBLE_HIGH - mtc1 zero, fa1 - MOVE_TO_FPU_HIGH(t0, fa1, fa1f) - c.ole.d fcc0, fa0, fa1 - li rRESULT1, LONG_MIN_HIGH - bc1t fcc0, .Lop_double_to_long_get_opcode - - neg.d fa1, fa1 - c.ole.d fcc0, fa1, fa0 - nor rRESULT0, rRESULT0, zero - nor rRESULT1, rRESULT1, zero - bc1t fcc0, .Lop_double_to_long_get_opcode - - JAL(__fixdfdi) - GET_INST_OPCODE(t1) # extract opcode from rINST - b .Lop_double_to_long_set_vreg -#endif - -/* ------------------------------ */ - .balign 128 -.L_op_double_to_float: /* 0x8c */ - /* - * Generic 64bit-to-32bit floating-point unary operation. Provide an "instr" - * line that specifies an instruction that performs "fv0 = op fa0". - * - * For: double-to-float - */ - /* unop vA, vB */ - GET_OPB(a3) # a3 <- B - GET_OPA4(rOBJ) # rOBJ <- A+ - EAS2(a3, rFP, a3) # a3 <- &fp[B] - LOAD64_F(fa0, fa0f, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - cvt.s.d fv0, fa0 - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_F_GOTO(fv0, rOBJ, t0) # vA <- fv0 - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_byte: /* 0x8d */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result0 = op a0". - * This could be a MIPS instruction or a function call. - * - * for: int-to-byte, int-to-char, int-to-short, - * neg-int, not-int, neg-float - */ - /* unop vA, vB */ - GET_OPB(a3) # a3 <- B - GET_OPA4(t0) # t0 <- A+ - GET_VREG(a0, a3) # a0 <- vB - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - # optional op - SEB(a0, a0) # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t1) # extract opcode from rINST - SET_VREG_GOTO(a0, t0, t1) # vA <- result0 - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_char: /* 0x8e */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result0 = op a0". - * This could be a MIPS instruction or a function call. - * - * for: int-to-byte, int-to-char, int-to-short, - * neg-int, not-int, neg-float - */ - /* unop vA, vB */ - GET_OPB(a3) # a3 <- B - GET_OPA4(t0) # t0 <- A+ - GET_VREG(a0, a3) # a0 <- vB - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - # optional op - and a0, 0xffff # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t1) # extract opcode from rINST - SET_VREG_GOTO(a0, t0, t1) # vA <- result0 - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_short: /* 0x8f */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result0 = op a0". - * This could be a MIPS instruction or a function call. - * - * for: int-to-byte, int-to-char, int-to-short, - * neg-int, not-int, neg-float - */ - /* unop vA, vB */ - GET_OPB(a3) # a3 <- B - GET_OPA4(t0) # t0 <- A+ - GET_VREG(a0, a3) # a0 <- vB - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - # optional op - SEH(a0, a0) # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t1) # extract opcode from rINST - SET_VREG_GOTO(a0, t0, t1) # vA <- result0 - -/* ------------------------------ */ - .balign 128 -.L_op_add_int: /* 0x90 */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - srl a3, a0, 8 # a3 <- CC - and a2, a0, 255 # a2 <- BB - GET_VREG(a1, a3) # a1 <- vCC - GET_VREG(a0, a2) # a0 <- vBB - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - # optional op - addu a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - -/* ------------------------------ */ - .balign 128 -.L_op_sub_int: /* 0x91 */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - srl a3, a0, 8 # a3 <- CC - and a2, a0, 255 # a2 <- BB - GET_VREG(a1, a3) # a1 <- vCC - GET_VREG(a0, a2) # a0 <- vBB - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - # optional op - subu a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int: /* 0x92 */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - srl a3, a0, 8 # a3 <- CC - and a2, a0, 255 # a2 <- BB - GET_VREG(a1, a3) # a1 <- vCC - GET_VREG(a0, a2) # a0 <- vBB - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - # optional op - mul a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - -/* ------------------------------ */ - .balign 128 -.L_op_div_int: /* 0x93 */ -#ifdef MIPS32REVGE6 - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - srl a3, a0, 8 # a3 <- CC - and a2, a0, 255 # a2 <- BB - GET_VREG(a1, a3) # a1 <- vCC - GET_VREG(a0, a2) # a0 <- vBB - .if 1 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - # optional op - div a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - -#else - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - srl a3, a0, 8 # a3 <- CC - and a2, a0, 255 # a2 <- BB - GET_VREG(a1, a3) # a1 <- vCC - GET_VREG(a0, a2) # a0 <- vBB - .if 1 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - div zero, a0, a1 # optional op - mflo a0 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - -#endif - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int: /* 0x94 */ -#ifdef MIPS32REVGE6 - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - srl a3, a0, 8 # a3 <- CC - and a2, a0, 255 # a2 <- BB - GET_VREG(a1, a3) # a1 <- vCC - GET_VREG(a0, a2) # a0 <- vBB - .if 1 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - # optional op - mod a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - -#else - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - srl a3, a0, 8 # a3 <- CC - and a2, a0, 255 # a2 <- BB - GET_VREG(a1, a3) # a1 <- vCC - GET_VREG(a0, a2) # a0 <- vBB - .if 1 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - div zero, a0, a1 # optional op - mfhi a0 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - -#endif - -/* ------------------------------ */ - .balign 128 -.L_op_and_int: /* 0x95 */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - srl a3, a0, 8 # a3 <- CC - and a2, a0, 255 # a2 <- BB - GET_VREG(a1, a3) # a1 <- vCC - GET_VREG(a0, a2) # a0 <- vBB - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - # optional op - and a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - -/* ------------------------------ */ - .balign 128 -.L_op_or_int: /* 0x96 */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - srl a3, a0, 8 # a3 <- CC - and a2, a0, 255 # a2 <- BB - GET_VREG(a1, a3) # a1 <- vCC - GET_VREG(a0, a2) # a0 <- vBB - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - # optional op - or a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int: /* 0x97 */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - srl a3, a0, 8 # a3 <- CC - and a2, a0, 255 # a2 <- BB - GET_VREG(a1, a3) # a1 <- vCC - GET_VREG(a0, a2) # a0 <- vBB - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - # optional op - xor a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - -/* ------------------------------ */ - .balign 128 -.L_op_shl_int: /* 0x98 */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - srl a3, a0, 8 # a3 <- CC - and a2, a0, 255 # a2 <- BB - GET_VREG(a1, a3) # a1 <- vCC - GET_VREG(a0, a2) # a0 <- vBB - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - # optional op - sll a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - -/* ------------------------------ */ - .balign 128 -.L_op_shr_int: /* 0x99 */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - srl a3, a0, 8 # a3 <- CC - and a2, a0, 255 # a2 <- BB - GET_VREG(a1, a3) # a1 <- vCC - GET_VREG(a0, a2) # a0 <- vBB - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - # optional op - sra a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_int: /* 0x9a */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - srl a3, a0, 8 # a3 <- CC - and a2, a0, 255 # a2 <- BB - GET_VREG(a1, a3) # a1 <- vCC - GET_VREG(a0, a2) # a0 <- vBB - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - # optional op - srl a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - -/* ------------------------------ */ - .balign 128 -.L_op_add_long: /* 0x9b */ -/* - * The compiler generates the following sequence for - * [v1 v0] = [a1 a0] + [a3 a2]; - * addu v0,a2,a0 - * addu a1,a3,a1 - * sltu v1,v0,a2 - * addu v1,v1,a1 - */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0-a1 op a2-a3". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register pair other than a0-a1, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a2-a3). Useful for integer division and modulus. - * - * for: add-long, sub-long, div-long, rem-long, and-long, or-long, - * xor-long - * - * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 # a3 <- CC - EAS2(a2, rFP, a2) # a2 <- &fp[BB] - EAS2(t1, rFP, a3) # a3 <- &fp[CC] - LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 - LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 - .if 0 - or t0, a2, a3 # second arg (a2-a3) is zero? - beqz t0, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - addu v0, a2, a0 # optional op - addu a1, a3, a1; sltu v1, v0, a2; addu v1, v1, a1 # result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vAA/vAA+1 <- v0/v1 - -/* ------------------------------ */ - .balign 128 -.L_op_sub_long: /* 0x9c */ -/* - * For little endian the code sequence looks as follows: - * subu v0,a0,a2 - * subu v1,a1,a3 - * sltu a0,a0,v0 - * subu v1,v1,a0 - */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0-a1 op a2-a3". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register pair other than a0-a1, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a2-a3). Useful for integer division and modulus. - * - * for: add-long, sub-long, div-long, rem-long, and-long, or-long, - * xor-long - * - * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 # a3 <- CC - EAS2(a2, rFP, a2) # a2 <- &fp[BB] - EAS2(t1, rFP, a3) # a3 <- &fp[CC] - LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 - LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 - .if 0 - or t0, a2, a3 # second arg (a2-a3) is zero? - beqz t0, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - subu v0, a0, a2 # optional op - subu v1, a1, a3; sltu a0, a0, v0; subu v1, v1, a0 # result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vAA/vAA+1 <- v0/v1 - -/* ------------------------------ */ - .balign 128 -.L_op_mul_long: /* 0x9d */ - /* - * Signed 64-bit integer multiply. - * a1 a0 - * x a3 a2 - * ------------- - * a2a1 a2a0 - * a3a0 - * a3a1 (<= unused) - * --------------- - * v1 v0 - */ - /* mul-long vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - and t0, a0, 255 # a2 <- BB - srl t1, a0, 8 # a3 <- CC - EAS2(t0, rFP, t0) # t0 <- &fp[BB] - LOAD64(a0, a1, t0) # a0/a1 <- vBB/vBB+1 - - EAS2(t1, rFP, t1) # t0 <- &fp[CC] - LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 - - mul v1, a3, a0 # v1= a3a0 -#ifdef MIPS32REVGE6 - mulu v0, a2, a0 # v0= a2a0 - muhu t1, a2, a0 -#else - multu a2, a0 - mfhi t1 - mflo v0 # v0= a2a0 -#endif - mul t0, a2, a1 # t0= a2a1 - addu v1, v1, t1 # v1+= hi(a2a0) - addu v1, v1, t0 # v1= a3a0 + a2a1; - - GET_OPA(a0) # a0 <- AA - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - b .Lop_mul_long_finish - -/* ------------------------------ */ - .balign 128 -.L_op_div_long: /* 0x9e */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0-a1 op a2-a3". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register pair other than a0-a1, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a2-a3). Useful for integer division and modulus. - * - * for: add-long, sub-long, div-long, rem-long, and-long, or-long, - * xor-long - * - * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 # a3 <- CC - EAS2(a2, rFP, a2) # a2 <- &fp[BB] - EAS2(t1, rFP, a3) # a3 <- &fp[CC] - LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 - LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 - .if 1 - or t0, a2, a3 # second arg (a2-a3) is zero? - beqz t0, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - # optional op - JAL(__divdi3) # result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vAA/vAA+1 <- v0/v1 - -/* ------------------------------ */ - .balign 128 -.L_op_rem_long: /* 0x9f */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0-a1 op a2-a3". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register pair other than a0-a1, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a2-a3). Useful for integer division and modulus. - * - * for: add-long, sub-long, div-long, rem-long, and-long, or-long, - * xor-long - * - * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 # a3 <- CC - EAS2(a2, rFP, a2) # a2 <- &fp[BB] - EAS2(t1, rFP, a3) # a3 <- &fp[CC] - LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 - LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 - .if 1 - or t0, a2, a3 # second arg (a2-a3) is zero? - beqz t0, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - # optional op - JAL(__moddi3) # result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vAA/vAA+1 <- v0/v1 - -/* ------------------------------ */ - .balign 128 -.L_op_and_long: /* 0xa0 */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0-a1 op a2-a3". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register pair other than a0-a1, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a2-a3). Useful for integer division and modulus. - * - * for: add-long, sub-long, div-long, rem-long, and-long, or-long, - * xor-long - * - * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 # a3 <- CC - EAS2(a2, rFP, a2) # a2 <- &fp[BB] - EAS2(t1, rFP, a3) # a3 <- &fp[CC] - LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 - LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 - .if 0 - or t0, a2, a3 # second arg (a2-a3) is zero? - beqz t0, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - and a0, a0, a2 # optional op - and a1, a1, a3 # result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vAA/vAA+1 <- a0/a1 - -/* ------------------------------ */ - .balign 128 -.L_op_or_long: /* 0xa1 */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0-a1 op a2-a3". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register pair other than a0-a1, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a2-a3). Useful for integer division and modulus. - * - * for: add-long, sub-long, div-long, rem-long, and-long, or-long, - * xor-long - * - * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 # a3 <- CC - EAS2(a2, rFP, a2) # a2 <- &fp[BB] - EAS2(t1, rFP, a3) # a3 <- &fp[CC] - LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 - LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 - .if 0 - or t0, a2, a3 # second arg (a2-a3) is zero? - beqz t0, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - or a0, a0, a2 # optional op - or a1, a1, a3 # result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vAA/vAA+1 <- a0/a1 - -/* ------------------------------ */ - .balign 128 -.L_op_xor_long: /* 0xa2 */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0-a1 op a2-a3". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register pair other than a0-a1, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a2-a3). Useful for integer division and modulus. - * - * for: add-long, sub-long, div-long, rem-long, and-long, or-long, - * xor-long - * - * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 # a3 <- CC - EAS2(a2, rFP, a2) # a2 <- &fp[BB] - EAS2(t1, rFP, a3) # a3 <- &fp[CC] - LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 - LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 - .if 0 - or t0, a2, a3 # second arg (a2-a3) is zero? - beqz t0, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - xor a0, a0, a2 # optional op - xor a1, a1, a3 # result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vAA/vAA+1 <- a0/a1 - -/* ------------------------------ */ - .balign 128 -.L_op_shl_long: /* 0xa3 */ - /* - * Long integer shift. This is different from the generic 32/64-bit - * binary operations because vAA/vBB are 64-bit but vCC (the shift - * distance) is 32-bit. Also, Dalvik requires us to mask off the low - * 6 bits of the shift distance. - */ - /* shl-long vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(t2) # t2 <- AA - and a3, a0, 255 # a3 <- BB - srl a0, a0, 8 # a0 <- CC - EAS2(a3, rFP, a3) # a3 <- &fp[BB] - GET_VREG(a2, a0) # a2 <- vCC - LOAD64(a0, a1, a3) # a0/a1 <- vBB/vBB+1 - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - - andi v1, a2, 0x20 # shift< shift & 0x20 - sll v0, a0, a2 # rlo<- alo << (shift&31) - bnez v1, .Lop_shl_long_finish - not v1, a2 # rhi<- 31-shift (shift is 5b) - srl a0, 1 - srl a0, v1 # alo<- alo >> (32-(shift&31)) - sll v1, a1, a2 # rhi<- ahi << (shift&31) - or v1, a0 # rhi<- rhi | alo - SET_VREG64_GOTO(v0, v1, t2, t0) # vAA/vAA+1 <- v0/v1 - -/* ------------------------------ */ - .balign 128 -.L_op_shr_long: /* 0xa4 */ - /* - * Long integer shift. This is different from the generic 32/64-bit - * binary operations because vAA/vBB are 64-bit but vCC (the shift - * distance) is 32-bit. Also, Dalvik requires us to mask off the low - * 6 bits of the shift distance. - */ - /* shr-long vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(t3) # t3 <- AA - and a3, a0, 255 # a3 <- BB - srl a0, a0, 8 # a0 <- CC - EAS2(a3, rFP, a3) # a3 <- &fp[BB] - GET_VREG(a2, a0) # a2 <- vCC - LOAD64(a0, a1, a3) # a0/a1 <- vBB/vBB+1 - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - - andi v0, a2, 0x20 # shift & 0x20 - sra v1, a1, a2 # rhi<- ahi >> (shift&31) - bnez v0, .Lop_shr_long_finish - srl v0, a0, a2 # rlo<- alo >> (shift&31) - not a0, a2 # alo<- 31-shift (shift is 5b) - sll a1, 1 - sll a1, a0 # ahi<- ahi << (32-(shift&31)) - or v0, a1 # rlo<- rlo | ahi - SET_VREG64_GOTO(v0, v1, t3, t0) # vAA/VAA+1 <- v0/v1 - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_long: /* 0xa5 */ - /* - * Long integer shift. This is different from the generic 32/64-bit - * binary operations because vAA/vBB are 64-bit but vCC (the shift - * distance) is 32-bit. Also, Dalvik requires us to mask off the low - * 6 bits of the shift distance. - */ - /* ushr-long vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - and a3, a0, 255 # a3 <- BB - srl a0, a0, 8 # a0 <- CC - EAS2(a3, rFP, a3) # a3 <- &fp[BB] - GET_VREG(a2, a0) # a2 <- vCC - LOAD64(a0, a1, a3) # a0/a1 <- vBB/vBB+1 - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - - andi v0, a2, 0x20 # shift & 0x20 - srl v1, a1, a2 # rhi<- ahi >> (shift&31) - bnez v0, .Lop_ushr_long_finish - srl v0, a0, a2 # rlo<- alo >> (shift&31) - not a0, a2 # alo<- 31-n (shift is 5b) - sll a1, 1 - sll a1, a0 # ahi<- ahi << (32-(shift&31)) - or v0, a1 # rlo<- rlo | ahi - SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vAA/vAA+1 <- v0/v1 - -/* ------------------------------ */ - .balign 128 -.L_op_add_float: /* 0xa6 */ - /* - * Generic 32-bit binary float operation. - * - * For: add-fp, sub-fp, mul-fp, div-fp, rem-fp - */ - - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - srl a3, a0, 8 # a3 <- CC - and a2, a0, 255 # a2 <- BB - GET_VREG_F(fa1, a3) # a1 <- vCC - GET_VREG_F(fa0, a2) # a0 <- vBB - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - add.s fv0, fa0, fa1 # f0 = result - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_F_GOTO(fv0, rOBJ, t0) # vAA <- fv0 - -/* ------------------------------ */ - .balign 128 -.L_op_sub_float: /* 0xa7 */ - /* - * Generic 32-bit binary float operation. - * - * For: add-fp, sub-fp, mul-fp, div-fp, rem-fp - */ - - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - srl a3, a0, 8 # a3 <- CC - and a2, a0, 255 # a2 <- BB - GET_VREG_F(fa1, a3) # a1 <- vCC - GET_VREG_F(fa0, a2) # a0 <- vBB - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - sub.s fv0, fa0, fa1 # f0 = result - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_F_GOTO(fv0, rOBJ, t0) # vAA <- fv0 - -/* ------------------------------ */ - .balign 128 -.L_op_mul_float: /* 0xa8 */ - /* - * Generic 32-bit binary float operation. - * - * For: add-fp, sub-fp, mul-fp, div-fp, rem-fp - */ - - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - srl a3, a0, 8 # a3 <- CC - and a2, a0, 255 # a2 <- BB - GET_VREG_F(fa1, a3) # a1 <- vCC - GET_VREG_F(fa0, a2) # a0 <- vBB - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - mul.s fv0, fa0, fa1 # f0 = result - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_F_GOTO(fv0, rOBJ, t0) # vAA <- fv0 - -/* ------------------------------ */ - .balign 128 -.L_op_div_float: /* 0xa9 */ - /* - * Generic 32-bit binary float operation. - * - * For: add-fp, sub-fp, mul-fp, div-fp, rem-fp - */ - - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - srl a3, a0, 8 # a3 <- CC - and a2, a0, 255 # a2 <- BB - GET_VREG_F(fa1, a3) # a1 <- vCC - GET_VREG_F(fa0, a2) # a0 <- vBB - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - div.s fv0, fa0, fa1 # f0 = result - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_F_GOTO(fv0, rOBJ, t0) # vAA <- fv0 - -/* ------------------------------ */ - .balign 128 -.L_op_rem_float: /* 0xaa */ - /* - * Generic 32-bit binary float operation. - * - * For: add-fp, sub-fp, mul-fp, div-fp, rem-fp - */ - - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - srl a3, a0, 8 # a3 <- CC - and a2, a0, 255 # a2 <- BB - GET_VREG_F(fa1, a3) # a1 <- vCC - GET_VREG_F(fa0, a2) # a0 <- vBB - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - JAL(fmodf) # f0 = result - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_F_GOTO(fv0, rOBJ, t0) # vAA <- fv0 - -/* ------------------------------ */ - .balign 128 -.L_op_add_double: /* 0xab */ - /* - * Generic 64-bit floating-point binary operation. Provide an "instr" - * line that specifies an instruction that performs "fv0 = fa0 op fa1". - * This could be an MIPS instruction or a function call. - * - * for: add-double, sub-double, mul-double, div-double, - * rem-double - * - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 # a3 <- CC - EAS2(a2, rFP, a2) # a2 <- &fp[BB] - EAS2(t1, rFP, a3) # a3 <- &fp[CC] - LOAD64_F(fa0, fa0f, a2) - LOAD64_F(fa1, fa1f, t1) - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - add.d fv0, fa0, fa1 - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vAA/vAA+1 <- fv0 - -/* ------------------------------ */ - .balign 128 -.L_op_sub_double: /* 0xac */ - /* - * Generic 64-bit floating-point binary operation. Provide an "instr" - * line that specifies an instruction that performs "fv0 = fa0 op fa1". - * This could be an MIPS instruction or a function call. - * - * for: add-double, sub-double, mul-double, div-double, - * rem-double - * - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 # a3 <- CC - EAS2(a2, rFP, a2) # a2 <- &fp[BB] - EAS2(t1, rFP, a3) # a3 <- &fp[CC] - LOAD64_F(fa0, fa0f, a2) - LOAD64_F(fa1, fa1f, t1) - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - sub.d fv0, fa0, fa1 - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vAA/vAA+1 <- fv0 - -/* ------------------------------ */ - .balign 128 -.L_op_mul_double: /* 0xad */ - /* - * Generic 64-bit floating-point binary operation. Provide an "instr" - * line that specifies an instruction that performs "fv0 = fa0 op fa1". - * This could be an MIPS instruction or a function call. - * - * for: add-double, sub-double, mul-double, div-double, - * rem-double - * - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 # a3 <- CC - EAS2(a2, rFP, a2) # a2 <- &fp[BB] - EAS2(t1, rFP, a3) # a3 <- &fp[CC] - LOAD64_F(fa0, fa0f, a2) - LOAD64_F(fa1, fa1f, t1) - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - mul.d fv0, fa0, fa1 - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vAA/vAA+1 <- fv0 - -/* ------------------------------ */ - .balign 128 -.L_op_div_double: /* 0xae */ - /* - * Generic 64-bit floating-point binary operation. Provide an "instr" - * line that specifies an instruction that performs "fv0 = fa0 op fa1". - * This could be an MIPS instruction or a function call. - * - * for: add-double, sub-double, mul-double, div-double, - * rem-double - * - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 # a3 <- CC - EAS2(a2, rFP, a2) # a2 <- &fp[BB] - EAS2(t1, rFP, a3) # a3 <- &fp[CC] - LOAD64_F(fa0, fa0f, a2) - LOAD64_F(fa1, fa1f, t1) - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - div.d fv0, fa0, fa1 - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vAA/vAA+1 <- fv0 - -/* ------------------------------ */ - .balign 128 -.L_op_rem_double: /* 0xaf */ - /* - * Generic 64-bit floating-point binary operation. Provide an "instr" - * line that specifies an instruction that performs "fv0 = fa0 op fa1". - * This could be an MIPS instruction or a function call. - * - * for: add-double, sub-double, mul-double, div-double, - * rem-double - * - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 # a3 <- CC - EAS2(a2, rFP, a2) # a2 <- &fp[BB] - EAS2(t1, rFP, a3) # a3 <- &fp[CC] - LOAD64_F(fa0, fa0f, a2) - LOAD64_F(fa1, fa1f, t1) - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - JAL(fmod) - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vAA/vAA+1 <- fv0 - -/* ------------------------------ */ - .balign 128 -.L_op_add_int_2addr: /* 0xb0 */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a0, rOBJ) # a0 <- vA - GET_VREG(a1, a3) # a1 <- vB - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - # optional op - addu a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - -/* ------------------------------ */ - .balign 128 -.L_op_sub_int_2addr: /* 0xb1 */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a0, rOBJ) # a0 <- vA - GET_VREG(a1, a3) # a1 <- vB - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - # optional op - subu a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int_2addr: /* 0xb2 */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a0, rOBJ) # a0 <- vA - GET_VREG(a1, a3) # a1 <- vB - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - # optional op - mul a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - -/* ------------------------------ */ - .balign 128 -.L_op_div_int_2addr: /* 0xb3 */ -#ifdef MIPS32REVGE6 - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a0, rOBJ) # a0 <- vA - GET_VREG(a1, a3) # a1 <- vB - .if 1 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - # optional op - div a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - -#else - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a0, rOBJ) # a0 <- vA - GET_VREG(a1, a3) # a1 <- vB - .if 1 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - div zero, a0, a1 # optional op - mflo a0 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - -#endif - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int_2addr: /* 0xb4 */ -#ifdef MIPS32REVGE6 - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a0, rOBJ) # a0 <- vA - GET_VREG(a1, a3) # a1 <- vB - .if 1 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - # optional op - mod a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - -#else - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a0, rOBJ) # a0 <- vA - GET_VREG(a1, a3) # a1 <- vB - .if 1 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - div zero, a0, a1 # optional op - mfhi a0 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - -#endif - -/* ------------------------------ */ - .balign 128 -.L_op_and_int_2addr: /* 0xb5 */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a0, rOBJ) # a0 <- vA - GET_VREG(a1, a3) # a1 <- vB - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - # optional op - and a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - -/* ------------------------------ */ - .balign 128 -.L_op_or_int_2addr: /* 0xb6 */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a0, rOBJ) # a0 <- vA - GET_VREG(a1, a3) # a1 <- vB - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - # optional op - or a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int_2addr: /* 0xb7 */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a0, rOBJ) # a0 <- vA - GET_VREG(a1, a3) # a1 <- vB - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - # optional op - xor a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - -/* ------------------------------ */ - .balign 128 -.L_op_shl_int_2addr: /* 0xb8 */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a0, rOBJ) # a0 <- vA - GET_VREG(a1, a3) # a1 <- vB - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - # optional op - sll a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - -/* ------------------------------ */ - .balign 128 -.L_op_shr_int_2addr: /* 0xb9 */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a0, rOBJ) # a0 <- vA - GET_VREG(a1, a3) # a1 <- vB - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - # optional op - sra a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_int_2addr: /* 0xba */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a0, rOBJ) # a0 <- vA - GET_VREG(a1, a3) # a1 <- vB - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - # optional op - srl a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - -/* ------------------------------ */ - .balign 128 -.L_op_add_long_2addr: /* 0xbb */ -/* - * See op_add_long.S for details - */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0-a1 op a2-a3". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register pair other than a0-a1, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a2-a3). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a1) # a1 <- B - EAS2(a1, rFP, a1) # a1 <- &fp[B] - EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] - LOAD64(a2, a3, a1) # a2/a3 <- vB/vB+1 - LOAD64(a0, a1, t0) # a0/a1 <- vA/vA+1 - .if 0 - or t0, a2, a3 # second arg (a2-a3) is zero? - beqz t0, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - addu v0, a2, a0 # optional op - addu a1, a3, a1; sltu v1, v0, a2; addu v1, v1, a1 # result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vA/vA+1 <- v0/v1 - -/* ------------------------------ */ - .balign 128 -.L_op_sub_long_2addr: /* 0xbc */ -/* - * See op_sub_long.S for more details - */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0-a1 op a2-a3". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register pair other than a0-a1, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a2-a3). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a1) # a1 <- B - EAS2(a1, rFP, a1) # a1 <- &fp[B] - EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] - LOAD64(a2, a3, a1) # a2/a3 <- vB/vB+1 - LOAD64(a0, a1, t0) # a0/a1 <- vA/vA+1 - .if 0 - or t0, a2, a3 # second arg (a2-a3) is zero? - beqz t0, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - subu v0, a0, a2 # optional op - subu v1, a1, a3; sltu a0, a0, v0; subu v1, v1, a0 # result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vA/vA+1 <- v0/v1 - -/* ------------------------------ */ - .balign 128 -.L_op_mul_long_2addr: /* 0xbd */ - /* - * See op_mul_long.S for more details - */ - /* mul-long/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - - EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] - LOAD64(a0, a1, t0) # vAA.low / high - - GET_OPB(t1) # t1 <- B - EAS2(t1, rFP, t1) # t1 <- &fp[B] - LOAD64(a2, a3, t1) # vBB.low / high - - mul v1, a3, a0 # v1= a3a0 -#ifdef MIPS32REVGE6 - mulu v0, a2, a0 # v0= a2a0 - muhu t1, a2, a0 -#else - multu a2, a0 - mfhi t1 - mflo v0 # v0= a2a0 - #endif - mul t2, a2, a1 # t2= a2a1 - addu v1, v1, t1 # v1= a3a0 + hi(a2a0) - addu v1, v1, t2 # v1= v1 + a2a1; - - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - GET_INST_OPCODE(t1) # extract opcode from rINST - SET_VREG64_GOTO(v0, v1, rOBJ, t1) # vA/vA+1 <- v0(low)/v1(high) - -/* ------------------------------ */ - .balign 128 -.L_op_div_long_2addr: /* 0xbe */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0-a1 op a2-a3". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register pair other than a0-a1, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a2-a3). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a1) # a1 <- B - EAS2(a1, rFP, a1) # a1 <- &fp[B] - EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] - LOAD64(a2, a3, a1) # a2/a3 <- vB/vB+1 - LOAD64(a0, a1, t0) # a0/a1 <- vA/vA+1 - .if 1 - or t0, a2, a3 # second arg (a2-a3) is zero? - beqz t0, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - # optional op - JAL(__divdi3) # result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vA/vA+1 <- v0/v1 - -/* ------------------------------ */ - .balign 128 -.L_op_rem_long_2addr: /* 0xbf */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0-a1 op a2-a3". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register pair other than a0-a1, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a2-a3). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a1) # a1 <- B - EAS2(a1, rFP, a1) # a1 <- &fp[B] - EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] - LOAD64(a2, a3, a1) # a2/a3 <- vB/vB+1 - LOAD64(a0, a1, t0) # a0/a1 <- vA/vA+1 - .if 1 - or t0, a2, a3 # second arg (a2-a3) is zero? - beqz t0, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - # optional op - JAL(__moddi3) # result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vA/vA+1 <- v0/v1 - -/* ------------------------------ */ - .balign 128 -.L_op_and_long_2addr: /* 0xc0 */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0-a1 op a2-a3". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register pair other than a0-a1, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a2-a3). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a1) # a1 <- B - EAS2(a1, rFP, a1) # a1 <- &fp[B] - EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] - LOAD64(a2, a3, a1) # a2/a3 <- vB/vB+1 - LOAD64(a0, a1, t0) # a0/a1 <- vA/vA+1 - .if 0 - or t0, a2, a3 # second arg (a2-a3) is zero? - beqz t0, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - and a0, a0, a2 # optional op - and a1, a1, a3 # result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vA/vA+1 <- a0/a1 - -/* ------------------------------ */ - .balign 128 -.L_op_or_long_2addr: /* 0xc1 */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0-a1 op a2-a3". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register pair other than a0-a1, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a2-a3). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a1) # a1 <- B - EAS2(a1, rFP, a1) # a1 <- &fp[B] - EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] - LOAD64(a2, a3, a1) # a2/a3 <- vB/vB+1 - LOAD64(a0, a1, t0) # a0/a1 <- vA/vA+1 - .if 0 - or t0, a2, a3 # second arg (a2-a3) is zero? - beqz t0, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - or a0, a0, a2 # optional op - or a1, a1, a3 # result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vA/vA+1 <- a0/a1 - -/* ------------------------------ */ - .balign 128 -.L_op_xor_long_2addr: /* 0xc2 */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0-a1 op a2-a3". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register pair other than a0-a1, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a2-a3). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a1) # a1 <- B - EAS2(a1, rFP, a1) # a1 <- &fp[B] - EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] - LOAD64(a2, a3, a1) # a2/a3 <- vB/vB+1 - LOAD64(a0, a1, t0) # a0/a1 <- vA/vA+1 - .if 0 - or t0, a2, a3 # second arg (a2-a3) is zero? - beqz t0, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - xor a0, a0, a2 # optional op - xor a1, a1, a3 # result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vA/vA+1 <- a0/a1 - -/* ------------------------------ */ - .balign 128 -.L_op_shl_long_2addr: /* 0xc3 */ - /* - * Long integer shift, 2addr version. vA is 64-bit value/result, vB is - * 32-bit shift distance. - */ - /* shl-long/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a2, a3) # a2 <- vB - EAS2(t2, rFP, rOBJ) # t2 <- &fp[A] - LOAD64(a0, a1, t2) # a0/a1 <- vA/vA+1 - - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - - andi v1, a2, 0x20 # shift< shift & 0x20 - sll v0, a0, a2 # rlo<- alo << (shift&31) - bnez v1, .Lop_shl_long_2addr_finish - not v1, a2 # rhi<- 31-shift (shift is 5b) - srl a0, 1 - srl a0, v1 # alo<- alo >> (32-(shift&31)) - sll v1, a1, a2 # rhi<- ahi << (shift&31) - or v1, a0 # rhi<- rhi | alo - SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vA/vA+1 <- v0/v1 - -/* ------------------------------ */ - .balign 128 -.L_op_shr_long_2addr: /* 0xc4 */ - /* - * Long integer shift, 2addr version. vA is 64-bit value/result, vB is - * 32-bit shift distance. - */ - /* shr-long/2addr vA, vB */ - GET_OPA4(t2) # t2 <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a2, a3) # a2 <- vB - EAS2(t0, rFP, t2) # t0 <- &fp[A] - LOAD64(a0, a1, t0) # a0/a1 <- vA/vA+1 - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - - andi v0, a2, 0x20 # shift & 0x20 - sra v1, a1, a2 # rhi<- ahi >> (shift&31) - bnez v0, .Lop_shr_long_2addr_finish - srl v0, a0, a2 # rlo<- alo >> (shift&31) - not a0, a2 # alo<- 31-shift (shift is 5b) - sll a1, 1 - sll a1, a0 # ahi<- ahi << (32-(shift&31)) - or v0, a1 # rlo<- rlo | ahi - SET_VREG64_GOTO(v0, v1, t2, t0) # vA/vA+1 <- v0/v1 - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_long_2addr: /* 0xc5 */ - /* - * Long integer shift, 2addr version. vA is 64-bit value/result, vB is - * 32-bit shift distance. - */ - /* ushr-long/2addr vA, vB */ - GET_OPA4(t3) # t3 <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a2, a3) # a2 <- vB - EAS2(t0, rFP, t3) # t0 <- &fp[A] - LOAD64(a0, a1, t0) # a0/a1 <- vA/vA+1 - - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - - andi v0, a2, 0x20 # shift & 0x20 - srl v1, a1, a2 # rhi<- ahi >> (shift&31) - bnez v0, .Lop_ushr_long_2addr_finish - srl v0, a0, a2 # rlo<- alo >> (shift&31) - not a0, a2 # alo<- 31-n (shift is 5b) - sll a1, 1 - sll a1, a0 # ahi<- ahi << (32-(shift&31)) - or v0, a1 # rlo<- rlo | ahi - SET_VREG64_GOTO(v0, v1, t3, t0) # vA/vA+1 <- v0/v1 - -/* ------------------------------ */ - .balign 128 -.L_op_add_float_2addr: /* 0xc6 */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" - * that specifies an instruction that performs "fv0 = fa0 op fa1". - * This could be an MIPS instruction or a function call. - * - * For: add-float/2addr, sub-float/2addr, mul-float/2addr, - * div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG_F(fa0, rOBJ) - GET_VREG_F(fa1, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - add.s fv0, fa0, fa1 - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_F_GOTO(fv0, rOBJ, t0) # vA <- result - -/* ------------------------------ */ - .balign 128 -.L_op_sub_float_2addr: /* 0xc7 */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" - * that specifies an instruction that performs "fv0 = fa0 op fa1". - * This could be an MIPS instruction or a function call. - * - * For: add-float/2addr, sub-float/2addr, mul-float/2addr, - * div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG_F(fa0, rOBJ) - GET_VREG_F(fa1, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - sub.s fv0, fa0, fa1 - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_F_GOTO(fv0, rOBJ, t0) # vA <- result - -/* ------------------------------ */ - .balign 128 -.L_op_mul_float_2addr: /* 0xc8 */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" - * that specifies an instruction that performs "fv0 = fa0 op fa1". - * This could be an MIPS instruction or a function call. - * - * For: add-float/2addr, sub-float/2addr, mul-float/2addr, - * div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG_F(fa0, rOBJ) - GET_VREG_F(fa1, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - mul.s fv0, fa0, fa1 - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_F_GOTO(fv0, rOBJ, t0) # vA <- result - -/* ------------------------------ */ - .balign 128 -.L_op_div_float_2addr: /* 0xc9 */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" - * that specifies an instruction that performs "fv0 = fa0 op fa1". - * This could be an MIPS instruction or a function call. - * - * For: add-float/2addr, sub-float/2addr, mul-float/2addr, - * div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG_F(fa0, rOBJ) - GET_VREG_F(fa1, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - div.s fv0, fa0, fa1 - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_F_GOTO(fv0, rOBJ, t0) # vA <- result - -/* ------------------------------ */ - .balign 128 -.L_op_rem_float_2addr: /* 0xca */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" - * that specifies an instruction that performs "fv0 = fa0 op fa1". - * This could be an MIPS instruction or a function call. - * - * For: add-float/2addr, sub-float/2addr, mul-float/2addr, - * div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG_F(fa0, rOBJ) - GET_VREG_F(fa1, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - JAL(fmodf) - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_F_GOTO(fv0, rOBJ, t0) # vA <- result - -/* ------------------------------ */ - .balign 128 -.L_op_add_double_2addr: /* 0xcb */ - /* - * Generic 64-bit floating-point "/2addr" binary operation. - * Provide an "instr" line that specifies an instruction that - * performs "fv0 = fa0 op fa1". - * This could be an MIPS instruction or a function call. - * - * For: add-double/2addr, sub-double/2addr, mul-double/2addr, - * div-double/2addr, rem-double/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a1) # a1 <- B - EAS2(a1, rFP, a1) # a1 <- &fp[B] - EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] - LOAD64_F(fa0, fa0f, t0) - LOAD64_F(fa1, fa1f, a1) - - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - add.d fv0, fa0, fa1 - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vA/vA+1 <- fv0 - -/* ------------------------------ */ - .balign 128 -.L_op_sub_double_2addr: /* 0xcc */ - /* - * Generic 64-bit floating-point "/2addr" binary operation. - * Provide an "instr" line that specifies an instruction that - * performs "fv0 = fa0 op fa1". - * This could be an MIPS instruction or a function call. - * - * For: add-double/2addr, sub-double/2addr, mul-double/2addr, - * div-double/2addr, rem-double/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a1) # a1 <- B - EAS2(a1, rFP, a1) # a1 <- &fp[B] - EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] - LOAD64_F(fa0, fa0f, t0) - LOAD64_F(fa1, fa1f, a1) - - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - sub.d fv0, fa0, fa1 - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vA/vA+1 <- fv0 - -/* ------------------------------ */ - .balign 128 -.L_op_mul_double_2addr: /* 0xcd */ - /* - * Generic 64-bit floating-point "/2addr" binary operation. - * Provide an "instr" line that specifies an instruction that - * performs "fv0 = fa0 op fa1". - * This could be an MIPS instruction or a function call. - * - * For: add-double/2addr, sub-double/2addr, mul-double/2addr, - * div-double/2addr, rem-double/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a1) # a1 <- B - EAS2(a1, rFP, a1) # a1 <- &fp[B] - EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] - LOAD64_F(fa0, fa0f, t0) - LOAD64_F(fa1, fa1f, a1) - - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - mul.d fv0, fa0, fa1 - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vA/vA+1 <- fv0 - -/* ------------------------------ */ - .balign 128 -.L_op_div_double_2addr: /* 0xce */ - /* - * Generic 64-bit floating-point "/2addr" binary operation. - * Provide an "instr" line that specifies an instruction that - * performs "fv0 = fa0 op fa1". - * This could be an MIPS instruction or a function call. - * - * For: add-double/2addr, sub-double/2addr, mul-double/2addr, - * div-double/2addr, rem-double/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a1) # a1 <- B - EAS2(a1, rFP, a1) # a1 <- &fp[B] - EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] - LOAD64_F(fa0, fa0f, t0) - LOAD64_F(fa1, fa1f, a1) - - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - div.d fv0, fa0, fa1 - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vA/vA+1 <- fv0 - -/* ------------------------------ */ - .balign 128 -.L_op_rem_double_2addr: /* 0xcf */ - /* - * Generic 64-bit floating-point "/2addr" binary operation. - * Provide an "instr" line that specifies an instruction that - * performs "fv0 = fa0 op fa1". - * This could be an MIPS instruction or a function call. - * - * For: add-double/2addr, sub-double/2addr, mul-double/2addr, - * div-double/2addr, rem-double/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a1) # a1 <- B - EAS2(a1, rFP, a1) # a1 <- &fp[B] - EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] - LOAD64_F(fa0, fa0f, t0) - LOAD64_F(fa1, fa1f, a1) - - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - JAL(fmod) - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vA/vA+1 <- fv0 - -/* ------------------------------ */ - .balign 128 -.L_op_add_int_lit16: /* 0xd0 */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, +CCCC */ - FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) - GET_OPB(a2) # a2 <- B - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_VREG(a0, a2) # a0 <- vB - .if 0 - # cmp a1, 0; is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - # optional op - addu a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - -/* ------------------------------ */ - .balign 128 -.L_op_rsub_int: /* 0xd1 */ -/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, +CCCC */ - FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) - GET_OPB(a2) # a2 <- B - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_VREG(a0, a2) # a0 <- vB - .if 0 - # cmp a1, 0; is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - # optional op - subu a0, a1, a0 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int_lit16: /* 0xd2 */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, +CCCC */ - FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) - GET_OPB(a2) # a2 <- B - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_VREG(a0, a2) # a0 <- vB - .if 0 - # cmp a1, 0; is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - # optional op - mul a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - -/* ------------------------------ */ - .balign 128 -.L_op_div_int_lit16: /* 0xd3 */ -#ifdef MIPS32REVGE6 - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, +CCCC */ - FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) - GET_OPB(a2) # a2 <- B - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_VREG(a0, a2) # a0 <- vB - .if 1 - # cmp a1, 0; is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - # optional op - div a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - -#else - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, +CCCC */ - FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) - GET_OPB(a2) # a2 <- B - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_VREG(a0, a2) # a0 <- vB - .if 1 - # cmp a1, 0; is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - div zero, a0, a1 # optional op - mflo a0 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - -#endif - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int_lit16: /* 0xd4 */ -#ifdef MIPS32REVGE6 - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, +CCCC */ - FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) - GET_OPB(a2) # a2 <- B - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_VREG(a0, a2) # a0 <- vB - .if 1 - # cmp a1, 0; is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - # optional op - mod a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - -#else - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, +CCCC */ - FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) - GET_OPB(a2) # a2 <- B - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_VREG(a0, a2) # a0 <- vB - .if 1 - # cmp a1, 0; is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - div zero, a0, a1 # optional op - mfhi a0 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - -#endif - -/* ------------------------------ */ - .balign 128 -.L_op_and_int_lit16: /* 0xd5 */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, +CCCC */ - FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) - GET_OPB(a2) # a2 <- B - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_VREG(a0, a2) # a0 <- vB - .if 0 - # cmp a1, 0; is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - # optional op - and a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - -/* ------------------------------ */ - .balign 128 -.L_op_or_int_lit16: /* 0xd6 */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, +CCCC */ - FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) - GET_OPB(a2) # a2 <- B - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_VREG(a0, a2) # a0 <- vB - .if 0 - # cmp a1, 0; is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - # optional op - or a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int_lit16: /* 0xd7 */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, +CCCC */ - FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) - GET_OPB(a2) # a2 <- B - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_VREG(a0, a2) # a0 <- vB - .if 0 - # cmp a1, 0; is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - # optional op - xor a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - -/* ------------------------------ */ - .balign 128 -.L_op_add_int_lit8: /* 0xd8 */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, +CC */ - FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a3, 255 # a2 <- BB - GET_VREG(a0, a2) # a0 <- vBB - sra a1, a3, 8 # a1 <- ssssssCC (sign extended) - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - # optional op - addu a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - -/* ------------------------------ */ - .balign 128 -.L_op_rsub_int_lit8: /* 0xd9 */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, +CC */ - FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a3, 255 # a2 <- BB - GET_VREG(a0, a2) # a0 <- vBB - sra a1, a3, 8 # a1 <- ssssssCC (sign extended) - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - # optional op - subu a0, a1, a0 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int_lit8: /* 0xda */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, +CC */ - FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a3, 255 # a2 <- BB - GET_VREG(a0, a2) # a0 <- vBB - sra a1, a3, 8 # a1 <- ssssssCC (sign extended) - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - # optional op - mul a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - -/* ------------------------------ */ - .balign 128 -.L_op_div_int_lit8: /* 0xdb */ -#ifdef MIPS32REVGE6 - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, +CC */ - FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a3, 255 # a2 <- BB - GET_VREG(a0, a2) # a0 <- vBB - sra a1, a3, 8 # a1 <- ssssssCC (sign extended) - .if 1 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - # optional op - div a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - -#else - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, +CC */ - FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a3, 255 # a2 <- BB - GET_VREG(a0, a2) # a0 <- vBB - sra a1, a3, 8 # a1 <- ssssssCC (sign extended) - .if 1 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - div zero, a0, a1 # optional op - mflo a0 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - -#endif - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int_lit8: /* 0xdc */ -#ifdef MIPS32REVGE6 - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, +CC */ - FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a3, 255 # a2 <- BB - GET_VREG(a0, a2) # a0 <- vBB - sra a1, a3, 8 # a1 <- ssssssCC (sign extended) - .if 1 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - # optional op - mod a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - -#else - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, +CC */ - FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a3, 255 # a2 <- BB - GET_VREG(a0, a2) # a0 <- vBB - sra a1, a3, 8 # a1 <- ssssssCC (sign extended) - .if 1 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - div zero, a0, a1 # optional op - mfhi a0 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - -#endif - -/* ------------------------------ */ - .balign 128 -.L_op_and_int_lit8: /* 0xdd */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, +CC */ - FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a3, 255 # a2 <- BB - GET_VREG(a0, a2) # a0 <- vBB - sra a1, a3, 8 # a1 <- ssssssCC (sign extended) - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - # optional op - and a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - -/* ------------------------------ */ - .balign 128 -.L_op_or_int_lit8: /* 0xde */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, +CC */ - FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a3, 255 # a2 <- BB - GET_VREG(a0, a2) # a0 <- vBB - sra a1, a3, 8 # a1 <- ssssssCC (sign extended) - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - # optional op - or a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int_lit8: /* 0xdf */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, +CC */ - FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a3, 255 # a2 <- BB - GET_VREG(a0, a2) # a0 <- vBB - sra a1, a3, 8 # a1 <- ssssssCC (sign extended) - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - # optional op - xor a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - -/* ------------------------------ */ - .balign 128 -.L_op_shl_int_lit8: /* 0xe0 */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, +CC */ - FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a3, 255 # a2 <- BB - GET_VREG(a0, a2) # a0 <- vBB - sra a1, a3, 8 # a1 <- ssssssCC (sign extended) - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - # optional op - sll a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - -/* ------------------------------ */ - .balign 128 -.L_op_shr_int_lit8: /* 0xe1 */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, +CC */ - FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a3, 255 # a2 <- BB - GET_VREG(a0, a2) # a0 <- vBB - sra a1, a3, 8 # a1 <- ssssssCC (sign extended) - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - # optional op - sra a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_int_lit8: /* 0xe2 */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, +CC */ - FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a3, 255 # a2 <- BB - GET_VREG(a0, a2) # a0 <- vBB - sra a1, a3, 8 # a1 <- ssssssCC (sign extended) - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - # optional op - srl a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - -/* ------------------------------ */ - .balign 128 -.L_op_iget_quick: /* 0xe3 */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset@CCCC */ - GET_OPB(a2) # a2 <- B - GET_VREG(a3, a2) # a3 <- object we're operating on - FETCH(a1, 1) # a1 <- field byte offset - GET_OPA4(a2) # a2 <- A(+) - # check object for null - beqz a3, common_errNullObject # object was null - addu t0, a3, a1 - lw a0, 0(t0) # a0 <- obj.field (8/16/32 bits) - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, a2, t0) # fp[A] <- a0 - -/* ------------------------------ */ - .balign 128 -.L_op_iget_wide_quick: /* 0xe4 */ - /* iget-wide-quick vA, vB, offset@CCCC */ - GET_OPB(a2) # a2 <- B - GET_VREG(a3, a2) # a3 <- object we're operating on - FETCH(a1, 1) # a1 <- field byte offset - GET_OPA4(a2) # a2 <- A(+) - # check object for null - beqz a3, common_errNullObject # object was null - addu t0, a3, a1 # t0 <- a3 + a1 - LOAD64(a0, a1, t0) # a0 <- obj.field (64 bits, aligned) - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(a0, a1, a2, t0) # fp[A] <- a0/a1 - -/* ------------------------------ */ - .balign 128 -.L_op_iget_object_quick: /* 0xe5 */ - /* For: iget-object-quick */ - /* op vA, vB, offset@CCCC */ - GET_OPB(a2) # a2 <- B - FETCH(a1, 1) # a1 <- field byte offset - EXPORT_PC() - GET_VREG(a0, a2) # a0 <- object we're operating on - JAL(artIGetObjectFromMterp) # v0 <- GetObj(obj, offset) - lw a3, THREAD_EXCEPTION_OFFSET(rSELF) - GET_OPA4(a2) # a2<- A+ - PREFETCH_INST(2) # load rINST - bnez a3, MterpPossibleException # bail out - ADVANCE(2) # advance rPC - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_OBJECT_GOTO(v0, a2, t0) # fp[A] <- v0 - -/* ------------------------------ */ - .balign 128 -.L_op_iput_quick: /* 0xe6 */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - GET_OPB(a2) # a2 <- B - GET_VREG(a3, a2) # a3 <- fp[B], the object pointer - FETCH(a1, 1) # a1 <- field byte offset - GET_OPA4(a2) # a2 <- A(+) - beqz a3, common_errNullObject # object was null - GET_VREG(a0, a2) # a0 <- fp[A] - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - addu t0, a3, a1 - GET_INST_OPCODE(t1) # extract opcode from rINST - GET_OPCODE_TARGET(t1) - sw a0, 0(t0) # obj.field (8/16/32 bits) <- a0 - JR(t1) # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_wide_quick: /* 0xe7 */ - /* iput-wide-quick vA, vB, offset@CCCC */ - GET_OPA4(a0) # a0 <- A(+) - GET_OPB(a1) # a1 <- B - GET_VREG(a2, a1) # a2 <- fp[B], the object pointer - # check object for null - beqz a2, common_errNullObject # object was null - EAS2(a3, rFP, a0) # a3 <- &fp[A] - LOAD64(a0, a1, a3) # a0/a1 <- fp[A] - FETCH(a3, 1) # a3 <- field byte offset - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - addu a2, a2, a3 # obj.field (64 bits, aligned) <- a0/a1 - GET_INST_OPCODE(t0) # extract opcode from rINST - GET_OPCODE_TARGET(t0) - STORE64(a0, a1, a2) # obj.field (64 bits, aligned) <- a0/a1 - JR(t0) # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_object_quick: /* 0xe8 */ - /* For: iput-object-quick */ - /* op vA, vB, offset@CCCC */ - EXPORT_PC() - addu a0, rFP, OFF_FP_SHADOWFRAME - move a1, rPC - move a2, rINST - JAL(MterpIputObjectQuick) - beqz v0, MterpException - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual_quick: /* 0xe9 */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtualQuick - EXPORT_PC() - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - JAL(MterpInvokeVirtualQuick) - beqz v0, MterpException - FETCH_ADVANCE_INST(3) - JAL(MterpShouldSwitchInterpreters) - bnez v0, MterpFallback - GET_INST_OPCODE(t0) - GOTO_OPCODE(t0) - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual_range_quick: /* 0xea */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtualQuickRange - EXPORT_PC() - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - JAL(MterpInvokeVirtualQuickRange) - beqz v0, MterpException - FETCH_ADVANCE_INST(3) - JAL(MterpShouldSwitchInterpreters) - bnez v0, MterpFallback - GET_INST_OPCODE(t0) - GOTO_OPCODE(t0) - -/* ------------------------------ */ - .balign 128 -.L_op_iput_boolean_quick: /* 0xeb */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - GET_OPB(a2) # a2 <- B - GET_VREG(a3, a2) # a3 <- fp[B], the object pointer - FETCH(a1, 1) # a1 <- field byte offset - GET_OPA4(a2) # a2 <- A(+) - beqz a3, common_errNullObject # object was null - GET_VREG(a0, a2) # a0 <- fp[A] - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - addu t0, a3, a1 - GET_INST_OPCODE(t1) # extract opcode from rINST - GET_OPCODE_TARGET(t1) - sb a0, 0(t0) # obj.field (8/16/32 bits) <- a0 - JR(t1) # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_byte_quick: /* 0xec */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - GET_OPB(a2) # a2 <- B - GET_VREG(a3, a2) # a3 <- fp[B], the object pointer - FETCH(a1, 1) # a1 <- field byte offset - GET_OPA4(a2) # a2 <- A(+) - beqz a3, common_errNullObject # object was null - GET_VREG(a0, a2) # a0 <- fp[A] - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - addu t0, a3, a1 - GET_INST_OPCODE(t1) # extract opcode from rINST - GET_OPCODE_TARGET(t1) - sb a0, 0(t0) # obj.field (8/16/32 bits) <- a0 - JR(t1) # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_char_quick: /* 0xed */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - GET_OPB(a2) # a2 <- B - GET_VREG(a3, a2) # a3 <- fp[B], the object pointer - FETCH(a1, 1) # a1 <- field byte offset - GET_OPA4(a2) # a2 <- A(+) - beqz a3, common_errNullObject # object was null - GET_VREG(a0, a2) # a0 <- fp[A] - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - addu t0, a3, a1 - GET_INST_OPCODE(t1) # extract opcode from rINST - GET_OPCODE_TARGET(t1) - sh a0, 0(t0) # obj.field (8/16/32 bits) <- a0 - JR(t1) # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_short_quick: /* 0xee */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - GET_OPB(a2) # a2 <- B - GET_VREG(a3, a2) # a3 <- fp[B], the object pointer - FETCH(a1, 1) # a1 <- field byte offset - GET_OPA4(a2) # a2 <- A(+) - beqz a3, common_errNullObject # object was null - GET_VREG(a0, a2) # a0 <- fp[A] - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - addu t0, a3, a1 - GET_INST_OPCODE(t1) # extract opcode from rINST - GET_OPCODE_TARGET(t1) - sh a0, 0(t0) # obj.field (8/16/32 bits) <- a0 - JR(t1) # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iget_boolean_quick: /* 0xef */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset@CCCC */ - GET_OPB(a2) # a2 <- B - GET_VREG(a3, a2) # a3 <- object we're operating on - FETCH(a1, 1) # a1 <- field byte offset - GET_OPA4(a2) # a2 <- A(+) - # check object for null - beqz a3, common_errNullObject # object was null - addu t0, a3, a1 - lbu a0, 0(t0) # a0 <- obj.field (8/16/32 bits) - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, a2, t0) # fp[A] <- a0 - -/* ------------------------------ */ - .balign 128 -.L_op_iget_byte_quick: /* 0xf0 */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset@CCCC */ - GET_OPB(a2) # a2 <- B - GET_VREG(a3, a2) # a3 <- object we're operating on - FETCH(a1, 1) # a1 <- field byte offset - GET_OPA4(a2) # a2 <- A(+) - # check object for null - beqz a3, common_errNullObject # object was null - addu t0, a3, a1 - lb a0, 0(t0) # a0 <- obj.field (8/16/32 bits) - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, a2, t0) # fp[A] <- a0 - -/* ------------------------------ */ - .balign 128 -.L_op_iget_char_quick: /* 0xf1 */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset@CCCC */ - GET_OPB(a2) # a2 <- B - GET_VREG(a3, a2) # a3 <- object we're operating on - FETCH(a1, 1) # a1 <- field byte offset - GET_OPA4(a2) # a2 <- A(+) - # check object for null - beqz a3, common_errNullObject # object was null - addu t0, a3, a1 - lhu a0, 0(t0) # a0 <- obj.field (8/16/32 bits) - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, a2, t0) # fp[A] <- a0 - -/* ------------------------------ */ - .balign 128 -.L_op_iget_short_quick: /* 0xf2 */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset@CCCC */ - GET_OPB(a2) # a2 <- B - GET_VREG(a3, a2) # a3 <- object we're operating on - FETCH(a1, 1) # a1 <- field byte offset - GET_OPA4(a2) # a2 <- A(+) - # check object for null - beqz a3, common_errNullObject # object was null - addu t0, a3, a1 - lh a0, 0(t0) # a0 <- obj.field (8/16/32 bits) - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, a2, t0) # fp[A] <- a0 - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f3: /* 0xf3 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f4: /* 0xf4 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f5: /* 0xf5 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f6: /* 0xf6 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f7: /* 0xf7 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f8: /* 0xf8 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f9: /* 0xf9 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_polymorphic: /* 0xfa */ - /* - * invoke-polymorphic handler wrapper. - */ - /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ - .extern MterpInvokePolymorphic - EXPORT_PC() - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - JAL(MterpInvokePolymorphic) - beqz v0, MterpException - FETCH_ADVANCE_INST(4) - JAL(MterpShouldSwitchInterpreters) - bnez v0, MterpFallback - GET_INST_OPCODE(t0) - GOTO_OPCODE(t0) - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_polymorphic_range: /* 0xfb */ - /* - * invoke-polymorphic handler wrapper. - */ - /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ - .extern MterpInvokePolymorphicRange - EXPORT_PC() - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - JAL(MterpInvokePolymorphicRange) - beqz v0, MterpException - FETCH_ADVANCE_INST(4) - JAL(MterpShouldSwitchInterpreters) - bnez v0, MterpFallback - GET_INST_OPCODE(t0) - GOTO_OPCODE(t0) - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_custom: /* 0xfc */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeCustom - EXPORT_PC() - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - JAL(MterpInvokeCustom) - beqz v0, MterpException - FETCH_ADVANCE_INST(3) - JAL(MterpShouldSwitchInterpreters) - bnez v0, MterpFallback - GET_INST_OPCODE(t0) - GOTO_OPCODE(t0) - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_custom_range: /* 0xfd */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeCustomRange - EXPORT_PC() - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - JAL(MterpInvokeCustomRange) - beqz v0, MterpException - FETCH_ADVANCE_INST(3) - JAL(MterpShouldSwitchInterpreters) - bnez v0, MterpFallback - GET_INST_OPCODE(t0) - GOTO_OPCODE(t0) - -/* ------------------------------ */ - .balign 128 -.L_op_const_method_handle: /* 0xfe */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstMethodHandle - EXPORT_PC() - FETCH(a0, 1) # a0 <- BBBB - GET_OPA(a1) # a1 <- AA - addu a2, rFP, OFF_FP_SHADOWFRAME # a2 <- shadow frame - move a3, rSELF - JAL(MterpConstMethodHandle) # v0 <- Mterp(index, tgt_reg, shadow_frame, self) - PREFETCH_INST(2) # load rINST - bnez v0, MterpPossibleException - ADVANCE(2) # advance rPC - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_method_type: /* 0xff */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstMethodType - EXPORT_PC() - FETCH(a0, 1) # a0 <- BBBB - GET_OPA(a1) # a1 <- AA - addu a2, rFP, OFF_FP_SHADOWFRAME # a2 <- shadow frame - move a3, rSELF - JAL(MterpConstMethodType) # v0 <- Mterp(index, tgt_reg, shadow_frame, self) - PREFETCH_INST(2) # load rINST - bnez v0, MterpPossibleException - ADVANCE(2) # advance rPC - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - - .balign 128 - - .global artMterpAsmInstructionEnd -artMterpAsmInstructionEnd: - -#ifndef MIPS32REVGE6 -.Lop_float_to_long_get_opcode: - GET_INST_OPCODE(t1) # extract opcode from rINST -.Lop_float_to_long_set_vreg: - SET_VREG64_GOTO(rRESULT0, rRESULT1, rOBJ, t1) # vA/vA+1 <- v0/v1 -#endif - -#ifndef MIPS32REVGE6 -.Lop_double_to_long_get_opcode: - GET_INST_OPCODE(t1) # extract opcode from rINST -.Lop_double_to_long_set_vreg: - SET_VREG64_GOTO(rRESULT0, rRESULT1, rOBJ, t1) # vA/vA+1 <- v0/v1 -#endif - -.Lop_mul_long_finish: - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(v0, v1, a0, t0) # vAA/vAA+1 <- v0(low)/v1(high) - -.Lop_shl_long_finish: - SET_VREG64_GOTO(zero, v0, t2, t0) # vAA/vAA+1 <- rlo/rhi - -.Lop_shr_long_finish: - sra a3, a1, 31 # a3<- sign(ah) - SET_VREG64_GOTO(v1, a3, t3, t0) # vAA/VAA+1 <- rlo/rhi - -.Lop_ushr_long_finish: - SET_VREG64_GOTO(v1, zero, rOBJ, t0) # vAA/vAA+1 <- rlo/rhi - -.Lop_shl_long_2addr_finish: - SET_VREG64_GOTO(zero, v0, rOBJ, t0) # vA/vA+1 <- rlo/rhi - -.Lop_shr_long_2addr_finish: - sra a3, a1, 31 # a3<- sign(ah) - SET_VREG64_GOTO(v1, a3, t2, t0) # vA/vA+1 <- rlo/rhi - -.Lop_ushr_long_2addr_finish: - SET_VREG64_GOTO(v1, zero, t3, t0) # vA/vA+1 <- rlo/rhi - - .global artMterpAsmAltInstructionStart -artMterpAsmAltInstructionStart = .L_ALT_op_nop - .text - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_nop: /* 0x00 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (0 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move: /* 0x01 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (1 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_from16: /* 0x02 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (2 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_16: /* 0x03 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (3 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_wide: /* 0x04 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (4 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_wide_from16: /* 0x05 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (5 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_wide_16: /* 0x06 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (6 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_object: /* 0x07 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (7 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_object_from16: /* 0x08 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (8 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_object_16: /* 0x09 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (9 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_result: /* 0x0a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (10 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_result_wide: /* 0x0b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (11 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_result_object: /* 0x0c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (12 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_exception: /* 0x0d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (13 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_void: /* 0x0e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (14 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return: /* 0x0f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (15 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_wide: /* 0x10 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (16 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_object: /* 0x11 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (17 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_4: /* 0x12 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (18 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_16: /* 0x13 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (19 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const: /* 0x14 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (20 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_high16: /* 0x15 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (21 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide_16: /* 0x16 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (22 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide_32: /* 0x17 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (23 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide: /* 0x18 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (24 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide_high16: /* 0x19 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (25 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_string: /* 0x1a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (26 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_string_jumbo: /* 0x1b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (27 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_class: /* 0x1c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (28 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_monitor_enter: /* 0x1d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (29 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_monitor_exit: /* 0x1e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (30 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_check_cast: /* 0x1f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (31 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_instance_of: /* 0x20 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (32 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_array_length: /* 0x21 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (33 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_new_instance: /* 0x22 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (34 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_new_array: /* 0x23 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (35 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_filled_new_array: /* 0x24 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (36 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_filled_new_array_range: /* 0x25 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (37 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_fill_array_data: /* 0x26 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (38 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_throw: /* 0x27 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (39 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_goto: /* 0x28 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (40 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_goto_16: /* 0x29 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (41 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_goto_32: /* 0x2a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (42 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_packed_switch: /* 0x2b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (43 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sparse_switch: /* 0x2c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (44 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpl_float: /* 0x2d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (45 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpg_float: /* 0x2e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (46 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpl_double: /* 0x2f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (47 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpg_double: /* 0x30 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (48 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmp_long: /* 0x31 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (49 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_eq: /* 0x32 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (50 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_ne: /* 0x33 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (51 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_lt: /* 0x34 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (52 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_ge: /* 0x35 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (53 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_gt: /* 0x36 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (54 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_le: /* 0x37 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (55 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_eqz: /* 0x38 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (56 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_nez: /* 0x39 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (57 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_ltz: /* 0x3a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (58 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_gez: /* 0x3b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (59 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_gtz: /* 0x3c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (60 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_lez: /* 0x3d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (61 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_3e: /* 0x3e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (62 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_3f: /* 0x3f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (63 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_40: /* 0x40 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (64 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_41: /* 0x41 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (65 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_42: /* 0x42 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (66 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_43: /* 0x43 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (67 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget: /* 0x44 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (68 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_wide: /* 0x45 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (69 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_object: /* 0x46 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (70 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_boolean: /* 0x47 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (71 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_byte: /* 0x48 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (72 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_char: /* 0x49 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (73 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_short: /* 0x4a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (74 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput: /* 0x4b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (75 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_wide: /* 0x4c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (76 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_object: /* 0x4d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (77 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_boolean: /* 0x4e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (78 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_byte: /* 0x4f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (79 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_char: /* 0x50 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (80 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_short: /* 0x51 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (81 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget: /* 0x52 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (82 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_wide: /* 0x53 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (83 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_object: /* 0x54 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (84 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_boolean: /* 0x55 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (85 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_byte: /* 0x56 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (86 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_char: /* 0x57 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (87 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_short: /* 0x58 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (88 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput: /* 0x59 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (89 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_wide: /* 0x5a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (90 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_object: /* 0x5b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (91 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_boolean: /* 0x5c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (92 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_byte: /* 0x5d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (93 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_char: /* 0x5e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (94 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_short: /* 0x5f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (95 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget: /* 0x60 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (96 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_wide: /* 0x61 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (97 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_object: /* 0x62 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (98 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_boolean: /* 0x63 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (99 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_byte: /* 0x64 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (100 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_char: /* 0x65 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (101 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_short: /* 0x66 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (102 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput: /* 0x67 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (103 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_wide: /* 0x68 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (104 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_object: /* 0x69 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (105 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_boolean: /* 0x6a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (106 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_byte: /* 0x6b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (107 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_char: /* 0x6c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (108 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_short: /* 0x6d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (109 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual: /* 0x6e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (110 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_super: /* 0x6f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (111 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_direct: /* 0x70 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (112 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_static: /* 0x71 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (113 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_interface: /* 0x72 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (114 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_void_no_barrier: /* 0x73 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (115 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual_range: /* 0x74 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (116 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_super_range: /* 0x75 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (117 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_direct_range: /* 0x76 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (118 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_static_range: /* 0x77 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (119 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_interface_range: /* 0x78 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (120 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_79: /* 0x79 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (121 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_7a: /* 0x7a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (122 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_int: /* 0x7b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (123 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_not_int: /* 0x7c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (124 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_long: /* 0x7d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (125 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_not_long: /* 0x7e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (126 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_float: /* 0x7f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (127 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_double: /* 0x80 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (128 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_long: /* 0x81 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (129 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_float: /* 0x82 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (130 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_double: /* 0x83 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (131 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_long_to_int: /* 0x84 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (132 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_long_to_float: /* 0x85 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (133 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_long_to_double: /* 0x86 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (134 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_float_to_int: /* 0x87 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (135 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_float_to_long: /* 0x88 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (136 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_float_to_double: /* 0x89 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (137 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_double_to_int: /* 0x8a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (138 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_double_to_long: /* 0x8b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (139 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_double_to_float: /* 0x8c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (140 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_byte: /* 0x8d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (141 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_char: /* 0x8e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (142 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_short: /* 0x8f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (143 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int: /* 0x90 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (144 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_int: /* 0x91 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (145 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int: /* 0x92 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (146 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int: /* 0x93 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (147 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int: /* 0x94 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (148 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int: /* 0x95 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (149 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int: /* 0x96 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (150 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int: /* 0x97 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (151 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_int: /* 0x98 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (152 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_int: /* 0x99 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (153 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_int: /* 0x9a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (154 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_long: /* 0x9b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (155 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_long: /* 0x9c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (156 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_long: /* 0x9d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (157 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_long: /* 0x9e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (158 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_long: /* 0x9f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (159 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_long: /* 0xa0 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (160 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_long: /* 0xa1 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (161 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_long: /* 0xa2 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (162 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_long: /* 0xa3 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (163 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_long: /* 0xa4 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (164 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_long: /* 0xa5 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (165 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_float: /* 0xa6 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (166 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_float: /* 0xa7 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (167 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_float: /* 0xa8 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (168 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_float: /* 0xa9 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (169 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_float: /* 0xaa */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (170 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_double: /* 0xab */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (171 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_double: /* 0xac */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (172 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_double: /* 0xad */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (173 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_double: /* 0xae */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (174 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_double: /* 0xaf */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (175 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int_2addr: /* 0xb0 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (176 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_int_2addr: /* 0xb1 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (177 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int_2addr: /* 0xb2 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (178 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int_2addr: /* 0xb3 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (179 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int_2addr: /* 0xb4 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (180 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int_2addr: /* 0xb5 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (181 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int_2addr: /* 0xb6 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (182 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int_2addr: /* 0xb7 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (183 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_int_2addr: /* 0xb8 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (184 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_int_2addr: /* 0xb9 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (185 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_int_2addr: /* 0xba */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (186 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_long_2addr: /* 0xbb */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (187 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_long_2addr: /* 0xbc */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (188 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_long_2addr: /* 0xbd */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (189 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_long_2addr: /* 0xbe */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (190 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_long_2addr: /* 0xbf */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (191 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_long_2addr: /* 0xc0 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (192 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_long_2addr: /* 0xc1 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (193 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_long_2addr: /* 0xc2 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (194 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_long_2addr: /* 0xc3 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (195 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_long_2addr: /* 0xc4 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (196 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_long_2addr: /* 0xc5 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (197 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_float_2addr: /* 0xc6 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (198 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_float_2addr: /* 0xc7 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (199 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_float_2addr: /* 0xc8 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (200 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_float_2addr: /* 0xc9 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (201 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_float_2addr: /* 0xca */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (202 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_double_2addr: /* 0xcb */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (203 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_double_2addr: /* 0xcc */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (204 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_double_2addr: /* 0xcd */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (205 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_double_2addr: /* 0xce */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (206 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_double_2addr: /* 0xcf */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (207 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int_lit16: /* 0xd0 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (208 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rsub_int: /* 0xd1 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (209 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int_lit16: /* 0xd2 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (210 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int_lit16: /* 0xd3 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (211 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int_lit16: /* 0xd4 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (212 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int_lit16: /* 0xd5 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (213 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int_lit16: /* 0xd6 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (214 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int_lit16: /* 0xd7 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (215 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int_lit8: /* 0xd8 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (216 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rsub_int_lit8: /* 0xd9 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (217 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int_lit8: /* 0xda */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (218 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int_lit8: /* 0xdb */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (219 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int_lit8: /* 0xdc */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (220 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int_lit8: /* 0xdd */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (221 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int_lit8: /* 0xde */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (222 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int_lit8: /* 0xdf */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (223 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_int_lit8: /* 0xe0 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (224 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_int_lit8: /* 0xe1 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (225 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_int_lit8: /* 0xe2 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (226 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_quick: /* 0xe3 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (227 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_wide_quick: /* 0xe4 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (228 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_object_quick: /* 0xe5 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (229 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_quick: /* 0xe6 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (230 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_wide_quick: /* 0xe7 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (231 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_object_quick: /* 0xe8 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (232 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual_quick: /* 0xe9 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (233 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual_range_quick: /* 0xea */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (234 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_boolean_quick: /* 0xeb */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (235 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_byte_quick: /* 0xec */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (236 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_char_quick: /* 0xed */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (237 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_short_quick: /* 0xee */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (238 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_boolean_quick: /* 0xef */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (239 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_byte_quick: /* 0xf0 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (240 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_char_quick: /* 0xf1 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (241 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_short_quick: /* 0xf2 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (242 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f3: /* 0xf3 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (243 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f4: /* 0xf4 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (244 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f5: /* 0xf5 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (245 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f6: /* 0xf6 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (246 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f7: /* 0xf7 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (247 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f8: /* 0xf8 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (248 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f9: /* 0xf9 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (249 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_polymorphic: /* 0xfa */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (250 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_polymorphic_range: /* 0xfb */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (251 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_custom: /* 0xfc */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (252 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_custom_range: /* 0xfd */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (253 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_method_handle: /* 0xfe */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (254 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_method_type: /* 0xff */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (255 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - - .balign 128 - - .global artMterpAsmAltInstructionEnd -artMterpAsmAltInstructionEnd: - -/* - * =========================================================================== - * Common subroutines and data - * =========================================================================== - */ - - .text - .align 2 - -/* - * We've detected a condition that will result in an exception, but the exception - * has not yet been thrown. Just bail out to the reference interpreter to deal with it. - * TUNING: for consistency, we may want to just go ahead and handle these here. - */ -common_errDivideByZero: - EXPORT_PC() -#if MTERP_LOGGING - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - JAL(MterpLogDivideByZeroException) -#endif - b MterpCommonFallback - -common_errArrayIndex: - EXPORT_PC() -#if MTERP_LOGGING - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - JAL(MterpLogArrayIndexException) -#endif - b MterpCommonFallback - -common_errNegativeArraySize: - EXPORT_PC() -#if MTERP_LOGGING - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - JAL(MterpLogNegativeArraySizeException) -#endif - b MterpCommonFallback - -common_errNoSuchMethod: - EXPORT_PC() -#if MTERP_LOGGING - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - JAL(MterpLogNoSuchMethodException) -#endif - b MterpCommonFallback - -common_errNullObject: - EXPORT_PC() -#if MTERP_LOGGING - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - JAL(MterpLogNullObjectException) -#endif - b MterpCommonFallback - -common_exceptionThrown: - EXPORT_PC() -#if MTERP_LOGGING - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - JAL(MterpLogExceptionThrownException) -#endif - b MterpCommonFallback - -MterpSuspendFallback: - EXPORT_PC() -#if MTERP_LOGGING - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - lw a2, THREAD_FLAGS_OFFSET(rSELF) - JAL(MterpLogSuspendFallback) -#endif - b MterpCommonFallback - -/* - * If we're here, something is out of the ordinary. If there is a pending - * exception, handle it. Otherwise, roll back and retry with the reference - * interpreter. - */ -MterpPossibleException: - lw a0, THREAD_EXCEPTION_OFFSET(rSELF) - beqz a0, MterpFallback # If exception, fall back to reference interpreter. - /* intentional fallthrough - handle pending exception. */ -/* - * On return from a runtime helper routine, we've found a pending exception. - * Can we handle it here - or need to bail out to caller? - * - */ -MterpException: - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - JAL(MterpHandleException) # (self, shadow_frame) - beqz v0, MterpExceptionReturn # no local catch, back to caller. - lw a0, OFF_FP_DEX_INSTRUCTIONS(rFP) - lw a1, OFF_FP_DEX_PC(rFP) - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) - EAS1(rPC, a0, a1) # generate new dex_pc_ptr - /* Do we need to switch interpreters? */ - JAL(MterpShouldSwitchInterpreters) - bnez v0, MterpFallback - /* resume execution at catch block */ - EXPORT_PC() - FETCH_INST() - GET_INST_OPCODE(t0) - GOTO_OPCODE(t0) - /* NOTE: no fallthrough */ - -/* - * Common handling for branches with support for Jit profiling. - * On entry: - * rINST <= signed offset - * rPROFILE <= signed hotness countdown (expanded to 32 bits) - * - * We have quite a few different cases for branch profiling, OSR detection and - * suspend check support here. - * - * Taken backward branches: - * If profiling active, do hotness countdown and report if we hit zero. - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * Is there a pending suspend request? If so, suspend. - * - * Taken forward branches and not-taken backward branches: - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * - * Our most common case is expected to be a taken backward branch with active jit profiling, - * but no full OSR check and no pending suspend request. - * Next most common case is not-taken branch with no full OSR check. - */ -MterpCommonTakenBranchNoFlags: - bgtz rINST, .L_forward_branch # don't add forward branches to hotness -/* - * We need to subtract 1 from positive values and we should not see 0 here, - * so we may use the result of the comparison with -1. - */ -#if JIT_CHECK_OSR != -1 -# error "JIT_CHECK_OSR must be -1." -#endif - li t0, JIT_CHECK_OSR - beq rPROFILE, t0, .L_osr_check - blt rPROFILE, t0, .L_resume_backward_branch - subu rPROFILE, 1 - beqz rPROFILE, .L_add_batch # counted down to zero - report -.L_resume_backward_branch: - lw ra, THREAD_FLAGS_OFFSET(rSELF) - REFRESH_IBASE() - addu a2, rINST, rINST # a2<- byte offset - FETCH_ADVANCE_INST_RB(a2) # update rPC, load rINST - and ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - bnez ra, .L_suspend_request_pending - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - -.L_suspend_request_pending: - EXPORT_PC() - move a0, rSELF - JAL(MterpSuspendCheck) # (self) - bnez v0, MterpFallback - REFRESH_IBASE() # might have changed during suspend - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - -.L_no_count_backwards: - li t0, JIT_CHECK_OSR # check for possible OSR re-entry - bne rPROFILE, t0, .L_resume_backward_branch -.L_osr_check: - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rINST - EXPORT_PC() - JAL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) - bnez v0, MterpOnStackReplacement - b .L_resume_backward_branch - -.L_forward_branch: - li t0, JIT_CHECK_OSR # check for possible OSR re-entry - beq rPROFILE, t0, .L_check_osr_forward -.L_resume_forward_branch: - add a2, rINST, rINST # a2<- byte offset - FETCH_ADVANCE_INST_RB(a2) # update rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - -.L_check_osr_forward: - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rINST - EXPORT_PC() - JAL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) - bnez v0, MterpOnStackReplacement - b .L_resume_forward_branch - -.L_add_batch: - addu a1, rFP, OFF_FP_SHADOWFRAME - sh rPROFILE, SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET(a1) - lw a0, OFF_FP_METHOD(rFP) - move a2, rSELF - JAL(MterpAddHotnessBatch) # (method, shadow_frame, self) - move rPROFILE, v0 # restore new hotness countdown to rPROFILE - b .L_no_count_backwards - -/* - * Entered from the conditional branch handlers when OSR check request active on - * not-taken path. All Dalvik not-taken conditional branch offsets are 2. - */ -.L_check_not_taken_osr: - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - li a2, 2 - EXPORT_PC() - JAL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) - bnez v0, MterpOnStackReplacement - FETCH_ADVANCE_INST(2) - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - -/* - * On-stack replacement has happened, and now we've returned from the compiled method. - */ -MterpOnStackReplacement: -#if MTERP_LOGGING - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rINST - JAL(MterpLogOSR) -#endif - li v0, 1 # Signal normal return - b MterpDone - -/* - * Bail out to reference interpreter. - */ -MterpFallback: - EXPORT_PC() -#if MTERP_LOGGING - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - JAL(MterpLogFallback) -#endif -MterpCommonFallback: - move v0, zero # signal retry with reference interpreter. - b MterpDone -/* - * We pushed some registers on the stack in ExecuteMterpImpl, then saved - * SP and LR. Here we restore SP, restore the registers, and then restore - * LR to PC. - * - * On entry: - * uint32_t* rFP (should still be live, pointer to base of vregs) - */ -MterpExceptionReturn: - li v0, 1 # signal return to caller. - b MterpDone -MterpReturn: - lw a2, OFF_FP_RESULT_REGISTER(rFP) - sw v0, 0(a2) - sw v1, 4(a2) - li v0, 1 # signal return to caller. -MterpDone: -/* - * At this point, we expect rPROFILE to be non-zero. If negative, hotness is disabled or we're - * checking for OSR. If greater than zero, we might have unreported hotness to register - * (the difference between the ending rPROFILE and the cached hotness counter). rPROFILE - * should only reach zero immediately after a hotness decrement, and is then reset to either - * a negative special state or the new non-zero countdown value. - */ - blez rPROFILE, .L_pop_and_return # if > 0, we may have some counts to report. - -MterpProfileActive: - move rINST, v0 # stash return value - /* Report cached hotness counts */ - lw a0, OFF_FP_METHOD(rFP) - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rSELF - sh rPROFILE, SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET(a1) - JAL(MterpAddHotnessBatch) # (method, shadow_frame, self) - move v0, rINST # restore return value - -.L_pop_and_return: -/* Restore from the stack and return. Frame size = STACK_SIZE */ - STACK_LOAD_FULL() - jalr zero, ra - - .cfi_endproc - .end ExecuteMterpImpl - diff --git a/runtime/interpreter/mterp/out/mterp_mips64.S b/runtime/interpreter/mterp/out/mterp_mips64.S deleted file mode 100644 index fa0744259c..0000000000 --- a/runtime/interpreter/mterp/out/mterp_mips64.S +++ /dev/null @@ -1,10963 +0,0 @@ -/* DO NOT EDIT: This file was generated by gen-mterp.py. */ -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#define zero $0 /* always zero */ -#define AT $at /* assembler temp */ -#define v0 $2 /* return value */ -#define v1 $3 -#define a0 $4 /* argument registers */ -#define a1 $5 -#define a2 $6 -#define a3 $7 -#define a4 $8 /* expanded register arguments */ -#define a5 $9 -#define a6 $10 -#define a7 $11 -#define ta0 $8 /* alias */ -#define ta1 $9 -#define ta2 $10 -#define ta3 $11 -#define t0 $12 /* temp registers (not saved across subroutine calls) */ -#define t1 $13 -#define t2 $14 -#define t3 $15 - -#define s0 $16 /* saved across subroutine calls (callee saved) */ -#define s1 $17 -#define s2 $18 -#define s3 $19 -#define s4 $20 -#define s5 $21 -#define s6 $22 -#define s7 $23 -#define t8 $24 /* two more temp registers */ -#define t9 $25 -#define k0 $26 /* kernel temporary */ -#define k1 $27 -#define gp $28 /* global pointer */ -#define sp $29 /* stack pointer */ -#define s8 $30 /* one more callee saved */ -#define ra $31 /* return address */ - -#define f0 $f0 -#define f1 $f1 -#define f2 $f2 -#define f3 $f3 -#define f12 $f12 -#define f13 $f13 - -/* - * It looks like the GNU assembler currently does not support the blec and bgtc - * idioms, which should translate into bgec and bltc respectively with swapped - * left and right register operands. - * TODO: remove these macros when the assembler is fixed. - */ -.macro blec lreg, rreg, target - bgec \rreg, \lreg, \target -.endm -.macro bgtc lreg, rreg, target - bltc \rreg, \lreg, \target -.endm - -/* -Mterp and MIPS64 notes: - -The following registers have fixed assignments: - - reg nick purpose - s0 rPC interpreted program counter, used for fetching instructions - s1 rFP interpreted frame pointer, used for accessing locals and args - s2 rSELF self (Thread) pointer - s3 rINST first 16-bit code unit of current instruction - s4 rIBASE interpreted instruction base pointer, used for computed goto - s5 rREFS base of object references in shadow frame (ideally, we'll get rid of this later). - s6 rPROFILE jit profile hotness countdown -*/ - -/* During bringup, we'll use the shadow frame model instead of rFP */ -/* single-purpose registers, given names for clarity */ -#define rPC s0 -#define CFI_DEX 16 // DWARF register number of the register holding dex-pc (s0). -#define CFI_TMP 4 // DWARF register number of the first argument register (a0). -#define rFP s1 -#define rSELF s2 -#define rINST s3 -#define rIBASE s4 -#define rREFS s5 -#define rPROFILE s6 - -/* - * This is a #include, not a %include, because we want the C pre-processor - * to expand the macros into assembler assignment statements. - */ -#include "asm_support.h" -#include "interpreter/cfi_asm_support.h" - -/* - * Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs. So, - * to access other shadow frame fields, we need to use a backwards offset. Define those here. - */ -#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) -#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) -#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) -#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) -#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) -#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) -#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) -#define OFF_FP_DEX_INSTRUCTIONS OFF_FP(SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET) -#define OFF_FP_SHADOWFRAME OFF_FP(0) - -#define MTERP_PROFILE_BRANCHES 1 -#define MTERP_LOGGING 0 - -/* - * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must - * be done *before* something throws. - * - * It's okay to do this more than once. - * - * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped - * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction - * offset into the code_items_[] array. For effiency, we will "export" the - * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC - * to convert to a dex pc when needed. - */ -.macro EXPORT_PC - sd rPC, OFF_FP_DEX_PC_PTR(rFP) -.endm - -/* - * Refresh handler table. - */ -.macro REFRESH_IBASE - ld rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) -.endm - -/* - * Fetch the next instruction from rPC into rINST. Does not advance rPC. - */ -.macro FETCH_INST - lhu rINST, 0(rPC) -.endm - -/* Advance rPC by some number of code units. */ -.macro ADVANCE count - daddu rPC, rPC, (\count) * 2 -.endm - -/* - * Fetch the next instruction from an offset specified by _reg and advance xPC. - * xPC to point to the next instruction. "_reg" must specify the distance - * in bytes, *not* 16-bit code units, and may be a signed value. Must not set flags. - * - */ -.macro FETCH_ADVANCE_INST_RB reg - daddu rPC, rPC, \reg - FETCH_INST -.endm - -/* - * Fetch the next instruction from the specified offset. Advances rPC - * to point to the next instruction. - * - * This must come AFTER anything that can throw an exception, or the - * exception catch may miss. (This also implies that it must come after - * EXPORT_PC.) - */ -.macro FETCH_ADVANCE_INST count - ADVANCE \count - FETCH_INST -.endm - -/* - * Similar to FETCH_ADVANCE_INST, but does not update rPC. Used to load - * rINST ahead of possible exception point. Be sure to manually advance rPC - * later. - */ -.macro PREFETCH_INST count - lhu rINST, ((\count) * 2)(rPC) -.endm - -/* - * Put the instruction's opcode field into the specified register. - */ -.macro GET_INST_OPCODE reg - and \reg, rINST, 255 -.endm - -/* - * Begin executing the opcode in _reg. - */ -.macro GOTO_OPCODE reg - .set noat - sll AT, \reg, 7 - daddu AT, rIBASE, AT - jic AT, 0 - .set at -.endm - -/* - * Get/set the 32-bit value from a Dalvik register. - * Note, GET_VREG does sign extension to 64 bits while - * GET_VREG_U does zero extension to 64 bits. - * One is useful for arithmetic while the other is - * useful for storing the result value as 64-bit. - */ -.macro GET_VREG reg, vreg - .set noat - dlsa AT, \vreg, rFP, 2 - lw \reg, 0(AT) - .set at -.endm -.macro GET_VREG_U reg, vreg - .set noat - dlsa AT, \vreg, rFP, 2 - lwu \reg, 0(AT) - .set at -.endm -.macro GET_VREG_FLOAT reg, vreg - .set noat - dlsa AT, \vreg, rFP, 2 - lwc1 \reg, 0(AT) - .set at -.endm -.macro SET_VREG reg, vreg - .set noat - dlsa AT, \vreg, rFP, 2 - sw \reg, 0(AT) - dlsa AT, \vreg, rREFS, 2 - sw zero, 0(AT) - .set at -.endm -.macro SET_VREG_OBJECT reg, vreg - .set noat - dlsa AT, \vreg, rFP, 2 - sw \reg, 0(AT) - dlsa AT, \vreg, rREFS, 2 - sw \reg, 0(AT) - .set at -.endm -.macro SET_VREG_FLOAT reg, vreg - .set noat - dlsa AT, \vreg, rFP, 2 - swc1 \reg, 0(AT) - dlsa AT, \vreg, rREFS, 2 - sw zero, 0(AT) - .set at -.endm - -/* - * Get/set the 64-bit value from a Dalvik register. - * Avoid unaligned memory accesses. - * Note, SET_VREG_WIDE clobbers the register containing the value being stored. - * Note, SET_VREG_DOUBLE clobbers the register containing the Dalvik register number. - */ -.macro GET_VREG_WIDE reg, vreg - .set noat - dlsa AT, \vreg, rFP, 2 - lw \reg, 0(AT) - lw AT, 4(AT) - dinsu \reg, AT, 32, 32 - .set at -.endm -.macro GET_VREG_DOUBLE reg, vreg - .set noat - dlsa AT, \vreg, rFP, 2 - lwc1 \reg, 0(AT) - lw AT, 4(AT) - mthc1 AT, \reg - .set at -.endm -.macro SET_VREG_WIDE reg, vreg - .set noat - dlsa AT, \vreg, rFP, 2 - sw \reg, 0(AT) - drotr32 \reg, \reg, 0 - sw \reg, 4(AT) - dlsa AT, \vreg, rREFS, 2 - sw zero, 0(AT) - sw zero, 4(AT) - .set at -.endm -.macro SET_VREG_DOUBLE reg, vreg - .set noat - dlsa AT, \vreg, rREFS, 2 - sw zero, 0(AT) - sw zero, 4(AT) - dlsa AT, \vreg, rFP, 2 - swc1 \reg, 0(AT) - mfhc1 \vreg, \reg - sw \vreg, 4(AT) - .set at -.endm - -/* - * On-stack offsets for spilling/unspilling callee-saved registers - * and the frame size. - */ -#define STACK_OFFSET_RA 0 -#define STACK_OFFSET_GP 8 -#define STACK_OFFSET_S0 16 -#define STACK_OFFSET_S1 24 -#define STACK_OFFSET_S2 32 -#define STACK_OFFSET_S3 40 -#define STACK_OFFSET_S4 48 -#define STACK_OFFSET_S5 56 -#define STACK_OFFSET_S6 64 -#define STACK_SIZE 80 /* needs 16 byte alignment */ - -/* Constants for float/double_to_int/long conversions */ -#define INT_MIN 0x80000000 -#define INT_MIN_AS_FLOAT 0xCF000000 -#define INT_MIN_AS_DOUBLE 0xC1E0000000000000 -#define LONG_MIN 0x8000000000000000 -#define LONG_MIN_AS_FLOAT 0xDF000000 -#define LONG_MIN_AS_DOUBLE 0xC3E0000000000000 - -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * Interpreter entry point. - */ - - .set reorder - - .text - .global ExecuteMterpImpl - .type ExecuteMterpImpl, %function - .balign 16 -/* - * On entry: - * a0 Thread* self - * a1 dex_instructions - * a2 ShadowFrame - * a3 JValue* result_register - * - */ -ExecuteMterpImpl: - .cfi_startproc - .cpsetup t9, t8, ExecuteMterpImpl - - .cfi_def_cfa sp, 0 - daddu sp, sp, -STACK_SIZE - .cfi_adjust_cfa_offset STACK_SIZE - - sd t8, STACK_OFFSET_GP(sp) - .cfi_rel_offset 28, STACK_OFFSET_GP - sd ra, STACK_OFFSET_RA(sp) - .cfi_rel_offset 31, STACK_OFFSET_RA - - sd s0, STACK_OFFSET_S0(sp) - .cfi_rel_offset 16, STACK_OFFSET_S0 - sd s1, STACK_OFFSET_S1(sp) - .cfi_rel_offset 17, STACK_OFFSET_S1 - sd s2, STACK_OFFSET_S2(sp) - .cfi_rel_offset 18, STACK_OFFSET_S2 - sd s3, STACK_OFFSET_S3(sp) - .cfi_rel_offset 19, STACK_OFFSET_S3 - sd s4, STACK_OFFSET_S4(sp) - .cfi_rel_offset 20, STACK_OFFSET_S4 - sd s5, STACK_OFFSET_S5(sp) - .cfi_rel_offset 21, STACK_OFFSET_S5 - sd s6, STACK_OFFSET_S6(sp) - .cfi_rel_offset 22, STACK_OFFSET_S6 - - /* Remember the return register */ - sd a3, SHADOWFRAME_RESULT_REGISTER_OFFSET(a2) - - /* Remember the dex instruction pointer */ - sd a1, SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET(a2) - - /* set up "named" registers */ - move rSELF, a0 - daddu rFP, a2, SHADOWFRAME_VREGS_OFFSET - lw v0, SHADOWFRAME_NUMBER_OF_VREGS_OFFSET(a2) - dlsa rREFS, v0, rFP, 2 - lw v0, SHADOWFRAME_DEX_PC_OFFSET(a2) - dlsa rPC, v0, a1, 1 - CFI_DEFINE_DEX_PC_WITH_OFFSET(CFI_TMP, CFI_DEX, 0) - EXPORT_PC - - /* Starting ibase */ - REFRESH_IBASE - - /* Set up for backwards branches & osr profiling */ - ld a0, OFF_FP_METHOD(rFP) - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rSELF - jal MterpSetUpHotnessCountdown - move rPROFILE, v0 # Starting hotness countdown to rPROFILE - - /* start executing the instruction at rPC */ - FETCH_INST - GET_INST_OPCODE v0 - GOTO_OPCODE v0 - - /* NOTE: no fallthrough */ - - .global artMterpAsmInstructionStart -artMterpAsmInstructionStart = .L_op_nop - .text - -/* ------------------------------ */ - .balign 128 -.L_op_nop: /* 0x00 */ - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move: /* 0x01 */ - /* for move, move-object, long-to-int */ - /* op vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_VREG a0, a3 # a0 <- vB - GET_INST_OPCODE v0 # extract opcode from rINST - .if 0 - SET_VREG_OBJECT a0, a2 # vA <- vB - .else - SET_VREG a0, a2 # vA <- vB - .endif - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_from16: /* 0x02 */ - /* for: move/from16, move-object/from16 */ - /* op vAA, vBBBB */ - lhu a3, 2(rPC) # a3 <- BBBB - srl a2, rINST, 8 # a2 <- AA - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_VREG a0, a3 # a0 <- vBBBB - GET_INST_OPCODE v0 # extract opcode from rINST - .if 0 - SET_VREG_OBJECT a0, a2 # vAA <- vBBBB - .else - SET_VREG a0, a2 # vAA <- vBBBB - .endif - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_16: /* 0x03 */ - /* for: move/16, move-object/16 */ - /* op vAAAA, vBBBB */ - lhu a3, 4(rPC) # a3 <- BBBB - lhu a2, 2(rPC) # a2 <- AAAA - FETCH_ADVANCE_INST 3 # advance rPC, load rINST - GET_VREG a0, a3 # a0 <- vBBBB - GET_INST_OPCODE v0 # extract opcode from rINST - .if 0 - SET_VREG_OBJECT a0, a2 # vAAAA <- vBBBB - .else - SET_VREG a0, a2 # vAAAA <- vBBBB - .endif - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_wide: /* 0x04 */ - /* move-wide vA, vB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - ext a3, rINST, 12, 4 # a3 <- B - ext a2, rINST, 8, 4 # a2 <- A - GET_VREG_WIDE a0, a3 # a0 <- vB - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vA <- vB - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_wide_from16: /* 0x05 */ - /* move-wide/from16 vAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - lhu a3, 2(rPC) # a3 <- BBBB - srl a2, rINST, 8 # a2 <- AA - GET_VREG_WIDE a0, a3 # a0 <- vBBBB - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vAA <- vBBBB - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_wide_16: /* 0x06 */ - /* move-wide/16 vAAAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - lhu a3, 4(rPC) # a3 <- BBBB - lhu a2, 2(rPC) # a2 <- AAAA - GET_VREG_WIDE a0, a3 # a0 <- vBBBB - FETCH_ADVANCE_INST 3 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vAAAA <- vBBBB - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_object: /* 0x07 */ - /* for move, move-object, long-to-int */ - /* op vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_VREG a0, a3 # a0 <- vB - GET_INST_OPCODE v0 # extract opcode from rINST - .if 1 - SET_VREG_OBJECT a0, a2 # vA <- vB - .else - SET_VREG a0, a2 # vA <- vB - .endif - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_object_from16: /* 0x08 */ - /* for: move/from16, move-object/from16 */ - /* op vAA, vBBBB */ - lhu a3, 2(rPC) # a3 <- BBBB - srl a2, rINST, 8 # a2 <- AA - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_VREG a0, a3 # a0 <- vBBBB - GET_INST_OPCODE v0 # extract opcode from rINST - .if 1 - SET_VREG_OBJECT a0, a2 # vAA <- vBBBB - .else - SET_VREG a0, a2 # vAA <- vBBBB - .endif - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_object_16: /* 0x09 */ - /* for: move/16, move-object/16 */ - /* op vAAAA, vBBBB */ - lhu a3, 4(rPC) # a3 <- BBBB - lhu a2, 2(rPC) # a2 <- AAAA - FETCH_ADVANCE_INST 3 # advance rPC, load rINST - GET_VREG a0, a3 # a0 <- vBBBB - GET_INST_OPCODE v0 # extract opcode from rINST - .if 1 - SET_VREG_OBJECT a0, a2 # vAAAA <- vBBBB - .else - SET_VREG a0, a2 # vAAAA <- vBBBB - .endif - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_result: /* 0x0a */ - /* for: move-result, move-result-object */ - /* op vAA */ - srl a2, rINST, 8 # a2 <- AA - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - ld a0, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType - lw a0, 0(a0) # a0 <- result.i - GET_INST_OPCODE v0 # extract opcode from rINST - .if 0 - SET_VREG_OBJECT a0, a2 # vAA <- result - .else - SET_VREG a0, a2 # vAA <- result - .endif - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_result_wide: /* 0x0b */ - /* for: move-result-wide */ - /* op vAA */ - srl a2, rINST, 8 # a2 <- AA - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - ld a0, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType - ld a0, 0(a0) # a0 <- result.j - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vAA <- result - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_result_object: /* 0x0c */ - /* for: move-result, move-result-object */ - /* op vAA */ - srl a2, rINST, 8 # a2 <- AA - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - ld a0, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType - lw a0, 0(a0) # a0 <- result.i - GET_INST_OPCODE v0 # extract opcode from rINST - .if 1 - SET_VREG_OBJECT a0, a2 # vAA <- result - .else - SET_VREG a0, a2 # vAA <- result - .endif - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_exception: /* 0x0d */ - /* move-exception vAA */ - srl a2, rINST, 8 # a2 <- AA - ld a0, THREAD_EXCEPTION_OFFSET(rSELF) # load exception obj - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - SET_VREG_OBJECT a0, a2 # vAA <- exception obj - GET_INST_OPCODE v0 # extract opcode from rINST - sd zero, THREAD_EXCEPTION_OFFSET(rSELF) # clear exception - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_return_void: /* 0x0e */ - .extern MterpThreadFenceForConstructor - .extern MterpSuspendCheck - jal MterpThreadFenceForConstructor - lw ra, THREAD_FLAGS_OFFSET(rSELF) - move a0, rSELF - and ra, ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - beqzc ra, 1f - jal MterpSuspendCheck # (self) -1: - li a0, 0 - b MterpReturn - -/* ------------------------------ */ - .balign 128 -.L_op_return: /* 0x0f */ - /* - * Return a 32-bit value. - * - * for: return (sign-extend), return-object (zero-extend) - */ - /* op vAA */ - .extern MterpThreadFenceForConstructor - .extern MterpSuspendCheck - jal MterpThreadFenceForConstructor - lw ra, THREAD_FLAGS_OFFSET(rSELF) - move a0, rSELF - and ra, ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - beqzc ra, 1f - jal MterpSuspendCheck # (self) -1: - srl a2, rINST, 8 # a2 <- AA - GET_VREG a0, a2 # a0 <- vAA - b MterpReturn - -/* ------------------------------ */ - .balign 128 -.L_op_return_wide: /* 0x10 */ - /* - * Return a 64-bit value. - */ - /* return-wide vAA */ - /* op vAA */ - .extern MterpThreadFenceForConstructor - .extern MterpSuspendCheck - jal MterpThreadFenceForConstructor - lw ra, THREAD_FLAGS_OFFSET(rSELF) - move a0, rSELF - and ra, ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - beqzc ra, 1f - jal MterpSuspendCheck # (self) -1: - srl a2, rINST, 8 # a2 <- AA - GET_VREG_WIDE a0, a2 # a0 <- vAA - b MterpReturn - -/* ------------------------------ */ - .balign 128 -.L_op_return_object: /* 0x11 */ - /* - * Return a 32-bit value. - * - * for: return (sign-extend), return-object (zero-extend) - */ - /* op vAA */ - .extern MterpThreadFenceForConstructor - .extern MterpSuspendCheck - jal MterpThreadFenceForConstructor - lw ra, THREAD_FLAGS_OFFSET(rSELF) - move a0, rSELF - and ra, ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - beqzc ra, 1f - jal MterpSuspendCheck # (self) -1: - srl a2, rINST, 8 # a2 <- AA - GET_VREG_U a0, a2 # a0 <- vAA - b MterpReturn - -/* ------------------------------ */ - .balign 128 -.L_op_const_4: /* 0x12 */ - /* const/4 vA, #+B */ - ext a2, rINST, 8, 4 # a2 <- A - seh a0, rINST # sign extend B in rINST - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - sra a0, a0, 12 # shift B into its final position - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- +B - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_16: /* 0x13 */ - /* const/16 vAA, #+BBBB */ - srl a2, rINST, 8 # a2 <- AA - lh a0, 2(rPC) # a0 <- sign-extended BBBB - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vAA <- +BBBB - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const: /* 0x14 */ - /* const vAA, #+BBBBbbbb */ - srl a2, rINST, 8 # a2 <- AA - lh a0, 2(rPC) # a0 <- bbbb (low) - lh a1, 4(rPC) # a1 <- BBBB (high) - FETCH_ADVANCE_INST 3 # advance rPC, load rINST - ins a0, a1, 16, 16 # a0 = BBBBbbbb - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vAA <- +BBBBbbbb - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_high16: /* 0x15 */ - /* const/high16 vAA, #+BBBB0000 */ - srl a2, rINST, 8 # a2 <- AA - lh a0, 2(rPC) # a0 <- BBBB - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - sll a0, a0, 16 # a0 <- BBBB0000 - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vAA <- +BBBB0000 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_wide_16: /* 0x16 */ - /* const-wide/16 vAA, #+BBBB */ - srl a2, rINST, 8 # a2 <- AA - lh a0, 2(rPC) # a0 <- sign-extended BBBB - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vAA <- +BBBB - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_wide_32: /* 0x17 */ - /* const-wide/32 vAA, #+BBBBbbbb */ - srl a2, rINST, 8 # a2 <- AA - lh a0, 2(rPC) # a0 <- bbbb (low) - lh a1, 4(rPC) # a1 <- BBBB (high) - FETCH_ADVANCE_INST 3 # advance rPC, load rINST - ins a0, a1, 16, 16 # a0 = BBBBbbbb - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vAA <- +BBBBbbbb - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_wide: /* 0x18 */ - /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ - srl a4, rINST, 8 # a4 <- AA - lh a0, 2(rPC) # a0 <- bbbb (low) - lh a1, 4(rPC) # a1 <- BBBB (low middle) - lh a2, 6(rPC) # a2 <- hhhh (high middle) - lh a3, 8(rPC) # a3 <- HHHH (high) - FETCH_ADVANCE_INST 5 # advance rPC, load rINST - ins a0, a1, 16, 16 # a0 = BBBBbbbb - ins a2, a3, 16, 16 # a2 = HHHHhhhh - dinsu a0, a2, 32, 32 # a0 = HHHHhhhhBBBBbbbb - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a4 # vAA <- +HHHHhhhhBBBBbbbb - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_wide_high16: /* 0x19 */ - /* const-wide/high16 vAA, #+BBBB000000000000 */ - srl a2, rINST, 8 # a2 <- AA - lh a0, 2(rPC) # a0 <- BBBB - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - dsll32 a0, a0, 16 # a0 <- BBBB000000000000 - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vAA <- +BBBB000000000000 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_string: /* 0x1a */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstString - EXPORT_PC - lhu a0, 2(rPC) # a0 <- BBBB - srl a1, rINST, 8 # a1 <- AA - daddu a2, rFP, OFF_FP_SHADOWFRAME - move a3, rSELF - jal MterpConstString # (index, tgt_reg, shadow_frame, self) - PREFETCH_INST 2 # load rINST - bnez v0, MterpPossibleException # let reference interpreter deal with it. - ADVANCE 2 # advance rPC - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_string_jumbo: /* 0x1b */ - /* const/string vAA, String//BBBBBBBB */ - .extern MterpConstString - EXPORT_PC - lh a0, 2(rPC) # a0 <- bbbb (low) - lh a4, 4(rPC) # a4 <- BBBB (high) - srl a1, rINST, 8 # a1 <- AA - ins a0, a4, 16, 16 # a0 <- BBBBbbbb - daddu a2, rFP, OFF_FP_SHADOWFRAME - move a3, rSELF - jal MterpConstString # (index, tgt_reg, shadow_frame, self) - PREFETCH_INST 3 # load rINST - bnez v0, MterpPossibleException # let reference interpreter deal with it. - ADVANCE 3 # advance rPC - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_class: /* 0x1c */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstClass - EXPORT_PC - lhu a0, 2(rPC) # a0 <- BBBB - srl a1, rINST, 8 # a1 <- AA - daddu a2, rFP, OFF_FP_SHADOWFRAME - move a3, rSELF - jal MterpConstClass # (index, tgt_reg, shadow_frame, self) - PREFETCH_INST 2 # load rINST - bnez v0, MterpPossibleException # let reference interpreter deal with it. - ADVANCE 2 # advance rPC - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_monitor_enter: /* 0x1d */ - /* - * Synchronize on an object. - */ - /* monitor-enter vAA */ - .extern artLockObjectFromCode - EXPORT_PC - srl a2, rINST, 8 # a2 <- AA - GET_VREG_U a0, a2 # a0 <- vAA (object) - move a1, rSELF # a1 <- self - jal artLockObjectFromCode - bnezc v0, MterpException - FETCH_ADVANCE_INST 1 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_monitor_exit: /* 0x1e */ - /* - * Unlock an object. - * - * Exceptions that occur when unlocking a monitor need to appear as - * if they happened at the following instruction. See the Dalvik - * instruction spec. - */ - /* monitor-exit vAA */ - .extern artUnlockObjectFromCode - EXPORT_PC - srl a2, rINST, 8 # a2 <- AA - GET_VREG_U a0, a2 # a0 <- vAA (object) - move a1, rSELF # a1 <- self - jal artUnlockObjectFromCode # v0 <- success for unlock(self, obj) - bnezc v0, MterpException - FETCH_ADVANCE_INST 1 # before throw: advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_check_cast: /* 0x1f */ - /* - * Check to see if a cast from one class to another is allowed. - */ - /* check-cast vAA, class//BBBB */ - .extern MterpCheckCast - EXPORT_PC - lhu a0, 2(rPC) # a0 <- BBBB - srl a1, rINST, 8 # a1 <- AA - dlsa a1, a1, rFP, 2 # a1 <- &object - ld a2, OFF_FP_METHOD(rFP) # a2 <- method - move a3, rSELF # a3 <- self - jal MterpCheckCast # (index, &obj, method, self) - PREFETCH_INST 2 - bnez v0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_instance_of: /* 0x20 */ - /* - * Check to see if an object reference is an instance of a class. - * - * Most common situation is a non-null object, being compared against - * an already-resolved class. - */ - /* instance-of vA, vB, class//CCCC */ - .extern MterpInstanceOf - EXPORT_PC - lhu a0, 2(rPC) # a0 <- CCCC - srl a1, rINST, 12 # a1 <- B - dlsa a1, a1, rFP, 2 # a1 <- &object - ld a2, OFF_FP_METHOD(rFP) # a2 <- method - move a3, rSELF # a3 <- self - jal MterpInstanceOf # (index, &obj, method, self) - ld a1, THREAD_EXCEPTION_OFFSET(rSELF) - ext a2, rINST, 8, 4 # a2 <- A - PREFETCH_INST 2 - bnez a1, MterpException - ADVANCE 2 # advance rPC - SET_VREG v0, a2 # vA <- v0 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_array_length: /* 0x21 */ - /* - * Return the length of an array. - */ - srl a1, rINST, 12 # a1 <- B - GET_VREG_U a0, a1 # a0 <- vB (object ref) - ext a2, rINST, 8, 4 # a2 <- A - beqz a0, common_errNullObject # yup, fail - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- array length - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a3, a2 # vB <- length - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_new_instance: /* 0x22 */ - /* - * Create a new instance of a class. - */ - /* new-instance vAA, class//BBBB */ - .extern MterpNewInstance - EXPORT_PC - daddu a0, rFP, OFF_FP_SHADOWFRAME - move a1, rSELF - move a2, rINST - jal MterpNewInstance # (shadow_frame, self, inst_data) - beqzc v0, MterpPossibleException - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_new_array: /* 0x23 */ - /* - * Allocate an array of objects, specified with the array class - * and a count. - * - * The verifier guarantees that this is an array class, so we don't - * check for it here. - */ - /* new-array vA, vB, class//CCCC */ - .extern MterpNewArray - EXPORT_PC - daddu a0, rFP, OFF_FP_SHADOWFRAME - move a1, rPC - move a2, rINST - move a3, rSELF - jal MterpNewArray - beqzc v0, MterpPossibleException - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_filled_new_array: /* 0x24 */ - /* - * Create a new array with elements filled from registers. - * - * for: filled-new-array, filled-new-array/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class//CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, type//BBBB */ - .extern MterpFilledNewArray - EXPORT_PC - daddu a0, rFP, OFF_FP_SHADOWFRAME - move a1, rPC - move a2, rSELF - jal MterpFilledNewArray - beqzc v0, MterpPossibleException - FETCH_ADVANCE_INST 3 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_filled_new_array_range: /* 0x25 */ - /* - * Create a new array with elements filled from registers. - * - * for: filled-new-array, filled-new-array/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class//CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, type//BBBB */ - .extern MterpFilledNewArrayRange - EXPORT_PC - daddu a0, rFP, OFF_FP_SHADOWFRAME - move a1, rPC - move a2, rSELF - jal MterpFilledNewArrayRange - beqzc v0, MterpPossibleException - FETCH_ADVANCE_INST 3 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_fill_array_data: /* 0x26 */ - /* fill-array-data vAA, +BBBBBBBB */ - .extern MterpFillArrayData - EXPORT_PC - lh a1, 2(rPC) # a1 <- bbbb (lo) - lh a0, 4(rPC) # a0 <- BBBB (hi) - srl a3, rINST, 8 # a3 <- AA - ins a1, a0, 16, 16 # a1 <- BBBBbbbb - GET_VREG_U a0, a3 # a0 <- vAA (array object) - dlsa a1, a1, rPC, 1 # a1 <- PC + BBBBbbbb*2 (array data off.) - jal MterpFillArrayData # (obj, payload) - beqzc v0, MterpPossibleException # exception? - FETCH_ADVANCE_INST 3 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_throw: /* 0x27 */ - /* - * Throw an exception object in the current thread. - */ - /* throw vAA */ - EXPORT_PC - srl a2, rINST, 8 # a2 <- AA - GET_VREG_U a0, a2 # a0 <- vAA (exception object) - beqzc a0, common_errNullObject - sd a0, THREAD_EXCEPTION_OFFSET(rSELF) # thread->exception <- obj - b MterpException - -/* ------------------------------ */ - .balign 128 -.L_op_goto: /* 0x28 */ - /* - * Unconditional branch, 8-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto +AA */ - srl rINST, rINST, 8 - seb rINST, rINST # rINST <- offset (sign-extended AA) - b MterpCommonTakenBranchNoFlags - -/* ------------------------------ */ - .balign 128 -.L_op_goto_16: /* 0x29 */ - /* - * Unconditional branch, 16-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto/16 +AAAA */ - lh rINST, 2(rPC) # rINST <- offset (sign-extended AAAA) - b MterpCommonTakenBranchNoFlags - -/* ------------------------------ */ - .balign 128 -.L_op_goto_32: /* 0x2a */ - /* - * Unconditional branch, 32-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - * - * Unlike most opcodes, this one is allowed to branch to itself, so - * our "backward branch" test must be "<=0" instead of "<0". - */ - /* goto/32 +AAAAAAAA */ - lh rINST, 2(rPC) # rINST <- aaaa (low) - lh a1, 4(rPC) # a1 <- AAAA (high) - ins rINST, a1, 16, 16 # rINST <- offset (sign-extended AAAAaaaa) - b MterpCommonTakenBranchNoFlags - -/* ------------------------------ */ - .balign 128 -.L_op_packed_switch: /* 0x2b */ - /* - * Handle a packed-switch or sparse-switch instruction. In both cases - * we decode it and hand it off to a helper function. - * - * We don't really expect backward branches in a switch statement, but - * they're perfectly legal, so we check for them here. - * - * for: packed-switch, sparse-switch - */ - /* op vAA, +BBBBBBBB */ - .extern MterpDoPackedSwitch - lh a0, 2(rPC) # a0 <- bbbb (lo) - lh a1, 4(rPC) # a1 <- BBBB (hi) - srl a3, rINST, 8 # a3 <- AA - ins a0, a1, 16, 16 # a0 <- BBBBbbbb - GET_VREG a1, a3 # a1 <- vAA - dlsa a0, a0, rPC, 1 # a0 <- PC + BBBBbbbb*2 - jal MterpDoPackedSwitch # v0 <- code-unit branch offset - move rINST, v0 - b MterpCommonTakenBranchNoFlags - -/* ------------------------------ */ - .balign 128 -.L_op_sparse_switch: /* 0x2c */ - /* - * Handle a packed-switch or sparse-switch instruction. In both cases - * we decode it and hand it off to a helper function. - * - * We don't really expect backward branches in a switch statement, but - * they're perfectly legal, so we check for them here. - * - * for: packed-switch, sparse-switch - */ - /* op vAA, +BBBBBBBB */ - .extern MterpDoSparseSwitch - lh a0, 2(rPC) # a0 <- bbbb (lo) - lh a1, 4(rPC) # a1 <- BBBB (hi) - srl a3, rINST, 8 # a3 <- AA - ins a0, a1, 16, 16 # a0 <- BBBBbbbb - GET_VREG a1, a3 # a1 <- vAA - dlsa a0, a0, rPC, 1 # a0 <- PC + BBBBbbbb*2 - jal MterpDoSparseSwitch # v0 <- code-unit branch offset - move rINST, v0 - b MterpCommonTakenBranchNoFlags - -/* ------------------------------ */ - .balign 128 -.L_op_cmpl_float: /* 0x2d */ - /* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * For: cmpl-float, cmpg-float - */ - /* op vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_FLOAT f0, a2 # f0 <- vBB - GET_VREG_FLOAT f1, a3 # f1 <- vCC - cmp.eq.s f2, f0, f1 - li a0, 0 - bc1nez f2, 1f # done if vBB == vCC (ordered) - .if 0 - cmp.lt.s f2, f0, f1 - li a0, -1 - bc1nez f2, 1f # done if vBB < vCC (ordered) - li a0, 1 # vBB > vCC or unordered - .else - cmp.lt.s f2, f1, f0 - li a0, 1 - bc1nez f2, 1f # done if vBB > vCC (ordered) - li a0, -1 # vBB < vCC or unordered - .endif -1: - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_cmpg_float: /* 0x2e */ - /* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * For: cmpl-float, cmpg-float - */ - /* op vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_FLOAT f0, a2 # f0 <- vBB - GET_VREG_FLOAT f1, a3 # f1 <- vCC - cmp.eq.s f2, f0, f1 - li a0, 0 - bc1nez f2, 1f # done if vBB == vCC (ordered) - .if 1 - cmp.lt.s f2, f0, f1 - li a0, -1 - bc1nez f2, 1f # done if vBB < vCC (ordered) - li a0, 1 # vBB > vCC or unordered - .else - cmp.lt.s f2, f1, f0 - li a0, 1 - bc1nez f2, 1f # done if vBB > vCC (ordered) - li a0, -1 # vBB < vCC or unordered - .endif -1: - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_cmpl_double: /* 0x2f */ - /* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * For: cmpl-double, cmpg-double - */ - /* op vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_DOUBLE f0, a2 # f0 <- vBB - GET_VREG_DOUBLE f1, a3 # f1 <- vCC - cmp.eq.d f2, f0, f1 - li a0, 0 - bc1nez f2, 1f # done if vBB == vCC (ordered) - .if 0 - cmp.lt.d f2, f0, f1 - li a0, -1 - bc1nez f2, 1f # done if vBB < vCC (ordered) - li a0, 1 # vBB > vCC or unordered - .else - cmp.lt.d f2, f1, f0 - li a0, 1 - bc1nez f2, 1f # done if vBB > vCC (ordered) - li a0, -1 # vBB < vCC or unordered - .endif -1: - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_cmpg_double: /* 0x30 */ - /* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * For: cmpl-double, cmpg-double - */ - /* op vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_DOUBLE f0, a2 # f0 <- vBB - GET_VREG_DOUBLE f1, a3 # f1 <- vCC - cmp.eq.d f2, f0, f1 - li a0, 0 - bc1nez f2, 1f # done if vBB == vCC (ordered) - .if 1 - cmp.lt.d f2, f0, f1 - li a0, -1 - bc1nez f2, 1f # done if vBB < vCC (ordered) - li a0, 1 # vBB > vCC or unordered - .else - cmp.lt.d f2, f1, f0 - li a0, 1 - bc1nez f2, 1f # done if vBB > vCC (ordered) - li a0, -1 # vBB < vCC or unordered - .endif -1: - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_cmp_long: /* 0x31 */ - /* cmp-long vAA, vBB, vCC */ - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - srl a4, rINST, 8 # a4 <- AA - GET_VREG_WIDE a0, a2 # a0 <- vBB - GET_VREG_WIDE a1, a3 # a1 <- vCC - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - slt a2, a0, a1 - slt a0, a1, a0 - subu a0, a0, a2 - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a4 # vAA <- result - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_eq: /* 0x32 */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform, e.g. for - * "if-le" you would use "le". - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - lh rINST, 2(rPC) # rINST <- offset (sign-extended CCCC) - GET_VREG a0, a2 # a0 <- vA - GET_VREG a1, a3 # a1 <- vB - beqc a0, a1, MterpCommonTakenBranchNoFlags - li v0, JIT_CHECK_OSR # possible OSR re-entry? - beqc rPROFILE, v0, .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_ne: /* 0x33 */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform, e.g. for - * "if-le" you would use "le". - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - lh rINST, 2(rPC) # rINST <- offset (sign-extended CCCC) - GET_VREG a0, a2 # a0 <- vA - GET_VREG a1, a3 # a1 <- vB - bnec a0, a1, MterpCommonTakenBranchNoFlags - li v0, JIT_CHECK_OSR # possible OSR re-entry? - beqc rPROFILE, v0, .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_lt: /* 0x34 */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform, e.g. for - * "if-le" you would use "le". - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - lh rINST, 2(rPC) # rINST <- offset (sign-extended CCCC) - GET_VREG a0, a2 # a0 <- vA - GET_VREG a1, a3 # a1 <- vB - bltc a0, a1, MterpCommonTakenBranchNoFlags - li v0, JIT_CHECK_OSR # possible OSR re-entry? - beqc rPROFILE, v0, .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_ge: /* 0x35 */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform, e.g. for - * "if-le" you would use "le". - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - lh rINST, 2(rPC) # rINST <- offset (sign-extended CCCC) - GET_VREG a0, a2 # a0 <- vA - GET_VREG a1, a3 # a1 <- vB - bgec a0, a1, MterpCommonTakenBranchNoFlags - li v0, JIT_CHECK_OSR # possible OSR re-entry? - beqc rPROFILE, v0, .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_gt: /* 0x36 */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform, e.g. for - * "if-le" you would use "le". - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - lh rINST, 2(rPC) # rINST <- offset (sign-extended CCCC) - GET_VREG a0, a2 # a0 <- vA - GET_VREG a1, a3 # a1 <- vB - bgtc a0, a1, MterpCommonTakenBranchNoFlags - li v0, JIT_CHECK_OSR # possible OSR re-entry? - beqc rPROFILE, v0, .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_le: /* 0x37 */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform, e.g. for - * "if-le" you would use "le". - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - lh rINST, 2(rPC) # rINST <- offset (sign-extended CCCC) - GET_VREG a0, a2 # a0 <- vA - GET_VREG a1, a3 # a1 <- vB - blec a0, a1, MterpCommonTakenBranchNoFlags - li v0, JIT_CHECK_OSR # possible OSR re-entry? - beqc rPROFILE, v0, .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_eqz: /* 0x38 */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform, e.g. for - * "if-lez" you would use "le". - * - * For: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - srl a2, rINST, 8 # a2 <- AA - lh rINST, 2(rPC) # rINST <- offset (sign-extended BBBB) - GET_VREG a0, a2 # a0 <- vAA - beqzc a0, MterpCommonTakenBranchNoFlags - li v0, JIT_CHECK_OSR # possible OSR re-entry? - beqc rPROFILE, v0, .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_nez: /* 0x39 */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform, e.g. for - * "if-lez" you would use "le". - * - * For: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - srl a2, rINST, 8 # a2 <- AA - lh rINST, 2(rPC) # rINST <- offset (sign-extended BBBB) - GET_VREG a0, a2 # a0 <- vAA - bnezc a0, MterpCommonTakenBranchNoFlags - li v0, JIT_CHECK_OSR # possible OSR re-entry? - beqc rPROFILE, v0, .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_ltz: /* 0x3a */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform, e.g. for - * "if-lez" you would use "le". - * - * For: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - srl a2, rINST, 8 # a2 <- AA - lh rINST, 2(rPC) # rINST <- offset (sign-extended BBBB) - GET_VREG a0, a2 # a0 <- vAA - bltzc a0, MterpCommonTakenBranchNoFlags - li v0, JIT_CHECK_OSR # possible OSR re-entry? - beqc rPROFILE, v0, .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_gez: /* 0x3b */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform, e.g. for - * "if-lez" you would use "le". - * - * For: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - srl a2, rINST, 8 # a2 <- AA - lh rINST, 2(rPC) # rINST <- offset (sign-extended BBBB) - GET_VREG a0, a2 # a0 <- vAA - bgezc a0, MterpCommonTakenBranchNoFlags - li v0, JIT_CHECK_OSR # possible OSR re-entry? - beqc rPROFILE, v0, .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_gtz: /* 0x3c */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform, e.g. for - * "if-lez" you would use "le". - * - * For: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - srl a2, rINST, 8 # a2 <- AA - lh rINST, 2(rPC) # rINST <- offset (sign-extended BBBB) - GET_VREG a0, a2 # a0 <- vAA - bgtzc a0, MterpCommonTakenBranchNoFlags - li v0, JIT_CHECK_OSR # possible OSR re-entry? - beqc rPROFILE, v0, .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_lez: /* 0x3d */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform, e.g. for - * "if-lez" you would use "le". - * - * For: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - srl a2, rINST, 8 # a2 <- AA - lh rINST, 2(rPC) # rINST <- offset (sign-extended BBBB) - GET_VREG a0, a2 # a0 <- vAA - blezc a0, MterpCommonTakenBranchNoFlags - li v0, JIT_CHECK_OSR # possible OSR re-entry? - beqc rPROFILE, v0, .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_unused_3e: /* 0x3e */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_3f: /* 0x3f */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_40: /* 0x40 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_41: /* 0x41 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_42: /* 0x42 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_43: /* 0x43 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_aget: /* 0x44 */ - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - srl a4, rINST, 8 # a4 <- AA - GET_VREG_U a0, a2 # a0 <- vBB (array object) - GET_VREG a1, a3 # a1 <- vCC (requested index) - beqz a0, common_errNullObject # bail if null array object - lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length - .if 2 - # [d]lsa does not support shift count of 0. - dlsa a0, a1, a0, 2 # a0 <- arrayObj + index*width - .else - daddu a0, a1, a0 # a0 <- arrayObj + index*width - .endif - bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - lw a2, MIRROR_INT_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a2, a4 # vAA <- a2 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aget_wide: /* 0x45 */ - /* - * Array get, 64 bits. vAA <- vBB[vCC]. - * - */ - /* aget-wide vAA, vBB, vCC */ - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - srl a4, rINST, 8 # a4 <- AA - GET_VREG_U a0, a2 # a0 <- vBB (array object) - GET_VREG a1, a3 # a1 <- vCC (requested index) - beqz a0, common_errNullObject # bail if null array object - lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length - dlsa a0, a1, a0, 3 # a0 <- arrayObj + index*width - bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - lw a2, MIRROR_WIDE_ARRAY_DATA_OFFSET(a0) - lw a3, (MIRROR_WIDE_ARRAY_DATA_OFFSET+4)(a0) - dinsu a2, a3, 32, 32 # a2 <- vBB[vCC] - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a2, a4 # vAA <- a2 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aget_object: /* 0x46 */ - /* - * Array object get. vAA <- vBB[vCC]. - * - * for: aget-object - */ - /* op vAA, vBB, vCC */ - .extern artAGetObjectFromMterp - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - EXPORT_PC - GET_VREG_U a0, a2 # a0 <- vBB (array object) - GET_VREG a1, a3 # a1 <- vCC (requested index) - jal artAGetObjectFromMterp # (array, index) - ld a1, THREAD_EXCEPTION_OFFSET(rSELF) - srl a4, rINST, 8 # a4 <- AA - PREFETCH_INST 2 - bnez a1, MterpException - SET_VREG_OBJECT v0, a4 # vAA <- v0 - ADVANCE 2 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aget_boolean: /* 0x47 */ - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - srl a4, rINST, 8 # a4 <- AA - GET_VREG_U a0, a2 # a0 <- vBB (array object) - GET_VREG a1, a3 # a1 <- vCC (requested index) - beqz a0, common_errNullObject # bail if null array object - lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length - .if 0 - # [d]lsa does not support shift count of 0. - dlsa a0, a1, a0, 0 # a0 <- arrayObj + index*width - .else - daddu a0, a1, a0 # a0 <- arrayObj + index*width - .endif - bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - lbu a2, MIRROR_BOOLEAN_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a2, a4 # vAA <- a2 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aget_byte: /* 0x48 */ - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - srl a4, rINST, 8 # a4 <- AA - GET_VREG_U a0, a2 # a0 <- vBB (array object) - GET_VREG a1, a3 # a1 <- vCC (requested index) - beqz a0, common_errNullObject # bail if null array object - lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length - .if 0 - # [d]lsa does not support shift count of 0. - dlsa a0, a1, a0, 0 # a0 <- arrayObj + index*width - .else - daddu a0, a1, a0 # a0 <- arrayObj + index*width - .endif - bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - lb a2, MIRROR_BYTE_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a2, a4 # vAA <- a2 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aget_char: /* 0x49 */ - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - srl a4, rINST, 8 # a4 <- AA - GET_VREG_U a0, a2 # a0 <- vBB (array object) - GET_VREG a1, a3 # a1 <- vCC (requested index) - beqz a0, common_errNullObject # bail if null array object - lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length - .if 1 - # [d]lsa does not support shift count of 0. - dlsa a0, a1, a0, 1 # a0 <- arrayObj + index*width - .else - daddu a0, a1, a0 # a0 <- arrayObj + index*width - .endif - bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - lhu a2, MIRROR_CHAR_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a2, a4 # vAA <- a2 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aget_short: /* 0x4a */ - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - srl a4, rINST, 8 # a4 <- AA - GET_VREG_U a0, a2 # a0 <- vBB (array object) - GET_VREG a1, a3 # a1 <- vCC (requested index) - beqz a0, common_errNullObject # bail if null array object - lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length - .if 1 - # [d]lsa does not support shift count of 0. - dlsa a0, a1, a0, 1 # a0 <- arrayObj + index*width - .else - daddu a0, a1, a0 # a0 <- arrayObj + index*width - .endif - bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - lh a2, MIRROR_SHORT_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a2, a4 # vAA <- a2 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aput: /* 0x4b */ - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - srl a4, rINST, 8 # a4 <- AA - GET_VREG_U a0, a2 # a0 <- vBB (array object) - GET_VREG a1, a3 # a1 <- vCC (requested index) - beqz a0, common_errNullObject # bail if null array object - lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length - .if 2 - # [d]lsa does not support shift count of 0. - dlsa a0, a1, a0, 2 # a0 <- arrayObj + index*width - .else - daddu a0, a1, a0 # a0 <- arrayObj + index*width - .endif - bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_VREG a2, a4 # a2 <- vAA - GET_INST_OPCODE v0 # extract opcode from rINST - sw a2, MIRROR_INT_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aput_wide: /* 0x4c */ - /* - * Array put, 64 bits. vBB[vCC] <- vAA. - * - */ - /* aput-wide vAA, vBB, vCC */ - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - srl a4, rINST, 8 # a4 <- AA - GET_VREG_U a0, a2 # a0 <- vBB (array object) - GET_VREG a1, a3 # a1 <- vCC (requested index) - beqz a0, common_errNullObject # bail if null array object - lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length - dlsa a0, a1, a0, 3 # a0 <- arrayObj + index*width - bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail - GET_VREG_WIDE a2, a4 # a2 <- vAA - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - sw a2, MIRROR_WIDE_ARRAY_DATA_OFFSET(a0) - dsrl32 a2, a2, 0 - sw a2, (MIRROR_WIDE_ARRAY_DATA_OFFSET+4)(a0) # vBB[vCC] <- a2 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aput_object: /* 0x4d */ - /* - * Store an object into an array. vBB[vCC] <- vAA. - */ - /* op vAA, vBB, vCC */ - .extern MterpAputObject - EXPORT_PC - daddu a0, rFP, OFF_FP_SHADOWFRAME - move a1, rPC - move a2, rINST - jal MterpAputObject - beqzc v0, MterpPossibleException - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aput_boolean: /* 0x4e */ - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - srl a4, rINST, 8 # a4 <- AA - GET_VREG_U a0, a2 # a0 <- vBB (array object) - GET_VREG a1, a3 # a1 <- vCC (requested index) - beqz a0, common_errNullObject # bail if null array object - lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length - .if 0 - # [d]lsa does not support shift count of 0. - dlsa a0, a1, a0, 0 # a0 <- arrayObj + index*width - .else - daddu a0, a1, a0 # a0 <- arrayObj + index*width - .endif - bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_VREG a2, a4 # a2 <- vAA - GET_INST_OPCODE v0 # extract opcode from rINST - sb a2, MIRROR_BOOLEAN_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aput_byte: /* 0x4f */ - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - srl a4, rINST, 8 # a4 <- AA - GET_VREG_U a0, a2 # a0 <- vBB (array object) - GET_VREG a1, a3 # a1 <- vCC (requested index) - beqz a0, common_errNullObject # bail if null array object - lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length - .if 0 - # [d]lsa does not support shift count of 0. - dlsa a0, a1, a0, 0 # a0 <- arrayObj + index*width - .else - daddu a0, a1, a0 # a0 <- arrayObj + index*width - .endif - bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_VREG a2, a4 # a2 <- vAA - GET_INST_OPCODE v0 # extract opcode from rINST - sb a2, MIRROR_BYTE_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aput_char: /* 0x50 */ - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - srl a4, rINST, 8 # a4 <- AA - GET_VREG_U a0, a2 # a0 <- vBB (array object) - GET_VREG a1, a3 # a1 <- vCC (requested index) - beqz a0, common_errNullObject # bail if null array object - lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length - .if 1 - # [d]lsa does not support shift count of 0. - dlsa a0, a1, a0, 1 # a0 <- arrayObj + index*width - .else - daddu a0, a1, a0 # a0 <- arrayObj + index*width - .endif - bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_VREG a2, a4 # a2 <- vAA - GET_INST_OPCODE v0 # extract opcode from rINST - sh a2, MIRROR_CHAR_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aput_short: /* 0x51 */ - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - srl a4, rINST, 8 # a4 <- AA - GET_VREG_U a0, a2 # a0 <- vBB (array object) - GET_VREG a1, a3 # a1 <- vCC (requested index) - beqz a0, common_errNullObject # bail if null array object - lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length - .if 1 - # [d]lsa does not support shift count of 0. - dlsa a0, a1, a0, 1 # a0 <- arrayObj + index*width - .else - daddu a0, a1, a0 # a0 <- arrayObj + index*width - .endif - bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_VREG a2, a4 # a2 <- vAA - GET_INST_OPCODE v0 # extract opcode from rINST - sh a2, MIRROR_SHORT_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iget: /* 0x52 */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_iget_wide: /* 0x53 */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_iget_object: /* 0x54 */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_iget_boolean: /* 0x55 */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_iget_byte: /* 0x56 */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_iget_char: /* 0x57 */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_iget_short: /* 0x58 */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_iput: /* 0x59 */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_iput_wide: /* 0x5a */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_iput_object: /* 0x5b */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_iput_boolean: /* 0x5c */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_iput_byte: /* 0x5d */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_iput_char: /* 0x5e */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_iput_short: /* 0x5f */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_sget: /* 0x60 */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_sget_wide: /* 0x61 */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_sget_object: /* 0x62 */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_sget_boolean: /* 0x63 */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_sget_byte: /* 0x64 */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_sget_char: /* 0x65 */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_sget_short: /* 0x66 */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_sput: /* 0x67 */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_sput_wide: /* 0x68 */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_sput_object: /* 0x69 */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_sput_boolean: /* 0x6a */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_sput_byte: /* 0x6b */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_sput_char: /* 0x6c */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_sput_short: /* 0x6d */ -TODO - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual: /* 0x6e */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtual - .extern MterpShouldSwitchInterpreters - EXPORT_PC - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - jal MterpInvokeVirtual - beqzc v0, MterpException - FETCH_ADVANCE_INST 3 - jal MterpShouldSwitchInterpreters - bnezc v0, MterpFallback - GET_INST_OPCODE v0 - GOTO_OPCODE v0 - - /* - * Handle a virtual method call. - * - * for: invoke-virtual, invoke-virtual/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_super: /* 0x6f */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeSuper - .extern MterpShouldSwitchInterpreters - EXPORT_PC - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - jal MterpInvokeSuper - beqzc v0, MterpException - FETCH_ADVANCE_INST 3 - jal MterpShouldSwitchInterpreters - bnezc v0, MterpFallback - GET_INST_OPCODE v0 - GOTO_OPCODE v0 - - /* - * Handle a "super" method call. - * - * for: invoke-super, invoke-super/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_direct: /* 0x70 */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeDirect - .extern MterpShouldSwitchInterpreters - EXPORT_PC - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - jal MterpInvokeDirect - beqzc v0, MterpException - FETCH_ADVANCE_INST 3 - jal MterpShouldSwitchInterpreters - bnezc v0, MterpFallback - GET_INST_OPCODE v0 - GOTO_OPCODE v0 - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_static: /* 0x71 */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeStatic - .extern MterpShouldSwitchInterpreters - EXPORT_PC - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - jal MterpInvokeStatic - beqzc v0, MterpException - FETCH_ADVANCE_INST 3 - jal MterpShouldSwitchInterpreters - bnezc v0, MterpFallback - GET_INST_OPCODE v0 - GOTO_OPCODE v0 - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_interface: /* 0x72 */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeInterface - .extern MterpShouldSwitchInterpreters - EXPORT_PC - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - jal MterpInvokeInterface - beqzc v0, MterpException - FETCH_ADVANCE_INST 3 - jal MterpShouldSwitchInterpreters - bnezc v0, MterpFallback - GET_INST_OPCODE v0 - GOTO_OPCODE v0 - - /* - * Handle an interface method call. - * - * for: invoke-interface, invoke-interface/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - -/* ------------------------------ */ - .balign 128 -.L_op_return_void_no_barrier: /* 0x73 */ - .extern MterpSuspendCheck - lw ra, THREAD_FLAGS_OFFSET(rSELF) - move a0, rSELF - and ra, ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - beqzc ra, 1f - jal MterpSuspendCheck # (self) -1: - li a0, 0 - b MterpReturn - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual_range: /* 0x74 */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtualRange - .extern MterpShouldSwitchInterpreters - EXPORT_PC - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - jal MterpInvokeVirtualRange - beqzc v0, MterpException - FETCH_ADVANCE_INST 3 - jal MterpShouldSwitchInterpreters - bnezc v0, MterpFallback - GET_INST_OPCODE v0 - GOTO_OPCODE v0 - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_super_range: /* 0x75 */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeSuperRange - .extern MterpShouldSwitchInterpreters - EXPORT_PC - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - jal MterpInvokeSuperRange - beqzc v0, MterpException - FETCH_ADVANCE_INST 3 - jal MterpShouldSwitchInterpreters - bnezc v0, MterpFallback - GET_INST_OPCODE v0 - GOTO_OPCODE v0 - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_direct_range: /* 0x76 */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeDirectRange - .extern MterpShouldSwitchInterpreters - EXPORT_PC - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - jal MterpInvokeDirectRange - beqzc v0, MterpException - FETCH_ADVANCE_INST 3 - jal MterpShouldSwitchInterpreters - bnezc v0, MterpFallback - GET_INST_OPCODE v0 - GOTO_OPCODE v0 - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_static_range: /* 0x77 */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeStaticRange - .extern MterpShouldSwitchInterpreters - EXPORT_PC - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - jal MterpInvokeStaticRange - beqzc v0, MterpException - FETCH_ADVANCE_INST 3 - jal MterpShouldSwitchInterpreters - bnezc v0, MterpFallback - GET_INST_OPCODE v0 - GOTO_OPCODE v0 - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_interface_range: /* 0x78 */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeInterfaceRange - .extern MterpShouldSwitchInterpreters - EXPORT_PC - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - jal MterpInvokeInterfaceRange - beqzc v0, MterpException - FETCH_ADVANCE_INST 3 - jal MterpShouldSwitchInterpreters - bnezc v0, MterpFallback - GET_INST_OPCODE v0 - GOTO_OPCODE v0 - -/* ------------------------------ */ - .balign 128 -.L_op_unused_79: /* 0x79 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_7a: /* 0x7a */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_neg_int: /* 0x7b */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "a0 = op a0". - * - * for: int-to-byte, int-to-char, int-to-short, - * not-int, neg-int - */ - /* unop vA, vB */ - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a3 # a0 <- vB - ext a2, rINST, 8, 4 # a2 <- A - # optional op - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - subu a0, zero, a0 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_not_int: /* 0x7c */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "a0 = op a0". - * - * for: int-to-byte, int-to-char, int-to-short, - * not-int, neg-int - */ - /* unop vA, vB */ - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a3 # a0 <- vB - ext a2, rINST, 8, 4 # a2 <- A - # optional op - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - nor a0, zero, a0 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_neg_long: /* 0x7d */ - /* - * Generic 64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "a0 = op a0". - * - * For: not-long, neg-long - */ - /* unop vA, vB */ - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_WIDE a0, a3 # a0 <- vB - ext a2, rINST, 8, 4 # a2 <- A - # optional op - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - dsubu a0, zero, a0 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_not_long: /* 0x7e */ - /* - * Generic 64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "a0 = op a0". - * - * For: not-long, neg-long - */ - /* unop vA, vB */ - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_WIDE a0, a3 # a0 <- vB - ext a2, rINST, 8, 4 # a2 <- A - # optional op - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - nor a0, zero, a0 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_neg_float: /* 0x7f */ - /* - * Loads a specified register from vB. Used primarily for conversions - * from or to a floating-point type. - * - * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to - * store the result in vA and jump to the next instruction. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - */ - ext a1, rINST, 8, 4 # a1 <- A - srl a2, rINST, 12 # a2 <- B - GET_VREG_FLOAT f0, a2 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - - neg.s f0, f0 - /* - * Stores a specified register containing the result of conversion - * from or to a floating-point type and jumps to the next instruction. - * - * Expects a1 to contain the destination Dalvik register number. - * a1 is set up by fcvtHeader.S. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - * - * Note that this file can't be included after a break in other files - * and in those files its contents appear as a copy. - * See: float-to-int, float-to-long, double-to-int, double-to-long. - */ - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_FLOAT f0, a1 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_neg_double: /* 0x80 */ - /* - * Loads a specified register from vB. Used primarily for conversions - * from or to a floating-point type. - * - * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to - * store the result in vA and jump to the next instruction. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - */ - ext a1, rINST, 8, 4 # a1 <- A - srl a2, rINST, 12 # a2 <- B - GET_VREG_DOUBLE f0, a2 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - - neg.d f0, f0 - /* - * Stores a specified register containing the result of conversion - * from or to a floating-point type and jumps to the next instruction. - * - * Expects a1 to contain the destination Dalvik register number. - * a1 is set up by fcvtHeader.S. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - * - * Note that this file can't be included after a break in other files - * and in those files its contents appear as a copy. - * See: float-to-int, float-to-long, double-to-int, double-to-long. - */ - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_DOUBLE f0, a1 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_long: /* 0x81 */ - /* int-to-long vA, vB */ - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a3 # a0 <- vB (sign-extended to 64 bits) - ext a2, rINST, 8, 4 # a2 <- A - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vA <- vB - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_float: /* 0x82 */ - /* - * Conversion from or to floating-point happens in a floating-point register. - * Therefore we load the input and store the output into or from a - * floating-point register irrespective of the type. - */ - /* - * Loads a specified register from vB. Used primarily for conversions - * from or to a floating-point type. - * - * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to - * store the result in vA and jump to the next instruction. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - */ - ext a1, rINST, 8, 4 # a1 <- A - srl a2, rINST, 12 # a2 <- B - GET_VREG_FLOAT f0, a2 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - - cvt.s.w f0, f0 - /* - * Stores a specified register containing the result of conversion - * from or to a floating-point type and jumps to the next instruction. - * - * Expects a1 to contain the destination Dalvik register number. - * a1 is set up by fcvtHeader.S. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - * - * Note that this file can't be included after a break in other files - * and in those files its contents appear as a copy. - * See: float-to-int, float-to-long, double-to-int, double-to-long. - */ - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_FLOAT f0, a1 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_double: /* 0x83 */ - /* - * Conversion from or to floating-point happens in a floating-point register. - * Therefore we load the input and store the output into or from a - * floating-point register irrespective of the type. - */ - /* - * Loads a specified register from vB. Used primarily for conversions - * from or to a floating-point type. - * - * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to - * store the result in vA and jump to the next instruction. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - */ - ext a1, rINST, 8, 4 # a1 <- A - srl a2, rINST, 12 # a2 <- B - GET_VREG_FLOAT f0, a2 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - - cvt.d.w f0, f0 - /* - * Stores a specified register containing the result of conversion - * from or to a floating-point type and jumps to the next instruction. - * - * Expects a1 to contain the destination Dalvik register number. - * a1 is set up by fcvtHeader.S. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - * - * Note that this file can't be included after a break in other files - * and in those files its contents appear as a copy. - * See: float-to-int, float-to-long, double-to-int, double-to-long. - */ - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_DOUBLE f0, a1 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_long_to_int: /* 0x84 */ -/* we ignore the high word, making this equivalent to a 32-bit reg move */ - /* for move, move-object, long-to-int */ - /* op vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_VREG a0, a3 # a0 <- vB - GET_INST_OPCODE v0 # extract opcode from rINST - .if 0 - SET_VREG_OBJECT a0, a2 # vA <- vB - .else - SET_VREG a0, a2 # vA <- vB - .endif - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_long_to_float: /* 0x85 */ - /* - * Conversion from or to floating-point happens in a floating-point register. - * Therefore we load the input and store the output into or from a - * floating-point register irrespective of the type. - */ - /* - * Loads a specified register from vB. Used primarily for conversions - * from or to a floating-point type. - * - * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to - * store the result in vA and jump to the next instruction. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - */ - ext a1, rINST, 8, 4 # a1 <- A - srl a2, rINST, 12 # a2 <- B - GET_VREG_DOUBLE f0, a2 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - - cvt.s.l f0, f0 - /* - * Stores a specified register containing the result of conversion - * from or to a floating-point type and jumps to the next instruction. - * - * Expects a1 to contain the destination Dalvik register number. - * a1 is set up by fcvtHeader.S. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - * - * Note that this file can't be included after a break in other files - * and in those files its contents appear as a copy. - * See: float-to-int, float-to-long, double-to-int, double-to-long. - */ - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_FLOAT f0, a1 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_long_to_double: /* 0x86 */ - /* - * Conversion from or to floating-point happens in a floating-point register. - * Therefore we load the input and store the output into or from a - * floating-point register irrespective of the type. - */ - /* - * Loads a specified register from vB. Used primarily for conversions - * from or to a floating-point type. - * - * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to - * store the result in vA and jump to the next instruction. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - */ - ext a1, rINST, 8, 4 # a1 <- A - srl a2, rINST, 12 # a2 <- B - GET_VREG_DOUBLE f0, a2 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - - cvt.d.l f0, f0 - /* - * Stores a specified register containing the result of conversion - * from or to a floating-point type and jumps to the next instruction. - * - * Expects a1 to contain the destination Dalvik register number. - * a1 is set up by fcvtHeader.S. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - * - * Note that this file can't be included after a break in other files - * and in those files its contents appear as a copy. - * See: float-to-int, float-to-long, double-to-int, double-to-long. - */ - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_DOUBLE f0, a1 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_float_to_int: /* 0x87 */ - /* - * Loads a specified register from vB. Used primarily for conversions - * from or to a floating-point type. - * - * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to - * store the result in vA and jump to the next instruction. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - */ - ext a1, rINST, 8, 4 # a1 <- A - srl a2, rINST, 12 # a2 <- B - GET_VREG_FLOAT f0, a2 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - - trunc.w.s f0, f0 - /* - * Stores a specified register containing the result of conversion - * from or to a floating-point type and jumps to the next instruction. - * - * Expects a1 to contain the destination Dalvik register number. - * a1 is set up by fcvtHeader.S. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - * - * Note that this file can't be included after a break in other files - * and in those files its contents appear as a copy. - * See: float-to-int, float-to-long, double-to-int, double-to-long. - */ - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_FLOAT f0, a1 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_float_to_long: /* 0x88 */ - /* - * Loads a specified register from vB. Used primarily for conversions - * from or to a floating-point type. - * - * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to - * store the result in vA and jump to the next instruction. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - */ - ext a1, rINST, 8, 4 # a1 <- A - srl a2, rINST, 12 # a2 <- B - GET_VREG_FLOAT f0, a2 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - - trunc.l.s f0, f0 - /* - * Stores a specified register containing the result of conversion - * from or to a floating-point type and jumps to the next instruction. - * - * Expects a1 to contain the destination Dalvik register number. - * a1 is set up by fcvtHeader.S. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - * - * Note that this file can't be included after a break in other files - * and in those files its contents appear as a copy. - * See: float-to-int, float-to-long, double-to-int, double-to-long. - */ - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_DOUBLE f0, a1 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_float_to_double: /* 0x89 */ - /* - * Conversion from or to floating-point happens in a floating-point register. - * Therefore we load the input and store the output into or from a - * floating-point register irrespective of the type. - */ - /* - * Loads a specified register from vB. Used primarily for conversions - * from or to a floating-point type. - * - * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to - * store the result in vA and jump to the next instruction. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - */ - ext a1, rINST, 8, 4 # a1 <- A - srl a2, rINST, 12 # a2 <- B - GET_VREG_FLOAT f0, a2 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - - cvt.d.s f0, f0 - /* - * Stores a specified register containing the result of conversion - * from or to a floating-point type and jumps to the next instruction. - * - * Expects a1 to contain the destination Dalvik register number. - * a1 is set up by fcvtHeader.S. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - * - * Note that this file can't be included after a break in other files - * and in those files its contents appear as a copy. - * See: float-to-int, float-to-long, double-to-int, double-to-long. - */ - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_DOUBLE f0, a1 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_double_to_int: /* 0x8a */ - /* - * Loads a specified register from vB. Used primarily for conversions - * from or to a floating-point type. - * - * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to - * store the result in vA and jump to the next instruction. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - */ - ext a1, rINST, 8, 4 # a1 <- A - srl a2, rINST, 12 # a2 <- B - GET_VREG_DOUBLE f0, a2 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - - trunc.w.d f0, f0 - /* - * Stores a specified register containing the result of conversion - * from or to a floating-point type and jumps to the next instruction. - * - * Expects a1 to contain the destination Dalvik register number. - * a1 is set up by fcvtHeader.S. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - * - * Note that this file can't be included after a break in other files - * and in those files its contents appear as a copy. - * See: float-to-int, float-to-long, double-to-int, double-to-long. - */ - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_FLOAT f0, a1 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_double_to_long: /* 0x8b */ - /* - * Loads a specified register from vB. Used primarily for conversions - * from or to a floating-point type. - * - * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to - * store the result in vA and jump to the next instruction. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - */ - ext a1, rINST, 8, 4 # a1 <- A - srl a2, rINST, 12 # a2 <- B - GET_VREG_DOUBLE f0, a2 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - - trunc.l.d f0, f0 - /* - * Stores a specified register containing the result of conversion - * from or to a floating-point type and jumps to the next instruction. - * - * Expects a1 to contain the destination Dalvik register number. - * a1 is set up by fcvtHeader.S. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - * - * Note that this file can't be included after a break in other files - * and in those files its contents appear as a copy. - * See: float-to-int, float-to-long, double-to-int, double-to-long. - */ - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_DOUBLE f0, a1 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_double_to_float: /* 0x8c */ - /* - * Conversion from or to floating-point happens in a floating-point register. - * Therefore we load the input and store the output into or from a - * floating-point register irrespective of the type. - */ - /* - * Loads a specified register from vB. Used primarily for conversions - * from or to a floating-point type. - * - * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to - * store the result in vA and jump to the next instruction. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - */ - ext a1, rINST, 8, 4 # a1 <- A - srl a2, rINST, 12 # a2 <- B - GET_VREG_DOUBLE f0, a2 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - - cvt.s.d f0, f0 - /* - * Stores a specified register containing the result of conversion - * from or to a floating-point type and jumps to the next instruction. - * - * Expects a1 to contain the destination Dalvik register number. - * a1 is set up by fcvtHeader.S. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - * - * Note that this file can't be included after a break in other files - * and in those files its contents appear as a copy. - * See: float-to-int, float-to-long, double-to-int, double-to-long. - */ - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_FLOAT f0, a1 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_byte: /* 0x8d */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "a0 = op a0". - * - * for: int-to-byte, int-to-char, int-to-short, - * not-int, neg-int - */ - /* unop vA, vB */ - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a3 # a0 <- vB - ext a2, rINST, 8, 4 # a2 <- A - # optional op - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - seb a0, a0 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_char: /* 0x8e */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "a0 = op a0". - * - * for: int-to-byte, int-to-char, int-to-short, - * not-int, neg-int - */ - /* unop vA, vB */ - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a3 # a0 <- vB - ext a2, rINST, 8, 4 # a2 <- A - # optional op - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - and a0, a0, 0xffff # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_short: /* 0x8f */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "a0 = op a0". - * - * for: int-to-byte, int-to-char, int-to-short, - * not-int, neg-int - */ - /* unop vA, vB */ - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a3 # a0 <- vB - ext a2, rINST, 8, 4 # a2 <- A - # optional op - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - seh a0, a0 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_add_int: /* 0x90 */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG a0, a2 # a0 <- vBB - GET_VREG a1, a3 # a1 <- vCC - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - addu a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_sub_int: /* 0x91 */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG a0, a2 # a0 <- vBB - GET_VREG a1, a3 # a1 <- vCC - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - subu a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int: /* 0x92 */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG a0, a2 # a0 <- vBB - GET_VREG a1, a3 # a1 <- vCC - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - mul a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_div_int: /* 0x93 */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG a0, a2 # a0 <- vBB - GET_VREG a1, a3 # a1 <- vCC - .if 1 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - div a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int: /* 0x94 */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG a0, a2 # a0 <- vBB - GET_VREG a1, a3 # a1 <- vCC - .if 1 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - mod a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_and_int: /* 0x95 */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG a0, a2 # a0 <- vBB - GET_VREG a1, a3 # a1 <- vCC - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - and a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_or_int: /* 0x96 */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG a0, a2 # a0 <- vBB - GET_VREG a1, a3 # a1 <- vCC - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - or a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int: /* 0x97 */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG a0, a2 # a0 <- vBB - GET_VREG a1, a3 # a1 <- vCC - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - xor a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_shl_int: /* 0x98 */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG a0, a2 # a0 <- vBB - GET_VREG a1, a3 # a1 <- vCC - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - sll a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_shr_int: /* 0x99 */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG a0, a2 # a0 <- vBB - GET_VREG a1, a3 # a1 <- vCC - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - sra a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_int: /* 0x9a */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG a0, a2 # a0 <- vBB - GET_VREG a1, a3 # a1 <- vCC - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - srl a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_add_long: /* 0x9b */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, shl-long, shr-long, ushr-long - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_WIDE a0, a2 # a0 <- vBB - GET_VREG_WIDE a1, a3 # a1 <- vCC - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - daddu a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_sub_long: /* 0x9c */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, shl-long, shr-long, ushr-long - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_WIDE a0, a2 # a0 <- vBB - GET_VREG_WIDE a1, a3 # a1 <- vCC - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - dsubu a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_mul_long: /* 0x9d */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, shl-long, shr-long, ushr-long - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_WIDE a0, a2 # a0 <- vBB - GET_VREG_WIDE a1, a3 # a1 <- vCC - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - dmul a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_div_long: /* 0x9e */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, shl-long, shr-long, ushr-long - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_WIDE a0, a2 # a0 <- vBB - GET_VREG_WIDE a1, a3 # a1 <- vCC - .if 1 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - ddiv a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_rem_long: /* 0x9f */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, shl-long, shr-long, ushr-long - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_WIDE a0, a2 # a0 <- vBB - GET_VREG_WIDE a1, a3 # a1 <- vCC - .if 1 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - dmod a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_and_long: /* 0xa0 */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, shl-long, shr-long, ushr-long - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_WIDE a0, a2 # a0 <- vBB - GET_VREG_WIDE a1, a3 # a1 <- vCC - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - and a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_or_long: /* 0xa1 */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, shl-long, shr-long, ushr-long - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_WIDE a0, a2 # a0 <- vBB - GET_VREG_WIDE a1, a3 # a1 <- vCC - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - or a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_xor_long: /* 0xa2 */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, shl-long, shr-long, ushr-long - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_WIDE a0, a2 # a0 <- vBB - GET_VREG_WIDE a1, a3 # a1 <- vCC - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - xor a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_shl_long: /* 0xa3 */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, shl-long, shr-long, ushr-long - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_WIDE a0, a2 # a0 <- vBB - GET_VREG_WIDE a1, a3 # a1 <- vCC - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - dsll a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_shr_long: /* 0xa4 */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, shl-long, shr-long, ushr-long - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_WIDE a0, a2 # a0 <- vBB - GET_VREG_WIDE a1, a3 # a1 <- vCC - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - dsra a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_long: /* 0xa5 */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, shl-long, shr-long, ushr-long - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_WIDE a0, a2 # a0 <- vBB - GET_VREG_WIDE a1, a3 # a1 <- vCC - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - dsrl a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_add_float: /* 0xa6 */ - /*: - * Generic 32-bit floating-point operation. - * - * For: add-float, sub-float, mul-float, div-float. - * form: f0, f0, f1 - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_FLOAT f0, a2 # f0 <- vBB - GET_VREG_FLOAT f1, a3 # f1 <- vCC - add.s f0, f0, f1 # f0 <- f0 op f1 - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_FLOAT f0, a4 # vAA <- f0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_sub_float: /* 0xa7 */ - /*: - * Generic 32-bit floating-point operation. - * - * For: add-float, sub-float, mul-float, div-float. - * form: f0, f0, f1 - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_FLOAT f0, a2 # f0 <- vBB - GET_VREG_FLOAT f1, a3 # f1 <- vCC - sub.s f0, f0, f1 # f0 <- f0 op f1 - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_FLOAT f0, a4 # vAA <- f0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_mul_float: /* 0xa8 */ - /*: - * Generic 32-bit floating-point operation. - * - * For: add-float, sub-float, mul-float, div-float. - * form: f0, f0, f1 - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_FLOAT f0, a2 # f0 <- vBB - GET_VREG_FLOAT f1, a3 # f1 <- vCC - mul.s f0, f0, f1 # f0 <- f0 op f1 - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_FLOAT f0, a4 # vAA <- f0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_div_float: /* 0xa9 */ - /*: - * Generic 32-bit floating-point operation. - * - * For: add-float, sub-float, mul-float, div-float. - * form: f0, f0, f1 - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_FLOAT f0, a2 # f0 <- vBB - GET_VREG_FLOAT f1, a3 # f1 <- vCC - div.s f0, f0, f1 # f0 <- f0 op f1 - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_FLOAT f0, a4 # vAA <- f0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_rem_float: /* 0xaa */ - /* rem-float vAA, vBB, vCC */ - .extern fmodf - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_FLOAT f12, a2 # f12 <- vBB - GET_VREG_FLOAT f13, a3 # f13 <- vCC - jal fmodf # f0 <- f12 op f13 - srl a4, rINST, 8 # a4 <- AA - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_FLOAT f0, a4 # vAA <- f0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_add_double: /* 0xab */ - /*: - * Generic 64-bit floating-point operation. - * - * For: add-double, sub-double, mul-double, div-double. - * form: f0, f0, f1 - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_DOUBLE f0, a2 # f0 <- vBB - GET_VREG_DOUBLE f1, a3 # f1 <- vCC - add.d f0, f0, f1 # f0 <- f0 op f1 - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_DOUBLE f0, a4 # vAA <- f0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_sub_double: /* 0xac */ - /*: - * Generic 64-bit floating-point operation. - * - * For: add-double, sub-double, mul-double, div-double. - * form: f0, f0, f1 - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_DOUBLE f0, a2 # f0 <- vBB - GET_VREG_DOUBLE f1, a3 # f1 <- vCC - sub.d f0, f0, f1 # f0 <- f0 op f1 - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_DOUBLE f0, a4 # vAA <- f0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_mul_double: /* 0xad */ - /*: - * Generic 64-bit floating-point operation. - * - * For: add-double, sub-double, mul-double, div-double. - * form: f0, f0, f1 - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_DOUBLE f0, a2 # f0 <- vBB - GET_VREG_DOUBLE f1, a3 # f1 <- vCC - mul.d f0, f0, f1 # f0 <- f0 op f1 - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_DOUBLE f0, a4 # vAA <- f0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_div_double: /* 0xae */ - /*: - * Generic 64-bit floating-point operation. - * - * For: add-double, sub-double, mul-double, div-double. - * form: f0, f0, f1 - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_DOUBLE f0, a2 # f0 <- vBB - GET_VREG_DOUBLE f1, a3 # f1 <- vCC - div.d f0, f0, f1 # f0 <- f0 op f1 - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_DOUBLE f0, a4 # vAA <- f0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_rem_double: /* 0xaf */ - /* rem-double vAA, vBB, vCC */ - .extern fmod - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_DOUBLE f12, a2 # f12 <- vBB - GET_VREG_DOUBLE f13, a3 # f13 <- vCC - jal fmod # f0 <- f12 op f13 - srl a4, rINST, 8 # a4 <- AA - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_DOUBLE f0, a4 # vAA <- f0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_add_int_2addr: /* 0xb0 */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a2 # a0 <- vA - GET_VREG a1, a3 # a1 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - addu a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_sub_int_2addr: /* 0xb1 */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a2 # a0 <- vA - GET_VREG a1, a3 # a1 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - subu a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int_2addr: /* 0xb2 */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a2 # a0 <- vA - GET_VREG a1, a3 # a1 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - mul a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_div_int_2addr: /* 0xb3 */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a2 # a0 <- vA - GET_VREG a1, a3 # a1 <- vB - .if 1 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - div a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int_2addr: /* 0xb4 */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a2 # a0 <- vA - GET_VREG a1, a3 # a1 <- vB - .if 1 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - mod a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_and_int_2addr: /* 0xb5 */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a2 # a0 <- vA - GET_VREG a1, a3 # a1 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - and a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_or_int_2addr: /* 0xb6 */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a2 # a0 <- vA - GET_VREG a1, a3 # a1 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - or a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int_2addr: /* 0xb7 */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a2 # a0 <- vA - GET_VREG a1, a3 # a1 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - xor a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_shl_int_2addr: /* 0xb8 */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a2 # a0 <- vA - GET_VREG a1, a3 # a1 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - sll a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_shr_int_2addr: /* 0xb9 */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a2 # a0 <- vA - GET_VREG a1, a3 # a1 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - sra a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_int_2addr: /* 0xba */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a2 # a0 <- vA - GET_VREG a1, a3 # a1 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - srl a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_add_long_2addr: /* 0xbb */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_WIDE a0, a2 # a0 <- vA - GET_VREG_WIDE a1, a3 # a1 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - daddu a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_sub_long_2addr: /* 0xbc */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_WIDE a0, a2 # a0 <- vA - GET_VREG_WIDE a1, a3 # a1 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - dsubu a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_mul_long_2addr: /* 0xbd */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_WIDE a0, a2 # a0 <- vA - GET_VREG_WIDE a1, a3 # a1 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - dmul a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_div_long_2addr: /* 0xbe */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_WIDE a0, a2 # a0 <- vA - GET_VREG_WIDE a1, a3 # a1 <- vB - .if 1 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - ddiv a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_rem_long_2addr: /* 0xbf */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_WIDE a0, a2 # a0 <- vA - GET_VREG_WIDE a1, a3 # a1 <- vB - .if 1 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - dmod a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_and_long_2addr: /* 0xc0 */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_WIDE a0, a2 # a0 <- vA - GET_VREG_WIDE a1, a3 # a1 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - and a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_or_long_2addr: /* 0xc1 */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_WIDE a0, a2 # a0 <- vA - GET_VREG_WIDE a1, a3 # a1 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - or a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_xor_long_2addr: /* 0xc2 */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_WIDE a0, a2 # a0 <- vA - GET_VREG_WIDE a1, a3 # a1 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - xor a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_shl_long_2addr: /* 0xc3 */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_WIDE a0, a2 # a0 <- vA - GET_VREG_WIDE a1, a3 # a1 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - dsll a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_shr_long_2addr: /* 0xc4 */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_WIDE a0, a2 # a0 <- vA - GET_VREG_WIDE a1, a3 # a1 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - dsra a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_long_2addr: /* 0xc5 */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_WIDE a0, a2 # a0 <- vA - GET_VREG_WIDE a1, a3 # a1 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - dsrl a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_add_float_2addr: /* 0xc6 */ - /*: - * Generic 32-bit "/2addr" floating-point operation. - * - * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr. - * form: f0, f0, f1 - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_FLOAT f0, a2 # f0 <- vA - GET_VREG_FLOAT f1, a3 # f1 <- vB - add.s f0, f0, f1 # f0 <- f0 op f1 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_FLOAT f0, a2 # vA <- f0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_sub_float_2addr: /* 0xc7 */ - /*: - * Generic 32-bit "/2addr" floating-point operation. - * - * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr. - * form: f0, f0, f1 - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_FLOAT f0, a2 # f0 <- vA - GET_VREG_FLOAT f1, a3 # f1 <- vB - sub.s f0, f0, f1 # f0 <- f0 op f1 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_FLOAT f0, a2 # vA <- f0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_mul_float_2addr: /* 0xc8 */ - /*: - * Generic 32-bit "/2addr" floating-point operation. - * - * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr. - * form: f0, f0, f1 - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_FLOAT f0, a2 # f0 <- vA - GET_VREG_FLOAT f1, a3 # f1 <- vB - mul.s f0, f0, f1 # f0 <- f0 op f1 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_FLOAT f0, a2 # vA <- f0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_div_float_2addr: /* 0xc9 */ - /*: - * Generic 32-bit "/2addr" floating-point operation. - * - * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr. - * form: f0, f0, f1 - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_FLOAT f0, a2 # f0 <- vA - GET_VREG_FLOAT f1, a3 # f1 <- vB - div.s f0, f0, f1 # f0 <- f0 op f1 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_FLOAT f0, a2 # vA <- f0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_rem_float_2addr: /* 0xca */ - /* rem-float/2addr vA, vB */ - .extern fmodf - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_FLOAT f12, a2 # f12 <- vA - GET_VREG_FLOAT f13, a3 # f13 <- vB - jal fmodf # f0 <- f12 op f13 - ext a2, rINST, 8, 4 # a2 <- A - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_FLOAT f0, a2 # vA <- f0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_add_double_2addr: /* 0xcb */ - /*: - * Generic 64-bit "/2addr" floating-point operation. - * - * For: add-double/2addr, sub-double/2addr, mul-double/2addr, div-double/2addr. - * form: f0, f0, f1 - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_DOUBLE f0, a2 # f0 <- vA - GET_VREG_DOUBLE f1, a3 # f1 <- vB - add.d f0, f0, f1 # f0 <- f0 op f1 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_DOUBLE f0, a2 # vA <- f0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_sub_double_2addr: /* 0xcc */ - /*: - * Generic 64-bit "/2addr" floating-point operation. - * - * For: add-double/2addr, sub-double/2addr, mul-double/2addr, div-double/2addr. - * form: f0, f0, f1 - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_DOUBLE f0, a2 # f0 <- vA - GET_VREG_DOUBLE f1, a3 # f1 <- vB - sub.d f0, f0, f1 # f0 <- f0 op f1 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_DOUBLE f0, a2 # vA <- f0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_mul_double_2addr: /* 0xcd */ - /*: - * Generic 64-bit "/2addr" floating-point operation. - * - * For: add-double/2addr, sub-double/2addr, mul-double/2addr, div-double/2addr. - * form: f0, f0, f1 - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_DOUBLE f0, a2 # f0 <- vA - GET_VREG_DOUBLE f1, a3 # f1 <- vB - mul.d f0, f0, f1 # f0 <- f0 op f1 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_DOUBLE f0, a2 # vA <- f0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_div_double_2addr: /* 0xce */ - /*: - * Generic 64-bit "/2addr" floating-point operation. - * - * For: add-double/2addr, sub-double/2addr, mul-double/2addr, div-double/2addr. - * form: f0, f0, f1 - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_DOUBLE f0, a2 # f0 <- vA - GET_VREG_DOUBLE f1, a3 # f1 <- vB - div.d f0, f0, f1 # f0 <- f0 op f1 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_DOUBLE f0, a2 # vA <- f0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_rem_double_2addr: /* 0xcf */ - /* rem-double/2addr vA, vB */ - .extern fmod - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_DOUBLE f12, a2 # f12 <- vA - GET_VREG_DOUBLE f13, a3 # f13 <- vB - jal fmod # f0 <- f12 op f13 - ext a2, rINST, 8, 4 # a2 <- A - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_DOUBLE f0, a2 # vA <- f0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_add_int_lit16: /* 0xd0 */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * CCCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - lh a1, 2(rPC) # a1 <- sign-extended CCCC - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a3 # a0 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - addu a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_rsub_int: /* 0xd1 */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * CCCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - lh a1, 2(rPC) # a1 <- sign-extended CCCC - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a3 # a0 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - subu a0, a1, a0 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int_lit16: /* 0xd2 */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * CCCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - lh a1, 2(rPC) # a1 <- sign-extended CCCC - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a3 # a0 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - mul a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_div_int_lit16: /* 0xd3 */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * CCCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - lh a1, 2(rPC) # a1 <- sign-extended CCCC - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a3 # a0 <- vB - .if 1 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - div a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int_lit16: /* 0xd4 */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * CCCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - lh a1, 2(rPC) # a1 <- sign-extended CCCC - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a3 # a0 <- vB - .if 1 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - mod a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_and_int_lit16: /* 0xd5 */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * CCCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - lh a1, 2(rPC) # a1 <- sign-extended CCCC - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a3 # a0 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - and a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_or_int_lit16: /* 0xd6 */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * CCCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - lh a1, 2(rPC) # a1 <- sign-extended CCCC - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a3 # a0 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - or a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int_lit16: /* 0xd7 */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * CCCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - lh a1, 2(rPC) # a1 <- sign-extended CCCC - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a3 # a0 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - xor a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_add_int_lit8: /* 0xd8 */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * CC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - lbu a3, 2(rPC) # a3 <- BB - lb a1, 3(rPC) # a1 <- sign-extended CC - srl a2, rINST, 8 # a2 <- AA - GET_VREG a0, a3 # a0 <- vBB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - addu a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_rsub_int_lit8: /* 0xd9 */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * CC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - lbu a3, 2(rPC) # a3 <- BB - lb a1, 3(rPC) # a1 <- sign-extended CC - srl a2, rINST, 8 # a2 <- AA - GET_VREG a0, a3 # a0 <- vBB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - subu a0, a1, a0 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int_lit8: /* 0xda */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * CC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - lbu a3, 2(rPC) # a3 <- BB - lb a1, 3(rPC) # a1 <- sign-extended CC - srl a2, rINST, 8 # a2 <- AA - GET_VREG a0, a3 # a0 <- vBB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - mul a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_div_int_lit8: /* 0xdb */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * CC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - lbu a3, 2(rPC) # a3 <- BB - lb a1, 3(rPC) # a1 <- sign-extended CC - srl a2, rINST, 8 # a2 <- AA - GET_VREG a0, a3 # a0 <- vBB - .if 1 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - div a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int_lit8: /* 0xdc */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * CC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - lbu a3, 2(rPC) # a3 <- BB - lb a1, 3(rPC) # a1 <- sign-extended CC - srl a2, rINST, 8 # a2 <- AA - GET_VREG a0, a3 # a0 <- vBB - .if 1 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - mod a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_and_int_lit8: /* 0xdd */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * CC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - lbu a3, 2(rPC) # a3 <- BB - lb a1, 3(rPC) # a1 <- sign-extended CC - srl a2, rINST, 8 # a2 <- AA - GET_VREG a0, a3 # a0 <- vBB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - and a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_or_int_lit8: /* 0xde */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * CC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - lbu a3, 2(rPC) # a3 <- BB - lb a1, 3(rPC) # a1 <- sign-extended CC - srl a2, rINST, 8 # a2 <- AA - GET_VREG a0, a3 # a0 <- vBB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - or a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int_lit8: /* 0xdf */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * CC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - lbu a3, 2(rPC) # a3 <- BB - lb a1, 3(rPC) # a1 <- sign-extended CC - srl a2, rINST, 8 # a2 <- AA - GET_VREG a0, a3 # a0 <- vBB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - xor a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_shl_int_lit8: /* 0xe0 */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * CC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - lbu a3, 2(rPC) # a3 <- BB - lb a1, 3(rPC) # a1 <- sign-extended CC - srl a2, rINST, 8 # a2 <- AA - GET_VREG a0, a3 # a0 <- vBB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - sll a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_shr_int_lit8: /* 0xe1 */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * CC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - lbu a3, 2(rPC) # a3 <- BB - lb a1, 3(rPC) # a1 <- sign-extended CC - srl a2, rINST, 8 # a2 <- AA - GET_VREG a0, a3 # a0 <- vBB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - sra a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_int_lit8: /* 0xe2 */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * CC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - lbu a3, 2(rPC) # a3 <- BB - lb a1, 3(rPC) # a1 <- sign-extended CC - srl a2, rINST, 8 # a2 <- AA - GET_VREG a0, a3 # a0 <- vBB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - srl a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iget_quick: /* 0xe3 */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset//CCCC */ - srl a2, rINST, 12 # a2 <- B - lhu a1, 2(rPC) # a1 <- field byte offset - GET_VREG_U a3, a2 # a3 <- object we're operating on - ext a4, rINST, 8, 4 # a4 <- A - daddu a1, a1, a3 - beqz a3, common_errNullObject # object was null - lw a0, 0(a1) # a0 <- obj.field - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - SET_VREG a0, a4 # fp[A] <- a0 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iget_wide_quick: /* 0xe4 */ - /* iget-wide-quick vA, vB, offset//CCCC */ - srl a2, rINST, 12 # a2 <- B - lhu a4, 2(rPC) # a4 <- field byte offset - GET_VREG_U a3, a2 # a3 <- object we're operating on - ext a2, rINST, 8, 4 # a2 <- A - beqz a3, common_errNullObject # object was null - daddu a4, a3, a4 # create direct pointer - lw a0, 0(a4) - lw a1, 4(a4) - dinsu a0, a1, 32, 32 - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - SET_VREG_WIDE a0, a2 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iget_object_quick: /* 0xe5 */ - /* For: iget-object-quick */ - /* op vA, vB, offset//CCCC */ - .extern artIGetObjectFromMterp - srl a2, rINST, 12 # a2 <- B - lhu a1, 2(rPC) # a1 <- field byte offset - EXPORT_PC - GET_VREG_U a0, a2 # a0 <- object we're operating on - jal artIGetObjectFromMterp # (obj, offset) - ld a3, THREAD_EXCEPTION_OFFSET(rSELF) - ext a2, rINST, 8, 4 # a2 <- A - PREFETCH_INST 2 - bnez a3, MterpPossibleException # bail out - SET_VREG_OBJECT v0, a2 # fp[A] <- v0 - ADVANCE 2 # advance rPC - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_quick: /* 0xe6 */ - /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */ - /* op vA, vB, offset//CCCC */ - srl a2, rINST, 12 # a2 <- B - lhu a1, 2(rPC) # a1 <- field byte offset - GET_VREG_U a3, a2 # a3 <- fp[B], the object pointer - ext a2, rINST, 8, 4 # a2 <- A - beqz a3, common_errNullObject # object was null - GET_VREG a0, a2 # a0 <- fp[A] - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - daddu a1, a1, a3 - sw a0, 0(a1) # obj.field <- a0 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_wide_quick: /* 0xe7 */ - /* iput-wide-quick vA, vB, offset//CCCC */ - srl a2, rINST, 12 # a2 <- B - lhu a3, 2(rPC) # a3 <- field byte offset - GET_VREG_U a2, a2 # a2 <- fp[B], the object pointer - ext a0, rINST, 8, 4 # a0 <- A - beqz a2, common_errNullObject # object was null - GET_VREG_WIDE a0, a0 # a0 <- fp[A] - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - daddu a1, a2, a3 # create a direct pointer - sw a0, 0(a1) - dsrl32 a0, a0, 0 - sw a0, 4(a1) - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_object_quick: /* 0xe8 */ - .extern MterpIputObjectQuick - EXPORT_PC - daddu a0, rFP, OFF_FP_SHADOWFRAME - move a1, rPC - move a2, rINST - jal MterpIputObjectQuick - beqzc v0, MterpException - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual_quick: /* 0xe9 */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtualQuick - .extern MterpShouldSwitchInterpreters - EXPORT_PC - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - jal MterpInvokeVirtualQuick - beqzc v0, MterpException - FETCH_ADVANCE_INST 3 - jal MterpShouldSwitchInterpreters - bnezc v0, MterpFallback - GET_INST_OPCODE v0 - GOTO_OPCODE v0 - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual_range_quick: /* 0xea */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtualQuickRange - .extern MterpShouldSwitchInterpreters - EXPORT_PC - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - jal MterpInvokeVirtualQuickRange - beqzc v0, MterpException - FETCH_ADVANCE_INST 3 - jal MterpShouldSwitchInterpreters - bnezc v0, MterpFallback - GET_INST_OPCODE v0 - GOTO_OPCODE v0 - -/* ------------------------------ */ - .balign 128 -.L_op_iput_boolean_quick: /* 0xeb */ - /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */ - /* op vA, vB, offset//CCCC */ - srl a2, rINST, 12 # a2 <- B - lhu a1, 2(rPC) # a1 <- field byte offset - GET_VREG_U a3, a2 # a3 <- fp[B], the object pointer - ext a2, rINST, 8, 4 # a2 <- A - beqz a3, common_errNullObject # object was null - GET_VREG a0, a2 # a0 <- fp[A] - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - daddu a1, a1, a3 - sb a0, 0(a1) # obj.field <- a0 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_byte_quick: /* 0xec */ - /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */ - /* op vA, vB, offset//CCCC */ - srl a2, rINST, 12 # a2 <- B - lhu a1, 2(rPC) # a1 <- field byte offset - GET_VREG_U a3, a2 # a3 <- fp[B], the object pointer - ext a2, rINST, 8, 4 # a2 <- A - beqz a3, common_errNullObject # object was null - GET_VREG a0, a2 # a0 <- fp[A] - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - daddu a1, a1, a3 - sb a0, 0(a1) # obj.field <- a0 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_char_quick: /* 0xed */ - /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */ - /* op vA, vB, offset//CCCC */ - srl a2, rINST, 12 # a2 <- B - lhu a1, 2(rPC) # a1 <- field byte offset - GET_VREG_U a3, a2 # a3 <- fp[B], the object pointer - ext a2, rINST, 8, 4 # a2 <- A - beqz a3, common_errNullObject # object was null - GET_VREG a0, a2 # a0 <- fp[A] - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - daddu a1, a1, a3 - sh a0, 0(a1) # obj.field <- a0 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_short_quick: /* 0xee */ - /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */ - /* op vA, vB, offset//CCCC */ - srl a2, rINST, 12 # a2 <- B - lhu a1, 2(rPC) # a1 <- field byte offset - GET_VREG_U a3, a2 # a3 <- fp[B], the object pointer - ext a2, rINST, 8, 4 # a2 <- A - beqz a3, common_errNullObject # object was null - GET_VREG a0, a2 # a0 <- fp[A] - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - daddu a1, a1, a3 - sh a0, 0(a1) # obj.field <- a0 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iget_boolean_quick: /* 0xef */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset//CCCC */ - srl a2, rINST, 12 # a2 <- B - lhu a1, 2(rPC) # a1 <- field byte offset - GET_VREG_U a3, a2 # a3 <- object we're operating on - ext a4, rINST, 8, 4 # a4 <- A - daddu a1, a1, a3 - beqz a3, common_errNullObject # object was null - lbu a0, 0(a1) # a0 <- obj.field - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - SET_VREG a0, a4 # fp[A] <- a0 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iget_byte_quick: /* 0xf0 */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset//CCCC */ - srl a2, rINST, 12 # a2 <- B - lhu a1, 2(rPC) # a1 <- field byte offset - GET_VREG_U a3, a2 # a3 <- object we're operating on - ext a4, rINST, 8, 4 # a4 <- A - daddu a1, a1, a3 - beqz a3, common_errNullObject # object was null - lb a0, 0(a1) # a0 <- obj.field - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - SET_VREG a0, a4 # fp[A] <- a0 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iget_char_quick: /* 0xf1 */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset//CCCC */ - srl a2, rINST, 12 # a2 <- B - lhu a1, 2(rPC) # a1 <- field byte offset - GET_VREG_U a3, a2 # a3 <- object we're operating on - ext a4, rINST, 8, 4 # a4 <- A - daddu a1, a1, a3 - beqz a3, common_errNullObject # object was null - lhu a0, 0(a1) # a0 <- obj.field - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - SET_VREG a0, a4 # fp[A] <- a0 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iget_short_quick: /* 0xf2 */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset//CCCC */ - srl a2, rINST, 12 # a2 <- B - lhu a1, 2(rPC) # a1 <- field byte offset - GET_VREG_U a3, a2 # a3 <- object we're operating on - ext a4, rINST, 8, 4 # a4 <- A - daddu a1, a1, a3 - beqz a3, common_errNullObject # object was null - lh a0, 0(a1) # a0 <- obj.field - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - SET_VREG a0, a4 # fp[A] <- a0 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f3: /* 0xf3 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f4: /* 0xf4 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f5: /* 0xf5 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f6: /* 0xf6 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f7: /* 0xf7 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f8: /* 0xf8 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f9: /* 0xf9 */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_polymorphic: /* 0xfa */ - /* - * invoke-polymorphic handler wrapper. - */ - /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ - .extern MterpInvokePolymorphic - .extern MterpShouldSwitchInterpreters - EXPORT_PC - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - jal MterpInvokePolymorphic - beqzc v0, MterpException - FETCH_ADVANCE_INST 4 - jal MterpShouldSwitchInterpreters - bnezc v0, MterpFallback - GET_INST_OPCODE v0 - GOTO_OPCODE v0 - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_polymorphic_range: /* 0xfb */ - /* - * invoke-polymorphic handler wrapper. - */ - /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ - .extern MterpInvokePolymorphicRange - .extern MterpShouldSwitchInterpreters - EXPORT_PC - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - jal MterpInvokePolymorphicRange - beqzc v0, MterpException - FETCH_ADVANCE_INST 4 - jal MterpShouldSwitchInterpreters - bnezc v0, MterpFallback - GET_INST_OPCODE v0 - GOTO_OPCODE v0 - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_custom: /* 0xfc */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeCustom - .extern MterpShouldSwitchInterpreters - EXPORT_PC - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - jal MterpInvokeCustom - beqzc v0, MterpException - FETCH_ADVANCE_INST 3 - jal MterpShouldSwitchInterpreters - bnezc v0, MterpFallback - GET_INST_OPCODE v0 - GOTO_OPCODE v0 - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_custom_range: /* 0xfd */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeCustomRange - .extern MterpShouldSwitchInterpreters - EXPORT_PC - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - jal MterpInvokeCustomRange - beqzc v0, MterpException - FETCH_ADVANCE_INST 3 - jal MterpShouldSwitchInterpreters - bnezc v0, MterpFallback - GET_INST_OPCODE v0 - GOTO_OPCODE v0 - -/* ------------------------------ */ - .balign 128 -.L_op_const_method_handle: /* 0xfe */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstMethodHandle - EXPORT_PC - lhu a0, 2(rPC) # a0 <- BBBB - srl a1, rINST, 8 # a1 <- AA - daddu a2, rFP, OFF_FP_SHADOWFRAME - move a3, rSELF - jal MterpConstMethodHandle # (index, tgt_reg, shadow_frame, self) - PREFETCH_INST 2 # load rINST - bnez v0, MterpPossibleException # let reference interpreter deal with it. - ADVANCE 2 # advance rPC - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_method_type: /* 0xff */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstMethodType - EXPORT_PC - lhu a0, 2(rPC) # a0 <- BBBB - srl a1, rINST, 8 # a1 <- AA - daddu a2, rFP, OFF_FP_SHADOWFRAME - move a3, rSELF - jal MterpConstMethodType # (index, tgt_reg, shadow_frame, self) - PREFETCH_INST 2 # load rINST - bnez v0, MterpPossibleException # let reference interpreter deal with it. - ADVANCE 2 # advance rPC - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - - .balign 128 - - .global artMterpAsmInstructionEnd -artMterpAsmInstructionEnd: - - .global artMterpAsmAltInstructionStart -artMterpAsmAltInstructionStart = .L_ALT_op_nop - .text -/* ------------------------------ */ - .balign 128 -.L_ALT_op_nop: /* 0x00 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (0 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move: /* 0x01 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (1 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_from16: /* 0x02 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (2 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_16: /* 0x03 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (3 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_wide: /* 0x04 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (4 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_wide_from16: /* 0x05 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (5 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_wide_16: /* 0x06 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (6 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_object: /* 0x07 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (7 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_object_from16: /* 0x08 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (8 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_object_16: /* 0x09 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (9 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_result: /* 0x0a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (10 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_result_wide: /* 0x0b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (11 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_result_object: /* 0x0c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (12 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_exception: /* 0x0d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (13 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_void: /* 0x0e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (14 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return: /* 0x0f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (15 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_wide: /* 0x10 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (16 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_object: /* 0x11 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (17 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_4: /* 0x12 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (18 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_16: /* 0x13 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (19 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const: /* 0x14 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (20 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_high16: /* 0x15 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (21 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide_16: /* 0x16 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (22 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide_32: /* 0x17 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (23 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide: /* 0x18 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (24 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide_high16: /* 0x19 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (25 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_string: /* 0x1a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (26 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_string_jumbo: /* 0x1b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (27 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_class: /* 0x1c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (28 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_monitor_enter: /* 0x1d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (29 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_monitor_exit: /* 0x1e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (30 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_check_cast: /* 0x1f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (31 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_instance_of: /* 0x20 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (32 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_array_length: /* 0x21 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (33 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_new_instance: /* 0x22 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (34 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_new_array: /* 0x23 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (35 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_filled_new_array: /* 0x24 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (36 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_filled_new_array_range: /* 0x25 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (37 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_fill_array_data: /* 0x26 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (38 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_throw: /* 0x27 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (39 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_goto: /* 0x28 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (40 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_goto_16: /* 0x29 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (41 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_goto_32: /* 0x2a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (42 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_packed_switch: /* 0x2b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (43 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sparse_switch: /* 0x2c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (44 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpl_float: /* 0x2d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (45 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpg_float: /* 0x2e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (46 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpl_double: /* 0x2f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (47 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpg_double: /* 0x30 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (48 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmp_long: /* 0x31 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (49 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_eq: /* 0x32 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (50 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_ne: /* 0x33 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (51 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_lt: /* 0x34 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (52 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_ge: /* 0x35 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (53 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_gt: /* 0x36 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (54 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_le: /* 0x37 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (55 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_eqz: /* 0x38 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (56 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_nez: /* 0x39 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (57 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_ltz: /* 0x3a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (58 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_gez: /* 0x3b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (59 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_gtz: /* 0x3c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (60 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_lez: /* 0x3d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (61 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_3e: /* 0x3e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (62 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_3f: /* 0x3f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (63 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_40: /* 0x40 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (64 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_41: /* 0x41 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (65 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_42: /* 0x42 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (66 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_43: /* 0x43 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (67 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget: /* 0x44 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (68 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_wide: /* 0x45 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (69 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_object: /* 0x46 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (70 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_boolean: /* 0x47 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (71 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_byte: /* 0x48 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (72 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_char: /* 0x49 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (73 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_short: /* 0x4a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (74 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput: /* 0x4b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (75 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_wide: /* 0x4c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (76 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_object: /* 0x4d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (77 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_boolean: /* 0x4e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (78 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_byte: /* 0x4f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (79 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_char: /* 0x50 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (80 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_short: /* 0x51 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (81 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget: /* 0x52 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (82 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_wide: /* 0x53 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (83 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_object: /* 0x54 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (84 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_boolean: /* 0x55 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (85 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_byte: /* 0x56 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (86 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_char: /* 0x57 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (87 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_short: /* 0x58 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (88 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput: /* 0x59 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (89 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_wide: /* 0x5a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (90 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_object: /* 0x5b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (91 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_boolean: /* 0x5c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (92 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_byte: /* 0x5d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (93 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_char: /* 0x5e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (94 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_short: /* 0x5f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (95 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget: /* 0x60 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (96 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_wide: /* 0x61 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (97 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_object: /* 0x62 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (98 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_boolean: /* 0x63 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (99 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_byte: /* 0x64 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (100 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_char: /* 0x65 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (101 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_short: /* 0x66 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (102 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput: /* 0x67 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (103 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_wide: /* 0x68 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (104 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_object: /* 0x69 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (105 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_boolean: /* 0x6a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (106 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_byte: /* 0x6b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (107 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_char: /* 0x6c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (108 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_short: /* 0x6d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (109 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual: /* 0x6e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (110 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_super: /* 0x6f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (111 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_direct: /* 0x70 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (112 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_static: /* 0x71 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (113 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_interface: /* 0x72 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (114 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_void_no_barrier: /* 0x73 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (115 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual_range: /* 0x74 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (116 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_super_range: /* 0x75 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (117 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_direct_range: /* 0x76 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (118 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_static_range: /* 0x77 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (119 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_interface_range: /* 0x78 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (120 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_79: /* 0x79 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (121 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_7a: /* 0x7a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (122 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_int: /* 0x7b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (123 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_not_int: /* 0x7c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (124 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_long: /* 0x7d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (125 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_not_long: /* 0x7e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (126 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_float: /* 0x7f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (127 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_double: /* 0x80 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (128 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_long: /* 0x81 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (129 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_float: /* 0x82 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (130 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_double: /* 0x83 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (131 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_long_to_int: /* 0x84 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (132 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_long_to_float: /* 0x85 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (133 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_long_to_double: /* 0x86 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (134 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_float_to_int: /* 0x87 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (135 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_float_to_long: /* 0x88 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (136 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_float_to_double: /* 0x89 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (137 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_double_to_int: /* 0x8a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (138 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_double_to_long: /* 0x8b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (139 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_double_to_float: /* 0x8c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (140 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_byte: /* 0x8d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (141 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_char: /* 0x8e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (142 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_short: /* 0x8f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (143 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int: /* 0x90 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (144 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_int: /* 0x91 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (145 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int: /* 0x92 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (146 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int: /* 0x93 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (147 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int: /* 0x94 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (148 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int: /* 0x95 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (149 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int: /* 0x96 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (150 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int: /* 0x97 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (151 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_int: /* 0x98 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (152 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_int: /* 0x99 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (153 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_int: /* 0x9a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (154 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_long: /* 0x9b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (155 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_long: /* 0x9c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (156 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_long: /* 0x9d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (157 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_long: /* 0x9e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (158 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_long: /* 0x9f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (159 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_long: /* 0xa0 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (160 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_long: /* 0xa1 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (161 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_long: /* 0xa2 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (162 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_long: /* 0xa3 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (163 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_long: /* 0xa4 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (164 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_long: /* 0xa5 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (165 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_float: /* 0xa6 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (166 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_float: /* 0xa7 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (167 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_float: /* 0xa8 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (168 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_float: /* 0xa9 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (169 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_float: /* 0xaa */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (170 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_double: /* 0xab */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (171 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_double: /* 0xac */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (172 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_double: /* 0xad */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (173 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_double: /* 0xae */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (174 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_double: /* 0xaf */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (175 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int_2addr: /* 0xb0 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (176 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_int_2addr: /* 0xb1 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (177 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int_2addr: /* 0xb2 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (178 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int_2addr: /* 0xb3 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (179 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int_2addr: /* 0xb4 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (180 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int_2addr: /* 0xb5 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (181 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int_2addr: /* 0xb6 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (182 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int_2addr: /* 0xb7 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (183 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_int_2addr: /* 0xb8 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (184 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_int_2addr: /* 0xb9 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (185 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_int_2addr: /* 0xba */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (186 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_long_2addr: /* 0xbb */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (187 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_long_2addr: /* 0xbc */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (188 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_long_2addr: /* 0xbd */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (189 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_long_2addr: /* 0xbe */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (190 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_long_2addr: /* 0xbf */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (191 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_long_2addr: /* 0xc0 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (192 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_long_2addr: /* 0xc1 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (193 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_long_2addr: /* 0xc2 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (194 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_long_2addr: /* 0xc3 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (195 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_long_2addr: /* 0xc4 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (196 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_long_2addr: /* 0xc5 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (197 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_float_2addr: /* 0xc6 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (198 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_float_2addr: /* 0xc7 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (199 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_float_2addr: /* 0xc8 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (200 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_float_2addr: /* 0xc9 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (201 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_float_2addr: /* 0xca */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (202 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_double_2addr: /* 0xcb */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (203 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_double_2addr: /* 0xcc */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (204 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_double_2addr: /* 0xcd */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (205 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_double_2addr: /* 0xce */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (206 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_double_2addr: /* 0xcf */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (207 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int_lit16: /* 0xd0 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (208 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rsub_int: /* 0xd1 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (209 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int_lit16: /* 0xd2 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (210 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int_lit16: /* 0xd3 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (211 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int_lit16: /* 0xd4 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (212 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int_lit16: /* 0xd5 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (213 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int_lit16: /* 0xd6 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (214 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int_lit16: /* 0xd7 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (215 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int_lit8: /* 0xd8 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (216 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rsub_int_lit8: /* 0xd9 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (217 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int_lit8: /* 0xda */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (218 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int_lit8: /* 0xdb */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (219 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int_lit8: /* 0xdc */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (220 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int_lit8: /* 0xdd */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (221 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int_lit8: /* 0xde */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (222 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int_lit8: /* 0xdf */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (223 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_int_lit8: /* 0xe0 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (224 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_int_lit8: /* 0xe1 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (225 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_int_lit8: /* 0xe2 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (226 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_quick: /* 0xe3 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (227 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_wide_quick: /* 0xe4 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (228 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_object_quick: /* 0xe5 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (229 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_quick: /* 0xe6 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (230 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_wide_quick: /* 0xe7 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (231 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_object_quick: /* 0xe8 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (232 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual_quick: /* 0xe9 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (233 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual_range_quick: /* 0xea */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (234 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_boolean_quick: /* 0xeb */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (235 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_byte_quick: /* 0xec */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (236 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_char_quick: /* 0xed */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (237 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_short_quick: /* 0xee */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (238 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_boolean_quick: /* 0xef */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (239 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_byte_quick: /* 0xf0 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (240 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_char_quick: /* 0xf1 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (241 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_short_quick: /* 0xf2 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (242 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f3: /* 0xf3 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (243 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f4: /* 0xf4 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (244 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f5: /* 0xf5 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (245 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f6: /* 0xf6 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (246 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f7: /* 0xf7 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (247 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f8: /* 0xf8 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (248 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f9: /* 0xf9 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (249 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_polymorphic: /* 0xfa */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (250 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_polymorphic_range: /* 0xfb */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (251 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_custom: /* 0xfc */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (252 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_custom_range: /* 0xfd */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (253 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_method_handle: /* 0xfe */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (254 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_method_type: /* 0xff */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (255 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - - .balign 128 - - .global artMterpAsmAltInstructionEnd -artMterpAsmAltInstructionEnd: - -/* - * We've detected a condition that will result in an exception, but the exception - * has not yet been thrown. Just bail out to the reference interpreter to deal with it. - * TUNING: for consistency, we may want to just go ahead and handle these here. - */ - - .extern MterpLogDivideByZeroException -common_errDivideByZero: - EXPORT_PC -#if MTERP_LOGGING - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - jal MterpLogDivideByZeroException -#endif - b MterpCommonFallback - - .extern MterpLogArrayIndexException -common_errArrayIndex: - EXPORT_PC -#if MTERP_LOGGING - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - jal MterpLogArrayIndexException -#endif - b MterpCommonFallback - - .extern MterpLogNullObjectException -common_errNullObject: - EXPORT_PC -#if MTERP_LOGGING - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - jal MterpLogNullObjectException -#endif - b MterpCommonFallback - -/* - * If we're here, something is out of the ordinary. If there is a pending - * exception, handle it. Otherwise, roll back and retry with the reference - * interpreter. - */ -MterpPossibleException: - ld a0, THREAD_EXCEPTION_OFFSET(rSELF) - beqzc a0, MterpFallback # If not, fall back to reference interpreter. - /* intentional fallthrough - handle pending exception. */ -/* - * On return from a runtime helper routine, we've found a pending exception. - * Can we handle it here - or need to bail out to caller? - * - */ - .extern MterpHandleException - .extern MterpShouldSwitchInterpreters -MterpException: - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - jal MterpHandleException # (self, shadow_frame) - beqzc v0, MterpExceptionReturn # no local catch, back to caller. - ld a0, OFF_FP_DEX_INSTRUCTIONS(rFP) - lwu a1, OFF_FP_DEX_PC(rFP) - REFRESH_IBASE - dlsa rPC, a1, a0, 1 # generate new dex_pc_ptr - /* Do we need to switch interpreters? */ - jal MterpShouldSwitchInterpreters - bnezc v0, MterpFallback - /* resume execution at catch block */ - EXPORT_PC - FETCH_INST - GET_INST_OPCODE v0 - GOTO_OPCODE v0 - /* NOTE: no fallthrough */ - -/* - * Common handling for branches with support for Jit profiling. - * On entry: - * rINST <= signed offset - * rPROFILE <= signed hotness countdown (expanded to 64 bits) - * - * We have quite a few different cases for branch profiling, OSR detection and - * suspend check support here. - * - * Taken backward branches: - * If profiling active, do hotness countdown and report if we hit zero. - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * Is there a pending suspend request? If so, suspend. - * - * Taken forward branches and not-taken backward branches: - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * - * Our most common case is expected to be a taken backward branch with active jit profiling, - * but no full OSR check and no pending suspend request. - * Next most common case is not-taken branch with no full OSR check. - * - */ -MterpCommonTakenBranchNoFlags: - bgtzc rINST, .L_forward_branch # don't add forward branches to hotness -/* - * We need to subtract 1 from positive values and we should not see 0 here, - * so we may use the result of the comparison with -1. - */ - li v0, JIT_CHECK_OSR - beqc rPROFILE, v0, .L_osr_check - bltc rPROFILE, v0, .L_resume_backward_branch - dsubu rPROFILE, 1 - beqzc rPROFILE, .L_add_batch # counted down to zero - report -.L_resume_backward_branch: - lw ra, THREAD_FLAGS_OFFSET(rSELF) - REFRESH_IBASE - daddu a2, rINST, rINST # a2<- byte offset - FETCH_ADVANCE_INST_RB a2 # update rPC, load rINST - and ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - bnezc ra, .L_suspend_request_pending - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -.L_suspend_request_pending: - EXPORT_PC - move a0, rSELF - jal MterpSuspendCheck # (self) - bnezc v0, MterpFallback - REFRESH_IBASE # might have changed during suspend - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -.L_no_count_backwards: - li v0, JIT_CHECK_OSR # check for possible OSR re-entry - bnec rPROFILE, v0, .L_resume_backward_branch -.L_osr_check: - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rINST - EXPORT_PC - jal MterpMaybeDoOnStackReplacement # (self, shadow_frame, offset) - bnezc v0, MterpOnStackReplacement - b .L_resume_backward_branch - -.L_forward_branch: - li v0, JIT_CHECK_OSR # check for possible OSR re-entry - beqc rPROFILE, v0, .L_check_osr_forward -.L_resume_forward_branch: - daddu a2, rINST, rINST # a2<- byte offset - FETCH_ADVANCE_INST_RB a2 # update rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -.L_check_osr_forward: - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rINST - EXPORT_PC - jal MterpMaybeDoOnStackReplacement # (self, shadow_frame, offset) - bnezc v0, MterpOnStackReplacement - b .L_resume_forward_branch - -.L_add_batch: - daddu a1, rFP, OFF_FP_SHADOWFRAME - sh rPROFILE, SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET(a1) - ld a0, OFF_FP_METHOD(rFP) - move a2, rSELF - jal MterpAddHotnessBatch # (method, shadow_frame, self) - move rPROFILE, v0 # restore new hotness countdown to rPROFILE - b .L_no_count_backwards - -/* - * Entered from the conditional branch handlers when OSR check request active on - * not-taken path. All Dalvik not-taken conditional branch offsets are 2. - */ -.L_check_not_taken_osr: - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - li a2, 2 - EXPORT_PC - jal MterpMaybeDoOnStackReplacement # (self, shadow_frame, offset) - bnezc v0, MterpOnStackReplacement - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* - * On-stack replacement has happened, and now we've returned from the compiled method. - */ -MterpOnStackReplacement: -#if MTERP_LOGGING - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rINST # rINST contains offset - jal MterpLogOSR -#endif - li v0, 1 # Signal normal return - b MterpDone - -/* - * Bail out to reference interpreter. - */ - .extern MterpLogFallback -MterpFallback: - EXPORT_PC -#if MTERP_LOGGING - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - jal MterpLogFallback -#endif -MterpCommonFallback: - li v0, 0 # signal retry with reference interpreter. - b MterpDone - -/* - * We pushed some registers on the stack in ExecuteMterpImpl, then saved - * SP and RA. Here we restore SP, restore the registers, and then restore - * RA to PC. - * - * On entry: - * uint32_t* rFP (should still be live, pointer to base of vregs) - */ -MterpExceptionReturn: - li v0, 1 # signal return to caller. - b MterpDone -/* - * Returned value is expected in a0 and if it's not 64-bit, the 32 most - * significant bits of a0 must be zero-extended or sign-extended - * depending on the return type. - */ -MterpReturn: - ld a2, OFF_FP_RESULT_REGISTER(rFP) - sd a0, 0(a2) - li v0, 1 # signal return to caller. -MterpDone: -/* - * At this point, we expect rPROFILE to be non-zero. If negative, hotness is disabled or we're - * checking for OSR. If greater than zero, we might have unreported hotness to register - * (the difference between the ending rPROFILE and the cached hotness counter). rPROFILE - * should only reach zero immediately after a hotness decrement, and is then reset to either - * a negative special state or the new non-zero countdown value. - */ - blez rPROFILE, .L_pop_and_return # if > 0, we may have some counts to report. - -MterpProfileActive: - move rINST, v0 # stash return value - /* Report cached hotness counts */ - ld a0, OFF_FP_METHOD(rFP) - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rSELF - sh rPROFILE, SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET(a1) - jal MterpAddHotnessBatch # (method, shadow_frame, self) - move v0, rINST # restore return value - -.L_pop_and_return: - ld s6, STACK_OFFSET_S6(sp) - .cfi_restore 22 - ld s5, STACK_OFFSET_S5(sp) - .cfi_restore 21 - ld s4, STACK_OFFSET_S4(sp) - .cfi_restore 20 - ld s3, STACK_OFFSET_S3(sp) - .cfi_restore 19 - ld s2, STACK_OFFSET_S2(sp) - .cfi_restore 18 - ld s1, STACK_OFFSET_S1(sp) - .cfi_restore 17 - ld s0, STACK_OFFSET_S0(sp) - .cfi_restore 16 - - ld ra, STACK_OFFSET_RA(sp) - .cfi_restore 31 - - ld t8, STACK_OFFSET_GP(sp) - .cpreturn - .cfi_restore 28 - - .set noreorder - jr ra - daddu sp, sp, STACK_SIZE - .cfi_adjust_cfa_offset -STACK_SIZE - - .cfi_endproc - .set reorder - .size ExecuteMterpImpl, .-ExecuteMterpImpl - diff --git a/runtime/interpreter/mterp/out/mterp_x86.S b/runtime/interpreter/mterp/out/mterp_x86.S deleted file mode 100644 index e2793ba2bf..0000000000 --- a/runtime/interpreter/mterp/out/mterp_x86.S +++ /dev/null @@ -1,11889 +0,0 @@ -/* DO NOT EDIT: This file was generated by gen-mterp.py. */ -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - Art assembly interpreter notes: - - First validate assembly code by implementing ExecuteXXXImpl() style body (doesn't - handle invoke, allows higher-level code to create frame & shadow frame. - - Once that's working, support direct entry code & eliminate shadow frame (and - excess locals allocation. - - Some (hopefully) temporary ugliness. We'll treat rFP as pointing to the - base of the vreg array within the shadow frame. Access the other fields, - dex_pc_, method_ and number_of_vregs_ via negative offsets. For now, we'll continue - the shadow frame mechanism of double-storing object references - via rFP & - number_of_vregs_. - - */ - -/* -x86 ABI general notes: - -Caller save set: - eax, edx, ecx, st(0)-st(7) -Callee save set: - ebx, esi, edi, ebp -Return regs: - 32-bit in eax - 64-bit in edx:eax (low-order 32 in eax) - fp on top of fp stack st(0) - -Parameters passed on stack, pushed right-to-left. On entry to target, first -parm is at 4(%esp). Traditional entry code is: - -functEntry: - push %ebp # save old frame pointer - mov %ebp,%esp # establish new frame pointer - sub FrameSize,%esp # Allocate storage for spill, locals & outs - -Once past the prologue, arguments are referenced at ((argno + 2)*4)(%ebp) - -Stack must be 16-byte aligned to support SSE in native code. - -If we're not doing variable stack allocation (alloca), the frame pointer can be -eliminated and all arg references adjusted to be esp relative. -*/ - -/* -Mterp and x86 notes: - -Some key interpreter variables will be assigned to registers. - - nick reg purpose - rPC esi interpreted program counter, used for fetching instructions - rFP edi interpreted frame pointer, used for accessing locals and args - rINSTw bx first 16-bit code of current instruction - rINSTbl bl opcode portion of instruction word - rINSTbh bh high byte of inst word, usually contains src/tgt reg names - rIBASE edx base of instruction handler table - rREFS ebp base of object references in shadow frame. - -Notes: - o High order 16 bits of ebx must be zero on entry to handler - o rPC, rFP, rINSTw/rINSTbl valid on handler entry and exit - o eax and ecx are scratch, rINSTw/ebx sometimes scratch - -Macros are provided for common operations. Each macro MUST emit only -one instruction to make instruction-counting easier. They MUST NOT alter -unspecified registers or condition codes. -*/ - -/* - * This is a #include, not a %include, because we want the C pre-processor - * to expand the macros into assembler assignment statements. - */ -#include "asm_support.h" -#include "interpreter/cfi_asm_support.h" - -/* - * Handle mac compiler specific - */ -#if defined(__APPLE__) - #define MACRO_LITERAL(value) $(value) - #define FUNCTION_TYPE(name) - #define OBJECT_TYPE(name) - #define SIZE(start,end) - // Mac OS' symbols have an _ prefix. - #define SYMBOL(name) _ ## name - #define ASM_HIDDEN .private_extern -#else - #define MACRO_LITERAL(value) $value - #define FUNCTION_TYPE(name) .type name, @function - #define OBJECT_TYPE(name) .type name, @object - #define SIZE(start,end) .size start, .-end - #define SYMBOL(name) name - #define ASM_HIDDEN .hidden -#endif - -.macro PUSH _reg - pushl \_reg - .cfi_adjust_cfa_offset 4 - .cfi_rel_offset \_reg, 0 -.endm - -.macro POP _reg - popl \_reg - .cfi_adjust_cfa_offset -4 - .cfi_restore \_reg -.endm - -/* - * Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs. So, - * to access other shadow frame fields, we need to use a backwards offset. Define those here. - */ -#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) -#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) -#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) -#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) -#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) -#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) -#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) -#define OFF_FP_DEX_INSTRUCTIONS OFF_FP(SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET) -#define OFF_FP_COUNTDOWN_OFFSET OFF_FP(SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET) -#define OFF_FP_SHADOWFRAME OFF_FP(0) - -/* Frame size must be 16-byte aligned. - * Remember about 4 bytes for return address + 4 * 4 for spills - */ -#define FRAME_SIZE 28 - -/* Frame diagram while executing ExecuteMterpImpl, high to low addresses */ -#define IN_ARG3 (FRAME_SIZE + 16 + 16) -#define IN_ARG2 (FRAME_SIZE + 16 + 12) -#define IN_ARG1 (FRAME_SIZE + 16 + 8) -#define IN_ARG0 (FRAME_SIZE + 16 + 4) -/* Spill offsets relative to %esp */ -#define LOCAL0 (FRAME_SIZE - 4) -#define LOCAL1 (FRAME_SIZE - 8) -#define LOCAL2 (FRAME_SIZE - 12) -/* Out Arg offsets, relative to %esp */ -#define OUT_ARG3 ( 12) -#define OUT_ARG2 ( 8) -#define OUT_ARG1 ( 4) -#define OUT_ARG0 ( 0) /* <- ExecuteMterpImpl esp + 0 */ - -/* During bringup, we'll use the shadow frame model instead of rFP */ -/* single-purpose registers, given names for clarity */ -#define rSELF IN_ARG0(%esp) -#define rPC %esi -#define CFI_DEX 6 // DWARF register number of the register holding dex-pc (esi). -#define CFI_TMP 0 // DWARF register number of the first argument register (eax). -#define rFP %edi -#define rINST %ebx -#define rINSTw %bx -#define rINSTbh %bh -#define rINSTbl %bl -#define rIBASE %edx -#define rREFS %ebp -#define rPROFILE OFF_FP_COUNTDOWN_OFFSET(rFP) - -#define MTERP_LOGGING 0 - -/* - * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must - * be done *before* something throws. - * - * It's okay to do this more than once. - * - * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped - * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction - * offset into the code_items_[] array. For effiency, we will "export" the - * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC - * to convert to a dex pc when needed. - */ -.macro EXPORT_PC - movl rPC, OFF_FP_DEX_PC_PTR(rFP) -.endm - -/* - * Refresh handler table. - */ -.macro REFRESH_IBASE - movl rSELF, rIBASE - movl THREAD_CURRENT_IBASE_OFFSET(rIBASE), rIBASE -.endm - -/* - * Refresh handler table. - * IBase handles uses the caller save register so we must restore it after each call. - * Also it is used as a result of some 64-bit operations (like imul) and we should - * restore it in such cases also. - * - * TODO: Consider spilling the IBase instead of restoring it from Thread structure. - */ -.macro RESTORE_IBASE - movl rSELF, rIBASE - movl THREAD_CURRENT_IBASE_OFFSET(rIBASE), rIBASE -.endm - -/* - * If rSELF is already loaded then we can use it from known reg. - */ -.macro RESTORE_IBASE_FROM_SELF _reg - movl THREAD_CURRENT_IBASE_OFFSET(\_reg), rIBASE -.endm - -/* - * Refresh rINST. - * At enter to handler rINST does not contain the opcode number. - * However some utilities require the full value, so this macro - * restores the opcode number. - */ -.macro REFRESH_INST _opnum - movb rINSTbl, rINSTbh - movb MACRO_LITERAL(\_opnum), rINSTbl -.endm - -/* - * Fetch the next instruction from rPC into rINSTw. Does not advance rPC. - */ -.macro FETCH_INST - movzwl (rPC), rINST -.endm - -/* - * Remove opcode from rINST, compute the address of handler and jump to it. - */ -.macro GOTO_NEXT - movzx rINSTbl,%eax - movzbl rINSTbh,rINST - shll MACRO_LITERAL(7), %eax - addl rIBASE, %eax - jmp *%eax -.endm - -/* - * Advance rPC by instruction count. - */ -.macro ADVANCE_PC _count - leal 2*\_count(rPC), rPC -.endm - -/* - * Advance rPC by instruction count, fetch instruction and jump to handler. - */ -.macro ADVANCE_PC_FETCH_AND_GOTO_NEXT _count - ADVANCE_PC \_count - FETCH_INST - GOTO_NEXT -.endm - -/* - * Get/set the 32-bit value from a Dalvik register. - */ -#define VREG_ADDRESS(_vreg) (rFP,_vreg,4) -#define VREG_HIGH_ADDRESS(_vreg) 4(rFP,_vreg,4) -#define VREG_REF_ADDRESS(_vreg) (rREFS,_vreg,4) -#define VREG_REF_HIGH_ADDRESS(_vreg) 4(rREFS,_vreg,4) - -.macro GET_VREG _reg _vreg - movl (rFP,\_vreg,4), \_reg -.endm - -/* Read wide value to xmm. */ -.macro GET_WIDE_FP_VREG _reg _vreg - movq (rFP,\_vreg,4), \_reg -.endm - -.macro SET_VREG _reg _vreg - movl \_reg, (rFP,\_vreg,4) - movl MACRO_LITERAL(0), (rREFS,\_vreg,4) -.endm - -/* Write wide value from xmm. xmm is clobbered. */ -.macro SET_WIDE_FP_VREG _reg _vreg - movq \_reg, (rFP,\_vreg,4) - pxor \_reg, \_reg - movq \_reg, (rREFS,\_vreg,4) -.endm - -.macro SET_VREG_OBJECT _reg _vreg - movl \_reg, (rFP,\_vreg,4) - movl \_reg, (rREFS,\_vreg,4) -.endm - -.macro GET_VREG_HIGH _reg _vreg - movl 4(rFP,\_vreg,4), \_reg -.endm - -.macro SET_VREG_HIGH _reg _vreg - movl \_reg, 4(rFP,\_vreg,4) - movl MACRO_LITERAL(0), 4(rREFS,\_vreg,4) -.endm - -.macro CLEAR_REF _vreg - movl MACRO_LITERAL(0), (rREFS,\_vreg,4) -.endm - -.macro CLEAR_WIDE_REF _vreg - movl MACRO_LITERAL(0), (rREFS,\_vreg,4) - movl MACRO_LITERAL(0), 4(rREFS,\_vreg,4) -.endm - -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -/* - * Interpreter entry point. - */ - - .text - ASM_HIDDEN SYMBOL(ExecuteMterpImpl) - .global SYMBOL(ExecuteMterpImpl) - FUNCTION_TYPE(ExecuteMterpImpl) - -/* - * On entry: - * 0 Thread* self - * 1 insns_ - * 2 ShadowFrame - * 3 JValue* result_register - * - */ - -SYMBOL(ExecuteMterpImpl): - .cfi_startproc - .cfi_def_cfa esp, 4 - - /* Spill callee save regs */ - PUSH %ebp - PUSH %edi - PUSH %esi - PUSH %ebx - - /* Allocate frame */ - subl $FRAME_SIZE, %esp - .cfi_adjust_cfa_offset FRAME_SIZE - - /* Load ShadowFrame pointer */ - movl IN_ARG2(%esp), %edx - - /* Remember the return register */ - movl IN_ARG3(%esp), %eax - movl %eax, SHADOWFRAME_RESULT_REGISTER_OFFSET(%edx) - - /* Remember the code_item */ - movl IN_ARG1(%esp), %ecx - movl %ecx, SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET(%edx) - - /* set up "named" registers */ - movl SHADOWFRAME_NUMBER_OF_VREGS_OFFSET(%edx), %eax - leal SHADOWFRAME_VREGS_OFFSET(%edx), rFP - leal (rFP, %eax, 4), rREFS - movl SHADOWFRAME_DEX_PC_OFFSET(%edx), %eax - lea (%ecx, %eax, 2), rPC - CFI_DEFINE_DEX_PC_WITH_OFFSET(CFI_TMP, CFI_DEX, 0) - EXPORT_PC - - /* Set up for backwards branches & osr profiling */ - movl OFF_FP_METHOD(rFP), %eax - movl %eax, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - movl rSELF, %eax - movl %eax, OUT_ARG2(%esp) - call SYMBOL(MterpSetUpHotnessCountdown) - - /* Starting ibase */ - REFRESH_IBASE - - /* start executing the instruction at rPC */ - FETCH_INST - GOTO_NEXT - /* NOTE: no fallthrough */ - - OBJECT_TYPE(artMterpAsmInstructionStart) - ASM_HIDDEN SYMBOL(artMterpAsmInstructionStart) - .global SYMBOL(artMterpAsmInstructionStart) -SYMBOL(artMterpAsmInstructionStart) = .L_op_nop - .text - -/* ------------------------------ */ - .balign 128 -.L_op_nop: /* 0x00 */ - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_move: /* 0x01 */ - /* for move, move-object, long-to-int */ - /* op vA, vB */ - movzbl rINSTbl, %eax # eax <- BA - andb $0xf, %al # eax <- A - shrl $4, rINST # rINST <- B - GET_VREG rINST, rINST - .if 0 - SET_VREG_OBJECT rINST, %eax # fp[A] <- fp[B] - .else - SET_VREG rINST, %eax # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_move_from16: /* 0x02 */ - /* for: move/from16, move-object/from16 */ - /* op vAA, vBBBB */ - movzx rINSTbl, %eax # eax <- AA - movw 2(rPC), rINSTw # rINSTw <- BBBB - GET_VREG rINST, rINST # rINST <- fp[BBBB] - .if 0 - SET_VREG_OBJECT rINST, %eax # fp[A] <- fp[B] - .else - SET_VREG rINST, %eax # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_move_16: /* 0x03 */ - /* for: move/16, move-object/16 */ - /* op vAAAA, vBBBB */ - movzwl 4(rPC), %ecx # ecx <- BBBB - movzwl 2(rPC), %eax # eax <- AAAA - GET_VREG rINST, %ecx - .if 0 - SET_VREG_OBJECT rINST, %eax # fp[A] <- fp[B] - .else - SET_VREG rINST, %eax # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 - -/* ------------------------------ */ - .balign 128 -.L_op_move_wide: /* 0x04 */ - /* move-wide vA, vB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - GET_WIDE_FP_VREG %xmm0, rINST # xmm0 <- v[B] - SET_WIDE_FP_VREG %xmm0, %ecx # v[A] <- xmm0 - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_move_wide_from16: /* 0x05 */ - /* move-wide/from16 vAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - movzwl 2(rPC), %ecx # ecx <- BBBB - movzbl rINSTbl, %eax # eax <- AAAA - GET_WIDE_FP_VREG %xmm0, %ecx # xmm0 <- v[B] - SET_WIDE_FP_VREG %xmm0, %eax # v[A] <- xmm0 - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_move_wide_16: /* 0x06 */ - /* move-wide/16 vAAAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - movzwl 4(rPC), %ecx # ecx<- BBBB - movzwl 2(rPC), %eax # eax<- AAAA - GET_WIDE_FP_VREG %xmm0, %ecx # xmm0 <- v[B] - SET_WIDE_FP_VREG %xmm0, %eax # v[A] <- xmm0 - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 - -/* ------------------------------ */ - .balign 128 -.L_op_move_object: /* 0x07 */ - /* for move, move-object, long-to-int */ - /* op vA, vB */ - movzbl rINSTbl, %eax # eax <- BA - andb $0xf, %al # eax <- A - shrl $4, rINST # rINST <- B - GET_VREG rINST, rINST - .if 1 - SET_VREG_OBJECT rINST, %eax # fp[A] <- fp[B] - .else - SET_VREG rINST, %eax # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_move_object_from16: /* 0x08 */ - /* for: move/from16, move-object/from16 */ - /* op vAA, vBBBB */ - movzx rINSTbl, %eax # eax <- AA - movw 2(rPC), rINSTw # rINSTw <- BBBB - GET_VREG rINST, rINST # rINST <- fp[BBBB] - .if 1 - SET_VREG_OBJECT rINST, %eax # fp[A] <- fp[B] - .else - SET_VREG rINST, %eax # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_move_object_16: /* 0x09 */ - /* for: move/16, move-object/16 */ - /* op vAAAA, vBBBB */ - movzwl 4(rPC), %ecx # ecx <- BBBB - movzwl 2(rPC), %eax # eax <- AAAA - GET_VREG rINST, %ecx - .if 1 - SET_VREG_OBJECT rINST, %eax # fp[A] <- fp[B] - .else - SET_VREG rINST, %eax # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 - -/* ------------------------------ */ - .balign 128 -.L_op_move_result: /* 0x0a */ - /* for: move-result, move-result-object */ - /* op vAA */ - movl OFF_FP_RESULT_REGISTER(rFP), %eax # get pointer to result JType. - movl (%eax), %eax # r0 <- result.i. - .if 0 - SET_VREG_OBJECT %eax, rINST # fp[A] <- fp[B] - .else - SET_VREG %eax, rINST # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_move_result_wide: /* 0x0b */ - /* move-result-wide vAA */ - movl OFF_FP_RESULT_REGISTER(rFP), %eax # get pointer to result JType. - movl 4(%eax), %ecx # Get high - movl (%eax), %eax # Get low - SET_VREG %eax, rINST # v[AA+0] <- eax - SET_VREG_HIGH %ecx, rINST # v[AA+1] <- ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_move_result_object: /* 0x0c */ - /* for: move-result, move-result-object */ - /* op vAA */ - movl OFF_FP_RESULT_REGISTER(rFP), %eax # get pointer to result JType. - movl (%eax), %eax # r0 <- result.i. - .if 1 - SET_VREG_OBJECT %eax, rINST # fp[A] <- fp[B] - .else - SET_VREG %eax, rINST # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_move_exception: /* 0x0d */ - /* move-exception vAA */ - movl rSELF, %ecx - movl THREAD_EXCEPTION_OFFSET(%ecx), %eax - SET_VREG_OBJECT %eax, rINST # fp[AA] <- exception object - movl $0, THREAD_EXCEPTION_OFFSET(%ecx) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_return_void: /* 0x0e */ - .extern MterpThreadFenceForConstructor - call SYMBOL(MterpThreadFenceForConstructor) - movl rSELF, %eax - testl $(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(%eax) - jz 1f - movl %eax, OUT_ARG0(%esp) - call SYMBOL(MterpSuspendCheck) -1: - xorl %eax, %eax - xorl %ecx, %ecx - jmp MterpReturn - -/* ------------------------------ */ - .balign 128 -.L_op_return: /* 0x0f */ -/* - * Return a 32-bit value. - * - * for: return, return-object - */ - /* op vAA */ - .extern MterpThreadFenceForConstructor - call SYMBOL(MterpThreadFenceForConstructor) - movl rSELF, %eax - testl $(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(%eax) - jz 1f - movl %eax, OUT_ARG0(%esp) - call SYMBOL(MterpSuspendCheck) -1: - GET_VREG %eax, rINST # eax <- vAA - xorl %ecx, %ecx - jmp MterpReturn - -/* ------------------------------ */ - .balign 128 -.L_op_return_wide: /* 0x10 */ -/* - * Return a 64-bit value. - */ - /* return-wide vAA */ - .extern MterpThreadFenceForConstructor - call SYMBOL(MterpThreadFenceForConstructor) - movl rSELF, %eax - testl $(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(%eax) - jz 1f - movl %eax, OUT_ARG0(%esp) - call SYMBOL(MterpSuspendCheck) -1: - GET_VREG %eax, rINST # eax <- v[AA+0] - GET_VREG_HIGH %ecx, rINST # ecx <- v[AA+1] - jmp MterpReturn - -/* ------------------------------ */ - .balign 128 -.L_op_return_object: /* 0x11 */ -/* - * Return a 32-bit value. - * - * for: return, return-object - */ - /* op vAA */ - .extern MterpThreadFenceForConstructor - call SYMBOL(MterpThreadFenceForConstructor) - movl rSELF, %eax - testl $(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(%eax) - jz 1f - movl %eax, OUT_ARG0(%esp) - call SYMBOL(MterpSuspendCheck) -1: - GET_VREG %eax, rINST # eax <- vAA - xorl %ecx, %ecx - jmp MterpReturn - -/* ------------------------------ */ - .balign 128 -.L_op_const_4: /* 0x12 */ - /* const/4 vA, #+B */ - movsx rINSTbl, %eax # eax <-ssssssBx - movl $0xf, rINST - andl %eax, rINST # rINST <- A - sarl $4, %eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_const_16: /* 0x13 */ - /* const/16 vAA, #+BBBB */ - movswl 2(rPC), %ecx # ecx <- ssssBBBB - SET_VREG %ecx, rINST # vAA <- ssssBBBB - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_const: /* 0x14 */ - /* const vAA, #+BBBBbbbb */ - movl 2(rPC), %eax # grab all 32 bits at once - SET_VREG %eax, rINST # vAA<- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 - -/* ------------------------------ */ - .balign 128 -.L_op_const_high16: /* 0x15 */ - /* const/high16 vAA, #+BBBB0000 */ - movzwl 2(rPC), %eax # eax <- 0000BBBB - sall $16, %eax # eax <- BBBB0000 - SET_VREG %eax, rINST # vAA <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_const_wide_16: /* 0x16 */ - /* const-wide/16 vAA, #+BBBB */ - movswl 2(rPC), %eax # eax <- ssssBBBB - movl rIBASE, %ecx # preserve rIBASE (cltd trashes it) - cltd # rIBASE:eax <- ssssssssssssBBBB - SET_VREG_HIGH rIBASE, rINST # store msw - SET_VREG %eax, rINST # store lsw - movl %ecx, rIBASE # restore rIBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_const_wide_32: /* 0x17 */ - /* const-wide/32 vAA, #+BBBBbbbb */ - movl 2(rPC), %eax # eax <- BBBBbbbb - movl rIBASE, %ecx # preserve rIBASE (cltd trashes it) - cltd # rIBASE:eax <- ssssssssssssBBBB - SET_VREG_HIGH rIBASE, rINST # store msw - SET_VREG %eax, rINST # store lsw - movl %ecx, rIBASE # restore rIBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 - -/* ------------------------------ */ - .balign 128 -.L_op_const_wide: /* 0x18 */ - /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ - movl 2(rPC), %eax # eax <- lsw - movzbl rINSTbl, %ecx # ecx <- AA - movl 6(rPC), rINST # rINST <- msw - SET_VREG %eax, %ecx - SET_VREG_HIGH rINST, %ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 5 - -/* ------------------------------ */ - .balign 128 -.L_op_const_wide_high16: /* 0x19 */ - /* const-wide/high16 vAA, #+BBBB000000000000 */ - movzwl 2(rPC), %eax # eax <- 0000BBBB - sall $16, %eax # eax <- BBBB0000 - SET_VREG_HIGH %eax, rINST # v[AA+1] <- eax - xorl %eax, %eax - SET_VREG %eax, rINST # v[AA+0] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_const_string: /* 0x1a */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstString - EXPORT_PC - movzwl 2(rPC), %eax # eax <- BBBB - movl %eax, OUT_ARG0(%esp) - movl rINST, OUT_ARG1(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) - call SYMBOL(MterpConstString) # (index, tgt_reg, shadow_frame, self) - RESTORE_IBASE - testb %al, %al - jnz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_const_string_jumbo: /* 0x1b */ - /* const/string vAA, String@BBBBBBBB */ - EXPORT_PC - movl 2(rPC), %eax # eax <- BBBB - movl %eax, OUT_ARG0(%esp) - movl rINST, OUT_ARG1(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) - call SYMBOL(MterpConstString) # (index, tgt_reg, shadow_frame, self) - RESTORE_IBASE - testb %al, %al - jnz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 - -/* ------------------------------ */ - .balign 128 -.L_op_const_class: /* 0x1c */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstClass - EXPORT_PC - movzwl 2(rPC), %eax # eax <- BBBB - movl %eax, OUT_ARG0(%esp) - movl rINST, OUT_ARG1(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) - call SYMBOL(MterpConstClass) # (index, tgt_reg, shadow_frame, self) - RESTORE_IBASE - testb %al, %al - jnz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_monitor_enter: /* 0x1d */ -/* - * Synchronize on an object. - */ - /* monitor-enter vAA */ - EXPORT_PC - GET_VREG %ecx, rINST - movl %ecx, OUT_ARG0(%esp) - movl rSELF, %eax - movl %eax, OUT_ARG1(%esp) - call SYMBOL(artLockObjectFromCode) # (object, self) - RESTORE_IBASE - testb %al, %al - jnz MterpException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_monitor_exit: /* 0x1e */ -/* - * Unlock an object. - * - * Exceptions that occur when unlocking a monitor need to appear as - * if they happened at the following instruction. See the Dalvik - * instruction spec. - */ - /* monitor-exit vAA */ - EXPORT_PC - GET_VREG %ecx, rINST - movl %ecx, OUT_ARG0(%esp) - movl rSELF, %eax - movl %eax, OUT_ARG1(%esp) - call SYMBOL(artUnlockObjectFromCode) # (object, self) - RESTORE_IBASE - testb %al, %al - jnz MterpException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_check_cast: /* 0x1f */ -/* - * Check to see if a cast from one class to another is allowed. - */ - /* check-cast vAA, class@BBBB */ - EXPORT_PC - movzwl 2(rPC), %eax # eax <- BBBB - movl %eax, OUT_ARG0(%esp) - leal VREG_ADDRESS(rINST), %ecx - movl %ecx, OUT_ARG1(%esp) - movl OFF_FP_METHOD(rFP),%eax - movl %eax, OUT_ARG2(%esp) - movl rSELF, %ecx - movl %ecx, OUT_ARG3(%esp) - call SYMBOL(MterpCheckCast) # (index, &obj, method, self) - RESTORE_IBASE - testb %al, %al - jnz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_instance_of: /* 0x20 */ -/* - * Check to see if an object reference is an instance of a class. - * - * Most common situation is a non-null object, being compared against - * an already-resolved class. - */ - /* instance-of vA, vB, class@CCCC */ - EXPORT_PC - movzwl 2(rPC), %eax # eax <- BBBB - movl %eax, OUT_ARG0(%esp) - movl rINST, %eax # eax <- BA - sarl $4, %eax # eax <- B - leal VREG_ADDRESS(%eax), %ecx # Get object address - movl %ecx, OUT_ARG1(%esp) - movl OFF_FP_METHOD(rFP),%eax - movl %eax, OUT_ARG2(%esp) - movl rSELF, %ecx - movl %ecx, OUT_ARG3(%esp) - call SYMBOL(MterpInstanceOf) # (index, &obj, method, self) - movl rSELF, %ecx - RESTORE_IBASE_FROM_SELF %ecx - cmpl $0, THREAD_EXCEPTION_OFFSET(%ecx) - jnz MterpException - andb $0xf, rINSTbl # rINSTbl <- A - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_array_length: /* 0x21 */ -/* - * Return the length of an array. - */ - mov rINST, %eax # eax <- BA - sarl $4, rINST # rINST <- B - GET_VREG %ecx, rINST # ecx <- vB (object ref) - testl %ecx, %ecx # is null? - je common_errNullObject - andb $0xf, %al # eax <- A - movl MIRROR_ARRAY_LENGTH_OFFSET(%ecx), rINST - SET_VREG rINST, %eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_new_instance: /* 0x22 */ -/* - * Create a new instance of a class. - */ - /* new-instance vAA, class@BBBB */ - EXPORT_PC - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG0(%esp) - movl rSELF, %ecx - movl %ecx, OUT_ARG1(%esp) - REFRESH_INST 34 - movl rINST, OUT_ARG2(%esp) - call SYMBOL(MterpNewInstance) - RESTORE_IBASE - testb %al, %al # 0 means an exception is thrown - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_new_array: /* 0x23 */ -/* - * Allocate an array of objects, specified with the array class - * and a count. - * - * The verifier guarantees that this is an array class, so we don't - * check for it here. - */ - /* new-array vA, vB, class@CCCC */ - EXPORT_PC - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG0(%esp) - movl rPC, OUT_ARG1(%esp) - REFRESH_INST 35 - movl rINST, OUT_ARG2(%esp) - movl rSELF, %ecx - movl %ecx, OUT_ARG3(%esp) - call SYMBOL(MterpNewArray) - RESTORE_IBASE - testb %al, %al # 0 means an exception is thrown - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_filled_new_array: /* 0x24 */ -/* - * Create a new array with elements filled from registers. - * - * for: filled-new-array, filled-new-array/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ - .extern MterpFilledNewArray - EXPORT_PC - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG0(%esp) - movl rPC, OUT_ARG1(%esp) - movl rSELF, %ecx - movl %ecx, OUT_ARG2(%esp) - call SYMBOL(MterpFilledNewArray) - REFRESH_IBASE - testb %al, %al # 0 means an exception is thrown - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 - -/* ------------------------------ */ - .balign 128 -.L_op_filled_new_array_range: /* 0x25 */ -/* - * Create a new array with elements filled from registers. - * - * for: filled-new-array, filled-new-array/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ - .extern MterpFilledNewArrayRange - EXPORT_PC - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG0(%esp) - movl rPC, OUT_ARG1(%esp) - movl rSELF, %ecx - movl %ecx, OUT_ARG2(%esp) - call SYMBOL(MterpFilledNewArrayRange) - REFRESH_IBASE - testb %al, %al # 0 means an exception is thrown - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 - -/* ------------------------------ */ - .balign 128 -.L_op_fill_array_data: /* 0x26 */ - /* fill-array-data vAA, +BBBBBBBB */ - EXPORT_PC - movl 2(rPC), %ecx # ecx <- BBBBbbbb - leal (rPC,%ecx,2), %ecx # ecx <- PC + BBBBbbbb*2 - GET_VREG %eax, rINST # eax <- vAA (array object) - movl %eax, OUT_ARG0(%esp) - movl %ecx, OUT_ARG1(%esp) - call SYMBOL(MterpFillArrayData) # (obj, payload) - REFRESH_IBASE - testb %al, %al # 0 means an exception is thrown - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 - -/* ------------------------------ */ - .balign 128 -.L_op_throw: /* 0x27 */ -/* - * Throw an exception object in the current thread. - */ - /* throw vAA */ - EXPORT_PC - GET_VREG %eax, rINST # eax<- vAA (exception object) - testl %eax, %eax - jz common_errNullObject - movl rSELF,%ecx - movl %eax, THREAD_EXCEPTION_OFFSET(%ecx) - jmp MterpException - -/* ------------------------------ */ - .balign 128 -.L_op_goto: /* 0x28 */ -/* - * Unconditional branch, 8-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto +AA */ - movsbl rINSTbl, rINST # rINST <- ssssssAA - testl rINST, rINST - jmp MterpCommonTakenBranch - -/* ------------------------------ */ - .balign 128 -.L_op_goto_16: /* 0x29 */ -/* - * Unconditional branch, 16-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto/16 +AAAA */ - movswl 2(rPC), rINST # rINST <- ssssAAAA - testl rINST, rINST - jmp MterpCommonTakenBranch - -/* ------------------------------ */ - .balign 128 -.L_op_goto_32: /* 0x2a */ -/* - * Unconditional branch, 32-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - * - * Unlike most opcodes, this one is allowed to branch to itself, so - * our "backward branch" test must be "<=0" instead of "<0". Because - * we need the V bit set, we'll use an adds to convert from Dalvik - * offset to byte offset. - */ - /* goto/32 +AAAAAAAA */ - movl 2(rPC), rINST # rINST <- AAAAAAAA - testl rINST, rINST - jmp MterpCommonTakenBranch - -/* ------------------------------ */ - .balign 128 -.L_op_packed_switch: /* 0x2b */ -/* - * Handle a packed-switch or sparse-switch instruction. In both cases - * we decode it and hand it off to a helper function. - * - * We don't really expect backward branches in a switch statement, but - * they're perfectly legal, so we check for them here. - * - * for: packed-switch, sparse-switch - */ - /* op vAA, +BBBB */ - movl 2(rPC), %ecx # ecx <- BBBBbbbb - GET_VREG %eax, rINST # eax <- vAA - leal (rPC,%ecx,2), %ecx # ecx <- PC + BBBBbbbb*2 - movl %eax, OUT_ARG1(%esp) # ARG1 <- vAA - movl %ecx, OUT_ARG0(%esp) # ARG0 <- switchData - call SYMBOL(MterpDoPackedSwitch) - REFRESH_IBASE - testl %eax, %eax - movl %eax, rINST - jmp MterpCommonTakenBranch - -/* ------------------------------ */ - .balign 128 -.L_op_sparse_switch: /* 0x2c */ -/* - * Handle a packed-switch or sparse-switch instruction. In both cases - * we decode it and hand it off to a helper function. - * - * We don't really expect backward branches in a switch statement, but - * they're perfectly legal, so we check for them here. - * - * for: packed-switch, sparse-switch - */ - /* op vAA, +BBBB */ - movl 2(rPC), %ecx # ecx <- BBBBbbbb - GET_VREG %eax, rINST # eax <- vAA - leal (rPC,%ecx,2), %ecx # ecx <- PC + BBBBbbbb*2 - movl %eax, OUT_ARG1(%esp) # ARG1 <- vAA - movl %ecx, OUT_ARG0(%esp) # ARG0 <- switchData - call SYMBOL(MterpDoSparseSwitch) - REFRESH_IBASE - testl %eax, %eax - movl %eax, rINST - jmp MterpCommonTakenBranch - -/* ------------------------------ */ - .balign 128 -.L_op_cmpl_float: /* 0x2d */ -/* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * int compare(x, y) { - * if (x == y) { - * return 0; - * } else if (x < y) { - * return -1; - * } else if (x > y) { - * return 1; - * } else { - * return nanval ? 1 : -1; - * } - * } - */ - /* op vAA, vBB, vCC */ - movzbl 3(rPC), %ecx # ecx<- CC - movzbl 2(rPC), %eax # eax<- BB - movss VREG_ADDRESS(%eax), %xmm0 - xor %eax, %eax - ucomiss VREG_ADDRESS(%ecx), %xmm0 - jp .Lop_cmpl_float_nan_is_neg - je .Lop_cmpl_float_finish - jb .Lop_cmpl_float_less -.Lop_cmpl_float_nan_is_pos: - incl %eax - jmp .Lop_cmpl_float_finish -.Lop_cmpl_float_nan_is_neg: -.Lop_cmpl_float_less: - decl %eax -.Lop_cmpl_float_finish: - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_cmpg_float: /* 0x2e */ -/* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * int compare(x, y) { - * if (x == y) { - * return 0; - * } else if (x < y) { - * return -1; - * } else if (x > y) { - * return 1; - * } else { - * return nanval ? 1 : -1; - * } - * } - */ - /* op vAA, vBB, vCC */ - movzbl 3(rPC), %ecx # ecx<- CC - movzbl 2(rPC), %eax # eax<- BB - movss VREG_ADDRESS(%eax), %xmm0 - xor %eax, %eax - ucomiss VREG_ADDRESS(%ecx), %xmm0 - jp .Lop_cmpg_float_nan_is_pos - je .Lop_cmpg_float_finish - jb .Lop_cmpg_float_less -.Lop_cmpg_float_nan_is_pos: - incl %eax - jmp .Lop_cmpg_float_finish -.Lop_cmpg_float_nan_is_neg: -.Lop_cmpg_float_less: - decl %eax -.Lop_cmpg_float_finish: - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_cmpl_double: /* 0x2f */ -/* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * int compare(x, y) { - * if (x == y) { - * return 0; - * } else if (x < y) { - * return -1; - * } else if (x > y) { - * return 1; - * } else { - * return nanval ? 1 : -1; - * } - * } - */ - /* op vAA, vBB, vCC */ - movzbl 3(rPC), %ecx # ecx<- CC - movzbl 2(rPC), %eax # eax<- BB - movsd VREG_ADDRESS(%eax), %xmm0 - xor %eax, %eax - ucomisd VREG_ADDRESS(%ecx), %xmm0 - jp .Lop_cmpl_double_nan_is_neg - je .Lop_cmpl_double_finish - jb .Lop_cmpl_double_less -.Lop_cmpl_double_nan_is_pos: - incl %eax - jmp .Lop_cmpl_double_finish -.Lop_cmpl_double_nan_is_neg: -.Lop_cmpl_double_less: - decl %eax -.Lop_cmpl_double_finish: - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_cmpg_double: /* 0x30 */ -/* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * int compare(x, y) { - * if (x == y) { - * return 0; - * } else if (x < y) { - * return -1; - * } else if (x > y) { - * return 1; - * } else { - * return nanval ? 1 : -1; - * } - * } - */ - /* op vAA, vBB, vCC */ - movzbl 3(rPC), %ecx # ecx<- CC - movzbl 2(rPC), %eax # eax<- BB - movsd VREG_ADDRESS(%eax), %xmm0 - xor %eax, %eax - ucomisd VREG_ADDRESS(%ecx), %xmm0 - jp .Lop_cmpg_double_nan_is_pos - je .Lop_cmpg_double_finish - jb .Lop_cmpg_double_less -.Lop_cmpg_double_nan_is_pos: - incl %eax - jmp .Lop_cmpg_double_finish -.Lop_cmpg_double_nan_is_neg: -.Lop_cmpg_double_less: - decl %eax -.Lop_cmpg_double_finish: - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_cmp_long: /* 0x31 */ -/* - * Compare two 64-bit values. Puts 0, 1, or -1 into the destination - * register based on the results of the comparison. - */ - /* cmp-long vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG_HIGH %eax, %eax # eax <- v[BB+1], BB is clobbered - cmpl VREG_HIGH_ADDRESS(%ecx), %eax - jl .Lop_cmp_long_smaller - jg .Lop_cmp_long_bigger - movzbl 2(rPC), %eax # eax <- BB, restore BB - GET_VREG %eax, %eax # eax <- v[BB] - sub VREG_ADDRESS(%ecx), %eax - ja .Lop_cmp_long_bigger - jb .Lop_cmp_long_smaller -.Lop_cmp_long_finish: - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -.Lop_cmp_long_bigger: - movl $1, %eax - jmp .Lop_cmp_long_finish - -.Lop_cmp_long_smaller: - movl $-1, %eax - jmp .Lop_cmp_long_finish - -/* ------------------------------ */ - .balign 128 -.L_op_if_eq: /* 0x32 */ -/* - * Generic two-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - movzx rINSTbl, %ecx # ecx <- A+ - andb $0xf, %cl # ecx <- A - GET_VREG %eax, %ecx # eax <- vA - sarl $4, rINST # rINST <- B - cmpl VREG_ADDRESS(rINST), %eax # compare (vA, vB) - jne 1f - movswl 2(rPC), rINST # Get signed branch offset - testl rINST, rINST - jmp MterpCommonTakenBranch -1: - cmpw $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_if_ne: /* 0x33 */ -/* - * Generic two-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - movzx rINSTbl, %ecx # ecx <- A+ - andb $0xf, %cl # ecx <- A - GET_VREG %eax, %ecx # eax <- vA - sarl $4, rINST # rINST <- B - cmpl VREG_ADDRESS(rINST), %eax # compare (vA, vB) - je 1f - movswl 2(rPC), rINST # Get signed branch offset - testl rINST, rINST - jmp MterpCommonTakenBranch -1: - cmpw $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_if_lt: /* 0x34 */ -/* - * Generic two-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - movzx rINSTbl, %ecx # ecx <- A+ - andb $0xf, %cl # ecx <- A - GET_VREG %eax, %ecx # eax <- vA - sarl $4, rINST # rINST <- B - cmpl VREG_ADDRESS(rINST), %eax # compare (vA, vB) - jge 1f - movswl 2(rPC), rINST # Get signed branch offset - testl rINST, rINST - jmp MterpCommonTakenBranch -1: - cmpw $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_if_ge: /* 0x35 */ -/* - * Generic two-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - movzx rINSTbl, %ecx # ecx <- A+ - andb $0xf, %cl # ecx <- A - GET_VREG %eax, %ecx # eax <- vA - sarl $4, rINST # rINST <- B - cmpl VREG_ADDRESS(rINST), %eax # compare (vA, vB) - jl 1f - movswl 2(rPC), rINST # Get signed branch offset - testl rINST, rINST - jmp MterpCommonTakenBranch -1: - cmpw $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_if_gt: /* 0x36 */ -/* - * Generic two-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - movzx rINSTbl, %ecx # ecx <- A+ - andb $0xf, %cl # ecx <- A - GET_VREG %eax, %ecx # eax <- vA - sarl $4, rINST # rINST <- B - cmpl VREG_ADDRESS(rINST), %eax # compare (vA, vB) - jle 1f - movswl 2(rPC), rINST # Get signed branch offset - testl rINST, rINST - jmp MterpCommonTakenBranch -1: - cmpw $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_if_le: /* 0x37 */ -/* - * Generic two-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - movzx rINSTbl, %ecx # ecx <- A+ - andb $0xf, %cl # ecx <- A - GET_VREG %eax, %ecx # eax <- vA - sarl $4, rINST # rINST <- B - cmpl VREG_ADDRESS(rINST), %eax # compare (vA, vB) - jg 1f - movswl 2(rPC), rINST # Get signed branch offset - testl rINST, rINST - jmp MterpCommonTakenBranch -1: - cmpw $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_if_eqz: /* 0x38 */ -/* - * Generic one-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - cmpl $0, VREG_ADDRESS(rINST) # compare (vA, 0) - jne 1f - movswl 2(rPC), rINST # fetch signed displacement - testl rINST, rINST - jmp MterpCommonTakenBranch -1: - cmpw $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_if_nez: /* 0x39 */ -/* - * Generic one-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - cmpl $0, VREG_ADDRESS(rINST) # compare (vA, 0) - je 1f - movswl 2(rPC), rINST # fetch signed displacement - testl rINST, rINST - jmp MterpCommonTakenBranch -1: - cmpw $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_if_ltz: /* 0x3a */ -/* - * Generic one-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - cmpl $0, VREG_ADDRESS(rINST) # compare (vA, 0) - jge 1f - movswl 2(rPC), rINST # fetch signed displacement - testl rINST, rINST - jmp MterpCommonTakenBranch -1: - cmpw $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_if_gez: /* 0x3b */ -/* - * Generic one-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - cmpl $0, VREG_ADDRESS(rINST) # compare (vA, 0) - jl 1f - movswl 2(rPC), rINST # fetch signed displacement - testl rINST, rINST - jmp MterpCommonTakenBranch -1: - cmpw $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_if_gtz: /* 0x3c */ -/* - * Generic one-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - cmpl $0, VREG_ADDRESS(rINST) # compare (vA, 0) - jle 1f - movswl 2(rPC), rINST # fetch signed displacement - testl rINST, rINST - jmp MterpCommonTakenBranch -1: - cmpw $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_if_lez: /* 0x3d */ -/* - * Generic one-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - cmpl $0, VREG_ADDRESS(rINST) # compare (vA, 0) - jg 1f - movswl 2(rPC), rINST # fetch signed displacement - testl rINST, rINST - jmp MterpCommonTakenBranch -1: - cmpw $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_unused_3e: /* 0x3e */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_3f: /* 0x3f */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_40: /* 0x40 */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_41: /* 0x41 */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_42: /* 0x42 */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_43: /* 0x43 */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_aget: /* 0x44 */ -/* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - */ - /* op vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB (array object) - GET_VREG %ecx, %ecx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - movl MIRROR_INT_ARRAY_DATA_OFFSET(%eax,%ecx,4), %eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_aget_wide: /* 0x45 */ -/* - * Array get, 64 bits. vAA <- vBB[vCC]. - */ - /* aget-wide vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB (array object) - GET_VREG %ecx, %ecx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - leal MIRROR_WIDE_ARRAY_DATA_OFFSET(%eax,%ecx,8), %eax - movq (%eax), %xmm0 # xmm0 <- vBB[vCC] - SET_WIDE_FP_VREG %xmm0, rINST # vAA <- xmm0 - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_aget_object: /* 0x46 */ -/* - * Array object get. vAA <- vBB[vCC]. - * - * for: aget-object - */ - /* op vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB (array object) - GET_VREG %ecx, %ecx # ecs <- vCC (requested index) - EXPORT_PC - movl %eax, OUT_ARG0(%esp) - movl %ecx, OUT_ARG1(%esp) - call SYMBOL(artAGetObjectFromMterp) # (array, index) - movl rSELF, %ecx - RESTORE_IBASE_FROM_SELF %ecx - cmpl $0, THREAD_EXCEPTION_OFFSET(%ecx) - jnz MterpException - SET_VREG_OBJECT %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_aget_boolean: /* 0x47 */ -/* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - */ - /* op vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB (array object) - GET_VREG %ecx, %ecx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - movzbl MIRROR_BOOLEAN_ARRAY_DATA_OFFSET(%eax,%ecx,1), %eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_aget_byte: /* 0x48 */ -/* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - */ - /* op vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB (array object) - GET_VREG %ecx, %ecx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - movsbl MIRROR_BYTE_ARRAY_DATA_OFFSET(%eax,%ecx,1), %eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_aget_char: /* 0x49 */ -/* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - */ - /* op vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB (array object) - GET_VREG %ecx, %ecx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - movzwl MIRROR_CHAR_ARRAY_DATA_OFFSET(%eax,%ecx,2), %eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_aget_short: /* 0x4a */ -/* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - */ - /* op vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB (array object) - GET_VREG %ecx, %ecx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - movswl MIRROR_SHORT_ARRAY_DATA_OFFSET(%eax,%ecx,2), %eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_aput: /* 0x4b */ -/* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - */ - /* op vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB (array object) - GET_VREG %ecx, %ecx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - leal MIRROR_INT_ARRAY_DATA_OFFSET(%eax,%ecx,4), %eax - GET_VREG rINST, rINST - movl rINST, (%eax) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_aput_wide: /* 0x4c */ -/* - * Array put, 64 bits. vBB[vCC] <- vAA. - * - */ - /* aput-wide vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB (array object) - GET_VREG %ecx, %ecx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - leal MIRROR_WIDE_ARRAY_DATA_OFFSET(%eax,%ecx,8), %eax - GET_WIDE_FP_VREG %xmm0, rINST # xmm0 <- vAA - movq %xmm0, (%eax) # vBB[vCC] <- xmm0 - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_aput_object: /* 0x4d */ -/* - * Store an object into an array. vBB[vCC] <- vAA. - */ - /* op vAA, vBB, vCC */ - EXPORT_PC - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG0(%esp) - movl rPC, OUT_ARG1(%esp) - REFRESH_INST 77 - movl rINST, OUT_ARG2(%esp) - call SYMBOL(MterpAputObject) # (array, index) - RESTORE_IBASE - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_aput_boolean: /* 0x4e */ -/* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - */ - /* op vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB (array object) - GET_VREG %ecx, %ecx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - leal MIRROR_BOOLEAN_ARRAY_DATA_OFFSET(%eax,%ecx,1), %eax - GET_VREG rINST, rINST - movb rINSTbl, (%eax) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_aput_byte: /* 0x4f */ -/* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - */ - /* op vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB (array object) - GET_VREG %ecx, %ecx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - leal MIRROR_BYTE_ARRAY_DATA_OFFSET(%eax,%ecx,1), %eax - GET_VREG rINST, rINST - movb rINSTbl, (%eax) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_aput_char: /* 0x50 */ -/* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - */ - /* op vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB (array object) - GET_VREG %ecx, %ecx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - leal MIRROR_CHAR_ARRAY_DATA_OFFSET(%eax,%ecx,2), %eax - GET_VREG rINST, rINST - movw rINSTw, (%eax) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_aput_short: /* 0x51 */ -/* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - */ - /* op vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB (array object) - GET_VREG %ecx, %ecx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - leal MIRROR_SHORT_ARRAY_DATA_OFFSET(%eax,%ecx,2), %eax - GET_VREG rINST, rINST - movw rINSTw, (%eax) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iget: /* 0x52 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetU32 - REFRESH_INST 82 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpIGetU32) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iget_wide: /* 0x53 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetU64 - REFRESH_INST 83 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpIGetU64) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iget_object: /* 0x54 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetObj - REFRESH_INST 84 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpIGetObj) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iget_boolean: /* 0x55 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetU8 - REFRESH_INST 85 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpIGetU8) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iget_byte: /* 0x56 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetI8 - REFRESH_INST 86 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpIGetI8) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iget_char: /* 0x57 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetU16 - REFRESH_INST 87 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpIGetU16) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iget_short: /* 0x58 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetI16 - REFRESH_INST 88 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpIGetI16) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iput: /* 0x59 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutU32 - REFRESH_INST 89 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpIPutU32) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iput_wide: /* 0x5a */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutU64 - REFRESH_INST 90 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpIPutU64) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iput_object: /* 0x5b */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutObj - REFRESH_INST 91 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpIPutObj) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iput_boolean: /* 0x5c */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutU8 - REFRESH_INST 92 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpIPutU8) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iput_byte: /* 0x5d */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutI8 - REFRESH_INST 93 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpIPutI8) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iput_char: /* 0x5e */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutU16 - REFRESH_INST 94 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpIPutU16) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iput_short: /* 0x5f */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutI16 - REFRESH_INST 95 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpIPutI16) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_sget: /* 0x60 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetU32 - REFRESH_INST 96 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpSGetU32) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_sget_wide: /* 0x61 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetU64 - REFRESH_INST 97 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpSGetU64) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_sget_object: /* 0x62 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetObj - REFRESH_INST 98 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpSGetObj) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_sget_boolean: /* 0x63 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetU8 - REFRESH_INST 99 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpSGetU8) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_sget_byte: /* 0x64 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetI8 - REFRESH_INST 100 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpSGetI8) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_sget_char: /* 0x65 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetU16 - REFRESH_INST 101 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpSGetU16) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_sget_short: /* 0x66 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetI16 - REFRESH_INST 102 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpSGetI16) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_sput: /* 0x67 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutU32 - REFRESH_INST 103 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpSPutU32) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_sput_wide: /* 0x68 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutU64 - REFRESH_INST 104 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpSPutU64) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_sput_object: /* 0x69 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutObj - REFRESH_INST 105 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpSPutObj) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_sput_boolean: /* 0x6a */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutU8 - REFRESH_INST 106 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpSPutU8) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_sput_byte: /* 0x6b */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutI8 - REFRESH_INST 107 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpSPutI8) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_sput_char: /* 0x6c */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutU16 - REFRESH_INST 108 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpSPutU16) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_sput_short: /* 0x6d */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutI16 - REFRESH_INST 109 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpSPutI16) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual: /* 0x6e */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtual - EXPORT_PC - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - REFRESH_INST 110 - movl rINST, OUT_ARG3(%esp) - call SYMBOL(MterpInvokeVirtual) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - RESTORE_IBASE - FETCH_INST - GOTO_NEXT - -/* - * Handle a virtual method call. - * - * for: invoke-virtual, invoke-virtual/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_super: /* 0x6f */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeSuper - EXPORT_PC - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - REFRESH_INST 111 - movl rINST, OUT_ARG3(%esp) - call SYMBOL(MterpInvokeSuper) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - RESTORE_IBASE - FETCH_INST - GOTO_NEXT - -/* - * Handle a "super" method call. - * - * for: invoke-super, invoke-super/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_direct: /* 0x70 */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeDirect - EXPORT_PC - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - REFRESH_INST 112 - movl rINST, OUT_ARG3(%esp) - call SYMBOL(MterpInvokeDirect) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - RESTORE_IBASE - FETCH_INST - GOTO_NEXT - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_static: /* 0x71 */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeStatic - EXPORT_PC - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - REFRESH_INST 113 - movl rINST, OUT_ARG3(%esp) - call SYMBOL(MterpInvokeStatic) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - RESTORE_IBASE - FETCH_INST - GOTO_NEXT - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_interface: /* 0x72 */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeInterface - EXPORT_PC - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - REFRESH_INST 114 - movl rINST, OUT_ARG3(%esp) - call SYMBOL(MterpInvokeInterface) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - RESTORE_IBASE - FETCH_INST - GOTO_NEXT - -/* - * Handle an interface method call. - * - * for: invoke-interface, invoke-interface/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - -/* ------------------------------ */ - .balign 128 -.L_op_return_void_no_barrier: /* 0x73 */ - movl rSELF, %eax - testl $(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(%eax) - jz 1f - movl %eax, OUT_ARG0(%esp) - call SYMBOL(MterpSuspendCheck) -1: - xorl %eax, %eax - xorl %ecx, %ecx - jmp MterpReturn - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual_range: /* 0x74 */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtualRange - EXPORT_PC - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - REFRESH_INST 116 - movl rINST, OUT_ARG3(%esp) - call SYMBOL(MterpInvokeVirtualRange) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - RESTORE_IBASE - FETCH_INST - GOTO_NEXT - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_super_range: /* 0x75 */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeSuperRange - EXPORT_PC - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - REFRESH_INST 117 - movl rINST, OUT_ARG3(%esp) - call SYMBOL(MterpInvokeSuperRange) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - RESTORE_IBASE - FETCH_INST - GOTO_NEXT - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_direct_range: /* 0x76 */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeDirectRange - EXPORT_PC - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - REFRESH_INST 118 - movl rINST, OUT_ARG3(%esp) - call SYMBOL(MterpInvokeDirectRange) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - RESTORE_IBASE - FETCH_INST - GOTO_NEXT - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_static_range: /* 0x77 */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeStaticRange - EXPORT_PC - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - REFRESH_INST 119 - movl rINST, OUT_ARG3(%esp) - call SYMBOL(MterpInvokeStaticRange) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - RESTORE_IBASE - FETCH_INST - GOTO_NEXT - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_interface_range: /* 0x78 */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeInterfaceRange - EXPORT_PC - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - REFRESH_INST 120 - movl rINST, OUT_ARG3(%esp) - call SYMBOL(MterpInvokeInterfaceRange) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - RESTORE_IBASE - FETCH_INST - GOTO_NEXT - -/* ------------------------------ */ - .balign 128 -.L_op_unused_79: /* 0x79 */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_7a: /* 0x7a */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_neg_int: /* 0x7b */ -/* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op eax". - */ - /* unop vA, vB */ - movzbl rINSTbl,%ecx # ecx <- A+ - sarl $4,rINST # rINST <- B - GET_VREG %eax, rINST # eax <- vB - andb $0xf,%cl # ecx <- A - negl %eax - SET_VREG %eax, %ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_not_int: /* 0x7c */ -/* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op eax". - */ - /* unop vA, vB */ - movzbl rINSTbl,%ecx # ecx <- A+ - sarl $4,rINST # rINST <- B - GET_VREG %eax, rINST # eax <- vB - andb $0xf,%cl # ecx <- A - notl %eax - SET_VREG %eax, %ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_neg_long: /* 0x7d */ - /* unop vA, vB */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $4, %ecx # ecx <- B - andb $0xf, rINSTbl # rINST <- A - GET_VREG %eax, %ecx # eax <- v[B+0] - GET_VREG_HIGH %ecx, %ecx # ecx <- v[B+1] - negl %eax - adcl $0, %ecx - negl %ecx - SET_VREG %eax, rINST # v[A+0] <- eax - SET_VREG_HIGH %ecx, rINST # v[A+1] <- ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_not_long: /* 0x7e */ - /* unop vA, vB */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $4, %ecx # ecx <- B - andb $0xf, rINSTbl # rINST <- A - GET_VREG %eax, %ecx # eax <- v[B+0] - GET_VREG_HIGH %ecx, %ecx # ecx <- v[B+1] - notl %eax - notl %ecx - SET_VREG %eax, rINST # v[A+0] <- eax - SET_VREG_HIGH %ecx, rINST # v[A+1] <- ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_neg_float: /* 0x7f */ -/* - * Generic 32-bit FP conversion operation. - */ - /* unop vA, vB */ - movzbl rINSTbl, %ecx # ecx <- A+ - sarl $4, rINST # rINST <- B - flds VREG_ADDRESS(rINST) # %st0 <- vB - andb $0xf, %cl # ecx <- A - fchs - fstps VREG_ADDRESS(%ecx) # vA <- %st0 - .if 0 - CLEAR_WIDE_REF %ecx - .else - CLEAR_REF %ecx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_neg_double: /* 0x80 */ -/* - * Generic 32-bit FP conversion operation. - */ - /* unop vA, vB */ - movzbl rINSTbl, %ecx # ecx <- A+ - sarl $4, rINST # rINST <- B - fldl VREG_ADDRESS(rINST) # %st0 <- vB - andb $0xf, %cl # ecx <- A - fchs - fstpl VREG_ADDRESS(%ecx) # vA <- %st0 - .if 1 - CLEAR_WIDE_REF %ecx - .else - CLEAR_REF %ecx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_long: /* 0x81 */ - /* int to long vA, vB */ - movzbl rINSTbl, %eax # eax <- +A - sarl $4, %eax # eax <- B - GET_VREG %eax, %eax # eax <- vB - andb $0xf, rINSTbl # rINST <- A - movl rIBASE, %ecx # cltd trashes rIBASE/edx - cltd # rINST:eax<- sssssssBBBBBBBB - SET_VREG_HIGH rIBASE, rINST # v[A+1] <- rIBASE - SET_VREG %eax, rINST # v[A+0] <- %eax - movl %ecx, rIBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_float: /* 0x82 */ -/* - * Generic 32-bit FP conversion operation. - */ - /* unop vA, vB */ - movzbl rINSTbl, %ecx # ecx <- A+ - sarl $4, rINST # rINST <- B - fildl VREG_ADDRESS(rINST) # %st0 <- vB - andb $0xf, %cl # ecx <- A - - fstps VREG_ADDRESS(%ecx) # vA <- %st0 - .if 0 - CLEAR_WIDE_REF %ecx - .else - CLEAR_REF %ecx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_double: /* 0x83 */ -/* - * Generic 32-bit FP conversion operation. - */ - /* unop vA, vB */ - movzbl rINSTbl, %ecx # ecx <- A+ - sarl $4, rINST # rINST <- B - fildl VREG_ADDRESS(rINST) # %st0 <- vB - andb $0xf, %cl # ecx <- A - - fstpl VREG_ADDRESS(%ecx) # vA <- %st0 - .if 1 - CLEAR_WIDE_REF %ecx - .else - CLEAR_REF %ecx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_long_to_int: /* 0x84 */ -/* we ignore the high word, making this equivalent to a 32-bit reg move */ - /* for move, move-object, long-to-int */ - /* op vA, vB */ - movzbl rINSTbl, %eax # eax <- BA - andb $0xf, %al # eax <- A - shrl $4, rINST # rINST <- B - GET_VREG rINST, rINST - .if 0 - SET_VREG_OBJECT rINST, %eax # fp[A] <- fp[B] - .else - SET_VREG rINST, %eax # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_long_to_float: /* 0x85 */ -/* - * Generic 32-bit FP conversion operation. - */ - /* unop vA, vB */ - movzbl rINSTbl, %ecx # ecx <- A+ - sarl $4, rINST # rINST <- B - fildll VREG_ADDRESS(rINST) # %st0 <- vB - andb $0xf, %cl # ecx <- A - - fstps VREG_ADDRESS(%ecx) # vA <- %st0 - .if 0 - CLEAR_WIDE_REF %ecx - .else - CLEAR_REF %ecx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_long_to_double: /* 0x86 */ -/* - * Generic 32-bit FP conversion operation. - */ - /* unop vA, vB */ - movzbl rINSTbl, %ecx # ecx <- A+ - sarl $4, rINST # rINST <- B - fildll VREG_ADDRESS(rINST) # %st0 <- vB - andb $0xf, %cl # ecx <- A - - fstpl VREG_ADDRESS(%ecx) # vA <- %st0 - .if 1 - CLEAR_WIDE_REF %ecx - .else - CLEAR_REF %ecx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_float_to_int: /* 0x87 */ -/* On fp to int conversions, Java requires that - * if the result > maxint, it should be clamped to maxint. If it is less - * than minint, it should be clamped to minint. If it is a nan, the result - * should be zero. Further, the rounding mode is to truncate. This model - * differs from what is delivered normally via the x86 fpu, so we have - * to play some games. - */ - /* float/double to int/long vA, vB */ - movzbl rINSTbl, %ecx # ecx <- A+ - sarl $4, rINST # rINST <- B - .if 0 - fldl VREG_ADDRESS(rINST) # %st0 <- vB - .else - flds VREG_ADDRESS(rINST) # %st0 <- vB - .endif - ftst - fnstcw LOCAL0(%esp) # remember original rounding mode - movzwl LOCAL0(%esp), %eax - movb $0xc, %ah - movw %ax, LOCAL0+2(%esp) - fldcw LOCAL0+2(%esp) # set "to zero" rounding mode - andb $0xf, %cl # ecx <- A - .if 0 - fistpll VREG_ADDRESS(%ecx) # convert and store - .else - fistpl VREG_ADDRESS(%ecx) # convert and store - .endif - fldcw LOCAL0(%esp) # restore previous rounding mode - .if 0 - movl $0x80000000, %eax - xorl VREG_HIGH_ADDRESS(%ecx), %eax - orl VREG_ADDRESS(%ecx), %eax - .else - cmpl $0x80000000, VREG_ADDRESS(%ecx) - .endif - je .Lop_float_to_int_special_case # fix up result - -.Lop_float_to_int_finish: - xor %eax, %eax - mov %eax, VREG_REF_ADDRESS(%ecx) - .if 0 - mov %eax, VREG_REF_HIGH_ADDRESS(%ecx) - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -.Lop_float_to_int_special_case: - fnstsw %ax - sahf - jp .Lop_float_to_int_isNaN - adcl $-1, VREG_ADDRESS(%ecx) - .if 0 - adcl $-1, VREG_HIGH_ADDRESS(%ecx) - .endif - jmp .Lop_float_to_int_finish -.Lop_float_to_int_isNaN: - movl $0, VREG_ADDRESS(%ecx) - .if 0 - movl $0, VREG_HIGH_ADDRESS(%ecx) - .endif - jmp .Lop_float_to_int_finish - -/* ------------------------------ */ - .balign 128 -.L_op_float_to_long: /* 0x88 */ -/* On fp to int conversions, Java requires that - * if the result > maxint, it should be clamped to maxint. If it is less - * than minint, it should be clamped to minint. If it is a nan, the result - * should be zero. Further, the rounding mode is to truncate. This model - * differs from what is delivered normally via the x86 fpu, so we have - * to play some games. - */ - /* float/double to int/long vA, vB */ - movzbl rINSTbl, %ecx # ecx <- A+ - sarl $4, rINST # rINST <- B - .if 0 - fldl VREG_ADDRESS(rINST) # %st0 <- vB - .else - flds VREG_ADDRESS(rINST) # %st0 <- vB - .endif - ftst - fnstcw LOCAL0(%esp) # remember original rounding mode - movzwl LOCAL0(%esp), %eax - movb $0xc, %ah - movw %ax, LOCAL0+2(%esp) - fldcw LOCAL0+2(%esp) # set "to zero" rounding mode - andb $0xf, %cl # ecx <- A - .if 1 - fistpll VREG_ADDRESS(%ecx) # convert and store - .else - fistpl VREG_ADDRESS(%ecx) # convert and store - .endif - fldcw LOCAL0(%esp) # restore previous rounding mode - .if 1 - movl $0x80000000, %eax - xorl VREG_HIGH_ADDRESS(%ecx), %eax - orl VREG_ADDRESS(%ecx), %eax - .else - cmpl $0x80000000, VREG_ADDRESS(%ecx) - .endif - je .Lop_float_to_long_special_case # fix up result - -.Lop_float_to_long_finish: - xor %eax, %eax - mov %eax, VREG_REF_ADDRESS(%ecx) - .if 1 - mov %eax, VREG_REF_HIGH_ADDRESS(%ecx) - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -.Lop_float_to_long_special_case: - fnstsw %ax - sahf - jp .Lop_float_to_long_isNaN - adcl $-1, VREG_ADDRESS(%ecx) - .if 1 - adcl $-1, VREG_HIGH_ADDRESS(%ecx) - .endif - jmp .Lop_float_to_long_finish -.Lop_float_to_long_isNaN: - movl $0, VREG_ADDRESS(%ecx) - .if 1 - movl $0, VREG_HIGH_ADDRESS(%ecx) - .endif - jmp .Lop_float_to_long_finish - -/* ------------------------------ */ - .balign 128 -.L_op_float_to_double: /* 0x89 */ -/* - * Generic 32-bit FP conversion operation. - */ - /* unop vA, vB */ - movzbl rINSTbl, %ecx # ecx <- A+ - sarl $4, rINST # rINST <- B - flds VREG_ADDRESS(rINST) # %st0 <- vB - andb $0xf, %cl # ecx <- A - - fstpl VREG_ADDRESS(%ecx) # vA <- %st0 - .if 1 - CLEAR_WIDE_REF %ecx - .else - CLEAR_REF %ecx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_double_to_int: /* 0x8a */ -/* On fp to int conversions, Java requires that - * if the result > maxint, it should be clamped to maxint. If it is less - * than minint, it should be clamped to minint. If it is a nan, the result - * should be zero. Further, the rounding mode is to truncate. This model - * differs from what is delivered normally via the x86 fpu, so we have - * to play some games. - */ - /* float/double to int/long vA, vB */ - movzbl rINSTbl, %ecx # ecx <- A+ - sarl $4, rINST # rINST <- B - .if 1 - fldl VREG_ADDRESS(rINST) # %st0 <- vB - .else - flds VREG_ADDRESS(rINST) # %st0 <- vB - .endif - ftst - fnstcw LOCAL0(%esp) # remember original rounding mode - movzwl LOCAL0(%esp), %eax - movb $0xc, %ah - movw %ax, LOCAL0+2(%esp) - fldcw LOCAL0+2(%esp) # set "to zero" rounding mode - andb $0xf, %cl # ecx <- A - .if 0 - fistpll VREG_ADDRESS(%ecx) # convert and store - .else - fistpl VREG_ADDRESS(%ecx) # convert and store - .endif - fldcw LOCAL0(%esp) # restore previous rounding mode - .if 0 - movl $0x80000000, %eax - xorl VREG_HIGH_ADDRESS(%ecx), %eax - orl VREG_ADDRESS(%ecx), %eax - .else - cmpl $0x80000000, VREG_ADDRESS(%ecx) - .endif - je .Lop_double_to_int_special_case # fix up result - -.Lop_double_to_int_finish: - xor %eax, %eax - mov %eax, VREG_REF_ADDRESS(%ecx) - .if 0 - mov %eax, VREG_REF_HIGH_ADDRESS(%ecx) - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -.Lop_double_to_int_special_case: - fnstsw %ax - sahf - jp .Lop_double_to_int_isNaN - adcl $-1, VREG_ADDRESS(%ecx) - .if 0 - adcl $-1, VREG_HIGH_ADDRESS(%ecx) - .endif - jmp .Lop_double_to_int_finish -.Lop_double_to_int_isNaN: - movl $0, VREG_ADDRESS(%ecx) - .if 0 - movl $0, VREG_HIGH_ADDRESS(%ecx) - .endif - jmp .Lop_double_to_int_finish - -/* ------------------------------ */ - .balign 128 -.L_op_double_to_long: /* 0x8b */ -/* On fp to int conversions, Java requires that - * if the result > maxint, it should be clamped to maxint. If it is less - * than minint, it should be clamped to minint. If it is a nan, the result - * should be zero. Further, the rounding mode is to truncate. This model - * differs from what is delivered normally via the x86 fpu, so we have - * to play some games. - */ - /* float/double to int/long vA, vB */ - movzbl rINSTbl, %ecx # ecx <- A+ - sarl $4, rINST # rINST <- B - .if 1 - fldl VREG_ADDRESS(rINST) # %st0 <- vB - .else - flds VREG_ADDRESS(rINST) # %st0 <- vB - .endif - ftst - fnstcw LOCAL0(%esp) # remember original rounding mode - movzwl LOCAL0(%esp), %eax - movb $0xc, %ah - movw %ax, LOCAL0+2(%esp) - fldcw LOCAL0+2(%esp) # set "to zero" rounding mode - andb $0xf, %cl # ecx <- A - .if 1 - fistpll VREG_ADDRESS(%ecx) # convert and store - .else - fistpl VREG_ADDRESS(%ecx) # convert and store - .endif - fldcw LOCAL0(%esp) # restore previous rounding mode - .if 1 - movl $0x80000000, %eax - xorl VREG_HIGH_ADDRESS(%ecx), %eax - orl VREG_ADDRESS(%ecx), %eax - .else - cmpl $0x80000000, VREG_ADDRESS(%ecx) - .endif - je .Lop_double_to_long_special_case # fix up result - -.Lop_double_to_long_finish: - xor %eax, %eax - mov %eax, VREG_REF_ADDRESS(%ecx) - .if 1 - mov %eax, VREG_REF_HIGH_ADDRESS(%ecx) - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -.Lop_double_to_long_special_case: - fnstsw %ax - sahf - jp .Lop_double_to_long_isNaN - adcl $-1, VREG_ADDRESS(%ecx) - .if 1 - adcl $-1, VREG_HIGH_ADDRESS(%ecx) - .endif - jmp .Lop_double_to_long_finish -.Lop_double_to_long_isNaN: - movl $0, VREG_ADDRESS(%ecx) - .if 1 - movl $0, VREG_HIGH_ADDRESS(%ecx) - .endif - jmp .Lop_double_to_long_finish - -/* ------------------------------ */ - .balign 128 -.L_op_double_to_float: /* 0x8c */ -/* - * Generic 32-bit FP conversion operation. - */ - /* unop vA, vB */ - movzbl rINSTbl, %ecx # ecx <- A+ - sarl $4, rINST # rINST <- B - fldl VREG_ADDRESS(rINST) # %st0 <- vB - andb $0xf, %cl # ecx <- A - - fstps VREG_ADDRESS(%ecx) # vA <- %st0 - .if 0 - CLEAR_WIDE_REF %ecx - .else - CLEAR_REF %ecx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_byte: /* 0x8d */ -/* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op eax". - */ - /* unop vA, vB */ - movzbl rINSTbl,%ecx # ecx <- A+ - sarl $4,rINST # rINST <- B - GET_VREG %eax, rINST # eax <- vB - andb $0xf,%cl # ecx <- A - movsbl %al, %eax - SET_VREG %eax, %ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_char: /* 0x8e */ -/* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op eax". - */ - /* unop vA, vB */ - movzbl rINSTbl,%ecx # ecx <- A+ - sarl $4,rINST # rINST <- B - GET_VREG %eax, rINST # eax <- vB - andb $0xf,%cl # ecx <- A - movzwl %ax,%eax - SET_VREG %eax, %ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_short: /* 0x8f */ -/* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op eax". - */ - /* unop vA, vB */ - movzbl rINSTbl,%ecx # ecx <- A+ - sarl $4,rINST # rINST <- B - GET_VREG %eax, rINST # eax <- vB - andb $0xf,%cl # ecx <- A - movswl %ax, %eax - SET_VREG %eax, %ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_add_int: /* 0x90 */ -/* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = eax op (rFP,%ecx,4)". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int, sub-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB - addl (rFP,%ecx,4), %eax # ex: addl (rFP,%ecx,4),%eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_sub_int: /* 0x91 */ -/* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = eax op (rFP,%ecx,4)". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int, sub-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB - subl (rFP,%ecx,4), %eax # ex: addl (rFP,%ecx,4),%eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int: /* 0x92 */ - /* - * 32-bit binary multiplication. - */ - /* mul vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB - mov rIBASE, LOCAL0(%esp) - imull (rFP,%ecx,4), %eax # trashes rIBASE/edx - mov LOCAL0(%esp), rIBASE - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_div_int: /* 0x93 */ -/* - * 32-bit binary div/rem operation. Handles special case of op0=minint and - * op1=-1. - */ - /* div/rem vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB - GET_VREG %ecx, %ecx # ecx <- vCC - mov rIBASE, LOCAL0(%esp) - testl %ecx, %ecx - je common_errDivideByZero - movl %eax, %edx - orl %ecx, %edx - testl $0xFFFFFF00, %edx # If both arguments are less - # than 8-bit and +ve - jz .Lop_div_int_8 # Do 8-bit divide - testl $0xFFFF0000, %edx # If both arguments are less - # than 16-bit and +ve - jz .Lop_div_int_16 # Do 16-bit divide - cmpl $-1, %ecx - jne .Lop_div_int_32 - cmpl $0x80000000, %eax - jne .Lop_div_int_32 - movl $0x80000000, %eax - jmp .Lop_div_int_finish -.Lop_div_int_32: - cltd - idivl %ecx - jmp .Lop_div_int_finish -.Lop_div_int_8: - div %cl # 8-bit divide otherwise. - # Remainder in %ah, quotient in %al - .if 0 - movl %eax, %edx - shr $8, %edx - .else - andl $0x000000FF, %eax - .endif - jmp .Lop_div_int_finish -.Lop_div_int_16: - xorl %edx, %edx # Clear %edx before divide - div %cx -.Lop_div_int_finish: - SET_VREG %eax, rINST - mov LOCAL0(%esp), rIBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int: /* 0x94 */ -/* - * 32-bit binary div/rem operation. Handles special case of op0=minint and - * op1=-1. - */ - /* div/rem vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB - GET_VREG %ecx, %ecx # ecx <- vCC - mov rIBASE, LOCAL0(%esp) - testl %ecx, %ecx - je common_errDivideByZero - movl %eax, %edx - orl %ecx, %edx - testl $0xFFFFFF00, %edx # If both arguments are less - # than 8-bit and +ve - jz .Lop_rem_int_8 # Do 8-bit divide - testl $0xFFFF0000, %edx # If both arguments are less - # than 16-bit and +ve - jz .Lop_rem_int_16 # Do 16-bit divide - cmpl $-1, %ecx - jne .Lop_rem_int_32 - cmpl $0x80000000, %eax - jne .Lop_rem_int_32 - movl $0, rIBASE - jmp .Lop_rem_int_finish -.Lop_rem_int_32: - cltd - idivl %ecx - jmp .Lop_rem_int_finish -.Lop_rem_int_8: - div %cl # 8-bit divide otherwise. - # Remainder in %ah, quotient in %al - .if 1 - movl %eax, %edx - shr $8, %edx - .else - andl $0x000000FF, %eax - .endif - jmp .Lop_rem_int_finish -.Lop_rem_int_16: - xorl %edx, %edx # Clear %edx before divide - div %cx -.Lop_rem_int_finish: - SET_VREG rIBASE, rINST - mov LOCAL0(%esp), rIBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_and_int: /* 0x95 */ -/* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = eax op (rFP,%ecx,4)". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int, sub-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB - andl (rFP,%ecx,4), %eax # ex: addl (rFP,%ecx,4),%eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_or_int: /* 0x96 */ -/* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = eax op (rFP,%ecx,4)". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int, sub-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB - orl (rFP,%ecx,4), %eax # ex: addl (rFP,%ecx,4),%eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int: /* 0x97 */ -/* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = eax op (rFP,%ecx,4)". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int, sub-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB - xorl (rFP,%ecx,4), %eax # ex: addl (rFP,%ecx,4),%eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_shl_int: /* 0x98 */ -/* - * Generic 32-bit binary operation in which both operands loaded to - * registers (op0 in eax, op1 in ecx). - */ - /* binop vAA, vBB, vCC */ - movzbl 2(rPC),%eax # eax <- BB - movzbl 3(rPC),%ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB - GET_VREG %ecx, %ecx # eax <- vBB - sall %cl, %eax # ex: addl %ecx,%eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_shr_int: /* 0x99 */ -/* - * Generic 32-bit binary operation in which both operands loaded to - * registers (op0 in eax, op1 in ecx). - */ - /* binop vAA, vBB, vCC */ - movzbl 2(rPC),%eax # eax <- BB - movzbl 3(rPC),%ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB - GET_VREG %ecx, %ecx # eax <- vBB - sarl %cl, %eax # ex: addl %ecx,%eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_int: /* 0x9a */ -/* - * Generic 32-bit binary operation in which both operands loaded to - * registers (op0 in eax, op1 in ecx). - */ - /* binop vAA, vBB, vCC */ - movzbl 2(rPC),%eax # eax <- BB - movzbl 3(rPC),%ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB - GET_VREG %ecx, %ecx # eax <- vBB - shrl %cl, %eax # ex: addl %ecx,%eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_add_long: /* 0x9b */ -/* - * Generic 64-bit binary operation. - */ - /* binop vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - movl rIBASE, LOCAL0(%esp) # save rIBASE - GET_VREG rIBASE, %eax # rIBASE <- v[BB+0] - GET_VREG_HIGH %eax, %eax # eax <- v[BB+1] - addl (rFP,%ecx,4), rIBASE # ex: addl (rFP,%ecx,4),rIBASE - adcl 4(rFP,%ecx,4), %eax # ex: adcl 4(rFP,%ecx,4),%eax - SET_VREG rIBASE, rINST # v[AA+0] <- rIBASE - movl LOCAL0(%esp), rIBASE # restore rIBASE - SET_VREG_HIGH %eax, rINST # v[AA+1] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_sub_long: /* 0x9c */ -/* - * Generic 64-bit binary operation. - */ - /* binop vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - movl rIBASE, LOCAL0(%esp) # save rIBASE - GET_VREG rIBASE, %eax # rIBASE <- v[BB+0] - GET_VREG_HIGH %eax, %eax # eax <- v[BB+1] - subl (rFP,%ecx,4), rIBASE # ex: addl (rFP,%ecx,4),rIBASE - sbbl 4(rFP,%ecx,4), %eax # ex: adcl 4(rFP,%ecx,4),%eax - SET_VREG rIBASE, rINST # v[AA+0] <- rIBASE - movl LOCAL0(%esp), rIBASE # restore rIBASE - SET_VREG_HIGH %eax, rINST # v[AA+1] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_mul_long: /* 0x9d */ -/* - * Signed 64-bit integer multiply. - * - * We could definately use more free registers for - * this code. We spill rINSTw (ebx), - * giving us eax, ebc, ecx and edx as computational - * temps. On top of that, we'll spill edi (rFP) - * for use as the vB pointer and esi (rPC) for use - * as the vC pointer. Yuck. - * - */ - /* mul-long vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- B - movzbl 3(rPC), %ecx # ecx <- C - mov rPC, LOCAL0(%esp) # save Interpreter PC - mov rFP, LOCAL1(%esp) # save FP - mov rIBASE, LOCAL2(%esp) # save rIBASE - leal (rFP,%eax,4), %esi # esi <- &v[B] - leal (rFP,%ecx,4), rFP # rFP <- &v[C] - movl 4(%esi), %ecx # ecx <- Bmsw - imull (rFP), %ecx # ecx <- (Bmsw*Clsw) - movl 4(rFP), %eax # eax <- Cmsw - imull (%esi), %eax # eax <- (Cmsw*Blsw) - addl %eax, %ecx # ecx <- (Bmsw*Clsw)+(Cmsw*Blsw) - movl (rFP), %eax # eax <- Clsw - mull (%esi) # eax <- (Clsw*Alsw) - mov LOCAL0(%esp), rPC # restore Interpreter PC - mov LOCAL1(%esp), rFP # restore FP - leal (%ecx,rIBASE), rIBASE # full result now in rIBASE:%eax - SET_VREG_HIGH rIBASE, rINST # v[B+1] <- rIBASE - mov LOCAL2(%esp), rIBASE # restore IBASE - SET_VREG %eax, rINST # v[B] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_div_long: /* 0x9e */ -/* art_quick_* methods has quick abi, - * so use eax, ecx, edx, ebx for args - */ - /* div vAA, vBB, vCC */ - .extern art_quick_ldiv - mov rIBASE, LOCAL0(%esp) # save rIBASE/%edx - mov rINST, LOCAL1(%esp) # save rINST/%ebx - movzbl 3(rPC), %eax # eax <- CC - GET_VREG %ecx, %eax - GET_VREG_HIGH %ebx, %eax - movl %ecx, %edx - orl %ebx, %ecx - jz common_errDivideByZero - movzbl 2(rPC), %eax # eax <- BB - GET_VREG_HIGH %ecx, %eax - GET_VREG %eax, %eax - call SYMBOL(art_quick_ldiv) - mov LOCAL1(%esp), rINST # restore rINST/%ebx - SET_VREG_HIGH rIBASE, rINST - SET_VREG %eax, rINST - mov LOCAL0(%esp), rIBASE # restore rIBASE/%edx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_rem_long: /* 0x9f */ -/* art_quick_* methods has quick abi, - * so use eax, ecx, edx, ebx for args - */ - /* div vAA, vBB, vCC */ - .extern art_quick_lmod - mov rIBASE, LOCAL0(%esp) # save rIBASE/%edx - mov rINST, LOCAL1(%esp) # save rINST/%ebx - movzbl 3(rPC), %eax # eax <- CC - GET_VREG %ecx, %eax - GET_VREG_HIGH %ebx, %eax - movl %ecx, %edx - orl %ebx, %ecx - jz common_errDivideByZero - movzbl 2(rPC), %eax # eax <- BB - GET_VREG_HIGH %ecx, %eax - GET_VREG %eax, %eax - call SYMBOL(art_quick_lmod) - mov LOCAL1(%esp), rINST # restore rINST/%ebx - SET_VREG_HIGH rIBASE, rINST - SET_VREG %eax, rINST - mov LOCAL0(%esp), rIBASE # restore rIBASE/%edx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_and_long: /* 0xa0 */ -/* - * Generic 64-bit binary operation. - */ - /* binop vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - movl rIBASE, LOCAL0(%esp) # save rIBASE - GET_VREG rIBASE, %eax # rIBASE <- v[BB+0] - GET_VREG_HIGH %eax, %eax # eax <- v[BB+1] - andl (rFP,%ecx,4), rIBASE # ex: addl (rFP,%ecx,4),rIBASE - andl 4(rFP,%ecx,4), %eax # ex: adcl 4(rFP,%ecx,4),%eax - SET_VREG rIBASE, rINST # v[AA+0] <- rIBASE - movl LOCAL0(%esp), rIBASE # restore rIBASE - SET_VREG_HIGH %eax, rINST # v[AA+1] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_or_long: /* 0xa1 */ -/* - * Generic 64-bit binary operation. - */ - /* binop vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - movl rIBASE, LOCAL0(%esp) # save rIBASE - GET_VREG rIBASE, %eax # rIBASE <- v[BB+0] - GET_VREG_HIGH %eax, %eax # eax <- v[BB+1] - orl (rFP,%ecx,4), rIBASE # ex: addl (rFP,%ecx,4),rIBASE - orl 4(rFP,%ecx,4), %eax # ex: adcl 4(rFP,%ecx,4),%eax - SET_VREG rIBASE, rINST # v[AA+0] <- rIBASE - movl LOCAL0(%esp), rIBASE # restore rIBASE - SET_VREG_HIGH %eax, rINST # v[AA+1] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_xor_long: /* 0xa2 */ -/* - * Generic 64-bit binary operation. - */ - /* binop vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - movl rIBASE, LOCAL0(%esp) # save rIBASE - GET_VREG rIBASE, %eax # rIBASE <- v[BB+0] - GET_VREG_HIGH %eax, %eax # eax <- v[BB+1] - xorl (rFP,%ecx,4), rIBASE # ex: addl (rFP,%ecx,4),rIBASE - xorl 4(rFP,%ecx,4), %eax # ex: adcl 4(rFP,%ecx,4),%eax - SET_VREG rIBASE, rINST # v[AA+0] <- rIBASE - movl LOCAL0(%esp), rIBASE # restore rIBASE - SET_VREG_HIGH %eax, rINST # v[AA+1] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_shl_long: /* 0xa3 */ -/* - * Long integer shift. This is different from the generic 32/64-bit - * binary operations because vAA/vBB are 64-bit but vCC (the shift - * distance) is 32-bit. Also, Dalvik requires us to mask off the low - * 6 bits of the shift distance. x86 shifts automatically mask off - * the low 5 bits of %cl, so have to handle the 64 > shiftcount > 31 - * case specially. - */ - /* shl-long vAA, vBB, vCC */ - /* ecx gets shift count */ - /* Need to spill rINST */ - /* rINSTw gets AA */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - movl rIBASE, LOCAL0(%esp) - GET_VREG_HIGH rIBASE, %eax # ecx <- v[BB+1] - GET_VREG %ecx, %ecx # ecx <- vCC - GET_VREG %eax, %eax # eax <- v[BB+0] - shldl %eax,rIBASE - sall %cl, %eax - testb $32, %cl - je 2f - movl %eax, rIBASE - xorl %eax, %eax -2: - SET_VREG_HIGH rIBASE, rINST # v[AA+1] <- rIBASE - movl LOCAL0(%esp), rIBASE - SET_VREG %eax, rINST # v[AA+0] <- %eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_shr_long: /* 0xa4 */ -/* - * Long integer shift. This is different from the generic 32/64-bit - * binary operations because vAA/vBB are 64-bit but vCC (the shift - * distance) is 32-bit. Also, Dalvik requires us to mask off the low - * 6 bits of the shift distance. x86 shifts automatically mask off - * the low 5 bits of %cl, so have to handle the 64 > shiftcount > 31 - * case specially. - */ - /* shr-long vAA, vBB, vCC */ - /* ecx gets shift count */ - /* Need to spill rIBASE */ - /* rINSTw gets AA */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - movl rIBASE, LOCAL0(%esp) - GET_VREG_HIGH rIBASE, %eax # rIBASE<- v[BB+1] - GET_VREG %ecx, %ecx # ecx <- vCC - GET_VREG %eax, %eax # eax <- v[BB+0] - shrdl rIBASE, %eax - sarl %cl, rIBASE - testb $32, %cl - je 2f - movl rIBASE, %eax - sarl $31, rIBASE -2: - SET_VREG_HIGH rIBASE, rINST # v[AA+1] <- rIBASE - movl LOCAL0(%esp), rIBASE - SET_VREG %eax, rINST # v[AA+0] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_long: /* 0xa5 */ -/* - * Long integer shift. This is different from the generic 32/64-bit - * binary operations because vAA/vBB are 64-bit but vCC (the shift - * distance) is 32-bit. Also, Dalvik requires us to mask off the low - * 6 bits of the shift distance. x86 shifts automatically mask off - * the low 5 bits of %cl, so have to handle the 64 > shiftcount > 31 - * case specially. - */ - /* shr-long vAA, vBB, vCC */ - /* ecx gets shift count */ - /* Need to spill rIBASE */ - /* rINSTw gets AA */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - movl rIBASE, LOCAL0(%esp) - GET_VREG_HIGH rIBASE, %eax # rIBASE <- v[BB+1] - GET_VREG %ecx, %ecx # ecx <- vCC - GET_VREG %eax, %eax # eax <- v[BB+0] - shrdl rIBASE, %eax - shrl %cl, rIBASE - testb $32, %cl - je 2f - movl rIBASE, %eax - xorl rIBASE, rIBASE -2: - SET_VREG_HIGH rIBASE, rINST # v[AA+1] <- rIBASE - movl LOCAL0(%esp), rIBASE - SET_VREG %eax, rINST # v[BB+0] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_add_float: /* 0xa6 */ - movzbl 2(rPC), %ecx # ecx <- BB - movzbl 3(rPC), %eax # eax <- CC - movss VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src - addss VREG_ADDRESS(%eax), %xmm0 - movss %xmm0, VREG_ADDRESS(rINST) # vAA <- %xmm0 - pxor %xmm0, %xmm0 - movss %xmm0, VREG_REF_ADDRESS(rINST) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_sub_float: /* 0xa7 */ - movzbl 2(rPC), %ecx # ecx <- BB - movzbl 3(rPC), %eax # eax <- CC - movss VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src - subss VREG_ADDRESS(%eax), %xmm0 - movss %xmm0, VREG_ADDRESS(rINST) # vAA <- %xmm0 - pxor %xmm0, %xmm0 - movss %xmm0, VREG_REF_ADDRESS(rINST) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_mul_float: /* 0xa8 */ - movzbl 2(rPC), %ecx # ecx <- BB - movzbl 3(rPC), %eax # eax <- CC - movss VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src - mulss VREG_ADDRESS(%eax), %xmm0 - movss %xmm0, VREG_ADDRESS(rINST) # vAA <- %xmm0 - pxor %xmm0, %xmm0 - movss %xmm0, VREG_REF_ADDRESS(rINST) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_div_float: /* 0xa9 */ - movzbl 2(rPC), %ecx # ecx <- BB - movzbl 3(rPC), %eax # eax <- CC - movss VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src - divss VREG_ADDRESS(%eax), %xmm0 - movss %xmm0, VREG_ADDRESS(rINST) # vAA <- %xmm0 - pxor %xmm0, %xmm0 - movss %xmm0, VREG_REF_ADDRESS(rINST) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_rem_float: /* 0xaa */ - /* rem_float vAA, vBB, vCC */ - movzbl 3(rPC), %ecx # ecx <- BB - movzbl 2(rPC), %eax # eax <- CC - flds VREG_ADDRESS(%ecx) # vBB to fp stack - flds VREG_ADDRESS(%eax) # vCC to fp stack -1: - fprem - fstsw %ax - sahf - jp 1b - fstp %st(1) - fstps VREG_ADDRESS(rINST) # %st to vAA - CLEAR_REF rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_add_double: /* 0xab */ - movzbl 2(rPC), %ecx # ecx <- BB - movzbl 3(rPC), %eax # eax <- CC - movsd VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src - addsd VREG_ADDRESS(%eax), %xmm0 - movsd %xmm0, VREG_ADDRESS(rINST) # vAA <- %xmm0 - pxor %xmm0, %xmm0 - movsd %xmm0, VREG_REF_ADDRESS(rINST) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_sub_double: /* 0xac */ - movzbl 2(rPC), %ecx # ecx <- BB - movzbl 3(rPC), %eax # eax <- CC - movsd VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src - subsd VREG_ADDRESS(%eax), %xmm0 - movsd %xmm0, VREG_ADDRESS(rINST) # vAA <- %xmm0 - pxor %xmm0, %xmm0 - movsd %xmm0, VREG_REF_ADDRESS(rINST) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_mul_double: /* 0xad */ - movzbl 2(rPC), %ecx # ecx <- BB - movzbl 3(rPC), %eax # eax <- CC - movsd VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src - mulsd VREG_ADDRESS(%eax), %xmm0 - movsd %xmm0, VREG_ADDRESS(rINST) # vAA <- %xmm0 - pxor %xmm0, %xmm0 - movsd %xmm0, VREG_REF_ADDRESS(rINST) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_div_double: /* 0xae */ - movzbl 2(rPC), %ecx # ecx <- BB - movzbl 3(rPC), %eax # eax <- CC - movsd VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src - divsd VREG_ADDRESS(%eax), %xmm0 - movsd %xmm0, VREG_ADDRESS(rINST) # vAA <- %xmm0 - pxor %xmm0, %xmm0 - movsd %xmm0, VREG_REF_ADDRESS(rINST) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_rem_double: /* 0xaf */ - /* rem_double vAA, vBB, vCC */ - movzbl 3(rPC), %ecx # ecx <- BB - movzbl 2(rPC), %eax # eax <- CC - fldl VREG_ADDRESS(%ecx) # %st1 <- fp[vBB] - fldl VREG_ADDRESS(%eax) # %st0 <- fp[vCC] -1: - fprem - fstsw %ax - sahf - jp 1b - fstp %st(1) - fstpl VREG_ADDRESS(rINST) # fp[vAA] <- %st - CLEAR_WIDE_REF rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_add_int_2addr: /* 0xb0 */ -/* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an instruction or a function call. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - movzx rINSTbl, %ecx # ecx <- A+ - sarl $4, rINST # rINST <- B - GET_VREG %eax, rINST # eax <- vB - andb $0xf, %cl # ecx <- A - addl %eax, (rFP,%ecx,4) # for ex: addl %eax,(rFP,%ecx,4) - CLEAR_REF %ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_sub_int_2addr: /* 0xb1 */ -/* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an instruction or a function call. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - movzx rINSTbl, %ecx # ecx <- A+ - sarl $4, rINST # rINST <- B - GET_VREG %eax, rINST # eax <- vB - andb $0xf, %cl # ecx <- A - subl %eax, (rFP,%ecx,4) # for ex: addl %eax,(rFP,%ecx,4) - CLEAR_REF %ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int_2addr: /* 0xb2 */ - /* mul vA, vB */ - movzx rINSTbl, %ecx # ecx <- A+ - sarl $4, rINST # rINST <- B - GET_VREG %eax, rINST # eax <- vB - andb $0xf, %cl # ecx <- A - movl rIBASE, rINST - imull (rFP,%ecx,4), %eax # trashes rIBASE/edx - movl rINST, rIBASE - SET_VREG %eax, %ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_div_int_2addr: /* 0xb3 */ -/* - * 32-bit binary div/rem operation. Handles special case of op0=minint and - * op1=-1. - */ - /* div/rem/2addr vA, vB */ - movzx rINSTbl, %ecx # eax <- BA - mov rIBASE, LOCAL0(%esp) - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # eax <- vBB - andb $0xf, rINSTbl # rINST <- A - GET_VREG %eax, rINST # eax <- vBB - testl %ecx, %ecx - je common_errDivideByZero - cmpl $-1, %ecx - jne .Lop_div_int_2addr_continue_div2addr - cmpl $0x80000000, %eax - jne .Lop_div_int_2addr_continue_div2addr - movl $0x80000000, %eax - SET_VREG %eax, rINST - mov LOCAL0(%esp), rIBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -.Lop_div_int_2addr_continue_div2addr: - cltd - idivl %ecx - SET_VREG %eax, rINST - mov LOCAL0(%esp), rIBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int_2addr: /* 0xb4 */ -/* - * 32-bit binary div/rem operation. Handles special case of op0=minint and - * op1=-1. - */ - /* div/rem/2addr vA, vB */ - movzx rINSTbl, %ecx # eax <- BA - mov rIBASE, LOCAL0(%esp) - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # eax <- vBB - andb $0xf, rINSTbl # rINST <- A - GET_VREG %eax, rINST # eax <- vBB - testl %ecx, %ecx - je common_errDivideByZero - cmpl $-1, %ecx - jne .Lop_rem_int_2addr_continue_div2addr - cmpl $0x80000000, %eax - jne .Lop_rem_int_2addr_continue_div2addr - movl $0, rIBASE - SET_VREG rIBASE, rINST - mov LOCAL0(%esp), rIBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -.Lop_rem_int_2addr_continue_div2addr: - cltd - idivl %ecx - SET_VREG rIBASE, rINST - mov LOCAL0(%esp), rIBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_and_int_2addr: /* 0xb5 */ -/* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an instruction or a function call. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - movzx rINSTbl, %ecx # ecx <- A+ - sarl $4, rINST # rINST <- B - GET_VREG %eax, rINST # eax <- vB - andb $0xf, %cl # ecx <- A - andl %eax, (rFP,%ecx,4) # for ex: addl %eax,(rFP,%ecx,4) - CLEAR_REF %ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_or_int_2addr: /* 0xb6 */ -/* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an instruction or a function call. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - movzx rINSTbl, %ecx # ecx <- A+ - sarl $4, rINST # rINST <- B - GET_VREG %eax, rINST # eax <- vB - andb $0xf, %cl # ecx <- A - orl %eax, (rFP,%ecx,4) # for ex: addl %eax,(rFP,%ecx,4) - CLEAR_REF %ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int_2addr: /* 0xb7 */ -/* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an instruction or a function call. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - movzx rINSTbl, %ecx # ecx <- A+ - sarl $4, rINST # rINST <- B - GET_VREG %eax, rINST # eax <- vB - andb $0xf, %cl # ecx <- A - xorl %eax, (rFP,%ecx,4) # for ex: addl %eax,(rFP,%ecx,4) - CLEAR_REF %ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_shl_int_2addr: /* 0xb8 */ -/* - * Generic 32-bit "shift/2addr" operation. - */ - /* shift/2addr vA, vB */ - movzx rINSTbl, %ecx # eax <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # eax <- vBB - andb $0xf, rINSTbl # rINST <- A - GET_VREG %eax, rINST # eax <- vAA - sall %cl, %eax # ex: sarl %cl, %eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_shr_int_2addr: /* 0xb9 */ -/* - * Generic 32-bit "shift/2addr" operation. - */ - /* shift/2addr vA, vB */ - movzx rINSTbl, %ecx # eax <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # eax <- vBB - andb $0xf, rINSTbl # rINST <- A - GET_VREG %eax, rINST # eax <- vAA - sarl %cl, %eax # ex: sarl %cl, %eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_int_2addr: /* 0xba */ -/* - * Generic 32-bit "shift/2addr" operation. - */ - /* shift/2addr vA, vB */ - movzx rINSTbl, %ecx # eax <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # eax <- vBB - andb $0xf, rINSTbl # rINST <- A - GET_VREG %eax, rINST # eax <- vAA - shrl %cl, %eax # ex: sarl %cl, %eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_add_long_2addr: /* 0xbb */ -/* - * Generic 64-bit binary operation. - */ - /* binop/2addr vA, vB */ - movzbl rINSTbl, %ecx # ecx<- BA - sarl $4, %ecx # ecx<- B - GET_VREG %eax, %ecx # eax<- v[B+0] - GET_VREG_HIGH %ecx, %ecx # eax<- v[B+1] - andb $0xF, rINSTbl # rINST<- A - addl %eax, (rFP,rINST,4) # ex: addl %eax,(rFP,rINST,4) - adcl %ecx, 4(rFP,rINST,4) # ex: adcl %ecx,4(rFP,rINST,4) - CLEAR_WIDE_REF rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_sub_long_2addr: /* 0xbc */ -/* - * Generic 64-bit binary operation. - */ - /* binop/2addr vA, vB */ - movzbl rINSTbl, %ecx # ecx<- BA - sarl $4, %ecx # ecx<- B - GET_VREG %eax, %ecx # eax<- v[B+0] - GET_VREG_HIGH %ecx, %ecx # eax<- v[B+1] - andb $0xF, rINSTbl # rINST<- A - subl %eax, (rFP,rINST,4) # ex: addl %eax,(rFP,rINST,4) - sbbl %ecx, 4(rFP,rINST,4) # ex: adcl %ecx,4(rFP,rINST,4) - CLEAR_WIDE_REF rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_mul_long_2addr: /* 0xbd */ -/* - * Signed 64-bit integer multiply, 2-addr version - * - * We could definately use more free registers for - * this code. We must spill %edx (rIBASE) because it - * is used by imul. We'll also spill rINST (ebx), - * giving us eax, ebc, ecx and rIBASE as computational - * temps. On top of that, we'll spill %esi (edi) - * for use as the vA pointer and rFP (esi) for use - * as the vB pointer. Yuck. - */ - /* mul-long/2addr vA, vB */ - movzbl rINSTbl, %eax # eax <- BA - andb $0xf, %al # eax <- A - CLEAR_WIDE_REF %eax # clear refs in advance - sarl $4, rINST # rINST <- B - mov rPC, LOCAL0(%esp) # save Interpreter PC - mov rFP, LOCAL1(%esp) # save FP - mov rIBASE, LOCAL2(%esp) # save rIBASE - leal (rFP,%eax,4), %esi # esi <- &v[A] - leal (rFP,rINST,4), rFP # rFP <- &v[B] - movl 4(%esi), %ecx # ecx <- Amsw - imull (rFP), %ecx # ecx <- (Amsw*Blsw) - movl 4(rFP), %eax # eax <- Bmsw - imull (%esi), %eax # eax <- (Bmsw*Alsw) - addl %eax, %ecx # ecx <- (Amsw*Blsw)+(Bmsw*Alsw) - movl (rFP), %eax # eax <- Blsw - mull (%esi) # eax <- (Blsw*Alsw) - leal (%ecx,rIBASE), rIBASE # full result now in %edx:%eax - movl rIBASE, 4(%esi) # v[A+1] <- rIBASE - movl %eax, (%esi) # v[A] <- %eax - mov LOCAL0(%esp), rPC # restore Interpreter PC - mov LOCAL2(%esp), rIBASE # restore IBASE - mov LOCAL1(%esp), rFP # restore FP - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_div_long_2addr: /* 0xbe */ -/* art_quick_* methods has quick abi, - * so use eax, ecx, edx, ebx for args - */ - /* div/2addr vA, vB */ - .extern art_quick_ldiv - mov rIBASE, LOCAL0(%esp) # save rIBASE/%edx - movzbl rINSTbl, %eax - shrl $4, %eax # eax <- B - andb $0xf, rINSTbl # rINST <- A - mov rINST, LOCAL1(%esp) # save rINST/%ebx - movl %ebx, %ecx - GET_VREG %edx, %eax - GET_VREG_HIGH %ebx, %eax - movl %edx, %eax - orl %ebx, %eax - jz common_errDivideByZero - GET_VREG %eax, %ecx - GET_VREG_HIGH %ecx, %ecx - call SYMBOL(art_quick_ldiv) - mov LOCAL1(%esp), rINST # restore rINST/%ebx - SET_VREG_HIGH rIBASE, rINST - SET_VREG %eax, rINST - mov LOCAL0(%esp), rIBASE # restore rIBASE/%edx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_rem_long_2addr: /* 0xbf */ -/* art_quick_* methods has quick abi, - * so use eax, ecx, edx, ebx for args - */ - /* div/2addr vA, vB */ - .extern art_quick_lmod - mov rIBASE, LOCAL0(%esp) # save rIBASE/%edx - movzbl rINSTbl, %eax - shrl $4, %eax # eax <- B - andb $0xf, rINSTbl # rINST <- A - mov rINST, LOCAL1(%esp) # save rINST/%ebx - movl %ebx, %ecx - GET_VREG %edx, %eax - GET_VREG_HIGH %ebx, %eax - movl %edx, %eax - orl %ebx, %eax - jz common_errDivideByZero - GET_VREG %eax, %ecx - GET_VREG_HIGH %ecx, %ecx - call SYMBOL(art_quick_lmod) - mov LOCAL1(%esp), rINST # restore rINST/%ebx - SET_VREG_HIGH rIBASE, rINST - SET_VREG %eax, rINST - mov LOCAL0(%esp), rIBASE # restore rIBASE/%edx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_and_long_2addr: /* 0xc0 */ -/* - * Generic 64-bit binary operation. - */ - /* binop/2addr vA, vB */ - movzbl rINSTbl, %ecx # ecx<- BA - sarl $4, %ecx # ecx<- B - GET_VREG %eax, %ecx # eax<- v[B+0] - GET_VREG_HIGH %ecx, %ecx # eax<- v[B+1] - andb $0xF, rINSTbl # rINST<- A - andl %eax, (rFP,rINST,4) # ex: addl %eax,(rFP,rINST,4) - andl %ecx, 4(rFP,rINST,4) # ex: adcl %ecx,4(rFP,rINST,4) - CLEAR_WIDE_REF rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_or_long_2addr: /* 0xc1 */ -/* - * Generic 64-bit binary operation. - */ - /* binop/2addr vA, vB */ - movzbl rINSTbl, %ecx # ecx<- BA - sarl $4, %ecx # ecx<- B - GET_VREG %eax, %ecx # eax<- v[B+0] - GET_VREG_HIGH %ecx, %ecx # eax<- v[B+1] - andb $0xF, rINSTbl # rINST<- A - orl %eax, (rFP,rINST,4) # ex: addl %eax,(rFP,rINST,4) - orl %ecx, 4(rFP,rINST,4) # ex: adcl %ecx,4(rFP,rINST,4) - CLEAR_WIDE_REF rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_xor_long_2addr: /* 0xc2 */ -/* - * Generic 64-bit binary operation. - */ - /* binop/2addr vA, vB */ - movzbl rINSTbl, %ecx # ecx<- BA - sarl $4, %ecx # ecx<- B - GET_VREG %eax, %ecx # eax<- v[B+0] - GET_VREG_HIGH %ecx, %ecx # eax<- v[B+1] - andb $0xF, rINSTbl # rINST<- A - xorl %eax, (rFP,rINST,4) # ex: addl %eax,(rFP,rINST,4) - xorl %ecx, 4(rFP,rINST,4) # ex: adcl %ecx,4(rFP,rINST,4) - CLEAR_WIDE_REF rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_shl_long_2addr: /* 0xc3 */ -/* - * Long integer shift, 2addr version. vA is 64-bit value/result, vB is - * 32-bit shift distance. - */ - /* shl-long/2addr vA, vB */ - /* ecx gets shift count */ - /* Need to spill rIBASE */ - /* rINSTw gets AA */ - movzbl rINSTbl, %ecx # ecx <- BA - andb $0xf, rINSTbl # rINST <- A - GET_VREG %eax, rINST # eax <- v[AA+0] - sarl $4, %ecx # ecx <- B - movl rIBASE, LOCAL0(%esp) - GET_VREG_HIGH rIBASE, rINST # rIBASE <- v[AA+1] - GET_VREG %ecx, %ecx # ecx <- vBB - shldl %eax, rIBASE - sall %cl, %eax - testb $32, %cl - je 2f - movl %eax, rIBASE - xorl %eax, %eax -2: - SET_VREG_HIGH rIBASE, rINST # v[AA+1] <- rIBASE - movl LOCAL0(%esp), rIBASE - SET_VREG %eax, rINST # v[AA+0] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_shr_long_2addr: /* 0xc4 */ -/* - * Long integer shift, 2addr version. vA is 64-bit value/result, vB is - * 32-bit shift distance. - */ - /* shl-long/2addr vA, vB */ - /* ecx gets shift count */ - /* Need to spill rIBASE */ - /* rINSTw gets AA */ - movzbl rINSTbl, %ecx # ecx <- BA - andb $0xf, rINSTbl # rINST <- A - GET_VREG %eax, rINST # eax <- v[AA+0] - sarl $4, %ecx # ecx <- B - movl rIBASE, LOCAL0(%esp) - GET_VREG_HIGH rIBASE, rINST # rIBASE <- v[AA+1] - GET_VREG %ecx, %ecx # ecx <- vBB - shrdl rIBASE, %eax - sarl %cl, rIBASE - testb $32, %cl - je 2f - movl rIBASE, %eax - sarl $31, rIBASE -2: - SET_VREG_HIGH rIBASE, rINST # v[AA+1] <- rIBASE - movl LOCAL0(%esp), rIBASE - SET_VREG %eax, rINST # v[AA+0] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_long_2addr: /* 0xc5 */ -/* - * Long integer shift, 2addr version. vA is 64-bit value/result, vB is - * 32-bit shift distance. - */ - /* shl-long/2addr vA, vB */ - /* ecx gets shift count */ - /* Need to spill rIBASE */ - /* rINSTw gets AA */ - movzbl rINSTbl, %ecx # ecx <- BA - andb $0xf, rINSTbl # rINST <- A - GET_VREG %eax, rINST # eax <- v[AA+0] - sarl $4, %ecx # ecx <- B - movl rIBASE, LOCAL0(%esp) - GET_VREG_HIGH rIBASE, rINST # rIBASE <- v[AA+1] - GET_VREG %ecx, %ecx # ecx <- vBB - shrdl rIBASE, %eax - shrl %cl, rIBASE - testb $32, %cl - je 2f - movl rIBASE, %eax - xorl rIBASE, rIBASE -2: - SET_VREG_HIGH rIBASE, rINST # v[AA+1] <- rIBASE - movl LOCAL0(%esp), rIBASE - SET_VREG %eax, rINST # v[AA+0] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_add_float_2addr: /* 0xc6 */ - movzx rINSTbl, %ecx # ecx <- A+ - andl $0xf, %ecx # ecx <- A - movss VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src - sarl $4, rINST # rINST<- B - addss VREG_ADDRESS(rINST), %xmm0 - movss %xmm0, VREG_ADDRESS(%ecx) # vAA<- %xmm0 - pxor %xmm0, %xmm0 - movss %xmm0, VREG_REF_ADDRESS(rINST) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_sub_float_2addr: /* 0xc7 */ - movzx rINSTbl, %ecx # ecx <- A+ - andl $0xf, %ecx # ecx <- A - movss VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src - sarl $4, rINST # rINST<- B - subss VREG_ADDRESS(rINST), %xmm0 - movss %xmm0, VREG_ADDRESS(%ecx) # vAA<- %xmm0 - pxor %xmm0, %xmm0 - movss %xmm0, VREG_REF_ADDRESS(rINST) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_mul_float_2addr: /* 0xc8 */ - movzx rINSTbl, %ecx # ecx <- A+ - andl $0xf, %ecx # ecx <- A - movss VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src - sarl $4, rINST # rINST<- B - mulss VREG_ADDRESS(rINST), %xmm0 - movss %xmm0, VREG_ADDRESS(%ecx) # vAA<- %xmm0 - pxor %xmm0, %xmm0 - movss %xmm0, VREG_REF_ADDRESS(rINST) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_div_float_2addr: /* 0xc9 */ - movzx rINSTbl, %ecx # ecx <- A+ - andl $0xf, %ecx # ecx <- A - movss VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src - sarl $4, rINST # rINST<- B - divss VREG_ADDRESS(rINST), %xmm0 - movss %xmm0, VREG_ADDRESS(%ecx) # vAA<- %xmm0 - pxor %xmm0, %xmm0 - movss %xmm0, VREG_REF_ADDRESS(rINST) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_rem_float_2addr: /* 0xca */ - /* rem_float/2addr vA, vB */ - movzx rINSTbl, %ecx # ecx <- A+ - sarl $4, rINST # rINST <- B - flds VREG_ADDRESS(rINST) # vB to fp stack - andb $0xf, %cl # ecx <- A - flds VREG_ADDRESS(%ecx) # vA to fp stack -1: - fprem - fstsw %ax - sahf - jp 1b - fstp %st(1) - fstps VREG_ADDRESS(%ecx) # %st to vA - CLEAR_REF %ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_add_double_2addr: /* 0xcb */ - movzx rINSTbl, %ecx # ecx <- A+ - andl $0xf, %ecx # ecx <- A - movsd VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src - sarl $4, rINST # rINST<- B - addsd VREG_ADDRESS(rINST), %xmm0 - movsd %xmm0, VREG_ADDRESS(%ecx) # vAA<- %xmm0 - pxor %xmm0, %xmm0 - movsd %xmm0, VREG_REF_ADDRESS(rINST) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_sub_double_2addr: /* 0xcc */ - movzx rINSTbl, %ecx # ecx <- A+ - andl $0xf, %ecx # ecx <- A - movsd VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src - sarl $4, rINST # rINST<- B - subsd VREG_ADDRESS(rINST), %xmm0 - movsd %xmm0, VREG_ADDRESS(%ecx) # vAA<- %xmm0 - pxor %xmm0, %xmm0 - movsd %xmm0, VREG_REF_ADDRESS(rINST) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_mul_double_2addr: /* 0xcd */ - movzx rINSTbl, %ecx # ecx <- A+ - andl $0xf, %ecx # ecx <- A - movsd VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src - sarl $4, rINST # rINST<- B - mulsd VREG_ADDRESS(rINST), %xmm0 - movsd %xmm0, VREG_ADDRESS(%ecx) # vAA<- %xmm0 - pxor %xmm0, %xmm0 - movsd %xmm0, VREG_REF_ADDRESS(rINST) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_div_double_2addr: /* 0xce */ - movzx rINSTbl, %ecx # ecx <- A+ - andl $0xf, %ecx # ecx <- A - movsd VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src - sarl $4, rINST # rINST<- B - divsd VREG_ADDRESS(rINST), %xmm0 - movsd %xmm0, VREG_ADDRESS(%ecx) # vAA<- %xmm0 - pxor %xmm0, %xmm0 - movsd %xmm0, VREG_REF_ADDRESS(rINST) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_rem_double_2addr: /* 0xcf */ - /* rem_double/2addr vA, vB */ - movzx rINSTbl, %ecx # ecx <- A+ - sarl $4, rINST # rINST <- B - fldl VREG_ADDRESS(rINST) # vB to fp stack - andb $0xf, %cl # ecx <- A - fldl VREG_ADDRESS(%ecx) # vA to fp stack -1: - fprem - fstsw %ax - sahf - jp 1b - fstp %st(1) - fstpl VREG_ADDRESS(%ecx) # %st to vA - CLEAR_WIDE_REF %ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_add_int_lit16: /* 0xd0 */ -/* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int/lit16, rsub-int, - * and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - movzbl rINSTbl, %eax # eax <- 000000BA - sarl $4, %eax # eax <- B - GET_VREG %eax, %eax # eax <- vB - movswl 2(rPC), %ecx # ecx <- ssssCCCC - andb $0xf, rINSTbl # rINST <- A - addl %ecx, %eax # for example: addl %ecx, %eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_rsub_int: /* 0xd1 */ -/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ -/* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int/lit16, rsub-int, - * and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - movzbl rINSTbl, %eax # eax <- 000000BA - sarl $4, %eax # eax <- B - GET_VREG %eax, %eax # eax <- vB - movswl 2(rPC), %ecx # ecx <- ssssCCCC - andb $0xf, rINSTbl # rINST <- A - subl %eax, %ecx # for example: addl %ecx, %eax - SET_VREG %ecx, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int_lit16: /* 0xd2 */ - /* mul/lit16 vA, vB, #+CCCC */ - /* Need A in rINST, ssssCCCC in ecx, vB in eax */ - movzbl rINSTbl, %eax # eax <- 000000BA - sarl $4, %eax # eax <- B - GET_VREG %eax, %eax # eax <- vB - movl rIBASE, %ecx - movswl 2(rPC), rIBASE # rIBASE <- ssssCCCC - andb $0xf, rINSTbl # rINST <- A - imull rIBASE, %eax # trashes rIBASE/edx - movl %ecx, rIBASE - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_div_int_lit16: /* 0xd3 */ -/* - * 32-bit binary div/rem operation. Handles special case of op0=minint and - * op1=-1. - */ - /* div/rem/lit16 vA, vB, #+CCCC */ - /* Need A in rINST, ssssCCCC in ecx, vB in eax */ - movzbl rINSTbl, %eax # eax <- 000000BA - sarl $4, %eax # eax <- B - GET_VREG %eax, %eax # eax <- vB - movswl 2(rPC), %ecx # ecx <- ssssCCCC - andb $0xf, rINSTbl # rINST <- A - testl %ecx, %ecx - je common_errDivideByZero - cmpl $-1, %ecx - jne .Lop_div_int_lit16_continue_div - cmpl $0x80000000, %eax - jne .Lop_div_int_lit16_continue_div - movl $0x80000000, %eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -.Lop_div_int_lit16_continue_div: - mov rIBASE, LOCAL0(%esp) - cltd - idivl %ecx - SET_VREG %eax, rINST - mov LOCAL0(%esp), rIBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int_lit16: /* 0xd4 */ -/* - * 32-bit binary div/rem operation. Handles special case of op0=minint and - * op1=-1. - */ - /* div/rem/lit16 vA, vB, #+CCCC */ - /* Need A in rINST, ssssCCCC in ecx, vB in eax */ - movzbl rINSTbl, %eax # eax <- 000000BA - sarl $4, %eax # eax <- B - GET_VREG %eax, %eax # eax <- vB - movswl 2(rPC), %ecx # ecx <- ssssCCCC - andb $0xf, rINSTbl # rINST <- A - testl %ecx, %ecx - je common_errDivideByZero - cmpl $-1, %ecx - jne .Lop_rem_int_lit16_continue_div - cmpl $0x80000000, %eax - jne .Lop_rem_int_lit16_continue_div - movl $0, %eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -.Lop_rem_int_lit16_continue_div: - mov rIBASE, LOCAL0(%esp) - cltd - idivl %ecx - SET_VREG rIBASE, rINST - mov LOCAL0(%esp), rIBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_and_int_lit16: /* 0xd5 */ -/* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int/lit16, rsub-int, - * and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - movzbl rINSTbl, %eax # eax <- 000000BA - sarl $4, %eax # eax <- B - GET_VREG %eax, %eax # eax <- vB - movswl 2(rPC), %ecx # ecx <- ssssCCCC - andb $0xf, rINSTbl # rINST <- A - andl %ecx, %eax # for example: addl %ecx, %eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_or_int_lit16: /* 0xd6 */ -/* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int/lit16, rsub-int, - * and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - movzbl rINSTbl, %eax # eax <- 000000BA - sarl $4, %eax # eax <- B - GET_VREG %eax, %eax # eax <- vB - movswl 2(rPC), %ecx # ecx <- ssssCCCC - andb $0xf, rINSTbl # rINST <- A - orl %ecx, %eax # for example: addl %ecx, %eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int_lit16: /* 0xd7 */ -/* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int/lit16, rsub-int, - * and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - movzbl rINSTbl, %eax # eax <- 000000BA - sarl $4, %eax # eax <- B - GET_VREG %eax, %eax # eax <- vB - movswl 2(rPC), %ecx # ecx <- ssssCCCC - andb $0xf, rINSTbl # rINST <- A - xorl %ecx, %eax # for example: addl %ecx, %eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_add_int_lit8: /* 0xd8 */ -/* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * For: add-int/lit8, rsub-int/lit8 - * and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - movzbl 2(rPC), %eax # eax <- BB - movsbl 3(rPC), %ecx # ecx <- ssssssCC - GET_VREG %eax, %eax # eax <- rBB - addl %ecx, %eax # ex: addl %ecx,%eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_rsub_int_lit8: /* 0xd9 */ -/* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * For: add-int/lit8, rsub-int/lit8 - * and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - movzbl 2(rPC), %eax # eax <- BB - movsbl 3(rPC), %ecx # ecx <- ssssssCC - GET_VREG %eax, %eax # eax <- rBB - subl %eax, %ecx # ex: addl %ecx,%eax - SET_VREG %ecx, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int_lit8: /* 0xda */ - /* mul/lit8 vAA, vBB, #+CC */ - movzbl 2(rPC), %eax # eax <- BB - movl rIBASE, %ecx - GET_VREG %eax, %eax # eax <- rBB - movsbl 3(rPC), rIBASE # rIBASE <- ssssssCC - imull rIBASE, %eax # trashes rIBASE/edx - movl %ecx, rIBASE - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_div_int_lit8: /* 0xdb */ -/* - * 32-bit div/rem "lit8" binary operation. Handles special case of - * op0=minint & op1=-1 - */ - /* div/rem/lit8 vAA, vBB, #+CC */ - movzbl 2(rPC), %eax # eax <- BB - movsbl 3(rPC), %ecx # ecx <- ssssssCC - GET_VREG %eax, %eax # eax <- rBB - testl %ecx, %ecx - je common_errDivideByZero - cmpl $0x80000000, %eax - jne .Lop_div_int_lit8_continue_div - cmpl $-1, %ecx - jne .Lop_div_int_lit8_continue_div - movl $0x80000000, %eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -.Lop_div_int_lit8_continue_div: - mov rIBASE, LOCAL0(%esp) - cltd - idivl %ecx - SET_VREG %eax, rINST - mov LOCAL0(%esp), rIBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int_lit8: /* 0xdc */ -/* - * 32-bit div/rem "lit8" binary operation. Handles special case of - * op0=minint & op1=-1 - */ - /* div/rem/lit8 vAA, vBB, #+CC */ - movzbl 2(rPC), %eax # eax <- BB - movsbl 3(rPC), %ecx # ecx <- ssssssCC - GET_VREG %eax, %eax # eax <- rBB - testl %ecx, %ecx - je common_errDivideByZero - cmpl $0x80000000, %eax - jne .Lop_rem_int_lit8_continue_div - cmpl $-1, %ecx - jne .Lop_rem_int_lit8_continue_div - movl $0, %eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -.Lop_rem_int_lit8_continue_div: - mov rIBASE, LOCAL0(%esp) - cltd - idivl %ecx - SET_VREG rIBASE, rINST - mov LOCAL0(%esp), rIBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_and_int_lit8: /* 0xdd */ -/* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * For: add-int/lit8, rsub-int/lit8 - * and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - movzbl 2(rPC), %eax # eax <- BB - movsbl 3(rPC), %ecx # ecx <- ssssssCC - GET_VREG %eax, %eax # eax <- rBB - andl %ecx, %eax # ex: addl %ecx,%eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_or_int_lit8: /* 0xde */ -/* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * For: add-int/lit8, rsub-int/lit8 - * and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - movzbl 2(rPC), %eax # eax <- BB - movsbl 3(rPC), %ecx # ecx <- ssssssCC - GET_VREG %eax, %eax # eax <- rBB - orl %ecx, %eax # ex: addl %ecx,%eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int_lit8: /* 0xdf */ -/* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * For: add-int/lit8, rsub-int/lit8 - * and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - movzbl 2(rPC), %eax # eax <- BB - movsbl 3(rPC), %ecx # ecx <- ssssssCC - GET_VREG %eax, %eax # eax <- rBB - xorl %ecx, %eax # ex: addl %ecx,%eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_shl_int_lit8: /* 0xe0 */ -/* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * For: add-int/lit8, rsub-int/lit8 - * and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - movzbl 2(rPC), %eax # eax <- BB - movsbl 3(rPC), %ecx # ecx <- ssssssCC - GET_VREG %eax, %eax # eax <- rBB - sall %cl, %eax # ex: addl %ecx,%eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_shr_int_lit8: /* 0xe1 */ -/* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * For: add-int/lit8, rsub-int/lit8 - * and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - movzbl 2(rPC), %eax # eax <- BB - movsbl 3(rPC), %ecx # ecx <- ssssssCC - GET_VREG %eax, %eax # eax <- rBB - sarl %cl, %eax # ex: addl %ecx,%eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_int_lit8: /* 0xe2 */ -/* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * For: add-int/lit8, rsub-int/lit8 - * and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - movzbl 2(rPC), %eax # eax <- BB - movsbl 3(rPC), %ecx # ecx <- ssssssCC - GET_VREG %eax, %eax # eax <- rBB - shrl %cl, %eax # ex: addl %ecx,%eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iget_quick: /* 0xe3 */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset@CCCC */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # vB (object we're operating on) - movzwl 2(rPC), %eax # eax <- field byte offset - testl %ecx, %ecx # is object null? - je common_errNullObject - movl (%ecx,%eax,1), %eax - andb $0xf,rINSTbl # rINST <- A - SET_VREG %eax, rINST # fp[A] <- value - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iget_wide_quick: /* 0xe4 */ - /* iget-wide-quick vA, vB, offset@CCCC */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # vB (object we're operating on) - movzwl 2(rPC), %eax # eax <- field byte offset - testl %ecx, %ecx # is object null? - je common_errNullObject - movq (%ecx,%eax,1), %xmm0 - andb $0xf, rINSTbl # rINST <- A - SET_WIDE_FP_VREG %xmm0, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iget_object_quick: /* 0xe5 */ - /* For: iget-object-quick */ - /* op vA, vB, offset@CCCC */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # vB (object we're operating on) - movzwl 2(rPC), %eax # eax <- field byte offset - movl %ecx, OUT_ARG0(%esp) - movl %eax, OUT_ARG1(%esp) - EXPORT_PC - call SYMBOL(artIGetObjectFromMterp) # (obj, offset) - movl rSELF, %ecx - RESTORE_IBASE_FROM_SELF %ecx - cmpl $0, THREAD_EXCEPTION_OFFSET(%ecx) - jnz MterpException # bail out - andb $0xf,rINSTbl # rINST <- A - SET_VREG_OBJECT %eax, rINST # fp[A] <- value - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iput_quick: /* 0xe6 */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # vB (object we're operating on) - testl %ecx, %ecx # is object null? - je common_errNullObject - andb $0xf, rINSTbl # rINST <- A - GET_VREG rINST, rINST # rINST <- v[A] - movzwl 2(rPC), %eax # eax <- field byte offset - movl rINST, (%ecx,%eax,1) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iput_wide_quick: /* 0xe7 */ - /* iput-wide-quick vA, vB, offset@CCCC */ - movzbl rINSTbl, %ecx # ecx<- BA - sarl $4, %ecx # ecx<- B - GET_VREG %ecx, %ecx # vB (object we're operating on) - testl %ecx, %ecx # is object null? - je common_errNullObject - movzwl 2(rPC), %eax # eax<- field byte offset - leal (%ecx,%eax,1), %ecx # ecx<- Address of 64-bit target - andb $0xf, rINSTbl # rINST<- A - GET_WIDE_FP_VREG %xmm0, rINST # xmm0<- fp[A]/fp[A+1] - movq %xmm0, (%ecx) # obj.field<- r0/r1 - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iput_object_quick: /* 0xe8 */ - EXPORT_PC - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG0(%esp) - movl rPC, OUT_ARG1(%esp) - REFRESH_INST 232 - movl rINST, OUT_ARG2(%esp) - call SYMBOL(MterpIputObjectQuick) - testb %al, %al - jz MterpException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual_quick: /* 0xe9 */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtualQuick - EXPORT_PC - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - REFRESH_INST 233 - movl rINST, OUT_ARG3(%esp) - call SYMBOL(MterpInvokeVirtualQuick) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - RESTORE_IBASE - FETCH_INST - GOTO_NEXT - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual_range_quick: /* 0xea */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtualQuickRange - EXPORT_PC - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - REFRESH_INST 234 - movl rINST, OUT_ARG3(%esp) - call SYMBOL(MterpInvokeVirtualQuickRange) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - RESTORE_IBASE - FETCH_INST - GOTO_NEXT - -/* ------------------------------ */ - .balign 128 -.L_op_iput_boolean_quick: /* 0xeb */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # vB (object we're operating on) - testl %ecx, %ecx # is object null? - je common_errNullObject - andb $0xf, rINSTbl # rINST <- A - GET_VREG rINST, rINST # rINST <- v[A] - movzwl 2(rPC), %eax # eax <- field byte offset - movb rINSTbl, (%ecx,%eax,1) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iput_byte_quick: /* 0xec */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # vB (object we're operating on) - testl %ecx, %ecx # is object null? - je common_errNullObject - andb $0xf, rINSTbl # rINST <- A - GET_VREG rINST, rINST # rINST <- v[A] - movzwl 2(rPC), %eax # eax <- field byte offset - movb rINSTbl, (%ecx,%eax,1) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iput_char_quick: /* 0xed */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # vB (object we're operating on) - testl %ecx, %ecx # is object null? - je common_errNullObject - andb $0xf, rINSTbl # rINST <- A - GET_VREG rINST, rINST # rINST <- v[A] - movzwl 2(rPC), %eax # eax <- field byte offset - movw rINSTw, (%ecx,%eax,1) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iput_short_quick: /* 0xee */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # vB (object we're operating on) - testl %ecx, %ecx # is object null? - je common_errNullObject - andb $0xf, rINSTbl # rINST <- A - GET_VREG rINST, rINST # rINST <- v[A] - movzwl 2(rPC), %eax # eax <- field byte offset - movw rINSTw, (%ecx,%eax,1) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iget_boolean_quick: /* 0xef */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset@CCCC */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # vB (object we're operating on) - movzwl 2(rPC), %eax # eax <- field byte offset - testl %ecx, %ecx # is object null? - je common_errNullObject - movsbl (%ecx,%eax,1), %eax - andb $0xf,rINSTbl # rINST <- A - SET_VREG %eax, rINST # fp[A] <- value - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iget_byte_quick: /* 0xf0 */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset@CCCC */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # vB (object we're operating on) - movzwl 2(rPC), %eax # eax <- field byte offset - testl %ecx, %ecx # is object null? - je common_errNullObject - movsbl (%ecx,%eax,1), %eax - andb $0xf,rINSTbl # rINST <- A - SET_VREG %eax, rINST # fp[A] <- value - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iget_char_quick: /* 0xf1 */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset@CCCC */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # vB (object we're operating on) - movzwl 2(rPC), %eax # eax <- field byte offset - testl %ecx, %ecx # is object null? - je common_errNullObject - movzwl (%ecx,%eax,1), %eax - andb $0xf,rINSTbl # rINST <- A - SET_VREG %eax, rINST # fp[A] <- value - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iget_short_quick: /* 0xf2 */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset@CCCC */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # vB (object we're operating on) - movzwl 2(rPC), %eax # eax <- field byte offset - testl %ecx, %ecx # is object null? - je common_errNullObject - movswl (%ecx,%eax,1), %eax - andb $0xf,rINSTbl # rINST <- A - SET_VREG %eax, rINST # fp[A] <- value - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f3: /* 0xf3 */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f4: /* 0xf4 */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f5: /* 0xf5 */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f6: /* 0xf6 */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f7: /* 0xf7 */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f8: /* 0xf8 */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f9: /* 0xf9 */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_polymorphic: /* 0xfa */ - /* - * invoke-polymorphic handler wrapper. - */ - /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ - .extern MterpInvokePolymorphic - EXPORT_PC - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - REFRESH_INST 250 - movl rINST, OUT_ARG3(%esp) - call SYMBOL(MterpInvokePolymorphic) - testb %al, %al - jz MterpException - ADVANCE_PC 4 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - RESTORE_IBASE - FETCH_INST - GOTO_NEXT - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_polymorphic_range: /* 0xfb */ - /* - * invoke-polymorphic handler wrapper. - */ - /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ - .extern MterpInvokePolymorphicRange - EXPORT_PC - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - REFRESH_INST 251 - movl rINST, OUT_ARG3(%esp) - call SYMBOL(MterpInvokePolymorphicRange) - testb %al, %al - jz MterpException - ADVANCE_PC 4 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - RESTORE_IBASE - FETCH_INST - GOTO_NEXT - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_custom: /* 0xfc */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeCustom - EXPORT_PC - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - REFRESH_INST 252 - movl rINST, OUT_ARG3(%esp) - call SYMBOL(MterpInvokeCustom) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - RESTORE_IBASE - FETCH_INST - GOTO_NEXT - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_custom_range: /* 0xfd */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeCustomRange - EXPORT_PC - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - REFRESH_INST 253 - movl rINST, OUT_ARG3(%esp) - call SYMBOL(MterpInvokeCustomRange) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - RESTORE_IBASE - FETCH_INST - GOTO_NEXT - -/* ------------------------------ */ - .balign 128 -.L_op_const_method_handle: /* 0xfe */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstMethodHandle - EXPORT_PC - movzwl 2(rPC), %eax # eax <- BBBB - movl %eax, OUT_ARG0(%esp) - movl rINST, OUT_ARG1(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) - call SYMBOL(MterpConstMethodHandle) # (index, tgt_reg, shadow_frame, self) - RESTORE_IBASE - testb %al, %al - jnz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_const_method_type: /* 0xff */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstMethodType - EXPORT_PC - movzwl 2(rPC), %eax # eax <- BBBB - movl %eax, OUT_ARG0(%esp) - movl rINST, OUT_ARG1(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) - call SYMBOL(MterpConstMethodType) # (index, tgt_reg, shadow_frame, self) - RESTORE_IBASE - testb %al, %al - jnz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - .balign 128 - - OBJECT_TYPE(artMterpAsmInstructionEnd) - ASM_HIDDEN SYMBOL(artMterpAsmInstructionEnd) - .global SYMBOL(artMterpAsmInstructionEnd) -SYMBOL(artMterpAsmInstructionEnd): - - OBJECT_TYPE(artMterpAsmAltInstructionStart) - ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionStart) - .global SYMBOL(artMterpAsmAltInstructionStart) - .text -SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_nop: /* 0x00 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(0*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move: /* 0x01 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(1*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_from16: /* 0x02 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(2*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_16: /* 0x03 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(3*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_wide: /* 0x04 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(4*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_wide_from16: /* 0x05 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(5*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_wide_16: /* 0x06 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(6*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_object: /* 0x07 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(7*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_object_from16: /* 0x08 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(8*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_object_16: /* 0x09 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(9*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_result: /* 0x0a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(10*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_result_wide: /* 0x0b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(11*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_result_object: /* 0x0c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(12*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_exception: /* 0x0d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(13*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_void: /* 0x0e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(14*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return: /* 0x0f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(15*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_wide: /* 0x10 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(16*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_object: /* 0x11 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(17*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_4: /* 0x12 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(18*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_16: /* 0x13 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(19*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const: /* 0x14 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(20*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_high16: /* 0x15 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(21*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide_16: /* 0x16 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(22*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide_32: /* 0x17 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(23*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide: /* 0x18 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(24*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide_high16: /* 0x19 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(25*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_string: /* 0x1a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(26*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_string_jumbo: /* 0x1b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(27*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_class: /* 0x1c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(28*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_monitor_enter: /* 0x1d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(29*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_monitor_exit: /* 0x1e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(30*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_check_cast: /* 0x1f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(31*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_instance_of: /* 0x20 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(32*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_array_length: /* 0x21 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(33*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_new_instance: /* 0x22 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(34*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_new_array: /* 0x23 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(35*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_filled_new_array: /* 0x24 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(36*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_filled_new_array_range: /* 0x25 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(37*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_fill_array_data: /* 0x26 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(38*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_throw: /* 0x27 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(39*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_goto: /* 0x28 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(40*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_goto_16: /* 0x29 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(41*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_goto_32: /* 0x2a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(42*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_packed_switch: /* 0x2b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(43*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sparse_switch: /* 0x2c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(44*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpl_float: /* 0x2d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(45*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpg_float: /* 0x2e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(46*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpl_double: /* 0x2f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(47*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpg_double: /* 0x30 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(48*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmp_long: /* 0x31 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(49*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_eq: /* 0x32 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(50*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_ne: /* 0x33 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(51*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_lt: /* 0x34 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(52*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_ge: /* 0x35 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(53*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_gt: /* 0x36 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(54*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_le: /* 0x37 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(55*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_eqz: /* 0x38 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(56*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_nez: /* 0x39 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(57*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_ltz: /* 0x3a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(58*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_gez: /* 0x3b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(59*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_gtz: /* 0x3c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(60*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_lez: /* 0x3d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(61*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_3e: /* 0x3e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(62*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_3f: /* 0x3f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(63*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_40: /* 0x40 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(64*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_41: /* 0x41 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(65*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_42: /* 0x42 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(66*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_43: /* 0x43 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(67*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget: /* 0x44 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(68*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_wide: /* 0x45 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(69*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_object: /* 0x46 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(70*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_boolean: /* 0x47 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(71*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_byte: /* 0x48 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(72*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_char: /* 0x49 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(73*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_short: /* 0x4a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(74*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput: /* 0x4b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(75*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_wide: /* 0x4c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(76*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_object: /* 0x4d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(77*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_boolean: /* 0x4e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(78*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_byte: /* 0x4f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(79*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_char: /* 0x50 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(80*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_short: /* 0x51 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(81*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget: /* 0x52 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(82*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_wide: /* 0x53 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(83*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_object: /* 0x54 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(84*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_boolean: /* 0x55 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(85*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_byte: /* 0x56 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(86*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_char: /* 0x57 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(87*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_short: /* 0x58 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(88*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput: /* 0x59 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(89*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_wide: /* 0x5a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(90*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_object: /* 0x5b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(91*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_boolean: /* 0x5c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(92*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_byte: /* 0x5d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(93*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_char: /* 0x5e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(94*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_short: /* 0x5f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(95*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget: /* 0x60 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(96*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_wide: /* 0x61 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(97*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_object: /* 0x62 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(98*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_boolean: /* 0x63 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(99*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_byte: /* 0x64 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(100*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_char: /* 0x65 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(101*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_short: /* 0x66 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(102*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput: /* 0x67 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(103*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_wide: /* 0x68 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(104*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_object: /* 0x69 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(105*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_boolean: /* 0x6a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(106*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_byte: /* 0x6b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(107*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_char: /* 0x6c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(108*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_short: /* 0x6d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(109*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual: /* 0x6e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(110*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_super: /* 0x6f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(111*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_direct: /* 0x70 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(112*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_static: /* 0x71 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(113*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_interface: /* 0x72 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(114*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_void_no_barrier: /* 0x73 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(115*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual_range: /* 0x74 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(116*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_super_range: /* 0x75 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(117*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_direct_range: /* 0x76 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(118*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_static_range: /* 0x77 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(119*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_interface_range: /* 0x78 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(120*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_79: /* 0x79 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(121*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_7a: /* 0x7a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(122*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_int: /* 0x7b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(123*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_not_int: /* 0x7c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(124*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_long: /* 0x7d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(125*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_not_long: /* 0x7e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(126*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_float: /* 0x7f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(127*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_double: /* 0x80 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(128*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_long: /* 0x81 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(129*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_float: /* 0x82 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(130*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_double: /* 0x83 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(131*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_long_to_int: /* 0x84 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(132*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_long_to_float: /* 0x85 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(133*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_long_to_double: /* 0x86 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(134*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_float_to_int: /* 0x87 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(135*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_float_to_long: /* 0x88 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(136*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_float_to_double: /* 0x89 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(137*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_double_to_int: /* 0x8a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(138*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_double_to_long: /* 0x8b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(139*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_double_to_float: /* 0x8c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(140*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_byte: /* 0x8d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(141*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_char: /* 0x8e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(142*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_short: /* 0x8f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(143*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int: /* 0x90 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(144*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_int: /* 0x91 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(145*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int: /* 0x92 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(146*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int: /* 0x93 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(147*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int: /* 0x94 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(148*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int: /* 0x95 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(149*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int: /* 0x96 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(150*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int: /* 0x97 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(151*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_int: /* 0x98 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(152*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_int: /* 0x99 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(153*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_int: /* 0x9a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(154*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_long: /* 0x9b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(155*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_long: /* 0x9c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(156*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_long: /* 0x9d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(157*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_long: /* 0x9e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(158*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_long: /* 0x9f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(159*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_long: /* 0xa0 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(160*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_long: /* 0xa1 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(161*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_long: /* 0xa2 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(162*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_long: /* 0xa3 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(163*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_long: /* 0xa4 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(164*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_long: /* 0xa5 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(165*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_float: /* 0xa6 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(166*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_float: /* 0xa7 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(167*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_float: /* 0xa8 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(168*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_float: /* 0xa9 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(169*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_float: /* 0xaa */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(170*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_double: /* 0xab */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(171*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_double: /* 0xac */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(172*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_double: /* 0xad */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(173*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_double: /* 0xae */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(174*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_double: /* 0xaf */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(175*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int_2addr: /* 0xb0 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(176*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_int_2addr: /* 0xb1 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(177*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int_2addr: /* 0xb2 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(178*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int_2addr: /* 0xb3 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(179*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int_2addr: /* 0xb4 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(180*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int_2addr: /* 0xb5 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(181*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int_2addr: /* 0xb6 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(182*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int_2addr: /* 0xb7 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(183*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_int_2addr: /* 0xb8 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(184*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_int_2addr: /* 0xb9 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(185*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_int_2addr: /* 0xba */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(186*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_long_2addr: /* 0xbb */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(187*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_long_2addr: /* 0xbc */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(188*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_long_2addr: /* 0xbd */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(189*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_long_2addr: /* 0xbe */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(190*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_long_2addr: /* 0xbf */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(191*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_long_2addr: /* 0xc0 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(192*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_long_2addr: /* 0xc1 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(193*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_long_2addr: /* 0xc2 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(194*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_long_2addr: /* 0xc3 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(195*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_long_2addr: /* 0xc4 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(196*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_long_2addr: /* 0xc5 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(197*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_float_2addr: /* 0xc6 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(198*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_float_2addr: /* 0xc7 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(199*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_float_2addr: /* 0xc8 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(200*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_float_2addr: /* 0xc9 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(201*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_float_2addr: /* 0xca */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(202*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_double_2addr: /* 0xcb */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(203*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_double_2addr: /* 0xcc */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(204*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_double_2addr: /* 0xcd */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(205*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_double_2addr: /* 0xce */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(206*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_double_2addr: /* 0xcf */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(207*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int_lit16: /* 0xd0 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(208*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rsub_int: /* 0xd1 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(209*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int_lit16: /* 0xd2 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(210*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int_lit16: /* 0xd3 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(211*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int_lit16: /* 0xd4 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(212*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int_lit16: /* 0xd5 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(213*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int_lit16: /* 0xd6 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(214*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int_lit16: /* 0xd7 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(215*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int_lit8: /* 0xd8 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(216*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rsub_int_lit8: /* 0xd9 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(217*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int_lit8: /* 0xda */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(218*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int_lit8: /* 0xdb */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(219*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int_lit8: /* 0xdc */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(220*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int_lit8: /* 0xdd */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(221*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int_lit8: /* 0xde */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(222*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int_lit8: /* 0xdf */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(223*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_int_lit8: /* 0xe0 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(224*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_int_lit8: /* 0xe1 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(225*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_int_lit8: /* 0xe2 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(226*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_quick: /* 0xe3 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(227*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_wide_quick: /* 0xe4 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(228*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_object_quick: /* 0xe5 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(229*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_quick: /* 0xe6 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(230*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_wide_quick: /* 0xe7 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(231*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_object_quick: /* 0xe8 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(232*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual_quick: /* 0xe9 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(233*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual_range_quick: /* 0xea */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(234*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_boolean_quick: /* 0xeb */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(235*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_byte_quick: /* 0xec */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(236*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_char_quick: /* 0xed */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(237*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_short_quick: /* 0xee */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(238*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_boolean_quick: /* 0xef */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(239*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_byte_quick: /* 0xf0 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(240*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_char_quick: /* 0xf1 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(241*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_short_quick: /* 0xf2 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(242*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f3: /* 0xf3 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(243*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f4: /* 0xf4 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(244*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f5: /* 0xf5 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(245*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f6: /* 0xf6 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(246*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f7: /* 0xf7 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(247*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f8: /* 0xf8 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(248*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f9: /* 0xf9 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(249*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_polymorphic: /* 0xfa */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(250*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_polymorphic_range: /* 0xfb */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(251*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_custom: /* 0xfc */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(252*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_custom_range: /* 0xfd */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(253*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_method_handle: /* 0xfe */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(254*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_method_type: /* 0xff */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(255*128) - - .balign 128 - - OBJECT_TYPE(artMterpAsmAltInstructionEnd) - ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionEnd) - .global SYMBOL(artMterpAsmAltInstructionEnd) -SYMBOL(artMterpAsmAltInstructionEnd): - -/* - * =========================================================================== - * Common subroutines and data - * =========================================================================== - */ - - .text - .align 2 - -/* - * We've detected a condition that will result in an exception, but the exception - * has not yet been thrown. Just bail out to the reference interpreter to deal with it. - * TUNING: for consistency, we may want to just go ahead and handle these here. - */ -common_errDivideByZero: - EXPORT_PC -#if MTERP_LOGGING - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - lea OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - call SYMBOL(MterpLogDivideByZeroException) -#endif - jmp MterpCommonFallback - -common_errArrayIndex: - EXPORT_PC -#if MTERP_LOGGING - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - lea OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - call SYMBOL(MterpLogArrayIndexException) -#endif - jmp MterpCommonFallback - -common_errNegativeArraySize: - EXPORT_PC -#if MTERP_LOGGING - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - lea OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - call SYMBOL(MterpLogNegativeArraySizeException) -#endif - jmp MterpCommonFallback - -common_errNoSuchMethod: - EXPORT_PC -#if MTERP_LOGGING - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - lea OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - call SYMBOL(MterpLogNoSuchMethodException) -#endif - jmp MterpCommonFallback - -common_errNullObject: - EXPORT_PC -#if MTERP_LOGGING - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - lea OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - call SYMBOL(MterpLogNullObjectException) -#endif - jmp MterpCommonFallback - -common_exceptionThrown: - EXPORT_PC -#if MTERP_LOGGING - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - lea OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG0(%esp) - call SYMBOL(MterpLogExceptionThrownException) -#endif - jmp MterpCommonFallback - -MterpSuspendFallback: - EXPORT_PC -#if MTERP_LOGGING - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - lea OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG0(%esp) - movl THREAD_FLAGS_OFFSET(%eax), %eax - movl %eax, OUT_ARG2(%esp) - call SYMBOL(MterpLogSuspendFallback) -#endif - jmp MterpCommonFallback - -/* - * If we're here, something is out of the ordinary. If there is a pending - * exception, handle it. Otherwise, roll back and retry with the reference - * interpreter. - */ -MterpPossibleException: - movl rSELF, %eax - testl $-1, THREAD_EXCEPTION_OFFSET(%eax) - jz MterpFallback - /* intentional fallthrough - handle pending exception. */ - -/* - * On return from a runtime helper routine, we've found a pending exception. - * Can we handle it here - or need to bail out to caller? - * - */ -MterpException: - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - lea OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - call SYMBOL(MterpHandleException) - testb %al, %al - jz MterpExceptionReturn - movl OFF_FP_DEX_INSTRUCTIONS(rFP), %eax - movl OFF_FP_DEX_PC(rFP), %ecx - lea (%eax, %ecx, 2), rPC - movl rPC, OFF_FP_DEX_PC_PTR(rFP) - /* Do we need to switch interpreters? */ - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - /* resume execution at catch block */ - REFRESH_IBASE - FETCH_INST - GOTO_NEXT - /* NOTE: no fallthrough */ - -/* - * Common handling for branches with support for Jit profiling. - * On entry: - * rINST <= signed offset - * condition bits <= set to establish sign of offset (use "NoFlags" entry if not) - * - * We have quite a few different cases for branch profiling, OSR detection and - * suspend check support here. - * - * Taken backward branches: - * If profiling active, do hotness countdown and report if we hit zero. - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * Is there a pending suspend request? If so, suspend. - * - * Taken forward branches and not-taken backward branches: - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * - * Our most common case is expected to be a taken backward branch with active jit profiling, - * but no full OSR check and no pending suspend request. - * Next most common case is not-taken branch with no full OSR check. - * - */ -MterpCommonTakenBranch: - jg .L_forward_branch # don't add forward branches to hotness -/* - * We need to subtract 1 from positive values and we should not see 0 here, - * so we may use the result of the comparison with -1. - */ -#if JIT_CHECK_OSR != -1 -# error "JIT_CHECK_OSR must be -1." -#endif - cmpw $JIT_CHECK_OSR, rPROFILE - je .L_osr_check - decw rPROFILE - je .L_add_batch # counted down to zero - report -.L_resume_backward_branch: - movl rSELF, %eax - testl $(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(%eax) - leal (rPC, rINST, 2), rPC - FETCH_INST - jnz .L_suspend_request_pending - REFRESH_IBASE - GOTO_NEXT - -.L_suspend_request_pending: - EXPORT_PC - movl %eax, OUT_ARG0(%esp) # rSELF in eax - call SYMBOL(MterpSuspendCheck) # (self) - testb %al, %al - jnz MterpFallback - REFRESH_IBASE # might have changed during suspend - GOTO_NEXT - -.L_no_count_backwards: - cmpw $JIT_CHECK_OSR, rPROFILE # possible OSR re-entry? - jne .L_resume_backward_branch -.L_osr_check: - EXPORT_PC - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - movl rINST, OUT_ARG2(%esp) - call SYMBOL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) - testb %al, %al - jz .L_resume_backward_branch - jmp MterpOnStackReplacement - -.L_forward_branch: - cmpw $JIT_CHECK_OSR, rPROFILE # possible OSR re-entry? - je .L_check_osr_forward -.L_resume_forward_branch: - leal (rPC, rINST, 2), rPC - FETCH_INST - GOTO_NEXT - -.L_check_osr_forward: - EXPORT_PC - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - movl rINST, OUT_ARG2(%esp) - call SYMBOL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) - testb %al, %al - REFRESH_IBASE - jz .L_resume_forward_branch - jmp MterpOnStackReplacement - -.L_add_batch: - movl OFF_FP_METHOD(rFP), %eax - movl %eax, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - movl rSELF, %eax - movl %eax, OUT_ARG2(%esp) - call SYMBOL(MterpAddHotnessBatch) # (method, shadow_frame, self) - jmp .L_no_count_backwards - -/* - * Entered from the conditional branch handlers when OSR check request active on - * not-taken path. All Dalvik not-taken conditional branch offsets are 2. - */ -.L_check_not_taken_osr: - EXPORT_PC - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - movl $2, OUT_ARG2(%esp) - call SYMBOL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) - testb %al, %al - REFRESH_IBASE - jnz MterpOnStackReplacement - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* - * On-stack replacement has happened, and now we've returned from the compiled method. - */ -MterpOnStackReplacement: -#if MTERP_LOGGING - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - lea OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - movl rINST, OUT_ARG2(%esp) - call SYMBOL(MterpLogOSR) -#endif - movl $1, %eax - jmp MterpDone - -/* - * Bail out to reference interpreter. - */ -MterpFallback: - EXPORT_PC -#if MTERP_LOGGING - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - lea OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - call SYMBOL(MterpLogFallback) -#endif -MterpCommonFallback: - xor %eax, %eax - jmp MterpDone - -/* - * On entry: - * uint32_t* rFP (should still be live, pointer to base of vregs) - */ -MterpExceptionReturn: - movl $1, %eax - jmp MterpDone -MterpReturn: - movl OFF_FP_RESULT_REGISTER(rFP), %edx - movl %eax, (%edx) - movl %ecx, 4(%edx) - mov $1, %eax -MterpDone: -/* - * At this point, we expect rPROFILE to be non-zero. If negative, hotness is disabled or we're - * checking for OSR. If greater than zero, we might have unreported hotness to register - * (the difference between the ending rPROFILE and the cached hotness counter). rPROFILE - * should only reach zero immediately after a hotness decrement, and is then reset to either - * a negative special state or the new non-zero countdown value. - */ - cmpw $0, rPROFILE - jle MRestoreFrame # if > 0, we may have some counts to report. - - movl %eax, rINST # stash return value - /* Report cached hotness counts */ - movl OFF_FP_METHOD(rFP), %eax - movl %eax, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - movl rSELF, %eax - movl %eax, OUT_ARG2(%esp) - call SYMBOL(MterpAddHotnessBatch) # (method, shadow_frame, self) - movl rINST, %eax # restore return value - - /* pop up frame */ -MRestoreFrame: - addl $FRAME_SIZE, %esp - .cfi_adjust_cfa_offset -FRAME_SIZE - - /* Restore callee save register */ - POP %ebx - POP %esi - POP %edi - POP %ebp - ret - .cfi_endproc - SIZE(ExecuteMterpImpl,ExecuteMterpImpl) - diff --git a/runtime/interpreter/mterp/out/mterp_x86_64.S b/runtime/interpreter/mterp/out/mterp_x86_64.S deleted file mode 100644 index 96f5204063..0000000000 --- a/runtime/interpreter/mterp/out/mterp_x86_64.S +++ /dev/null @@ -1,11040 +0,0 @@ -/* DO NOT EDIT: This file was generated by gen-mterp.py. */ -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - Art assembly interpreter notes: - - First validate assembly code by implementing ExecuteXXXImpl() style body (doesn't - handle invoke, allows higher-level code to create frame & shadow frame. - - Once that's working, support direct entry code & eliminate shadow frame (and - excess locals allocation. - - Some (hopefully) temporary ugliness. We'll treat rFP as pointing to the - base of the vreg array within the shadow frame. Access the other fields, - dex_pc_, method_ and number_of_vregs_ via negative offsets. For now, we'll continue - the shadow frame mechanism of double-storing object references - via rFP & - number_of_vregs_. - - */ - -/* -x86_64 ABI general notes: - -Caller save set: - rax, rdx, rcx, rsi, rdi, r8-r11, st(0)-st(7) -Callee save set: - rbx, rbp, r12-r15 -Return regs: - 32-bit in eax - 64-bit in rax - fp on xmm0 - -First 8 fp parameters came in xmm0-xmm7. -First 6 non-fp parameters came in rdi, rsi, rdx, rcx, r8, r9. -Other parameters passed on stack, pushed right-to-left. On entry to target, first -param is at 8(%esp). Traditional entry code is: - -Stack must be 16-byte aligned to support SSE in native code. - -If we're not doing variable stack allocation (alloca), the frame pointer can be -eliminated and all arg references adjusted to be esp relative. -*/ - -/* -Mterp and x86_64 notes: - -Some key interpreter variables will be assigned to registers. - - nick reg purpose - rPROFILE rbp countdown register for jit profiling - rPC r12 interpreted program counter, used for fetching instructions - rFP r13 interpreted frame pointer, used for accessing locals and args - rINSTw bx first 16-bit code of current instruction - rINSTbl bl opcode portion of instruction word - rINSTbh bh high byte of inst word, usually contains src/tgt reg names - rIBASE r14 base of instruction handler table - rREFS r15 base of object references in shadow frame. - -Notes: - o High order 16 bits of ebx must be zero on entry to handler - o rPC, rFP, rINSTw/rINSTbl valid on handler entry and exit - o eax and ecx are scratch, rINSTw/ebx sometimes scratch - -Macros are provided for common operations. Each macro MUST emit only -one instruction to make instruction-counting easier. They MUST NOT alter -unspecified registers or condition codes. -*/ - -/* - * This is a #include, not a %include, because we want the C pre-processor - * to expand the macros into assembler assignment statements. - */ -#include "asm_support.h" -#include "interpreter/cfi_asm_support.h" - -/* - * Handle mac compiler specific - */ -#if defined(__APPLE__) - #define MACRO_LITERAL(value) $(value) - #define FUNCTION_TYPE(name) - #define OBJECT_TYPE(name) - #define SIZE(start,end) - // Mac OS' symbols have an _ prefix. - #define SYMBOL(name) _ ## name - #define ASM_HIDDEN .private_extern -#else - #define MACRO_LITERAL(value) $value - #define FUNCTION_TYPE(name) .type name, @function - #define OBJECT_TYPE(name) .type name, @object - #define SIZE(start,end) .size start, .-end - #define SYMBOL(name) name - #define ASM_HIDDEN .hidden -#endif - -.macro PUSH _reg - pushq \_reg - .cfi_adjust_cfa_offset 8 - .cfi_rel_offset \_reg, 0 -.endm - -.macro POP _reg - popq \_reg - .cfi_adjust_cfa_offset -8 - .cfi_restore \_reg -.endm - -/* - * Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs. So, - * to access other shadow frame fields, we need to use a backwards offset. Define those here. - */ -#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) -#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) -#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) -#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) -#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) -#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) -#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) -#define OFF_FP_DEX_INSTRUCTIONS OFF_FP(SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET) -#define OFF_FP_COUNTDOWN_OFFSET OFF_FP(SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET) -#define OFF_FP_SHADOWFRAME (-SHADOWFRAME_VREGS_OFFSET) - -/* Frame size must be 16-byte aligned. - * Remember about 8 bytes for return address + 6 * 8 for spills. - */ -#define FRAME_SIZE 8 - -/* Frame diagram while executing ExecuteMterpImpl, high to low addresses */ -#define IN_ARG3 %rcx -#define IN_ARG2 %rdx -#define IN_ARG1 %rsi -#define IN_ARG0 %rdi -/* Spill offsets relative to %esp */ -#define SELF_SPILL (FRAME_SIZE - 8) -/* Out Args */ -#define OUT_ARG3 %rcx -#define OUT_ARG2 %rdx -#define OUT_ARG1 %rsi -#define OUT_ARG0 %rdi -#define OUT_32_ARG3 %ecx -#define OUT_32_ARG2 %edx -#define OUT_32_ARG1 %esi -#define OUT_32_ARG0 %edi -#define OUT_FP_ARG1 %xmm1 -#define OUT_FP_ARG0 %xmm0 - -/* During bringup, we'll use the shadow frame model instead of rFP */ -/* single-purpose registers, given names for clarity */ -#define rSELF SELF_SPILL(%rsp) -#define rPC %r12 -#define CFI_DEX 12 // DWARF register number of the register holding dex-pc (rPC). -#define CFI_TMP 5 // DWARF register number of the first argument register (rdi). -#define rFP %r13 -#define rINST %ebx -#define rINSTq %rbx -#define rINSTw %bx -#define rINSTbh %bh -#define rINSTbl %bl -#define rIBASE %r14 -#define rREFS %r15 -#define rPROFILE %ebp - -#define MTERP_LOGGING 0 - -/* - * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must - * be done *before* something throws. - * - * It's okay to do this more than once. - * - * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped - * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction - * offset into the code_items_[] array. For effiency, we will "export" the - * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC - * to convert to a dex pc when needed. - */ -.macro EXPORT_PC - movq rPC, OFF_FP_DEX_PC_PTR(rFP) -.endm - -/* - * Refresh handler table. - * IBase handles uses the caller save register so we must restore it after each call. - * Also it is used as a result of some 64-bit operations (like imul) and we should - * restore it in such cases also. - * - */ -.macro REFRESH_IBASE_REG self_reg - movq THREAD_CURRENT_IBASE_OFFSET(\self_reg), rIBASE -.endm -.macro REFRESH_IBASE - movq rSELF, rIBASE - REFRESH_IBASE_REG rIBASE -.endm - -/* - * Refresh rINST. - * At enter to handler rINST does not contain the opcode number. - * However some utilities require the full value, so this macro - * restores the opcode number. - */ -.macro REFRESH_INST _opnum - movb rINSTbl, rINSTbh - movb $\_opnum, rINSTbl -.endm - -/* - * Fetch the next instruction from rPC into rINSTw. Does not advance rPC. - */ -.macro FETCH_INST - movzwq (rPC), rINSTq -.endm - -/* - * Remove opcode from rINST, compute the address of handler and jump to it. - */ -.macro GOTO_NEXT - movzx rINSTbl,%eax - movzbl rINSTbh,rINST - shll MACRO_LITERAL(7), %eax - addq rIBASE, %rax - jmp *%rax -.endm - -/* - * Advance rPC by instruction count. - */ -.macro ADVANCE_PC _count - leaq 2*\_count(rPC), rPC -.endm - -/* - * Advance rPC by instruction count, fetch instruction and jump to handler. - */ -.macro ADVANCE_PC_FETCH_AND_GOTO_NEXT _count - ADVANCE_PC \_count - FETCH_INST - GOTO_NEXT -.endm - -/* - * Get/set the 32-bit value from a Dalvik register. - */ -#define VREG_ADDRESS(_vreg) (rFP,_vreg,4) -#define VREG_REF_ADDRESS(_vreg) (rREFS,_vreg,4) - -.macro GET_VREG _reg _vreg - movl (rFP,\_vreg,4), \_reg -.endm - -/* Read wide value. */ -.macro GET_WIDE_VREG _reg _vreg - movq (rFP,\_vreg,4), \_reg -.endm - -.macro SET_VREG _reg _vreg - movl \_reg, (rFP,\_vreg,4) - movl MACRO_LITERAL(0), (rREFS,\_vreg,4) -.endm - -/* Write wide value. reg is clobbered. */ -.macro SET_WIDE_VREG _reg _vreg - movq \_reg, (rFP,\_vreg,4) - xorq \_reg, \_reg - movq \_reg, (rREFS,\_vreg,4) -.endm - -.macro SET_VREG_OBJECT _reg _vreg - movl \_reg, (rFP,\_vreg,4) - movl \_reg, (rREFS,\_vreg,4) -.endm - -.macro GET_VREG_HIGH _reg _vreg - movl 4(rFP,\_vreg,4), \_reg -.endm - -.macro SET_VREG_HIGH _reg _vreg - movl \_reg, 4(rFP,\_vreg,4) - movl MACRO_LITERAL(0), 4(rREFS,\_vreg,4) -.endm - -.macro CLEAR_REF _vreg - movl MACRO_LITERAL(0), (rREFS,\_vreg,4) -.endm - -.macro CLEAR_WIDE_REF _vreg - movl MACRO_LITERAL(0), (rREFS,\_vreg,4) - movl MACRO_LITERAL(0), 4(rREFS,\_vreg,4) -.endm - -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -/* - * Interpreter entry point. - */ - - .text - ASM_HIDDEN SYMBOL(ExecuteMterpImpl) - .global SYMBOL(ExecuteMterpImpl) - FUNCTION_TYPE(ExecuteMterpImpl) - -/* - * On entry: - * 0 Thread* self - * 1 insns_ - * 2 ShadowFrame - * 3 JValue* result_register - * - */ - -SYMBOL(ExecuteMterpImpl): - .cfi_startproc - .cfi_def_cfa rsp, 8 - - /* Spill callee save regs */ - PUSH %rbx - PUSH %rbp - PUSH %r12 - PUSH %r13 - PUSH %r14 - PUSH %r15 - - /* Allocate frame */ - subq $FRAME_SIZE, %rsp - .cfi_adjust_cfa_offset FRAME_SIZE - - /* Remember the return register */ - movq IN_ARG3, SHADOWFRAME_RESULT_REGISTER_OFFSET(IN_ARG2) - - /* Remember the code_item */ - movq IN_ARG1, SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET(IN_ARG2) - - /* set up "named" registers */ - movl SHADOWFRAME_NUMBER_OF_VREGS_OFFSET(IN_ARG2), %eax - leaq SHADOWFRAME_VREGS_OFFSET(IN_ARG2), rFP - leaq (rFP, %rax, 4), rREFS - movl SHADOWFRAME_DEX_PC_OFFSET(IN_ARG2), %eax - leaq (IN_ARG1, %rax, 2), rPC - CFI_DEFINE_DEX_PC_WITH_OFFSET(CFI_TMP, CFI_DEX, 0) - EXPORT_PC - - /* Starting ibase */ - movq IN_ARG0, rSELF - REFRESH_IBASE_REG IN_ARG0 - - /* Set up for backwards branches & osr profiling */ - movq IN_ARG0, OUT_ARG2 /* Set up OUT_ARG2 before clobbering IN_ARG0 */ - movq OFF_FP_METHOD(rFP), OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - call SYMBOL(MterpSetUpHotnessCountdown) - movswl %ax, rPROFILE - - /* start executing the instruction at rPC */ - FETCH_INST - GOTO_NEXT - /* NOTE: no fallthrough */ - - OBJECT_TYPE(artMterpAsmInstructionStart) - ASM_HIDDEN SYMBOL(artMterpAsmInstructionStart) - .global SYMBOL(artMterpAsmInstructionStart) -SYMBOL(artMterpAsmInstructionStart) = .L_op_nop - .text - -/* ------------------------------ */ - .balign 128 -.L_op_nop: /* 0x00 */ - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_move: /* 0x01 */ - /* for move, move-object, long-to-int */ - /* op vA, vB */ - movl rINST, %eax # eax <- BA - andb $0xf, %al # eax <- A - shrl $4, rINST # rINST <- B - GET_VREG %edx, rINSTq - .if 0 - SET_VREG_OBJECT %edx, %rax # fp[A] <- fp[B] - .else - SET_VREG %edx, %rax # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_move_from16: /* 0x02 */ - /* for: move/from16, move-object/from16 */ - /* op vAA, vBBBB */ - movzwq 2(rPC), %rax # eax <- BBBB - GET_VREG %edx, %rax # edx <- fp[BBBB] - .if 0 - SET_VREG_OBJECT %edx, rINSTq # fp[A] <- fp[B] - .else - SET_VREG %edx, rINSTq # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_move_16: /* 0x03 */ - /* for: move/16, move-object/16 */ - /* op vAAAA, vBBBB */ - movzwq 4(rPC), %rcx # ecx <- BBBB - movzwq 2(rPC), %rax # eax <- AAAA - GET_VREG %edx, %rcx - .if 0 - SET_VREG_OBJECT %edx, %rax # fp[A] <- fp[B] - .else - SET_VREG %edx, %rax # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 - -/* ------------------------------ */ - .balign 128 -.L_op_move_wide: /* 0x04 */ - /* move-wide vA, vB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - movl rINST, %ecx # ecx <- BA - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - GET_WIDE_VREG %rdx, rINSTq # rdx <- v[B] - SET_WIDE_VREG %rdx, %rcx # v[A] <- rdx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_move_wide_from16: /* 0x05 */ - /* move-wide/from16 vAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - movzwl 2(rPC), %ecx # ecx <- BBBB - GET_WIDE_VREG %rdx, %rcx # rdx <- v[B] - SET_WIDE_VREG %rdx, rINSTq # v[A] <- rdx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_move_wide_16: /* 0x06 */ - /* move-wide/16 vAAAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - movzwq 4(rPC), %rcx # ecx<- BBBB - movzwq 2(rPC), %rax # eax<- AAAA - GET_WIDE_VREG %rdx, %rcx # rdx <- v[B] - SET_WIDE_VREG %rdx, %rax # v[A] <- rdx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 - -/* ------------------------------ */ - .balign 128 -.L_op_move_object: /* 0x07 */ - /* for move, move-object, long-to-int */ - /* op vA, vB */ - movl rINST, %eax # eax <- BA - andb $0xf, %al # eax <- A - shrl $4, rINST # rINST <- B - GET_VREG %edx, rINSTq - .if 1 - SET_VREG_OBJECT %edx, %rax # fp[A] <- fp[B] - .else - SET_VREG %edx, %rax # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_move_object_from16: /* 0x08 */ - /* for: move/from16, move-object/from16 */ - /* op vAA, vBBBB */ - movzwq 2(rPC), %rax # eax <- BBBB - GET_VREG %edx, %rax # edx <- fp[BBBB] - .if 1 - SET_VREG_OBJECT %edx, rINSTq # fp[A] <- fp[B] - .else - SET_VREG %edx, rINSTq # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_move_object_16: /* 0x09 */ - /* for: move/16, move-object/16 */ - /* op vAAAA, vBBBB */ - movzwq 4(rPC), %rcx # ecx <- BBBB - movzwq 2(rPC), %rax # eax <- AAAA - GET_VREG %edx, %rcx - .if 1 - SET_VREG_OBJECT %edx, %rax # fp[A] <- fp[B] - .else - SET_VREG %edx, %rax # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 - -/* ------------------------------ */ - .balign 128 -.L_op_move_result: /* 0x0a */ - /* for: move-result, move-result-object */ - /* op vAA */ - movq OFF_FP_RESULT_REGISTER(rFP), %rax # get pointer to result JType. - movl (%rax), %eax # r0 <- result.i. - .if 0 - SET_VREG_OBJECT %eax, rINSTq # fp[A] <- fp[B] - .else - SET_VREG %eax, rINSTq # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_move_result_wide: /* 0x0b */ - /* move-result-wide vAA */ - movq OFF_FP_RESULT_REGISTER(rFP), %rax # get pointer to result JType. - movq (%rax), %rdx # Get wide - SET_WIDE_VREG %rdx, rINSTq # v[AA] <- rdx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_move_result_object: /* 0x0c */ - /* for: move-result, move-result-object */ - /* op vAA */ - movq OFF_FP_RESULT_REGISTER(rFP), %rax # get pointer to result JType. - movl (%rax), %eax # r0 <- result.i. - .if 1 - SET_VREG_OBJECT %eax, rINSTq # fp[A] <- fp[B] - .else - SET_VREG %eax, rINSTq # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_move_exception: /* 0x0d */ - /* move-exception vAA */ - movq rSELF, %rcx - movl THREAD_EXCEPTION_OFFSET(%rcx), %eax - SET_VREG_OBJECT %eax, rINSTq # fp[AA] <- exception object - movl $0, THREAD_EXCEPTION_OFFSET(%rcx) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_return_void: /* 0x0e */ - .extern MterpThreadFenceForConstructor - call SYMBOL(MterpThreadFenceForConstructor) - movq rSELF, OUT_ARG0 - testl $(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(OUT_ARG0) - jz 1f - call SYMBOL(MterpSuspendCheck) -1: - xorq %rax, %rax - jmp MterpReturn - -/* ------------------------------ */ - .balign 128 -.L_op_return: /* 0x0f */ -/* - * Return a 32-bit value. - * - * for: return, return-object - */ - /* op vAA */ - .extern MterpThreadFenceForConstructor - call SYMBOL(MterpThreadFenceForConstructor) - movq rSELF, OUT_ARG0 - testl $(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(OUT_ARG0) - jz 1f - call SYMBOL(MterpSuspendCheck) -1: - GET_VREG %eax, rINSTq # eax <- vAA - jmp MterpReturn - -/* ------------------------------ */ - .balign 128 -.L_op_return_wide: /* 0x10 */ -/* - * Return a 64-bit value. - */ - /* return-wide vAA */ - .extern MterpThreadFenceForConstructor - call SYMBOL(MterpThreadFenceForConstructor) - movq rSELF, OUT_ARG0 - testl $(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(OUT_ARG0) - jz 1f - call SYMBOL(MterpSuspendCheck) -1: - GET_WIDE_VREG %rax, rINSTq # eax <- v[AA] - jmp MterpReturn - -/* ------------------------------ */ - .balign 128 -.L_op_return_object: /* 0x11 */ -/* - * Return a 32-bit value. - * - * for: return, return-object - */ - /* op vAA */ - .extern MterpThreadFenceForConstructor - call SYMBOL(MterpThreadFenceForConstructor) - movq rSELF, OUT_ARG0 - testl $(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(OUT_ARG0) - jz 1f - call SYMBOL(MterpSuspendCheck) -1: - GET_VREG %eax, rINSTq # eax <- vAA - jmp MterpReturn - -/* ------------------------------ */ - .balign 128 -.L_op_const_4: /* 0x12 */ - /* const/4 vA, #+B */ - movsbl rINSTbl, %eax # eax <-ssssssBx - movl $0xf, rINST - andl %eax, rINST # rINST <- A - sarl $4, %eax - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_const_16: /* 0x13 */ - /* const/16 vAA, #+BBBB */ - movswl 2(rPC), %ecx # ecx <- ssssBBBB - SET_VREG %ecx, rINSTq # vAA <- ssssBBBB - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_const: /* 0x14 */ - /* const vAA, #+BBBBbbbb */ - movl 2(rPC), %eax # grab all 32 bits at once - SET_VREG %eax, rINSTq # vAA<- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 - -/* ------------------------------ */ - .balign 128 -.L_op_const_high16: /* 0x15 */ - /* const/high16 vAA, #+BBBB0000 */ - movzwl 2(rPC), %eax # eax <- 0000BBBB - sall $16, %eax # eax <- BBBB0000 - SET_VREG %eax, rINSTq # vAA <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_const_wide_16: /* 0x16 */ - /* const-wide/16 vAA, #+BBBB */ - movswq 2(rPC), %rax # rax <- ssssBBBB - SET_WIDE_VREG %rax, rINSTq # store - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_const_wide_32: /* 0x17 */ - /* const-wide/32 vAA, #+BBBBbbbb */ - movslq 2(rPC), %rax # eax <- ssssssssBBBBbbbb - SET_WIDE_VREG %rax, rINSTq # store - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 - -/* ------------------------------ */ - .balign 128 -.L_op_const_wide: /* 0x18 */ - /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ - movq 2(rPC), %rax # rax <- HHHHhhhhBBBBbbbb - SET_WIDE_VREG %rax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 5 - -/* ------------------------------ */ - .balign 128 -.L_op_const_wide_high16: /* 0x19 */ - /* const-wide/high16 vAA, #+BBBB000000000000 */ - movzwq 2(rPC), %rax # eax <- 0000BBBB - salq $48, %rax # eax <- BBBB0000 - SET_WIDE_VREG %rax, rINSTq # v[AA+0] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_const_string: /* 0x1a */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstString - EXPORT_PC - movzwq 2(rPC), OUT_ARG0 # eax <- OUT_ARG0 - movq rINSTq, OUT_ARG1 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 - movq rSELF, OUT_ARG3 - call SYMBOL(MterpConstString) # (index, tgt_reg, shadow_frame, self) - testb %al, %al - jnz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_const_string_jumbo: /* 0x1b */ - /* const/string vAA, String@BBBBBBBB */ - EXPORT_PC - movl 2(rPC), OUT_32_ARG0 # OUT_32_ARG0 <- BBBB - movq rINSTq, OUT_ARG1 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 - movq rSELF, OUT_ARG3 - call SYMBOL(MterpConstString) # (index, tgt_reg, shadow_frame, self) - testb %al, %al - jnz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 - -/* ------------------------------ */ - .balign 128 -.L_op_const_class: /* 0x1c */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstClass - EXPORT_PC - movzwq 2(rPC), OUT_ARG0 # eax <- OUT_ARG0 - movq rINSTq, OUT_ARG1 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 - movq rSELF, OUT_ARG3 - call SYMBOL(MterpConstClass) # (index, tgt_reg, shadow_frame, self) - testb %al, %al - jnz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_monitor_enter: /* 0x1d */ -/* - * Synchronize on an object. - */ - /* monitor-enter vAA */ - EXPORT_PC - GET_VREG OUT_32_ARG0, rINSTq - movq rSELF, OUT_ARG1 - call SYMBOL(artLockObjectFromCode) # (object, self) - testq %rax, %rax - jnz MterpException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_monitor_exit: /* 0x1e */ -/* - * Unlock an object. - * - * Exceptions that occur when unlocking a monitor need to appear as - * if they happened at the following instruction. See the Dalvik - * instruction spec. - */ - /* monitor-exit vAA */ - EXPORT_PC - GET_VREG OUT_32_ARG0, rINSTq - movq rSELF, OUT_ARG1 - call SYMBOL(artUnlockObjectFromCode) # (object, self) - testq %rax, %rax - jnz MterpException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_check_cast: /* 0x1f */ -/* - * Check to see if a cast from one class to another is allowed. - */ - /* check-cast vAA, class@BBBB */ - EXPORT_PC - movzwq 2(rPC), OUT_ARG0 # OUT_ARG0 <- BBBB - leaq VREG_ADDRESS(rINSTq), OUT_ARG1 - movq OFF_FP_METHOD(rFP), OUT_ARG2 - movq rSELF, OUT_ARG3 - call SYMBOL(MterpCheckCast) # (index, &obj, method, self) - testb %al, %al - jnz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_instance_of: /* 0x20 */ -/* - * Check to see if an object reference is an instance of a class. - * - * Most common situation is a non-null object, being compared against - * an already-resolved class. - */ - /* instance-of vA, vB, class@CCCC */ - EXPORT_PC - movzwl 2(rPC), OUT_32_ARG0 # OUT_32_ARG0 <- CCCC - movl rINST, %eax # eax <- BA - sarl $4, %eax # eax <- B - leaq VREG_ADDRESS(%rax), OUT_ARG1 # Get object address - movq OFF_FP_METHOD(rFP), OUT_ARG2 - movq rSELF, OUT_ARG3 - call SYMBOL(MterpInstanceOf) # (index, &obj, method, self) - movsbl %al, %eax - movq rSELF, %rcx - cmpq $0, THREAD_EXCEPTION_OFFSET(%rcx) - jnz MterpException - andb $0xf, rINSTbl # rINSTbl <- A - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_array_length: /* 0x21 */ -/* - * Return the length of an array. - */ - movl rINST, %eax # eax <- BA - sarl $4, rINST # rINST <- B - GET_VREG %ecx, rINSTq # ecx <- vB (object ref) - testl %ecx, %ecx # is null? - je common_errNullObject - andb $0xf, %al # eax <- A - movl MIRROR_ARRAY_LENGTH_OFFSET(%rcx), rINST - SET_VREG rINST, %rax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_new_instance: /* 0x22 */ -/* - * Create a new instance of a class. - */ - /* new-instance vAA, class@BBBB */ - EXPORT_PC - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG0 - movq rSELF, OUT_ARG1 - REFRESH_INST 34 - movq rINSTq, OUT_ARG2 - call SYMBOL(MterpNewInstance) - testb %al, %al # 0 means an exception is thrown - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_new_array: /* 0x23 */ -/* - * Allocate an array of objects, specified with the array class - * and a count. - * - * The verifier guarantees that this is an array class, so we don't - * check for it here. - */ - /* new-array vA, vB, class@CCCC */ - EXPORT_PC - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG0 - movq rPC, OUT_ARG1 - REFRESH_INST 35 - movq rINSTq, OUT_ARG2 - movq rSELF, OUT_ARG3 - call SYMBOL(MterpNewArray) - testb %al, %al # 0 means an exception is thrown - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_filled_new_array: /* 0x24 */ -/* - * Create a new array with elements filled from registers. - * - * for: filled-new-array, filled-new-array/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ - .extern MterpFilledNewArray - EXPORT_PC - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG0 - movq rPC, OUT_ARG1 - movq rSELF, OUT_ARG2 - call SYMBOL(MterpFilledNewArray) - testb %al, %al # 0 means an exception is thrown - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 - -/* ------------------------------ */ - .balign 128 -.L_op_filled_new_array_range: /* 0x25 */ -/* - * Create a new array with elements filled from registers. - * - * for: filled-new-array, filled-new-array/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ - .extern MterpFilledNewArrayRange - EXPORT_PC - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG0 - movq rPC, OUT_ARG1 - movq rSELF, OUT_ARG2 - call SYMBOL(MterpFilledNewArrayRange) - testb %al, %al # 0 means an exception is thrown - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 - -/* ------------------------------ */ - .balign 128 -.L_op_fill_array_data: /* 0x26 */ - /* fill-array-data vAA, +BBBBBBBB */ - EXPORT_PC - movslq 2(rPC), %rcx # rcx <- ssssssssBBBBbbbb - leaq (rPC,%rcx,2), OUT_ARG1 # OUT_ARG1 <- PC + ssssssssBBBBbbbb*2 - GET_VREG OUT_32_ARG0, rINSTq # OUT_ARG0 <- vAA (array object) - call SYMBOL(MterpFillArrayData) # (obj, payload) - testb %al, %al # 0 means an exception is thrown - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 - -/* ------------------------------ */ - .balign 128 -.L_op_throw: /* 0x27 */ -/* - * Throw an exception object in the current thread. - */ - /* throw vAA */ - EXPORT_PC - GET_VREG %eax, rINSTq # eax<- vAA (exception object) - testb %al, %al - jz common_errNullObject - movq rSELF, %rcx - movq %rax, THREAD_EXCEPTION_OFFSET(%rcx) - jmp MterpException - -/* ------------------------------ */ - .balign 128 -.L_op_goto: /* 0x28 */ -/* - * Unconditional branch, 8-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto +AA */ - movsbq rINSTbl, rINSTq # rINSTq <- ssssssAA - testq rINSTq, rINSTq - jmp MterpCommonTakenBranch - -/* ------------------------------ */ - .balign 128 -.L_op_goto_16: /* 0x29 */ -/* - * Unconditional branch, 16-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto/16 +AAAA */ - movswq 2(rPC), rINSTq # rINSTq <- ssssAAAA - testq rINSTq, rINSTq - jmp MterpCommonTakenBranch - -/* ------------------------------ */ - .balign 128 -.L_op_goto_32: /* 0x2a */ -/* - * Unconditional branch, 32-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - * - * Because we need the SF bit set, we'll use an adds - * to convert from Dalvik offset to byte offset. - */ - /* goto/32 +AAAAAAAA */ - movslq 2(rPC), rINSTq # rINSTq <- AAAAAAAA - testq rINSTq, rINSTq - jmp MterpCommonTakenBranch - -/* ------------------------------ */ - .balign 128 -.L_op_packed_switch: /* 0x2b */ -/* - * Handle a packed-switch or sparse-switch instruction. In both cases - * we decode it and hand it off to a helper function. - * - * We don't really expect backward branches in a switch statement, but - * they're perfectly legal, so we check for them here. - * - * for: packed-switch, sparse-switch - */ - /* op vAA, +BBBB */ - movslq 2(rPC), OUT_ARG0 # rcx <- ssssssssBBBBbbbb - leaq (rPC,OUT_ARG0,2), OUT_ARG0 # rcx <- PC + ssssssssBBBBbbbb*2 - GET_VREG OUT_32_ARG1, rINSTq # eax <- vAA - call SYMBOL(MterpDoPackedSwitch) - testl %eax, %eax - movslq %eax, rINSTq - jmp MterpCommonTakenBranch - -/* ------------------------------ */ - .balign 128 -.L_op_sparse_switch: /* 0x2c */ -/* - * Handle a packed-switch or sparse-switch instruction. In both cases - * we decode it and hand it off to a helper function. - * - * We don't really expect backward branches in a switch statement, but - * they're perfectly legal, so we check for them here. - * - * for: packed-switch, sparse-switch - */ - /* op vAA, +BBBB */ - movslq 2(rPC), OUT_ARG0 # rcx <- ssssssssBBBBbbbb - leaq (rPC,OUT_ARG0,2), OUT_ARG0 # rcx <- PC + ssssssssBBBBbbbb*2 - GET_VREG OUT_32_ARG1, rINSTq # eax <- vAA - call SYMBOL(MterpDoSparseSwitch) - testl %eax, %eax - movslq %eax, rINSTq - jmp MterpCommonTakenBranch - -/* ------------------------------ */ - .balign 128 -.L_op_cmpl_float: /* 0x2d */ -/* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * int compare(x, y) { - * if (x == y) { - * return 0; - * } else if (x < y) { - * return -1; - * } else if (x > y) { - * return 1; - * } else { - * return nanval ? 1 : -1; - * } - * } - */ - /* op vAA, vBB, vCC */ - movzbq 3(rPC), %rcx # ecx<- CC - movzbq 2(rPC), %rax # eax<- BB - movss VREG_ADDRESS(%rax), %xmm0 - xor %eax, %eax - ucomiss VREG_ADDRESS(%rcx), %xmm0 - jp .Lop_cmpl_float_nan_is_neg - je .Lop_cmpl_float_finish - jb .Lop_cmpl_float_less -.Lop_cmpl_float_nan_is_pos: - addb $1, %al - jmp .Lop_cmpl_float_finish -.Lop_cmpl_float_nan_is_neg: -.Lop_cmpl_float_less: - movl $-1, %eax -.Lop_cmpl_float_finish: - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_cmpg_float: /* 0x2e */ -/* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * int compare(x, y) { - * if (x == y) { - * return 0; - * } else if (x < y) { - * return -1; - * } else if (x > y) { - * return 1; - * } else { - * return nanval ? 1 : -1; - * } - * } - */ - /* op vAA, vBB, vCC */ - movzbq 3(rPC), %rcx # ecx<- CC - movzbq 2(rPC), %rax # eax<- BB - movss VREG_ADDRESS(%rax), %xmm0 - xor %eax, %eax - ucomiss VREG_ADDRESS(%rcx), %xmm0 - jp .Lop_cmpg_float_nan_is_pos - je .Lop_cmpg_float_finish - jb .Lop_cmpg_float_less -.Lop_cmpg_float_nan_is_pos: - addb $1, %al - jmp .Lop_cmpg_float_finish -.Lop_cmpg_float_nan_is_neg: -.Lop_cmpg_float_less: - movl $-1, %eax -.Lop_cmpg_float_finish: - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_cmpl_double: /* 0x2f */ -/* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * int compare(x, y) { - * if (x == y) { - * return 0; - * } else if (x < y) { - * return -1; - * } else if (x > y) { - * return 1; - * } else { - * return nanval ? 1 : -1; - * } - * } - */ - /* op vAA, vBB, vCC */ - movzbq 3(rPC), %rcx # ecx<- CC - movzbq 2(rPC), %rax # eax<- BB - movsd VREG_ADDRESS(%rax), %xmm0 - xor %eax, %eax - ucomisd VREG_ADDRESS(%rcx), %xmm0 - jp .Lop_cmpl_double_nan_is_neg - je .Lop_cmpl_double_finish - jb .Lop_cmpl_double_less -.Lop_cmpl_double_nan_is_pos: - addb $1, %al - jmp .Lop_cmpl_double_finish -.Lop_cmpl_double_nan_is_neg: -.Lop_cmpl_double_less: - movl $-1, %eax -.Lop_cmpl_double_finish: - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_cmpg_double: /* 0x30 */ -/* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * int compare(x, y) { - * if (x == y) { - * return 0; - * } else if (x < y) { - * return -1; - * } else if (x > y) { - * return 1; - * } else { - * return nanval ? 1 : -1; - * } - * } - */ - /* op vAA, vBB, vCC */ - movzbq 3(rPC), %rcx # ecx<- CC - movzbq 2(rPC), %rax # eax<- BB - movsd VREG_ADDRESS(%rax), %xmm0 - xor %eax, %eax - ucomisd VREG_ADDRESS(%rcx), %xmm0 - jp .Lop_cmpg_double_nan_is_pos - je .Lop_cmpg_double_finish - jb .Lop_cmpg_double_less -.Lop_cmpg_double_nan_is_pos: - addb $1, %al - jmp .Lop_cmpg_double_finish -.Lop_cmpg_double_nan_is_neg: -.Lop_cmpg_double_less: - movl $-1, %eax -.Lop_cmpg_double_finish: - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_cmp_long: /* 0x31 */ -/* - * Compare two 64-bit values. Puts 0, 1, or -1 into the destination - * register based on the results of the comparison. - */ - /* cmp-long vAA, vBB, vCC */ - movzbq 2(rPC), %rdx # edx <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_WIDE_VREG %rdx, %rdx # rdx <- v[BB] - xorl %eax, %eax - xorl %edi, %edi - addb $1, %al - movl $-1, %esi - cmpq VREG_ADDRESS(%rcx), %rdx - cmovl %esi, %edi - cmovg %eax, %edi - SET_VREG %edi, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_if_eq: /* 0x32 */ -/* - * Generic two-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # rcx <- A - GET_VREG %eax, %rcx # eax <- vA - cmpl VREG_ADDRESS(rINSTq), %eax # compare (vA, vB) - jne 1f - movswq 2(rPC), rINSTq # Get signed branch offset - testq rINSTq, rINSTq - jmp MterpCommonTakenBranch -1: - cmpl $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_if_ne: /* 0x33 */ -/* - * Generic two-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # rcx <- A - GET_VREG %eax, %rcx # eax <- vA - cmpl VREG_ADDRESS(rINSTq), %eax # compare (vA, vB) - je 1f - movswq 2(rPC), rINSTq # Get signed branch offset - testq rINSTq, rINSTq - jmp MterpCommonTakenBranch -1: - cmpl $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_if_lt: /* 0x34 */ -/* - * Generic two-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # rcx <- A - GET_VREG %eax, %rcx # eax <- vA - cmpl VREG_ADDRESS(rINSTq), %eax # compare (vA, vB) - jge 1f - movswq 2(rPC), rINSTq # Get signed branch offset - testq rINSTq, rINSTq - jmp MterpCommonTakenBranch -1: - cmpl $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_if_ge: /* 0x35 */ -/* - * Generic two-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # rcx <- A - GET_VREG %eax, %rcx # eax <- vA - cmpl VREG_ADDRESS(rINSTq), %eax # compare (vA, vB) - jl 1f - movswq 2(rPC), rINSTq # Get signed branch offset - testq rINSTq, rINSTq - jmp MterpCommonTakenBranch -1: - cmpl $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_if_gt: /* 0x36 */ -/* - * Generic two-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # rcx <- A - GET_VREG %eax, %rcx # eax <- vA - cmpl VREG_ADDRESS(rINSTq), %eax # compare (vA, vB) - jle 1f - movswq 2(rPC), rINSTq # Get signed branch offset - testq rINSTq, rINSTq - jmp MterpCommonTakenBranch -1: - cmpl $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_if_le: /* 0x37 */ -/* - * Generic two-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # rcx <- A - GET_VREG %eax, %rcx # eax <- vA - cmpl VREG_ADDRESS(rINSTq), %eax # compare (vA, vB) - jg 1f - movswq 2(rPC), rINSTq # Get signed branch offset - testq rINSTq, rINSTq - jmp MterpCommonTakenBranch -1: - cmpl $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_if_eqz: /* 0x38 */ -/* - * Generic one-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - cmpl $0, VREG_ADDRESS(rINSTq) # compare (vA, 0) - jne 1f - movswq 2(rPC), rINSTq # fetch signed displacement - testq rINSTq, rINSTq - jmp MterpCommonTakenBranch -1: - cmpl $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_if_nez: /* 0x39 */ -/* - * Generic one-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - cmpl $0, VREG_ADDRESS(rINSTq) # compare (vA, 0) - je 1f - movswq 2(rPC), rINSTq # fetch signed displacement - testq rINSTq, rINSTq - jmp MterpCommonTakenBranch -1: - cmpl $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_if_ltz: /* 0x3a */ -/* - * Generic one-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - cmpl $0, VREG_ADDRESS(rINSTq) # compare (vA, 0) - jge 1f - movswq 2(rPC), rINSTq # fetch signed displacement - testq rINSTq, rINSTq - jmp MterpCommonTakenBranch -1: - cmpl $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_if_gez: /* 0x3b */ -/* - * Generic one-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - cmpl $0, VREG_ADDRESS(rINSTq) # compare (vA, 0) - jl 1f - movswq 2(rPC), rINSTq # fetch signed displacement - testq rINSTq, rINSTq - jmp MterpCommonTakenBranch -1: - cmpl $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_if_gtz: /* 0x3c */ -/* - * Generic one-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - cmpl $0, VREG_ADDRESS(rINSTq) # compare (vA, 0) - jle 1f - movswq 2(rPC), rINSTq # fetch signed displacement - testq rINSTq, rINSTq - jmp MterpCommonTakenBranch -1: - cmpl $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_if_lez: /* 0x3d */ -/* - * Generic one-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - cmpl $0, VREG_ADDRESS(rINSTq) # compare (vA, 0) - jg 1f - movswq 2(rPC), rINSTq # fetch signed displacement - testq rINSTq, rINSTq - jmp MterpCommonTakenBranch -1: - cmpl $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_unused_3e: /* 0x3e */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_3f: /* 0x3f */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_40: /* 0x40 */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_41: /* 0x41 */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_42: /* 0x42 */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_43: /* 0x43 */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_aget: /* 0x44 */ -/* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short, aget-wide - * - */ - /* op vAA, vBB, vCC */ - movzbq 2(rPC), %rax # eax <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_VREG %eax, %rax # eax <- vBB (array object) - GET_VREG %ecx, %rcx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - .if 0 - movq MIRROR_INT_ARRAY_DATA_OFFSET(%rax,%rcx,8), %rax - SET_WIDE_VREG %rax, rINSTq - .else - movl MIRROR_INT_ARRAY_DATA_OFFSET(%rax,%rcx,4), %eax - SET_VREG %eax, rINSTq - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_aget_wide: /* 0x45 */ -/* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short, aget-wide - * - */ - /* op vAA, vBB, vCC */ - movzbq 2(rPC), %rax # eax <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_VREG %eax, %rax # eax <- vBB (array object) - GET_VREG %ecx, %rcx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - .if 1 - movq MIRROR_WIDE_ARRAY_DATA_OFFSET(%rax,%rcx,8), %rax - SET_WIDE_VREG %rax, rINSTq - .else - movq MIRROR_WIDE_ARRAY_DATA_OFFSET(%rax,%rcx,8), %eax - SET_VREG %eax, rINSTq - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_aget_object: /* 0x46 */ -/* - * Array object get. vAA <- vBB[vCC]. - * - * for: aget-object - */ - /* op vAA, vBB, vCC */ - movzbq 2(rPC), %rax # rax <- BB - movzbq 3(rPC), %rcx # rcx <- CC - GET_VREG OUT_32_ARG0, %rax # eax <- vBB (array object) - GET_VREG OUT_32_ARG1, %rcx # ecx <- vCC (requested index) - EXPORT_PC - call SYMBOL(artAGetObjectFromMterp) # (array, index) - movq rSELF, %rcx - cmpq $0, THREAD_EXCEPTION_OFFSET(%rcx) - jnz MterpException - SET_VREG_OBJECT %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_aget_boolean: /* 0x47 */ -/* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short, aget-wide - * - */ - /* op vAA, vBB, vCC */ - movzbq 2(rPC), %rax # eax <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_VREG %eax, %rax # eax <- vBB (array object) - GET_VREG %ecx, %rcx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - .if 0 - movq MIRROR_BOOLEAN_ARRAY_DATA_OFFSET(%rax,%rcx,8), %rax - SET_WIDE_VREG %rax, rINSTq - .else - movzbl MIRROR_BOOLEAN_ARRAY_DATA_OFFSET(%rax,%rcx,1), %eax - SET_VREG %eax, rINSTq - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_aget_byte: /* 0x48 */ -/* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short, aget-wide - * - */ - /* op vAA, vBB, vCC */ - movzbq 2(rPC), %rax # eax <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_VREG %eax, %rax # eax <- vBB (array object) - GET_VREG %ecx, %rcx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - .if 0 - movq MIRROR_BYTE_ARRAY_DATA_OFFSET(%rax,%rcx,8), %rax - SET_WIDE_VREG %rax, rINSTq - .else - movsbl MIRROR_BYTE_ARRAY_DATA_OFFSET(%rax,%rcx,1), %eax - SET_VREG %eax, rINSTq - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_aget_char: /* 0x49 */ -/* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short, aget-wide - * - */ - /* op vAA, vBB, vCC */ - movzbq 2(rPC), %rax # eax <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_VREG %eax, %rax # eax <- vBB (array object) - GET_VREG %ecx, %rcx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - .if 0 - movq MIRROR_CHAR_ARRAY_DATA_OFFSET(%rax,%rcx,8), %rax - SET_WIDE_VREG %rax, rINSTq - .else - movzwl MIRROR_CHAR_ARRAY_DATA_OFFSET(%rax,%rcx,2), %eax - SET_VREG %eax, rINSTq - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_aget_short: /* 0x4a */ -/* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short, aget-wide - * - */ - /* op vAA, vBB, vCC */ - movzbq 2(rPC), %rax # eax <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_VREG %eax, %rax # eax <- vBB (array object) - GET_VREG %ecx, %rcx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - .if 0 - movq MIRROR_SHORT_ARRAY_DATA_OFFSET(%rax,%rcx,8), %rax - SET_WIDE_VREG %rax, rINSTq - .else - movswl MIRROR_SHORT_ARRAY_DATA_OFFSET(%rax,%rcx,2), %eax - SET_VREG %eax, rINSTq - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_aput: /* 0x4b */ -/* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short, aput-wide - * - */ - /* op vAA, vBB, vCC */ - movzbq 2(rPC), %rax # rax <- BB - movzbq 3(rPC), %rcx # rcx <- CC - GET_VREG %eax, %rax # eax <- vBB (array object) - GET_VREG %ecx, %rcx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - .if 0 - GET_WIDE_VREG rINSTq, rINSTq - .else - GET_VREG rINST, rINSTq - .endif - movl rINST, MIRROR_INT_ARRAY_DATA_OFFSET(%rax,%rcx,4) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_aput_wide: /* 0x4c */ -/* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short, aput-wide - * - */ - /* op vAA, vBB, vCC */ - movzbq 2(rPC), %rax # rax <- BB - movzbq 3(rPC), %rcx # rcx <- CC - GET_VREG %eax, %rax # eax <- vBB (array object) - GET_VREG %ecx, %rcx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - .if 1 - GET_WIDE_VREG rINSTq, rINSTq - .else - GET_VREG rINST, rINSTq - .endif - movq rINSTq, MIRROR_WIDE_ARRAY_DATA_OFFSET(%rax,%rcx,8) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_aput_object: /* 0x4d */ -/* - * Store an object into an array. vBB[vCC] <- vAA. - */ - /* op vAA, vBB, vCC */ - EXPORT_PC - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG0 - movq rPC, OUT_ARG1 - REFRESH_INST 77 - movq rINSTq, OUT_ARG2 - call SYMBOL(MterpAputObject) # (array, index) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_aput_boolean: /* 0x4e */ -/* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short, aput-wide - * - */ - /* op vAA, vBB, vCC */ - movzbq 2(rPC), %rax # rax <- BB - movzbq 3(rPC), %rcx # rcx <- CC - GET_VREG %eax, %rax # eax <- vBB (array object) - GET_VREG %ecx, %rcx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - .if 0 - GET_WIDE_VREG rINSTq, rINSTq - .else - GET_VREG rINST, rINSTq - .endif - movb rINSTbl, MIRROR_BOOLEAN_ARRAY_DATA_OFFSET(%rax,%rcx,1) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_aput_byte: /* 0x4f */ -/* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short, aput-wide - * - */ - /* op vAA, vBB, vCC */ - movzbq 2(rPC), %rax # rax <- BB - movzbq 3(rPC), %rcx # rcx <- CC - GET_VREG %eax, %rax # eax <- vBB (array object) - GET_VREG %ecx, %rcx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - .if 0 - GET_WIDE_VREG rINSTq, rINSTq - .else - GET_VREG rINST, rINSTq - .endif - movb rINSTbl, MIRROR_BYTE_ARRAY_DATA_OFFSET(%rax,%rcx,1) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_aput_char: /* 0x50 */ -/* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short, aput-wide - * - */ - /* op vAA, vBB, vCC */ - movzbq 2(rPC), %rax # rax <- BB - movzbq 3(rPC), %rcx # rcx <- CC - GET_VREG %eax, %rax # eax <- vBB (array object) - GET_VREG %ecx, %rcx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - .if 0 - GET_WIDE_VREG rINSTq, rINSTq - .else - GET_VREG rINST, rINSTq - .endif - movw rINSTw, MIRROR_CHAR_ARRAY_DATA_OFFSET(%rax,%rcx,2) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_aput_short: /* 0x51 */ -/* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short, aput-wide - * - */ - /* op vAA, vBB, vCC */ - movzbq 2(rPC), %rax # rax <- BB - movzbq 3(rPC), %rcx # rcx <- CC - GET_VREG %eax, %rax # eax <- vBB (array object) - GET_VREG %ecx, %rcx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - .if 0 - GET_WIDE_VREG rINSTq, rINSTq - .else - GET_VREG rINST, rINSTq - .endif - movw rINSTw, MIRROR_SHORT_ARRAY_DATA_OFFSET(%rax,%rcx,2) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iget: /* 0x52 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetU32 - REFRESH_INST 82 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpIGetU32) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iget_wide: /* 0x53 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetU64 - REFRESH_INST 83 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpIGetU64) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iget_object: /* 0x54 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetObj - REFRESH_INST 84 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpIGetObj) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iget_boolean: /* 0x55 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetU8 - REFRESH_INST 85 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpIGetU8) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iget_byte: /* 0x56 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetI8 - REFRESH_INST 86 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpIGetI8) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iget_char: /* 0x57 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetU16 - REFRESH_INST 87 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpIGetU16) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iget_short: /* 0x58 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetI16 - REFRESH_INST 88 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpIGetI16) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iput: /* 0x59 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutU32 - REFRESH_INST 89 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpIPutU32) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iput_wide: /* 0x5a */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutU64 - REFRESH_INST 90 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpIPutU64) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iput_object: /* 0x5b */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutObj - REFRESH_INST 91 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpIPutObj) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iput_boolean: /* 0x5c */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutU8 - REFRESH_INST 92 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpIPutU8) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iput_byte: /* 0x5d */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutI8 - REFRESH_INST 93 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpIPutI8) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iput_char: /* 0x5e */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutU16 - REFRESH_INST 94 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpIPutU16) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iput_short: /* 0x5f */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutI16 - REFRESH_INST 95 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpIPutI16) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_sget: /* 0x60 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetU32 - REFRESH_INST 96 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpSGetU32) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_sget_wide: /* 0x61 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetU64 - REFRESH_INST 97 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpSGetU64) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_sget_object: /* 0x62 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetObj - REFRESH_INST 98 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpSGetObj) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_sget_boolean: /* 0x63 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetU8 - REFRESH_INST 99 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpSGetU8) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_sget_byte: /* 0x64 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetI8 - REFRESH_INST 100 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpSGetI8) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_sget_char: /* 0x65 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetU16 - REFRESH_INST 101 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpSGetU16) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_sget_short: /* 0x66 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetI16 - REFRESH_INST 102 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpSGetI16) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_sput: /* 0x67 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutU32 - REFRESH_INST 103 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpSPutU32) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_sput_wide: /* 0x68 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutU64 - REFRESH_INST 104 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpSPutU64) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_sput_object: /* 0x69 */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutObj - REFRESH_INST 105 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpSPutObj) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_sput_boolean: /* 0x6a */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutU8 - REFRESH_INST 106 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpSPutU8) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_sput_byte: /* 0x6b */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutI8 - REFRESH_INST 107 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpSPutI8) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_sput_char: /* 0x6c */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutU16 - REFRESH_INST 108 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpSPutU16) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_sput_short: /* 0x6d */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutI16 - REFRESH_INST 109 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpSPutI16) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual: /* 0x6e */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtual - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - REFRESH_INST 110 - movl rINST, OUT_32_ARG3 - call SYMBOL(MterpInvokeVirtual) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - FETCH_INST - GOTO_NEXT - -/* - * Handle a virtual method call. - * - * for: invoke-virtual, invoke-virtual/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_super: /* 0x6f */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeSuper - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - REFRESH_INST 111 - movl rINST, OUT_32_ARG3 - call SYMBOL(MterpInvokeSuper) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - FETCH_INST - GOTO_NEXT - -/* - * Handle a "super" method call. - * - * for: invoke-super, invoke-super/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_direct: /* 0x70 */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeDirect - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - REFRESH_INST 112 - movl rINST, OUT_32_ARG3 - call SYMBOL(MterpInvokeDirect) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - FETCH_INST - GOTO_NEXT - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_static: /* 0x71 */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeStatic - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - REFRESH_INST 113 - movl rINST, OUT_32_ARG3 - call SYMBOL(MterpInvokeStatic) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - FETCH_INST - GOTO_NEXT - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_interface: /* 0x72 */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeInterface - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - REFRESH_INST 114 - movl rINST, OUT_32_ARG3 - call SYMBOL(MterpInvokeInterface) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - FETCH_INST - GOTO_NEXT - -/* - * Handle an interface method call. - * - * for: invoke-interface, invoke-interface/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - -/* ------------------------------ */ - .balign 128 -.L_op_return_void_no_barrier: /* 0x73 */ - movq rSELF, OUT_ARG0 - testl $(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(OUT_ARG0) - jz 1f - call SYMBOL(MterpSuspendCheck) -1: - xorq %rax, %rax - jmp MterpReturn - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual_range: /* 0x74 */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtualRange - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - REFRESH_INST 116 - movl rINST, OUT_32_ARG3 - call SYMBOL(MterpInvokeVirtualRange) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - FETCH_INST - GOTO_NEXT - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_super_range: /* 0x75 */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeSuperRange - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - REFRESH_INST 117 - movl rINST, OUT_32_ARG3 - call SYMBOL(MterpInvokeSuperRange) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - FETCH_INST - GOTO_NEXT - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_direct_range: /* 0x76 */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeDirectRange - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - REFRESH_INST 118 - movl rINST, OUT_32_ARG3 - call SYMBOL(MterpInvokeDirectRange) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - FETCH_INST - GOTO_NEXT - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_static_range: /* 0x77 */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeStaticRange - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - REFRESH_INST 119 - movl rINST, OUT_32_ARG3 - call SYMBOL(MterpInvokeStaticRange) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - FETCH_INST - GOTO_NEXT - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_interface_range: /* 0x78 */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeInterfaceRange - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - REFRESH_INST 120 - movl rINST, OUT_32_ARG3 - call SYMBOL(MterpInvokeInterfaceRange) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - FETCH_INST - GOTO_NEXT - -/* ------------------------------ */ - .balign 128 -.L_op_unused_79: /* 0x79 */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_7a: /* 0x7a */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_neg_int: /* 0x7b */ -/* - * Generic 32/64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op eax". - */ - /* unop vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4,rINST # rINST <- B - .if 0 - GET_WIDE_VREG %rax, rINSTq # rax <- vB - .else - GET_VREG %eax, rINSTq # eax <- vB - .endif - andb $0xf,%cl # ecx <- A - - negl %eax - .if 0 - SET_WIDE_VREG %rax, %rcx - .else - SET_VREG %eax, %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_not_int: /* 0x7c */ -/* - * Generic 32/64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op eax". - */ - /* unop vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4,rINST # rINST <- B - .if 0 - GET_WIDE_VREG %rax, rINSTq # rax <- vB - .else - GET_VREG %eax, rINSTq # eax <- vB - .endif - andb $0xf,%cl # ecx <- A - - notl %eax - .if 0 - SET_WIDE_VREG %rax, %rcx - .else - SET_VREG %eax, %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_neg_long: /* 0x7d */ -/* - * Generic 32/64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op eax". - */ - /* unop vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4,rINST # rINST <- B - .if 1 - GET_WIDE_VREG %rax, rINSTq # rax <- vB - .else - GET_VREG %eax, rINSTq # eax <- vB - .endif - andb $0xf,%cl # ecx <- A - - negq %rax - .if 1 - SET_WIDE_VREG %rax, %rcx - .else - SET_VREG %eax, %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_not_long: /* 0x7e */ -/* - * Generic 32/64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op eax". - */ - /* unop vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4,rINST # rINST <- B - .if 1 - GET_WIDE_VREG %rax, rINSTq # rax <- vB - .else - GET_VREG %eax, rINSTq # eax <- vB - .endif - andb $0xf,%cl # ecx <- A - - notq %rax - .if 1 - SET_WIDE_VREG %rax, %rcx - .else - SET_VREG %eax, %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_neg_float: /* 0x7f */ -/* - * Generic 32/64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op eax". - */ - /* unop vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4,rINST # rINST <- B - .if 0 - GET_WIDE_VREG %rax, rINSTq # rax <- vB - .else - GET_VREG %eax, rINSTq # eax <- vB - .endif - andb $0xf,%cl # ecx <- A - - xorl $0x80000000, %eax - .if 0 - SET_WIDE_VREG %rax, %rcx - .else - SET_VREG %eax, %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_neg_double: /* 0x80 */ -/* - * Generic 32/64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op eax". - */ - /* unop vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4,rINST # rINST <- B - .if 1 - GET_WIDE_VREG %rax, rINSTq # rax <- vB - .else - GET_VREG %eax, rINSTq # eax <- vB - .endif - andb $0xf,%cl # ecx <- A - movq $0x8000000000000000, %rsi - xorq %rsi, %rax - .if 1 - SET_WIDE_VREG %rax, %rcx - .else - SET_VREG %eax, %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_long: /* 0x81 */ - /* int to long vA, vB */ - movzbq rINSTbl, %rax # rax <- +A - sarl $4, %eax # eax <- B - andb $0xf, rINSTbl # rINST <- A - movslq VREG_ADDRESS(%rax), %rax - SET_WIDE_VREG %rax, rINSTq # v[A] <- %rax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_float: /* 0x82 */ -/* - * Generic 32-bit FP conversion operation. - */ - /* unop vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - cvtsi2ssl VREG_ADDRESS(rINSTq), %xmm0 - .if 0 - movsd %xmm0, VREG_ADDRESS(%rcx) - CLEAR_WIDE_REF %rcx - .else - movss %xmm0, VREG_ADDRESS(%rcx) - CLEAR_REF %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_double: /* 0x83 */ -/* - * Generic 32-bit FP conversion operation. - */ - /* unop vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - cvtsi2sdl VREG_ADDRESS(rINSTq), %xmm0 - .if 1 - movsd %xmm0, VREG_ADDRESS(%rcx) - CLEAR_WIDE_REF %rcx - .else - movss %xmm0, VREG_ADDRESS(%rcx) - CLEAR_REF %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_long_to_int: /* 0x84 */ -/* we ignore the high word, making this equivalent to a 32-bit reg move */ - /* for move, move-object, long-to-int */ - /* op vA, vB */ - movl rINST, %eax # eax <- BA - andb $0xf, %al # eax <- A - shrl $4, rINST # rINST <- B - GET_VREG %edx, rINSTq - .if 0 - SET_VREG_OBJECT %edx, %rax # fp[A] <- fp[B] - .else - SET_VREG %edx, %rax # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_long_to_float: /* 0x85 */ -/* - * Generic 32-bit FP conversion operation. - */ - /* unop vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - cvtsi2ssq VREG_ADDRESS(rINSTq), %xmm0 - .if 0 - movsd %xmm0, VREG_ADDRESS(%rcx) - CLEAR_WIDE_REF %rcx - .else - movss %xmm0, VREG_ADDRESS(%rcx) - CLEAR_REF %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_long_to_double: /* 0x86 */ -/* - * Generic 32-bit FP conversion operation. - */ - /* unop vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - cvtsi2sdq VREG_ADDRESS(rINSTq), %xmm0 - .if 1 - movsd %xmm0, VREG_ADDRESS(%rcx) - CLEAR_WIDE_REF %rcx - .else - movss %xmm0, VREG_ADDRESS(%rcx) - CLEAR_REF %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_float_to_int: /* 0x87 */ -/* On fp to int conversions, Java requires that - * if the result > maxint, it should be clamped to maxint. If it is less - * than minint, it should be clamped to minint. If it is a nan, the result - * should be zero. Further, the rounding mode is to truncate. - */ - /* float/double to int/long vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - movss VREG_ADDRESS(rINSTq), %xmm0 - movl $0x7fffffff, %eax - cvtsi2ssl %eax, %xmm1 - comiss %xmm1, %xmm0 - jae 1f - jp 2f - cvttss2sil %xmm0, %eax - jmp 1f -2: - xorl %eax, %eax -1: - .if 0 - SET_WIDE_VREG %eax, %rcx - .else - SET_VREG %eax, %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_float_to_long: /* 0x88 */ -/* On fp to int conversions, Java requires that - * if the result > maxint, it should be clamped to maxint. If it is less - * than minint, it should be clamped to minint. If it is a nan, the result - * should be zero. Further, the rounding mode is to truncate. - */ - /* float/double to int/long vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - movss VREG_ADDRESS(rINSTq), %xmm0 - movq $0x7fffffffffffffff, %rax - cvtsi2ssq %rax, %xmm1 - comiss %xmm1, %xmm0 - jae 1f - jp 2f - cvttss2siq %xmm0, %rax - jmp 1f -2: - xorq %rax, %rax -1: - .if 1 - SET_WIDE_VREG %rax, %rcx - .else - SET_VREG %rax, %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_float_to_double: /* 0x89 */ -/* - * Generic 32-bit FP conversion operation. - */ - /* unop vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - cvtss2sd VREG_ADDRESS(rINSTq), %xmm0 - .if 1 - movsd %xmm0, VREG_ADDRESS(%rcx) - CLEAR_WIDE_REF %rcx - .else - movss %xmm0, VREG_ADDRESS(%rcx) - CLEAR_REF %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_double_to_int: /* 0x8a */ -/* On fp to int conversions, Java requires that - * if the result > maxint, it should be clamped to maxint. If it is less - * than minint, it should be clamped to minint. If it is a nan, the result - * should be zero. Further, the rounding mode is to truncate. - */ - /* float/double to int/long vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - movsd VREG_ADDRESS(rINSTq), %xmm0 - movl $0x7fffffff, %eax - cvtsi2sdl %eax, %xmm1 - comisd %xmm1, %xmm0 - jae 1f - jp 2f - cvttsd2sil %xmm0, %eax - jmp 1f -2: - xorl %eax, %eax -1: - .if 0 - SET_WIDE_VREG %eax, %rcx - .else - SET_VREG %eax, %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_double_to_long: /* 0x8b */ -/* On fp to int conversions, Java requires that - * if the result > maxint, it should be clamped to maxint. If it is less - * than minint, it should be clamped to minint. If it is a nan, the result - * should be zero. Further, the rounding mode is to truncate. - */ - /* float/double to int/long vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - movsd VREG_ADDRESS(rINSTq), %xmm0 - movq $0x7fffffffffffffff, %rax - cvtsi2sdq %rax, %xmm1 - comisd %xmm1, %xmm0 - jae 1f - jp 2f - cvttsd2siq %xmm0, %rax - jmp 1f -2: - xorq %rax, %rax -1: - .if 1 - SET_WIDE_VREG %rax, %rcx - .else - SET_VREG %rax, %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_double_to_float: /* 0x8c */ -/* - * Generic 32-bit FP conversion operation. - */ - /* unop vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - cvtsd2ss VREG_ADDRESS(rINSTq), %xmm0 - .if 0 - movsd %xmm0, VREG_ADDRESS(%rcx) - CLEAR_WIDE_REF %rcx - .else - movss %xmm0, VREG_ADDRESS(%rcx) - CLEAR_REF %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_byte: /* 0x8d */ -/* - * Generic 32/64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op eax". - */ - /* unop vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4,rINST # rINST <- B - .if 0 - GET_WIDE_VREG %rax, rINSTq # rax <- vB - .else - GET_VREG %eax, rINSTq # eax <- vB - .endif - andb $0xf,%cl # ecx <- A - -movsbl %al, %eax - .if 0 - SET_WIDE_VREG %rax, %rcx - .else - SET_VREG %eax, %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_char: /* 0x8e */ -/* - * Generic 32/64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op eax". - */ - /* unop vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4,rINST # rINST <- B - .if 0 - GET_WIDE_VREG %rax, rINSTq # rax <- vB - .else - GET_VREG %eax, rINSTq # eax <- vB - .endif - andb $0xf,%cl # ecx <- A - -movzwl %ax,%eax - .if 0 - SET_WIDE_VREG %rax, %rcx - .else - SET_VREG %eax, %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_short: /* 0x8f */ -/* - * Generic 32/64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op eax". - */ - /* unop vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4,rINST # rINST <- B - .if 0 - GET_WIDE_VREG %rax, rINSTq # rax <- vB - .else - GET_VREG %eax, rINSTq # eax <- vB - .endif - andb $0xf,%cl # ecx <- A - -movswl %ax, %eax - .if 0 - SET_WIDE_VREG %rax, %rcx - .else - SET_VREG %eax, %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_add_int: /* 0x90 */ -/* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = eax op (rFP,%ecx,4)". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int, sub-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - movzbq 2(rPC), %rax # rax <- BB - movzbq 3(rPC), %rcx # rcx <- CC - GET_VREG %eax, %rax # eax <- vBB - addl (rFP,%rcx,4), %eax # ex: addl (rFP,%rcx,4),%eax - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_sub_int: /* 0x91 */ -/* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = eax op (rFP,%ecx,4)". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int, sub-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - movzbq 2(rPC), %rax # rax <- BB - movzbq 3(rPC), %rcx # rcx <- CC - GET_VREG %eax, %rax # eax <- vBB - subl (rFP,%rcx,4), %eax # ex: addl (rFP,%rcx,4),%eax - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int: /* 0x92 */ -/* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = eax op (rFP,%ecx,4)". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int, sub-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - movzbq 2(rPC), %rax # rax <- BB - movzbq 3(rPC), %rcx # rcx <- CC - GET_VREG %eax, %rax # eax <- vBB - imull (rFP,%rcx,4), %eax # ex: addl (rFP,%rcx,4),%eax - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_div_int: /* 0x93 */ -/* - * 32-bit binary div/rem operation. Handles special case of op1=-1. - */ - /* div/rem vAA, vBB, vCC */ - movzbq 2(rPC), %rax # rax <- BB - movzbq 3(rPC), %rcx # rcx <- CC - .if 0 - GET_WIDE_VREG %rax, %rax # eax <- vBB - GET_WIDE_VREG %ecx, %rcx # ecx <- vCC - .else - GET_VREG %eax, %rax # eax <- vBB - GET_VREG %ecx, %rcx # ecx <- vCC - .endif - testl %ecx, %ecx - jz common_errDivideByZero - cmpl $-1, %ecx - je 2f - cdq # rdx:rax <- sign-extended of rax - idivl %ecx -1: - .if 0 - SET_WIDE_VREG %eax, rINSTq # eax <- vBB - .else - SET_VREG %eax, rINSTq # eax <- vBB - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 -2: - .if 0 - xorl %eax, %eax - .else - negl %eax - .endif - jmp 1b - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int: /* 0x94 */ -/* - * 32-bit binary div/rem operation. Handles special case of op1=-1. - */ - /* div/rem vAA, vBB, vCC */ - movzbq 2(rPC), %rax # rax <- BB - movzbq 3(rPC), %rcx # rcx <- CC - .if 0 - GET_WIDE_VREG %rax, %rax # eax <- vBB - GET_WIDE_VREG %ecx, %rcx # ecx <- vCC - .else - GET_VREG %eax, %rax # eax <- vBB - GET_VREG %ecx, %rcx # ecx <- vCC - .endif - testl %ecx, %ecx - jz common_errDivideByZero - cmpl $-1, %ecx - je 2f - cdq # rdx:rax <- sign-extended of rax - idivl %ecx -1: - .if 0 - SET_WIDE_VREG %edx, rINSTq # eax <- vBB - .else - SET_VREG %edx, rINSTq # eax <- vBB - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 -2: - .if 1 - xorl %edx, %edx - .else - negl %edx - .endif - jmp 1b - -/* ------------------------------ */ - .balign 128 -.L_op_and_int: /* 0x95 */ -/* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = eax op (rFP,%ecx,4)". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int, sub-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - movzbq 2(rPC), %rax # rax <- BB - movzbq 3(rPC), %rcx # rcx <- CC - GET_VREG %eax, %rax # eax <- vBB - andl (rFP,%rcx,4), %eax # ex: addl (rFP,%rcx,4),%eax - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_or_int: /* 0x96 */ -/* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = eax op (rFP,%ecx,4)". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int, sub-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - movzbq 2(rPC), %rax # rax <- BB - movzbq 3(rPC), %rcx # rcx <- CC - GET_VREG %eax, %rax # eax <- vBB - orl (rFP,%rcx,4), %eax # ex: addl (rFP,%rcx,4),%eax - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int: /* 0x97 */ -/* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = eax op (rFP,%ecx,4)". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int, sub-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - movzbq 2(rPC), %rax # rax <- BB - movzbq 3(rPC), %rcx # rcx <- CC - GET_VREG %eax, %rax # eax <- vBB - xorl (rFP,%rcx,4), %eax # ex: addl (rFP,%rcx,4),%eax - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_shl_int: /* 0x98 */ -/* - * Generic 32-bit binary operation in which both operands loaded to - * registers (op0 in eax, op1 in ecx). - */ - /* binop vAA, vBB, vCC */ - movzbq 2(rPC), %rax # eax <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_VREG %ecx, %rcx # eax <- vCC - .if 0 - GET_WIDE_VREG %rax, %rax # rax <- vBB - sall %cl, %eax # ex: addl %ecx,%eax - SET_WIDE_VREG %rax, rINSTq - .else - GET_VREG %eax, %rax # eax <- vBB - sall %cl, %eax # ex: addl %ecx,%eax - SET_VREG %eax, rINSTq - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_shr_int: /* 0x99 */ -/* - * Generic 32-bit binary operation in which both operands loaded to - * registers (op0 in eax, op1 in ecx). - */ - /* binop vAA, vBB, vCC */ - movzbq 2(rPC), %rax # eax <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_VREG %ecx, %rcx # eax <- vCC - .if 0 - GET_WIDE_VREG %rax, %rax # rax <- vBB - sarl %cl, %eax # ex: addl %ecx,%eax - SET_WIDE_VREG %rax, rINSTq - .else - GET_VREG %eax, %rax # eax <- vBB - sarl %cl, %eax # ex: addl %ecx,%eax - SET_VREG %eax, rINSTq - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_int: /* 0x9a */ -/* - * Generic 32-bit binary operation in which both operands loaded to - * registers (op0 in eax, op1 in ecx). - */ - /* binop vAA, vBB, vCC */ - movzbq 2(rPC), %rax # eax <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_VREG %ecx, %rcx # eax <- vCC - .if 0 - GET_WIDE_VREG %rax, %rax # rax <- vBB - shrl %cl, %eax # ex: addl %ecx,%eax - SET_WIDE_VREG %rax, rINSTq - .else - GET_VREG %eax, %rax # eax <- vBB - shrl %cl, %eax # ex: addl %ecx,%eax - SET_VREG %eax, rINSTq - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_add_long: /* 0x9b */ -/* - * Generic 64-bit binary operation. - */ - /* binop vAA, vBB, vCC */ - movzbq 2(rPC), %rax # eax <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_WIDE_VREG %rax, %rax # rax <- v[BB] - addq (rFP,%rcx,4), %rax # ex: addq (rFP,%rcx,4),%rax - SET_WIDE_VREG %rax, rINSTq # v[AA] <- rax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_sub_long: /* 0x9c */ -/* - * Generic 64-bit binary operation. - */ - /* binop vAA, vBB, vCC */ - movzbq 2(rPC), %rax # eax <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_WIDE_VREG %rax, %rax # rax <- v[BB] - subq (rFP,%rcx,4), %rax # ex: addq (rFP,%rcx,4),%rax - SET_WIDE_VREG %rax, rINSTq # v[AA] <- rax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_mul_long: /* 0x9d */ -/* - * Generic 64-bit binary operation. - */ - /* binop vAA, vBB, vCC */ - movzbq 2(rPC), %rax # eax <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_WIDE_VREG %rax, %rax # rax <- v[BB] - imulq (rFP,%rcx,4), %rax # ex: addq (rFP,%rcx,4),%rax - SET_WIDE_VREG %rax, rINSTq # v[AA] <- rax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_div_long: /* 0x9e */ -/* - * 32-bit binary div/rem operation. Handles special case of op1=-1. - */ - /* div/rem vAA, vBB, vCC */ - movzbq 2(rPC), %rax # rax <- BB - movzbq 3(rPC), %rcx # rcx <- CC - .if 1 - GET_WIDE_VREG %rax, %rax # eax <- vBB - GET_WIDE_VREG %rcx, %rcx # ecx <- vCC - .else - GET_VREG %eax, %rax # eax <- vBB - GET_VREG %rcx, %rcx # ecx <- vCC - .endif - testq %rcx, %rcx - jz common_errDivideByZero - cmpq $-1, %rcx - je 2f - cqo # rdx:rax <- sign-extended of rax - idivq %rcx -1: - .if 1 - SET_WIDE_VREG %rax, rINSTq # eax <- vBB - .else - SET_VREG %rax, rINSTq # eax <- vBB - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 -2: - .if 0 - xorq %rax, %rax - .else - negq %rax - .endif - jmp 1b - -/* ------------------------------ */ - .balign 128 -.L_op_rem_long: /* 0x9f */ -/* - * 32-bit binary div/rem operation. Handles special case of op1=-1. - */ - /* div/rem vAA, vBB, vCC */ - movzbq 2(rPC), %rax # rax <- BB - movzbq 3(rPC), %rcx # rcx <- CC - .if 1 - GET_WIDE_VREG %rax, %rax # eax <- vBB - GET_WIDE_VREG %rcx, %rcx # ecx <- vCC - .else - GET_VREG %eax, %rax # eax <- vBB - GET_VREG %rcx, %rcx # ecx <- vCC - .endif - testq %rcx, %rcx - jz common_errDivideByZero - cmpq $-1, %rcx - je 2f - cqo # rdx:rax <- sign-extended of rax - idivq %rcx -1: - .if 1 - SET_WIDE_VREG %rdx, rINSTq # eax <- vBB - .else - SET_VREG %rdx, rINSTq # eax <- vBB - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 -2: - .if 1 - xorq %rdx, %rdx - .else - negq %rdx - .endif - jmp 1b - -/* ------------------------------ */ - .balign 128 -.L_op_and_long: /* 0xa0 */ -/* - * Generic 64-bit binary operation. - */ - /* binop vAA, vBB, vCC */ - movzbq 2(rPC), %rax # eax <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_WIDE_VREG %rax, %rax # rax <- v[BB] - andq (rFP,%rcx,4), %rax # ex: addq (rFP,%rcx,4),%rax - SET_WIDE_VREG %rax, rINSTq # v[AA] <- rax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_or_long: /* 0xa1 */ -/* - * Generic 64-bit binary operation. - */ - /* binop vAA, vBB, vCC */ - movzbq 2(rPC), %rax # eax <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_WIDE_VREG %rax, %rax # rax <- v[BB] - orq (rFP,%rcx,4), %rax # ex: addq (rFP,%rcx,4),%rax - SET_WIDE_VREG %rax, rINSTq # v[AA] <- rax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_xor_long: /* 0xa2 */ -/* - * Generic 64-bit binary operation. - */ - /* binop vAA, vBB, vCC */ - movzbq 2(rPC), %rax # eax <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_WIDE_VREG %rax, %rax # rax <- v[BB] - xorq (rFP,%rcx,4), %rax # ex: addq (rFP,%rcx,4),%rax - SET_WIDE_VREG %rax, rINSTq # v[AA] <- rax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_shl_long: /* 0xa3 */ -/* - * Generic 32-bit binary operation in which both operands loaded to - * registers (op0 in eax, op1 in ecx). - */ - /* binop vAA, vBB, vCC */ - movzbq 2(rPC), %rax # eax <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_VREG %ecx, %rcx # eax <- vCC - .if 1 - GET_WIDE_VREG %rax, %rax # rax <- vBB - salq %cl, %rax # ex: addl %ecx,%eax - SET_WIDE_VREG %rax, rINSTq - .else - GET_VREG %eax, %rax # eax <- vBB - salq %cl, %rax # ex: addl %ecx,%eax - SET_VREG %eax, rINSTq - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_shr_long: /* 0xa4 */ -/* - * Generic 32-bit binary operation in which both operands loaded to - * registers (op0 in eax, op1 in ecx). - */ - /* binop vAA, vBB, vCC */ - movzbq 2(rPC), %rax # eax <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_VREG %ecx, %rcx # eax <- vCC - .if 1 - GET_WIDE_VREG %rax, %rax # rax <- vBB - sarq %cl, %rax # ex: addl %ecx,%eax - SET_WIDE_VREG %rax, rINSTq - .else - GET_VREG %eax, %rax # eax <- vBB - sarq %cl, %rax # ex: addl %ecx,%eax - SET_VREG %eax, rINSTq - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_long: /* 0xa5 */ -/* - * Generic 32-bit binary operation in which both operands loaded to - * registers (op0 in eax, op1 in ecx). - */ - /* binop vAA, vBB, vCC */ - movzbq 2(rPC), %rax # eax <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_VREG %ecx, %rcx # eax <- vCC - .if 1 - GET_WIDE_VREG %rax, %rax # rax <- vBB - shrq %cl, %rax # ex: addl %ecx,%eax - SET_WIDE_VREG %rax, rINSTq - .else - GET_VREG %eax, %rax # eax <- vBB - shrq %cl, %rax # ex: addl %ecx,%eax - SET_VREG %eax, rINSTq - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_add_float: /* 0xa6 */ - movzbq 2(rPC), %rcx # ecx <- BB - movzbq 3(rPC), %rax # eax <- CC - movss VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src - addss VREG_ADDRESS(%rax), %xmm0 - movss %xmm0, VREG_ADDRESS(rINSTq) # vAA <- %xmm0 - pxor %xmm0, %xmm0 - movss %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_sub_float: /* 0xa7 */ - movzbq 2(rPC), %rcx # ecx <- BB - movzbq 3(rPC), %rax # eax <- CC - movss VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src - subss VREG_ADDRESS(%rax), %xmm0 - movss %xmm0, VREG_ADDRESS(rINSTq) # vAA <- %xmm0 - pxor %xmm0, %xmm0 - movss %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_mul_float: /* 0xa8 */ - movzbq 2(rPC), %rcx # ecx <- BB - movzbq 3(rPC), %rax # eax <- CC - movss VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src - mulss VREG_ADDRESS(%rax), %xmm0 - movss %xmm0, VREG_ADDRESS(rINSTq) # vAA <- %xmm0 - pxor %xmm0, %xmm0 - movss %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_div_float: /* 0xa9 */ - movzbq 2(rPC), %rcx # ecx <- BB - movzbq 3(rPC), %rax # eax <- CC - movss VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src - divss VREG_ADDRESS(%rax), %xmm0 - movss %xmm0, VREG_ADDRESS(rINSTq) # vAA <- %xmm0 - pxor %xmm0, %xmm0 - movss %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_rem_float: /* 0xaa */ - /* rem_float vAA, vBB, vCC */ - movzbq 3(rPC), %rcx # ecx <- BB - movzbq 2(rPC), %rax # eax <- CC - flds VREG_ADDRESS(%rcx) # vBB to fp stack - flds VREG_ADDRESS(%rax) # vCC to fp stack -1: - fprem - fstsw %ax - sahf - jp 1b - fstp %st(1) - fstps VREG_ADDRESS(rINSTq) # %st to vAA - CLEAR_REF rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_add_double: /* 0xab */ - movzbq 2(rPC), %rcx # ecx <- BB - movzbq 3(rPC), %rax # eax <- CC - movsd VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src - addsd VREG_ADDRESS(%rax), %xmm0 - movsd %xmm0, VREG_ADDRESS(rINSTq) # vAA <- %xmm0 - pxor %xmm0, %xmm0 - movsd %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_sub_double: /* 0xac */ - movzbq 2(rPC), %rcx # ecx <- BB - movzbq 3(rPC), %rax # eax <- CC - movsd VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src - subsd VREG_ADDRESS(%rax), %xmm0 - movsd %xmm0, VREG_ADDRESS(rINSTq) # vAA <- %xmm0 - pxor %xmm0, %xmm0 - movsd %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_mul_double: /* 0xad */ - movzbq 2(rPC), %rcx # ecx <- BB - movzbq 3(rPC), %rax # eax <- CC - movsd VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src - mulsd VREG_ADDRESS(%rax), %xmm0 - movsd %xmm0, VREG_ADDRESS(rINSTq) # vAA <- %xmm0 - pxor %xmm0, %xmm0 - movsd %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_div_double: /* 0xae */ - movzbq 2(rPC), %rcx # ecx <- BB - movzbq 3(rPC), %rax # eax <- CC - movsd VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src - divsd VREG_ADDRESS(%rax), %xmm0 - movsd %xmm0, VREG_ADDRESS(rINSTq) # vAA <- %xmm0 - pxor %xmm0, %xmm0 - movsd %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_rem_double: /* 0xaf */ - /* rem_double vAA, vBB, vCC */ - movzbq 3(rPC), %rcx # ecx <- BB - movzbq 2(rPC), %rax # eax <- CC - fldl VREG_ADDRESS(%rcx) # %st1 <- fp[vBB] - fldl VREG_ADDRESS(%rax) # %st0 <- fp[vCC] -1: - fprem - fstsw %ax - sahf - jp 1b - fstp %st(1) - fstpl VREG_ADDRESS(rINSTq) # fp[vAA] <- %st - CLEAR_WIDE_REF rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_add_int_2addr: /* 0xb0 */ -/* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an instruction or a function call. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - GET_VREG %eax, rINSTq # eax <- vB - addl %eax, (rFP,%rcx,4) # for ex: addl %eax,(rFP,%ecx,4) - CLEAR_REF %rcx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_sub_int_2addr: /* 0xb1 */ -/* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an instruction or a function call. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - GET_VREG %eax, rINSTq # eax <- vB - subl %eax, (rFP,%rcx,4) # for ex: addl %eax,(rFP,%ecx,4) - CLEAR_REF %rcx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int_2addr: /* 0xb2 */ - /* mul vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - GET_VREG %eax, %rcx # eax <- vA - imull (rFP,rINSTq,4), %eax - SET_VREG %eax, %rcx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_div_int_2addr: /* 0xb3 */ -/* - * 32-bit binary div/rem operation. Handles special case of op1=-1. - */ - /* div/rem/2addr vA, vB */ - movl rINST, %ecx # rcx <- BA - sarl $4, %ecx # rcx <- B - andb $0xf, rINSTbl # rINST <- A - .if 0 - GET_WIDE_VREG %rax, rINSTq # eax <- vA - GET_WIDE_VREG %ecx, %rcx # ecx <- vB - .else - GET_VREG %eax, rINSTq # eax <- vA - GET_VREG %ecx, %rcx # ecx <- vB - .endif - testl %ecx, %ecx - jz common_errDivideByZero - cmpl $-1, %ecx - je 2f - cdq # rdx:rax <- sign-extended of rax - idivl %ecx -1: - .if 0 - SET_WIDE_VREG %eax, rINSTq # vA <- result - .else - SET_VREG %eax, rINSTq # vA <- result - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 -2: - .if 0 - xorl %eax, %eax - .else - negl %eax - .endif - jmp 1b - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int_2addr: /* 0xb4 */ -/* - * 32-bit binary div/rem operation. Handles special case of op1=-1. - */ - /* div/rem/2addr vA, vB */ - movl rINST, %ecx # rcx <- BA - sarl $4, %ecx # rcx <- B - andb $0xf, rINSTbl # rINST <- A - .if 0 - GET_WIDE_VREG %rax, rINSTq # eax <- vA - GET_WIDE_VREG %ecx, %rcx # ecx <- vB - .else - GET_VREG %eax, rINSTq # eax <- vA - GET_VREG %ecx, %rcx # ecx <- vB - .endif - testl %ecx, %ecx - jz common_errDivideByZero - cmpl $-1, %ecx - je 2f - cdq # rdx:rax <- sign-extended of rax - idivl %ecx -1: - .if 0 - SET_WIDE_VREG %edx, rINSTq # vA <- result - .else - SET_VREG %edx, rINSTq # vA <- result - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 -2: - .if 1 - xorl %edx, %edx - .else - negl %edx - .endif - jmp 1b - -/* ------------------------------ */ - .balign 128 -.L_op_and_int_2addr: /* 0xb5 */ -/* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an instruction or a function call. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - GET_VREG %eax, rINSTq # eax <- vB - andl %eax, (rFP,%rcx,4) # for ex: addl %eax,(rFP,%ecx,4) - CLEAR_REF %rcx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_or_int_2addr: /* 0xb6 */ -/* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an instruction or a function call. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - GET_VREG %eax, rINSTq # eax <- vB - orl %eax, (rFP,%rcx,4) # for ex: addl %eax,(rFP,%ecx,4) - CLEAR_REF %rcx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int_2addr: /* 0xb7 */ -/* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an instruction or a function call. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - GET_VREG %eax, rINSTq # eax <- vB - xorl %eax, (rFP,%rcx,4) # for ex: addl %eax,(rFP,%ecx,4) - CLEAR_REF %rcx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_shl_int_2addr: /* 0xb8 */ -/* - * Generic 32-bit "shift/2addr" operation. - */ - /* shift/2addr vA, vB */ - movl rINST, %ecx # ecx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %rcx # ecx <- vBB - andb $0xf, rINSTbl # rINST <- A - .if 0 - GET_WIDE_VREG %rax, rINSTq # rax <- vAA - sall %cl, %eax # ex: sarl %cl, %eax - SET_WIDE_VREG %rax, rINSTq - .else - GET_VREG %eax, rINSTq # eax <- vAA - sall %cl, %eax # ex: sarl %cl, %eax - SET_VREG %eax, rINSTq - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_shr_int_2addr: /* 0xb9 */ -/* - * Generic 32-bit "shift/2addr" operation. - */ - /* shift/2addr vA, vB */ - movl rINST, %ecx # ecx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %rcx # ecx <- vBB - andb $0xf, rINSTbl # rINST <- A - .if 0 - GET_WIDE_VREG %rax, rINSTq # rax <- vAA - sarl %cl, %eax # ex: sarl %cl, %eax - SET_WIDE_VREG %rax, rINSTq - .else - GET_VREG %eax, rINSTq # eax <- vAA - sarl %cl, %eax # ex: sarl %cl, %eax - SET_VREG %eax, rINSTq - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_int_2addr: /* 0xba */ -/* - * Generic 32-bit "shift/2addr" operation. - */ - /* shift/2addr vA, vB */ - movl rINST, %ecx # ecx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %rcx # ecx <- vBB - andb $0xf, rINSTbl # rINST <- A - .if 0 - GET_WIDE_VREG %rax, rINSTq # rax <- vAA - shrl %cl, %eax # ex: sarl %cl, %eax - SET_WIDE_VREG %rax, rINSTq - .else - GET_VREG %eax, rINSTq # eax <- vAA - shrl %cl, %eax # ex: sarl %cl, %eax - SET_VREG %eax, rINSTq - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_add_long_2addr: /* 0xbb */ -/* - * Generic 64-bit binary operation. - */ - /* binop/2addr vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - GET_WIDE_VREG %rax, rINSTq # rax <- vB - addq %rax, (rFP,%rcx,4) # for ex: addq %rax,(rFP,%rcx,4) - CLEAR_WIDE_REF %rcx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_sub_long_2addr: /* 0xbc */ -/* - * Generic 64-bit binary operation. - */ - /* binop/2addr vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - GET_WIDE_VREG %rax, rINSTq # rax <- vB - subq %rax, (rFP,%rcx,4) # for ex: addq %rax,(rFP,%rcx,4) - CLEAR_WIDE_REF %rcx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_mul_long_2addr: /* 0xbd */ - /* mul vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - GET_WIDE_VREG %rax, %rcx # rax <- vA - imulq (rFP,rINSTq,4), %rax - SET_WIDE_VREG %rax, %rcx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_div_long_2addr: /* 0xbe */ -/* - * 32-bit binary div/rem operation. Handles special case of op1=-1. - */ - /* div/rem/2addr vA, vB */ - movl rINST, %ecx # rcx <- BA - sarl $4, %ecx # rcx <- B - andb $0xf, rINSTbl # rINST <- A - .if 1 - GET_WIDE_VREG %rax, rINSTq # eax <- vA - GET_WIDE_VREG %rcx, %rcx # ecx <- vB - .else - GET_VREG %eax, rINSTq # eax <- vA - GET_VREG %rcx, %rcx # ecx <- vB - .endif - testq %rcx, %rcx - jz common_errDivideByZero - cmpq $-1, %rcx - je 2f - cqo # rdx:rax <- sign-extended of rax - idivq %rcx -1: - .if 1 - SET_WIDE_VREG %rax, rINSTq # vA <- result - .else - SET_VREG %rax, rINSTq # vA <- result - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 -2: - .if 0 - xorq %rax, %rax - .else - negq %rax - .endif - jmp 1b - -/* ------------------------------ */ - .balign 128 -.L_op_rem_long_2addr: /* 0xbf */ -/* - * 32-bit binary div/rem operation. Handles special case of op1=-1. - */ - /* div/rem/2addr vA, vB */ - movl rINST, %ecx # rcx <- BA - sarl $4, %ecx # rcx <- B - andb $0xf, rINSTbl # rINST <- A - .if 1 - GET_WIDE_VREG %rax, rINSTq # eax <- vA - GET_WIDE_VREG %rcx, %rcx # ecx <- vB - .else - GET_VREG %eax, rINSTq # eax <- vA - GET_VREG %rcx, %rcx # ecx <- vB - .endif - testq %rcx, %rcx - jz common_errDivideByZero - cmpq $-1, %rcx - je 2f - cqo # rdx:rax <- sign-extended of rax - idivq %rcx -1: - .if 1 - SET_WIDE_VREG %rdx, rINSTq # vA <- result - .else - SET_VREG %rdx, rINSTq # vA <- result - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 -2: - .if 1 - xorq %rdx, %rdx - .else - negq %rdx - .endif - jmp 1b - -/* ------------------------------ */ - .balign 128 -.L_op_and_long_2addr: /* 0xc0 */ -/* - * Generic 64-bit binary operation. - */ - /* binop/2addr vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - GET_WIDE_VREG %rax, rINSTq # rax <- vB - andq %rax, (rFP,%rcx,4) # for ex: addq %rax,(rFP,%rcx,4) - CLEAR_WIDE_REF %rcx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_or_long_2addr: /* 0xc1 */ -/* - * Generic 64-bit binary operation. - */ - /* binop/2addr vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - GET_WIDE_VREG %rax, rINSTq # rax <- vB - orq %rax, (rFP,%rcx,4) # for ex: addq %rax,(rFP,%rcx,4) - CLEAR_WIDE_REF %rcx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_xor_long_2addr: /* 0xc2 */ -/* - * Generic 64-bit binary operation. - */ - /* binop/2addr vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - GET_WIDE_VREG %rax, rINSTq # rax <- vB - xorq %rax, (rFP,%rcx,4) # for ex: addq %rax,(rFP,%rcx,4) - CLEAR_WIDE_REF %rcx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_shl_long_2addr: /* 0xc3 */ -/* - * Generic 32-bit "shift/2addr" operation. - */ - /* shift/2addr vA, vB */ - movl rINST, %ecx # ecx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %rcx # ecx <- vBB - andb $0xf, rINSTbl # rINST <- A - .if 1 - GET_WIDE_VREG %rax, rINSTq # rax <- vAA - salq %cl, %rax # ex: sarl %cl, %eax - SET_WIDE_VREG %rax, rINSTq - .else - GET_VREG %eax, rINSTq # eax <- vAA - salq %cl, %rax # ex: sarl %cl, %eax - SET_VREG %eax, rINSTq - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_shr_long_2addr: /* 0xc4 */ -/* - * Generic 32-bit "shift/2addr" operation. - */ - /* shift/2addr vA, vB */ - movl rINST, %ecx # ecx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %rcx # ecx <- vBB - andb $0xf, rINSTbl # rINST <- A - .if 1 - GET_WIDE_VREG %rax, rINSTq # rax <- vAA - sarq %cl, %rax # ex: sarl %cl, %eax - SET_WIDE_VREG %rax, rINSTq - .else - GET_VREG %eax, rINSTq # eax <- vAA - sarq %cl, %rax # ex: sarl %cl, %eax - SET_VREG %eax, rINSTq - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_long_2addr: /* 0xc5 */ -/* - * Generic 32-bit "shift/2addr" operation. - */ - /* shift/2addr vA, vB */ - movl rINST, %ecx # ecx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %rcx # ecx <- vBB - andb $0xf, rINSTbl # rINST <- A - .if 1 - GET_WIDE_VREG %rax, rINSTq # rax <- vAA - shrq %cl, %rax # ex: sarl %cl, %eax - SET_WIDE_VREG %rax, rINSTq - .else - GET_VREG %eax, rINSTq # eax <- vAA - shrq %cl, %rax # ex: sarl %cl, %eax - SET_VREG %eax, rINSTq - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_add_float_2addr: /* 0xc6 */ - movl rINST, %ecx # ecx <- A+ - andl $0xf, %ecx # ecx <- A - movss VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src - sarl $4, rINST # rINST<- B - addss VREG_ADDRESS(rINSTq), %xmm0 - movss %xmm0, VREG_ADDRESS(%rcx) # vAA<- %xmm0 - pxor %xmm0, %xmm0 - movss %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_sub_float_2addr: /* 0xc7 */ - movl rINST, %ecx # ecx <- A+ - andl $0xf, %ecx # ecx <- A - movss VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src - sarl $4, rINST # rINST<- B - subss VREG_ADDRESS(rINSTq), %xmm0 - movss %xmm0, VREG_ADDRESS(%rcx) # vAA<- %xmm0 - pxor %xmm0, %xmm0 - movss %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_mul_float_2addr: /* 0xc8 */ - movl rINST, %ecx # ecx <- A+ - andl $0xf, %ecx # ecx <- A - movss VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src - sarl $4, rINST # rINST<- B - mulss VREG_ADDRESS(rINSTq), %xmm0 - movss %xmm0, VREG_ADDRESS(%rcx) # vAA<- %xmm0 - pxor %xmm0, %xmm0 - movss %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_div_float_2addr: /* 0xc9 */ - movl rINST, %ecx # ecx <- A+ - andl $0xf, %ecx # ecx <- A - movss VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src - sarl $4, rINST # rINST<- B - divss VREG_ADDRESS(rINSTq), %xmm0 - movss %xmm0, VREG_ADDRESS(%rcx) # vAA<- %xmm0 - pxor %xmm0, %xmm0 - movss %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_rem_float_2addr: /* 0xca */ - /* rem_float/2addr vA, vB */ - movzbq rINSTbl, %rcx # ecx <- A+ - sarl $4, rINST # rINST <- B - flds VREG_ADDRESS(rINSTq) # vB to fp stack - andb $0xf, %cl # ecx <- A - flds VREG_ADDRESS(%rcx) # vA to fp stack -1: - fprem - fstsw %ax - sahf - jp 1b - fstp %st(1) - fstps VREG_ADDRESS(%rcx) # %st to vA - CLEAR_REF %rcx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_add_double_2addr: /* 0xcb */ - movl rINST, %ecx # ecx <- A+ - andl $0xf, %ecx # ecx <- A - movsd VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src - sarl $4, rINST # rINST<- B - addsd VREG_ADDRESS(rINSTq), %xmm0 - movsd %xmm0, VREG_ADDRESS(%rcx) # vAA<- %xmm0 - pxor %xmm0, %xmm0 - movsd %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_sub_double_2addr: /* 0xcc */ - movl rINST, %ecx # ecx <- A+ - andl $0xf, %ecx # ecx <- A - movsd VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src - sarl $4, rINST # rINST<- B - subsd VREG_ADDRESS(rINSTq), %xmm0 - movsd %xmm0, VREG_ADDRESS(%rcx) # vAA<- %xmm0 - pxor %xmm0, %xmm0 - movsd %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_mul_double_2addr: /* 0xcd */ - movl rINST, %ecx # ecx <- A+ - andl $0xf, %ecx # ecx <- A - movsd VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src - sarl $4, rINST # rINST<- B - mulsd VREG_ADDRESS(rINSTq), %xmm0 - movsd %xmm0, VREG_ADDRESS(%rcx) # vAA<- %xmm0 - pxor %xmm0, %xmm0 - movsd %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_div_double_2addr: /* 0xce */ - movl rINST, %ecx # ecx <- A+ - andl $0xf, %ecx # ecx <- A - movsd VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src - sarl $4, rINST # rINST<- B - divsd VREG_ADDRESS(rINSTq), %xmm0 - movsd %xmm0, VREG_ADDRESS(%rcx) # vAA<- %xmm0 - pxor %xmm0, %xmm0 - movsd %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_rem_double_2addr: /* 0xcf */ - /* rem_double/2addr vA, vB */ - movzbq rINSTbl, %rcx # ecx <- A+ - sarl $4, rINST # rINST <- B - fldl VREG_ADDRESS(rINSTq) # vB to fp stack - andb $0xf, %cl # ecx <- A - fldl VREG_ADDRESS(%rcx) # vA to fp stack -1: - fprem - fstsw %ax - sahf - jp 1b - fstp %st(1) - fstpl VREG_ADDRESS(%rcx) # %st to vA - CLEAR_WIDE_REF %rcx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_add_int_lit16: /* 0xd0 */ -/* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int/lit16, rsub-int, - * and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - movl rINST, %eax # rax <- 000000BA - sarl $4, %eax # eax <- B - GET_VREG %eax, %rax # eax <- vB - andb $0xf, rINSTbl # rINST <- A - movswl 2(rPC), %ecx # ecx <- ssssCCCC - addl %ecx, %eax # for example: addl %ecx, %eax - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_rsub_int: /* 0xd1 */ -/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ -/* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int/lit16, rsub-int, - * and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - movl rINST, %eax # rax <- 000000BA - sarl $4, %eax # eax <- B - GET_VREG %eax, %rax # eax <- vB - andb $0xf, rINSTbl # rINST <- A - movswl 2(rPC), %ecx # ecx <- ssssCCCC - subl %eax, %ecx # for example: addl %ecx, %eax - SET_VREG %ecx, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int_lit16: /* 0xd2 */ -/* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int/lit16, rsub-int, - * and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - movl rINST, %eax # rax <- 000000BA - sarl $4, %eax # eax <- B - GET_VREG %eax, %rax # eax <- vB - andb $0xf, rINSTbl # rINST <- A - movswl 2(rPC), %ecx # ecx <- ssssCCCC - imull %ecx, %eax # for example: addl %ecx, %eax - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_div_int_lit16: /* 0xd3 */ -/* - * 32-bit binary div/rem operation. Handles special case of op1=-1. - */ - /* div/rem/lit16 vA, vB, #+CCCC */ - /* Need A in rINST, ssssCCCC in ecx, vB in eax */ - movl rINST, %eax # rax <- 000000BA - sarl $4, %eax # eax <- B - GET_VREG %eax, %rax # eax <- vB - movswl 2(rPC), %ecx # ecx <- ssssCCCC - andb $0xf, rINSTbl # rINST <- A - testl %ecx, %ecx - jz common_errDivideByZero - cmpl $-1, %ecx - je 2f - cdq # rax <- sign-extended of eax - idivl %ecx -1: - SET_VREG %eax, rINSTq # vA <- result - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 -2: - .if 0 - xorl %eax, %eax - .else - negl %eax - .endif - jmp 1b - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int_lit16: /* 0xd4 */ -/* - * 32-bit binary div/rem operation. Handles special case of op1=-1. - */ - /* div/rem/lit16 vA, vB, #+CCCC */ - /* Need A in rINST, ssssCCCC in ecx, vB in eax */ - movl rINST, %eax # rax <- 000000BA - sarl $4, %eax # eax <- B - GET_VREG %eax, %rax # eax <- vB - movswl 2(rPC), %ecx # ecx <- ssssCCCC - andb $0xf, rINSTbl # rINST <- A - testl %ecx, %ecx - jz common_errDivideByZero - cmpl $-1, %ecx - je 2f - cdq # rax <- sign-extended of eax - idivl %ecx -1: - SET_VREG %edx, rINSTq # vA <- result - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 -2: - .if 1 - xorl %edx, %edx - .else - negl %edx - .endif - jmp 1b - -/* ------------------------------ */ - .balign 128 -.L_op_and_int_lit16: /* 0xd5 */ -/* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int/lit16, rsub-int, - * and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - movl rINST, %eax # rax <- 000000BA - sarl $4, %eax # eax <- B - GET_VREG %eax, %rax # eax <- vB - andb $0xf, rINSTbl # rINST <- A - movswl 2(rPC), %ecx # ecx <- ssssCCCC - andl %ecx, %eax # for example: addl %ecx, %eax - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_or_int_lit16: /* 0xd6 */ -/* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int/lit16, rsub-int, - * and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - movl rINST, %eax # rax <- 000000BA - sarl $4, %eax # eax <- B - GET_VREG %eax, %rax # eax <- vB - andb $0xf, rINSTbl # rINST <- A - movswl 2(rPC), %ecx # ecx <- ssssCCCC - orl %ecx, %eax # for example: addl %ecx, %eax - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int_lit16: /* 0xd7 */ -/* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int/lit16, rsub-int, - * and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - movl rINST, %eax # rax <- 000000BA - sarl $4, %eax # eax <- B - GET_VREG %eax, %rax # eax <- vB - andb $0xf, rINSTbl # rINST <- A - movswl 2(rPC), %ecx # ecx <- ssssCCCC - xorl %ecx, %eax # for example: addl %ecx, %eax - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_add_int_lit8: /* 0xd8 */ -/* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * For: add-int/lit8, rsub-int/lit8 - * and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - movzbq 2(rPC), %rax # rax <- BB - movsbl 3(rPC), %ecx # rcx <- ssssssCC - GET_VREG %eax, %rax # eax <- rBB - addl %ecx, %eax # ex: addl %ecx,%eax - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_rsub_int_lit8: /* 0xd9 */ -/* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * For: add-int/lit8, rsub-int/lit8 - * and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - movzbq 2(rPC), %rax # rax <- BB - movsbl 3(rPC), %ecx # rcx <- ssssssCC - GET_VREG %eax, %rax # eax <- rBB - subl %eax, %ecx # ex: addl %ecx,%eax - SET_VREG %ecx, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int_lit8: /* 0xda */ -/* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * For: add-int/lit8, rsub-int/lit8 - * and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - movzbq 2(rPC), %rax # rax <- BB - movsbl 3(rPC), %ecx # rcx <- ssssssCC - GET_VREG %eax, %rax # eax <- rBB - imull %ecx, %eax # ex: addl %ecx,%eax - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_div_int_lit8: /* 0xdb */ -/* - * 32-bit div/rem "lit8" binary operation. Handles special case of - * op0=minint & op1=-1 - */ - /* div/rem/lit8 vAA, vBB, #+CC */ - movzbq 2(rPC), %rax # eax <- BB - movsbl 3(rPC), %ecx # ecx <- ssssssCC - GET_VREG %eax, %rax # eax <- rBB - testl %ecx, %ecx - je common_errDivideByZero - cmpl $-1, %ecx - je 2f - cdq # rax <- sign-extended of eax - idivl %ecx -1: - SET_VREG %eax, rINSTq # vA <- result - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 -2: - .if 0 - xorl %eax, %eax - .else - negl %eax - .endif - jmp 1b - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int_lit8: /* 0xdc */ -/* - * 32-bit div/rem "lit8" binary operation. Handles special case of - * op0=minint & op1=-1 - */ - /* div/rem/lit8 vAA, vBB, #+CC */ - movzbq 2(rPC), %rax # eax <- BB - movsbl 3(rPC), %ecx # ecx <- ssssssCC - GET_VREG %eax, %rax # eax <- rBB - testl %ecx, %ecx - je common_errDivideByZero - cmpl $-1, %ecx - je 2f - cdq # rax <- sign-extended of eax - idivl %ecx -1: - SET_VREG %edx, rINSTq # vA <- result - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 -2: - .if 1 - xorl %edx, %edx - .else - negl %edx - .endif - jmp 1b - -/* ------------------------------ */ - .balign 128 -.L_op_and_int_lit8: /* 0xdd */ -/* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * For: add-int/lit8, rsub-int/lit8 - * and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - movzbq 2(rPC), %rax # rax <- BB - movsbl 3(rPC), %ecx # rcx <- ssssssCC - GET_VREG %eax, %rax # eax <- rBB - andl %ecx, %eax # ex: addl %ecx,%eax - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_or_int_lit8: /* 0xde */ -/* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * For: add-int/lit8, rsub-int/lit8 - * and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - movzbq 2(rPC), %rax # rax <- BB - movsbl 3(rPC), %ecx # rcx <- ssssssCC - GET_VREG %eax, %rax # eax <- rBB - orl %ecx, %eax # ex: addl %ecx,%eax - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int_lit8: /* 0xdf */ -/* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * For: add-int/lit8, rsub-int/lit8 - * and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - movzbq 2(rPC), %rax # rax <- BB - movsbl 3(rPC), %ecx # rcx <- ssssssCC - GET_VREG %eax, %rax # eax <- rBB - xorl %ecx, %eax # ex: addl %ecx,%eax - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_shl_int_lit8: /* 0xe0 */ -/* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * For: add-int/lit8, rsub-int/lit8 - * and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - movzbq 2(rPC), %rax # rax <- BB - movsbl 3(rPC), %ecx # rcx <- ssssssCC - GET_VREG %eax, %rax # eax <- rBB - sall %cl, %eax # ex: addl %ecx,%eax - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_shr_int_lit8: /* 0xe1 */ -/* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * For: add-int/lit8, rsub-int/lit8 - * and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - movzbq 2(rPC), %rax # rax <- BB - movsbl 3(rPC), %ecx # rcx <- ssssssCC - GET_VREG %eax, %rax # eax <- rBB - sarl %cl, %eax # ex: addl %ecx,%eax - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_int_lit8: /* 0xe2 */ -/* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * For: add-int/lit8, rsub-int/lit8 - * and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - movzbq 2(rPC), %rax # rax <- BB - movsbl 3(rPC), %ecx # rcx <- ssssssCC - GET_VREG %eax, %rax # eax <- rBB - shrl %cl, %eax # ex: addl %ecx,%eax - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iget_quick: /* 0xe3 */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick, iget-wide-quick */ - /* op vA, vB, offset@CCCC */ - movl rINST, %ecx # rcx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %rcx # vB (object we're operating on) - movzwq 2(rPC), %rax # eax <- field byte offset - testl %ecx, %ecx # is object null? - je common_errNullObject - andb $0xf,rINSTbl # rINST <- A - .if 0 - movq (%rcx,%rax,1), %rax - SET_WIDE_VREG %rax, rINSTq # fp[A] <- value - .else - movl (%rcx,%rax,1), %eax - SET_VREG %eax, rINSTq # fp[A] <- value - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iget_wide_quick: /* 0xe4 */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick, iget-wide-quick */ - /* op vA, vB, offset@CCCC */ - movl rINST, %ecx # rcx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %rcx # vB (object we're operating on) - movzwq 2(rPC), %rax # eax <- field byte offset - testl %ecx, %ecx # is object null? - je common_errNullObject - andb $0xf,rINSTbl # rINST <- A - .if 1 - movq (%rcx,%rax,1), %rax - SET_WIDE_VREG %rax, rINSTq # fp[A] <- value - .else - movswl (%rcx,%rax,1), %eax - SET_VREG %eax, rINSTq # fp[A] <- value - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iget_object_quick: /* 0xe5 */ - /* For: iget-object-quick */ - /* op vA, vB, offset@CCCC */ - .extern artIGetObjectFromMterp - movzbq rINSTbl, %rcx # rcx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG OUT_32_ARG0, %rcx # vB (object we're operating on) - movzwl 2(rPC), OUT_32_ARG1 # eax <- field byte offset - EXPORT_PC - callq SYMBOL(artIGetObjectFromMterp) # (obj, offset) - movq rSELF, %rcx - cmpq $0, THREAD_EXCEPTION_OFFSET(%rcx) - jnz MterpException # bail out - andb $0xf, rINSTbl # rINST <- A - SET_VREG_OBJECT %eax, rINSTq # fp[A] <- value - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iput_quick: /* 0xe6 */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - movzbq rINSTbl, %rcx # rcx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %rcx # vB (object we're operating on) - testl %ecx, %ecx # is object null? - je common_errNullObject - andb $0xf, rINSTbl # rINST <- A - GET_VREG rINST, rINSTq # rINST <- v[A] - movzwq 2(rPC), %rax # rax <- field byte offset - movl rINST, (%rcx,%rax,1) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iput_wide_quick: /* 0xe7 */ - /* iput-wide-quick vA, vB, offset@CCCC */ - movzbq rINSTbl, %rcx # rcx<- BA - sarl $4, %ecx # ecx<- B - GET_VREG %ecx, %rcx # vB (object we're operating on) - testl %ecx, %ecx # is object null? - je common_errNullObject - movzwq 2(rPC), %rax # rax<- field byte offset - leaq (%rcx,%rax,1), %rcx # ecx<- Address of 64-bit target - andb $0xf, rINSTbl # rINST<- A - GET_WIDE_VREG %rax, rINSTq # rax<- fp[A]/fp[A+1] - movq %rax, (%rcx) # obj.field<- r0/r1 - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iput_object_quick: /* 0xe8 */ - EXPORT_PC - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG0 - movq rPC, OUT_ARG1 - REFRESH_INST 232 - movl rINST, OUT_32_ARG2 - call SYMBOL(MterpIputObjectQuick) - testb %al, %al - jz MterpException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual_quick: /* 0xe9 */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtualQuick - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - REFRESH_INST 233 - movl rINST, OUT_32_ARG3 - call SYMBOL(MterpInvokeVirtualQuick) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - FETCH_INST - GOTO_NEXT - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual_range_quick: /* 0xea */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtualQuickRange - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - REFRESH_INST 234 - movl rINST, OUT_32_ARG3 - call SYMBOL(MterpInvokeVirtualQuickRange) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - FETCH_INST - GOTO_NEXT - -/* ------------------------------ */ - .balign 128 -.L_op_iput_boolean_quick: /* 0xeb */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - movzbq rINSTbl, %rcx # rcx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %rcx # vB (object we're operating on) - testl %ecx, %ecx # is object null? - je common_errNullObject - andb $0xf, rINSTbl # rINST <- A - GET_VREG rINST, rINSTq # rINST <- v[A] - movzwq 2(rPC), %rax # rax <- field byte offset - movb rINSTbl, (%rcx,%rax,1) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iput_byte_quick: /* 0xec */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - movzbq rINSTbl, %rcx # rcx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %rcx # vB (object we're operating on) - testl %ecx, %ecx # is object null? - je common_errNullObject - andb $0xf, rINSTbl # rINST <- A - GET_VREG rINST, rINSTq # rINST <- v[A] - movzwq 2(rPC), %rax # rax <- field byte offset - movb rINSTbl, (%rcx,%rax,1) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iput_char_quick: /* 0xed */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - movzbq rINSTbl, %rcx # rcx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %rcx # vB (object we're operating on) - testl %ecx, %ecx # is object null? - je common_errNullObject - andb $0xf, rINSTbl # rINST <- A - GET_VREG rINST, rINSTq # rINST <- v[A] - movzwq 2(rPC), %rax # rax <- field byte offset - movw rINSTw, (%rcx,%rax,1) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iput_short_quick: /* 0xee */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - movzbq rINSTbl, %rcx # rcx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %rcx # vB (object we're operating on) - testl %ecx, %ecx # is object null? - je common_errNullObject - andb $0xf, rINSTbl # rINST <- A - GET_VREG rINST, rINSTq # rINST <- v[A] - movzwq 2(rPC), %rax # rax <- field byte offset - movw rINSTw, (%rcx,%rax,1) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iget_boolean_quick: /* 0xef */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick, iget-wide-quick */ - /* op vA, vB, offset@CCCC */ - movl rINST, %ecx # rcx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %rcx # vB (object we're operating on) - movzwq 2(rPC), %rax # eax <- field byte offset - testl %ecx, %ecx # is object null? - je common_errNullObject - andb $0xf,rINSTbl # rINST <- A - .if 0 - movq (%rcx,%rax,1), %rax - SET_WIDE_VREG %rax, rINSTq # fp[A] <- value - .else - movsbl (%rcx,%rax,1), %eax - SET_VREG %eax, rINSTq # fp[A] <- value - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iget_byte_quick: /* 0xf0 */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick, iget-wide-quick */ - /* op vA, vB, offset@CCCC */ - movl rINST, %ecx # rcx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %rcx # vB (object we're operating on) - movzwq 2(rPC), %rax # eax <- field byte offset - testl %ecx, %ecx # is object null? - je common_errNullObject - andb $0xf,rINSTbl # rINST <- A - .if 0 - movq (%rcx,%rax,1), %rax - SET_WIDE_VREG %rax, rINSTq # fp[A] <- value - .else - movsbl (%rcx,%rax,1), %eax - SET_VREG %eax, rINSTq # fp[A] <- value - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iget_char_quick: /* 0xf1 */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick, iget-wide-quick */ - /* op vA, vB, offset@CCCC */ - movl rINST, %ecx # rcx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %rcx # vB (object we're operating on) - movzwq 2(rPC), %rax # eax <- field byte offset - testl %ecx, %ecx # is object null? - je common_errNullObject - andb $0xf,rINSTbl # rINST <- A - .if 0 - movq (%rcx,%rax,1), %rax - SET_WIDE_VREG %rax, rINSTq # fp[A] <- value - .else - movzwl (%rcx,%rax,1), %eax - SET_VREG %eax, rINSTq # fp[A] <- value - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iget_short_quick: /* 0xf2 */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick, iget-wide-quick */ - /* op vA, vB, offset@CCCC */ - movl rINST, %ecx # rcx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %rcx # vB (object we're operating on) - movzwq 2(rPC), %rax # eax <- field byte offset - testl %ecx, %ecx # is object null? - je common_errNullObject - andb $0xf,rINSTbl # rINST <- A - .if 0 - movq (%rcx,%rax,1), %rax - SET_WIDE_VREG %rax, rINSTq # fp[A] <- value - .else - movswl (%rcx,%rax,1), %eax - SET_VREG %eax, rINSTq # fp[A] <- value - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f3: /* 0xf3 */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f4: /* 0xf4 */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f5: /* 0xf5 */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f6: /* 0xf6 */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f7: /* 0xf7 */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f8: /* 0xf8 */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f9: /* 0xf9 */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_polymorphic: /* 0xfa */ - /* - * invoke-polymorphic handler wrapper. - */ - /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ - .extern MterpInvokePolymorphic - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - REFRESH_INST 250 - movl rINST, OUT_32_ARG3 - call SYMBOL(MterpInvokePolymorphic) - testb %al, %al - jz MterpException - ADVANCE_PC 4 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - FETCH_INST - GOTO_NEXT - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_polymorphic_range: /* 0xfb */ - /* - * invoke-polymorphic handler wrapper. - */ - /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ - .extern MterpInvokePolymorphicRange - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - REFRESH_INST 251 - movl rINST, OUT_32_ARG3 - call SYMBOL(MterpInvokePolymorphicRange) - testb %al, %al - jz MterpException - ADVANCE_PC 4 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - FETCH_INST - GOTO_NEXT - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_custom: /* 0xfc */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeCustom - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - REFRESH_INST 252 - movl rINST, OUT_32_ARG3 - call SYMBOL(MterpInvokeCustom) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - FETCH_INST - GOTO_NEXT - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_custom_range: /* 0xfd */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeCustomRange - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - REFRESH_INST 253 - movl rINST, OUT_32_ARG3 - call SYMBOL(MterpInvokeCustomRange) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - FETCH_INST - GOTO_NEXT - -/* ------------------------------ */ - .balign 128 -.L_op_const_method_handle: /* 0xfe */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstMethodHandle - EXPORT_PC - movzwq 2(rPC), OUT_ARG0 # eax <- OUT_ARG0 - movq rINSTq, OUT_ARG1 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 - movq rSELF, OUT_ARG3 - call SYMBOL(MterpConstMethodHandle) # (index, tgt_reg, shadow_frame, self) - testb %al, %al - jnz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_const_method_type: /* 0xff */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstMethodType - EXPORT_PC - movzwq 2(rPC), OUT_ARG0 # eax <- OUT_ARG0 - movq rINSTq, OUT_ARG1 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 - movq rSELF, OUT_ARG3 - call SYMBOL(MterpConstMethodType) # (index, tgt_reg, shadow_frame, self) - testb %al, %al - jnz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - .balign 128 - - OBJECT_TYPE(artMterpAsmInstructionEnd) - ASM_HIDDEN SYMBOL(artMterpAsmInstructionEnd) - .global SYMBOL(artMterpAsmInstructionEnd) -SYMBOL(artMterpAsmInstructionEnd): - - OBJECT_TYPE(artMterpAsmAltInstructionStart) - ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionStart) - .global SYMBOL(artMterpAsmAltInstructionStart) - .text -SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop -/* ------------------------------ */ - .balign 128 -.L_ALT_op_nop: /* 0x00 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(0*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move: /* 0x01 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(1*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_from16: /* 0x02 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(2*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_16: /* 0x03 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(3*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_wide: /* 0x04 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(4*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_wide_from16: /* 0x05 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(5*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_wide_16: /* 0x06 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(6*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_object: /* 0x07 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(7*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_object_from16: /* 0x08 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(8*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_object_16: /* 0x09 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(9*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_result: /* 0x0a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(10*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_result_wide: /* 0x0b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(11*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_result_object: /* 0x0c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(12*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_exception: /* 0x0d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(13*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_void: /* 0x0e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(14*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return: /* 0x0f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(15*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_wide: /* 0x10 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(16*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_object: /* 0x11 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(17*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_4: /* 0x12 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(18*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_16: /* 0x13 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(19*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const: /* 0x14 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(20*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_high16: /* 0x15 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(21*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide_16: /* 0x16 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(22*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide_32: /* 0x17 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(23*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide: /* 0x18 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(24*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide_high16: /* 0x19 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(25*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_string: /* 0x1a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(26*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_string_jumbo: /* 0x1b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(27*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_class: /* 0x1c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(28*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_monitor_enter: /* 0x1d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(29*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_monitor_exit: /* 0x1e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(30*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_check_cast: /* 0x1f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(31*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_instance_of: /* 0x20 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(32*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_array_length: /* 0x21 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(33*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_new_instance: /* 0x22 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(34*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_new_array: /* 0x23 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(35*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_filled_new_array: /* 0x24 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(36*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_filled_new_array_range: /* 0x25 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(37*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_fill_array_data: /* 0x26 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(38*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_throw: /* 0x27 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(39*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_goto: /* 0x28 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(40*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_goto_16: /* 0x29 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(41*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_goto_32: /* 0x2a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(42*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_packed_switch: /* 0x2b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(43*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sparse_switch: /* 0x2c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(44*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpl_float: /* 0x2d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(45*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpg_float: /* 0x2e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(46*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpl_double: /* 0x2f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(47*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpg_double: /* 0x30 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(48*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmp_long: /* 0x31 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(49*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_eq: /* 0x32 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(50*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_ne: /* 0x33 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(51*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_lt: /* 0x34 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(52*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_ge: /* 0x35 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(53*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_gt: /* 0x36 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(54*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_le: /* 0x37 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(55*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_eqz: /* 0x38 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(56*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_nez: /* 0x39 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(57*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_ltz: /* 0x3a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(58*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_gez: /* 0x3b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(59*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_gtz: /* 0x3c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(60*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_lez: /* 0x3d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(61*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_3e: /* 0x3e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(62*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_3f: /* 0x3f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(63*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_40: /* 0x40 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(64*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_41: /* 0x41 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(65*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_42: /* 0x42 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(66*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_43: /* 0x43 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(67*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget: /* 0x44 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(68*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_wide: /* 0x45 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(69*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_object: /* 0x46 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(70*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_boolean: /* 0x47 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(71*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_byte: /* 0x48 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(72*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_char: /* 0x49 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(73*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_short: /* 0x4a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(74*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput: /* 0x4b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(75*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_wide: /* 0x4c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(76*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_object: /* 0x4d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(77*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_boolean: /* 0x4e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(78*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_byte: /* 0x4f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(79*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_char: /* 0x50 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(80*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_short: /* 0x51 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(81*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget: /* 0x52 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(82*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_wide: /* 0x53 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(83*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_object: /* 0x54 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(84*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_boolean: /* 0x55 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(85*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_byte: /* 0x56 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(86*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_char: /* 0x57 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(87*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_short: /* 0x58 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(88*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput: /* 0x59 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(89*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_wide: /* 0x5a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(90*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_object: /* 0x5b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(91*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_boolean: /* 0x5c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(92*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_byte: /* 0x5d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(93*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_char: /* 0x5e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(94*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_short: /* 0x5f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(95*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget: /* 0x60 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(96*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_wide: /* 0x61 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(97*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_object: /* 0x62 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(98*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_boolean: /* 0x63 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(99*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_byte: /* 0x64 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(100*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_char: /* 0x65 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(101*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_short: /* 0x66 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(102*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput: /* 0x67 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(103*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_wide: /* 0x68 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(104*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_object: /* 0x69 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(105*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_boolean: /* 0x6a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(106*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_byte: /* 0x6b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(107*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_char: /* 0x6c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(108*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_short: /* 0x6d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(109*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual: /* 0x6e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(110*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_super: /* 0x6f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(111*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_direct: /* 0x70 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(112*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_static: /* 0x71 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(113*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_interface: /* 0x72 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(114*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_void_no_barrier: /* 0x73 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(115*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual_range: /* 0x74 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(116*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_super_range: /* 0x75 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(117*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_direct_range: /* 0x76 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(118*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_static_range: /* 0x77 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(119*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_interface_range: /* 0x78 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(120*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_79: /* 0x79 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(121*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_7a: /* 0x7a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(122*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_int: /* 0x7b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(123*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_not_int: /* 0x7c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(124*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_long: /* 0x7d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(125*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_not_long: /* 0x7e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(126*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_float: /* 0x7f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(127*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_double: /* 0x80 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(128*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_long: /* 0x81 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(129*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_float: /* 0x82 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(130*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_double: /* 0x83 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(131*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_long_to_int: /* 0x84 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(132*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_long_to_float: /* 0x85 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(133*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_long_to_double: /* 0x86 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(134*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_float_to_int: /* 0x87 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(135*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_float_to_long: /* 0x88 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(136*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_float_to_double: /* 0x89 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(137*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_double_to_int: /* 0x8a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(138*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_double_to_long: /* 0x8b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(139*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_double_to_float: /* 0x8c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(140*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_byte: /* 0x8d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(141*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_char: /* 0x8e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(142*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_short: /* 0x8f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(143*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int: /* 0x90 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(144*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_int: /* 0x91 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(145*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int: /* 0x92 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(146*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int: /* 0x93 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(147*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int: /* 0x94 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(148*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int: /* 0x95 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(149*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int: /* 0x96 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(150*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int: /* 0x97 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(151*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_int: /* 0x98 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(152*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_int: /* 0x99 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(153*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_int: /* 0x9a */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(154*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_long: /* 0x9b */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(155*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_long: /* 0x9c */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(156*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_long: /* 0x9d */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(157*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_long: /* 0x9e */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(158*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_long: /* 0x9f */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(159*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_long: /* 0xa0 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(160*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_long: /* 0xa1 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(161*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_long: /* 0xa2 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(162*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_long: /* 0xa3 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(163*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_long: /* 0xa4 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(164*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_long: /* 0xa5 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(165*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_float: /* 0xa6 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(166*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_float: /* 0xa7 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(167*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_float: /* 0xa8 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(168*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_float: /* 0xa9 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(169*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_float: /* 0xaa */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(170*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_double: /* 0xab */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(171*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_double: /* 0xac */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(172*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_double: /* 0xad */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(173*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_double: /* 0xae */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(174*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_double: /* 0xaf */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(175*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int_2addr: /* 0xb0 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(176*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_int_2addr: /* 0xb1 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(177*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int_2addr: /* 0xb2 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(178*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int_2addr: /* 0xb3 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(179*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int_2addr: /* 0xb4 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(180*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int_2addr: /* 0xb5 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(181*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int_2addr: /* 0xb6 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(182*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int_2addr: /* 0xb7 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(183*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_int_2addr: /* 0xb8 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(184*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_int_2addr: /* 0xb9 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(185*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_int_2addr: /* 0xba */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(186*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_long_2addr: /* 0xbb */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(187*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_long_2addr: /* 0xbc */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(188*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_long_2addr: /* 0xbd */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(189*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_long_2addr: /* 0xbe */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(190*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_long_2addr: /* 0xbf */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(191*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_long_2addr: /* 0xc0 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(192*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_long_2addr: /* 0xc1 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(193*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_long_2addr: /* 0xc2 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(194*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_long_2addr: /* 0xc3 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(195*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_long_2addr: /* 0xc4 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(196*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_long_2addr: /* 0xc5 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(197*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_float_2addr: /* 0xc6 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(198*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_float_2addr: /* 0xc7 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(199*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_float_2addr: /* 0xc8 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(200*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_float_2addr: /* 0xc9 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(201*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_float_2addr: /* 0xca */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(202*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_double_2addr: /* 0xcb */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(203*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_double_2addr: /* 0xcc */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(204*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_double_2addr: /* 0xcd */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(205*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_double_2addr: /* 0xce */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(206*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_double_2addr: /* 0xcf */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(207*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int_lit16: /* 0xd0 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(208*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rsub_int: /* 0xd1 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(209*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int_lit16: /* 0xd2 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(210*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int_lit16: /* 0xd3 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(211*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int_lit16: /* 0xd4 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(212*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int_lit16: /* 0xd5 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(213*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int_lit16: /* 0xd6 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(214*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int_lit16: /* 0xd7 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(215*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int_lit8: /* 0xd8 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(216*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rsub_int_lit8: /* 0xd9 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(217*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int_lit8: /* 0xda */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(218*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int_lit8: /* 0xdb */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(219*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int_lit8: /* 0xdc */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(220*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int_lit8: /* 0xdd */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(221*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int_lit8: /* 0xde */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(222*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int_lit8: /* 0xdf */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(223*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_int_lit8: /* 0xe0 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(224*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_int_lit8: /* 0xe1 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(225*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_int_lit8: /* 0xe2 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(226*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_quick: /* 0xe3 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(227*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_wide_quick: /* 0xe4 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(228*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_object_quick: /* 0xe5 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(229*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_quick: /* 0xe6 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(230*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_wide_quick: /* 0xe7 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(231*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_object_quick: /* 0xe8 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(232*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual_quick: /* 0xe9 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(233*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual_range_quick: /* 0xea */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(234*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_boolean_quick: /* 0xeb */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(235*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_byte_quick: /* 0xec */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(236*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_char_quick: /* 0xed */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(237*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_short_quick: /* 0xee */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(238*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_boolean_quick: /* 0xef */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(239*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_byte_quick: /* 0xf0 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(240*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_char_quick: /* 0xf1 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(241*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_short_quick: /* 0xf2 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(242*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f3: /* 0xf3 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(243*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f4: /* 0xf4 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(244*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f5: /* 0xf5 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(245*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f6: /* 0xf6 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(246*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f7: /* 0xf7 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(247*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f8: /* 0xf8 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(248*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f9: /* 0xf9 */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(249*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_polymorphic: /* 0xfa */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(250*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_polymorphic_range: /* 0xfb */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(251*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_custom: /* 0xfc */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(252*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_custom_range: /* 0xfd */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(253*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_method_handle: /* 0xfe */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(254*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_method_type: /* 0xff */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(255*128) - - .balign 128 - - OBJECT_TYPE(artMterpAsmAltInstructionEnd) - ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionEnd) - .global SYMBOL(artMterpAsmAltInstructionEnd) -SYMBOL(artMterpAsmAltInstructionEnd): - -/* - * =========================================================================== - * Common subroutines and data - * =========================================================================== - */ - - .text - .align 2 - -/* - * We've detected a condition that will result in an exception, but the exception - * has not yet been thrown. Just bail out to the reference interpreter to deal with it. - * TUNING: for consistency, we may want to just go ahead and handle these here. - */ -common_errDivideByZero: - EXPORT_PC -#if MTERP_LOGGING - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - call SYMBOL(MterpLogDivideByZeroException) -#endif - jmp MterpCommonFallback - -common_errArrayIndex: - EXPORT_PC -#if MTERP_LOGGING - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - call SYMBOL(MterpLogArrayIndexException) -#endif - jmp MterpCommonFallback - -common_errNegativeArraySize: - EXPORT_PC -#if MTERP_LOGGING - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - call SYMBOL(MterpLogNegativeArraySizeException) -#endif - jmp MterpCommonFallback - -common_errNoSuchMethod: - EXPORT_PC -#if MTERP_LOGGING - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - call SYMBOL(MterpLogNoSuchMethodException) -#endif - jmp MterpCommonFallback - -common_errNullObject: - EXPORT_PC -#if MTERP_LOGGING - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - call SYMBOL(MterpLogNullObjectException) -#endif - jmp MterpCommonFallback - -common_exceptionThrown: - EXPORT_PC -#if MTERP_LOGGING - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - call SYMBOL(MterpLogExceptionThrownException) -#endif - jmp MterpCommonFallback - -MterpSuspendFallback: - EXPORT_PC -#if MTERP_LOGGING - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movl THREAD_FLAGS_OFFSET(OUT_ARG0), OUT_32_ARG2 - call SYMBOL(MterpLogSuspendFallback) -#endif - jmp MterpCommonFallback - -/* - * If we're here, something is out of the ordinary. If there is a pending - * exception, handle it. Otherwise, roll back and retry with the reference - * interpreter. - */ -MterpPossibleException: - movq rSELF, %rcx - cmpq $0, THREAD_EXCEPTION_OFFSET(%rcx) - jz MterpFallback - /* intentional fallthrough - handle pending exception. */ - -/* - * On return from a runtime helper routine, we've found a pending exception. - * Can we handle it here - or need to bail out to caller? - * - */ -MterpException: - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - call SYMBOL(MterpHandleException) - testb %al, %al - jz MterpExceptionReturn - movq OFF_FP_DEX_INSTRUCTIONS(rFP), %rax - mov OFF_FP_DEX_PC(rFP), %ecx - leaq (%rax, %rcx, 2), rPC - movq rPC, OFF_FP_DEX_PC_PTR(rFP) - /* Do we need to switch interpreters? */ - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - /* resume execution at catch block */ - REFRESH_IBASE - FETCH_INST - GOTO_NEXT - /* NOTE: no fallthrough */ - -/* - * Common handling for branches with support for Jit profiling. - * On entry: - * rINST <= signed offset - * rPROFILE <= signed hotness countdown (expanded to 32 bits) - * condition bits <= set to establish sign of offset (use "NoFlags" entry if not) - * - * We have quite a few different cases for branch profiling, OSR detection and - * suspend check support here. - * - * Taken backward branches: - * If profiling active, do hotness countdown and report if we hit zero. - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * Is there a pending suspend request? If so, suspend. - * - * Taken forward branches and not-taken backward branches: - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * - * Our most common case is expected to be a taken backward branch with active jit profiling, - * but no full OSR check and no pending suspend request. - * Next most common case is not-taken branch with no full OSR check. - * - */ -MterpCommonTakenBranch: - jg .L_forward_branch # don't add forward branches to hotness -/* - * We need to subtract 1 from positive values and we should not see 0 here, - * so we may use the result of the comparison with -1. - */ -#if JIT_CHECK_OSR != -1 -# error "JIT_CHECK_OSR must be -1." -#endif - cmpl $JIT_CHECK_OSR, rPROFILE - je .L_osr_check - decl rPROFILE - je .L_add_batch # counted down to zero - report -.L_resume_backward_branch: - movq rSELF, %rax - testl $(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(%rax) - REFRESH_IBASE_REG %rax - leaq (rPC, rINSTq, 2), rPC - FETCH_INST - jnz .L_suspend_request_pending - GOTO_NEXT - -.L_suspend_request_pending: - EXPORT_PC - movq rSELF, OUT_ARG0 - call SYMBOL(MterpSuspendCheck) # (self) - testb %al, %al - jnz MterpFallback - REFRESH_IBASE # might have changed during suspend - GOTO_NEXT - -.L_no_count_backwards: - cmpl $JIT_CHECK_OSR, rPROFILE # possible OSR re-entry? - jne .L_resume_backward_branch -.L_osr_check: - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rINSTq, OUT_ARG2 - call SYMBOL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) - testb %al, %al - jz .L_resume_backward_branch - jmp MterpOnStackReplacement - -.L_forward_branch: - cmpl $JIT_CHECK_OSR, rPROFILE # possible OSR re-entry? - je .L_check_osr_forward -.L_resume_forward_branch: - leaq (rPC, rINSTq, 2), rPC - FETCH_INST - GOTO_NEXT - -.L_check_osr_forward: - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rINSTq, OUT_ARG2 - call SYMBOL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) - testb %al, %al - jz .L_resume_forward_branch - jmp MterpOnStackReplacement - -.L_add_batch: - movl rPROFILE, %eax - movq OFF_FP_METHOD(rFP), OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movw %ax, OFF_FP_COUNTDOWN_OFFSET(rFP) - movq rSELF, OUT_ARG2 - call SYMBOL(MterpAddHotnessBatch) # (method, shadow_frame, self) - movswl %ax, rPROFILE - jmp .L_no_count_backwards - -/* - * Entered from the conditional branch handlers when OSR check request active on - * not-taken path. All Dalvik not-taken conditional branch offsets are 2. - */ -.L_check_not_taken_osr: - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movl $2, OUT_32_ARG2 - call SYMBOL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) - testb %al, %al - jnz MterpOnStackReplacement - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* - * On-stack replacement has happened, and now we've returned from the compiled method. - */ -MterpOnStackReplacement: -#if MTERP_LOGGING - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movl rINST, OUT_32_ARG2 - call SYMBOL(MterpLogOSR) -#endif - movl $1, %eax - jmp MterpDone - -/* - * Bail out to reference interpreter. - */ -MterpFallback: - EXPORT_PC -#if MTERP_LOGGING - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - call SYMBOL(MterpLogFallback) -#endif -MterpCommonFallback: - xorl %eax, %eax - jmp MterpDone - -/* - * On entry: - * uint32_t* rFP (should still be live, pointer to base of vregs) - */ -MterpExceptionReturn: - movl $1, %eax - jmp MterpDone -MterpReturn: - movq OFF_FP_RESULT_REGISTER(rFP), %rdx - movq %rax, (%rdx) - movl $1, %eax -MterpDone: -/* - * At this point, we expect rPROFILE to be non-zero. If negative, hotness is disabled or we're - * checking for OSR. If greater than zero, we might have unreported hotness to register - * (the difference between the ending rPROFILE and the cached hotness counter). rPROFILE - * should only reach zero immediately after a hotness decrement, and is then reset to either - * a negative special state or the new non-zero countdown value. - */ - testl rPROFILE, rPROFILE - jle MRestoreFrame # if > 0, we may have some counts to report. - - movl %eax, rINST # stash return value - /* Report cached hotness counts */ - movl rPROFILE, %eax - movq OFF_FP_METHOD(rFP), OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movw %ax, OFF_FP_COUNTDOWN_OFFSET(rFP) - movq rSELF, OUT_ARG2 - call SYMBOL(MterpAddHotnessBatch) # (method, shadow_frame, self) - movl rINST, %eax # restore return value - - /* pop up frame */ -MRestoreFrame: - addq $FRAME_SIZE, %rsp - .cfi_adjust_cfa_offset -FRAME_SIZE - - /* Restore callee save register */ - POP %r15 - POP %r14 - POP %r13 - POP %r12 - POP %rbp - POP %rbx - ret - .cfi_endproc - SIZE(ExecuteMterpImpl,ExecuteMterpImpl) - -- GitLab