diff --git a/runtime/Android.bp b/runtime/Android.bp index 1cebb065705bc1013612df58333ce792d9d4ed24..15ccb70df056da643a09cdc86648269c29a83afd 100644 --- a/runtime/Android.bp +++ b/runtime/Android.bp @@ -246,7 +246,7 @@ libart_cc_defaults { arm: { srcs: [ "interpreter/mterp/mterp.cc", - "interpreter/mterp/out/mterp_arm.S", + ":libart_mterp.arm", "arch/arm/context_arm.cc", "arch/arm/entrypoints_init_arm.cc", "arch/arm/instruction_set_features_assembly_tests.S", @@ -261,7 +261,7 @@ libart_cc_defaults { arm64: { srcs: [ "interpreter/mterp/mterp.cc", - "interpreter/mterp/out/mterp_arm64.S", + ":libart_mterp.arm64", "arch/arm64/context_arm64.cc", "arch/arm64/entrypoints_init_arm64.cc", "arch/arm64/jni_entrypoints_arm64.S", @@ -275,7 +275,7 @@ libart_cc_defaults { x86: { srcs: [ "interpreter/mterp/mterp.cc", - "interpreter/mterp/out/mterp_x86.S", + ":libart_mterp.x86", "arch/x86/context_x86.cc", "arch/x86/entrypoints_init_x86.cc", "arch/x86/jni_entrypoints_x86.S", @@ -290,7 +290,7 @@ libart_cc_defaults { // Note that the fault_handler_x86.cc is not a mistake. This file is // shared between the x86 and x86_64 architectures. "interpreter/mterp/mterp.cc", - "interpreter/mterp/out/mterp_x86_64.S", + ":libart_mterp.x86_64", "arch/x86_64/context_x86_64.cc", "arch/x86_64/entrypoints_init_x86_64.cc", "arch/x86_64/jni_entrypoints_x86_64.S", @@ -304,7 +304,7 @@ libart_cc_defaults { mips: { srcs: [ "interpreter/mterp/mterp.cc", - "interpreter/mterp/out/mterp_mips.S", + ":libart_mterp.mips", "arch/mips/context_mips.cc", "arch/mips/entrypoints_init_mips.cc", "arch/mips/jni_entrypoints_mips.S", @@ -317,7 +317,7 @@ libart_cc_defaults { mips64: { srcs: [ "interpreter/mterp/mterp.cc", - "interpreter/mterp/out/mterp_mips64.S", + ":libart_mterp.mips64", "arch/mips64/context_mips64.cc", "arch/mips64/entrypoints_init_mips64.cc", "arch/mips64/jni_entrypoints_mips64.S", @@ -669,3 +669,51 @@ cc_library_headers { host_supported: true, export_include_dirs: ["."], } + +genrule { + name: "libart_mterp.arm", + out: ["mterp_arm.S"], + srcs: ["interpreter/mterp/arm/*.S"], + tool_files: ["interpreter/mterp/gen_mterp.py", "interpreter/mterp/common/gen_setup.py"], + cmd: "$(location interpreter/mterp/gen_mterp.py) $(out) $(in)", +} + +genrule { + name: "libart_mterp.arm64", + out: ["mterp_arm64.S"], + srcs: ["interpreter/mterp/arm64/*.S"], + tool_files: ["interpreter/mterp/gen_mterp.py", "interpreter/mterp/common/gen_setup.py"], + cmd: "$(location interpreter/mterp/gen_mterp.py) $(out) $(in)", +} + +genrule { + name: "libart_mterp.mips", + out: ["mterp_mips.S"], + srcs: ["interpreter/mterp/mips/*.S"], + tool_files: ["interpreter/mterp/gen_mterp.py", "interpreter/mterp/common/gen_setup.py"], + cmd: "$(location interpreter/mterp/gen_mterp.py) $(out) $(in)", +} + +genrule { + name: "libart_mterp.mips64", + out: ["mterp_mips64.S"], + srcs: ["interpreter/mterp/mips64/*.S"], + tool_files: ["interpreter/mterp/gen_mterp.py", "interpreter/mterp/common/gen_setup.py"], + cmd: "$(location interpreter/mterp/gen_mterp.py) $(out) $(in)", +} + +genrule { + name: "libart_mterp.x86", + out: ["mterp_x86.S"], + srcs: ["interpreter/mterp/x86/*.S"], + tool_files: ["interpreter/mterp/gen_mterp.py", "interpreter/mterp/common/gen_setup.py"], + cmd: "$(location interpreter/mterp/gen_mterp.py) $(out) $(in)", +} + +genrule { + name: "libart_mterp.x86_64", + out: ["mterp_x86_64.S"], + srcs: ["interpreter/mterp/x86_64/*.S"], + tool_files: ["interpreter/mterp/gen_mterp.py", "interpreter/mterp/common/gen_setup.py"], + cmd: "$(location interpreter/mterp/gen_mterp.py) $(out) $(in)", +} diff --git a/runtime/interpreter/mterp/Makefile_mterp b/runtime/interpreter/mterp/Makefile_mterp deleted file mode 100644 index ac8da69742d03b6f4ef59e4322d35d0d40b7e4c8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/Makefile_mterp +++ /dev/null @@ -1,49 +0,0 @@ -# Copyright (C) 2016 The Android Open Source Project -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -# -# Makefile for the Art fast interpreter. This is not currently -# integrated into the build system. -# - -SHELL := /bin/sh - -# Build system has TARGET_ARCH=arm, but we can support the exact architecture -# if it is worthwhile. -# -# To generate sources: -# for arch in arm arm64 x86 x86_64 mips mips64 -# do -# TARGET_ARCH_EXT=$arch make -f Makefile_mterp -# done -# - -OUTPUT_DIR := out - -# Accumulate all possible dependencies for the generated files in a very -# conservative fashion. If it's not one of the generated files in "out", -# assume it's a dependency. -SOURCE_DEPS := \ - $(shell find . -path ./$(OUTPUT_DIR) -prune -o -type f -print) \ - -# Source files generated by the script. There's always one C and one -# assembly file, though in practice one or the other could be empty. -GEN_SOURCES := \ - $(OUTPUT_DIR)/interp_asm_$(TARGET_ARCH_EXT).S - -target: $(GEN_SOURCES) - -$(GEN_SOURCES): $(SOURCE_DEPS) - @mkdir -p out - ./gen_mterp.py $(TARGET_ARCH_EXT) $(OUTPUT_DIR) diff --git a/runtime/interpreter/mterp/README.txt b/runtime/interpreter/mterp/README.txt index 19e02bec5010c1676d393520850b40c007cec9ad..54bb634cb59ebb2f373792103cd130c886b216e3 100644 --- a/runtime/interpreter/mterp/README.txt +++ b/runtime/interpreter/mterp/README.txt @@ -1,108 +1,29 @@ -rt "mterp" README - -NOTE: Find rebuilding instructions at the bottom of this file. - - ==== Overview ==== -Every configuration has a "config-*" file that controls how the sources -are generated. The sources are written into the "out" directory, where +The assembly source code is produced from custom python-based templates. +All the architecture-specific template files are concatenated to create +one big python script. This generated python script is then executed to +produced the final assembly file. The template syntax is: + * Lines starting with % are python code. They will be copied as-is to + the script (without the %) and thus executed during the generation. + * Other lines are text, and they are essentially syntax sugar for + out.write('''(line text)''') and thus they write the main output. + * Within a text line, $ can be used insert variables from code. + +The final assembly sources are written into the "out" directory, where they are picked up by the Android build system. The best way to become familiar with the interpreter is to look at the generated files in the "out" directory. -==== Config file format ==== - -The config files are parsed from top to bottom. Each line in the file -may be blank, hold a comment (line starts with '#'), or be a command. - -The commands are: - - handler-style - - Specify which style of interpreter to generate. In computed-goto, - each handler is allocated a fixed region, allowing transitions to - be done via table-start-address + (opcode * handler-size). With - jump-table style, handlers may be of any length, and the generated - table is an array of pointers to the handlers. This command is required, - and must be the first command in the config file. - - handler-size - - Specify the size of the fixed region, in bytes. On most platforms - this will need to be a power of 2. For jump-table implementations, - this command is ignored. - - import - - The specified file is included immediately, in its entirety. No - substitutions are performed. ".cpp" and ".h" files are copied to the - C output, ".S" files are copied to the asm output. - - asm-alt-stub - - When present, this command will cause the generation of an alternate - set of entry points (for computed-goto interpreters) or an alternate - jump table (for jump-table interpreters). - - fallback-stub - - Specifies a file to be used for the special FALLBACK tag on the "op" - command below. Intended to be used to transfer control to an alternate - interpreter to single-step a not-yet-implemented opcode. Note: should - note be used on RETURN-class instructions. - - op-start - - Indicates the start of the opcode list. Must precede any "op" - commands. The specified directory is the default location to pull - instruction files from. - - op |FALLBACK - - Can only appear after "op-start" and before "op-end". Overrides the - default source file location of the specified opcode. The opcode - definition will come from the specified file, e.g. "op OP_NOP arm" - will load from "arm/OP_NOP.S". A substitution dictionary will be - applied (see below). If the special "FALLBACK" token is used instead of - a directory name, the source file specified in fallback-stub will instead - be used for this opcode. - - alt - - Can only appear after "op-start" and before "op-end". Similar to the - "op" command above, but denotes a source file to override the entry - in the alternate handler table. The opcode definition will come from - the specified file, e.g. "alt OP_NOP arm" will load from - "arm/ALT_OP_NOP.S". A substitution dictionary will be applied - (see below). - - op-end - - Indicates the end of the opcode list. All kNumPackedOpcodes - opcodes are emitted when this is seen, followed by any code that - didn't fit inside the fixed-size instruction handler space. - -The order of "op" and "alt" directives are not significant; the generation -tool will extract ordering info from the VM sources. - -Typically the form in which most opcodes currently exist is used in -the "op-start" directive. - ==== Instruction file format ==== The assembly instruction files are simply fragments of assembly sources. The starting label will be provided by the generation tool, as will -declarations for the segment type and alignment. The expected target -assembler is GNU "as", but others will work (may require fiddling with -some of the pseudo-ops emitted by the generation tool). - -A substitution dictionary is applied to all opcode fragments as they are -appended to the output. Substitutions can look like "$value" or "${value}". +declarations for the segment type and alignment. -The dictionary always includes: +The following global variables are generally available: $opcode - opcode name, e.g. "OP_NOP" $opnum - opcode number, e.g. 0 for OP_NOP @@ -113,29 +34,6 @@ Both C and assembly sources will be passed through the C pre-processor, so you can take advantage of C-style comments and preprocessor directives like "#define". -Some generator operations are available. - - %include "filename" [subst-dict] - - Includes the file, which should look like "arm/OP_NOP.S". You can - specify values for the substitution dictionary, using standard Python - syntax. For example, this: - %include "arm/unop.S" {"result":"r1"} - would insert "arm/unop.S" at the current file position, replacing - occurrences of "$result" with "r1". - - %default - - Specify default substitution dictionary values, using standard Python - syntax. Useful if you want to have a "base" version and variants. - - %break - - Identifies the split between the main portion of the instruction - handler (which must fit in "handler-size" bytes) and the "sister" - code, which is appended to the end of the instruction handler block. - In jump table implementations, %break is ignored. - The generation tool does *not* print a warning if your instructions exceed "handler-size", but the VM will abort on startup if it detects an oversized handler. On architectures with fixed-width instructions this @@ -153,20 +51,6 @@ If a constant in the file becomes out of sync, the VM will log an error message and abort during startup. -==== Development tips ==== - -If you need to debug the initial piece of an opcode handler, and your -debug code expands it beyond the handler size limit, you can insert a -generic header at the top: - - b ${opcode}_start -%break -${opcode}_start: - -If you already have a %break, it's okay to leave it in place -- the second -%break is ignored. - - ==== Rebuilding ==== If you change any of the source file fragments, you need to rebuild the @@ -174,7 +58,7 @@ combined source files in the "out" directory. Make sure the files in "out" are editable, then: $ cd mterp - $ ./rebuild.sh + $ ./gen_mterp.py The ultimate goal is to have the build system generate the necessary output files without requiring this separate step, but we're not yet diff --git a/runtime/interpreter/mterp/arm/alt_stub.S b/runtime/interpreter/mterp/arm/alt_stub.S deleted file mode 100644 index 8799d9520c60c1c51c22b3f3db39acee190061f0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/alt_stub.S +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_${opcode} - sub lr, lr, #(.L_ALT_${opcode} - .L_${opcode}) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. diff --git a/runtime/interpreter/mterp/arm/arithmetic.S b/runtime/interpreter/mterp/arm/arithmetic.S new file mode 100644 index 0000000000000000000000000000000000000000..6413b63627663d1ff373331a788e64ed25a70245 --- /dev/null +++ b/runtime/interpreter/mterp/arm/arithmetic.S @@ -0,0 +1,975 @@ +%def binop(preinstr="", result="r0", chkzero="0", instr=""): + /* + * Generic 32-bit binary operation. Provide an "instr" line that + * specifies an instruction that performs "result = r0 op r1". + * This could be an ARM instruction or a function call. (If the result + * comes back in a register other than r0, you can override "result".) + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vCC (r1). Useful for integer division and modulus. Note that we + * *don't* check for (INT_MIN / -1) here, because the ARM math lib + * handles it correctly. + * + * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, + * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, + * mul-float, div-float, rem-float + */ + /* binop vAA, vBB, vCC */ + FETCH r0, 1 @ r0<- CCBB + mov r9, rINST, lsr #8 @ r9<- AA + mov r3, r0, lsr #8 @ r3<- CC + and r2, r0, #255 @ r2<- BB + GET_VREG r1, r3 @ r1<- vCC + GET_VREG r0, r2 @ r0<- vBB + .if $chkzero + cmp r1, #0 @ is second operand zero? + beq common_errDivideByZero + .endif + + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + $preinstr @ optional op; may set condition codes + $instr @ $result<- op, r0-r3 changed + GET_INST_OPCODE ip @ extract opcode from rINST + SET_VREG $result, r9 @ vAA<- $result + GOTO_OPCODE ip @ jump to next instruction + /* 11-14 instructions */ + +%def binop2addr(preinstr="", result="r0", chkzero="0", instr=""): + /* + * Generic 32-bit "/2addr" binary operation. Provide an "instr" line + * that specifies an instruction that performs "result = r0 op r1". + * This could be an ARM instruction or a function call. (If the result + * comes back in a register other than r0, you can override "result".) + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vCC (r1). Useful for integer division and modulus. + * + * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, + * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, + * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, + * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr + */ + /* binop/2addr vA, vB */ + mov r3, rINST, lsr #12 @ r3<- B + ubfx r9, rINST, #8, #4 @ r9<- A + GET_VREG r1, r3 @ r1<- vB + GET_VREG r0, r9 @ r0<- vA + .if $chkzero + cmp r1, #0 @ is second operand zero? + beq common_errDivideByZero + .endif + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + + $preinstr @ optional op; may set condition codes + $instr @ $result<- op, r0-r3 changed + GET_INST_OPCODE ip @ extract opcode from rINST + SET_VREG $result, r9 @ vAA<- $result + GOTO_OPCODE ip @ jump to next instruction + /* 10-13 instructions */ + +%def binopLit16(result="r0", chkzero="0", instr=""): + /* + * Generic 32-bit "lit16" binary operation. Provide an "instr" line + * that specifies an instruction that performs "result = r0 op r1". + * This could be an ARM instruction or a function call. (If the result + * comes back in a register other than r0, you can override "result".) + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vCC (r1). Useful for integer division and modulus. + * + * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, + * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 + */ + /* binop/lit16 vA, vB, #+CCCC */ + FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) + mov r2, rINST, lsr #12 @ r2<- B + ubfx r9, rINST, #8, #4 @ r9<- A + GET_VREG r0, r2 @ r0<- vB + .if $chkzero + cmp r1, #0 @ is second operand zero? + beq common_errDivideByZero + .endif + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + + $instr @ $result<- op, r0-r3 changed + GET_INST_OPCODE ip @ extract opcode from rINST + SET_VREG $result, r9 @ vAA<- $result + GOTO_OPCODE ip @ jump to next instruction + /* 10-13 instructions */ + +%def binopLit8(extract="asr r1, r3, #8", result="r0", chkzero="0", instr=""): + /* + * Generic 32-bit "lit8" binary operation. Provide an "instr" line + * that specifies an instruction that performs "result = r0 op r1". + * This could be an ARM instruction or a function call. (If the result + * comes back in a register other than r0, you can override "result".) + * + * You can override "extract" if the extraction of the literal value + * from r3 to r1 is not the default "asr r1, r3, #8". The extraction + * can be omitted completely if the shift is embedded in "instr". + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vCC (r1). Useful for integer division and modulus. + * + * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, + * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, + * shl-int/lit8, shr-int/lit8, ushr-int/lit8 + */ + /* binop/lit8 vAA, vBB, #+CC */ + FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) + mov r9, rINST, lsr #8 @ r9<- AA + and r2, r3, #255 @ r2<- BB + GET_VREG r0, r2 @ r0<- vBB + $extract @ optional; typically r1<- ssssssCC (sign extended) + .if $chkzero + @cmp r1, #0 @ is second operand zero? + beq common_errDivideByZero + .endif + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + + $instr @ $result<- op, r0-r3 changed + GET_INST_OPCODE ip @ extract opcode from rINST + SET_VREG $result, r9 @ vAA<- $result + GOTO_OPCODE ip @ jump to next instruction + /* 10-12 instructions */ + +%def binopWide(preinstr="", result0="r0", result1="r1", chkzero="0", instr=""): + /* + * Generic 64-bit binary operation. Provide an "instr" line that + * specifies an instruction that performs "result = r0-r1 op r2-r3". + * This could be an ARM instruction or a function call. (If the result + * comes back in a register other than r0, you can override "result".) + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vCC (r1). Useful for integer division and modulus. + * + * for: add-long, sub-long, div-long, rem-long, and-long, or-long, + * xor-long, add-double, sub-double, mul-double, div-double, + * rem-double + * + * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. + */ + /* binop vAA, vBB, vCC */ + FETCH r0, 1 @ r0<- CCBB + mov rINST, rINST, lsr #8 @ rINST<- AA + and r2, r0, #255 @ r2<- BB + mov r3, r0, lsr #8 @ r3<- CC + VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[AA] + VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] + ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 + ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 + .if $chkzero + orrs ip, r2, r3 @ second arg (r2-r3) is zero? + beq common_errDivideByZero + .endif + CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + $preinstr @ optional op; may set condition codes + $instr @ result<- op, r0-r3 changed + GET_INST_OPCODE ip @ extract opcode from rINST + stmia r9, {$result0,$result1} @ vAA/vAA+1<- $result0/$result1 + GOTO_OPCODE ip @ jump to next instruction + /* 14-17 instructions */ + +%def binopWide2addr(preinstr="", result0="r0", result1="r1", chkzero="0", instr=""): + /* + * Generic 64-bit "/2addr" binary operation. Provide an "instr" line + * that specifies an instruction that performs "result = r0-r1 op r2-r3". + * This could be an ARM instruction or a function call. (If the result + * comes back in a register other than r0, you can override "result".) + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vCC (r1). Useful for integer division and modulus. + * + * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, + * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, + * sub-double/2addr, mul-double/2addr, div-double/2addr, + * rem-double/2addr + */ + /* binop/2addr vA, vB */ + mov r1, rINST, lsr #12 @ r1<- B + ubfx rINST, rINST, #8, #4 @ rINST<- A + VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] + VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] + ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 + ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 + .if $chkzero + orrs ip, r2, r3 @ second arg (r2-r3) is zero? + beq common_errDivideByZero + .endif + CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + $preinstr @ optional op; may set condition codes + $instr @ result<- op, r0-r3 changed + GET_INST_OPCODE ip @ extract opcode from rINST + stmia r9, {$result0,$result1} @ vAA/vAA+1<- $result0/$result1 + GOTO_OPCODE ip @ jump to next instruction + /* 12-15 instructions */ + +%def unop(preinstr="", instr=""): + /* + * Generic 32-bit unary operation. Provide an "instr" line that + * specifies an instruction that performs "result = op r0". + * This could be an ARM instruction or a function call. + * + * for: neg-int, not-int, neg-float, int-to-float, float-to-int, + * int-to-byte, int-to-char, int-to-short + */ + /* unop vA, vB */ + mov r3, rINST, lsr #12 @ r3<- B + ubfx r9, rINST, #8, #4 @ r9<- A + GET_VREG r0, r3 @ r0<- vB + $preinstr @ optional op; may set condition codes + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + $instr @ r0<- op, r0-r3 changed + GET_INST_OPCODE ip @ extract opcode from rINST + SET_VREG r0, r9 @ vAA<- r0 + GOTO_OPCODE ip @ jump to next instruction + /* 8-9 instructions */ + +%def unopNarrower(preinstr="", instr=""): + /* + * Generic 64bit-to-32bit unary operation. Provide an "instr" line + * that specifies an instruction that performs "result = op r0/r1", where + * "result" is a 32-bit quantity in r0. + * + * For: long-to-float, double-to-int, double-to-float + * + * (This would work for long-to-int, but that instruction is actually + * an exact match for op_move.) + */ + /* unop vA, vB */ + mov r3, rINST, lsr #12 @ r3<- B + ubfx r9, rINST, #8, #4 @ r9<- A + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] + ldmia r3, {r0-r1} @ r0/r1<- vB/vB+1 + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + $preinstr @ optional op; may set condition codes + $instr @ r0<- op, r0-r3 changed + GET_INST_OPCODE ip @ extract opcode from rINST + SET_VREG r0, r9 @ vA<- r0 + GOTO_OPCODE ip @ jump to next instruction + /* 9-10 instructions */ + +%def unopWide(preinstr="", instr=""): + /* + * Generic 64-bit unary operation. Provide an "instr" line that + * specifies an instruction that performs "result = op r0/r1". + * This could be an ARM instruction or a function call. + * + * For: neg-long, not-long, neg-double, long-to-double, double-to-long + */ + /* unop vA, vB */ + mov r3, rINST, lsr #12 @ r3<- B + ubfx rINST, rINST, #8, #4 @ rINST<- A + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] + VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] + ldmia r3, {r0-r1} @ r0/r1<- vAA + CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + $preinstr @ optional op; may set condition codes + $instr @ r0/r1<- op, r2-r3 changed + GET_INST_OPCODE ip @ extract opcode from rINST + stmia r9, {r0-r1} @ vAA<- r0/r1 + GOTO_OPCODE ip @ jump to next instruction + /* 10-11 instructions */ + +%def unopWider(preinstr="", instr=""): + /* + * Generic 32bit-to-64bit unary operation. Provide an "instr" line + * that specifies an instruction that performs "result = op r0", where + * "result" is a 64-bit quantity in r0/r1. + * + * For: int-to-long, int-to-double, float-to-long, float-to-double + */ + /* unop vA, vB */ + mov r3, rINST, lsr #12 @ r3<- B + ubfx rINST, rINST, #8, #4 @ rINST<- A + GET_VREG r0, r3 @ r0<- vB + VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] + $preinstr @ optional op; may set condition codes + CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + $instr @ r0<- op, r0-r3 changed + GET_INST_OPCODE ip @ extract opcode from rINST + stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 + GOTO_OPCODE ip @ jump to next instruction + /* 9-10 instructions */ + +%def op_add_int(): +% binop(instr="add r0, r0, r1") + +%def op_add_int_2addr(): +% binop2addr(instr="add r0, r0, r1") + +%def op_add_int_lit16(): +% binopLit16(instr="add r0, r0, r1") + +%def op_add_int_lit8(): +% binopLit8(extract="", instr="add r0, r0, r3, asr #8") + +%def op_add_long(): +% binopWide(preinstr="adds r0, r0, r2", instr="adc r1, r1, r3") + +%def op_add_long_2addr(): +% binopWide2addr(preinstr="adds r0, r0, r2", instr="adc r1, r1, r3") + +%def op_and_int(): +% binop(instr="and r0, r0, r1") + +%def op_and_int_2addr(): +% binop2addr(instr="and r0, r0, r1") + +%def op_and_int_lit16(): +% binopLit16(instr="and r0, r0, r1") + +%def op_and_int_lit8(): +% binopLit8(extract="", instr="and r0, r0, r3, asr #8") + +%def op_and_long(): +% binopWide(preinstr="and r0, r0, r2", instr="and r1, r1, r3") + +%def op_and_long_2addr(): +% binopWide2addr(preinstr="and r0, r0, r2", instr="and r1, r1, r3") + +%def op_cmp_long(): + /* + * Compare two 64-bit values. Puts 0, 1, or -1 into the destination + * register based on the results of the comparison. + */ + /* cmp-long vAA, vBB, vCC */ + FETCH r0, 1 @ r0<- CCBB + mov r9, rINST, lsr #8 @ r9<- AA + and r2, r0, #255 @ r2<- BB + mov r3, r0, lsr #8 @ r3<- CC + VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] + ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 + ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 + cmp r0, r2 + sbcs ip, r1, r3 @ Sets correct CCs for checking LT (but not EQ/NE) + mov ip, #0 + mvnlt ip, #0 @ -1 + cmpeq r0, r2 @ For correct EQ/NE, we may need to repeat the first CMP + orrne ip, #1 + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + SET_VREG ip, r9 @ vAA<- ip + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def op_div_int(): + /* + * Specialized 32-bit binary operation + * + * Performs "r0 = r0 div r1". The selection between sdiv or the gcc helper + * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for + * ARMv7 CPUs that have hardware division support). + * + * div-int + * + */ + FETCH r0, 1 @ r0<- CCBB + mov r9, rINST, lsr #8 @ r9<- AA + mov r3, r0, lsr #8 @ r3<- CC + and r2, r0, #255 @ r2<- BB + GET_VREG r1, r3 @ r1<- vCC + GET_VREG r0, r2 @ r0<- vBB + cmp r1, #0 @ is second operand zero? + beq common_errDivideByZero + + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST +#ifdef __ARM_ARCH_EXT_IDIV__ + sdiv r0, r0, r1 @ r0<- op +#else + bl __aeabi_idiv @ r0<- op, r0-r3 changed +#endif + GET_INST_OPCODE ip @ extract opcode from rINST + SET_VREG r0, r9 @ vAA<- r0 + GOTO_OPCODE ip @ jump to next instruction + /* 11-14 instructions */ + +%def op_div_int_2addr(): + /* + * Specialized 32-bit binary operation + * + * Performs "r0 = r0 div r1". The selection between sdiv or the gcc helper + * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for + * ARMv7 CPUs that have hardware division support). + * + * div-int/2addr + * + */ + mov r3, rINST, lsr #12 @ r3<- B + ubfx r9, rINST, #8, #4 @ r9<- A + GET_VREG r1, r3 @ r1<- vB + GET_VREG r0, r9 @ r0<- vA + cmp r1, #0 @ is second operand zero? + beq common_errDivideByZero + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + +#ifdef __ARM_ARCH_EXT_IDIV__ + sdiv r0, r0, r1 @ r0<- op +#else + bl __aeabi_idiv @ r0<- op, r0-r3 changed +#endif + GET_INST_OPCODE ip @ extract opcode from rINST + SET_VREG r0, r9 @ vAA<- r0 + GOTO_OPCODE ip @ jump to next instruction + /* 10-13 instructions */ + + +%def op_div_int_lit16(): + /* + * Specialized 32-bit binary operation + * + * Performs "r0 = r0 div r1". The selection between sdiv or the gcc helper + * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for + * ARMv7 CPUs that have hardware division support). + * + * div-int/lit16 + * + */ + FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) + mov r2, rINST, lsr #12 @ r2<- B + ubfx r9, rINST, #8, #4 @ r9<- A + GET_VREG r0, r2 @ r0<- vB + cmp r1, #0 @ is second operand zero? + beq common_errDivideByZero + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + +#ifdef __ARM_ARCH_EXT_IDIV__ + sdiv r0, r0, r1 @ r0<- op +#else + bl __aeabi_idiv @ r0<- op, r0-r3 changed +#endif + GET_INST_OPCODE ip @ extract opcode from rINST + SET_VREG r0, r9 @ vAA<- r0 + GOTO_OPCODE ip @ jump to next instruction + /* 10-13 instructions */ + +%def op_div_int_lit8(): + /* + * Specialized 32-bit binary operation + * + * Performs "r0 = r0 div r1". The selection between sdiv or the gcc helper + * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for + * ARMv7 CPUs that have hardware division support). + * + * div-int/lit8 + * + */ + FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC + mov r9, rINST, lsr #8 @ r9<- AA + and r2, r3, #255 @ r2<- BB + GET_VREG r0, r2 @ r0<- vBB + movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) + @cmp r1, #0 @ is second operand zero? + beq common_errDivideByZero + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + +#ifdef __ARM_ARCH_EXT_IDIV__ + sdiv r0, r0, r1 @ r0<- op +#else + bl __aeabi_idiv @ r0<- op, r0-r3 changed +#endif + GET_INST_OPCODE ip @ extract opcode from rINST + SET_VREG r0, r9 @ vAA<- r0 + GOTO_OPCODE ip @ jump to next instruction + /* 10-12 instructions */ + +%def op_div_long(): +% binopWide(instr="bl __aeabi_ldivmod", chkzero="1") + +%def op_div_long_2addr(): +% binopWide2addr(instr="bl __aeabi_ldivmod", chkzero="1") + +%def op_int_to_byte(): +% unop(instr="sxtb r0, r0") + +%def op_int_to_char(): +% unop(instr="uxth r0, r0") + +%def op_int_to_long(): +% unopWider(instr="mov r1, r0, asr #31") + +%def op_int_to_short(): +% unop(instr="sxth r0, r0") + +%def op_long_to_int(): +/* we ignore the high word, making this equivalent to a 32-bit reg move */ +% op_move() + +%def op_mul_int(): +/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ +% binop(instr="mul r0, r1, r0") + +%def op_mul_int_2addr(): +/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ +% binop2addr(instr="mul r0, r1, r0") + +%def op_mul_int_lit16(): +/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ +% binopLit16(instr="mul r0, r1, r0") + +%def op_mul_int_lit8(): +/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ +% binopLit8(instr="mul r0, r1, r0") + +%def op_mul_long(): + /* + * Signed 64-bit integer multiply. + * + * Consider WXxYZ (r1r0 x r3r2) with a long multiply: + * WX + * x YZ + * -------- + * ZW ZX + * YW YX + * + * The low word of the result holds ZX, the high word holds + * (ZW+YX) + (the high overflow from ZX). YW doesn't matter because + * it doesn't fit in the low 64 bits. + * + * Unlike most ARM math operations, multiply instructions have + * restrictions on using the same register more than once (Rd and Rm + * cannot be the same). + */ + /* mul-long vAA, vBB, vCC */ + FETCH r0, 1 @ r0<- CCBB + and r2, r0, #255 @ r2<- BB + mov r3, r0, lsr #8 @ r3<- CC + VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] + ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 + ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 + mul ip, r2, r1 @ ip<- ZxW + umull r1, lr, r2, r0 @ r1/lr <- ZxX + mla r2, r0, r3, ip @ r2<- YxX + (ZxW) + mov r0, rINST, lsr #8 @ r0<- AA + add r2, r2, lr @ r2<- lr + low(ZxW + (YxX)) + CLEAR_SHADOW_PAIR r0, lr, ip @ Zero out the shadow regs + VREG_INDEX_TO_ADDR r0, r0 @ r0<- &fp[AA] + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + GET_INST_OPCODE ip @ extract opcode from rINST + stmia r0, {r1-r2 } @ vAA/vAA+1<- r1/r2 + GOTO_OPCODE ip @ jump to next instruction + +%def op_mul_long_2addr(): + /* + * Signed 64-bit integer multiply, "/2addr" version. + * + * See op_mul_long for an explanation. + * + * We get a little tight on registers, so to avoid looking up &fp[A] + * again we stuff it into rINST. + */ + /* mul-long/2addr vA, vB */ + mov r1, rINST, lsr #12 @ r1<- B + ubfx r9, rINST, #8, #4 @ r9<- A + VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] + VREG_INDEX_TO_ADDR rINST, r9 @ rINST<- &fp[A] + ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 + ldmia rINST, {r0-r1} @ r0/r1<- vAA/vAA+1 + mul ip, r2, r1 @ ip<- ZxW + umull r1, lr, r2, r0 @ r1/lr <- ZxX + mla r2, r0, r3, ip @ r2<- YxX + (ZxW) + mov r0, rINST @ r0<- &fp[A] (free up rINST) + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + add r2, r2, lr @ r2<- r2 + low(ZxW + (YxX)) + GET_INST_OPCODE ip @ extract opcode from rINST + stmia r0, {r1-r2} @ vAA/vAA+1<- r1/r2 + GOTO_OPCODE ip @ jump to next instruction + +%def op_neg_int(): +% unop(instr="rsb r0, r0, #0") + +%def op_neg_long(): +% unopWide(preinstr="rsbs r0, r0, #0", instr="rsc r1, r1, #0") + +%def op_not_int(): +% unop(instr="mvn r0, r0") + +%def op_not_long(): +% unopWide(preinstr="mvn r0, r0", instr="mvn r1, r1") + +%def op_or_int(): +% binop(instr="orr r0, r0, r1") + +%def op_or_int_2addr(): +% binop2addr(instr="orr r0, r0, r1") + +%def op_or_int_lit16(): +% binopLit16(instr="orr r0, r0, r1") + +%def op_or_int_lit8(): +% binopLit8(extract="", instr="orr r0, r0, r3, asr #8") + +%def op_or_long(): +% binopWide(preinstr="orr r0, r0, r2", instr="orr r1, r1, r3") + +%def op_or_long_2addr(): +% binopWide2addr(preinstr="orr r0, r0, r2", instr="orr r1, r1, r3") + +%def op_rem_int(): + /* + * Specialized 32-bit binary operation + * + * Performs "r1 = r0 rem r1". The selection between sdiv block or the gcc helper + * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for + * ARMv7 CPUs that have hardware division support). + * + * NOTE: idivmod returns quotient in r0 and remainder in r1 + * + * rem-int + * + */ + FETCH r0, 1 @ r0<- CCBB + mov r9, rINST, lsr #8 @ r9<- AA + mov r3, r0, lsr #8 @ r3<- CC + and r2, r0, #255 @ r2<- BB + GET_VREG r1, r3 @ r1<- vCC + GET_VREG r0, r2 @ r0<- vBB + cmp r1, #0 @ is second operand zero? + beq common_errDivideByZero + + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST +#ifdef __ARM_ARCH_EXT_IDIV__ + sdiv r2, r0, r1 + mls r1, r1, r2, r0 @ r1<- op, r0-r2 changed +#else + bl __aeabi_idivmod @ r1<- op, r0-r3 changed +#endif + GET_INST_OPCODE ip @ extract opcode from rINST + SET_VREG r1, r9 @ vAA<- r1 + GOTO_OPCODE ip @ jump to next instruction + /* 11-14 instructions */ + +%def op_rem_int_2addr(): + /* + * Specialized 32-bit binary operation + * + * Performs "r1 = r0 rem r1". The selection between sdiv block or the gcc helper + * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for + * ARMv7 CPUs that have hardware division support). + * + * NOTE: idivmod returns quotient in r0 and remainder in r1 + * + * rem-int/2addr + * + */ + mov r3, rINST, lsr #12 @ r3<- B + ubfx r9, rINST, #8, #4 @ r9<- A + GET_VREG r1, r3 @ r1<- vB + GET_VREG r0, r9 @ r0<- vA + cmp r1, #0 @ is second operand zero? + beq common_errDivideByZero + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + +#ifdef __ARM_ARCH_EXT_IDIV__ + sdiv r2, r0, r1 + mls r1, r1, r2, r0 @ r1<- op +#else + bl __aeabi_idivmod @ r1<- op, r0-r3 changed +#endif + GET_INST_OPCODE ip @ extract opcode from rINST + SET_VREG r1, r9 @ vAA<- r1 + GOTO_OPCODE ip @ jump to next instruction + /* 10-13 instructions */ + + +%def op_rem_int_lit16(): + /* + * Specialized 32-bit binary operation + * + * Performs "r1 = r0 rem r1". The selection between sdiv block or the gcc helper + * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for + * ARMv7 CPUs that have hardware division support). + * + * NOTE: idivmod returns quotient in r0 and remainder in r1 + * + * rem-int/lit16 + * + */ + FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) + mov r2, rINST, lsr #12 @ r2<- B + ubfx r9, rINST, #8, #4 @ r9<- A + GET_VREG r0, r2 @ r0<- vB + cmp r1, #0 @ is second operand zero? + beq common_errDivideByZero + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + +#ifdef __ARM_ARCH_EXT_IDIV__ + sdiv r2, r0, r1 + mls r1, r1, r2, r0 @ r1<- op +#else + bl __aeabi_idivmod @ r1<- op, r0-r3 changed +#endif + GET_INST_OPCODE ip @ extract opcode from rINST + SET_VREG r1, r9 @ vAA<- r1 + GOTO_OPCODE ip @ jump to next instruction + /* 10-13 instructions */ + +%def op_rem_int_lit8(): + /* + * Specialized 32-bit binary operation + * + * Performs "r1 = r0 rem r1". The selection between sdiv block or the gcc helper + * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for + * ARMv7 CPUs that have hardware division support). + * + * NOTE: idivmod returns quotient in r0 and remainder in r1 + * + * rem-int/lit8 + * + */ + FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) + mov r9, rINST, lsr #8 @ r9<- AA + and r2, r3, #255 @ r2<- BB + GET_VREG r0, r2 @ r0<- vBB + movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) + @cmp r1, #0 @ is second operand zero? + beq common_errDivideByZero + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + +#ifdef __ARM_ARCH_EXT_IDIV__ + sdiv r2, r0, r1 + mls r1, r1, r2, r0 @ r1<- op +#else + bl __aeabi_idivmod @ r1<- op, r0-r3 changed +#endif + GET_INST_OPCODE ip @ extract opcode from rINST + SET_VREG r1, r9 @ vAA<- r1 + GOTO_OPCODE ip @ jump to next instruction + /* 10-12 instructions */ + +%def op_rem_long(): +/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ +% binopWide(instr="bl __aeabi_ldivmod", result0="r2", result1="r3", chkzero="1") + +%def op_rem_long_2addr(): +/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ +% binopWide2addr(instr="bl __aeabi_ldivmod", result0="r2", result1="r3", chkzero="1") + +%def op_rsub_int(): +/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ +% binopLit16(instr="rsb r0, r0, r1") + +%def op_rsub_int_lit8(): +% binopLit8(extract="", instr="rsb r0, r0, r3, asr #8") + +%def op_shl_int(): +% binop(preinstr="and r1, r1, #31", instr="mov r0, r0, asl r1") + +%def op_shl_int_2addr(): +% binop2addr(preinstr="and r1, r1, #31", instr="mov r0, r0, asl r1") + +%def op_shl_int_lit8(): +% binopLit8(extract="ubfx r1, r3, #8, #5", instr="mov r0, r0, asl r1") + +%def op_shl_long(): + /* + * Long integer shift. This is different from the generic 32/64-bit + * binary operations because vAA/vBB are 64-bit but vCC (the shift + * distance) is 32-bit. Also, Dalvik requires us to mask off the low + * 6 bits of the shift distance. + */ + /* shl-long vAA, vBB, vCC */ + FETCH r0, 1 @ r0<- CCBB + mov r9, rINST, lsr #8 @ r9<- AA + and r3, r0, #255 @ r3<- BB + mov r0, r0, lsr #8 @ r0<- CC + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[BB] + GET_VREG r2, r0 @ r2<- vCC + ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 + CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs + and r2, r2, #63 @ r2<- r2 & 0x3f + VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] + mov r1, r1, asl r2 @ r1<- r1 << r2 + rsb r3, r2, #32 @ r3<- 32 - r2 + orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) + subs ip, r2, #32 @ ip<- r2 - 32 + movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + mov r0, r0, asl r2 @ r0<- r0 << r2 + GET_INST_OPCODE ip @ extract opcode from rINST + stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 + GOTO_OPCODE ip @ jump to next instruction + +%def op_shl_long_2addr(): + /* + * Long integer shift, 2addr version. vA is 64-bit value/result, vB is + * 32-bit shift distance. + */ + /* shl-long/2addr vA, vB */ + mov r3, rINST, lsr #12 @ r3<- B + ubfx r9, rINST, #8, #4 @ r9<- A + GET_VREG r2, r3 @ r2<- vB + CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs + VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[A] + and r2, r2, #63 @ r2<- r2 & 0x3f + ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 + mov r1, r1, asl r2 @ r1<- r1 << r2 + rsb r3, r2, #32 @ r3<- 32 - r2 + orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) + subs ip, r2, #32 @ ip<- r2 - 32 + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) + mov r0, r0, asl r2 @ r0<- r0 << r2 + GET_INST_OPCODE ip @ extract opcode from rINST + stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 + GOTO_OPCODE ip @ jump to next instruction + +%def op_shr_int(): +% binop(preinstr="and r1, r1, #31", instr="mov r0, r0, asr r1") + +%def op_shr_int_2addr(): +% binop2addr(preinstr="and r1, r1, #31", instr="mov r0, r0, asr r1") + +%def op_shr_int_lit8(): +% binopLit8(extract="ubfx r1, r3, #8, #5", instr="mov r0, r0, asr r1") + +%def op_shr_long(): + /* + * Long integer shift. This is different from the generic 32/64-bit + * binary operations because vAA/vBB are 64-bit but vCC (the shift + * distance) is 32-bit. Also, Dalvik requires us to mask off the low + * 6 bits of the shift distance. + */ + /* shr-long vAA, vBB, vCC */ + FETCH r0, 1 @ r0<- CCBB + mov r9, rINST, lsr #8 @ r9<- AA + and r3, r0, #255 @ r3<- BB + mov r0, r0, lsr #8 @ r0<- CC + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[BB] + GET_VREG r2, r0 @ r2<- vCC + ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 + CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs + and r2, r2, #63 @ r0<- r0 & 0x3f + VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] + mov r0, r0, lsr r2 @ r0<- r2 >> r2 + rsb r3, r2, #32 @ r3<- 32 - r2 + orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) + subs ip, r2, #32 @ ip<- r2 - 32 + movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + mov r1, r1, asr r2 @ r1<- r1 >> r2 + GET_INST_OPCODE ip @ extract opcode from rINST + stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 + GOTO_OPCODE ip @ jump to next instruction + +%def op_shr_long_2addr(): + /* + * Long integer shift, 2addr version. vA is 64-bit value/result, vB is + * 32-bit shift distance. + */ + /* shr-long/2addr vA, vB */ + mov r3, rINST, lsr #12 @ r3<- B + ubfx r9, rINST, #8, #4 @ r9<- A + GET_VREG r2, r3 @ r2<- vB + CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs + VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[A] + and r2, r2, #63 @ r2<- r2 & 0x3f + ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 + mov r0, r0, lsr r2 @ r0<- r2 >> r2 + rsb r3, r2, #32 @ r3<- 32 - r2 + orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) + subs ip, r2, #32 @ ip<- r2 - 32 + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) + mov r1, r1, asr r2 @ r1<- r1 >> r2 + GET_INST_OPCODE ip @ extract opcode from rINST + stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 + GOTO_OPCODE ip @ jump to next instruction + +%def op_sub_int(): +% binop(instr="sub r0, r0, r1") + +%def op_sub_int_2addr(): +% binop2addr(instr="sub r0, r0, r1") + +%def op_sub_long(): +% binopWide(preinstr="subs r0, r0, r2", instr="sbc r1, r1, r3") + +%def op_sub_long_2addr(): +% binopWide2addr(preinstr="subs r0, r0, r2", instr="sbc r1, r1, r3") + +%def op_ushr_int(): +% binop(preinstr="and r1, r1, #31", instr="mov r0, r0, lsr r1") + +%def op_ushr_int_2addr(): +% binop2addr(preinstr="and r1, r1, #31", instr="mov r0, r0, lsr r1") + +%def op_ushr_int_lit8(): +% binopLit8(extract="ubfx r1, r3, #8, #5", instr="mov r0, r0, lsr r1") + +%def op_ushr_long(): + /* + * Long integer shift. This is different from the generic 32/64-bit + * binary operations because vAA/vBB are 64-bit but vCC (the shift + * distance) is 32-bit. Also, Dalvik requires us to mask off the low + * 6 bits of the shift distance. + */ + /* ushr-long vAA, vBB, vCC */ + FETCH r0, 1 @ r0<- CCBB + mov r9, rINST, lsr #8 @ r9<- AA + and r3, r0, #255 @ r3<- BB + mov r0, r0, lsr #8 @ r0<- CC + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[BB] + GET_VREG r2, r0 @ r2<- vCC + ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 + CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs + and r2, r2, #63 @ r0<- r0 & 0x3f + VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] + mov r0, r0, lsr r2 @ r0<- r2 >> r2 + rsb r3, r2, #32 @ r3<- 32 - r2 + orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) + subs ip, r2, #32 @ ip<- r2 - 32 + movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + mov r1, r1, lsr r2 @ r1<- r1 >>> r2 + GET_INST_OPCODE ip @ extract opcode from rINST + stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 + GOTO_OPCODE ip @ jump to next instruction + +%def op_ushr_long_2addr(): + /* + * Long integer shift, 2addr version. vA is 64-bit value/result, vB is + * 32-bit shift distance. + */ + /* ushr-long/2addr vA, vB */ + mov r3, rINST, lsr #12 @ r3<- B + ubfx r9, rINST, #8, #4 @ r9<- A + GET_VREG r2, r3 @ r2<- vB + CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs + VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[A] + and r2, r2, #63 @ r2<- r2 & 0x3f + ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 + mov r0, r0, lsr r2 @ r0<- r2 >> r2 + rsb r3, r2, #32 @ r3<- 32 - r2 + orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) + subs ip, r2, #32 @ ip<- r2 - 32 + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) + mov r1, r1, lsr r2 @ r1<- r1 >>> r2 + GET_INST_OPCODE ip @ extract opcode from rINST + stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 + GOTO_OPCODE ip @ jump to next instruction + +%def op_xor_int(): +% binop(instr="eor r0, r0, r1") + +%def op_xor_int_2addr(): +% binop2addr(instr="eor r0, r0, r1") + +%def op_xor_int_lit16(): +% binopLit16(instr="eor r0, r0, r1") + +%def op_xor_int_lit8(): +% binopLit8(extract="", instr="eor r0, r0, r3, asr #8") + +%def op_xor_long(): +% binopWide(preinstr="eor r0, r0, r2", instr="eor r1, r1, r3") + +%def op_xor_long_2addr(): +% binopWide2addr(preinstr="eor r0, r0, r2", instr="eor r1, r1, r3") diff --git a/runtime/interpreter/mterp/arm/array.S b/runtime/interpreter/mterp/arm/array.S new file mode 100644 index 0000000000000000000000000000000000000000..88d89c53a2f91c4b514c292fe5b9da129630f967 --- /dev/null +++ b/runtime/interpreter/mterp/arm/array.S @@ -0,0 +1,250 @@ +%def op_aget(load="ldr", shift="2", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"): + /* + * Array get, 32 bits or less. vAA <- vBB[vCC]. + * + * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 + * instructions. We use a pair of FETCH_Bs instead. + * + * for: aget, aget-boolean, aget-byte, aget-char, aget-short + * + * NOTE: assumes data offset for arrays is the same for all non-wide types. + * If this changes, specialize. + */ + /* op vAA, vBB, vCC */ + FETCH_B r2, 1, 0 @ r2<- BB + mov r9, rINST, lsr #8 @ r9<- AA + FETCH_B r3, 1, 1 @ r3<- CC + GET_VREG r0, r2 @ r0<- vBB (array object) + GET_VREG r1, r3 @ r1<- vCC (requested index) + cmp r0, #0 @ null array object? + beq common_errNullObject @ yes, bail + ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length + add r0, r0, r1, lsl #$shift @ r0<- arrayObj + index*width + cmp r1, r3 @ compare unsigned index, length + bcs common_errArrayIndex @ index >= length, bail + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + $load r2, [r0, #$data_offset] @ r2<- vBB[vCC] + GET_INST_OPCODE ip @ extract opcode from rINST + SET_VREG r2, r9 @ vAA<- r2 + GOTO_OPCODE ip @ jump to next instruction + +%def op_aget_boolean(): +% op_aget(load="ldrb", shift="0", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") + +%def op_aget_byte(): +% op_aget(load="ldrsb", shift="0", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") + +%def op_aget_char(): +% op_aget(load="ldrh", shift="1", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") + +%def op_aget_object(): + /* + * Array object get. vAA <- vBB[vCC]. + * + * for: aget-object + */ + /* op vAA, vBB, vCC */ + FETCH_B r2, 1, 0 @ r2<- BB + mov r9, rINST, lsr #8 @ r9<- AA + FETCH_B r3, 1, 1 @ r3<- CC + EXPORT_PC + GET_VREG r0, r2 @ r0<- vBB (array object) + GET_VREG r1, r3 @ r1<- vCC (requested index) + bl artAGetObjectFromMterp @ (array, index) + ldr r1, [rSELF, #THREAD_EXCEPTION_OFFSET] + PREFETCH_INST 2 + cmp r1, #0 + bne MterpException + SET_VREG_OBJECT r0, r9 + ADVANCE 2 + GET_INST_OPCODE ip + GOTO_OPCODE ip @ jump to next instruction + +%def op_aget_short(): +% op_aget(load="ldrsh", shift="1", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") + +%def op_aget_wide(): + /* + * Array get, 64 bits. vAA <- vBB[vCC]. + * + * Arrays of long/double are 64-bit aligned, so it's okay to use LDRD. + */ + /* aget-wide vAA, vBB, vCC */ + FETCH r0, 1 @ r0<- CCBB + mov r9, rINST, lsr #8 @ r9<- AA + and r2, r0, #255 @ r2<- BB + mov r3, r0, lsr #8 @ r3<- CC + GET_VREG r0, r2 @ r0<- vBB (array object) + GET_VREG r1, r3 @ r1<- vCC (requested index) + cmp r0, #0 @ null array object? + beq common_errNullObject @ yes, bail + ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length + add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width + cmp r1, r3 @ compare unsigned index, length + bcs common_errArrayIndex @ index >= length, bail + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs + ldrd r2, [r0, #MIRROR_WIDE_ARRAY_DATA_OFFSET] @ r2/r3<- vBB[vCC] + VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] + GET_INST_OPCODE ip @ extract opcode from rINST + stmia r9, {r2-r3} @ vAA/vAA+1<- r2/r3 + GOTO_OPCODE ip @ jump to next instruction + +%def op_aput(store="str", shift="2", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"): + /* + * Array put, 32 bits or less. vBB[vCC] <- vAA. + * + * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 + * instructions. We use a pair of FETCH_Bs instead. + * + * for: aput, aput-boolean, aput-byte, aput-char, aput-short + * + * NOTE: this assumes data offset for arrays is the same for all non-wide types. + * If this changes, specialize. + */ + /* op vAA, vBB, vCC */ + FETCH_B r2, 1, 0 @ r2<- BB + mov r9, rINST, lsr #8 @ r9<- AA + FETCH_B r3, 1, 1 @ r3<- CC + GET_VREG r0, r2 @ r0<- vBB (array object) + GET_VREG r1, r3 @ r1<- vCC (requested index) + cmp r0, #0 @ null array object? + beq common_errNullObject @ yes, bail + ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length + add r0, r0, r1, lsl #$shift @ r0<- arrayObj + index*width + cmp r1, r3 @ compare unsigned index, length + bcs common_errArrayIndex @ index >= length, bail + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + GET_VREG r2, r9 @ r2<- vAA + GET_INST_OPCODE ip @ extract opcode from rINST + $store r2, [r0, #$data_offset] @ vBB[vCC]<- r2 + GOTO_OPCODE ip @ jump to next instruction + +%def op_aput_boolean(): +% op_aput(store="strb", shift="0", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") + +%def op_aput_byte(): +% op_aput(store="strb", shift="0", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") + +%def op_aput_char(): +% op_aput(store="strh", shift="1", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") + +%def op_aput_object(): + /* + * Store an object into an array. vBB[vCC] <- vAA. + */ + /* op vAA, vBB, vCC */ + EXPORT_PC + add r0, rFP, #OFF_FP_SHADOWFRAME + mov r1, rPC + mov r2, rINST + bl MterpAputObject + cmp r0, #0 + beq MterpPossibleException + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def op_aput_short(): +% op_aput(store="strh", shift="1", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") + +%def op_aput_wide(): + /* + * Array put, 64 bits. vBB[vCC] <- vAA. + * + * Arrays of long/double are 64-bit aligned, so it's okay to use STRD. + */ + /* aput-wide vAA, vBB, vCC */ + FETCH r0, 1 @ r0<- CCBB + mov r9, rINST, lsr #8 @ r9<- AA + and r2, r0, #255 @ r2<- BB + mov r3, r0, lsr #8 @ r3<- CC + GET_VREG r0, r2 @ r0<- vBB (array object) + GET_VREG r1, r3 @ r1<- vCC (requested index) + cmp r0, #0 @ null array object? + beq common_errNullObject @ yes, bail + ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length + add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width + cmp r1, r3 @ compare unsigned index, length + VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] + bcs common_errArrayIndex @ index >= length, bail + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + ldmia r9, {r2-r3} @ r2/r3<- vAA/vAA+1 + GET_INST_OPCODE ip @ extract opcode from rINST + strd r2, [r0, #MIRROR_WIDE_ARRAY_DATA_OFFSET] @ r2/r3<- vBB[vCC] + GOTO_OPCODE ip @ jump to next instruction + +%def op_array_length(): + /* + * Return the length of an array. + */ + mov r1, rINST, lsr #12 @ r1<- B + ubfx r2, rINST, #8, #4 @ r2<- A + GET_VREG r0, r1 @ r0<- vB (object ref) + cmp r0, #0 @ is object null? + beq common_errNullObject @ yup, fail + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- array length + GET_INST_OPCODE ip @ extract opcode from rINST + SET_VREG r3, r2 @ vB<- length + GOTO_OPCODE ip @ jump to next instruction + +%def op_fill_array_data(): + /* fill-array-data vAA, +BBBBBBBB */ + EXPORT_PC + FETCH r0, 1 @ r0<- bbbb (lo) + FETCH r1, 2 @ r1<- BBBB (hi) + mov r3, rINST, lsr #8 @ r3<- AA + orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb + GET_VREG r0, r3 @ r0<- vAA (array object) + add r1, rPC, r1, lsl #1 @ r1<- PC + BBBBbbbb*2 (array data off.) + bl MterpFillArrayData @ (obj, payload) + cmp r0, #0 @ 0 means an exception is thrown + beq MterpPossibleException @ exception? + FETCH_ADVANCE_INST 3 @ advance rPC, load rINST + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def op_filled_new_array(helper="MterpFilledNewArray"): + /* + * Create a new array with elements filled from registers. + * + * for: filled-new-array, filled-new-array/range + */ + /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ + /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ + .extern $helper + EXPORT_PC + add r0, rFP, #OFF_FP_SHADOWFRAME + mov r1, rPC + mov r2, rSELF + bl $helper + cmp r0, #0 + beq MterpPossibleException + FETCH_ADVANCE_INST 3 @ advance rPC, load rINST + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def op_filled_new_array_range(): +% op_filled_new_array(helper="MterpFilledNewArrayRange") + +%def op_new_array(): + /* + * Allocate an array of objects, specified with the array class + * and a count. + * + * The verifier guarantees that this is an array class, so we don't + * check for it here. + */ + /* new-array vA, vB, class@CCCC */ + EXPORT_PC + add r0, rFP, #OFF_FP_SHADOWFRAME + mov r1, rPC + mov r2, rINST + mov r3, rSELF + bl MterpNewArray + cmp r0, #0 + beq MterpPossibleException + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/bincmp.S b/runtime/interpreter/mterp/arm/bincmp.S deleted file mode 100644 index 8fad42f0d239f3df111c820d33616d8c7a987f75..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/bincmp.S +++ /dev/null @@ -1,19 +0,0 @@ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - mov r1, rINST, lsr #12 @ r1<- B - ubfx r0, rINST, #8, #4 @ r0<- A - GET_VREG r3, r1 @ r3<- vB - GET_VREG r0, r0 @ r0<- vA - FETCH_S rINST, 1 @ rINST<- branch offset, in code units - cmp r0, r3 @ compare (vA, vB) - b${condition} MterpCommonTakenBranchNoFlags - cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? - beq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/binop.S b/runtime/interpreter/mterp/arm/binop.S deleted file mode 100644 index eeb72ef65b44caa6cd39f3a524a1e54f6988c0fc..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/binop.S +++ /dev/null @@ -1,35 +0,0 @@ -%default {"preinstr":"", "result":"r0", "chkzero":"0"} - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - GET_VREG r1, r3 @ r1<- vCC - GET_VREG r0, r2 @ r0<- vBB - .if $chkzero - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - $preinstr @ optional op; may set condition codes - $instr @ $result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG $result, r9 @ vAA<- $result - GOTO_OPCODE ip @ jump to next instruction - /* 11-14 instructions */ diff --git a/runtime/interpreter/mterp/arm/binop2addr.S b/runtime/interpreter/mterp/arm/binop2addr.S deleted file mode 100644 index d09a43ae48ee6c9edaee16c2fcc8c76c740f79a1..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/binop2addr.S +++ /dev/null @@ -1,32 +0,0 @@ -%default {"preinstr":"", "result":"r0", "chkzero":"0"} - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r1, r3 @ r1<- vB - GET_VREG r0, r9 @ r0<- vA - .if $chkzero - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - - $preinstr @ optional op; may set condition codes - $instr @ $result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG $result, r9 @ vAA<- $result - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ diff --git a/runtime/interpreter/mterp/arm/binopLit16.S b/runtime/interpreter/mterp/arm/binopLit16.S deleted file mode 100644 index 065394e4ef2738d86028db15fefb7afa635c3049..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/binopLit16.S +++ /dev/null @@ -1,29 +0,0 @@ -%default {"result":"r0", "chkzero":"0"} - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) - mov r2, rINST, lsr #12 @ r2<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r0, r2 @ r0<- vB - .if $chkzero - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - - $instr @ $result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG $result, r9 @ vAA<- $result - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ diff --git a/runtime/interpreter/mterp/arm/binopLit8.S b/runtime/interpreter/mterp/arm/binopLit8.S deleted file mode 100644 index 7c9c6312cded9e89ca1a2f59f9d73f6306be60e7..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/binopLit8.S +++ /dev/null @@ -1,35 +0,0 @@ -%default {"extract":"asr r1, r3, #8", "result":"r0", "chkzero":"0"} - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from r3 to r1 is not the default "asr r1, r3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r3, #255 @ r2<- BB - GET_VREG r0, r2 @ r0<- vBB - $extract @ optional; typically r1<- ssssssCC (sign extended) - .if $chkzero - @cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - - $instr @ $result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG $result, r9 @ vAA<- $result - GOTO_OPCODE ip @ jump to next instruction - /* 10-12 instructions */ diff --git a/runtime/interpreter/mterp/arm/binopWide.S b/runtime/interpreter/mterp/arm/binopWide.S deleted file mode 100644 index 4d880015c87127ff23b45d469c654250cab4cb03..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/binopWide.S +++ /dev/null @@ -1,38 +0,0 @@ -%default {"preinstr":"", "result0":"r0", "result1":"r1", "chkzero":"0"} - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = r0-r1 op r2-r3". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * for: add-long, sub-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, - * rem-double - * - * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. - */ - /* binop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov rINST, rINST, lsr #8 @ rINST<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[AA] - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] - ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 - ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 - .if $chkzero - orrs ip, r2, r3 @ second arg (r2-r3) is zero? - beq common_errDivideByZero - .endif - CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - $preinstr @ optional op; may set condition codes - $instr @ result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {$result0,$result1} @ vAA/vAA+1<- $result0/$result1 - GOTO_OPCODE ip @ jump to next instruction - /* 14-17 instructions */ diff --git a/runtime/interpreter/mterp/arm/binopWide2addr.S b/runtime/interpreter/mterp/arm/binopWide2addr.S deleted file mode 100644 index bb16335c343ff9fcb3dab99f53ea3794b1a7cec4..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/binopWide2addr.S +++ /dev/null @@ -1,34 +0,0 @@ -%default {"preinstr":"", "result0":"r0", "result1":"r1", "chkzero":"0"} - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0-r1 op r2-r3". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, - * rem-double/2addr - */ - /* binop/2addr vA, vB */ - mov r1, rINST, lsr #12 @ r1<- B - ubfx rINST, rINST, #8, #4 @ rINST<- A - VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] - ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 - ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 - .if $chkzero - orrs ip, r2, r3 @ second arg (r2-r3) is zero? - beq common_errDivideByZero - .endif - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - $preinstr @ optional op; may set condition codes - $instr @ result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {$result0,$result1} @ vAA/vAA+1<- $result0/$result1 - GOTO_OPCODE ip @ jump to next instruction - /* 12-15 instructions */ diff --git a/runtime/interpreter/mterp/arm/const.S b/runtime/interpreter/mterp/arm/const.S deleted file mode 100644 index f6f8157a0b31b0078bdc1dd3f84802b65399c75c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/const.S +++ /dev/null @@ -1,18 +0,0 @@ -%default { "helper":"UndefinedConstHandler" } - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern $helper - EXPORT_PC - FETCH r0, 1 @ r0<- BBBB - mov r1, rINST, lsr #8 @ r1<- AA - add r2, rFP, #OFF_FP_SHADOWFRAME - mov r3, rSELF - bl $helper @ (index, tgt_reg, shadow_frame, self) - PREFETCH_INST 2 @ load rINST - cmp r0, #0 @ fail? - bne MterpPossibleException @ let reference interpreter deal with it. - ADVANCE 2 @ advance rPC - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/control_flow.S b/runtime/interpreter/mterp/arm/control_flow.S new file mode 100644 index 0000000000000000000000000000000000000000..51832e10b50335bf6df12dca752d6d04fd6b535f --- /dev/null +++ b/runtime/interpreter/mterp/arm/control_flow.S @@ -0,0 +1,209 @@ +%def bincmp(condition=""): + /* + * Generic two-operand compare-and-branch operation. Provide a "condition" + * fragment that specifies the comparison to perform. + * + * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le + */ + /* if-cmp vA, vB, +CCCC */ + mov r1, rINST, lsr #12 @ r1<- B + ubfx r0, rINST, #8, #4 @ r0<- A + GET_VREG r3, r1 @ r3<- vB + GET_VREG r0, r0 @ r0<- vA + FETCH_S rINST, 1 @ rINST<- branch offset, in code units + cmp r0, r3 @ compare (vA, vB) + b${condition} MterpCommonTakenBranchNoFlags + cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? + beq .L_check_not_taken_osr + FETCH_ADVANCE_INST 2 + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def zcmp(condition=""): + /* + * Generic one-operand compare-and-branch operation. Provide a "condition" + * fragment that specifies the comparison to perform. + * + * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez + */ + /* if-cmp vAA, +BBBB */ + mov r0, rINST, lsr #8 @ r0<- AA + GET_VREG r0, r0 @ r0<- vAA + FETCH_S rINST, 1 @ rINST<- branch offset, in code units + cmp r0, #0 @ compare (vA, 0) + b${condition} MterpCommonTakenBranchNoFlags + cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? + beq .L_check_not_taken_osr + FETCH_ADVANCE_INST 2 + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def op_goto(): + /* + * Unconditional branch, 8-bit offset. + * + * The branch distance is a signed code-unit offset, which we need to + * double to get a byte offset. + */ + /* goto +AA */ + sbfx rINST, rINST, #8, #8 @ rINST<- ssssssAA (sign-extended) + b MterpCommonTakenBranchNoFlags + +%def op_goto_16(): + /* + * Unconditional branch, 16-bit offset. + * + * The branch distance is a signed code-unit offset, which we need to + * double to get a byte offset. + */ + /* goto/16 +AAAA */ + FETCH_S rINST, 1 @ rINST<- ssssAAAA (sign-extended) + b MterpCommonTakenBranchNoFlags + +%def op_goto_32(): + /* + * Unconditional branch, 32-bit offset. + * + * The branch distance is a signed code-unit offset, which we need to + * double to get a byte offset. + * + * Unlike most opcodes, this one is allowed to branch to itself, so + * our "backward branch" test must be "<=0" instead of "<0". Because + * we need the V bit set, we'll use an adds to convert from Dalvik + * offset to byte offset. + */ + /* goto/32 +AAAAAAAA */ + FETCH r0, 1 @ r0<- aaaa (lo) + FETCH r3, 2 @ r1<- AAAA (hi) + orrs rINST, r0, r3, lsl #16 @ rINST<- AAAAaaaa + b MterpCommonTakenBranch + +%def op_if_eq(): +% bincmp(condition="eq") + +%def op_if_eqz(): +% zcmp(condition="eq") + +%def op_if_ge(): +% bincmp(condition="ge") + +%def op_if_gez(): +% zcmp(condition="ge") + +%def op_if_gt(): +% bincmp(condition="gt") + +%def op_if_gtz(): +% zcmp(condition="gt") + +%def op_if_le(): +% bincmp(condition="le") + +%def op_if_lez(): +% zcmp(condition="le") + +%def op_if_lt(): +% bincmp(condition="lt") + +%def op_if_ltz(): +% zcmp(condition="lt") + +%def op_if_ne(): +% bincmp(condition="ne") + +%def op_if_nez(): +% zcmp(condition="ne") + +%def op_packed_switch(func="MterpDoPackedSwitch"): + /* + * Handle a packed-switch or sparse-switch instruction. In both cases + * we decode it and hand it off to a helper function. + * + * We don't really expect backward branches in a switch statement, but + * they're perfectly legal, so we check for them here. + * + * for: packed-switch, sparse-switch + */ + /* op vAA, +BBBB */ + FETCH r0, 1 @ r0<- bbbb (lo) + FETCH r1, 2 @ r1<- BBBB (hi) + mov r3, rINST, lsr #8 @ r3<- AA + orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb + GET_VREG r1, r3 @ r1<- vAA + add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 + bl $func @ r0<- code-unit branch offset + movs rINST, r0 + b MterpCommonTakenBranch + +%def op_return(): + /* + * Return a 32-bit value. + * + * for: return, return-object + */ + /* op vAA */ + .extern MterpThreadFenceForConstructor + bl MterpThreadFenceForConstructor + ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] + mov r0, rSELF + ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST + blne MterpSuspendCheck @ (self) + mov r2, rINST, lsr #8 @ r2<- AA + GET_VREG r0, r2 @ r0<- vAA + mov r1, #0 + b MterpReturn + +%def op_return_object(): +% op_return() + +%def op_return_void(): + .extern MterpThreadFenceForConstructor + bl MterpThreadFenceForConstructor + ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] + mov r0, rSELF + ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST + blne MterpSuspendCheck @ (self) + mov r0, #0 + mov r1, #0 + b MterpReturn + +%def op_return_void_no_barrier(): + ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] + mov r0, rSELF + ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST + blne MterpSuspendCheck @ (self) + mov r0, #0 + mov r1, #0 + b MterpReturn + +%def op_return_wide(): + /* + * Return a 64-bit value. + */ + /* return-wide vAA */ + .extern MterpThreadFenceForConstructor + bl MterpThreadFenceForConstructor + ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] + mov r0, rSELF + ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST + blne MterpSuspendCheck @ (self) + mov r2, rINST, lsr #8 @ r2<- AA + VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[AA] + ldmia r2, {r0-r1} @ r0/r1 <- vAA/vAA+1 + b MterpReturn + +%def op_sparse_switch(): +% op_packed_switch(func="MterpDoSparseSwitch") + +%def op_throw(): + /* + * Throw an exception object in the current thread. + */ + /* throw vAA */ + EXPORT_PC + mov r2, rINST, lsr #8 @ r2<- AA + GET_VREG r1, r2 @ r1<- vAA (exception object) + cmp r1, #0 @ null object? + beq common_errNullObject @ yes, throw an NPE instead + str r1, [rSELF, #THREAD_EXCEPTION_OFFSET] @ thread->exception<- obj + b MterpException diff --git a/runtime/interpreter/mterp/arm/entry.S b/runtime/interpreter/mterp/arm/entry.S deleted file mode 100644 index 7c7c527ef44c97b6122343b1cc50f0726635477f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/entry.S +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -/* - * Interpreter entry point. - */ - - .text - .align 2 - -/* - * On entry: - * r0 Thread* self/ - * r1 insns_ - * r2 ShadowFrame - * r3 JValue* result_register - * - */ - -ENTRY ExecuteMterpImpl - stmfd sp!, {r3-r10,fp,lr} @ save 10 regs, (r3 just to align 64) - .cfi_adjust_cfa_offset 40 - .cfi_rel_offset r3, 0 - .cfi_rel_offset r4, 4 - .cfi_rel_offset r5, 8 - .cfi_rel_offset r6, 12 - .cfi_rel_offset r7, 16 - .cfi_rel_offset r8, 20 - .cfi_rel_offset r9, 24 - .cfi_rel_offset r10, 28 - .cfi_rel_offset fp, 32 - .cfi_rel_offset lr, 36 - - /* Remember the return register */ - str r3, [r2, #SHADOWFRAME_RESULT_REGISTER_OFFSET] - - /* Remember the dex instruction pointer */ - str r1, [r2, #SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET] - - /* set up "named" registers */ - mov rSELF, r0 - ldr r0, [r2, #SHADOWFRAME_NUMBER_OF_VREGS_OFFSET] - add rFP, r2, #SHADOWFRAME_VREGS_OFFSET @ point to vregs. - VREG_INDEX_TO_ADDR rREFS, r0 @ point to reference array in shadow frame - ldr r0, [r2, #SHADOWFRAME_DEX_PC_OFFSET] @ Get starting dex_pc. - add rPC, r1, r0, lsl #1 @ Create direct pointer to 1st dex opcode - CFI_DEFINE_DEX_PC_WITH_OFFSET(CFI_TMP, CFI_DEX, 0) - EXPORT_PC - - /* Starting ibase */ - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] - - /* Set up for backwards branches & osr profiling */ - ldr r0, [rFP, #OFF_FP_METHOD] - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rSELF - bl MterpSetUpHotnessCountdown - mov rPROFILE, r0 @ Starting hotness countdown to rPROFILE - - /* start executing the instruction at rPC */ - FETCH_INST @ load rINST from rPC - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - /* NOTE: no fallthrough */ diff --git a/runtime/interpreter/mterp/arm/fallback.S b/runtime/interpreter/mterp/arm/fallback.S deleted file mode 100644 index 44e7e1220d841247a99eb6ff9ae11f11f0a1ea8e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/fallback.S +++ /dev/null @@ -1,3 +0,0 @@ -/* Transfer stub to alternate interpreter */ - b MterpFallback - diff --git a/runtime/interpreter/mterp/arm/fbinop.S b/runtime/interpreter/mterp/arm/fbinop.S deleted file mode 100644 index 594ee032d18e5d165e9c2f5c10494599e9d6b428..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/fbinop.S +++ /dev/null @@ -1,23 +0,0 @@ - /* - * Generic 32-bit floating-point operation. Provide an "instr" line that - * specifies an instruction that performs "s2 = s0 op s1". Because we - * use the "softfp" ABI, this must be an instruction, not a function call. - * - * For: add-float, sub-float, mul-float, div-float - */ - /* floatop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB - flds s1, [r3] @ s1<- vCC - flds s0, [r2] @ s0<- vBB - - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - $instr @ s2<- op - GET_INST_OPCODE ip @ extract opcode from rINST - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA - fsts s2, [r9] @ vAA<- s2 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/fbinop2addr.S b/runtime/interpreter/mterp/arm/fbinop2addr.S deleted file mode 100644 index 53c87a08f399a463b0f427fe8ab7d7fd3bad1cc4..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/fbinop2addr.S +++ /dev/null @@ -1,19 +0,0 @@ - /* - * Generic 32-bit floating point "/2addr" binary operation. Provide - * an "instr" line that specifies an instruction that performs - * "s2 = s0 op s1". - * - * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr - */ - /* binop/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA - flds s1, [r3] @ s1<- vB - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - flds s0, [r9] @ s0<- vA - $instr @ s2<- op - GET_INST_OPCODE ip @ extract opcode from rINST - fsts s2, [r9] @ vAA<- s2 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/fbinopWide.S b/runtime/interpreter/mterp/arm/fbinopWide.S deleted file mode 100644 index ca13bfbab6d94ec883289b4992ce214f74ac06a9..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/fbinopWide.S +++ /dev/null @@ -1,23 +0,0 @@ - /* - * Generic 64-bit double-precision floating point binary operation. - * Provide an "instr" line that specifies an instruction that performs - * "d2 = d0 op d1". - * - * for: add-double, sub-double, mul-double, div-double - */ - /* doubleop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB - fldd d1, [r3] @ d1<- vCC - fldd d0, [r2] @ d0<- vBB - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - $instr @ s2<- op - CLEAR_SHADOW_PAIR r9, ip, lr @ Zero shadow regs - GET_INST_OPCODE ip @ extract opcode from rINST - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA - fstd d2, [r9] @ vAA<- d2 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/fbinopWide2addr.S b/runtime/interpreter/mterp/arm/fbinopWide2addr.S deleted file mode 100644 index 9766e2c0c454aa1d7690d7f242433e2b4a31d408..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/fbinopWide2addr.S +++ /dev/null @@ -1,21 +0,0 @@ - /* - * Generic 64-bit floating point "/2addr" binary operation. Provide - * an "instr" line that specifies an instruction that performs - * "d2 = d0 op d1". - * - * For: add-double/2addr, sub-double/2addr, mul-double/2addr, - * div-double/2addr - */ - /* binop/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB - CLEAR_SHADOW_PAIR r9, ip, r0 @ Zero out shadow regs - fldd d1, [r3] @ d1<- vB - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - fldd d0, [r9] @ d0<- vA - $instr @ d2<- op - GET_INST_OPCODE ip @ extract opcode from rINST - fstd d2, [r9] @ vAA<- d2 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/field.S b/runtime/interpreter/mterp/arm/field.S deleted file mode 100644 index c46878829e2c05f05f9d69e27b32c2af69e54b56..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/field.S +++ /dev/null @@ -1,16 +0,0 @@ -%default { } - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern $helper - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl $helper - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/floating_point.S b/runtime/interpreter/mterp/arm/floating_point.S new file mode 100644 index 0000000000000000000000000000000000000000..9f72464db67483471b80ba506a050883ed7e72fb --- /dev/null +++ b/runtime/interpreter/mterp/arm/floating_point.S @@ -0,0 +1,482 @@ +%def fbinop(instr=""): + /* + * Generic 32-bit floating-point operation. Provide an "instr" line that + * specifies an instruction that performs "s2 = s0 op s1". Because we + * use the "softfp" ABI, this must be an instruction, not a function call. + * + * For: add-float, sub-float, mul-float, div-float + */ + /* floatop vAA, vBB, vCC */ + FETCH r0, 1 @ r0<- CCBB + mov r9, rINST, lsr #8 @ r9<- AA + mov r3, r0, lsr #8 @ r3<- CC + and r2, r0, #255 @ r2<- BB + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC + VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB + flds s1, [r3] @ s1<- vCC + flds s0, [r2] @ s0<- vBB + + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + $instr @ s2<- op + GET_INST_OPCODE ip @ extract opcode from rINST + VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA + fsts s2, [r9] @ vAA<- s2 + GOTO_OPCODE ip @ jump to next instruction + +%def fbinop2addr(instr=""): + /* + * Generic 32-bit floating point "/2addr" binary operation. Provide + * an "instr" line that specifies an instruction that performs + * "s2 = s0 op s1". + * + * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr + */ + /* binop/2addr vA, vB */ + mov r3, rINST, lsr #12 @ r3<- B + ubfx r9, rINST, #8, #4 @ r9<- A + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB + VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA + flds s1, [r3] @ s1<- vB + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + flds s0, [r9] @ s0<- vA + $instr @ s2<- op + GET_INST_OPCODE ip @ extract opcode from rINST + fsts s2, [r9] @ vAA<- s2 + GOTO_OPCODE ip @ jump to next instruction + +%def fbinopWide(instr=""): + /* + * Generic 64-bit double-precision floating point binary operation. + * Provide an "instr" line that specifies an instruction that performs + * "d2 = d0 op d1". + * + * for: add-double, sub-double, mul-double, div-double + */ + /* doubleop vAA, vBB, vCC */ + FETCH r0, 1 @ r0<- CCBB + mov r9, rINST, lsr #8 @ r9<- AA + mov r3, r0, lsr #8 @ r3<- CC + and r2, r0, #255 @ r2<- BB + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC + VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB + fldd d1, [r3] @ d1<- vCC + fldd d0, [r2] @ d0<- vBB + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + $instr @ s2<- op + CLEAR_SHADOW_PAIR r9, ip, lr @ Zero shadow regs + GET_INST_OPCODE ip @ extract opcode from rINST + VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA + fstd d2, [r9] @ vAA<- d2 + GOTO_OPCODE ip @ jump to next instruction + +%def fbinopWide2addr(instr=""): + /* + * Generic 64-bit floating point "/2addr" binary operation. Provide + * an "instr" line that specifies an instruction that performs + * "d2 = d0 op d1". + * + * For: add-double/2addr, sub-double/2addr, mul-double/2addr, + * div-double/2addr + */ + /* binop/2addr vA, vB */ + mov r3, rINST, lsr #12 @ r3<- B + ubfx r9, rINST, #8, #4 @ r9<- A + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB + CLEAR_SHADOW_PAIR r9, ip, r0 @ Zero out shadow regs + fldd d1, [r3] @ d1<- vB + VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + fldd d0, [r9] @ d0<- vA + $instr @ d2<- op + GET_INST_OPCODE ip @ extract opcode from rINST + fstd d2, [r9] @ vAA<- d2 + GOTO_OPCODE ip @ jump to next instruction + +%def funop(instr=""): + /* + * Generic 32-bit unary floating-point operation. Provide an "instr" + * line that specifies an instruction that performs "s1 = op s0". + * + * for: int-to-float, float-to-int + */ + /* unop vA, vB */ + mov r3, rINST, lsr #12 @ r3<- B + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB + flds s0, [r3] @ s0<- vB + ubfx r9, rINST, #8, #4 @ r9<- A + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + $instr @ s1<- op + GET_INST_OPCODE ip @ extract opcode from rINST + VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA + fsts s1, [r9] @ vA<- s1 + GOTO_OPCODE ip @ jump to next instruction + +%def funopNarrower(instr=""): + /* + * Generic 64bit-to-32bit unary floating point operation. Provide an + * "instr" line that specifies an instruction that performs "s0 = op d0". + * + * For: double-to-int, double-to-float + */ + /* unop vA, vB */ + mov r3, rINST, lsr #12 @ r3<- B + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB + fldd d0, [r3] @ d0<- vB + ubfx r9, rINST, #8, #4 @ r9<- A + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + $instr @ s0<- op + GET_INST_OPCODE ip @ extract opcode from rINST + VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA + fsts s0, [r9] @ vA<- s0 + GOTO_OPCODE ip @ jump to next instruction + +%def funopWider(instr=""): + /* + * Generic 32bit-to-64bit floating point unary operation. Provide an + * "instr" line that specifies an instruction that performs "d0 = op s0". + * + * For: int-to-double, float-to-double + */ + /* unop vA, vB */ + mov r3, rINST, lsr #12 @ r3<- B + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB + flds s0, [r3] @ s0<- vB + ubfx r9, rINST, #8, #4 @ r9<- A + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + $instr @ d0<- op + CLEAR_SHADOW_PAIR r9, ip, lr @ Zero shadow regs + GET_INST_OPCODE ip @ extract opcode from rINST + VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA + fstd d0, [r9] @ vA<- d0 + GOTO_OPCODE ip @ jump to next instruction + +%def op_add_double(): +% fbinopWide(instr="faddd d2, d0, d1") + +%def op_add_double_2addr(): +% fbinopWide2addr(instr="faddd d2, d0, d1") + +%def op_add_float(): +% fbinop(instr="fadds s2, s0, s1") + +%def op_add_float_2addr(): +% fbinop2addr(instr="fadds s2, s0, s1") + +%def op_cmpg_double(): + /* + * Compare two floating-point values. Puts 0, 1, or -1 into the + * destination register based on the results of the comparison. + * + * int compare(x, y) { + * if (x == y) { + * return 0; + * } else if (x < y) { + * return -1; + * } else if (x > y) { + * return 1; + * } else { + * return 1; + * } + * } + */ + /* op vAA, vBB, vCC */ + FETCH r0, 1 @ r0<- CCBB + mov r9, rINST, lsr #8 @ r9<- AA + and r2, r0, #255 @ r2<- BB + mov r3, r0, lsr #8 @ r3<- CC + VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC + fldd d0, [r2] @ d0<- vBB + fldd d1, [r3] @ d1<- vCC + vcmpe.f64 d0, d1 @ compare (vBB, vCC) + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + mov r0, #1 @ r0<- 1 (default) + GET_INST_OPCODE ip @ extract opcode from rINST + fmstat @ export status flags + mvnmi r0, #0 @ (less than) r1<- -1 + moveq r0, #0 @ (equal) r1<- 0 + SET_VREG r0, r9 @ vAA<- r0 + GOTO_OPCODE ip @ jump to next instruction + +%def op_cmpg_float(): + /* + * Compare two floating-point values. Puts 0, 1, or -1 into the + * destination register based on the results of the comparison. + * + * int compare(x, y) { + * if (x == y) { + * return 0; + * } else if (x < y) { + * return -1; + * } else if (x > y) { + * return 1; + * } else { + * return 1; + * } + * } + */ + /* op vAA, vBB, vCC */ + FETCH r0, 1 @ r0<- CCBB + mov r9, rINST, lsr #8 @ r9<- AA + and r2, r0, #255 @ r2<- BB + mov r3, r0, lsr #8 @ r3<- CC + VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC + flds s0, [r2] @ s0<- vBB + flds s1, [r3] @ s1<- vCC + vcmpe.f32 s0, s1 @ compare (vBB, vCC) + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + mov r0, #1 @ r0<- 1 (default) + GET_INST_OPCODE ip @ extract opcode from rINST + fmstat @ export status flags + mvnmi r0, #0 @ (less than) r1<- -1 + moveq r0, #0 @ (equal) r1<- 0 + SET_VREG r0, r9 @ vAA<- r0 + GOTO_OPCODE ip @ jump to next instruction + +%def op_cmpl_double(): + /* + * Compare two floating-point values. Puts 0, 1, or -1 into the + * destination register based on the results of the comparison. + * + * int compare(x, y) { + * if (x == y) { + * return 0; + * } else if (x > y) { + * return 1; + * } else if (x < y) { + * return -1; + * } else { + * return -1; + * } + * } + */ + /* op vAA, vBB, vCC */ + FETCH r0, 1 @ r0<- CCBB + mov r9, rINST, lsr #8 @ r9<- AA + and r2, r0, #255 @ r2<- BB + mov r3, r0, lsr #8 @ r3<- CC + VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC + fldd d0, [r2] @ d0<- vBB + fldd d1, [r3] @ d1<- vCC + vcmpe.f64 d0, d1 @ compare (vBB, vCC) + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + mvn r0, #0 @ r0<- -1 (default) + GET_INST_OPCODE ip @ extract opcode from rINST + fmstat @ export status flags + movgt r0, #1 @ (greater than) r1<- 1 + moveq r0, #0 @ (equal) r1<- 0 + SET_VREG r0, r9 @ vAA<- r0 + GOTO_OPCODE ip @ jump to next instruction + +%def op_cmpl_float(): + /* + * Compare two floating-point values. Puts 0, 1, or -1 into the + * destination register based on the results of the comparison. + * + * int compare(x, y) { + * if (x == y) { + * return 0; + * } else if (x > y) { + * return 1; + * } else if (x < y) { + * return -1; + * } else { + * return -1; + * } + * } + */ + /* op vAA, vBB, vCC */ + FETCH r0, 1 @ r0<- CCBB + mov r9, rINST, lsr #8 @ r9<- AA + and r2, r0, #255 @ r2<- BB + mov r3, r0, lsr #8 @ r3<- CC + VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC + flds s0, [r2] @ s0<- vBB + flds s1, [r3] @ s1<- vCC + vcmpe.f32 s0, s1 @ compare (vBB, vCC) + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + mvn r0, #0 @ r0<- -1 (default) + GET_INST_OPCODE ip @ extract opcode from rINST + fmstat @ export status flags + movgt r0, #1 @ (greater than) r1<- 1 + moveq r0, #0 @ (equal) r1<- 0 + SET_VREG r0, r9 @ vAA<- r0 + GOTO_OPCODE ip @ jump to next instruction + +%def op_div_double(): +% fbinopWide(instr="fdivd d2, d0, d1") + +%def op_div_double_2addr(): +% fbinopWide2addr(instr="fdivd d2, d0, d1") + +%def op_div_float(): +% fbinop(instr="fdivs s2, s0, s1") + +%def op_div_float_2addr(): +% fbinop2addr(instr="fdivs s2, s0, s1") + +%def op_double_to_float(): +% funopNarrower(instr="vcvt.f32.f64 s0, d0") + +%def op_double_to_int(): +% funopNarrower(instr="ftosizd s0, d0") + +%def op_double_to_long(): +% unopWide(instr="bl d2l_doconv") + +%def op_double_to_long_helper_code(): +/* + * Convert the double in r0/r1 to a long in r0/r1. + * + * We have to clip values to long min/max per the specification. The + * expected common case is a "reasonable" value that converts directly + * to modest integer. The EABI convert function isn't doing this for us. + */ +d2l_doconv: + ubfx r2, r1, #20, #11 @ grab the exponent + movw r3, #0x43e + cmp r2, r3 @ MINLONG < x > MAXLONG? + bhs d2l_special_cases + b __aeabi_d2lz @ tail call to convert double to long +d2l_special_cases: + movw r3, #0x7ff + cmp r2, r3 + beq d2l_maybeNaN @ NaN? +d2l_notNaN: + adds r1, r1, r1 @ sign bit to carry + mov r0, #0xffffffff @ assume maxlong for lsw + mov r1, #0x7fffffff @ assume maxlong for msw + adc r0, r0, #0 + adc r1, r1, #0 @ convert maxlong to minlong if exp negative + bx lr @ return +d2l_maybeNaN: + orrs r3, r0, r1, lsl #12 + beq d2l_notNaN @ if fraction is non-zero, it's a NaN + mov r0, #0 + mov r1, #0 + bx lr @ return 0 for NaN + +%def op_float_to_double(): +% funopWider(instr="vcvt.f64.f32 d0, s0") + +%def op_float_to_int(): +% funop(instr="ftosizs s1, s0") + +%def op_float_to_long(): +% unopWider(instr="bl f2l_doconv") + +%def op_float_to_long_helper_code(): +/* + * Convert the float in r0 to a long in r0/r1. + * + * We have to clip values to long min/max per the specification. The + * expected common case is a "reasonable" value that converts directly + * to modest integer. The EABI convert function isn't doing this for us. + */ +f2l_doconv: + ubfx r2, r0, #23, #8 @ grab the exponent + cmp r2, #0xbe @ MININT < x > MAXINT? + bhs f2l_special_cases + b __aeabi_f2lz @ tail call to convert float to long +f2l_special_cases: + cmp r2, #0xff @ NaN or infinity? + beq f2l_maybeNaN +f2l_notNaN: + adds r0, r0, r0 @ sign bit to carry + mov r0, #0xffffffff @ assume maxlong for lsw + mov r1, #0x7fffffff @ assume maxlong for msw + adc r0, r0, #0 + adc r1, r1, #0 @ convert maxlong to minlong if exp negative + bx lr @ return +f2l_maybeNaN: + lsls r3, r0, #9 + beq f2l_notNaN @ if fraction is non-zero, it's a NaN + mov r0, #0 + mov r1, #0 + bx lr @ return 0 for NaN + +%def op_int_to_double(): +% funopWider(instr="fsitod d0, s0") + +%def op_int_to_float(): +% funop(instr="fsitos s1, s0") + +%def op_long_to_double(): + /* + * Specialised 64-bit floating point operation. + * + * Note: The result will be returned in d2. + * + * For: long-to-double + */ + mov r3, rINST, lsr #12 @ r3<- B + ubfx r9, rINST, #8, #4 @ r9<- A + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] + VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[A] + vldr d0, [r3] @ d0<- vAA + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + + vcvt.f64.s32 d1, s1 @ d1<- (double)(vAAh) + vcvt.f64.u32 d2, s0 @ d2<- (double)(vAAl) + vldr d3, constval$opcode + vmla.f64 d2, d1, d3 @ d2<- vAAh*2^32 + vAAl + + GET_INST_OPCODE ip @ extract opcode from rINST + vstr.64 d2, [r9] @ vAA<- d2 + GOTO_OPCODE ip @ jump to next instruction + + /* literal pool helper */ +constval${opcode}: + .8byte 0x41f0000000000000 + +%def op_long_to_float(): +% unopNarrower(instr="bl __aeabi_l2f") + +%def op_mul_double(): +% fbinopWide(instr="fmuld d2, d0, d1") + +%def op_mul_double_2addr(): +% fbinopWide2addr(instr="fmuld d2, d0, d1") + +%def op_mul_float(): +% fbinop(instr="fmuls s2, s0, s1") + +%def op_mul_float_2addr(): +% fbinop2addr(instr="fmuls s2, s0, s1") + +%def op_neg_double(): +% unopWide(instr="add r1, r1, #0x80000000") + +%def op_neg_float(): +% unop(instr="add r0, r0, #0x80000000") + +%def op_rem_double(): +/* EABI doesn't define a double remainder function, but libm does */ +% binopWide(instr="bl fmod") + +%def op_rem_double_2addr(): +/* EABI doesn't define a double remainder function, but libm does */ +% binopWide2addr(instr="bl fmod") + +%def op_rem_float(): +/* EABI doesn't define a float remainder function, but libm does */ +% binop(instr="bl fmodf") + +%def op_rem_float_2addr(): +/* EABI doesn't define a float remainder function, but libm does */ +% binop2addr(instr="bl fmodf") + +%def op_sub_double(): +% fbinopWide(instr="fsubd d2, d0, d1") + +%def op_sub_double_2addr(): +% fbinopWide2addr(instr="fsubd d2, d0, d1") + +%def op_sub_float(): +% fbinop(instr="fsubs s2, s0, s1") + +%def op_sub_float_2addr(): +% fbinop2addr(instr="fsubs s2, s0, s1") diff --git a/runtime/interpreter/mterp/arm/footer.S b/runtime/interpreter/mterp/arm/footer.S deleted file mode 100644 index 8e9c3c22fe913adf501d6fbe5d9d7704dfa9b4c1..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/footer.S +++ /dev/null @@ -1,297 +0,0 @@ -/* - * =========================================================================== - * Common subroutines and data - * =========================================================================== - */ - - .text - .align 2 - -/* - * We've detected a condition that will result in an exception, but the exception - * has not yet been thrown. Just bail out to the reference interpreter to deal with it. - * TUNING: for consistency, we may want to just go ahead and handle these here. - */ -common_errDivideByZero: - EXPORT_PC -#if MTERP_LOGGING - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - bl MterpLogDivideByZeroException -#endif - b MterpCommonFallback - -common_errArrayIndex: - EXPORT_PC -#if MTERP_LOGGING - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - bl MterpLogArrayIndexException -#endif - b MterpCommonFallback - -common_errNegativeArraySize: - EXPORT_PC -#if MTERP_LOGGING - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - bl MterpLogNegativeArraySizeException -#endif - b MterpCommonFallback - -common_errNoSuchMethod: - EXPORT_PC -#if MTERP_LOGGING - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - bl MterpLogNoSuchMethodException -#endif - b MterpCommonFallback - -common_errNullObject: - EXPORT_PC -#if MTERP_LOGGING - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - bl MterpLogNullObjectException -#endif - b MterpCommonFallback - -common_exceptionThrown: - EXPORT_PC -#if MTERP_LOGGING - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - bl MterpLogExceptionThrownException -#endif - b MterpCommonFallback - -MterpSuspendFallback: - EXPORT_PC -#if MTERP_LOGGING - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - ldr r2, [rSELF, #THREAD_FLAGS_OFFSET] - bl MterpLogSuspendFallback -#endif - b MterpCommonFallback - -/* - * If we're here, something is out of the ordinary. If there is a pending - * exception, handle it. Otherwise, roll back and retry with the reference - * interpreter. - */ -MterpPossibleException: - ldr r0, [rSELF, #THREAD_EXCEPTION_OFFSET] - cmp r0, #0 @ Exception pending? - beq MterpFallback @ If not, fall back to reference interpreter. - /* intentional fallthrough - handle pending exception. */ -/* - * On return from a runtime helper routine, we've found a pending exception. - * Can we handle it here - or need to bail out to caller? - * - */ -MterpException: - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - bl MterpHandleException @ (self, shadow_frame) - cmp r0, #0 - beq MterpExceptionReturn @ no local catch, back to caller. - ldr r0, [rFP, #OFF_FP_DEX_INSTRUCTIONS] - ldr r1, [rFP, #OFF_FP_DEX_PC] - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] - add rPC, r0, r1, lsl #1 @ generate new dex_pc_ptr - /* Do we need to switch interpreters? */ - bl MterpShouldSwitchInterpreters - cmp r0, #0 - bne MterpFallback - /* resume execution at catch block */ - EXPORT_PC - FETCH_INST - GET_INST_OPCODE ip - GOTO_OPCODE ip - /* NOTE: no fallthrough */ - -/* - * Common handling for branches with support for Jit profiling. - * On entry: - * rINST <= signed offset - * rPROFILE <= signed hotness countdown (expanded to 32 bits) - * condition bits <= set to establish sign of offset (use "NoFlags" entry if not) - * - * We have quite a few different cases for branch profiling, OSR detection and - * suspend check support here. - * - * Taken backward branches: - * If profiling active, do hotness countdown and report if we hit zero. - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * Is there a pending suspend request? If so, suspend. - * - * Taken forward branches and not-taken backward branches: - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * - * Our most common case is expected to be a taken backward branch with active jit profiling, - * but no full OSR check and no pending suspend request. - * Next most common case is not-taken branch with no full OSR check. - * - */ -MterpCommonTakenBranchNoFlags: - cmp rINST, #0 -MterpCommonTakenBranch: - bgt .L_forward_branch @ don't add forward branches to hotness -/* - * We need to subtract 1 from positive values and we should not see 0 here, - * so we may use the result of the comparison with -1. - */ -#if JIT_CHECK_OSR != -1 -# error "JIT_CHECK_OSR must be -1." -#endif - cmp rPROFILE, #JIT_CHECK_OSR - beq .L_osr_check - subsgt rPROFILE, #1 - beq .L_add_batch @ counted down to zero - report -.L_resume_backward_branch: - ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] - REFRESH_IBASE - add r2, rINST, rINST @ r2<- byte offset - FETCH_ADVANCE_INST_RB r2 @ update rPC, load rINST - ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - bne .L_suspend_request_pending - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -.L_suspend_request_pending: - EXPORT_PC - mov r0, rSELF - bl MterpSuspendCheck @ (self) - cmp r0, #0 - bne MterpFallback - REFRESH_IBASE @ might have changed during suspend - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -.L_no_count_backwards: - cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? - bne .L_resume_backward_branch -.L_osr_check: - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rINST - EXPORT_PC - bl MterpMaybeDoOnStackReplacement @ (self, shadow_frame, offset) - cmp r0, #0 - bne MterpOnStackReplacement - b .L_resume_backward_branch - -.L_forward_branch: - cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? - beq .L_check_osr_forward -.L_resume_forward_branch: - add r2, rINST, rINST @ r2<- byte offset - FETCH_ADVANCE_INST_RB r2 @ update rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -.L_check_osr_forward: - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rINST - EXPORT_PC - bl MterpMaybeDoOnStackReplacement @ (self, shadow_frame, offset) - cmp r0, #0 - bne MterpOnStackReplacement - b .L_resume_forward_branch - -.L_add_batch: - add r1, rFP, #OFF_FP_SHADOWFRAME - strh rPROFILE, [r1, #SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET] - ldr r0, [rFP, #OFF_FP_METHOD] - mov r2, rSELF - bl MterpAddHotnessBatch @ (method, shadow_frame, self) - mov rPROFILE, r0 @ restore new hotness countdown to rPROFILE - b .L_no_count_backwards - -/* - * Entered from the conditional branch handlers when OSR check request active on - * not-taken path. All Dalvik not-taken conditional branch offsets are 2. - */ -.L_check_not_taken_osr: - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, #2 - EXPORT_PC - bl MterpMaybeDoOnStackReplacement @ (self, shadow_frame, offset) - cmp r0, #0 - bne MterpOnStackReplacement - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* - * On-stack replacement has happened, and now we've returned from the compiled method. - */ -MterpOnStackReplacement: -#if MTERP_LOGGING - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rINST - bl MterpLogOSR -#endif - mov r0, #1 @ Signal normal return - b MterpDone - -/* - * Bail out to reference interpreter. - */ -MterpFallback: - EXPORT_PC -#if MTERP_LOGGING - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - bl MterpLogFallback -#endif -MterpCommonFallback: - mov r0, #0 @ signal retry with reference interpreter. - b MterpDone - -/* - * We pushed some registers on the stack in ExecuteMterpImpl, then saved - * SP and LR. Here we restore SP, restore the registers, and then restore - * LR to PC. - * - * On entry: - * uint32_t* rFP (should still be live, pointer to base of vregs) - */ -MterpExceptionReturn: - mov r0, #1 @ signal return to caller. - b MterpDone -MterpReturn: - ldr r2, [rFP, #OFF_FP_RESULT_REGISTER] - str r0, [r2] - str r1, [r2, #4] - mov r0, #1 @ signal return to caller. -MterpDone: -/* - * At this point, we expect rPROFILE to be non-zero. If negative, hotness is disabled or we're - * checking for OSR. If greater than zero, we might have unreported hotness to register - * (the difference between the ending rPROFILE and the cached hotness counter). rPROFILE - * should only reach zero immediately after a hotness decrement, and is then reset to either - * a negative special state or the new non-zero countdown value. - */ - cmp rPROFILE, #0 - bgt MterpProfileActive @ if > 0, we may have some counts to report. - ldmfd sp!, {r3-r10,fp,pc} @ restore 10 regs and return - -MterpProfileActive: - mov rINST, r0 @ stash return value - /* Report cached hotness counts */ - ldr r0, [rFP, #OFF_FP_METHOD] - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rSELF - strh rPROFILE, [r1, #SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET] - bl MterpAddHotnessBatch @ (method, shadow_frame, self) - mov r0, rINST @ restore return value - ldmfd sp!, {r3-r10,fp,pc} @ restore 10 regs and return - - END ExecuteMterpImpl - diff --git a/runtime/interpreter/mterp/arm/funop.S b/runtime/interpreter/mterp/arm/funop.S deleted file mode 100644 index 1b8bb8bac68c9c5f9a754ea26f211ee0169a0fcd..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/funop.S +++ /dev/null @@ -1,17 +0,0 @@ - /* - * Generic 32-bit unary floating-point operation. Provide an "instr" - * line that specifies an instruction that performs "s1 = op s0". - * - * for: int-to-float, float-to-int - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB - flds s0, [r3] @ s0<- vB - ubfx r9, rINST, #8, #4 @ r9<- A - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - $instr @ s1<- op - GET_INST_OPCODE ip @ extract opcode from rINST - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA - fsts s1, [r9] @ vA<- s1 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/funopNarrower.S b/runtime/interpreter/mterp/arm/funopNarrower.S deleted file mode 100644 index b9f758ba867e64c8374235a8013871cc7a456de8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/funopNarrower.S +++ /dev/null @@ -1,17 +0,0 @@ - /* - * Generic 64bit-to-32bit unary floating point operation. Provide an - * "instr" line that specifies an instruction that performs "s0 = op d0". - * - * For: double-to-int, double-to-float - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB - fldd d0, [r3] @ d0<- vB - ubfx r9, rINST, #8, #4 @ r9<- A - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - $instr @ s0<- op - GET_INST_OPCODE ip @ extract opcode from rINST - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA - fsts s0, [r9] @ vA<- s0 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/funopWider.S b/runtime/interpreter/mterp/arm/funopWider.S deleted file mode 100644 index 854cdc9b66304c12086416d1f67dcb7970ab3ab7..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/funopWider.S +++ /dev/null @@ -1,18 +0,0 @@ - /* - * Generic 32bit-to-64bit floating point unary operation. Provide an - * "instr" line that specifies an instruction that performs "d0 = op s0". - * - * For: int-to-double, float-to-double - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB - flds s0, [r3] @ s0<- vB - ubfx r9, rINST, #8, #4 @ r9<- A - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - $instr @ d0<- op - CLEAR_SHADOW_PAIR r9, ip, lr @ Zero shadow regs - GET_INST_OPCODE ip @ extract opcode from rINST - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA - fstd d0, [r9] @ vA<- d0 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/header.S b/runtime/interpreter/mterp/arm/header.S deleted file mode 100644 index 8d9cab5a2f14154ba5b1b8c3975e4124f559d08a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/header.S +++ /dev/null @@ -1,312 +0,0 @@ -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - Art assembly interpreter notes: - - First validate assembly code by implementing ExecuteXXXImpl() style body (doesn't - handle invoke, allows higher-level code to create frame & shadow frame. - - Once that's working, support direct entry code & eliminate shadow frame (and - excess locals allocation. - - Some (hopefully) temporary ugliness. We'll treat rFP as pointing to the - base of the vreg array within the shadow frame. Access the other fields, - dex_pc_, method_ and number_of_vregs_ via negative offsets. For now, we'll continue - the shadow frame mechanism of double-storing object references - via rFP & - number_of_vregs_. - - */ - -/* -ARM EABI general notes: - -r0-r3 hold first 4 args to a method; they are not preserved across method calls -r4-r8 are available for general use -r9 is given special treatment in some situations, but not for us -r10 (sl) seems to be generally available -r11 (fp) is used by gcc (unless -fomit-frame-pointer is set) -r12 (ip) is scratch -- not preserved across method calls -r13 (sp) should be managed carefully in case a signal arrives -r14 (lr) must be preserved -r15 (pc) can be tinkered with directly - -r0 holds returns of <= 4 bytes -r0-r1 hold returns of 8 bytes, low word in r0 - -Callee must save/restore r4+ (except r12) if it modifies them. If VFP -is present, registers s16-s31 (a/k/a d8-d15, a/k/a q4-q7) must be preserved, -s0-s15 (d0-d7, q0-a3) do not need to be. - -Stack is "full descending". Only the arguments that don't fit in the first 4 -registers are placed on the stack. "sp" points at the first stacked argument -(i.e. the 5th arg). - -VFP: single-precision results in s0, double-precision results in d0. - -In the EABI, "sp" must be 64-bit aligned on entry to a function, and any -64-bit quantities (long long, double) must be 64-bit aligned. -*/ - -/* -Mterp and ARM notes: - -The following registers have fixed assignments: - - reg nick purpose - r4 rPC interpreted program counter, used for fetching instructions - r5 rFP interpreted frame pointer, used for accessing locals and args - r6 rSELF self (Thread) pointer - r7 rINST first 16-bit code unit of current instruction - r8 rIBASE interpreted instruction base pointer, used for computed goto - r10 rPROFILE branch profiling countdown - r11 rREFS base of object references in shadow frame (ideally, we'll get rid of this later). - -Macros are provided for common operations. Each macro MUST emit only -one instruction to make instruction-counting easier. They MUST NOT alter -unspecified registers or condition codes. -*/ - -/* - * This is a #include, not a %include, because we want the C pre-processor - * to expand the macros into assembler assignment statements. - */ -#include "asm_support.h" -#include "interpreter/cfi_asm_support.h" - -#define MTERP_PROFILE_BRANCHES 1 -#define MTERP_LOGGING 0 - -/* During bringup, we'll use the shadow frame model instead of rFP */ -/* single-purpose registers, given names for clarity */ -#define rPC r4 -#define CFI_DEX 4 // DWARF register number of the register holding dex-pc (xPC). -#define CFI_TMP 0 // DWARF register number of the first argument register (r0). -#define rFP r5 -#define rSELF r6 -#define rINST r7 -#define rIBASE r8 -#define rPROFILE r10 -#define rREFS r11 - -/* - * Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs. So, - * to access other shadow frame fields, we need to use a backwards offset. Define those here. - */ -#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) -#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) -#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) -#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) -#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) -#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) -#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) -#define OFF_FP_DEX_INSTRUCTIONS OFF_FP(SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET) -#define OFF_FP_SHADOWFRAME OFF_FP(0) - -/* - * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must - * be done *before* something throws. - * - * It's okay to do this more than once. - * - * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped - * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction - * offset into the code_items_[] array. For effiency, we will "export" the - * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC - * to convert to a dex pc when needed. - */ -.macro EXPORT_PC - str rPC, [rFP, #OFF_FP_DEX_PC_PTR] -.endm - -.macro EXPORT_DEX_PC tmp - ldr \tmp, [rFP, #OFF_FP_DEX_INSTRUCTIONS] - str rPC, [rFP, #OFF_FP_DEX_PC_PTR] - sub \tmp, rPC, \tmp - asr \tmp, #1 - str \tmp, [rFP, #OFF_FP_DEX_PC] -.endm - -/* - * Fetch the next instruction from rPC into rINST. Does not advance rPC. - */ -.macro FETCH_INST - ldrh rINST, [rPC] -.endm - -/* - * Fetch the next instruction from the specified offset. Advances rPC - * to point to the next instruction. "_count" is in 16-bit code units. - * - * Because of the limited size of immediate constants on ARM, this is only - * suitable for small forward movements (i.e. don't try to implement "goto" - * with this). - * - * This must come AFTER anything that can throw an exception, or the - * exception catch may miss. (This also implies that it must come after - * EXPORT_PC.) - */ -.macro FETCH_ADVANCE_INST count - ldrh rINST, [rPC, #((\count)*2)]! -.endm - -/* - * The operation performed here is similar to FETCH_ADVANCE_INST, except the - * src and dest registers are parameterized (not hard-wired to rPC and rINST). - */ -.macro PREFETCH_ADVANCE_INST dreg, sreg, count - ldrh \dreg, [\sreg, #((\count)*2)]! -.endm - -/* - * Similar to FETCH_ADVANCE_INST, but does not update rPC. Used to load - * rINST ahead of possible exception point. Be sure to manually advance rPC - * later. - */ -.macro PREFETCH_INST count - ldrh rINST, [rPC, #((\count)*2)] -.endm - -/* Advance rPC by some number of code units. */ -.macro ADVANCE count - add rPC, #((\count)*2) -.endm - -/* - * Fetch the next instruction from an offset specified by _reg. Updates - * rPC to point to the next instruction. "_reg" must specify the distance - * in bytes, *not* 16-bit code units, and may be a signed value. - * - * We want to write "ldrh rINST, [rPC, _reg, lsl #1]!", but some of the - * bits that hold the shift distance are used for the half/byte/sign flags. - * In some cases we can pre-double _reg for free, so we require a byte offset - * here. - */ -.macro FETCH_ADVANCE_INST_RB reg - ldrh rINST, [rPC, \reg]! -.endm - -/* - * Fetch a half-word code unit from an offset past the current PC. The - * "_count" value is in 16-bit code units. Does not advance rPC. - * - * The "_S" variant works the same but treats the value as signed. - */ -.macro FETCH reg, count - ldrh \reg, [rPC, #((\count)*2)] -.endm - -.macro FETCH_S reg, count - ldrsh \reg, [rPC, #((\count)*2)] -.endm - -/* - * Fetch one byte from an offset past the current PC. Pass in the same - * "_count" as you would for FETCH, and an additional 0/1 indicating which - * byte of the halfword you want (lo/hi). - */ -.macro FETCH_B reg, count, byte - ldrb \reg, [rPC, #((\count)*2+(\byte))] -.endm - -/* - * Put the instruction's opcode field into the specified register. - */ -.macro GET_INST_OPCODE reg - and \reg, rINST, #255 -.endm - -/* - * Put the prefetched instruction's opcode field into the specified register. - */ -.macro GET_PREFETCHED_OPCODE oreg, ireg - and \oreg, \ireg, #255 -.endm - -/* - * Begin executing the opcode in _reg. Because this only jumps within the - * interpreter, we don't have to worry about pre-ARMv5 THUMB interwork. - */ -.macro GOTO_OPCODE reg - add pc, rIBASE, \reg, lsl #${handler_size_bits} -.endm -.macro GOTO_OPCODE_BASE base,reg - add pc, \base, \reg, lsl #${handler_size_bits} -.endm - -/* - * Get/set the 32-bit value from a Dalvik register. - */ -.macro GET_VREG reg, vreg - ldr \reg, [rFP, \vreg, lsl #2] -.endm -.macro SET_VREG reg, vreg - str \reg, [rFP, \vreg, lsl #2] - mov \reg, #0 - str \reg, [rREFS, \vreg, lsl #2] -.endm -.macro SET_VREG_OBJECT reg, vreg, tmpreg - str \reg, [rFP, \vreg, lsl #2] - str \reg, [rREFS, \vreg, lsl #2] -.endm -.macro SET_VREG_SHADOW reg, vreg - str \reg, [rREFS, \vreg, lsl #2] -.endm - -/* - * Clear the corresponding shadow regs for a vreg pair - */ -.macro CLEAR_SHADOW_PAIR vreg, tmp1, tmp2 - mov \tmp1, #0 - add \tmp2, \vreg, #1 - SET_VREG_SHADOW \tmp1, \vreg - SET_VREG_SHADOW \tmp1, \tmp2 -.endm - -/* - * Convert a virtual register index into an address. - */ -.macro VREG_INDEX_TO_ADDR reg, vreg - add \reg, rFP, \vreg, lsl #2 /* WARNING/FIXME: handle shadow frame vreg zero if store */ -.endm - -/* - * Refresh handler table. - */ -.macro REFRESH_IBASE - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] -.endm - -/* - * cfi support macros. - */ -.macro ENTRY name - .arm - .type \name, #function - .hidden \name // Hide this as a global symbol, so we do not incur plt calls. - .global \name - /* Cache alignment for function entry */ - .balign 16 -\name: - .cfi_startproc - .fnstart -.endm - -.macro END name - .fnend - .cfi_endproc - .size \name, .-\name -.endm diff --git a/runtime/interpreter/mterp/arm/instruction_end.S b/runtime/interpreter/mterp/arm/instruction_end.S deleted file mode 100644 index f90ebd0221f7ff35964753368888c2576917d112..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/instruction_end.S +++ /dev/null @@ -1,5 +0,0 @@ - - .type artMterpAsmInstructionEnd, #object - .hidden artMterpAsmInstructionEnd - .global artMterpAsmInstructionEnd -artMterpAsmInstructionEnd: diff --git a/runtime/interpreter/mterp/arm/instruction_end_alt.S b/runtime/interpreter/mterp/arm/instruction_end_alt.S deleted file mode 100644 index 0b66dbb9479dd5600b5b69aeeb3ed91bcaa09e1f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/instruction_end_alt.S +++ /dev/null @@ -1,5 +0,0 @@ - - .type artMterpAsmAltInstructionEnd, #object - .hidden artMterpAsmAltInstructionEnd - .global artMterpAsmAltInstructionEnd -artMterpAsmAltInstructionEnd: diff --git a/runtime/interpreter/mterp/arm/instruction_end_sister.S b/runtime/interpreter/mterp/arm/instruction_end_sister.S deleted file mode 100644 index 71c0300f6d5a139f623fd1397be73b7a6cc01c34..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/instruction_end_sister.S +++ /dev/null @@ -1,5 +0,0 @@ - - .type artMterpAsmSisterEnd, #object - .hidden artMterpAsmSisterEnd - .global artMterpAsmSisterEnd -artMterpAsmSisterEnd: diff --git a/runtime/interpreter/mterp/arm/instruction_start.S b/runtime/interpreter/mterp/arm/instruction_start.S deleted file mode 100644 index b7e9cf51e4ff0498942076b0a4de9d13c228a933..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/instruction_start.S +++ /dev/null @@ -1,6 +0,0 @@ - - .type artMterpAsmInstructionStart, #object - .hidden artMterpAsmInstructionStart - .global artMterpAsmInstructionStart -artMterpAsmInstructionStart = .L_op_nop - .text diff --git a/runtime/interpreter/mterp/arm/instruction_start_alt.S b/runtime/interpreter/mterp/arm/instruction_start_alt.S deleted file mode 100644 index 7a67ba064c3171e55aad5cabf1458c58c184c5ff..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/instruction_start_alt.S +++ /dev/null @@ -1,6 +0,0 @@ - - .type artMterpAsmAltInstructionStart, #object - .hidden artMterpAsmAltInstructionStart - .global artMterpAsmAltInstructionStart -artMterpAsmAltInstructionStart = .L_ALT_op_nop - .text diff --git a/runtime/interpreter/mterp/arm/instruction_start_sister.S b/runtime/interpreter/mterp/arm/instruction_start_sister.S deleted file mode 100644 index 00360616053f769913e829e97a698931958f6b9a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/instruction_start_sister.S +++ /dev/null @@ -1,7 +0,0 @@ - - .type artMterpAsmSisterStart, #object - .hidden artMterpAsmSisterStart - .global artMterpAsmSisterStart - .text - .balign 4 -artMterpAsmSisterStart: diff --git a/runtime/interpreter/mterp/arm/invoke.S b/runtime/interpreter/mterp/arm/invoke.S index e47dd1b3ca222a7c4a96b2cc7d79cacaa5cf89f2..8693d3b8ca72541eedd7c7fd601505a79c01f8a3 100644 --- a/runtime/interpreter/mterp/arm/invoke.S +++ b/runtime/interpreter/mterp/arm/invoke.S @@ -1,4 +1,4 @@ -%default { "helper":"UndefinedInvokeHandler" } +%def invoke(helper="UndefinedInvokeHandler"): /* * Generic invoke handler wrapper. */ @@ -20,3 +20,102 @@ GET_INST_OPCODE ip GOTO_OPCODE ip + +%def invoke_polymorphic(helper="UndefinedInvokeHandler"): + /* + * invoke-polymorphic handler wrapper. + */ + /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ + /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ + .extern $helper + EXPORT_PC + mov r0, rSELF + add r1, rFP, #OFF_FP_SHADOWFRAME + mov r2, rPC + mov r3, rINST + bl $helper + cmp r0, #0 + beq MterpException + FETCH_ADVANCE_INST 4 + bl MterpShouldSwitchInterpreters + cmp r0, #0 + bne MterpFallback + GET_INST_OPCODE ip + GOTO_OPCODE ip + +%def op_invoke_custom(): +% invoke(helper="MterpInvokeCustom") + /* + * Handle an invoke-custom invocation. + * + * for: invoke-custom, invoke-custom/range + */ + /* op vB, {vD, vE, vF, vG, vA}, call_site@BBBB */ + /* op vAA, {vCCCC..v(CCCC+AA-1)}, call_site@BBBB */ + +%def op_invoke_custom_range(): +% invoke(helper="MterpInvokeCustomRange") + +%def op_invoke_direct(): +% invoke(helper="MterpInvokeDirect") + +%def op_invoke_direct_range(): +% invoke(helper="MterpInvokeDirectRange") + +%def op_invoke_interface(): +% invoke(helper="MterpInvokeInterface") + /* + * Handle an interface method call. + * + * for: invoke-interface, invoke-interface/range + */ + /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ + /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ + +%def op_invoke_interface_range(): +% invoke(helper="MterpInvokeInterfaceRange") + +%def op_invoke_polymorphic(): +% invoke_polymorphic(helper="MterpInvokePolymorphic") + +%def op_invoke_polymorphic_range(): +% invoke_polymorphic(helper="MterpInvokePolymorphicRange") + +%def op_invoke_static(): +% invoke(helper="MterpInvokeStatic") + + +%def op_invoke_static_range(): +% invoke(helper="MterpInvokeStaticRange") + +%def op_invoke_super(): +% invoke(helper="MterpInvokeSuper") + /* + * Handle a "super" method call. + * + * for: invoke-super, invoke-super/range + */ + /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ + /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ + +%def op_invoke_super_range(): +% invoke(helper="MterpInvokeSuperRange") + +%def op_invoke_virtual(): +% invoke(helper="MterpInvokeVirtual") + /* + * Handle a virtual method call. + * + * for: invoke-virtual, invoke-virtual/range + */ + /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ + /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ + +%def op_invoke_virtual_quick(): +% invoke(helper="MterpInvokeVirtualQuick") + +%def op_invoke_virtual_range(): +% invoke(helper="MterpInvokeVirtualRange") + +%def op_invoke_virtual_range_quick(): +% invoke(helper="MterpInvokeVirtualQuickRange") diff --git a/runtime/interpreter/mterp/arm/invoke_polymorphic.S b/runtime/interpreter/mterp/arm/invoke_polymorphic.S deleted file mode 100644 index f569d61c0bad4d209c2e826a48e6f53443d3431f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/invoke_polymorphic.S +++ /dev/null @@ -1,21 +0,0 @@ -%default { "helper":"UndefinedInvokeHandler" } - /* - * invoke-polymorphic handler wrapper. - */ - /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ - .extern $helper - EXPORT_PC - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - mov r3, rINST - bl $helper - cmp r0, #0 - beq MterpException - FETCH_ADVANCE_INST 4 - bl MterpShouldSwitchInterpreters - cmp r0, #0 - bne MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip diff --git a/runtime/interpreter/mterp/arm/main.S b/runtime/interpreter/mterp/arm/main.S new file mode 100644 index 0000000000000000000000000000000000000000..dbccb465d131e6e5af655e7a8d4d2d7679c575ca --- /dev/null +++ b/runtime/interpreter/mterp/arm/main.S @@ -0,0 +1,744 @@ +%def header(): +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + Art assembly interpreter notes: + + First validate assembly code by implementing ExecuteXXXImpl() style body (doesn't + handle invoke, allows higher-level code to create frame & shadow frame. + + Once that's working, support direct entry code & eliminate shadow frame (and + excess locals allocation. + + Some (hopefully) temporary ugliness. We'll treat rFP as pointing to the + base of the vreg array within the shadow frame. Access the other fields, + dex_pc_, method_ and number_of_vregs_ via negative offsets. For now, we'll continue + the shadow frame mechanism of double-storing object references - via rFP & + number_of_vregs_. + + */ + +/* +ARM EABI general notes: + +r0-r3 hold first 4 args to a method; they are not preserved across method calls +r4-r8 are available for general use +r9 is given special treatment in some situations, but not for us +r10 (sl) seems to be generally available +r11 (fp) is used by gcc (unless -fomit-frame-pointer is set) +r12 (ip) is scratch -- not preserved across method calls +r13 (sp) should be managed carefully in case a signal arrives +r14 (lr) must be preserved +r15 (pc) can be tinkered with directly + +r0 holds returns of <= 4 bytes +r0-r1 hold returns of 8 bytes, low word in r0 + +Callee must save/restore r4+ (except r12) if it modifies them. If VFP +is present, registers s16-s31 (a/k/a d8-d15, a/k/a q4-q7) must be preserved, +s0-s15 (d0-d7, q0-a3) do not need to be. + +Stack is "full descending". Only the arguments that don't fit in the first 4 +registers are placed on the stack. "sp" points at the first stacked argument +(i.e. the 5th arg). + +VFP: single-precision results in s0, double-precision results in d0. + +In the EABI, "sp" must be 64-bit aligned on entry to a function, and any +64-bit quantities (long long, double) must be 64-bit aligned. +*/ + +/* +Mterp and ARM notes: + +The following registers have fixed assignments: + + reg nick purpose + r4 rPC interpreted program counter, used for fetching instructions + r5 rFP interpreted frame pointer, used for accessing locals and args + r6 rSELF self (Thread) pointer + r7 rINST first 16-bit code unit of current instruction + r8 rIBASE interpreted instruction base pointer, used for computed goto + r10 rPROFILE branch profiling countdown + r11 rREFS base of object references in shadow frame (ideally, we'll get rid of this later). + +Macros are provided for common operations. Each macro MUST emit only +one instruction to make instruction-counting easier. They MUST NOT alter +unspecified registers or condition codes. +*/ + +/* + * This is a #include, not a %include, because we want the C pre-processor + * to expand the macros into assembler assignment statements. + */ +#include "asm_support.h" +#include "interpreter/cfi_asm_support.h" + +#define MTERP_PROFILE_BRANCHES 1 +#define MTERP_LOGGING 0 + +/* During bringup, we'll use the shadow frame model instead of rFP */ +/* single-purpose registers, given names for clarity */ +#define rPC r4 +#define CFI_DEX 4 // DWARF register number of the register holding dex-pc (xPC). +#define CFI_TMP 0 // DWARF register number of the first argument register (r0). +#define rFP r5 +#define rSELF r6 +#define rINST r7 +#define rIBASE r8 +#define rPROFILE r10 +#define rREFS r11 + +/* + * Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs. So, + * to access other shadow frame fields, we need to use a backwards offset. Define those here. + */ +#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) +#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) +#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) +#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) +#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) +#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) +#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) +#define OFF_FP_DEX_INSTRUCTIONS OFF_FP(SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET) +#define OFF_FP_SHADOWFRAME OFF_FP(0) + +/* + * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must + * be done *before* something throws. + * + * It's okay to do this more than once. + * + * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped + * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction + * offset into the code_items_[] array. For effiency, we will "export" the + * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC + * to convert to a dex pc when needed. + */ +.macro EXPORT_PC + str rPC, [rFP, #OFF_FP_DEX_PC_PTR] +.endm + +.macro EXPORT_DEX_PC tmp + ldr \tmp, [rFP, #OFF_FP_DEX_INSTRUCTIONS] + str rPC, [rFP, #OFF_FP_DEX_PC_PTR] + sub \tmp, rPC, \tmp + asr \tmp, #1 + str \tmp, [rFP, #OFF_FP_DEX_PC] +.endm + +/* + * Fetch the next instruction from rPC into rINST. Does not advance rPC. + */ +.macro FETCH_INST + ldrh rINST, [rPC] +.endm + +/* + * Fetch the next instruction from the specified offset. Advances rPC + * to point to the next instruction. "_count" is in 16-bit code units. + * + * Because of the limited size of immediate constants on ARM, this is only + * suitable for small forward movements (i.e. don't try to implement "goto" + * with this). + * + * This must come AFTER anything that can throw an exception, or the + * exception catch may miss. (This also implies that it must come after + * EXPORT_PC.) + */ +.macro FETCH_ADVANCE_INST count + ldrh rINST, [rPC, #((\count)*2)]! +.endm + +/* + * The operation performed here is similar to FETCH_ADVANCE_INST, except the + * src and dest registers are parameterized (not hard-wired to rPC and rINST). + */ +.macro PREFETCH_ADVANCE_INST dreg, sreg, count + ldrh \dreg, [\sreg, #((\count)*2)]! +.endm + +/* + * Similar to FETCH_ADVANCE_INST, but does not update rPC. Used to load + * rINST ahead of possible exception point. Be sure to manually advance rPC + * later. + */ +.macro PREFETCH_INST count + ldrh rINST, [rPC, #((\count)*2)] +.endm + +/* Advance rPC by some number of code units. */ +.macro ADVANCE count + add rPC, #((\count)*2) +.endm + +/* + * Fetch the next instruction from an offset specified by _reg. Updates + * rPC to point to the next instruction. "_reg" must specify the distance + * in bytes, *not* 16-bit code units, and may be a signed value. + * + * We want to write "ldrh rINST, [rPC, _reg, lsl #1]!", but some of the + * bits that hold the shift distance are used for the half/byte/sign flags. + * In some cases we can pre-double _reg for free, so we require a byte offset + * here. + */ +.macro FETCH_ADVANCE_INST_RB reg + ldrh rINST, [rPC, \reg]! +.endm + +/* + * Fetch a half-word code unit from an offset past the current PC. The + * "_count" value is in 16-bit code units. Does not advance rPC. + * + * The "_S" variant works the same but treats the value as signed. + */ +.macro FETCH reg, count + ldrh \reg, [rPC, #((\count)*2)] +.endm + +.macro FETCH_S reg, count + ldrsh \reg, [rPC, #((\count)*2)] +.endm + +/* + * Fetch one byte from an offset past the current PC. Pass in the same + * "_count" as you would for FETCH, and an additional 0/1 indicating which + * byte of the halfword you want (lo/hi). + */ +.macro FETCH_B reg, count, byte + ldrb \reg, [rPC, #((\count)*2+(\byte))] +.endm + +/* + * Put the instruction's opcode field into the specified register. + */ +.macro GET_INST_OPCODE reg + and \reg, rINST, #255 +.endm + +/* + * Put the prefetched instruction's opcode field into the specified register. + */ +.macro GET_PREFETCHED_OPCODE oreg, ireg + and \oreg, \ireg, #255 +.endm + +/* + * Begin executing the opcode in _reg. Because this only jumps within the + * interpreter, we don't have to worry about pre-ARMv5 THUMB interwork. + */ +.macro GOTO_OPCODE reg + add pc, rIBASE, \reg, lsl #${handler_size_bits} +.endm +.macro GOTO_OPCODE_BASE base,reg + add pc, \base, \reg, lsl #${handler_size_bits} +.endm + +/* + * Get/set the 32-bit value from a Dalvik register. + */ +.macro GET_VREG reg, vreg + ldr \reg, [rFP, \vreg, lsl #2] +.endm +.macro SET_VREG reg, vreg + str \reg, [rFP, \vreg, lsl #2] + mov \reg, #0 + str \reg, [rREFS, \vreg, lsl #2] +.endm +.macro SET_VREG_OBJECT reg, vreg, tmpreg + str \reg, [rFP, \vreg, lsl #2] + str \reg, [rREFS, \vreg, lsl #2] +.endm +.macro SET_VREG_SHADOW reg, vreg + str \reg, [rREFS, \vreg, lsl #2] +.endm + +/* + * Clear the corresponding shadow regs for a vreg pair + */ +.macro CLEAR_SHADOW_PAIR vreg, tmp1, tmp2 + mov \tmp1, #0 + add \tmp2, \vreg, #1 + SET_VREG_SHADOW \tmp1, \vreg + SET_VREG_SHADOW \tmp1, \tmp2 +.endm + +/* + * Convert a virtual register index into an address. + */ +.macro VREG_INDEX_TO_ADDR reg, vreg + add \reg, rFP, \vreg, lsl #2 /* WARNING/FIXME: handle shadow frame vreg zero if store */ +.endm + +/* + * Refresh handler table. + */ +.macro REFRESH_IBASE + ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] +.endm + +/* + * cfi support macros. + */ +.macro ENTRY name + .arm + .type \name, #function + .hidden \name // Hide this as a global symbol, so we do not incur plt calls. + .global \name + /* Cache alignment for function entry */ + .balign 16 +\name: + .cfi_startproc + .fnstart +.endm + +.macro END name + .fnend + .cfi_endproc + .size \name, .-\name +.endm + +%def entry(): +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* + * Interpreter entry point. + */ + + .text + .align 2 + +/* + * On entry: + * r0 Thread* self/ + * r1 insns_ + * r2 ShadowFrame + * r3 JValue* result_register + * + */ + +ENTRY ExecuteMterpImpl + stmfd sp!, {r3-r10,fp,lr} @ save 10 regs, (r3 just to align 64) + .cfi_adjust_cfa_offset 40 + .cfi_rel_offset r3, 0 + .cfi_rel_offset r4, 4 + .cfi_rel_offset r5, 8 + .cfi_rel_offset r6, 12 + .cfi_rel_offset r7, 16 + .cfi_rel_offset r8, 20 + .cfi_rel_offset r9, 24 + .cfi_rel_offset r10, 28 + .cfi_rel_offset fp, 32 + .cfi_rel_offset lr, 36 + + /* Remember the return register */ + str r3, [r2, #SHADOWFRAME_RESULT_REGISTER_OFFSET] + + /* Remember the dex instruction pointer */ + str r1, [r2, #SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET] + + /* set up "named" registers */ + mov rSELF, r0 + ldr r0, [r2, #SHADOWFRAME_NUMBER_OF_VREGS_OFFSET] + add rFP, r2, #SHADOWFRAME_VREGS_OFFSET @ point to vregs. + VREG_INDEX_TO_ADDR rREFS, r0 @ point to reference array in shadow frame + ldr r0, [r2, #SHADOWFRAME_DEX_PC_OFFSET] @ Get starting dex_pc. + add rPC, r1, r0, lsl #1 @ Create direct pointer to 1st dex opcode + CFI_DEFINE_DEX_PC_WITH_OFFSET(CFI_TMP, CFI_DEX, 0) + EXPORT_PC + + /* Starting ibase */ + ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] + + /* Set up for backwards branches & osr profiling */ + ldr r0, [rFP, #OFF_FP_METHOD] + add r1, rFP, #OFF_FP_SHADOWFRAME + mov r2, rSELF + bl MterpSetUpHotnessCountdown + mov rPROFILE, r0 @ Starting hotness countdown to rPROFILE + + /* start executing the instruction at rPC */ + FETCH_INST @ load rINST from rPC + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + /* NOTE: no fallthrough */ + +%def alt_stub(): +/* + * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle + * any interesting requests and then jump to the real instruction + * handler. Note that the call to MterpCheckBefore is done as a tail call. + */ + .extern MterpCheckBefore + ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. + adr lr, .L_ALT_${opcode} + sub lr, lr, #(.L_ALT_${opcode} - .L_${opcode}) @ Addr of primary handler. + mov r0, rSELF + add r1, rFP, #OFF_FP_SHADOWFRAME + mov r2, rPC + b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. + +%def fallback(): +/* Transfer stub to alternate interpreter */ + b MterpFallback + + +%def helpers(): +% op_float_to_long_helper_code() +% op_double_to_long_helper_code() + +%def footer(): +/* + * =========================================================================== + * Common subroutines and data + * =========================================================================== + */ + + .text + .align 2 + +/* + * We've detected a condition that will result in an exception, but the exception + * has not yet been thrown. Just bail out to the reference interpreter to deal with it. + * TUNING: for consistency, we may want to just go ahead and handle these here. + */ +common_errDivideByZero: + EXPORT_PC +#if MTERP_LOGGING + mov r0, rSELF + add r1, rFP, #OFF_FP_SHADOWFRAME + bl MterpLogDivideByZeroException +#endif + b MterpCommonFallback + +common_errArrayIndex: + EXPORT_PC +#if MTERP_LOGGING + mov r0, rSELF + add r1, rFP, #OFF_FP_SHADOWFRAME + bl MterpLogArrayIndexException +#endif + b MterpCommonFallback + +common_errNegativeArraySize: + EXPORT_PC +#if MTERP_LOGGING + mov r0, rSELF + add r1, rFP, #OFF_FP_SHADOWFRAME + bl MterpLogNegativeArraySizeException +#endif + b MterpCommonFallback + +common_errNoSuchMethod: + EXPORT_PC +#if MTERP_LOGGING + mov r0, rSELF + add r1, rFP, #OFF_FP_SHADOWFRAME + bl MterpLogNoSuchMethodException +#endif + b MterpCommonFallback + +common_errNullObject: + EXPORT_PC +#if MTERP_LOGGING + mov r0, rSELF + add r1, rFP, #OFF_FP_SHADOWFRAME + bl MterpLogNullObjectException +#endif + b MterpCommonFallback + +common_exceptionThrown: + EXPORT_PC +#if MTERP_LOGGING + mov r0, rSELF + add r1, rFP, #OFF_FP_SHADOWFRAME + bl MterpLogExceptionThrownException +#endif + b MterpCommonFallback + +MterpSuspendFallback: + EXPORT_PC +#if MTERP_LOGGING + mov r0, rSELF + add r1, rFP, #OFF_FP_SHADOWFRAME + ldr r2, [rSELF, #THREAD_FLAGS_OFFSET] + bl MterpLogSuspendFallback +#endif + b MterpCommonFallback + +/* + * If we're here, something is out of the ordinary. If there is a pending + * exception, handle it. Otherwise, roll back and retry with the reference + * interpreter. + */ +MterpPossibleException: + ldr r0, [rSELF, #THREAD_EXCEPTION_OFFSET] + cmp r0, #0 @ Exception pending? + beq MterpFallback @ If not, fall back to reference interpreter. + /* intentional fallthrough - handle pending exception. */ +/* + * On return from a runtime helper routine, we've found a pending exception. + * Can we handle it here - or need to bail out to caller? + * + */ +MterpException: + mov r0, rSELF + add r1, rFP, #OFF_FP_SHADOWFRAME + bl MterpHandleException @ (self, shadow_frame) + cmp r0, #0 + beq MterpExceptionReturn @ no local catch, back to caller. + ldr r0, [rFP, #OFF_FP_DEX_INSTRUCTIONS] + ldr r1, [rFP, #OFF_FP_DEX_PC] + ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] + add rPC, r0, r1, lsl #1 @ generate new dex_pc_ptr + /* Do we need to switch interpreters? */ + bl MterpShouldSwitchInterpreters + cmp r0, #0 + bne MterpFallback + /* resume execution at catch block */ + EXPORT_PC + FETCH_INST + GET_INST_OPCODE ip + GOTO_OPCODE ip + /* NOTE: no fallthrough */ + +/* + * Common handling for branches with support for Jit profiling. + * On entry: + * rINST <= signed offset + * rPROFILE <= signed hotness countdown (expanded to 32 bits) + * condition bits <= set to establish sign of offset (use "NoFlags" entry if not) + * + * We have quite a few different cases for branch profiling, OSR detection and + * suspend check support here. + * + * Taken backward branches: + * If profiling active, do hotness countdown and report if we hit zero. + * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. + * Is there a pending suspend request? If so, suspend. + * + * Taken forward branches and not-taken backward branches: + * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. + * + * Our most common case is expected to be a taken backward branch with active jit profiling, + * but no full OSR check and no pending suspend request. + * Next most common case is not-taken branch with no full OSR check. + * + */ +MterpCommonTakenBranchNoFlags: + cmp rINST, #0 +MterpCommonTakenBranch: + bgt .L_forward_branch @ don't add forward branches to hotness +/* + * We need to subtract 1 from positive values and we should not see 0 here, + * so we may use the result of the comparison with -1. + */ +#if JIT_CHECK_OSR != -1 +# error "JIT_CHECK_OSR must be -1." +#endif + cmp rPROFILE, #JIT_CHECK_OSR + beq .L_osr_check + subsgt rPROFILE, #1 + beq .L_add_batch @ counted down to zero - report +.L_resume_backward_branch: + ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] + REFRESH_IBASE + add r2, rINST, rINST @ r2<- byte offset + FETCH_ADVANCE_INST_RB r2 @ update rPC, load rINST + ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST + bne .L_suspend_request_pending + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +.L_suspend_request_pending: + EXPORT_PC + mov r0, rSELF + bl MterpSuspendCheck @ (self) + cmp r0, #0 + bne MterpFallback + REFRESH_IBASE @ might have changed during suspend + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +.L_no_count_backwards: + cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? + bne .L_resume_backward_branch +.L_osr_check: + mov r0, rSELF + add r1, rFP, #OFF_FP_SHADOWFRAME + mov r2, rINST + EXPORT_PC + bl MterpMaybeDoOnStackReplacement @ (self, shadow_frame, offset) + cmp r0, #0 + bne MterpOnStackReplacement + b .L_resume_backward_branch + +.L_forward_branch: + cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? + beq .L_check_osr_forward +.L_resume_forward_branch: + add r2, rINST, rINST @ r2<- byte offset + FETCH_ADVANCE_INST_RB r2 @ update rPC, load rINST + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +.L_check_osr_forward: + mov r0, rSELF + add r1, rFP, #OFF_FP_SHADOWFRAME + mov r2, rINST + EXPORT_PC + bl MterpMaybeDoOnStackReplacement @ (self, shadow_frame, offset) + cmp r0, #0 + bne MterpOnStackReplacement + b .L_resume_forward_branch + +.L_add_batch: + add r1, rFP, #OFF_FP_SHADOWFRAME + strh rPROFILE, [r1, #SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET] + ldr r0, [rFP, #OFF_FP_METHOD] + mov r2, rSELF + bl MterpAddHotnessBatch @ (method, shadow_frame, self) + mov rPROFILE, r0 @ restore new hotness countdown to rPROFILE + b .L_no_count_backwards + +/* + * Entered from the conditional branch handlers when OSR check request active on + * not-taken path. All Dalvik not-taken conditional branch offsets are 2. + */ +.L_check_not_taken_osr: + mov r0, rSELF + add r1, rFP, #OFF_FP_SHADOWFRAME + mov r2, #2 + EXPORT_PC + bl MterpMaybeDoOnStackReplacement @ (self, shadow_frame, offset) + cmp r0, #0 + bne MterpOnStackReplacement + FETCH_ADVANCE_INST 2 + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +/* + * On-stack replacement has happened, and now we've returned from the compiled method. + */ +MterpOnStackReplacement: +#if MTERP_LOGGING + mov r0, rSELF + add r1, rFP, #OFF_FP_SHADOWFRAME + mov r2, rINST + bl MterpLogOSR +#endif + mov r0, #1 @ Signal normal return + b MterpDone + +/* + * Bail out to reference interpreter. + */ +MterpFallback: + EXPORT_PC +#if MTERP_LOGGING + mov r0, rSELF + add r1, rFP, #OFF_FP_SHADOWFRAME + bl MterpLogFallback +#endif +MterpCommonFallback: + mov r0, #0 @ signal retry with reference interpreter. + b MterpDone + +/* + * We pushed some registers on the stack in ExecuteMterpImpl, then saved + * SP and LR. Here we restore SP, restore the registers, and then restore + * LR to PC. + * + * On entry: + * uint32_t* rFP (should still be live, pointer to base of vregs) + */ +MterpExceptionReturn: + mov r0, #1 @ signal return to caller. + b MterpDone +MterpReturn: + ldr r2, [rFP, #OFF_FP_RESULT_REGISTER] + str r0, [r2] + str r1, [r2, #4] + mov r0, #1 @ signal return to caller. +MterpDone: +/* + * At this point, we expect rPROFILE to be non-zero. If negative, hotness is disabled or we're + * checking for OSR. If greater than zero, we might have unreported hotness to register + * (the difference between the ending rPROFILE and the cached hotness counter). rPROFILE + * should only reach zero immediately after a hotness decrement, and is then reset to either + * a negative special state or the new non-zero countdown value. + */ + cmp rPROFILE, #0 + bgt MterpProfileActive @ if > 0, we may have some counts to report. + ldmfd sp!, {r3-r10,fp,pc} @ restore 10 regs and return + +MterpProfileActive: + mov rINST, r0 @ stash return value + /* Report cached hotness counts */ + ldr r0, [rFP, #OFF_FP_METHOD] + add r1, rFP, #OFF_FP_SHADOWFRAME + mov r2, rSELF + strh rPROFILE, [r1, #SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET] + bl MterpAddHotnessBatch @ (method, shadow_frame, self) + mov r0, rINST @ restore return value + ldmfd sp!, {r3-r10,fp,pc} @ restore 10 regs and return + + END ExecuteMterpImpl + + +%def instruction_end(): + + .type artMterpAsmInstructionEnd, #object + .hidden artMterpAsmInstructionEnd + .global artMterpAsmInstructionEnd +artMterpAsmInstructionEnd: + +%def instruction_end_alt(): + + .type artMterpAsmAltInstructionEnd, #object + .hidden artMterpAsmAltInstructionEnd + .global artMterpAsmAltInstructionEnd +artMterpAsmAltInstructionEnd: + +%def instruction_start(): + + .type artMterpAsmInstructionStart, #object + .hidden artMterpAsmInstructionStart + .global artMterpAsmInstructionStart +artMterpAsmInstructionStart = .L_op_nop + .text + +%def instruction_start_alt(): + + .type artMterpAsmAltInstructionStart, #object + .hidden artMterpAsmAltInstructionStart + .global artMterpAsmAltInstructionStart +artMterpAsmAltInstructionStart = .L_ALT_op_nop + .text diff --git a/runtime/interpreter/mterp/arm/object.S b/runtime/interpreter/mterp/arm/object.S new file mode 100644 index 0000000000000000000000000000000000000000..af1ece2ec206f3549ef87e0e7126b4e518298081 --- /dev/null +++ b/runtime/interpreter/mterp/arm/object.S @@ -0,0 +1,275 @@ +%def field(helper=""): + /* + * General field read / write (iget-* iput-* sget-* sput-*). + */ + .extern $helper + mov r0, rPC @ arg0: Instruction* inst + mov r1, rINST @ arg1: uint16_t inst_data + add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf + mov r3, rSELF @ arg3: Thread* self + PREFETCH_INST 2 @ prefetch next opcode + bl $helper + cmp r0, #0 + beq MterpPossibleException + ADVANCE 2 + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def op_check_cast(): + /* + * Check to see if a cast from one class to another is allowed. + */ + /* check-cast vAA, class@BBBB */ + EXPORT_PC + FETCH r0, 1 @ r0<- BBBB + mov r1, rINST, lsr #8 @ r1<- AA + VREG_INDEX_TO_ADDR r1, r1 @ r1<- &object + ldr r2, [rFP, #OFF_FP_METHOD] @ r2<- method + mov r3, rSELF @ r3<- self + bl MterpCheckCast @ (index, &obj, method, self) + PREFETCH_INST 2 + cmp r0, #0 + bne MterpPossibleException + ADVANCE 2 + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def op_iget(is_object="0", helper="MterpIGetU32"): +% field(helper=helper) + +%def op_iget_boolean(): +% op_iget(helper="MterpIGetU8") + +%def op_iget_boolean_quick(): +% op_iget_quick(load="ldrb") + +%def op_iget_byte(): +% op_iget(helper="MterpIGetI8") + +%def op_iget_byte_quick(): +% op_iget_quick(load="ldrsb") + +%def op_iget_char(): +% op_iget(helper="MterpIGetU16") + +%def op_iget_char_quick(): +% op_iget_quick(load="ldrh") + +%def op_iget_object(): +% op_iget(is_object="1", helper="MterpIGetObj") + +%def op_iget_object_quick(): + /* For: iget-object-quick */ + /* op vA, vB, offset@CCCC */ + mov r2, rINST, lsr #12 @ r2<- B + FETCH r1, 1 @ r1<- field byte offset + EXPORT_PC + GET_VREG r0, r2 @ r0<- object we're operating on + bl artIGetObjectFromMterp @ (obj, offset) + ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] + ubfx r2, rINST, #8, #4 @ r2<- A + PREFETCH_INST 2 + cmp r3, #0 + bne MterpPossibleException @ bail out + SET_VREG_OBJECT r0, r2 @ fp[A]<- r0 + ADVANCE 2 @ advance rPC + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def op_iget_quick(load="ldr"): + /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ + /* op vA, vB, offset@CCCC */ + mov r2, rINST, lsr #12 @ r2<- B + FETCH r1, 1 @ r1<- field byte offset + GET_VREG r3, r2 @ r3<- object we're operating on + ubfx r2, rINST, #8, #4 @ r2<- A + cmp r3, #0 @ check object for null + beq common_errNullObject @ object was null + $load r0, [r3, r1] @ r0<- obj.field + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + SET_VREG r0, r2 @ fp[A]<- r0 + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def op_iget_short(): +% op_iget(helper="MterpIGetI16") + +%def op_iget_short_quick(): +% op_iget_quick(load="ldrsh") + +%def op_iget_wide(): +% op_iget(helper="MterpIGetU64") + +%def op_iget_wide_quick(): + /* iget-wide-quick vA, vB, offset@CCCC */ + mov r2, rINST, lsr #12 @ r2<- B + FETCH ip, 1 @ ip<- field byte offset + GET_VREG r3, r2 @ r3<- object we're operating on + ubfx r2, rINST, #8, #4 @ r2<- A + cmp r3, #0 @ check object for null + beq common_errNullObject @ object was null + ldrd r0, [r3, ip] @ r0<- obj.field (64 bits, aligned) + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + VREG_INDEX_TO_ADDR r3, r2 @ r3<- &fp[A] + CLEAR_SHADOW_PAIR r2, ip, lr @ Zero out the shadow regs + GET_INST_OPCODE ip @ extract opcode from rINST + stmia r3, {r0-r1} @ fp[A]<- r0/r1 + GOTO_OPCODE ip @ jump to next instruction + +%def op_instance_of(): + /* + * Check to see if an object reference is an instance of a class. + * + * Most common situation is a non-null object, being compared against + * an already-resolved class. + */ + /* instance-of vA, vB, class@CCCC */ + EXPORT_PC + FETCH r0, 1 @ r0<- CCCC + mov r1, rINST, lsr #12 @ r1<- B + VREG_INDEX_TO_ADDR r1, r1 @ r1<- &object + ldr r2, [rFP, #OFF_FP_METHOD] @ r2<- method + mov r3, rSELF @ r3<- self + bl MterpInstanceOf @ (index, &obj, method, self) + ldr r1, [rSELF, #THREAD_EXCEPTION_OFFSET] + ubfx r9, rINST, #8, #4 @ r9<- A + PREFETCH_INST 2 + cmp r1, #0 @ exception pending? + bne MterpException + ADVANCE 2 @ advance rPC + SET_VREG r0, r9 @ vA<- r0 + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def op_iput(is_object="0", helper="MterpIPutU32"): +% field(helper=helper) + +%def op_iput_boolean(): +% op_iput(helper="MterpIPutU8") + +%def op_iput_boolean_quick(): +% op_iput_quick(store="strb") + +%def op_iput_byte(): +% op_iput(helper="MterpIPutI8") + +%def op_iput_byte_quick(): +% op_iput_quick(store="strb") + +%def op_iput_char(): +% op_iput(helper="MterpIPutU16") + +%def op_iput_char_quick(): +% op_iput_quick(store="strh") + +%def op_iput_object(): +% op_iput(is_object="1", helper="MterpIPutObj") + +%def op_iput_object_quick(): + EXPORT_PC + add r0, rFP, #OFF_FP_SHADOWFRAME + mov r1, rPC + mov r2, rINST + bl MterpIputObjectQuick + cmp r0, #0 + beq MterpException + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def op_iput_quick(store="str"): + /* For: iput-quick, iput-object-quick */ + /* op vA, vB, offset@CCCC */ + mov r2, rINST, lsr #12 @ r2<- B + FETCH r1, 1 @ r1<- field byte offset + GET_VREG r3, r2 @ r3<- fp[B], the object pointer + ubfx r2, rINST, #8, #4 @ r2<- A + cmp r3, #0 @ check object for null + beq common_errNullObject @ object was null + GET_VREG r0, r2 @ r0<- fp[A] + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + $store r0, [r3, r1] @ obj.field<- r0 + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def op_iput_short(): +% op_iput(helper="MterpIPutI16") + +%def op_iput_short_quick(): +% op_iput_quick(store="strh") + +%def op_iput_wide(): +% op_iput(helper="MterpIPutU64") + +%def op_iput_wide_quick(): + /* iput-wide-quick vA, vB, offset@CCCC */ + mov r2, rINST, lsr #12 @ r2<- B + FETCH r3, 1 @ r3<- field byte offset + GET_VREG r2, r2 @ r2<- fp[B], the object pointer + ubfx r0, rINST, #8, #4 @ r0<- A + cmp r2, #0 @ check object for null + beq common_errNullObject @ object was null + VREG_INDEX_TO_ADDR r0, r0 @ r0<- &fp[A] + ldmia r0, {r0-r1} @ r0/r1<- fp[A]/fp[A+1] + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + strd r0, [r2, r3] @ obj.field<- r0/r1 + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def op_new_instance(): + /* + * Create a new instance of a class. + */ + /* new-instance vAA, class@BBBB */ + EXPORT_PC + add r0, rFP, #OFF_FP_SHADOWFRAME + mov r1, rSELF + mov r2, rINST + bl MterpNewInstance @ (shadow_frame, self, inst_data) + cmp r0, #0 + beq MterpPossibleException + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def op_sget(is_object="0", helper="MterpSGetU32"): +% field(helper=helper) + +%def op_sget_boolean(): +% op_sget(helper="MterpSGetU8") + +%def op_sget_byte(): +% op_sget(helper="MterpSGetI8") + +%def op_sget_char(): +% op_sget(helper="MterpSGetU16") + +%def op_sget_object(): +% op_sget(is_object="1", helper="MterpSGetObj") + +%def op_sget_short(): +% op_sget(helper="MterpSGetI16") + +%def op_sget_wide(): +% op_sget(helper="MterpSGetU64") + +%def op_sput(is_object="0", helper="MterpSPutU32"): +% field(helper=helper) + +%def op_sput_boolean(): +% op_sput(helper="MterpSPutU8") + +%def op_sput_byte(): +% op_sput(helper="MterpSPutI8") + +%def op_sput_char(): +% op_sput(helper="MterpSPutU16") + +%def op_sput_object(): +% op_sput(is_object="1", helper="MterpSPutObj") + +%def op_sput_short(): +% op_sput(helper="MterpSPutI16") + +%def op_sput_wide(): +% op_sput(helper="MterpSPutU64") diff --git a/runtime/interpreter/mterp/arm/op_add_double.S b/runtime/interpreter/mterp/arm/op_add_double.S deleted file mode 100644 index 9332bf2005fb815e435fe5bdb718c0f91d82327d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_add_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/fbinopWide.S" {"instr":"faddd d2, d0, d1"} diff --git a/runtime/interpreter/mterp/arm/op_add_double_2addr.S b/runtime/interpreter/mterp/arm/op_add_double_2addr.S deleted file mode 100644 index 3242c53f656b72e5d3c688fe5cef8fbc6f1b5d53..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_add_double_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/fbinopWide2addr.S" {"instr":"faddd d2, d0, d1"} diff --git a/runtime/interpreter/mterp/arm/op_add_float.S b/runtime/interpreter/mterp/arm/op_add_float.S deleted file mode 100644 index afb7967eb7a17967e720dc18bda4b80151557ea8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_add_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/fbinop.S" {"instr":"fadds s2, s0, s1"} diff --git a/runtime/interpreter/mterp/arm/op_add_float_2addr.S b/runtime/interpreter/mterp/arm/op_add_float_2addr.S deleted file mode 100644 index 0067b6a010dd08a5a9d000e2f328d13a0aaa36fe..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_add_float_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/fbinop2addr.S" {"instr":"fadds s2, s0, s1"} diff --git a/runtime/interpreter/mterp/arm/op_add_int.S b/runtime/interpreter/mterp/arm/op_add_int.S deleted file mode 100644 index 1dcae7eab31e861a28f31fa01a950992a5d44432..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_add_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/binop.S" {"instr":"add r0, r0, r1"} diff --git a/runtime/interpreter/mterp/arm/op_add_int_2addr.S b/runtime/interpreter/mterp/arm/op_add_int_2addr.S deleted file mode 100644 index 9ea98f1928aa13e69acf0adbd717557a1cdb7649..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_add_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/binop2addr.S" {"instr":"add r0, r0, r1"} diff --git a/runtime/interpreter/mterp/arm/op_add_int_lit16.S b/runtime/interpreter/mterp/arm/op_add_int_lit16.S deleted file mode 100644 index 5763ab849bbcf88a447db5615668fc297d193c86..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_add_int_lit16.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/binopLit16.S" {"instr":"add r0, r0, r1"} diff --git a/runtime/interpreter/mterp/arm/op_add_int_lit8.S b/runtime/interpreter/mterp/arm/op_add_int_lit8.S deleted file mode 100644 index 035510d062c3803e8f0828631f0065133a1ce06a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_add_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/binopLit8.S" {"extract":"", "instr":"add r0, r0, r3, asr #8"} diff --git a/runtime/interpreter/mterp/arm/op_add_long.S b/runtime/interpreter/mterp/arm/op_add_long.S deleted file mode 100644 index 093223e755a4951d81c6c8e64bf7a7b53385a7c0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_add_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/binopWide.S" {"preinstr":"adds r0, r0, r2", "instr":"adc r1, r1, r3"} diff --git a/runtime/interpreter/mterp/arm/op_add_long_2addr.S b/runtime/interpreter/mterp/arm/op_add_long_2addr.S deleted file mode 100644 index c11e0aff44905d1d4952b831085251cd3809ed82..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_add_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/binopWide2addr.S" {"preinstr":"adds r0, r0, r2", "instr":"adc r1, r1, r3"} diff --git a/runtime/interpreter/mterp/arm/op_aget.S b/runtime/interpreter/mterp/arm/op_aget.S deleted file mode 100644 index 11f7079c3fbb24326c632887d440cd407dba20ac..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_aget.S +++ /dev/null @@ -1,29 +0,0 @@ -%default { "load":"ldr", "shift":"2", "data_offset":"MIRROR_INT_ARRAY_DATA_OFFSET" } - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B r2, 1, 0 @ r2<- BB - mov r9, rINST, lsr #8 @ r9<- AA - FETCH_B r3, 1, 1 @ r3<- CC - GET_VREG r0, r2 @ r0<- vBB (array object) - GET_VREG r1, r3 @ r1<- vCC (requested index) - cmp r0, #0 @ null array object? - beq common_errNullObject @ yes, bail - ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length - add r0, r0, r1, lsl #$shift @ r0<- arrayObj + index*width - cmp r1, r3 @ compare unsigned index, length - bcs common_errArrayIndex @ index >= length, bail - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - $load r2, [r0, #$data_offset] @ r2<- vBB[vCC] - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r2, r9 @ vAA<- r2 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_aget_boolean.S b/runtime/interpreter/mterp/arm/op_aget_boolean.S deleted file mode 100644 index 8f678dc14f02f647402800a15785bf5f85726970..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_aget_boolean.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_aget.S" { "load":"ldrb", "shift":"0", "data_offset":"MIRROR_BOOLEAN_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/arm/op_aget_byte.S b/runtime/interpreter/mterp/arm/op_aget_byte.S deleted file mode 100644 index a30465068880cac7be29e5844ecba74672731f9a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_aget_byte.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_aget.S" { "load":"ldrsb", "shift":"0", "data_offset":"MIRROR_BYTE_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/arm/op_aget_char.S b/runtime/interpreter/mterp/arm/op_aget_char.S deleted file mode 100644 index 490830620e4102582b2242d1b8845c116fc89e8a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_aget_char.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_aget.S" { "load":"ldrh", "shift":"1", "data_offset":"MIRROR_CHAR_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/arm/op_aget_object.S b/runtime/interpreter/mterp/arm/op_aget_object.S deleted file mode 100644 index 4e0aab5d13ca6dc2ac4da8d1d06102b3b602deab..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_aget_object.S +++ /dev/null @@ -1,21 +0,0 @@ - /* - * Array object get. vAA <- vBB[vCC]. - * - * for: aget-object - */ - /* op vAA, vBB, vCC */ - FETCH_B r2, 1, 0 @ r2<- BB - mov r9, rINST, lsr #8 @ r9<- AA - FETCH_B r3, 1, 1 @ r3<- CC - EXPORT_PC - GET_VREG r0, r2 @ r0<- vBB (array object) - GET_VREG r1, r3 @ r1<- vCC (requested index) - bl artAGetObjectFromMterp @ (array, index) - ldr r1, [rSELF, #THREAD_EXCEPTION_OFFSET] - PREFETCH_INST 2 - cmp r1, #0 - bne MterpException - SET_VREG_OBJECT r0, r9 - ADVANCE 2 - GET_INST_OPCODE ip - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_aget_short.S b/runtime/interpreter/mterp/arm/op_aget_short.S deleted file mode 100644 index b71e659a4a4a2354d142af2c566a48e2fda230df..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_aget_short.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_aget.S" { "load":"ldrsh", "shift":"1", "data_offset":"MIRROR_SHORT_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/arm/op_aget_wide.S b/runtime/interpreter/mterp/arm/op_aget_wide.S deleted file mode 100644 index 66ec950531286bdf163a7b96616a4998640ec30d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_aget_wide.S +++ /dev/null @@ -1,25 +0,0 @@ - /* - * Array get, 64 bits. vAA <- vBB[vCC]. - * - * Arrays of long/double are 64-bit aligned, so it's okay to use LDRD. - */ - /* aget-wide vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - GET_VREG r0, r2 @ r0<- vBB (array object) - GET_VREG r1, r3 @ r1<- vCC (requested index) - cmp r0, #0 @ null array object? - beq common_errNullObject @ yes, bail - ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length - add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width - cmp r1, r3 @ compare unsigned index, length - bcs common_errArrayIndex @ index >= length, bail - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs - ldrd r2, [r0, #MIRROR_WIDE_ARRAY_DATA_OFFSET] @ r2/r3<- vBB[vCC] - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r2-r3} @ vAA/vAA+1<- r2/r3 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_and_int.S b/runtime/interpreter/mterp/arm/op_and_int.S deleted file mode 100644 index 7c16d376be0d8eb4f98f73d37cdc12f28272ea42..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_and_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/binop.S" {"instr":"and r0, r0, r1"} diff --git a/runtime/interpreter/mterp/arm/op_and_int_2addr.S b/runtime/interpreter/mterp/arm/op_and_int_2addr.S deleted file mode 100644 index 0fbab0286340cf72a0cea13db3d7e98b08f67948..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_and_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/binop2addr.S" {"instr":"and r0, r0, r1"} diff --git a/runtime/interpreter/mterp/arm/op_and_int_lit16.S b/runtime/interpreter/mterp/arm/op_and_int_lit16.S deleted file mode 100644 index 541e9b781492b841a4c220b05992ca0119f4f7f9..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_and_int_lit16.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/binopLit16.S" {"instr":"and r0, r0, r1"} diff --git a/runtime/interpreter/mterp/arm/op_and_int_lit8.S b/runtime/interpreter/mterp/arm/op_and_int_lit8.S deleted file mode 100644 index af746b5447cd0a9686fe1e2f347b742ff7898b0b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_and_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/binopLit8.S" {"extract":"", "instr":"and r0, r0, r3, asr #8"} diff --git a/runtime/interpreter/mterp/arm/op_and_long.S b/runtime/interpreter/mterp/arm/op_and_long.S deleted file mode 100644 index 4ad5158da711354b703e49e39e6e60b03edee871..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_and_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/binopWide.S" {"preinstr":"and r0, r0, r2", "instr":"and r1, r1, r3"} diff --git a/runtime/interpreter/mterp/arm/op_and_long_2addr.S b/runtime/interpreter/mterp/arm/op_and_long_2addr.S deleted file mode 100644 index e23ea447ba433e975411ba525fb82a20d2b8a51c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_and_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/binopWide2addr.S" {"preinstr":"and r0, r0, r2", "instr":"and r1, r1, r3"} diff --git a/runtime/interpreter/mterp/arm/op_aput.S b/runtime/interpreter/mterp/arm/op_aput.S deleted file mode 100644 index a511fa59e02a86e53d0912116b8047fa46e7945a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_aput.S +++ /dev/null @@ -1,29 +0,0 @@ -%default { "store":"str", "shift":"2", "data_offset":"MIRROR_INT_ARRAY_DATA_OFFSET" } - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B r2, 1, 0 @ r2<- BB - mov r9, rINST, lsr #8 @ r9<- AA - FETCH_B r3, 1, 1 @ r3<- CC - GET_VREG r0, r2 @ r0<- vBB (array object) - GET_VREG r1, r3 @ r1<- vCC (requested index) - cmp r0, #0 @ null array object? - beq common_errNullObject @ yes, bail - ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length - add r0, r0, r1, lsl #$shift @ r0<- arrayObj + index*width - cmp r1, r3 @ compare unsigned index, length - bcs common_errArrayIndex @ index >= length, bail - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - GET_VREG r2, r9 @ r2<- vAA - GET_INST_OPCODE ip @ extract opcode from rINST - $store r2, [r0, #$data_offset] @ vBB[vCC]<- r2 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_aput_boolean.S b/runtime/interpreter/mterp/arm/op_aput_boolean.S deleted file mode 100644 index e86663f19988034fd4fcbc1bb8964a01c7cf3efc..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_aput_boolean.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_aput.S" { "store":"strb", "shift":"0", "data_offset":"MIRROR_BOOLEAN_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/arm/op_aput_byte.S b/runtime/interpreter/mterp/arm/op_aput_byte.S deleted file mode 100644 index 83694b788d82521c1a28f286ed57deff844a9b25..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_aput_byte.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_aput.S" { "store":"strb", "shift":"0", "data_offset":"MIRROR_BYTE_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/arm/op_aput_char.S b/runtime/interpreter/mterp/arm/op_aput_char.S deleted file mode 100644 index 3551cace334aab72f3aedd8de14bfdac4bae435d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_aput_char.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_aput.S" { "store":"strh", "shift":"1", "data_offset":"MIRROR_CHAR_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/arm/op_aput_object.S b/runtime/interpreter/mterp/arm/op_aput_object.S deleted file mode 100644 index c5399163e313aa5a146aee7984ea93c4a5881ab7..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_aput_object.S +++ /dev/null @@ -1,14 +0,0 @@ - /* - * Store an object into an array. vBB[vCC] <- vAA. - */ - /* op vAA, vBB, vCC */ - EXPORT_PC - add r0, rFP, #OFF_FP_SHADOWFRAME - mov r1, rPC - mov r2, rINST - bl MterpAputObject - cmp r0, #0 - beq MterpPossibleException - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_aput_short.S b/runtime/interpreter/mterp/arm/op_aput_short.S deleted file mode 100644 index 0a0590ec369fd525bef8ce7ea5926410484aaa14..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_aput_short.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_aput.S" { "store":"strh", "shift":"1", "data_offset":"MIRROR_SHORT_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/arm/op_aput_wide.S b/runtime/interpreter/mterp/arm/op_aput_wide.S deleted file mode 100644 index 005750752f8dfbf3f62bc9cfa89fae58e1c166c6..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_aput_wide.S +++ /dev/null @@ -1,24 +0,0 @@ - /* - * Array put, 64 bits. vBB[vCC] <- vAA. - * - * Arrays of long/double are 64-bit aligned, so it's okay to use STRD. - */ - /* aput-wide vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - GET_VREG r0, r2 @ r0<- vBB (array object) - GET_VREG r1, r3 @ r1<- vCC (requested index) - cmp r0, #0 @ null array object? - beq common_errNullObject @ yes, bail - ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length - add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width - cmp r1, r3 @ compare unsigned index, length - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] - bcs common_errArrayIndex @ index >= length, bail - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - ldmia r9, {r2-r3} @ r2/r3<- vAA/vAA+1 - GET_INST_OPCODE ip @ extract opcode from rINST - strd r2, [r0, #MIRROR_WIDE_ARRAY_DATA_OFFSET] @ r2/r3<- vBB[vCC] - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_array_length.S b/runtime/interpreter/mterp/arm/op_array_length.S deleted file mode 100644 index 43b1682a9d9599c3bae35964a311e749eb318543..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_array_length.S +++ /dev/null @@ -1,13 +0,0 @@ - /* - * Return the length of an array. - */ - mov r1, rINST, lsr #12 @ r1<- B - ubfx r2, rINST, #8, #4 @ r2<- A - GET_VREG r0, r1 @ r0<- vB (object ref) - cmp r0, #0 @ is object null? - beq common_errNullObject @ yup, fail - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- array length - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r3, r2 @ vB<- length - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_check_cast.S b/runtime/interpreter/mterp/arm/op_check_cast.S deleted file mode 100644 index 24eba45a692dcbd2df04391c364e68ff7d8ccfec..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_check_cast.S +++ /dev/null @@ -1,17 +0,0 @@ - /* - * Check to see if a cast from one class to another is allowed. - */ - /* check-cast vAA, class@BBBB */ - EXPORT_PC - FETCH r0, 1 @ r0<- BBBB - mov r1, rINST, lsr #8 @ r1<- AA - VREG_INDEX_TO_ADDR r1, r1 @ r1<- &object - ldr r2, [rFP, #OFF_FP_METHOD] @ r2<- method - mov r3, rSELF @ r3<- self - bl MterpCheckCast @ (index, &obj, method, self) - PREFETCH_INST 2 - cmp r0, #0 - bne MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_cmp_long.S b/runtime/interpreter/mterp/arm/op_cmp_long.S deleted file mode 100644 index 6626ff0f492c3a0f7628812ee33f7521a99c526c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_cmp_long.S +++ /dev/null @@ -1,23 +0,0 @@ - /* - * Compare two 64-bit values. Puts 0, 1, or -1 into the destination - * register based on the results of the comparison. - */ - /* cmp-long vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] - ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 - ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 - cmp r0, r2 - sbcs ip, r1, r3 @ Sets correct CCs for checking LT (but not EQ/NE) - mov ip, #0 - mvnlt ip, #0 @ -1 - cmpeq r0, r2 @ For correct EQ/NE, we may need to repeat the first CMP - orrne ip, #1 - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - SET_VREG ip, r9 @ vAA<- ip - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_cmpg_double.S b/runtime/interpreter/mterp/arm/op_cmpg_double.S deleted file mode 100644 index 602a4b1bfd62931d9ad73c138f689f32f838d857..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_cmpg_double.S +++ /dev/null @@ -1,34 +0,0 @@ - /* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * int compare(x, y) { - * if (x == y) { - * return 0; - * } else if (x < y) { - * return -1; - * } else if (x > y) { - * return 1; - * } else { - * return 1; - * } - * } - */ - /* op vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC - fldd d0, [r2] @ d0<- vBB - fldd d1, [r3] @ d1<- vCC - vcmpe.f64 d0, d1 @ compare (vBB, vCC) - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - mov r0, #1 @ r0<- 1 (default) - GET_INST_OPCODE ip @ extract opcode from rINST - fmstat @ export status flags - mvnmi r0, #0 @ (less than) r1<- -1 - moveq r0, #0 @ (equal) r1<- 0 - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_cmpg_float.S b/runtime/interpreter/mterp/arm/op_cmpg_float.S deleted file mode 100644 index 965091f82d0db1327d9c88da0b56d9d28314102d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_cmpg_float.S +++ /dev/null @@ -1,34 +0,0 @@ - /* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * int compare(x, y) { - * if (x == y) { - * return 0; - * } else if (x < y) { - * return -1; - * } else if (x > y) { - * return 1; - * } else { - * return 1; - * } - * } - */ - /* op vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC - flds s0, [r2] @ s0<- vBB - flds s1, [r3] @ s1<- vCC - vcmpe.f32 s0, s1 @ compare (vBB, vCC) - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - mov r0, #1 @ r0<- 1 (default) - GET_INST_OPCODE ip @ extract opcode from rINST - fmstat @ export status flags - mvnmi r0, #0 @ (less than) r1<- -1 - moveq r0, #0 @ (equal) r1<- 0 - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_cmpl_double.S b/runtime/interpreter/mterp/arm/op_cmpl_double.S deleted file mode 100644 index 8a5e509ee8aa1bc5565772e5e50f5519ff477b5e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_cmpl_double.S +++ /dev/null @@ -1,34 +0,0 @@ - /* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * int compare(x, y) { - * if (x == y) { - * return 0; - * } else if (x > y) { - * return 1; - * } else if (x < y) { - * return -1; - * } else { - * return -1; - * } - * } - */ - /* op vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC - fldd d0, [r2] @ d0<- vBB - fldd d1, [r3] @ d1<- vCC - vcmpe.f64 d0, d1 @ compare (vBB, vCC) - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - mvn r0, #0 @ r0<- -1 (default) - GET_INST_OPCODE ip @ extract opcode from rINST - fmstat @ export status flags - movgt r0, #1 @ (greater than) r1<- 1 - moveq r0, #0 @ (equal) r1<- 0 - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_cmpl_float.S b/runtime/interpreter/mterp/arm/op_cmpl_float.S deleted file mode 100644 index 9df0c2c17199daa9c09e1cf2c0d5ce5b41b7b0bc..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_cmpl_float.S +++ /dev/null @@ -1,34 +0,0 @@ - /* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * int compare(x, y) { - * if (x == y) { - * return 0; - * } else if (x > y) { - * return 1; - * } else if (x < y) { - * return -1; - * } else { - * return -1; - * } - * } - */ - /* op vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC - flds s0, [r2] @ s0<- vBB - flds s1, [r3] @ s1<- vCC - vcmpe.f32 s0, s1 @ compare (vBB, vCC) - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - mvn r0, #0 @ r0<- -1 (default) - GET_INST_OPCODE ip @ extract opcode from rINST - fmstat @ export status flags - movgt r0, #1 @ (greater than) r1<- 1 - moveq r0, #0 @ (equal) r1<- 0 - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_const.S b/runtime/interpreter/mterp/arm/op_const.S deleted file mode 100644 index 39890a085a8443c742e248404e10c3e65526b6d4..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_const.S +++ /dev/null @@ -1,9 +0,0 @@ - /* const vAA, #+BBBBbbbb */ - mov r3, rINST, lsr #8 @ r3<- AA - FETCH r0, 1 @ r0<- bbbb (low) - FETCH r1, 2 @ r1<- BBBB (high) - FETCH_ADVANCE_INST 3 @ advance rPC, load rINST - orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r3 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_const_16.S b/runtime/interpreter/mterp/arm/op_const_16.S deleted file mode 100644 index a30cf3a0dbb310f7b37d35d92f4759cac97bf9aa..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_const_16.S +++ /dev/null @@ -1,7 +0,0 @@ - /* const/16 vAA, #+BBBB */ - FETCH_S r0, 1 @ r0<- ssssBBBB (sign-extended) - mov r3, rINST, lsr #8 @ r3<- AA - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - SET_VREG r0, r3 @ vAA<- r0 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_const_4.S b/runtime/interpreter/mterp/arm/op_const_4.S deleted file mode 100644 index c97b0e91f52f705810cc61087716b2f262dabb6f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_const_4.S +++ /dev/null @@ -1,7 +0,0 @@ - /* const/4 vA, #+B */ - sbfx r1, rINST, #12, #4 @ r1<- sssssssB (sign-extended) - ubfx r0, rINST, #8, #4 @ r0<- A - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - GET_INST_OPCODE ip @ ip<- opcode from rINST - SET_VREG r1, r0 @ fp[A]<- r1 - GOTO_OPCODE ip @ execute next instruction diff --git a/runtime/interpreter/mterp/arm/op_const_class.S b/runtime/interpreter/mterp/arm/op_const_class.S deleted file mode 100644 index ff5c98c7432937caec67f5e6b065c06141ab91b8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_const_class.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/const.S" { "helper":"MterpConstClass" } diff --git a/runtime/interpreter/mterp/arm/op_const_high16.S b/runtime/interpreter/mterp/arm/op_const_high16.S deleted file mode 100644 index 536276d52d76ce971d125bdee373543678c047be..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_const_high16.S +++ /dev/null @@ -1,8 +0,0 @@ - /* const/high16 vAA, #+BBBB0000 */ - FETCH r0, 1 @ r0<- 0000BBBB (zero-extended) - mov r3, rINST, lsr #8 @ r3<- AA - mov r0, r0, lsl #16 @ r0<- BBBB0000 - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - SET_VREG r0, r3 @ vAA<- r0 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_const_method_handle.S b/runtime/interpreter/mterp/arm/op_const_method_handle.S deleted file mode 100644 index 71f05501e7e952cf591f13406352a6edbb5acc90..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_const_method_handle.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/const.S" { "helper":"MterpConstMethodHandle" } diff --git a/runtime/interpreter/mterp/arm/op_const_method_type.S b/runtime/interpreter/mterp/arm/op_const_method_type.S deleted file mode 100644 index 2cccdafef4966cf199bc3f1ed2ee62da40bc4e71..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_const_method_type.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/const.S" { "helper":"MterpConstMethodType" } diff --git a/runtime/interpreter/mterp/arm/op_const_string.S b/runtime/interpreter/mterp/arm/op_const_string.S deleted file mode 100644 index 75ec34ffb4dc6970e37da53963e05de7ecd3d850..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_const_string.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/const.S" { "helper":"MterpConstString" } diff --git a/runtime/interpreter/mterp/arm/op_const_string_jumbo.S b/runtime/interpreter/mterp/arm/op_const_string_jumbo.S deleted file mode 100644 index 1255c0768d1b9796f6ea23ada9601a43dffaf21d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_const_string_jumbo.S +++ /dev/null @@ -1,15 +0,0 @@ - /* const/string vAA, String@BBBBBBBB */ - EXPORT_PC - FETCH r0, 1 @ r0<- bbbb (low) - FETCH r2, 2 @ r2<- BBBB (high) - mov r1, rINST, lsr #8 @ r1<- AA - orr r0, r0, r2, lsl #16 @ r1<- BBBBbbbb - add r2, rFP, #OFF_FP_SHADOWFRAME - mov r3, rSELF - bl MterpConstString @ (index, tgt_reg, shadow_frame, self) - PREFETCH_INST 3 @ advance rPC - cmp r0, #0 @ fail? - bne MterpPossibleException @ let reference interpreter deal with it. - ADVANCE 3 @ advance rPC - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_const_wide.S b/runtime/interpreter/mterp/arm/op_const_wide.S deleted file mode 100644 index 8310a4c129e5db089264e07489aabfc2ce31c286..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_const_wide.S +++ /dev/null @@ -1,14 +0,0 @@ - /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ - FETCH r0, 1 @ r0<- bbbb (low) - FETCH r1, 2 @ r1<- BBBB (low middle) - FETCH r2, 3 @ r2<- hhhh (high middle) - orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb (low word) - FETCH r3, 4 @ r3<- HHHH (high) - mov r9, rINST, lsr #8 @ r9<- AA - orr r1, r2, r3, lsl #16 @ r1<- HHHHhhhh (high word) - CLEAR_SHADOW_PAIR r9, r2, r3 @ Zero out the shadow regs - FETCH_ADVANCE_INST 5 @ advance rPC, load rINST - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vAA<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_const_wide_16.S b/runtime/interpreter/mterp/arm/op_const_wide_16.S deleted file mode 100644 index 28abb512f02e256dbe93e3108dd725a128e6da22..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_const_wide_16.S +++ /dev/null @@ -1,10 +0,0 @@ - /* const-wide/16 vAA, #+BBBB */ - FETCH_S r0, 1 @ r0<- ssssBBBB (sign-extended) - mov r3, rINST, lsr #8 @ r3<- AA - mov r1, r0, asr #31 @ r1<- ssssssss - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - CLEAR_SHADOW_PAIR r3, r2, lr @ Zero out the shadow regs - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[AA] - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r3, {r0-r1} @ vAA<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_const_wide_32.S b/runtime/interpreter/mterp/arm/op_const_wide_32.S deleted file mode 100644 index c10bb0461ac428a71e083f6e9d24f3f3ebeb0aa6..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_const_wide_32.S +++ /dev/null @@ -1,12 +0,0 @@ - /* const-wide/32 vAA, #+BBBBbbbb */ - FETCH r0, 1 @ r0<- 0000bbbb (low) - mov r3, rINST, lsr #8 @ r3<- AA - FETCH_S r2, 2 @ r2<- ssssBBBB (high) - FETCH_ADVANCE_INST 3 @ advance rPC, load rINST - orr r0, r0, r2, lsl #16 @ r0<- BBBBbbbb - CLEAR_SHADOW_PAIR r3, r2, lr @ Zero out the shadow regs - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[AA] - mov r1, r0, asr #31 @ r1<- ssssssss - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r3, {r0-r1} @ vAA<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_const_wide_high16.S b/runtime/interpreter/mterp/arm/op_const_wide_high16.S deleted file mode 100644 index d7e38ecc20670f1cd0e82d3096a7509249927938..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_const_wide_high16.S +++ /dev/null @@ -1,11 +0,0 @@ - /* const-wide/high16 vAA, #+BBBB000000000000 */ - FETCH r1, 1 @ r1<- 0000BBBB (zero-extended) - mov r3, rINST, lsr #8 @ r3<- AA - mov r0, #0 @ r0<- 00000000 - mov r1, r1, lsl #16 @ r1<- BBBB0000 - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - CLEAR_SHADOW_PAIR r3, r0, r2 @ Zero shadow regs - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[AA] - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r3, {r0-r1} @ vAA<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_div_double.S b/runtime/interpreter/mterp/arm/op_div_double.S deleted file mode 100644 index 5147550b97ecb6f848c847e5ad914b04785c2b10..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_div_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/fbinopWide.S" {"instr":"fdivd d2, d0, d1"} diff --git a/runtime/interpreter/mterp/arm/op_div_double_2addr.S b/runtime/interpreter/mterp/arm/op_div_double_2addr.S deleted file mode 100644 index b812f17ac9c37eebf04f89de090075d9091f78e8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_div_double_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/fbinopWide2addr.S" {"instr":"fdivd d2, d0, d1"} diff --git a/runtime/interpreter/mterp/arm/op_div_float.S b/runtime/interpreter/mterp/arm/op_div_float.S deleted file mode 100644 index 0f24d11e54d419f0684e15122a044dcc840f961b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_div_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/fbinop.S" {"instr":"fdivs s2, s0, s1"} diff --git a/runtime/interpreter/mterp/arm/op_div_float_2addr.S b/runtime/interpreter/mterp/arm/op_div_float_2addr.S deleted file mode 100644 index a1dbf01713eaa8212d3b12605624881ffb2c6b4a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_div_float_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/fbinop2addr.S" {"instr":"fdivs s2, s0, s1"} diff --git a/runtime/interpreter/mterp/arm/op_div_int.S b/runtime/interpreter/mterp/arm/op_div_int.S deleted file mode 100644 index 251064be0dbd3bf26d31fdc02b9bd8fe0886ea40..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_div_int.S +++ /dev/null @@ -1,30 +0,0 @@ -%default {} - /* - * Specialized 32-bit binary operation - * - * Performs "r0 = r0 div r1". The selection between sdiv or the gcc helper - * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for - * ARMv7 CPUs that have hardware division support). - * - * div-int - * - */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - GET_VREG r1, r3 @ r1<- vCC - GET_VREG r0, r2 @ r0<- vBB - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST -#ifdef __ARM_ARCH_EXT_IDIV__ - sdiv r0, r0, r1 @ r0<- op -#else - bl __aeabi_idiv @ r0<- op, r0-r3 changed -#endif - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 11-14 instructions */ diff --git a/runtime/interpreter/mterp/arm/op_div_int_2addr.S b/runtime/interpreter/mterp/arm/op_div_int_2addr.S deleted file mode 100644 index 9be4cd8b140f7268e4a12fad71d1f5500ac1f061..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_div_int_2addr.S +++ /dev/null @@ -1,29 +0,0 @@ -%default {} - /* - * Specialized 32-bit binary operation - * - * Performs "r0 = r0 div r1". The selection between sdiv or the gcc helper - * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for - * ARMv7 CPUs that have hardware division support). - * - * div-int/2addr - * - */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r1, r3 @ r1<- vB - GET_VREG r0, r9 @ r0<- vA - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - -#ifdef __ARM_ARCH_EXT_IDIV__ - sdiv r0, r0, r1 @ r0<- op -#else - bl __aeabi_idiv @ r0<- op, r0-r3 changed -#endif - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - diff --git a/runtime/interpreter/mterp/arm/op_div_int_lit16.S b/runtime/interpreter/mterp/arm/op_div_int_lit16.S deleted file mode 100644 index d9bc7d65ce4affff40445f374097b862f798b872..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_div_int_lit16.S +++ /dev/null @@ -1,28 +0,0 @@ -%default {} - /* - * Specialized 32-bit binary operation - * - * Performs "r0 = r0 div r1". The selection between sdiv or the gcc helper - * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for - * ARMv7 CPUs that have hardware division support). - * - * div-int/lit16 - * - */ - FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) - mov r2, rINST, lsr #12 @ r2<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r0, r2 @ r0<- vB - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - -#ifdef __ARM_ARCH_EXT_IDIV__ - sdiv r0, r0, r1 @ r0<- op -#else - bl __aeabi_idiv @ r0<- op, r0-r3 changed -#endif - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ diff --git a/runtime/interpreter/mterp/arm/op_div_int_lit8.S b/runtime/interpreter/mterp/arm/op_div_int_lit8.S deleted file mode 100644 index 5d2dbd3ecbd198f65fcad6a65dbae73d9b0cdb22..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_div_int_lit8.S +++ /dev/null @@ -1,29 +0,0 @@ -%default {} - /* - * Specialized 32-bit binary operation - * - * Performs "r0 = r0 div r1". The selection between sdiv or the gcc helper - * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for - * ARMv7 CPUs that have hardware division support). - * - * div-int/lit8 - * - */ - FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r3, #255 @ r2<- BB - GET_VREG r0, r2 @ r0<- vBB - movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) - @cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - -#ifdef __ARM_ARCH_EXT_IDIV__ - sdiv r0, r0, r1 @ r0<- op -#else - bl __aeabi_idiv @ r0<- op, r0-r3 changed -#endif - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-12 instructions */ diff --git a/runtime/interpreter/mterp/arm/op_div_long.S b/runtime/interpreter/mterp/arm/op_div_long.S deleted file mode 100644 index 0f21a845d4c79a2f3012950431f155d7a26429f3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_div_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/binopWide.S" {"instr":"bl __aeabi_ldivmod", "chkzero":"1"} diff --git a/runtime/interpreter/mterp/arm/op_div_long_2addr.S b/runtime/interpreter/mterp/arm/op_div_long_2addr.S deleted file mode 100644 index e172b2949606dd05db0a9c73bbdb44cafdc9c0c4..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_div_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/binopWide2addr.S" {"instr":"bl __aeabi_ldivmod", "chkzero":"1"} diff --git a/runtime/interpreter/mterp/arm/op_double_to_float.S b/runtime/interpreter/mterp/arm/op_double_to_float.S deleted file mode 100644 index 98fdfbc64ed521d6aaa231d11a1638c9daaef7da..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_double_to_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/funopNarrower.S" {"instr":"vcvt.f32.f64 s0, d0"} diff --git a/runtime/interpreter/mterp/arm/op_double_to_int.S b/runtime/interpreter/mterp/arm/op_double_to_int.S deleted file mode 100644 index aa035de63ac5ea537878649704a6f8f2773cda67..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_double_to_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/funopNarrower.S" {"instr":"ftosizd s0, d0"} diff --git a/runtime/interpreter/mterp/arm/op_double_to_long.S b/runtime/interpreter/mterp/arm/op_double_to_long.S deleted file mode 100644 index 19ff7235e03b5d246c03baf8ef3696d5988d05e7..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_double_to_long.S +++ /dev/null @@ -1,33 +0,0 @@ -%include "arm/unopWide.S" {"instr":"bl d2l_doconv"} - -%break -/* - * Convert the double in r0/r1 to a long in r0/r1. - * - * We have to clip values to long min/max per the specification. The - * expected common case is a "reasonable" value that converts directly - * to modest integer. The EABI convert function isn't doing this for us. - */ -d2l_doconv: - ubfx r2, r1, #20, #11 @ grab the exponent - movw r3, #0x43e - cmp r2, r3 @ MINLONG < x > MAXLONG? - bhs d2l_special_cases - b __aeabi_d2lz @ tail call to convert double to long -d2l_special_cases: - movw r3, #0x7ff - cmp r2, r3 - beq d2l_maybeNaN @ NaN? -d2l_notNaN: - adds r1, r1, r1 @ sign bit to carry - mov r0, #0xffffffff @ assume maxlong for lsw - mov r1, #0x7fffffff @ assume maxlong for msw - adc r0, r0, #0 - adc r1, r1, #0 @ convert maxlong to minlong if exp negative - bx lr @ return -d2l_maybeNaN: - orrs r3, r0, r1, lsl #12 - beq d2l_notNaN @ if fraction is non-zero, it's a NaN - mov r0, #0 - mov r1, #0 - bx lr @ return 0 for NaN diff --git a/runtime/interpreter/mterp/arm/op_fill_array_data.S b/runtime/interpreter/mterp/arm/op_fill_array_data.S deleted file mode 100644 index e1ca85c8661e6fbbcbe8de67d8e5a5b7085aa132..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_fill_array_data.S +++ /dev/null @@ -1,14 +0,0 @@ - /* fill-array-data vAA, +BBBBBBBB */ - EXPORT_PC - FETCH r0, 1 @ r0<- bbbb (lo) - FETCH r1, 2 @ r1<- BBBB (hi) - mov r3, rINST, lsr #8 @ r3<- AA - orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb - GET_VREG r0, r3 @ r0<- vAA (array object) - add r1, rPC, r1, lsl #1 @ r1<- PC + BBBBbbbb*2 (array data off.) - bl MterpFillArrayData @ (obj, payload) - cmp r0, #0 @ 0 means an exception is thrown - beq MterpPossibleException @ exception? - FETCH_ADVANCE_INST 3 @ advance rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_filled_new_array.S b/runtime/interpreter/mterp/arm/op_filled_new_array.S deleted file mode 100644 index 1075f0c68371df874e59ac70bec50b1dcc6cdbb5..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_filled_new_array.S +++ /dev/null @@ -1,19 +0,0 @@ -%default { "helper":"MterpFilledNewArray" } - /* - * Create a new array with elements filled from registers. - * - * for: filled-new-array, filled-new-array/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ - .extern $helper - EXPORT_PC - add r0, rFP, #OFF_FP_SHADOWFRAME - mov r1, rPC - mov r2, rSELF - bl $helper - cmp r0, #0 - beq MterpPossibleException - FETCH_ADVANCE_INST 3 @ advance rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_filled_new_array_range.S b/runtime/interpreter/mterp/arm/op_filled_new_array_range.S deleted file mode 100644 index 16567af567406c206d868cc6b9b4b9136106d1c9..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_filled_new_array_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_filled_new_array.S" { "helper":"MterpFilledNewArrayRange" } diff --git a/runtime/interpreter/mterp/arm/op_float_to_double.S b/runtime/interpreter/mterp/arm/op_float_to_double.S deleted file mode 100644 index b1e12bdc7a5db3943144acee403bf79bb882cf7a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_float_to_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/funopWider.S" {"instr":"vcvt.f64.f32 d0, s0"} diff --git a/runtime/interpreter/mterp/arm/op_float_to_int.S b/runtime/interpreter/mterp/arm/op_float_to_int.S deleted file mode 100644 index aab87167bb8729faa01525342b0d7ffc072eecf8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_float_to_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/funop.S" {"instr":"ftosizs s1, s0"} diff --git a/runtime/interpreter/mterp/arm/op_float_to_long.S b/runtime/interpreter/mterp/arm/op_float_to_long.S deleted file mode 100644 index 42bd98dbc25fdabc0a33cdfe4492dc4250800924..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_float_to_long.S +++ /dev/null @@ -1,31 +0,0 @@ -%include "arm/unopWider.S" {"instr":"bl f2l_doconv"} - -%break -/* - * Convert the float in r0 to a long in r0/r1. - * - * We have to clip values to long min/max per the specification. The - * expected common case is a "reasonable" value that converts directly - * to modest integer. The EABI convert function isn't doing this for us. - */ -f2l_doconv: - ubfx r2, r0, #23, #8 @ grab the exponent - cmp r2, #0xbe @ MININT < x > MAXINT? - bhs f2l_special_cases - b __aeabi_f2lz @ tail call to convert float to long -f2l_special_cases: - cmp r2, #0xff @ NaN or infinity? - beq f2l_maybeNaN -f2l_notNaN: - adds r0, r0, r0 @ sign bit to carry - mov r0, #0xffffffff @ assume maxlong for lsw - mov r1, #0x7fffffff @ assume maxlong for msw - adc r0, r0, #0 - adc r1, r1, #0 @ convert maxlong to minlong if exp negative - bx lr @ return -f2l_maybeNaN: - lsls r3, r0, #9 - beq f2l_notNaN @ if fraction is non-zero, it's a NaN - mov r0, #0 - mov r1, #0 - bx lr @ return 0 for NaN diff --git a/runtime/interpreter/mterp/arm/op_goto.S b/runtime/interpreter/mterp/arm/op_goto.S deleted file mode 100644 index aa42dfd843cd55f9357c3a8e5cc0d638c49aa383..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_goto.S +++ /dev/null @@ -1,9 +0,0 @@ - /* - * Unconditional branch, 8-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto +AA */ - sbfx rINST, rINST, #8, #8 @ rINST<- ssssssAA (sign-extended) - b MterpCommonTakenBranchNoFlags diff --git a/runtime/interpreter/mterp/arm/op_goto_16.S b/runtime/interpreter/mterp/arm/op_goto_16.S deleted file mode 100644 index 12a6bc07f88b617d3f04307945d31e93a6851bfd..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_goto_16.S +++ /dev/null @@ -1,9 +0,0 @@ - /* - * Unconditional branch, 16-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto/16 +AAAA */ - FETCH_S rINST, 1 @ rINST<- ssssAAAA (sign-extended) - b MterpCommonTakenBranchNoFlags diff --git a/runtime/interpreter/mterp/arm/op_goto_32.S b/runtime/interpreter/mterp/arm/op_goto_32.S deleted file mode 100644 index 7325a1c2d68071844a6204ca3bf518ab23214a18..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_goto_32.S +++ /dev/null @@ -1,16 +0,0 @@ - /* - * Unconditional branch, 32-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - * - * Unlike most opcodes, this one is allowed to branch to itself, so - * our "backward branch" test must be "<=0" instead of "<0". Because - * we need the V bit set, we'll use an adds to convert from Dalvik - * offset to byte offset. - */ - /* goto/32 +AAAAAAAA */ - FETCH r0, 1 @ r0<- aaaa (lo) - FETCH r3, 2 @ r1<- AAAA (hi) - orrs rINST, r0, r3, lsl #16 @ rINST<- AAAAaaaa - b MterpCommonTakenBranch diff --git a/runtime/interpreter/mterp/arm/op_if_eq.S b/runtime/interpreter/mterp/arm/op_if_eq.S deleted file mode 100644 index b8b6a6eec1596e3cd741b8df2f7e6e0e27c83703..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_if_eq.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/bincmp.S" { "condition":"eq" } diff --git a/runtime/interpreter/mterp/arm/op_if_eqz.S b/runtime/interpreter/mterp/arm/op_if_eqz.S deleted file mode 100644 index 7012f61c699e544fadf32da719680a669e27c194..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_if_eqz.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/zcmp.S" { "condition":"eq" } diff --git a/runtime/interpreter/mterp/arm/op_if_ge.S b/runtime/interpreter/mterp/arm/op_if_ge.S deleted file mode 100644 index eb29e63f7cb8da6256b0b819b83efdab806af390..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_if_ge.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/bincmp.S" { "condition":"ge" } diff --git a/runtime/interpreter/mterp/arm/op_if_gez.S b/runtime/interpreter/mterp/arm/op_if_gez.S deleted file mode 100644 index d9da374199bf1b2890cc86b21ccf114fc4fc9389..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_if_gez.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/zcmp.S" { "condition":"ge" } diff --git a/runtime/interpreter/mterp/arm/op_if_gt.S b/runtime/interpreter/mterp/arm/op_if_gt.S deleted file mode 100644 index a35eab8f47dc1953363f74a41806c8493c1a23d3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_if_gt.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/bincmp.S" { "condition":"gt" } diff --git a/runtime/interpreter/mterp/arm/op_if_gtz.S b/runtime/interpreter/mterp/arm/op_if_gtz.S deleted file mode 100644 index 4ef4d8ee19114d2186ed42e26265c2805f76d1b0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_if_gtz.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/zcmp.S" { "condition":"gt" } diff --git a/runtime/interpreter/mterp/arm/op_if_le.S b/runtime/interpreter/mterp/arm/op_if_le.S deleted file mode 100644 index c7c31bc089be58c447567888da51dbfb4b4fc166..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_if_le.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/bincmp.S" { "condition":"le" } diff --git a/runtime/interpreter/mterp/arm/op_if_lez.S b/runtime/interpreter/mterp/arm/op_if_lez.S deleted file mode 100644 index 9fbf6c9f02c145c1daefd3ab82c2e2e9d4d5bbe6..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_if_lez.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/zcmp.S" { "condition":"le" } diff --git a/runtime/interpreter/mterp/arm/op_if_lt.S b/runtime/interpreter/mterp/arm/op_if_lt.S deleted file mode 100644 index 9469fbb1efe9404408a5253548e9835605d41bd4..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_if_lt.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/bincmp.S" { "condition":"lt" } diff --git a/runtime/interpreter/mterp/arm/op_if_ltz.S b/runtime/interpreter/mterp/arm/op_if_ltz.S deleted file mode 100644 index a4fc1b8f0b858a38a5c8c63f3d0403c80b2cf11f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_if_ltz.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/zcmp.S" { "condition":"lt" } diff --git a/runtime/interpreter/mterp/arm/op_if_ne.S b/runtime/interpreter/mterp/arm/op_if_ne.S deleted file mode 100644 index c945331a31cd2f614eeec36cc7dedfaf90569bf9..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_if_ne.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/bincmp.S" { "condition":"ne" } diff --git a/runtime/interpreter/mterp/arm/op_if_nez.S b/runtime/interpreter/mterp/arm/op_if_nez.S deleted file mode 100644 index 2d81fda444a6e2efc6201d3a2ba097edd1b193f3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_if_nez.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/zcmp.S" { "condition":"ne" } diff --git a/runtime/interpreter/mterp/arm/op_iget.S b/runtime/interpreter/mterp/arm/op_iget.S deleted file mode 100644 index 1fa32faa9966602c3834a71676389ebb27d708f3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_iget.S +++ /dev/null @@ -1,2 +0,0 @@ -%default { "is_object":"0", "helper":"MterpIGetU32"} -%include "arm/field.S" { } diff --git a/runtime/interpreter/mterp/arm/op_iget_boolean.S b/runtime/interpreter/mterp/arm/op_iget_boolean.S deleted file mode 100644 index f23cb3aa97e8f6abf4af825791010c84d8728429..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_iget_boolean.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_iget.S" { "helper":"MterpIGetU8" } diff --git a/runtime/interpreter/mterp/arm/op_iget_boolean_quick.S b/runtime/interpreter/mterp/arm/op_iget_boolean_quick.S deleted file mode 100644 index 0ae4843595151785935812b5f23737a3e9b78d08..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_iget_boolean_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_iget_quick.S" { "load":"ldrb" } diff --git a/runtime/interpreter/mterp/arm/op_iget_byte.S b/runtime/interpreter/mterp/arm/op_iget_byte.S deleted file mode 100644 index 9c4f37c8ac8b1b4dca46e557aa645c1447eddd46..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_iget_byte.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_iget.S" { "helper":"MterpIGetI8" } diff --git a/runtime/interpreter/mterp/arm/op_iget_byte_quick.S b/runtime/interpreter/mterp/arm/op_iget_byte_quick.S deleted file mode 100644 index e1b3083404519d95b755b72833c6ecdd73608506..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_iget_byte_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_iget_quick.S" { "load":"ldrsb" } diff --git a/runtime/interpreter/mterp/arm/op_iget_char.S b/runtime/interpreter/mterp/arm/op_iget_char.S deleted file mode 100644 index 80c4227ed2fc9be6a99cb6a1e7f5a4767211ae7f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_iget_char.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_iget.S" { "helper":"MterpIGetU16" } diff --git a/runtime/interpreter/mterp/arm/op_iget_char_quick.S b/runtime/interpreter/mterp/arm/op_iget_char_quick.S deleted file mode 100644 index b44d8f14d8d27fa8aa42a6d8ae3d0667ea04ce7e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_iget_char_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_iget_quick.S" { "load":"ldrh" } diff --git a/runtime/interpreter/mterp/arm/op_iget_object.S b/runtime/interpreter/mterp/arm/op_iget_object.S deleted file mode 100644 index e30b129efe586bf16eb692e77b3b0d7c924053d3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_iget_object.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_iget.S" { "is_object":"1", "helper":"MterpIGetObj" } diff --git a/runtime/interpreter/mterp/arm/op_iget_object_quick.S b/runtime/interpreter/mterp/arm/op_iget_object_quick.S deleted file mode 100644 index 16cb1189ad3ca91a819b6e84b5dcc632e8714945..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_iget_object_quick.S +++ /dev/null @@ -1,16 +0,0 @@ - /* For: iget-object-quick */ - /* op vA, vB, offset@CCCC */ - mov r2, rINST, lsr #12 @ r2<- B - FETCH r1, 1 @ r1<- field byte offset - EXPORT_PC - GET_VREG r0, r2 @ r0<- object we're operating on - bl artIGetObjectFromMterp @ (obj, offset) - ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] - ubfx r2, rINST, #8, #4 @ r2<- A - PREFETCH_INST 2 - cmp r3, #0 - bne MterpPossibleException @ bail out - SET_VREG_OBJECT r0, r2 @ fp[A]<- r0 - ADVANCE 2 @ advance rPC - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_iget_quick.S b/runtime/interpreter/mterp/arm/op_iget_quick.S deleted file mode 100644 index 0eaf364f6b07ade23a6ac26751236a7723211ae6..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_iget_quick.S +++ /dev/null @@ -1,14 +0,0 @@ -%default { "load":"ldr" } - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset@CCCC */ - mov r2, rINST, lsr #12 @ r2<- B - FETCH r1, 1 @ r1<- field byte offset - GET_VREG r3, r2 @ r3<- object we're operating on - ubfx r2, rINST, #8, #4 @ r2<- A - cmp r3, #0 @ check object for null - beq common_errNullObject @ object was null - $load r0, [r3, r1] @ r0<- obj.field - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - SET_VREG r0, r2 @ fp[A]<- r0 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_iget_short.S b/runtime/interpreter/mterp/arm/op_iget_short.S deleted file mode 100644 index dd6bc9991c9ee34a895fd7f716b1b66a955ddf44..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_iget_short.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_iget.S" { "helper":"MterpIGetI16" } diff --git a/runtime/interpreter/mterp/arm/op_iget_short_quick.S b/runtime/interpreter/mterp/arm/op_iget_short_quick.S deleted file mode 100644 index 1831b99ac3c4241e2930fc16bc97a71f690bb673..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_iget_short_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_iget_quick.S" { "load":"ldrsh" } diff --git a/runtime/interpreter/mterp/arm/op_iget_wide.S b/runtime/interpreter/mterp/arm/op_iget_wide.S deleted file mode 100644 index ede21ebd35079ac2104ce7fb6006492036af9b0e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_iget_wide.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_iget.S" { "helper":"MterpIGetU64" } diff --git a/runtime/interpreter/mterp/arm/op_iget_wide_quick.S b/runtime/interpreter/mterp/arm/op_iget_wide_quick.S deleted file mode 100644 index 5a7177d8f5f86b385eb9e09f92c254f6ebbce5aa..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_iget_wide_quick.S +++ /dev/null @@ -1,14 +0,0 @@ - /* iget-wide-quick vA, vB, offset@CCCC */ - mov r2, rINST, lsr #12 @ r2<- B - FETCH ip, 1 @ ip<- field byte offset - GET_VREG r3, r2 @ r3<- object we're operating on - ubfx r2, rINST, #8, #4 @ r2<- A - cmp r3, #0 @ check object for null - beq common_errNullObject @ object was null - ldrd r0, [r3, ip] @ r0<- obj.field (64 bits, aligned) - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - VREG_INDEX_TO_ADDR r3, r2 @ r3<- &fp[A] - CLEAR_SHADOW_PAIR r2, ip, lr @ Zero out the shadow regs - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r3, {r0-r1} @ fp[A]<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_instance_of.S b/runtime/interpreter/mterp/arm/op_instance_of.S deleted file mode 100644 index 019929edf910da5e06d7e0159f46922466a80fd7..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_instance_of.S +++ /dev/null @@ -1,23 +0,0 @@ - /* - * Check to see if an object reference is an instance of a class. - * - * Most common situation is a non-null object, being compared against - * an already-resolved class. - */ - /* instance-of vA, vB, class@CCCC */ - EXPORT_PC - FETCH r0, 1 @ r0<- CCCC - mov r1, rINST, lsr #12 @ r1<- B - VREG_INDEX_TO_ADDR r1, r1 @ r1<- &object - ldr r2, [rFP, #OFF_FP_METHOD] @ r2<- method - mov r3, rSELF @ r3<- self - bl MterpInstanceOf @ (index, &obj, method, self) - ldr r1, [rSELF, #THREAD_EXCEPTION_OFFSET] - ubfx r9, rINST, #8, #4 @ r9<- A - PREFETCH_INST 2 - cmp r1, #0 @ exception pending? - bne MterpException - ADVANCE 2 @ advance rPC - SET_VREG r0, r9 @ vA<- r0 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_int_to_byte.S b/runtime/interpreter/mterp/arm/op_int_to_byte.S deleted file mode 100644 index 059d5c2cf5037556b740ff52f530a94b88362ca4..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_int_to_byte.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/unop.S" {"instr":"sxtb r0, r0"} diff --git a/runtime/interpreter/mterp/arm/op_int_to_char.S b/runtime/interpreter/mterp/arm/op_int_to_char.S deleted file mode 100644 index 83a0c196d642856a1ba6f6397f40fd2f7938aa3f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_int_to_char.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/unop.S" {"instr":"uxth r0, r0"} diff --git a/runtime/interpreter/mterp/arm/op_int_to_double.S b/runtime/interpreter/mterp/arm/op_int_to_double.S deleted file mode 100644 index 810c2e49bbfd4c0cc19514855ef31c84b62bdb93..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_int_to_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/funopWider.S" {"instr":"fsitod d0, s0"} diff --git a/runtime/interpreter/mterp/arm/op_int_to_float.S b/runtime/interpreter/mterp/arm/op_int_to_float.S deleted file mode 100644 index f41654c678db1305d96f9d0fd41f17ed7583963a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_int_to_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/funop.S" {"instr":"fsitos s1, s0"} diff --git a/runtime/interpreter/mterp/arm/op_int_to_long.S b/runtime/interpreter/mterp/arm/op_int_to_long.S deleted file mode 100644 index b5aed8e0565a244966f48102b38ad636fdd35177..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_int_to_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/unopWider.S" {"instr":"mov r1, r0, asr #31"} diff --git a/runtime/interpreter/mterp/arm/op_int_to_short.S b/runtime/interpreter/mterp/arm/op_int_to_short.S deleted file mode 100644 index 717bd96bd18b13149213adf1b5013710f52f7ce5..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_int_to_short.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/unop.S" {"instr":"sxth r0, r0"} diff --git a/runtime/interpreter/mterp/arm/op_invoke_custom.S b/runtime/interpreter/mterp/arm/op_invoke_custom.S deleted file mode 100644 index 2af875c9dfebc9952e72b782b734b6c0f750a768..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_invoke_custom.S +++ /dev/null @@ -1,8 +0,0 @@ -%include "arm/invoke.S" { "helper":"MterpInvokeCustom" } - /* - * Handle an invoke-custom invocation. - * - * for: invoke-custom, invoke-custom/range - */ - /* op vB, {vD, vE, vF, vG, vA}, call_site@BBBB */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, call_site@BBBB */ diff --git a/runtime/interpreter/mterp/arm/op_invoke_custom_range.S b/runtime/interpreter/mterp/arm/op_invoke_custom_range.S deleted file mode 100644 index 32575c4d45cf7669504a636cea43bcc6d93742cc..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_invoke_custom_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/invoke.S" { "helper":"MterpInvokeCustomRange" } diff --git a/runtime/interpreter/mterp/arm/op_invoke_direct.S b/runtime/interpreter/mterp/arm/op_invoke_direct.S deleted file mode 100644 index 1edf2219142bc4ed7443f79b95d45b0dc6f799c5..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_invoke_direct.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/invoke.S" { "helper":"MterpInvokeDirect" } diff --git a/runtime/interpreter/mterp/arm/op_invoke_direct_range.S b/runtime/interpreter/mterp/arm/op_invoke_direct_range.S deleted file mode 100644 index 3097b8e2c79b3c620a75287a3da9834f0002c818..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_invoke_direct_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/invoke.S" { "helper":"MterpInvokeDirectRange" } diff --git a/runtime/interpreter/mterp/arm/op_invoke_interface.S b/runtime/interpreter/mterp/arm/op_invoke_interface.S deleted file mode 100644 index f6d565b16822c73cba4b884d8763b34b012dcfc1..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_invoke_interface.S +++ /dev/null @@ -1,8 +0,0 @@ -%include "arm/invoke.S" { "helper":"MterpInvokeInterface" } - /* - * Handle an interface method call. - * - * for: invoke-interface, invoke-interface/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ diff --git a/runtime/interpreter/mterp/arm/op_invoke_interface_range.S b/runtime/interpreter/mterp/arm/op_invoke_interface_range.S deleted file mode 100644 index c8443b0cdc59e12cad99f177f046e90511e5a332..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_invoke_interface_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/invoke.S" { "helper":"MterpInvokeInterfaceRange" } diff --git a/runtime/interpreter/mterp/arm/op_invoke_polymorphic.S b/runtime/interpreter/mterp/arm/op_invoke_polymorphic.S deleted file mode 100644 index 816a7ae21761333af6b17647dd232ea929728803..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_invoke_polymorphic.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/invoke_polymorphic.S" { "helper":"MterpInvokePolymorphic" } diff --git a/runtime/interpreter/mterp/arm/op_invoke_polymorphic_range.S b/runtime/interpreter/mterp/arm/op_invoke_polymorphic_range.S deleted file mode 100644 index 2541c270e29f5663c05ea59c9f63e3a154d5704f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_invoke_polymorphic_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/invoke_polymorphic.S" { "helper":"MterpInvokePolymorphicRange" } diff --git a/runtime/interpreter/mterp/arm/op_invoke_static.S b/runtime/interpreter/mterp/arm/op_invoke_static.S deleted file mode 100644 index c3cefcff46302479b83647623cdfc701449b20b3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_invoke_static.S +++ /dev/null @@ -1,2 +0,0 @@ -%include "arm/invoke.S" { "helper":"MterpInvokeStatic" } - diff --git a/runtime/interpreter/mterp/arm/op_invoke_static_range.S b/runtime/interpreter/mterp/arm/op_invoke_static_range.S deleted file mode 100644 index dd60d7bbfad742d2dbeaf1759bd4ccf48fa92966..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_invoke_static_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/invoke.S" { "helper":"MterpInvokeStaticRange" } diff --git a/runtime/interpreter/mterp/arm/op_invoke_super.S b/runtime/interpreter/mterp/arm/op_invoke_super.S deleted file mode 100644 index 92ef2a4e3e2f685cdb756d4d0a8fd7f4e4ea8af9..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_invoke_super.S +++ /dev/null @@ -1,8 +0,0 @@ -%include "arm/invoke.S" { "helper":"MterpInvokeSuper" } - /* - * Handle a "super" method call. - * - * for: invoke-super, invoke-super/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ diff --git a/runtime/interpreter/mterp/arm/op_invoke_super_range.S b/runtime/interpreter/mterp/arm/op_invoke_super_range.S deleted file mode 100644 index 9e4fb1c9a1b78a1cf88ad2a10f6665a85c985426..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_invoke_super_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/invoke.S" { "helper":"MterpInvokeSuperRange" } diff --git a/runtime/interpreter/mterp/arm/op_invoke_virtual.S b/runtime/interpreter/mterp/arm/op_invoke_virtual.S deleted file mode 100644 index 5b893ff866e631c8d961e45edb6a2b81427374ae..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_invoke_virtual.S +++ /dev/null @@ -1,8 +0,0 @@ -%include "arm/invoke.S" { "helper":"MterpInvokeVirtual" } - /* - * Handle a virtual method call. - * - * for: invoke-virtual, invoke-virtual/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ diff --git a/runtime/interpreter/mterp/arm/op_invoke_virtual_quick.S b/runtime/interpreter/mterp/arm/op_invoke_virtual_quick.S deleted file mode 100644 index 020e8b81350e01462d8332b35a7b3ea4d965f609..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_invoke_virtual_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/invoke.S" { "helper":"MterpInvokeVirtualQuick" } diff --git a/runtime/interpreter/mterp/arm/op_invoke_virtual_range.S b/runtime/interpreter/mterp/arm/op_invoke_virtual_range.S deleted file mode 100644 index 2b42a7863a34366fd886fb8abdfaec7bcdf0b559..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_invoke_virtual_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/invoke.S" { "helper":"MterpInvokeVirtualRange" } diff --git a/runtime/interpreter/mterp/arm/op_invoke_virtual_range_quick.S b/runtime/interpreter/mterp/arm/op_invoke_virtual_range_quick.S deleted file mode 100644 index 42f2deda39052dd78ea0d9bcfce143a23d2ee5c5..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_invoke_virtual_range_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/invoke.S" { "helper":"MterpInvokeVirtualQuickRange" } diff --git a/runtime/interpreter/mterp/arm/op_iput.S b/runtime/interpreter/mterp/arm/op_iput.S deleted file mode 100644 index 6201d805f0da8609b233384d7ec53eeab47804e5..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_iput.S +++ /dev/null @@ -1,2 +0,0 @@ -%default { "is_object":"0", "helper":"MterpIPutU32" } -%include "arm/field.S" { } diff --git a/runtime/interpreter/mterp/arm/op_iput_boolean.S b/runtime/interpreter/mterp/arm/op_iput_boolean.S deleted file mode 100644 index 57edadddd73cec143a84c047de9e351fbeac24fc..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_iput_boolean.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_iput.S" { "helper":"MterpIPutU8" } diff --git a/runtime/interpreter/mterp/arm/op_iput_boolean_quick.S b/runtime/interpreter/mterp/arm/op_iput_boolean_quick.S deleted file mode 100644 index f0a2777821430bac778fa7bf279a76cc77166f98..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_iput_boolean_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_iput_quick.S" { "store":"strb" } diff --git a/runtime/interpreter/mterp/arm/op_iput_byte.S b/runtime/interpreter/mterp/arm/op_iput_byte.S deleted file mode 100644 index ab283b90fb679cd52327dde7f6278377fe22e9cc..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_iput_byte.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_iput.S" { "helper":"MterpIPutI8" } diff --git a/runtime/interpreter/mterp/arm/op_iput_byte_quick.S b/runtime/interpreter/mterp/arm/op_iput_byte_quick.S deleted file mode 100644 index f0a2777821430bac778fa7bf279a76cc77166f98..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_iput_byte_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_iput_quick.S" { "store":"strb" } diff --git a/runtime/interpreter/mterp/arm/op_iput_char.S b/runtime/interpreter/mterp/arm/op_iput_char.S deleted file mode 100644 index 0fe5d964ccc42ee5c8f3df36ad49d4087db92a12..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_iput_char.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_iput.S" { "helper":"MterpIPutU16" } diff --git a/runtime/interpreter/mterp/arm/op_iput_char_quick.S b/runtime/interpreter/mterp/arm/op_iput_char_quick.S deleted file mode 100644 index 5212fc355bf17e0d4836932682e77fc6892ca57e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_iput_char_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_iput_quick.S" { "store":"strh" } diff --git a/runtime/interpreter/mterp/arm/op_iput_object.S b/runtime/interpreter/mterp/arm/op_iput_object.S deleted file mode 100644 index 1003d10d4f74c3cf8fdd90eae643a3ed11ea7ce1..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_iput_object.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_iput.S" { "is_object":"1", "helper":"MterpIPutObj" } diff --git a/runtime/interpreter/mterp/arm/op_iput_object_quick.S b/runtime/interpreter/mterp/arm/op_iput_object_quick.S deleted file mode 100644 index 876b3daad8c98e0161e70edc5a556af387ca4183..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_iput_object_quick.S +++ /dev/null @@ -1,10 +0,0 @@ - EXPORT_PC - add r0, rFP, #OFF_FP_SHADOWFRAME - mov r1, rPC - mov r2, rINST - bl MterpIputObjectQuick - cmp r0, #0 - beq MterpException - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_iput_quick.S b/runtime/interpreter/mterp/arm/op_iput_quick.S deleted file mode 100644 index 98c8150cd65928c22987071e059fcc03451a3c12..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_iput_quick.S +++ /dev/null @@ -1,14 +0,0 @@ -%default { "store":"str" } - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - mov r2, rINST, lsr #12 @ r2<- B - FETCH r1, 1 @ r1<- field byte offset - GET_VREG r3, r2 @ r3<- fp[B], the object pointer - ubfx r2, rINST, #8, #4 @ r2<- A - cmp r3, #0 @ check object for null - beq common_errNullObject @ object was null - GET_VREG r0, r2 @ r0<- fp[A] - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - $store r0, [r3, r1] @ obj.field<- r0 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_iput_short.S b/runtime/interpreter/mterp/arm/op_iput_short.S deleted file mode 100644 index cc983630ffccc6b96623698273f98803f9bdab72..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_iput_short.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_iput.S" { "helper":"MterpIPutI16" } diff --git a/runtime/interpreter/mterp/arm/op_iput_short_quick.S b/runtime/interpreter/mterp/arm/op_iput_short_quick.S deleted file mode 100644 index 5212fc355bf17e0d4836932682e77fc6892ca57e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_iput_short_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_iput_quick.S" { "store":"strh" } diff --git a/runtime/interpreter/mterp/arm/op_iput_wide.S b/runtime/interpreter/mterp/arm/op_iput_wide.S deleted file mode 100644 index f2845ad29c4b9b7de0d3bd2a9e8ec5843a284ee7..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_iput_wide.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_iput.S" { "helper":"MterpIPutU64" } diff --git a/runtime/interpreter/mterp/arm/op_iput_wide_quick.S b/runtime/interpreter/mterp/arm/op_iput_wide_quick.S deleted file mode 100644 index 88e6ea102c36b4bee7be78bea8527c3bc2636205..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_iput_wide_quick.S +++ /dev/null @@ -1,13 +0,0 @@ - /* iput-wide-quick vA, vB, offset@CCCC */ - mov r2, rINST, lsr #12 @ r2<- B - FETCH r3, 1 @ r3<- field byte offset - GET_VREG r2, r2 @ r2<- fp[B], the object pointer - ubfx r0, rINST, #8, #4 @ r0<- A - cmp r2, #0 @ check object for null - beq common_errNullObject @ object was null - VREG_INDEX_TO_ADDR r0, r0 @ r0<- &fp[A] - ldmia r0, {r0-r1} @ r0/r1<- fp[A]/fp[A+1] - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - strd r0, [r2, r3] @ obj.field<- r0/r1 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_long_to_double.S b/runtime/interpreter/mterp/arm/op_long_to_double.S deleted file mode 100644 index cac12d48d45386c0f2d44c4330562a8dc4823ff6..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_long_to_double.S +++ /dev/null @@ -1,27 +0,0 @@ -%default {} - /* - * Specialised 64-bit floating point operation. - * - * Note: The result will be returned in d2. - * - * For: long-to-double - */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[A] - vldr d0, [r3] @ d0<- vAA - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - - vcvt.f64.s32 d1, s1 @ d1<- (double)(vAAh) - vcvt.f64.u32 d2, s0 @ d2<- (double)(vAAl) - vldr d3, constval$opcode - vmla.f64 d2, d1, d3 @ d2<- vAAh*2^32 + vAAl - - GET_INST_OPCODE ip @ extract opcode from rINST - vstr.64 d2, [r9] @ vAA<- d2 - GOTO_OPCODE ip @ jump to next instruction - - /* literal pool helper */ -constval${opcode}: - .8byte 0x41f0000000000000 diff --git a/runtime/interpreter/mterp/arm/op_long_to_float.S b/runtime/interpreter/mterp/arm/op_long_to_float.S deleted file mode 100644 index efa5a669135aadd5804901263b48bead06a41442..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_long_to_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/unopNarrower.S" {"instr":"bl __aeabi_l2f"} diff --git a/runtime/interpreter/mterp/arm/op_long_to_int.S b/runtime/interpreter/mterp/arm/op_long_to_int.S deleted file mode 100644 index 3e91f230b7579ae9ee54b189d998633433329f4b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_long_to_int.S +++ /dev/null @@ -1,2 +0,0 @@ -/* we ignore the high word, making this equivalent to a 32-bit reg move */ -%include "arm/op_move.S" diff --git a/runtime/interpreter/mterp/arm/op_monitor_enter.S b/runtime/interpreter/mterp/arm/op_monitor_enter.S deleted file mode 100644 index 3c34f75d9dc673a7e4e6ae75af7e54526fb13067..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_monitor_enter.S +++ /dev/null @@ -1,14 +0,0 @@ - /* - * Synchronize on an object. - */ - /* monitor-enter vAA */ - EXPORT_PC - mov r2, rINST, lsr #8 @ r2<- AA - GET_VREG r0, r2 @ r0<- vAA (object) - mov r1, rSELF @ r1<- self - bl artLockObjectFromCode - cmp r0, #0 - bne MterpException - FETCH_ADVANCE_INST 1 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_monitor_exit.S b/runtime/interpreter/mterp/arm/op_monitor_exit.S deleted file mode 100644 index fc7cef5395fb12d431b6b70b419e367453c84702..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_monitor_exit.S +++ /dev/null @@ -1,18 +0,0 @@ - /* - * Unlock an object. - * - * Exceptions that occur when unlocking a monitor need to appear as - * if they happened at the following instruction. See the Dalvik - * instruction spec. - */ - /* monitor-exit vAA */ - EXPORT_PC - mov r2, rINST, lsr #8 @ r2<- AA - GET_VREG r0, r2 @ r0<- vAA (object) - mov r1, rSELF @ r0<- self - bl artUnlockObjectFromCode @ r0<- success for unlock(self, obj) - cmp r0, #0 @ failed? - bne MterpException - FETCH_ADVANCE_INST 1 @ before throw: advance rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_move.S b/runtime/interpreter/mterp/arm/op_move.S deleted file mode 100644 index dfecc2432d44710ec0383e6537d5e0d8ead07cf2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_move.S +++ /dev/null @@ -1,14 +0,0 @@ -%default { "is_object":"0" } - /* for move, move-object, long-to-int */ - /* op vA, vB */ - mov r1, rINST, lsr #12 @ r1<- B from 15:12 - ubfx r0, rINST, #8, #4 @ r0<- A from 11:8 - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - GET_VREG r2, r1 @ r2<- fp[B] - GET_INST_OPCODE ip @ ip<- opcode from rINST - .if $is_object - SET_VREG_OBJECT r2, r0 @ fp[A]<- r2 - .else - SET_VREG r2, r0 @ fp[A]<- r2 - .endif - GOTO_OPCODE ip @ execute next instruction diff --git a/runtime/interpreter/mterp/arm/op_move_16.S b/runtime/interpreter/mterp/arm/op_move_16.S deleted file mode 100644 index 78138a238cb175f5786f3d2ec202cc40f1118848..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_move_16.S +++ /dev/null @@ -1,14 +0,0 @@ -%default { "is_object":"0" } - /* for: move/16, move-object/16 */ - /* op vAAAA, vBBBB */ - FETCH r1, 2 @ r1<- BBBB - FETCH r0, 1 @ r0<- AAAA - FETCH_ADVANCE_INST 3 @ advance rPC, load rINST - GET_VREG r2, r1 @ r2<- fp[BBBB] - GET_INST_OPCODE ip @ extract opcode from rINST - .if $is_object - SET_VREG_OBJECT r2, r0 @ fp[AAAA]<- r2 - .else - SET_VREG r2, r0 @ fp[AAAA]<- r2 - .endif - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_move_exception.S b/runtime/interpreter/mterp/arm/op_move_exception.S deleted file mode 100644 index 0242e26ee57fcf4fd63872679d11a17f426dd19b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_move_exception.S +++ /dev/null @@ -1,9 +0,0 @@ - /* move-exception vAA */ - mov r2, rINST, lsr #8 @ r2<- AA - ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] - mov r1, #0 @ r1<- 0 - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - SET_VREG_OBJECT r3, r2 @ fp[AA]<- exception obj - GET_INST_OPCODE ip @ extract opcode from rINST - str r1, [rSELF, #THREAD_EXCEPTION_OFFSET] @ clear exception - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_move_from16.S b/runtime/interpreter/mterp/arm/op_move_from16.S deleted file mode 100644 index 3e79417307856c3287fdf73a73f962542dd4f56f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_move_from16.S +++ /dev/null @@ -1,14 +0,0 @@ -%default { "is_object":"0" } - /* for: move/from16, move-object/from16 */ - /* op vAA, vBBBB */ - FETCH r1, 1 @ r1<- BBBB - mov r0, rINST, lsr #8 @ r0<- AA - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - GET_VREG r2, r1 @ r2<- fp[BBBB] - GET_INST_OPCODE ip @ extract opcode from rINST - .if $is_object - SET_VREG_OBJECT r2, r0 @ fp[AA]<- r2 - .else - SET_VREG r2, r0 @ fp[AA]<- r2 - .endif - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_move_object.S b/runtime/interpreter/mterp/arm/op_move_object.S deleted file mode 100644 index 16de57bac06e7621f0a60c1c0cee4f01da3ef95c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_move_object.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_move.S" {"is_object":"1"} diff --git a/runtime/interpreter/mterp/arm/op_move_object_16.S b/runtime/interpreter/mterp/arm/op_move_object_16.S deleted file mode 100644 index 25343006a3b7f18c72717b59bbd42700570aed23..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_move_object_16.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_move_16.S" {"is_object":"1"} diff --git a/runtime/interpreter/mterp/arm/op_move_object_from16.S b/runtime/interpreter/mterp/arm/op_move_object_from16.S deleted file mode 100644 index 9e0cf02d17e74b29d7eb375d1317595022084e30..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_move_object_from16.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_move_from16.S" {"is_object":"1"} diff --git a/runtime/interpreter/mterp/arm/op_move_result.S b/runtime/interpreter/mterp/arm/op_move_result.S deleted file mode 100644 index f2586a0769d2f33954f3118e607092afdb2babfb..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_move_result.S +++ /dev/null @@ -1,14 +0,0 @@ -%default { "is_object":"0" } - /* for: move-result, move-result-object */ - /* op vAA */ - mov r2, rINST, lsr #8 @ r2<- AA - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - ldr r0, [rFP, #OFF_FP_RESULT_REGISTER] @ get pointer to result JType. - ldr r0, [r0] @ r0 <- result.i. - GET_INST_OPCODE ip @ extract opcode from rINST - .if $is_object - SET_VREG_OBJECT r0, r2, r1 @ fp[AA]<- r0 - .else - SET_VREG r0, r2 @ fp[AA]<- r0 - .endif - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_move_result_object.S b/runtime/interpreter/mterp/arm/op_move_result_object.S deleted file mode 100644 index 643296a5dc33369673aa9ef0d2b06260bce4bed7..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_move_result_object.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_move_result.S" {"is_object":"1"} diff --git a/runtime/interpreter/mterp/arm/op_move_result_wide.S b/runtime/interpreter/mterp/arm/op_move_result_wide.S deleted file mode 100644 index 87929eaeeb0bca5439d3e3fda5cb244efc99110c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_move_result_wide.S +++ /dev/null @@ -1,10 +0,0 @@ - /* move-result-wide vAA */ - mov rINST, rINST, lsr #8 @ rINST<- AA - ldr r3, [rFP, #OFF_FP_RESULT_REGISTER] - VREG_INDEX_TO_ADDR r2, rINST @ r2<- &fp[AA] - ldmia r3, {r0-r1} @ r0/r1<- retval.j - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - stmia r2, {r0-r1} @ fp[AA]<- r0/r1 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_move_wide.S b/runtime/interpreter/mterp/arm/op_move_wide.S deleted file mode 100644 index ff353ea5d928e3f9e558182cad2e810e535cb054..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_move_wide.S +++ /dev/null @@ -1,12 +0,0 @@ - /* move-wide vA, vB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx rINST, rINST, #8, #4 @ rINST<- A - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] - VREG_INDEX_TO_ADDR r2, rINST @ r2<- &fp[A] - ldmia r3, {r0-r1} @ r0/r1<- fp[B] - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r2, {r0-r1} @ fp[A]<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_move_wide_16.S b/runtime/interpreter/mterp/arm/op_move_wide_16.S deleted file mode 100644 index 9812b66e97065113ca753325474c7a7c7cbe3686..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_move_wide_16.S +++ /dev/null @@ -1,12 +0,0 @@ - /* move-wide/16 vAAAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - FETCH r3, 2 @ r3<- BBBB - FETCH r2, 1 @ r2<- AAAA - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[BBBB] - VREG_INDEX_TO_ADDR lr, r2 @ r2<- &fp[AAAA] - ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] - FETCH_ADVANCE_INST 3 @ advance rPC, load rINST - CLEAR_SHADOW_PAIR r2, r3, ip @ Zero out the shadow regs - stmia lr, {r0-r1} @ fp[AAAA]<- r0/r1 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_move_wide_from16.S b/runtime/interpreter/mterp/arm/op_move_wide_from16.S deleted file mode 100644 index d2cc60ca9da597d140b51d0d3235a00113b952b7..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_move_wide_from16.S +++ /dev/null @@ -1,12 +0,0 @@ - /* move-wide/from16 vAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - FETCH r3, 1 @ r3<- BBBB - mov rINST, rINST, lsr #8 @ rINST<- AA - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[BBBB] - VREG_INDEX_TO_ADDR r2, rINST @ r2<- &fp[AA] - ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r2, {r0-r1} @ fp[AA]<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_mul_double.S b/runtime/interpreter/mterp/arm/op_mul_double.S deleted file mode 100644 index 530e85a39ed9c1e7fa6e857963d789d1be40688b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_mul_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/fbinopWide.S" {"instr":"fmuld d2, d0, d1"} diff --git a/runtime/interpreter/mterp/arm/op_mul_double_2addr.S b/runtime/interpreter/mterp/arm/op_mul_double_2addr.S deleted file mode 100644 index da1abc6e0413a15d996a01558f9aa038afc25ea2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_mul_double_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/fbinopWide2addr.S" {"instr":"fmuld d2, d0, d1"} diff --git a/runtime/interpreter/mterp/arm/op_mul_float.S b/runtime/interpreter/mterp/arm/op_mul_float.S deleted file mode 100644 index 6a72e6f42cfe07c411869ab09d0e6a7f580da349..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_mul_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/fbinop.S" {"instr":"fmuls s2, s0, s1"} diff --git a/runtime/interpreter/mterp/arm/op_mul_float_2addr.S b/runtime/interpreter/mterp/arm/op_mul_float_2addr.S deleted file mode 100644 index edb51016664ec713b5173234f0f3762de9e7b1de..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_mul_float_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/fbinop2addr.S" {"instr":"fmuls s2, s0, s1"} diff --git a/runtime/interpreter/mterp/arm/op_mul_int.S b/runtime/interpreter/mterp/arm/op_mul_int.S deleted file mode 100644 index d6151d4d4557cbf46d81cc0ddad29a375bd4fa22..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_mul_int.S +++ /dev/null @@ -1,2 +0,0 @@ -/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ -%include "arm/binop.S" {"instr":"mul r0, r1, r0"} diff --git a/runtime/interpreter/mterp/arm/op_mul_int_2addr.S b/runtime/interpreter/mterp/arm/op_mul_int_2addr.S deleted file mode 100644 index 66a797d9fef8ac40e182dc1270e2a74340307104..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_mul_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ -%include "arm/binop2addr.S" {"instr":"mul r0, r1, r0"} diff --git a/runtime/interpreter/mterp/arm/op_mul_int_lit16.S b/runtime/interpreter/mterp/arm/op_mul_int_lit16.S deleted file mode 100644 index 4e40c438f74e6e7c4b6a3aa04fe3a1aded12f5b7..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_mul_int_lit16.S +++ /dev/null @@ -1,2 +0,0 @@ -/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ -%include "arm/binopLit16.S" {"instr":"mul r0, r1, r0"} diff --git a/runtime/interpreter/mterp/arm/op_mul_int_lit8.S b/runtime/interpreter/mterp/arm/op_mul_int_lit8.S deleted file mode 100644 index dbafae9d24d0c2ebe9a4b1c24a346cc5d7160609..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_mul_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ -%include "arm/binopLit8.S" {"instr":"mul r0, r1, r0"} diff --git a/runtime/interpreter/mterp/arm/op_mul_long.S b/runtime/interpreter/mterp/arm/op_mul_long.S deleted file mode 100644 index 4f55280871a4a8b65ec267b4985efe1c75c8c789..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_mul_long.S +++ /dev/null @@ -1,37 +0,0 @@ - /* - * Signed 64-bit integer multiply. - * - * Consider WXxYZ (r1r0 x r3r2) with a long multiply: - * WX - * x YZ - * -------- - * ZW ZX - * YW YX - * - * The low word of the result holds ZX, the high word holds - * (ZW+YX) + (the high overflow from ZX). YW doesn't matter because - * it doesn't fit in the low 64 bits. - * - * Unlike most ARM math operations, multiply instructions have - * restrictions on using the same register more than once (Rd and Rm - * cannot be the same). - */ - /* mul-long vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] - ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 - ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 - mul ip, r2, r1 @ ip<- ZxW - umull r1, lr, r2, r0 @ r1/lr <- ZxX - mla r2, r0, r3, ip @ r2<- YxX + (ZxW) - mov r0, rINST, lsr #8 @ r0<- AA - add r2, r2, lr @ r2<- lr + low(ZxW + (YxX)) - CLEAR_SHADOW_PAIR r0, lr, ip @ Zero out the shadow regs - VREG_INDEX_TO_ADDR r0, r0 @ r0<- &fp[AA] - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r0, {r1-r2 } @ vAA/vAA+1<- r1/r2 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_mul_long_2addr.S b/runtime/interpreter/mterp/arm/op_mul_long_2addr.S deleted file mode 100644 index 4c1f058260887ee3e9753060e8b8421a4a0dabd3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_mul_long_2addr.S +++ /dev/null @@ -1,24 +0,0 @@ - /* - * Signed 64-bit integer multiply, "/2addr" version. - * - * See op_mul_long for an explanation. - * - * We get a little tight on registers, so to avoid looking up &fp[A] - * again we stuff it into rINST. - */ - /* mul-long/2addr vA, vB */ - mov r1, rINST, lsr #12 @ r1<- B - ubfx r9, rINST, #8, #4 @ r9<- A - VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] - VREG_INDEX_TO_ADDR rINST, r9 @ rINST<- &fp[A] - ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 - ldmia rINST, {r0-r1} @ r0/r1<- vAA/vAA+1 - mul ip, r2, r1 @ ip<- ZxW - umull r1, lr, r2, r0 @ r1/lr <- ZxX - mla r2, r0, r3, ip @ r2<- YxX + (ZxW) - mov r0, rINST @ r0<- &fp[A] (free up rINST) - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - add r2, r2, lr @ r2<- r2 + low(ZxW + (YxX)) - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r0, {r1-r2} @ vAA/vAA+1<- r1/r2 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_neg_double.S b/runtime/interpreter/mterp/arm/op_neg_double.S deleted file mode 100644 index 33e609cbfabd4a1e268236459176ea951d05ed56..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_neg_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/unopWide.S" {"instr":"add r1, r1, #0x80000000"} diff --git a/runtime/interpreter/mterp/arm/op_neg_float.S b/runtime/interpreter/mterp/arm/op_neg_float.S deleted file mode 100644 index 993583fc867f539209658ca14bf25c80603b89e1..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_neg_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/unop.S" {"instr":"add r0, r0, #0x80000000"} diff --git a/runtime/interpreter/mterp/arm/op_neg_int.S b/runtime/interpreter/mterp/arm/op_neg_int.S deleted file mode 100644 index ec0b253745d7b1738e4257e80b3d5b619ba12b64..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_neg_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/unop.S" {"instr":"rsb r0, r0, #0"} diff --git a/runtime/interpreter/mterp/arm/op_neg_long.S b/runtime/interpreter/mterp/arm/op_neg_long.S deleted file mode 100644 index dab2eb492ec95009787685c233b1d2a20d792595..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_neg_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/unopWide.S" {"preinstr":"rsbs r0, r0, #0", "instr":"rsc r1, r1, #0"} diff --git a/runtime/interpreter/mterp/arm/op_new_array.S b/runtime/interpreter/mterp/arm/op_new_array.S deleted file mode 100644 index 8bb792c2173cd18e9a96f80c85ba0583b003a829..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_new_array.S +++ /dev/null @@ -1,19 +0,0 @@ - /* - * Allocate an array of objects, specified with the array class - * and a count. - * - * The verifier guarantees that this is an array class, so we don't - * check for it here. - */ - /* new-array vA, vB, class@CCCC */ - EXPORT_PC - add r0, rFP, #OFF_FP_SHADOWFRAME - mov r1, rPC - mov r2, rINST - mov r3, rSELF - bl MterpNewArray - cmp r0, #0 - beq MterpPossibleException - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_new_instance.S b/runtime/interpreter/mterp/arm/op_new_instance.S deleted file mode 100644 index 95d4be8762249c1a0110e933fbfbeb4f81f55f85..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_new_instance.S +++ /dev/null @@ -1,14 +0,0 @@ - /* - * Create a new instance of a class. - */ - /* new-instance vAA, class@BBBB */ - EXPORT_PC - add r0, rFP, #OFF_FP_SHADOWFRAME - mov r1, rSELF - mov r2, rINST - bl MterpNewInstance @ (shadow_frame, self, inst_data) - cmp r0, #0 - beq MterpPossibleException - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_nop.S b/runtime/interpreter/mterp/arm/op_nop.S deleted file mode 100644 index af0f88f7e37c6234be3a1f37ddfbf9bb0e39d200..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_nop.S +++ /dev/null @@ -1,3 +0,0 @@ - FETCH_ADVANCE_INST 1 @ advance to next instr, load rINST - GET_INST_OPCODE ip @ ip<- opcode from rINST - GOTO_OPCODE ip @ execute it diff --git a/runtime/interpreter/mterp/arm/op_not_int.S b/runtime/interpreter/mterp/arm/op_not_int.S deleted file mode 100644 index 816485ae6ac4779fe29cfba13c450401bf836bc8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_not_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/unop.S" {"instr":"mvn r0, r0"} diff --git a/runtime/interpreter/mterp/arm/op_not_long.S b/runtime/interpreter/mterp/arm/op_not_long.S deleted file mode 100644 index 49a59056d51466d50988fd03d7213ec8aa60d845..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_not_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/unopWide.S" {"preinstr":"mvn r0, r0", "instr":"mvn r1, r1"} diff --git a/runtime/interpreter/mterp/arm/op_or_int.S b/runtime/interpreter/mterp/arm/op_or_int.S deleted file mode 100644 index b046e8d8d83a60cadc4c3a411cb97fe5242ba91d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_or_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/binop.S" {"instr":"orr r0, r0, r1"} diff --git a/runtime/interpreter/mterp/arm/op_or_int_2addr.S b/runtime/interpreter/mterp/arm/op_or_int_2addr.S deleted file mode 100644 index 493c59f285968c3df694caf933b16e02bbeb9922..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_or_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/binop2addr.S" {"instr":"orr r0, r0, r1"} diff --git a/runtime/interpreter/mterp/arm/op_or_int_lit16.S b/runtime/interpreter/mterp/arm/op_or_int_lit16.S deleted file mode 100644 index 0a01db80521dd4d2bb6c3d27386df19d2bd645c9..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_or_int_lit16.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/binopLit16.S" {"instr":"orr r0, r0, r1"} diff --git a/runtime/interpreter/mterp/arm/op_or_int_lit8.S b/runtime/interpreter/mterp/arm/op_or_int_lit8.S deleted file mode 100644 index 9882bfcf5ed427c01ab9072ced1d3b92c0653e3a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_or_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/binopLit8.S" {"extract":"", "instr":"orr r0, r0, r3, asr #8"} diff --git a/runtime/interpreter/mterp/arm/op_or_long.S b/runtime/interpreter/mterp/arm/op_or_long.S deleted file mode 100644 index 048c45ccb52f5b5e69f06e38db08a89e1e5dced4..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_or_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/binopWide.S" {"preinstr":"orr r0, r0, r2", "instr":"orr r1, r1, r3"} diff --git a/runtime/interpreter/mterp/arm/op_or_long_2addr.S b/runtime/interpreter/mterp/arm/op_or_long_2addr.S deleted file mode 100644 index 93953461ba2f41c35c18a177827f36c50fbeed55..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_or_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/binopWide2addr.S" {"preinstr":"orr r0, r0, r2", "instr":"orr r1, r1, r3"} diff --git a/runtime/interpreter/mterp/arm/op_packed_switch.S b/runtime/interpreter/mterp/arm/op_packed_switch.S deleted file mode 100644 index 412c58f1bcdc8831059cfb8105d5404087c90b07..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_packed_switch.S +++ /dev/null @@ -1,20 +0,0 @@ -%default { "func":"MterpDoPackedSwitch" } - /* - * Handle a packed-switch or sparse-switch instruction. In both cases - * we decode it and hand it off to a helper function. - * - * We don't really expect backward branches in a switch statement, but - * they're perfectly legal, so we check for them here. - * - * for: packed-switch, sparse-switch - */ - /* op vAA, +BBBB */ - FETCH r0, 1 @ r0<- bbbb (lo) - FETCH r1, 2 @ r1<- BBBB (hi) - mov r3, rINST, lsr #8 @ r3<- AA - orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb - GET_VREG r1, r3 @ r1<- vAA - add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 - bl $func @ r0<- code-unit branch offset - movs rINST, r0 - b MterpCommonTakenBranch diff --git a/runtime/interpreter/mterp/arm/op_rem_double.S b/runtime/interpreter/mterp/arm/op_rem_double.S deleted file mode 100644 index b539221eacee3b1959d570e2433dc431ea8d7c12..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_rem_double.S +++ /dev/null @@ -1,2 +0,0 @@ -/* EABI doesn't define a double remainder function, but libm does */ -%include "arm/binopWide.S" {"instr":"bl fmod"} diff --git a/runtime/interpreter/mterp/arm/op_rem_double_2addr.S b/runtime/interpreter/mterp/arm/op_rem_double_2addr.S deleted file mode 100644 index 372ef1dfe66b133b05985cf861af7c56c608bb30..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_rem_double_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -/* EABI doesn't define a double remainder function, but libm does */ -%include "arm/binopWide2addr.S" {"instr":"bl fmod"} diff --git a/runtime/interpreter/mterp/arm/op_rem_float.S b/runtime/interpreter/mterp/arm/op_rem_float.S deleted file mode 100644 index 7bd10deafed979b0ca275f860a8ff6e9cba86bec..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_rem_float.S +++ /dev/null @@ -1,2 +0,0 @@ -/* EABI doesn't define a float remainder function, but libm does */ -%include "arm/binop.S" {"instr":"bl fmodf"} diff --git a/runtime/interpreter/mterp/arm/op_rem_float_2addr.S b/runtime/interpreter/mterp/arm/op_rem_float_2addr.S deleted file mode 100644 index 93c5faef68704529984570160226b1904b5fa919..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_rem_float_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -/* EABI doesn't define a float remainder function, but libm does */ -%include "arm/binop2addr.S" {"instr":"bl fmodf"} diff --git a/runtime/interpreter/mterp/arm/op_rem_int.S b/runtime/interpreter/mterp/arm/op_rem_int.S deleted file mode 100644 index ff6257340f66f8139c333e6e8c6660a51e88267d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_rem_int.S +++ /dev/null @@ -1,33 +0,0 @@ -%default {} - /* - * Specialized 32-bit binary operation - * - * Performs "r1 = r0 rem r1". The selection between sdiv block or the gcc helper - * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for - * ARMv7 CPUs that have hardware division support). - * - * NOTE: idivmod returns quotient in r0 and remainder in r1 - * - * rem-int - * - */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - GET_VREG r1, r3 @ r1<- vCC - GET_VREG r0, r2 @ r0<- vBB - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST -#ifdef __ARM_ARCH_EXT_IDIV__ - sdiv r2, r0, r1 - mls r1, r1, r2, r0 @ r1<- op, r0-r2 changed -#else - bl __aeabi_idivmod @ r1<- op, r0-r3 changed -#endif - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r1, r9 @ vAA<- r1 - GOTO_OPCODE ip @ jump to next instruction - /* 11-14 instructions */ diff --git a/runtime/interpreter/mterp/arm/op_rem_int_2addr.S b/runtime/interpreter/mterp/arm/op_rem_int_2addr.S deleted file mode 100644 index ba5751a2aec32bb6292ab34b496c5e8bc9043547..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_rem_int_2addr.S +++ /dev/null @@ -1,32 +0,0 @@ -%default {} - /* - * Specialized 32-bit binary operation - * - * Performs "r1 = r0 rem r1". The selection between sdiv block or the gcc helper - * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for - * ARMv7 CPUs that have hardware division support). - * - * NOTE: idivmod returns quotient in r0 and remainder in r1 - * - * rem-int/2addr - * - */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r1, r3 @ r1<- vB - GET_VREG r0, r9 @ r0<- vA - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - -#ifdef __ARM_ARCH_EXT_IDIV__ - sdiv r2, r0, r1 - mls r1, r1, r2, r0 @ r1<- op -#else - bl __aeabi_idivmod @ r1<- op, r0-r3 changed -#endif - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r1, r9 @ vAA<- r1 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - diff --git a/runtime/interpreter/mterp/arm/op_rem_int_lit16.S b/runtime/interpreter/mterp/arm/op_rem_int_lit16.S deleted file mode 100644 index 4edb187f50dbed49a4cda998862f425791fe9a91..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_rem_int_lit16.S +++ /dev/null @@ -1,31 +0,0 @@ -%default {} - /* - * Specialized 32-bit binary operation - * - * Performs "r1 = r0 rem r1". The selection between sdiv block or the gcc helper - * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for - * ARMv7 CPUs that have hardware division support). - * - * NOTE: idivmod returns quotient in r0 and remainder in r1 - * - * rem-int/lit16 - * - */ - FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) - mov r2, rINST, lsr #12 @ r2<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r0, r2 @ r0<- vB - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - -#ifdef __ARM_ARCH_EXT_IDIV__ - sdiv r2, r0, r1 - mls r1, r1, r2, r0 @ r1<- op -#else - bl __aeabi_idivmod @ r1<- op, r0-r3 changed -#endif - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r1, r9 @ vAA<- r1 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ diff --git a/runtime/interpreter/mterp/arm/op_rem_int_lit8.S b/runtime/interpreter/mterp/arm/op_rem_int_lit8.S deleted file mode 100644 index 3888361bc5a0c04b83fbc9d17bd4e295ffdeafca..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_rem_int_lit8.S +++ /dev/null @@ -1,32 +0,0 @@ -%default {} - /* - * Specialized 32-bit binary operation - * - * Performs "r1 = r0 rem r1". The selection between sdiv block or the gcc helper - * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for - * ARMv7 CPUs that have hardware division support). - * - * NOTE: idivmod returns quotient in r0 and remainder in r1 - * - * rem-int/lit8 - * - */ - FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r3, #255 @ r2<- BB - GET_VREG r0, r2 @ r0<- vBB - movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) - @cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - -#ifdef __ARM_ARCH_EXT_IDIV__ - sdiv r2, r0, r1 - mls r1, r1, r2, r0 @ r1<- op -#else - bl __aeabi_idivmod @ r1<- op, r0-r3 changed -#endif - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r1, r9 @ vAA<- r1 - GOTO_OPCODE ip @ jump to next instruction - /* 10-12 instructions */ diff --git a/runtime/interpreter/mterp/arm/op_rem_long.S b/runtime/interpreter/mterp/arm/op_rem_long.S deleted file mode 100644 index b2b1c2418783dbe3749159f55d9b324381ba1e79..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_rem_long.S +++ /dev/null @@ -1,2 +0,0 @@ -/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ -%include "arm/binopWide.S" {"instr":"bl __aeabi_ldivmod", "result0":"r2", "result1":"r3", "chkzero":"1"} diff --git a/runtime/interpreter/mterp/arm/op_rem_long_2addr.S b/runtime/interpreter/mterp/arm/op_rem_long_2addr.S deleted file mode 100644 index f87d493a9126ab83f3a94ccf97946824f2783014..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_rem_long_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ -%include "arm/binopWide2addr.S" {"instr":"bl __aeabi_ldivmod", "result0":"r2", "result1":"r3", "chkzero":"1"} diff --git a/runtime/interpreter/mterp/arm/op_return.S b/runtime/interpreter/mterp/arm/op_return.S deleted file mode 100644 index f9c0f0fa1966ec0d1ccb98f5297c95419a4939ac..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_return.S +++ /dev/null @@ -1,16 +0,0 @@ - /* - * Return a 32-bit value. - * - * for: return, return-object - */ - /* op vAA */ - .extern MterpThreadFenceForConstructor - bl MterpThreadFenceForConstructor - ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] - mov r0, rSELF - ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - blne MterpSuspendCheck @ (self) - mov r2, rINST, lsr #8 @ r2<- AA - GET_VREG r0, r2 @ r0<- vAA - mov r1, #0 - b MterpReturn diff --git a/runtime/interpreter/mterp/arm/op_return_object.S b/runtime/interpreter/mterp/arm/op_return_object.S deleted file mode 100644 index c4907302c9c809aa9873b8547a6605f3e1315d8a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_return_object.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_return.S" diff --git a/runtime/interpreter/mterp/arm/op_return_void.S b/runtime/interpreter/mterp/arm/op_return_void.S deleted file mode 100644 index a91ccb31f5cec8e97ffbebd8d8b05088825b05df..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_return_void.S +++ /dev/null @@ -1,9 +0,0 @@ - .extern MterpThreadFenceForConstructor - bl MterpThreadFenceForConstructor - ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] - mov r0, rSELF - ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - blne MterpSuspendCheck @ (self) - mov r0, #0 - mov r1, #0 - b MterpReturn diff --git a/runtime/interpreter/mterp/arm/op_return_void_no_barrier.S b/runtime/interpreter/mterp/arm/op_return_void_no_barrier.S deleted file mode 100644 index b953f4c7fd1f44db39e04270ec3000a54b082757..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_return_void_no_barrier.S +++ /dev/null @@ -1,7 +0,0 @@ - ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] - mov r0, rSELF - ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - blne MterpSuspendCheck @ (self) - mov r0, #0 - mov r1, #0 - b MterpReturn diff --git a/runtime/interpreter/mterp/arm/op_return_wide.S b/runtime/interpreter/mterp/arm/op_return_wide.S deleted file mode 100644 index df582c08316dbabee0d150ffec133980e6161c0f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_return_wide.S +++ /dev/null @@ -1,14 +0,0 @@ - /* - * Return a 64-bit value. - */ - /* return-wide vAA */ - .extern MterpThreadFenceForConstructor - bl MterpThreadFenceForConstructor - ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] - mov r0, rSELF - ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - blne MterpSuspendCheck @ (self) - mov r2, rINST, lsr #8 @ r2<- AA - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[AA] - ldmia r2, {r0-r1} @ r0/r1 <- vAA/vAA+1 - b MterpReturn diff --git a/runtime/interpreter/mterp/arm/op_rsub_int.S b/runtime/interpreter/mterp/arm/op_rsub_int.S deleted file mode 100644 index 1508dd437325736a81db19fc00a4336af7a10883..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_rsub_int.S +++ /dev/null @@ -1,2 +0,0 @@ -/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ -%include "arm/binopLit16.S" {"instr":"rsb r0, r0, r1"} diff --git a/runtime/interpreter/mterp/arm/op_rsub_int_lit8.S b/runtime/interpreter/mterp/arm/op_rsub_int_lit8.S deleted file mode 100644 index dc953dcc4ad79829160ff514de731aa1ea3662ce..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_rsub_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/binopLit8.S" {"extract":"", "instr":"rsb r0, r0, r3, asr #8"} diff --git a/runtime/interpreter/mterp/arm/op_sget.S b/runtime/interpreter/mterp/arm/op_sget.S deleted file mode 100644 index b382de4c8defbc43b84cc8f386368409b1ed30ac..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_sget.S +++ /dev/null @@ -1,2 +0,0 @@ -%default { "is_object":"0", "helper":"MterpSGetU32" } -%include "arm/field.S" { } diff --git a/runtime/interpreter/mterp/arm/op_sget_boolean.S b/runtime/interpreter/mterp/arm/op_sget_boolean.S deleted file mode 100644 index df1a0246b58867a83c185d836388d3b084ca69c0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_sget_boolean.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_sget.S" {"helper":"MterpSGetU8"} diff --git a/runtime/interpreter/mterp/arm/op_sget_byte.S b/runtime/interpreter/mterp/arm/op_sget_byte.S deleted file mode 100644 index 8ad3ff0e651a43f0798da2449f039398cee956bb..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_sget_byte.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_sget.S" {"helper":"MterpSGetI8"} diff --git a/runtime/interpreter/mterp/arm/op_sget_char.S b/runtime/interpreter/mterp/arm/op_sget_char.S deleted file mode 100644 index 523951490a8acb0718de78bca44d2a3a51e53aa2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_sget_char.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_sget.S" {"helper":"MterpSGetU16"} diff --git a/runtime/interpreter/mterp/arm/op_sget_object.S b/runtime/interpreter/mterp/arm/op_sget_object.S deleted file mode 100644 index e61a5a7b2137add30d4b34e2e6282db3ad56a1fd..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_sget_object.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_sget.S" {"is_object":"1", "helper":"MterpSGetObj"} diff --git a/runtime/interpreter/mterp/arm/op_sget_short.S b/runtime/interpreter/mterp/arm/op_sget_short.S deleted file mode 100644 index 49493ebc68b2718280703128b4fe9bff4b983f07..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_sget_short.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_sget.S" {"helper":"MterpSGetI16"} diff --git a/runtime/interpreter/mterp/arm/op_sget_wide.S b/runtime/interpreter/mterp/arm/op_sget_wide.S deleted file mode 100644 index d6905df7d8e238b288b0dcab87636554f2ed8501..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_sget_wide.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_sget.S" {"helper":"MterpSGetU64"} diff --git a/runtime/interpreter/mterp/arm/op_shl_int.S b/runtime/interpreter/mterp/arm/op_shl_int.S deleted file mode 100644 index 7e4c768888c873627e51cb1fda5c500707e177bd..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_shl_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/binop.S" {"preinstr":"and r1, r1, #31", "instr":"mov r0, r0, asl r1"} diff --git a/runtime/interpreter/mterp/arm/op_shl_int_2addr.S b/runtime/interpreter/mterp/arm/op_shl_int_2addr.S deleted file mode 100644 index 4286577e19bccf35410b0ccd614d288e36a85893..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_shl_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/binop2addr.S" {"preinstr":"and r1, r1, #31", "instr":"mov r0, r0, asl r1"} diff --git a/runtime/interpreter/mterp/arm/op_shl_int_lit8.S b/runtime/interpreter/mterp/arm/op_shl_int_lit8.S deleted file mode 100644 index 60a149880f13c2a4e693741c57fe90a79178a7e2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_shl_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/binopLit8.S" {"extract":"ubfx r1, r3, #8, #5", "instr":"mov r0, r0, asl r1"} diff --git a/runtime/interpreter/mterp/arm/op_shl_long.S b/runtime/interpreter/mterp/arm/op_shl_long.S deleted file mode 100644 index 82ec6ed09f628ba6212578b35afc524a6ea654f5..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_shl_long.S +++ /dev/null @@ -1,27 +0,0 @@ - /* - * Long integer shift. This is different from the generic 32/64-bit - * binary operations because vAA/vBB are 64-bit but vCC (the shift - * distance) is 32-bit. Also, Dalvik requires us to mask off the low - * 6 bits of the shift distance. - */ - /* shl-long vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - and r3, r0, #255 @ r3<- BB - mov r0, r0, lsr #8 @ r0<- CC - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[BB] - GET_VREG r2, r0 @ r2<- vCC - ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 - CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs - and r2, r2, #63 @ r2<- r2 & 0x3f - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] - mov r1, r1, asl r2 @ r1<- r1 << r2 - rsb r3, r2, #32 @ r3<- 32 - r2 - orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) - subs ip, r2, #32 @ ip<- r2 - 32 - movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - mov r0, r0, asl r2 @ r0<- r0 << r2 - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_shl_long_2addr.S b/runtime/interpreter/mterp/arm/op_shl_long_2addr.S deleted file mode 100644 index f361a7d29c3e000163559db9fe43f1f1deeb0553..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_shl_long_2addr.S +++ /dev/null @@ -1,22 +0,0 @@ - /* - * Long integer shift, 2addr version. vA is 64-bit value/result, vB is - * 32-bit shift distance. - */ - /* shl-long/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r2, r3 @ r2<- vB - CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[A] - and r2, r2, #63 @ r2<- r2 & 0x3f - ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 - mov r1, r1, asl r2 @ r1<- r1 << r2 - rsb r3, r2, #32 @ r3<- 32 - r2 - orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) - subs ip, r2, #32 @ ip<- r2 - 32 - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) - mov r0, r0, asl r2 @ r0<- r0 << r2 - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_shr_int.S b/runtime/interpreter/mterp/arm/op_shr_int.S deleted file mode 100644 index 6317605c6d8e764618e8c78c94da925800d63185..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_shr_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/binop.S" {"preinstr":"and r1, r1, #31", "instr":"mov r0, r0, asr r1"} diff --git a/runtime/interpreter/mterp/arm/op_shr_int_2addr.S b/runtime/interpreter/mterp/arm/op_shr_int_2addr.S deleted file mode 100644 index cc8632f4bd3fb0806a47802fba8bac4dcf2b3735..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_shr_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/binop2addr.S" {"preinstr":"and r1, r1, #31", "instr":"mov r0, r0, asr r1"} diff --git a/runtime/interpreter/mterp/arm/op_shr_int_lit8.S b/runtime/interpreter/mterp/arm/op_shr_int_lit8.S deleted file mode 100644 index c2f6cb05032a11b4bc2864aa3363ccefc2b27fd4..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_shr_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/binopLit8.S" {"extract":"ubfx r1, r3, #8, #5", "instr":"mov r0, r0, asr r1"} diff --git a/runtime/interpreter/mterp/arm/op_shr_long.S b/runtime/interpreter/mterp/arm/op_shr_long.S deleted file mode 100644 index a0afe5b04047a1fec0eff8cef0182e64dd76d35b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_shr_long.S +++ /dev/null @@ -1,27 +0,0 @@ - /* - * Long integer shift. This is different from the generic 32/64-bit - * binary operations because vAA/vBB are 64-bit but vCC (the shift - * distance) is 32-bit. Also, Dalvik requires us to mask off the low - * 6 bits of the shift distance. - */ - /* shr-long vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - and r3, r0, #255 @ r3<- BB - mov r0, r0, lsr #8 @ r0<- CC - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[BB] - GET_VREG r2, r0 @ r2<- vCC - ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 - CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs - and r2, r2, #63 @ r0<- r0 & 0x3f - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] - mov r0, r0, lsr r2 @ r0<- r2 >> r2 - rsb r3, r2, #32 @ r3<- 32 - r2 - orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) - subs ip, r2, #32 @ ip<- r2 - 32 - movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - mov r1, r1, asr r2 @ r1<- r1 >> r2 - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_shr_long_2addr.S b/runtime/interpreter/mterp/arm/op_shr_long_2addr.S deleted file mode 100644 index 976110efd4140bba28ba64e9041deb2c0da3f060..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_shr_long_2addr.S +++ /dev/null @@ -1,22 +0,0 @@ - /* - * Long integer shift, 2addr version. vA is 64-bit value/result, vB is - * 32-bit shift distance. - */ - /* shr-long/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r2, r3 @ r2<- vB - CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[A] - and r2, r2, #63 @ r2<- r2 & 0x3f - ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 - mov r0, r0, lsr r2 @ r0<- r2 >> r2 - rsb r3, r2, #32 @ r3<- 32 - r2 - orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) - subs ip, r2, #32 @ ip<- r2 - 32 - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) - mov r1, r1, asr r2 @ r1<- r1 >> r2 - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_sparse_switch.S b/runtime/interpreter/mterp/arm/op_sparse_switch.S deleted file mode 100644 index 9f7a42b96eb5449031e3ce51ff5b6e5d29c0869a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_sparse_switch.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_packed_switch.S" { "func":"MterpDoSparseSwitch" } diff --git a/runtime/interpreter/mterp/arm/op_sput.S b/runtime/interpreter/mterp/arm/op_sput.S deleted file mode 100644 index 171f02444bcae60e5adce2c14f871eb3bc0b15d0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_sput.S +++ /dev/null @@ -1,2 +0,0 @@ -%default { "is_object":"0", "helper":"MterpSPutU32"} -%include "arm/field.S" { } diff --git a/runtime/interpreter/mterp/arm/op_sput_boolean.S b/runtime/interpreter/mterp/arm/op_sput_boolean.S deleted file mode 100644 index 0c37623fb6e806a0e0464c13ca69592b5c5e6330..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_sput_boolean.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_sput.S" {"helper":"MterpSPutU8"} diff --git a/runtime/interpreter/mterp/arm/op_sput_byte.S b/runtime/interpreter/mterp/arm/op_sput_byte.S deleted file mode 100644 index 8d4e7542291b9262ff7c5d58426c6debc7d7092a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_sput_byte.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_sput.S" {"helper":"MterpSPutI8"} diff --git a/runtime/interpreter/mterp/arm/op_sput_char.S b/runtime/interpreter/mterp/arm/op_sput_char.S deleted file mode 100644 index 442b56f7b1e28ed96730923c1ebf9535a0727ee1..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_sput_char.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_sput.S" {"helper":"MterpSPutU16"} diff --git a/runtime/interpreter/mterp/arm/op_sput_object.S b/runtime/interpreter/mterp/arm/op_sput_object.S deleted file mode 100644 index 8fcd52e2c4ff5f268a433a42c87f7ead040924eb..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_sput_object.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_sput.S" {"is_object":"1", "helper":"MterpSPutObj"} diff --git a/runtime/interpreter/mterp/arm/op_sput_short.S b/runtime/interpreter/mterp/arm/op_sput_short.S deleted file mode 100644 index 0eb533fe3c95ddff1955f29218056745e94503d8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_sput_short.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_sput.S" {"helper":"MterpSPutI16"} diff --git a/runtime/interpreter/mterp/arm/op_sput_wide.S b/runtime/interpreter/mterp/arm/op_sput_wide.S deleted file mode 100644 index c254f7834c85cb7f4862beeaa0c5ecd96b032634..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_sput_wide.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/op_sput.S" {"helper":"MterpSPutU64"} diff --git a/runtime/interpreter/mterp/arm/op_sub_double.S b/runtime/interpreter/mterp/arm/op_sub_double.S deleted file mode 100644 index 69bcc6736cf5ff3144af7cbcebf670a2bc078059..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_sub_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/fbinopWide.S" {"instr":"fsubd d2, d0, d1"} diff --git a/runtime/interpreter/mterp/arm/op_sub_double_2addr.S b/runtime/interpreter/mterp/arm/op_sub_double_2addr.S deleted file mode 100644 index 2ea59fe854e075e20eb607a89b30cf8ea5dc25ce..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_sub_double_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/fbinopWide2addr.S" {"instr":"fsubd d2, d0, d1"} diff --git a/runtime/interpreter/mterp/arm/op_sub_float.S b/runtime/interpreter/mterp/arm/op_sub_float.S deleted file mode 100644 index 3f17a0dfe372aae5e8ab910157f46ad8ad657dc4..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_sub_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/fbinop.S" {"instr":"fsubs s2, s0, s1"} diff --git a/runtime/interpreter/mterp/arm/op_sub_float_2addr.S b/runtime/interpreter/mterp/arm/op_sub_float_2addr.S deleted file mode 100644 index 2f4aac4ad87ac1c3b5ffe1b5f974938606b43e86..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_sub_float_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/fbinop2addr.S" {"instr":"fsubs s2, s0, s1"} diff --git a/runtime/interpreter/mterp/arm/op_sub_int.S b/runtime/interpreter/mterp/arm/op_sub_int.S deleted file mode 100644 index efb9e10035c1b28d4109174b73b144180a204537..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_sub_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/binop.S" {"instr":"sub r0, r0, r1"} diff --git a/runtime/interpreter/mterp/arm/op_sub_int_2addr.S b/runtime/interpreter/mterp/arm/op_sub_int_2addr.S deleted file mode 100644 index 4d3036b82c2666f9f6763cc9eecf6fcfb634a766..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_sub_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/binop2addr.S" {"instr":"sub r0, r0, r1"} diff --git a/runtime/interpreter/mterp/arm/op_sub_long.S b/runtime/interpreter/mterp/arm/op_sub_long.S deleted file mode 100644 index 6f1eb6ed77f981708d5289ae59f701a254602e25..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_sub_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/binopWide.S" {"preinstr":"subs r0, r0, r2", "instr":"sbc r1, r1, r3"} diff --git a/runtime/interpreter/mterp/arm/op_sub_long_2addr.S b/runtime/interpreter/mterp/arm/op_sub_long_2addr.S deleted file mode 100644 index 8e9da055257143905f0e5e25165588596cc7cc18..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_sub_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/binopWide2addr.S" {"preinstr":"subs r0, r0, r2", "instr":"sbc r1, r1, r3"} diff --git a/runtime/interpreter/mterp/arm/op_throw.S b/runtime/interpreter/mterp/arm/op_throw.S deleted file mode 100644 index be49ada424ae5377ad52cd8540e54931c4d4433d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_throw.S +++ /dev/null @@ -1,11 +0,0 @@ - /* - * Throw an exception object in the current thread. - */ - /* throw vAA */ - EXPORT_PC - mov r2, rINST, lsr #8 @ r2<- AA - GET_VREG r1, r2 @ r1<- vAA (exception object) - cmp r1, #0 @ null object? - beq common_errNullObject @ yes, throw an NPE instead - str r1, [rSELF, #THREAD_EXCEPTION_OFFSET] @ thread->exception<- obj - b MterpException diff --git a/runtime/interpreter/mterp/arm/op_unused_3e.S b/runtime/interpreter/mterp/arm/op_unused_3e.S deleted file mode 100644 index 10948dc06c75b94fe3313bfcd1fe63766427b719..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_unused_3e.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/unused.S" diff --git a/runtime/interpreter/mterp/arm/op_unused_3f.S b/runtime/interpreter/mterp/arm/op_unused_3f.S deleted file mode 100644 index 10948dc06c75b94fe3313bfcd1fe63766427b719..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_unused_3f.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/unused.S" diff --git a/runtime/interpreter/mterp/arm/op_unused_40.S b/runtime/interpreter/mterp/arm/op_unused_40.S deleted file mode 100644 index 10948dc06c75b94fe3313bfcd1fe63766427b719..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_unused_40.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/unused.S" diff --git a/runtime/interpreter/mterp/arm/op_unused_41.S b/runtime/interpreter/mterp/arm/op_unused_41.S deleted file mode 100644 index 10948dc06c75b94fe3313bfcd1fe63766427b719..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_unused_41.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/unused.S" diff --git a/runtime/interpreter/mterp/arm/op_unused_42.S b/runtime/interpreter/mterp/arm/op_unused_42.S deleted file mode 100644 index 10948dc06c75b94fe3313bfcd1fe63766427b719..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_unused_42.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/unused.S" diff --git a/runtime/interpreter/mterp/arm/op_unused_43.S b/runtime/interpreter/mterp/arm/op_unused_43.S deleted file mode 100644 index 10948dc06c75b94fe3313bfcd1fe63766427b719..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_unused_43.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/unused.S" diff --git a/runtime/interpreter/mterp/arm/op_unused_73.S b/runtime/interpreter/mterp/arm/op_unused_73.S deleted file mode 100644 index 10948dc06c75b94fe3313bfcd1fe63766427b719..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_unused_73.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/unused.S" diff --git a/runtime/interpreter/mterp/arm/op_unused_79.S b/runtime/interpreter/mterp/arm/op_unused_79.S deleted file mode 100644 index 10948dc06c75b94fe3313bfcd1fe63766427b719..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_unused_79.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/unused.S" diff --git a/runtime/interpreter/mterp/arm/op_unused_7a.S b/runtime/interpreter/mterp/arm/op_unused_7a.S deleted file mode 100644 index 10948dc06c75b94fe3313bfcd1fe63766427b719..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_unused_7a.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/unused.S" diff --git a/runtime/interpreter/mterp/arm/op_unused_f3.S b/runtime/interpreter/mterp/arm/op_unused_f3.S deleted file mode 100644 index 10948dc06c75b94fe3313bfcd1fe63766427b719..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_unused_f3.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/unused.S" diff --git a/runtime/interpreter/mterp/arm/op_unused_f4.S b/runtime/interpreter/mterp/arm/op_unused_f4.S deleted file mode 100644 index 10948dc06c75b94fe3313bfcd1fe63766427b719..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_unused_f4.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/unused.S" diff --git a/runtime/interpreter/mterp/arm/op_unused_f5.S b/runtime/interpreter/mterp/arm/op_unused_f5.S deleted file mode 100644 index 10948dc06c75b94fe3313bfcd1fe63766427b719..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_unused_f5.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/unused.S" diff --git a/runtime/interpreter/mterp/arm/op_unused_f6.S b/runtime/interpreter/mterp/arm/op_unused_f6.S deleted file mode 100644 index 10948dc06c75b94fe3313bfcd1fe63766427b719..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_unused_f6.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/unused.S" diff --git a/runtime/interpreter/mterp/arm/op_unused_f7.S b/runtime/interpreter/mterp/arm/op_unused_f7.S deleted file mode 100644 index 10948dc06c75b94fe3313bfcd1fe63766427b719..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_unused_f7.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/unused.S" diff --git a/runtime/interpreter/mterp/arm/op_unused_f8.S b/runtime/interpreter/mterp/arm/op_unused_f8.S deleted file mode 100644 index 10948dc06c75b94fe3313bfcd1fe63766427b719..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_unused_f8.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/unused.S" diff --git a/runtime/interpreter/mterp/arm/op_unused_f9.S b/runtime/interpreter/mterp/arm/op_unused_f9.S deleted file mode 100644 index 10948dc06c75b94fe3313bfcd1fe63766427b719..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_unused_f9.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/unused.S" diff --git a/runtime/interpreter/mterp/arm/op_unused_fc.S b/runtime/interpreter/mterp/arm/op_unused_fc.S deleted file mode 100644 index 10948dc06c75b94fe3313bfcd1fe63766427b719..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_unused_fc.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/unused.S" diff --git a/runtime/interpreter/mterp/arm/op_unused_fd.S b/runtime/interpreter/mterp/arm/op_unused_fd.S deleted file mode 100644 index 10948dc06c75b94fe3313bfcd1fe63766427b719..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_unused_fd.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/unused.S" diff --git a/runtime/interpreter/mterp/arm/op_ushr_int.S b/runtime/interpreter/mterp/arm/op_ushr_int.S deleted file mode 100644 index a74361b64c91d53e67e16dc5bc76e3a4131af4f1..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_ushr_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/binop.S" {"preinstr":"and r1, r1, #31", "instr":"mov r0, r0, lsr r1"} diff --git a/runtime/interpreter/mterp/arm/op_ushr_int_2addr.S b/runtime/interpreter/mterp/arm/op_ushr_int_2addr.S deleted file mode 100644 index f2d1d13881533d9b447ceed56ca2bd1476a05209..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_ushr_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/binop2addr.S" {"preinstr":"and r1, r1, #31", "instr":"mov r0, r0, lsr r1"} diff --git a/runtime/interpreter/mterp/arm/op_ushr_int_lit8.S b/runtime/interpreter/mterp/arm/op_ushr_int_lit8.S deleted file mode 100644 index 5554eb06f72cf56f274dc9c612efade7124fa4df..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_ushr_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/binopLit8.S" {"extract":"ubfx r1, r3, #8, #5", "instr":"mov r0, r0, lsr r1"} diff --git a/runtime/interpreter/mterp/arm/op_ushr_long.S b/runtime/interpreter/mterp/arm/op_ushr_long.S deleted file mode 100644 index c817bc9fb958f9e27f60656980e7d2b16a971773..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_ushr_long.S +++ /dev/null @@ -1,27 +0,0 @@ - /* - * Long integer shift. This is different from the generic 32/64-bit - * binary operations because vAA/vBB are 64-bit but vCC (the shift - * distance) is 32-bit. Also, Dalvik requires us to mask off the low - * 6 bits of the shift distance. - */ - /* ushr-long vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - and r3, r0, #255 @ r3<- BB - mov r0, r0, lsr #8 @ r0<- CC - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[BB] - GET_VREG r2, r0 @ r2<- vCC - ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 - CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs - and r2, r2, #63 @ r0<- r0 & 0x3f - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] - mov r0, r0, lsr r2 @ r0<- r2 >> r2 - rsb r3, r2, #32 @ r3<- 32 - r2 - orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) - subs ip, r2, #32 @ ip<- r2 - 32 - movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - mov r1, r1, lsr r2 @ r1<- r1 >>> r2 - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_ushr_long_2addr.S b/runtime/interpreter/mterp/arm/op_ushr_long_2addr.S deleted file mode 100644 index 2735f8733aafba2f3b9aba192e28c655ffb4eade..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_ushr_long_2addr.S +++ /dev/null @@ -1,22 +0,0 @@ - /* - * Long integer shift, 2addr version. vA is 64-bit value/result, vB is - * 32-bit shift distance. - */ - /* ushr-long/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r2, r3 @ r2<- vB - CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[A] - and r2, r2, #63 @ r2<- r2 & 0x3f - ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 - mov r0, r0, lsr r2 @ r0<- r2 >> r2 - rsb r3, r2, #32 @ r3<- 32 - r2 - orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) - subs ip, r2, #32 @ ip<- r2 - 32 - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) - mov r1, r1, lsr r2 @ r1<- r1 >>> r2 - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_xor_int.S b/runtime/interpreter/mterp/arm/op_xor_int.S deleted file mode 100644 index fd7a4b7a025665530f7c99f14eeb0634f04b40c9..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_xor_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/binop.S" {"instr":"eor r0, r0, r1"} diff --git a/runtime/interpreter/mterp/arm/op_xor_int_2addr.S b/runtime/interpreter/mterp/arm/op_xor_int_2addr.S deleted file mode 100644 index 196a6657245c6d30c8db5d93c96c824f26011b36..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_xor_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/binop2addr.S" {"instr":"eor r0, r0, r1"} diff --git a/runtime/interpreter/mterp/arm/op_xor_int_lit16.S b/runtime/interpreter/mterp/arm/op_xor_int_lit16.S deleted file mode 100644 index 39f2a47bfac016b0099d9d98b50283d50374988a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_xor_int_lit16.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/binopLit16.S" {"instr":"eor r0, r0, r1"} diff --git a/runtime/interpreter/mterp/arm/op_xor_int_lit8.S b/runtime/interpreter/mterp/arm/op_xor_int_lit8.S deleted file mode 100644 index 97d0b9ee14a99c0582473bbe2bfd5902dd17a26f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_xor_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/binopLit8.S" {"extract":"", "instr":"eor r0, r0, r3, asr #8"} diff --git a/runtime/interpreter/mterp/arm/op_xor_long.S b/runtime/interpreter/mterp/arm/op_xor_long.S deleted file mode 100644 index 4f830d01be6bd8ae090021927b649a405856e27f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_xor_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/binopWide.S" {"preinstr":"eor r0, r0, r2", "instr":"eor r1, r1, r3"} diff --git a/runtime/interpreter/mterp/arm/op_xor_long_2addr.S b/runtime/interpreter/mterp/arm/op_xor_long_2addr.S deleted file mode 100644 index 5b5ed88059b444a04e266f87d31edea2d8817c98..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/op_xor_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm/binopWide2addr.S" {"preinstr":"eor r0, r0, r2", "instr":"eor r1, r1, r3"} diff --git a/runtime/interpreter/mterp/arm/other.S b/runtime/interpreter/mterp/arm/other.S new file mode 100644 index 0000000000000000000000000000000000000000..340038c83e951253b6ae9e840021f1b750f86e4f --- /dev/null +++ b/runtime/interpreter/mterp/arm/other.S @@ -0,0 +1,379 @@ +%def const(helper="UndefinedConstHandler"): + /* const/class vAA, type@BBBB */ + /* const/method-handle vAA, method_handle@BBBB */ + /* const/method-type vAA, proto@BBBB */ + /* const/string vAA, string@@BBBB */ + .extern $helper + EXPORT_PC + FETCH r0, 1 @ r0<- BBBB + mov r1, rINST, lsr #8 @ r1<- AA + add r2, rFP, #OFF_FP_SHADOWFRAME + mov r3, rSELF + bl $helper @ (index, tgt_reg, shadow_frame, self) + PREFETCH_INST 2 @ load rINST + cmp r0, #0 @ fail? + bne MterpPossibleException @ let reference interpreter deal with it. + ADVANCE 2 @ advance rPC + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def unused(): +/* + * Bail to reference interpreter to throw. + */ + b MterpFallback + +%def op_const(): + /* const vAA, #+BBBBbbbb */ + mov r3, rINST, lsr #8 @ r3<- AA + FETCH r0, 1 @ r0<- bbbb (low) + FETCH r1, 2 @ r1<- BBBB (high) + FETCH_ADVANCE_INST 3 @ advance rPC, load rINST + orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb + GET_INST_OPCODE ip @ extract opcode from rINST + SET_VREG r0, r3 @ vAA<- r0 + GOTO_OPCODE ip @ jump to next instruction + +%def op_const_16(): + /* const/16 vAA, #+BBBB */ + FETCH_S r0, 1 @ r0<- ssssBBBB (sign-extended) + mov r3, rINST, lsr #8 @ r3<- AA + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + SET_VREG r0, r3 @ vAA<- r0 + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def op_const_4(): + /* const/4 vA, #+B */ + sbfx r1, rINST, #12, #4 @ r1<- sssssssB (sign-extended) + ubfx r0, rINST, #8, #4 @ r0<- A + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + GET_INST_OPCODE ip @ ip<- opcode from rINST + SET_VREG r1, r0 @ fp[A]<- r1 + GOTO_OPCODE ip @ execute next instruction + +%def op_const_class(): +% const(helper="MterpConstClass") + +%def op_const_high16(): + /* const/high16 vAA, #+BBBB0000 */ + FETCH r0, 1 @ r0<- 0000BBBB (zero-extended) + mov r3, rINST, lsr #8 @ r3<- AA + mov r0, r0, lsl #16 @ r0<- BBBB0000 + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + SET_VREG r0, r3 @ vAA<- r0 + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def op_const_method_handle(): +% const(helper="MterpConstMethodHandle") + +%def op_const_method_type(): +% const(helper="MterpConstMethodType") + +%def op_const_string(): +% const(helper="MterpConstString") + +%def op_const_string_jumbo(): + /* const/string vAA, String@BBBBBBBB */ + EXPORT_PC + FETCH r0, 1 @ r0<- bbbb (low) + FETCH r2, 2 @ r2<- BBBB (high) + mov r1, rINST, lsr #8 @ r1<- AA + orr r0, r0, r2, lsl #16 @ r1<- BBBBbbbb + add r2, rFP, #OFF_FP_SHADOWFRAME + mov r3, rSELF + bl MterpConstString @ (index, tgt_reg, shadow_frame, self) + PREFETCH_INST 3 @ advance rPC + cmp r0, #0 @ fail? + bne MterpPossibleException @ let reference interpreter deal with it. + ADVANCE 3 @ advance rPC + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def op_const_wide(): + /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ + FETCH r0, 1 @ r0<- bbbb (low) + FETCH r1, 2 @ r1<- BBBB (low middle) + FETCH r2, 3 @ r2<- hhhh (high middle) + orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb (low word) + FETCH r3, 4 @ r3<- HHHH (high) + mov r9, rINST, lsr #8 @ r9<- AA + orr r1, r2, r3, lsl #16 @ r1<- HHHHhhhh (high word) + CLEAR_SHADOW_PAIR r9, r2, r3 @ Zero out the shadow regs + FETCH_ADVANCE_INST 5 @ advance rPC, load rINST + VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] + GET_INST_OPCODE ip @ extract opcode from rINST + stmia r9, {r0-r1} @ vAA<- r0/r1 + GOTO_OPCODE ip @ jump to next instruction + +%def op_const_wide_16(): + /* const-wide/16 vAA, #+BBBB */ + FETCH_S r0, 1 @ r0<- ssssBBBB (sign-extended) + mov r3, rINST, lsr #8 @ r3<- AA + mov r1, r0, asr #31 @ r1<- ssssssss + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + CLEAR_SHADOW_PAIR r3, r2, lr @ Zero out the shadow regs + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[AA] + GET_INST_OPCODE ip @ extract opcode from rINST + stmia r3, {r0-r1} @ vAA<- r0/r1 + GOTO_OPCODE ip @ jump to next instruction + +%def op_const_wide_32(): + /* const-wide/32 vAA, #+BBBBbbbb */ + FETCH r0, 1 @ r0<- 0000bbbb (low) + mov r3, rINST, lsr #8 @ r3<- AA + FETCH_S r2, 2 @ r2<- ssssBBBB (high) + FETCH_ADVANCE_INST 3 @ advance rPC, load rINST + orr r0, r0, r2, lsl #16 @ r0<- BBBBbbbb + CLEAR_SHADOW_PAIR r3, r2, lr @ Zero out the shadow regs + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[AA] + mov r1, r0, asr #31 @ r1<- ssssssss + GET_INST_OPCODE ip @ extract opcode from rINST + stmia r3, {r0-r1} @ vAA<- r0/r1 + GOTO_OPCODE ip @ jump to next instruction + +%def op_const_wide_high16(): + /* const-wide/high16 vAA, #+BBBB000000000000 */ + FETCH r1, 1 @ r1<- 0000BBBB (zero-extended) + mov r3, rINST, lsr #8 @ r3<- AA + mov r0, #0 @ r0<- 00000000 + mov r1, r1, lsl #16 @ r1<- BBBB0000 + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + CLEAR_SHADOW_PAIR r3, r0, r2 @ Zero shadow regs + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[AA] + GET_INST_OPCODE ip @ extract opcode from rINST + stmia r3, {r0-r1} @ vAA<- r0/r1 + GOTO_OPCODE ip @ jump to next instruction + +%def op_monitor_enter(): + /* + * Synchronize on an object. + */ + /* monitor-enter vAA */ + EXPORT_PC + mov r2, rINST, lsr #8 @ r2<- AA + GET_VREG r0, r2 @ r0<- vAA (object) + mov r1, rSELF @ r1<- self + bl artLockObjectFromCode + cmp r0, #0 + bne MterpException + FETCH_ADVANCE_INST 1 + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def op_monitor_exit(): + /* + * Unlock an object. + * + * Exceptions that occur when unlocking a monitor need to appear as + * if they happened at the following instruction. See the Dalvik + * instruction spec. + */ + /* monitor-exit vAA */ + EXPORT_PC + mov r2, rINST, lsr #8 @ r2<- AA + GET_VREG r0, r2 @ r0<- vAA (object) + mov r1, rSELF @ r0<- self + bl artUnlockObjectFromCode @ r0<- success for unlock(self, obj) + cmp r0, #0 @ failed? + bne MterpException + FETCH_ADVANCE_INST 1 @ before throw: advance rPC, load rINST + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def op_move(is_object="0"): + /* for move, move-object, long-to-int */ + /* op vA, vB */ + mov r1, rINST, lsr #12 @ r1<- B from 15:12 + ubfx r0, rINST, #8, #4 @ r0<- A from 11:8 + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + GET_VREG r2, r1 @ r2<- fp[B] + GET_INST_OPCODE ip @ ip<- opcode from rINST + .if $is_object + SET_VREG_OBJECT r2, r0 @ fp[A]<- r2 + .else + SET_VREG r2, r0 @ fp[A]<- r2 + .endif + GOTO_OPCODE ip @ execute next instruction + +%def op_move_16(is_object="0"): + /* for: move/16, move-object/16 */ + /* op vAAAA, vBBBB */ + FETCH r1, 2 @ r1<- BBBB + FETCH r0, 1 @ r0<- AAAA + FETCH_ADVANCE_INST 3 @ advance rPC, load rINST + GET_VREG r2, r1 @ r2<- fp[BBBB] + GET_INST_OPCODE ip @ extract opcode from rINST + .if $is_object + SET_VREG_OBJECT r2, r0 @ fp[AAAA]<- r2 + .else + SET_VREG r2, r0 @ fp[AAAA]<- r2 + .endif + GOTO_OPCODE ip @ jump to next instruction + +%def op_move_exception(): + /* move-exception vAA */ + mov r2, rINST, lsr #8 @ r2<- AA + ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] + mov r1, #0 @ r1<- 0 + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + SET_VREG_OBJECT r3, r2 @ fp[AA]<- exception obj + GET_INST_OPCODE ip @ extract opcode from rINST + str r1, [rSELF, #THREAD_EXCEPTION_OFFSET] @ clear exception + GOTO_OPCODE ip @ jump to next instruction + +%def op_move_from16(is_object="0"): + /* for: move/from16, move-object/from16 */ + /* op vAA, vBBBB */ + FETCH r1, 1 @ r1<- BBBB + mov r0, rINST, lsr #8 @ r0<- AA + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + GET_VREG r2, r1 @ r2<- fp[BBBB] + GET_INST_OPCODE ip @ extract opcode from rINST + .if $is_object + SET_VREG_OBJECT r2, r0 @ fp[AA]<- r2 + .else + SET_VREG r2, r0 @ fp[AA]<- r2 + .endif + GOTO_OPCODE ip @ jump to next instruction + +%def op_move_object(): +% op_move(is_object="1") + +%def op_move_object_16(): +% op_move_16(is_object="1") + +%def op_move_object_from16(): +% op_move_from16(is_object="1") + +%def op_move_result(is_object="0"): + /* for: move-result, move-result-object */ + /* op vAA */ + mov r2, rINST, lsr #8 @ r2<- AA + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + ldr r0, [rFP, #OFF_FP_RESULT_REGISTER] @ get pointer to result JType. + ldr r0, [r0] @ r0 <- result.i. + GET_INST_OPCODE ip @ extract opcode from rINST + .if $is_object + SET_VREG_OBJECT r0, r2, r1 @ fp[AA]<- r0 + .else + SET_VREG r0, r2 @ fp[AA]<- r0 + .endif + GOTO_OPCODE ip @ jump to next instruction + +%def op_move_result_object(): +% op_move_result(is_object="1") + +%def op_move_result_wide(): + /* move-result-wide vAA */ + mov rINST, rINST, lsr #8 @ rINST<- AA + ldr r3, [rFP, #OFF_FP_RESULT_REGISTER] + VREG_INDEX_TO_ADDR r2, rINST @ r2<- &fp[AA] + ldmia r3, {r0-r1} @ r0/r1<- retval.j + CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + stmia r2, {r0-r1} @ fp[AA]<- r0/r1 + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def op_move_wide(): + /* move-wide vA, vB */ + /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ + mov r3, rINST, lsr #12 @ r3<- B + ubfx rINST, rINST, #8, #4 @ rINST<- A + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] + VREG_INDEX_TO_ADDR r2, rINST @ r2<- &fp[A] + ldmia r3, {r0-r1} @ r0/r1<- fp[B] + CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs + FETCH_ADVANCE_INST 1 @ advance rPC, load rINST + GET_INST_OPCODE ip @ extract opcode from rINST + stmia r2, {r0-r1} @ fp[A]<- r0/r1 + GOTO_OPCODE ip @ jump to next instruction + +%def op_move_wide_16(): + /* move-wide/16 vAAAA, vBBBB */ + /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ + FETCH r3, 2 @ r3<- BBBB + FETCH r2, 1 @ r2<- AAAA + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[BBBB] + VREG_INDEX_TO_ADDR lr, r2 @ r2<- &fp[AAAA] + ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] + FETCH_ADVANCE_INST 3 @ advance rPC, load rINST + CLEAR_SHADOW_PAIR r2, r3, ip @ Zero out the shadow regs + stmia lr, {r0-r1} @ fp[AAAA]<- r0/r1 + GET_INST_OPCODE ip @ extract opcode from rINST + GOTO_OPCODE ip @ jump to next instruction + +%def op_move_wide_from16(): + /* move-wide/from16 vAA, vBBBB */ + /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ + FETCH r3, 1 @ r3<- BBBB + mov rINST, rINST, lsr #8 @ rINST<- AA + VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[BBBB] + VREG_INDEX_TO_ADDR r2, rINST @ r2<- &fp[AA] + ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] + CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs + FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + GET_INST_OPCODE ip @ extract opcode from rINST + stmia r2, {r0-r1} @ fp[AA]<- r0/r1 + GOTO_OPCODE ip @ jump to next instruction + +%def op_nop(): + FETCH_ADVANCE_INST 1 @ advance to next instr, load rINST + GET_INST_OPCODE ip @ ip<- opcode from rINST + GOTO_OPCODE ip @ execute it + +%def op_unused_3e(): +% unused() + +%def op_unused_3f(): +% unused() + +%def op_unused_40(): +% unused() + +%def op_unused_41(): +% unused() + +%def op_unused_42(): +% unused() + +%def op_unused_43(): +% unused() + +%def op_unused_73(): +% unused() + +%def op_unused_79(): +% unused() + +%def op_unused_7a(): +% unused() + +%def op_unused_f3(): +% unused() + +%def op_unused_f4(): +% unused() + +%def op_unused_f5(): +% unused() + +%def op_unused_f6(): +% unused() + +%def op_unused_f7(): +% unused() + +%def op_unused_f8(): +% unused() + +%def op_unused_f9(): +% unused() + +%def op_unused_fc(): +% unused() + +%def op_unused_fd(): +% unused() diff --git a/runtime/interpreter/mterp/arm/unop.S b/runtime/interpreter/mterp/arm/unop.S deleted file mode 100644 index 56518b5b2b95b0dcfaf9ea5334e29c1dedf93767..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/unop.S +++ /dev/null @@ -1,20 +0,0 @@ -%default {"preinstr":""} - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op r0". - * This could be an ARM instruction or a function call. - * - * for: neg-int, not-int, neg-float, int-to-float, float-to-int, - * int-to-byte, int-to-char, int-to-short - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r0, r3 @ r0<- vB - $preinstr @ optional op; may set condition codes - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - $instr @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 8-9 instructions */ diff --git a/runtime/interpreter/mterp/arm/unopNarrower.S b/runtime/interpreter/mterp/arm/unopNarrower.S deleted file mode 100644 index 2d0453aeb1a991d78773bb1b1b30303cb976a2fc..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/unopNarrower.S +++ /dev/null @@ -1,23 +0,0 @@ -%default {"preinstr":""} - /* - * Generic 64bit-to-32bit unary operation. Provide an "instr" line - * that specifies an instruction that performs "result = op r0/r1", where - * "result" is a 32-bit quantity in r0. - * - * For: long-to-float, double-to-int, double-to-float - * - * (This would work for long-to-int, but that instruction is actually - * an exact match for op_move.) - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] - ldmia r3, {r0-r1} @ r0/r1<- vB/vB+1 - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - $preinstr @ optional op; may set condition codes - $instr @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 9-10 instructions */ diff --git a/runtime/interpreter/mterp/arm/unopWide.S b/runtime/interpreter/mterp/arm/unopWide.S deleted file mode 100644 index cd5defd616dbc05d333edddb3289d8c469a2cc56..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/unopWide.S +++ /dev/null @@ -1,22 +0,0 @@ -%default {"preinstr":""} - /* - * Generic 64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op r0/r1". - * This could be an ARM instruction or a function call. - * - * For: neg-long, not-long, neg-double, long-to-double, double-to-long - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx rINST, rINST, #8, #4 @ rINST<- A - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] - ldmia r3, {r0-r1} @ r0/r1<- vAA - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - $preinstr @ optional op; may set condition codes - $instr @ r0/r1<- op, r2-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vAA<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 10-11 instructions */ diff --git a/runtime/interpreter/mterp/arm/unopWider.S b/runtime/interpreter/mterp/arm/unopWider.S deleted file mode 100644 index 9d504899b838138ef06101beedf2f7152a229758..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/unopWider.S +++ /dev/null @@ -1,21 +0,0 @@ -%default {"preinstr":""} - /* - * Generic 32bit-to-64bit unary operation. Provide an "instr" line - * that specifies an instruction that performs "result = op r0", where - * "result" is a 64-bit quantity in r0/r1. - * - * For: int-to-long, int-to-double, float-to-long, float-to-double - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx rINST, rINST, #8, #4 @ rINST<- A - GET_VREG r0, r3 @ r0<- vB - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] - $preinstr @ optional op; may set condition codes - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - $instr @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 9-10 instructions */ diff --git a/runtime/interpreter/mterp/arm/unused.S b/runtime/interpreter/mterp/arm/unused.S deleted file mode 100644 index ffa00becfdb2bb4ba58ee7659a0609978599110e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/unused.S +++ /dev/null @@ -1,4 +0,0 @@ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback diff --git a/runtime/interpreter/mterp/arm/zcmp.S b/runtime/interpreter/mterp/arm/zcmp.S deleted file mode 100644 index 5db8b6cdd7f42d0584038562d74b1cb74ad53b1f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm/zcmp.S +++ /dev/null @@ -1,17 +0,0 @@ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - mov r0, rINST, lsr #8 @ r0<- AA - GET_VREG r0, r0 @ r0<- vAA - FETCH_S rINST, 1 @ rINST<- branch offset, in code units - cmp r0, #0 @ compare (vA, 0) - b${condition} MterpCommonTakenBranchNoFlags - cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? - beq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/alt_stub.S b/runtime/interpreter/mterp/arm64/alt_stub.S deleted file mode 100644 index 3a463feb415c7898894f6a7ffa40a0c59bd75d1f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/alt_stub.S +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (${opnum} * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. diff --git a/runtime/interpreter/mterp/arm64/arithmetic.S b/runtime/interpreter/mterp/arm64/arithmetic.S new file mode 100644 index 0000000000000000000000000000000000000000..cf9dd869d04a0902fd50cf6e3667d8eea8ea2545 --- /dev/null +++ b/runtime/interpreter/mterp/arm64/arithmetic.S @@ -0,0 +1,507 @@ +%def binop(preinstr="", result="w0", chkzero="0", instr=""): + /* + * Generic 32-bit binary operation. Provide an "instr" line that + * specifies an instruction that performs "result = w0 op w1". + * This could be an ARM instruction or a function call. (If the result + * comes back in a register other than w0, you can override "result".) + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vCC (w1). Useful for integer division and modulus. Note that we + * *don't* check for (INT_MIN / -1) here, because the ARM math lib + * handles it correctly. + * + * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, + * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, + * mul-float, div-float, rem-float + */ + /* binop vAA, vBB, vCC */ + FETCH w0, 1 // w0<- CCBB + lsr w9, wINST, #8 // w9<- AA + lsr w3, w0, #8 // w3<- CC + and w2, w0, #255 // w2<- BB + GET_VREG w1, w3 // w1<- vCC + GET_VREG w0, w2 // w0<- vBB + .if $chkzero + cbz w1, common_errDivideByZero // is second operand zero? + .endif + FETCH_ADVANCE_INST 2 // advance rPC, load rINST + $preinstr // optional op; may set condition codes + $instr // $result<- op, w0-w3 changed + GET_INST_OPCODE ip // extract opcode from rINST + SET_VREG $result, w9 // vAA<- $result + GOTO_OPCODE ip // jump to next instruction + /* 11-14 instructions */ + +%def binop2addr(preinstr="", result="w0", chkzero="0", instr=""): + /* + * Generic 32-bit "/2addr" binary operation. Provide an "instr" line + * that specifies an instruction that performs "result = w0 op w1". + * This could be an ARM instruction or a function call. (If the result + * comes back in a register other than w0, you can override "result".) + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vCC (w1). Useful for integer division and modulus. + * + * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, + * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, + * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, + * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr + */ + /* binop/2addr vA, vB */ + lsr w3, wINST, #12 // w3<- B + ubfx w9, wINST, #8, #4 // w9<- A + GET_VREG w1, w3 // w1<- vB + GET_VREG w0, w9 // w0<- vA + .if $chkzero + cbz w1, common_errDivideByZero + .endif + FETCH_ADVANCE_INST 1 // advance rPC, load rINST + $preinstr // optional op; may set condition codes + $instr // $result<- op, w0-w3 changed + GET_INST_OPCODE ip // extract opcode from rINST + SET_VREG $result, w9 // vAA<- $result + GOTO_OPCODE ip // jump to next instruction + /* 10-13 instructions */ + +%def binopLit16(preinstr="", result="w0", chkzero="0", instr=""): + /* + * Generic 32-bit "lit16" binary operation. Provide an "instr" line + * that specifies an instruction that performs "result = w0 op w1". + * This could be an ARM instruction or a function call. (If the result + * comes back in a register other than w0, you can override "result".) + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vCC (w1). Useful for integer division and modulus. + * + * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, + * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 + */ + /* binop/lit16 vA, vB, #+CCCC */ + FETCH_S w1, 1 // w1<- ssssCCCC (sign-extended) + lsr w2, wINST, #12 // w2<- B + ubfx w9, wINST, #8, #4 // w9<- A + GET_VREG w0, w2 // w0<- vB + .if $chkzero + cbz w1, common_errDivideByZero + .endif + FETCH_ADVANCE_INST 2 // advance rPC, load rINST + $preinstr + $instr // $result<- op, w0-w3 changed + GET_INST_OPCODE ip // extract opcode from rINST + SET_VREG $result, w9 // vAA<- $result + GOTO_OPCODE ip // jump to next instruction + /* 10-13 instructions */ + +%def binopLit8(extract="asr w1, w3, #8", preinstr="", result="w0", chkzero="0", instr=""): + /* + * Generic 32-bit "lit8" binary operation. Provide an "instr" line + * that specifies an instruction that performs "result = w0 op w1". + * This could be an ARM instruction or a function call. (If the result + * comes back in a register other than w0, you can override "result".) + * + * You can override "extract" if the extraction of the literal value + * from w3 to w1 is not the default "asr w1, w3, #8". The extraction + * can be omitted completely if the shift is embedded in "instr". + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vCC (w1). Useful for integer division and modulus. + * + * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, + * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, + * shl-int/lit8, shr-int/lit8, ushr-int/lit8 + */ + /* binop/lit8 vAA, vBB, #+CC */ + FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC) + lsr w9, wINST, #8 // w9<- AA + and w2, w3, #255 // w2<- BB + GET_VREG w0, w2 // w0<- vBB + $extract // optional; typically w1<- ssssssCC (sign extended) + .if $chkzero + cbz w1, common_errDivideByZero + .endif + FETCH_ADVANCE_INST 2 // advance rPC, load rINST + $preinstr // optional op; may set condition codes + $instr // $result<- op, w0-w3 changed + GET_INST_OPCODE ip // extract opcode from rINST + SET_VREG $result, w9 // vAA<- $result + GOTO_OPCODE ip // jump to next instruction + /* 10-12 instructions */ + +%def binopWide(preinstr="", instr="add x0, x1, x2", result="x0", r1="x1", r2="x2", chkzero="0"): + /* + * Generic 64-bit binary operation. Provide an "instr" line that + * specifies an instruction that performs "result = x1 op x2". + * This could be an ARM instruction or a function call. (If the result + * comes back in a register other than x0, you can override "result".) + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vCC (w1). Useful for integer division and modulus. + * + * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, + * xor-long, add-double, sub-double, mul-double, div-double, rem-double + */ + /* binop vAA, vBB, vCC */ + FETCH w0, 1 // w0<- CCBB + lsr w4, wINST, #8 // w4<- AA + lsr w2, w0, #8 // w2<- CC + and w1, w0, #255 // w1<- BB + GET_VREG_WIDE $r2, w2 // w2<- vCC + GET_VREG_WIDE $r1, w1 // w1<- vBB + .if $chkzero + cbz $r2, common_errDivideByZero // is second operand zero? + .endif + FETCH_ADVANCE_INST 2 // advance rPC, load rINST + $preinstr + $instr // $result<- op, w0-w4 changed + GET_INST_OPCODE ip // extract opcode from rINST + SET_VREG_WIDE $result, w4 // vAA<- $result + GOTO_OPCODE ip // jump to next instruction + /* 11-14 instructions */ + +%def binopWide2addr(preinstr="", instr="add x0, x0, x1", r0="x0", r1="x1", chkzero="0"): + /* + * Generic 64-bit "/2addr" binary operation. Provide an "instr" line + * that specifies an instruction that performs "x0 = x0 op x1". + * This must not be a function call, as we keep w2 live across it. + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vCC (w1). Useful for integer division and modulus. + * + * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, + * and-long/2addr, or-long/2addr, xor-long/2addr, + * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, + * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr + */ + /* binop/2addr vA, vB */ + lsr w1, wINST, #12 // w1<- B + ubfx w2, wINST, #8, #4 // w2<- A + GET_VREG_WIDE $r1, w1 // x1<- vB + GET_VREG_WIDE $r0, w2 // x0<- vA + .if $chkzero + cbz $r1, common_errDivideByZero + .endif + FETCH_ADVANCE_INST 1 // advance rPC, load rINST + $preinstr + $instr // result<- op + GET_INST_OPCODE ip // extract opcode from rINST + SET_VREG_WIDE $r0, w2 // vAA<- result + GOTO_OPCODE ip // jump to next instruction + /* 10-13 instructions */ + +%def shiftWide(opcode="shl"): + /* + * 64-bit shift operation. + * + * For: shl-long, shr-long, ushr-long + */ + /* binop vAA, vBB, vCC */ + FETCH w0, 1 // w0<- CCBB + lsr w3, wINST, #8 // w3<- AA + lsr w2, w0, #8 // w2<- CC + GET_VREG w2, w2 // w2<- vCC (shift count) + and w1, w0, #255 // w1<- BB + GET_VREG_WIDE x1, w1 // x1<- vBB + FETCH_ADVANCE_INST 2 // advance rPC, load rINST + $opcode x0, x1, x2 // Do the shift. Only low 6 bits of x2 are used. + GET_INST_OPCODE ip // extract opcode from rINST + SET_VREG_WIDE x0, w3 // vAA<- x0 + GOTO_OPCODE ip // jump to next instruction + /* 11-14 instructions */ + +%def shiftWide2addr(opcode="lsl"): + /* + * Generic 64-bit shift operation. + */ + /* binop/2addr vA, vB */ + lsr w1, wINST, #12 // w1<- B + ubfx w2, wINST, #8, #4 // w2<- A + GET_VREG w1, w1 // x1<- vB + GET_VREG_WIDE x0, w2 // x0<- vA + FETCH_ADVANCE_INST 1 // advance rPC, load rINST + $opcode x0, x0, x1 // Do the shift. Only low 6 bits of x1 are used. + GET_INST_OPCODE ip // extract opcode from rINST + SET_VREG_WIDE x0, w2 // vAA<- result + GOTO_OPCODE ip // jump to next instruction + /* 10-13 instructions */ + +%def unop(instr=""): + /* + * Generic 32-bit unary operation. Provide an "instr" line that + * specifies an instruction that performs "result = op w0". + * This could be an ARM instruction or a function call. + * + * for: neg-int, not-int, neg-float, int-to-float, float-to-int, + * int-to-byte, int-to-char, int-to-short + */ + /* unop vA, vB */ + lsr w3, wINST, #12 // w3<- B + GET_VREG w0, w3 // w0<- vB + ubfx w9, wINST, #8, #4 // w9<- A + FETCH_ADVANCE_INST 1 // advance rPC, load rINST + $instr // w0<- op, w0-w3 changed + GET_INST_OPCODE ip // extract opcode from rINST + SET_VREG w0, w9 // vAA<- w0 + GOTO_OPCODE ip // jump to next instruction + /* 8-9 instructions */ + +%def unopWide(instr="sub x0, xzr, x0"): + /* + * Generic 64-bit unary operation. Provide an "instr" line that + * specifies an instruction that performs "result = op x0". + * + * For: neg-long, not-long + */ + /* unop vA, vB */ + lsr w3, wINST, #12 // w3<- B + ubfx w4, wINST, #8, #4 // w4<- A + GET_VREG_WIDE x0, w3 + FETCH_ADVANCE_INST 1 // advance rPC, load wINST + $instr + GET_INST_OPCODE ip // extract opcode from wINST + SET_VREG_WIDE x0, w4 + GOTO_OPCODE ip // jump to next instruction + /* 10-11 instructions */ + +%def op_add_int(): +% binop(instr="add w0, w0, w1") + +%def op_add_int_2addr(): +% binop2addr(instr="add w0, w0, w1") + +%def op_add_int_lit16(): +% binopLit16(instr="add w0, w0, w1") + +%def op_add_int_lit8(): +% binopLit8(extract="", instr="add w0, w0, w3, asr #8") + +%def op_add_long(): +% binopWide(instr="add x0, x1, x2") + +%def op_add_long_2addr(): +% binopWide2addr(instr="add x0, x0, x1") + +%def op_and_int(): +% binop(instr="and w0, w0, w1") + +%def op_and_int_2addr(): +% binop2addr(instr="and w0, w0, w1") + +%def op_and_int_lit16(): +% binopLit16(instr="and w0, w0, w1") + +%def op_and_int_lit8(): +% binopLit8(extract="", instr="and w0, w0, w3, asr #8") + +%def op_and_long(): +% binopWide(instr="and x0, x1, x2") + +%def op_and_long_2addr(): +% binopWide2addr(instr="and x0, x0, x1") + +%def op_cmp_long(): + FETCH w0, 1 // w0<- CCBB + lsr w4, wINST, #8 // w4<- AA + and w2, w0, #255 // w2<- BB + lsr w3, w0, #8 // w3<- CC + GET_VREG_WIDE x1, w2 + GET_VREG_WIDE x2, w3 + cmp x1, x2 + cset w0, ne + cneg w0, w0, lt + FETCH_ADVANCE_INST 2 // advance rPC, load wINST + SET_VREG w0, w4 + GET_INST_OPCODE ip // extract opcode from wINST + GOTO_OPCODE ip // jump to next instruction + +%def op_div_int(): +% binop(instr="sdiv w0, w0, w1", chkzero="1") + +%def op_div_int_2addr(): +% binop2addr(instr="sdiv w0, w0, w1", chkzero="1") + +%def op_div_int_lit16(): +% binopLit16(instr="sdiv w0, w0, w1", chkzero="1") + +%def op_div_int_lit8(): +% binopLit8(instr="sdiv w0, w0, w1", chkzero="1") + +%def op_div_long(): +% binopWide(instr="sdiv x0, x1, x2", chkzero="1") + +%def op_div_long_2addr(): +% binopWide2addr(instr="sdiv x0, x0, x1", chkzero="1") + +%def op_int_to_byte(): +% unop(instr="sxtb w0, w0") + +%def op_int_to_char(): +% unop(instr="uxth w0, w0") + +%def op_int_to_long(): + /* int-to-long vA, vB */ + lsr w3, wINST, #12 // w3<- B + ubfx w4, wINST, #8, #4 // w4<- A + GET_VREG_S x0, w3 // x0<- sign_extend(fp[B]) + FETCH_ADVANCE_INST 1 // advance rPC, load wINST + GET_INST_OPCODE ip // extract opcode from wINST + SET_VREG_WIDE x0, w4 // fp[A]<- x0 + GOTO_OPCODE ip // jump to next instruction + +%def op_int_to_short(): +% unop(instr="sxth w0, w0") + +%def op_long_to_int(): +/* we ignore the high word, making this equivalent to a 32-bit reg move */ +% op_move() + +%def op_mul_int(): +/* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */ +% binop(instr="mul w0, w1, w0") + +%def op_mul_int_2addr(): +/* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */ +% binop2addr(instr="mul w0, w1, w0") + +%def op_mul_int_lit16(): +/* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */ +% binopLit16(instr="mul w0, w1, w0") + +%def op_mul_int_lit8(): +/* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */ +% binopLit8(instr="mul w0, w1, w0") + +%def op_mul_long(): +% binopWide(instr="mul x0, x1, x2") + +%def op_mul_long_2addr(): +% binopWide2addr(instr="mul x0, x0, x1") + +%def op_neg_int(): +% unop(instr="sub w0, wzr, w0") + +%def op_neg_long(): +% unopWide(instr="sub x0, xzr, x0") + +%def op_not_int(): +% unop(instr="mvn w0, w0") + +%def op_not_long(): +% unopWide(instr="mvn x0, x0") + +%def op_or_int(): +% binop(instr="orr w0, w0, w1") + +%def op_or_int_2addr(): +% binop2addr(instr="orr w0, w0, w1") + +%def op_or_int_lit16(): +% binopLit16(instr="orr w0, w0, w1") + +%def op_or_int_lit8(): +% binopLit8(extract="", instr="orr w0, w0, w3, asr #8") + +%def op_or_long(): +% binopWide(instr="orr x0, x1, x2") + +%def op_or_long_2addr(): +% binopWide2addr(instr="orr x0, x0, x1") + +%def op_rem_int(): +% binop(preinstr="sdiv w2, w0, w1", instr="msub w0, w2, w1, w0", chkzero="1") + +%def op_rem_int_2addr(): +% binop2addr(preinstr="sdiv w2, w0, w1", instr="msub w0, w2, w1, w0", chkzero="1") + +%def op_rem_int_lit16(): +% binopLit16(preinstr="sdiv w3, w0, w1", instr="msub w0, w3, w1, w0", chkzero="1") + +%def op_rem_int_lit8(): +% binopLit8(preinstr="sdiv w3, w0, w1", instr="msub w0, w3, w1, w0", chkzero="1") + +%def op_rem_long(): +% binopWide(preinstr="sdiv x3, x1, x2", instr="msub x0, x3, x2, x1", chkzero="1") + +%def op_rem_long_2addr(): +% binopWide2addr(preinstr="sdiv x3, x0, x1", instr="msub x0, x3, x1, x0", chkzero="1") + +%def op_rsub_int(): +/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ +% binopLit16(instr="sub w0, w1, w0") + +%def op_rsub_int_lit8(): +% binopLit8(instr="sub w0, w1, w0") + +%def op_shl_int(): +% binop(instr="lsl w0, w0, w1") + +%def op_shl_int_2addr(): +% binop2addr(instr="lsl w0, w0, w1") + +%def op_shl_int_lit8(): +% binopLit8(extract="ubfx w1, w3, #8, #5", instr="lsl w0, w0, w1") + +%def op_shl_long(): +% shiftWide(opcode="lsl") + +%def op_shl_long_2addr(): +% shiftWide2addr(opcode="lsl") + +%def op_shr_int(): +% binop(instr="asr w0, w0, w1") + +%def op_shr_int_2addr(): +% binop2addr(instr="asr w0, w0, w1") + +%def op_shr_int_lit8(): +% binopLit8(extract="ubfx w1, w3, #8, #5", instr="asr w0, w0, w1") + +%def op_shr_long(): +% shiftWide(opcode="asr") + +%def op_shr_long_2addr(): +% shiftWide2addr(opcode="asr") + +%def op_sub_int(): +% binop(instr="sub w0, w0, w1") + +%def op_sub_int_2addr(): +% binop2addr(instr="sub w0, w0, w1") + +%def op_sub_long(): +% binopWide(instr="sub x0, x1, x2") + +%def op_sub_long_2addr(): +% binopWide2addr(instr="sub x0, x0, x1") + +%def op_ushr_int(): +% binop(instr="lsr w0, w0, w1") + +%def op_ushr_int_2addr(): +% binop2addr(instr="lsr w0, w0, w1") + +%def op_ushr_int_lit8(): +% binopLit8(extract="ubfx w1, w3, #8, #5", instr="lsr w0, w0, w1") + +%def op_ushr_long(): +% shiftWide(opcode="lsr") + +%def op_ushr_long_2addr(): +% shiftWide2addr(opcode="lsr") + +%def op_xor_int(): +% binop(instr="eor w0, w0, w1") + +%def op_xor_int_2addr(): +% binop2addr(instr="eor w0, w0, w1") + +%def op_xor_int_lit16(): +% binopLit16(instr="eor w0, w0, w1") + +%def op_xor_int_lit8(): +% binopLit8(extract="", instr="eor w0, w0, w3, asr #8") + +%def op_xor_long(): +% binopWide(instr="eor x0, x1, x2") + +%def op_xor_long_2addr(): +% binopWide2addr(instr="eor x0, x0, x1") diff --git a/runtime/interpreter/mterp/arm64/array.S b/runtime/interpreter/mterp/arm64/array.S new file mode 100644 index 0000000000000000000000000000000000000000..a023d22ff5c625c332c46a3040e9664c52343565 --- /dev/null +++ b/runtime/interpreter/mterp/arm64/array.S @@ -0,0 +1,235 @@ +%def op_aget(load="ldr", shift="2", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"): + /* + * Array get, 32 bits or less. vAA <- vBB[vCC]. + * + * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 + * instructions. We use a pair of FETCH_Bs instead. + * + * for: aget, aget-boolean, aget-byte, aget-char, aget-short + * + * NOTE: assumes data offset for arrays is the same for all non-wide types. + * If this changes, specialize. + */ + /* op vAA, vBB, vCC */ + FETCH_B w2, 1, 0 // w2<- BB + lsr w9, wINST, #8 // w9<- AA + FETCH_B w3, 1, 1 // w3<- CC + GET_VREG w0, w2 // w0<- vBB (array object) + GET_VREG w1, w3 // w1<- vCC (requested index) + cbz x0, common_errNullObject // bail if null array object. + ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length + add x0, x0, w1, uxtw #$shift // w0<- arrayObj + index*width + cmp w1, w3 // compare unsigned index, length + bcs common_errArrayIndex // index >= length, bail + FETCH_ADVANCE_INST 2 // advance rPC, load rINST + $load w2, [x0, #$data_offset] // w2<- vBB[vCC] + GET_INST_OPCODE ip // extract opcode from rINST + SET_VREG w2, w9 // vAA<- w2 + GOTO_OPCODE ip // jump to next instruction + +%def op_aget_boolean(): +% op_aget(load="ldrb", shift="0", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") + +%def op_aget_byte(): +% op_aget(load="ldrsb", shift="0", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") + +%def op_aget_char(): +% op_aget(load="ldrh", shift="1", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") + +%def op_aget_object(): + /* + * Array object get. vAA <- vBB[vCC]. + * + * for: aget-object + */ + /* op vAA, vBB, vCC */ + FETCH_B w2, 1, 0 // w2<- BB + FETCH_B w3, 1, 1 // w3<- CC + EXPORT_PC + GET_VREG w0, w2 // w0<- vBB (array object) + GET_VREG w1, w3 // w1<- vCC (requested index) + bl artAGetObjectFromMterp // (array, index) + ldr x1, [xSELF, #THREAD_EXCEPTION_OFFSET] + lsr w2, wINST, #8 // w9<- AA + PREFETCH_INST 2 + cbnz w1, MterpException + SET_VREG_OBJECT w0, w2 + ADVANCE 2 + GET_INST_OPCODE ip + GOTO_OPCODE ip // jump to next instruction + +%def op_aget_short(): +% op_aget(load="ldrsh", shift="1", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") + +%def op_aget_wide(): + /* + * Array get, 64 bits. vAA <- vBB[vCC]. + * + */ + /* aget-wide vAA, vBB, vCC */ + FETCH w0, 1 // w0<- CCBB + lsr w4, wINST, #8 // w4<- AA + and w2, w0, #255 // w2<- BB + lsr w3, w0, #8 // w3<- CC + GET_VREG w0, w2 // w0<- vBB (array object) + GET_VREG w1, w3 // w1<- vCC (requested index) + cbz w0, common_errNullObject // yes, bail + ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length + add x0, x0, w1, lsl #3 // w0<- arrayObj + index*width + cmp w1, w3 // compare unsigned index, length + bcs common_errArrayIndex // index >= length, bail + FETCH_ADVANCE_INST 2 // advance rPC, load wINST + ldr x2, [x0, #MIRROR_WIDE_ARRAY_DATA_OFFSET] // x2<- vBB[vCC] + GET_INST_OPCODE ip // extract opcode from wINST + SET_VREG_WIDE x2, w4 + GOTO_OPCODE ip // jump to next instruction + +%def op_aput(store="str", shift="2", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"): + /* + * Array put, 32 bits or less. vBB[vCC] <- vAA. + * + * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 + * instructions. We use a pair of FETCH_Bs instead. + * + * for: aput, aput-boolean, aput-byte, aput-char, aput-short + * + * NOTE: this assumes data offset for arrays is the same for all non-wide types. + * If this changes, specialize. + */ + /* op vAA, vBB, vCC */ + FETCH_B w2, 1, 0 // w2<- BB + lsr w9, wINST, #8 // w9<- AA + FETCH_B w3, 1, 1 // w3<- CC + GET_VREG w0, w2 // w0<- vBB (array object) + GET_VREG w1, w3 // w1<- vCC (requested index) + cbz w0, common_errNullObject // bail if null + ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length + add x0, x0, w1, lsl #$shift // w0<- arrayObj + index*width + cmp w1, w3 // compare unsigned index, length + bcs common_errArrayIndex // index >= length, bail + FETCH_ADVANCE_INST 2 // advance rPC, load rINST + GET_VREG w2, w9 // w2<- vAA + GET_INST_OPCODE ip // extract opcode from rINST + $store w2, [x0, #$data_offset] // vBB[vCC]<- w2 + GOTO_OPCODE ip // jump to next instruction + +%def op_aput_boolean(): +% op_aput(store="strb", shift="0", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") + +%def op_aput_byte(): +% op_aput(store="strb", shift="0", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") + +%def op_aput_char(): +% op_aput(store="strh", shift="1", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") + +%def op_aput_object(): + /* + * Store an object into an array. vBB[vCC] <- vAA. + */ + /* op vAA, vBB, vCC */ + EXPORT_PC + add x0, xFP, #OFF_FP_SHADOWFRAME + mov x1, xPC + mov w2, wINST + bl MterpAputObject + cbz w0, MterpPossibleException + FETCH_ADVANCE_INST 2 // advance rPC, load rINST + GET_INST_OPCODE ip // extract opcode from rINST + GOTO_OPCODE ip // jump to next instruction + +%def op_aput_short(): +% op_aput(store="strh", shift="1", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") + +%def op_aput_wide(): + /* + * Array put, 64 bits. vBB[vCC] <- vAA. + * + */ + /* aput-wide vAA, vBB, vCC */ + FETCH w0, 1 // w0<- CCBB + lsr w4, wINST, #8 // w4<- AA + and w2, w0, #255 // w2<- BB + lsr w3, w0, #8 // w3<- CC + GET_VREG w0, w2 // w0<- vBB (array object) + GET_VREG w1, w3 // w1<- vCC (requested index) + cbz w0, common_errNullObject // bail if null + ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length + add x0, x0, w1, lsl #3 // w0<- arrayObj + index*width + cmp w1, w3 // compare unsigned index, length + bcs common_errArrayIndex // index >= length, bail + GET_VREG_WIDE x1, w4 + FETCH_ADVANCE_INST 2 // advance rPC, load wINST + GET_INST_OPCODE ip // extract opcode from wINST + str x1, [x0, #MIRROR_WIDE_ARRAY_DATA_OFFSET] + GOTO_OPCODE ip // jump to next instruction + +%def op_array_length(): + /* + * Return the length of an array. + */ + lsr w1, wINST, #12 // w1<- B + ubfx w2, wINST, #8, #4 // w2<- A + GET_VREG w0, w1 // w0<- vB (object ref) + cbz w0, common_errNullObject // yup, fail + FETCH_ADVANCE_INST 1 // advance rPC, load rINST + ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- array length + GET_INST_OPCODE ip // extract opcode from rINST + SET_VREG w3, w2 // vB<- length + GOTO_OPCODE ip // jump to next instruction + +%def op_fill_array_data(): + /* fill-array-data vAA, +BBBBBBBB */ + EXPORT_PC + FETCH w0, 1 // x0<- 000000000000bbbb (lo) + FETCH_S x1, 2 // x1<- ssssssssssssBBBB (hi) + lsr w3, wINST, #8 // w3<- AA + orr x1, x0, x1, lsl #16 // x1<- ssssssssBBBBbbbb + GET_VREG w0, w3 // w0<- vAA (array object) + add x1, xPC, x1, lsl #1 // x1<- PC + ssssssssBBBBbbbb*2 (array data off.) + bl MterpFillArrayData // (obj, payload) + cbz w0, MterpPossibleException // exception? + FETCH_ADVANCE_INST 3 // advance rPC, load rINST + GET_INST_OPCODE ip // extract opcode from rINST + GOTO_OPCODE ip // jump to next instruction + +%def op_filled_new_array(helper="MterpFilledNewArray"): + /* + * Create a new array with elements filled from registers. + * + * for: filled-new-array, filled-new-array/range + */ + /* op vB, {vD, vE, vF, vG, vA}, class//CCCC */ + /* op {vCCCC..v(CCCC+AA-1)}, type//BBBB */ + .extern $helper + EXPORT_PC + add x0, xFP, #OFF_FP_SHADOWFRAME + mov x1, xPC + mov x2, xSELF + bl $helper + cbz w0, MterpPossibleException + FETCH_ADVANCE_INST 3 // advance rPC, load rINST + GET_INST_OPCODE ip // extract opcode from rINST + GOTO_OPCODE ip // jump to next instruction + +%def op_filled_new_array_range(): +% op_filled_new_array(helper="MterpFilledNewArrayRange") + +%def op_new_array(): + /* + * Allocate an array of objects, specified with the array class + * and a count. + * + * The verifier guarantees that this is an array class, so we don't + * check for it here. + */ + /* new-array vA, vB, class//CCCC */ + EXPORT_PC + add x0, xFP, #OFF_FP_SHADOWFRAME + mov x1, xPC + mov w2, wINST + mov x3, xSELF + bl MterpNewArray + cbz w0, MterpPossibleException + FETCH_ADVANCE_INST 2 // advance rPC, load rINST + GET_INST_OPCODE ip // extract opcode from rINST + GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/bincmp.S b/runtime/interpreter/mterp/arm64/bincmp.S deleted file mode 100644 index 8dd4fed7ca38ac7cedf4a9ea4344dc64311d6398..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/bincmp.S +++ /dev/null @@ -1,19 +0,0 @@ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - lsr w1, wINST, #12 // w1<- B - ubfx w0, wINST, #8, #4 // w0<- A - GET_VREG w3, w1 // w3<- vB - GET_VREG w2, w0 // w2<- vA - FETCH_S wINST, 1 // wINST<- branch offset, in code units - cmp w2, w3 // compare (vA, vB) - b.${condition} MterpCommonTakenBranchNoFlags - cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? - b.eq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/binop.S b/runtime/interpreter/mterp/arm64/binop.S deleted file mode 100644 index b629b0b37e9342e10d4d473bbf8d2a5744b14839..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/binop.S +++ /dev/null @@ -1,33 +0,0 @@ -%default {"preinstr":"", "result":"w0", "chkzero":"0"} - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w9, wINST, #8 // w9<- AA - lsr w3, w0, #8 // w3<- CC - and w2, w0, #255 // w2<- BB - GET_VREG w1, w3 // w1<- vCC - GET_VREG w0, w2 // w0<- vBB - .if $chkzero - cbz w1, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - $preinstr // optional op; may set condition codes - $instr // $result<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG $result, w9 // vAA<- $result - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ diff --git a/runtime/interpreter/mterp/arm64/binop2addr.S b/runtime/interpreter/mterp/arm64/binop2addr.S deleted file mode 100644 index a480a7d55134717d5c6e98c5c0ba2fcde8e1892e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/binop2addr.S +++ /dev/null @@ -1,30 +0,0 @@ -%default {"preinstr":"", "result":"w0", "chkzero":"0"} - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG w1, w3 // w1<- vB - GET_VREG w0, w9 // w0<- vA - .if $chkzero - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - $preinstr // optional op; may set condition codes - $instr // $result<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG $result, w9 // vAA<- $result - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ diff --git a/runtime/interpreter/mterp/arm64/binopLit16.S b/runtime/interpreter/mterp/arm64/binopLit16.S deleted file mode 100644 index 4f9d205b38a84fc44dd31f90009e77c14fbb5a14..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/binopLit16.S +++ /dev/null @@ -1,28 +0,0 @@ -%default {"preinstr":"", "result":"w0", "chkzero":"0"} - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - FETCH_S w1, 1 // w1<- ssssCCCC (sign-extended) - lsr w2, wINST, #12 // w2<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG w0, w2 // w0<- vB - .if $chkzero - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - $preinstr - $instr // $result<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG $result, w9 // vAA<- $result - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ diff --git a/runtime/interpreter/mterp/arm64/binopLit8.S b/runtime/interpreter/mterp/arm64/binopLit8.S deleted file mode 100644 index dfa316990523753e61aedf868313147694615fbc..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/binopLit8.S +++ /dev/null @@ -1,34 +0,0 @@ -%default {"extract": "asr w1, w3, #8", "preinstr":"", "result":"w0", "chkzero":"0"} - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from w3 to w1 is not the default "asr w1, w3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC) - lsr w9, wINST, #8 // w9<- AA - and w2, w3, #255 // w2<- BB - GET_VREG w0, w2 // w0<- vBB - $extract // optional; typically w1<- ssssssCC (sign extended) - .if $chkzero - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - $preinstr // optional op; may set condition codes - $instr // $result<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG $result, w9 // vAA<- $result - GOTO_OPCODE ip // jump to next instruction - /* 10-12 instructions */ diff --git a/runtime/interpreter/mterp/arm64/binopWide.S b/runtime/interpreter/mterp/arm64/binopWide.S deleted file mode 100644 index 9de24f1c229e4c856806e125b8f47ec591acc47a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/binopWide.S +++ /dev/null @@ -1,30 +0,0 @@ -%default {"preinstr":"", "instr":"add x0, x1, x2", "result":"x0", "r1":"x1", "r2":"x2", "chkzero":"0"} - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = x1 op x2". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than x0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, rem-double - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - lsr w2, w0, #8 // w2<- CC - and w1, w0, #255 // w1<- BB - GET_VREG_WIDE $r2, w2 // w2<- vCC - GET_VREG_WIDE $r1, w1 // w1<- vBB - .if $chkzero - cbz $r2, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - $preinstr - $instr // $result<- op, w0-w4 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE $result, w4 // vAA<- $result - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ diff --git a/runtime/interpreter/mterp/arm64/binopWide2addr.S b/runtime/interpreter/mterp/arm64/binopWide2addr.S deleted file mode 100644 index d9927a2ca88fa64d4a7ce345a530359800475726..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/binopWide2addr.S +++ /dev/null @@ -1,29 +0,0 @@ -%default {"preinstr":"", "instr":"add x0, x0, x1", "r0":"x0", "r1":"x1", "chkzero":"0"} - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "x0 = x0 op x1". - * This must not be a function call, as we keep w2 live across it. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr - */ - /* binop/2addr vA, vB */ - lsr w1, wINST, #12 // w1<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG_WIDE $r1, w1 // x1<- vB - GET_VREG_WIDE $r0, w2 // x0<- vA - .if $chkzero - cbz $r1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - $preinstr - $instr // result<- op - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE $r0, w2 // vAA<- result - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ diff --git a/runtime/interpreter/mterp/arm64/close_cfi.S b/runtime/interpreter/mterp/arm64/close_cfi.S deleted file mode 100644 index 7ba0486079e56f3778b6daeec65f14b91b5767a2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/close_cfi.S +++ /dev/null @@ -1,4 +0,0 @@ -// Close out the cfi info. We're treating mterp as a single function. - -END ExecuteMterpImpl - diff --git a/runtime/interpreter/mterp/arm64/const.S b/runtime/interpreter/mterp/arm64/const.S deleted file mode 100644 index 6f82bbf0ba113d6ca49c3f7dcb63448cc88f91ae..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/const.S +++ /dev/null @@ -1,17 +0,0 @@ -%default { "helper":"UndefinedConstHandler" } - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern $helper - EXPORT_PC - FETCH w0, 1 // w0<- BBBB - lsr w1, wINST, #8 // w1<- AA - add x2, xFP, #OFF_FP_SHADOWFRAME - mov x3, xSELF - bl $helper // (index, tgt_reg, shadow_frame, self) - PREFETCH_INST 2 // load rINST - cbnz w0, MterpPossibleException // let reference interpreter deal with it. - ADVANCE 2 // advance rPC - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/control_flow.S b/runtime/interpreter/mterp/arm64/control_flow.S new file mode 100644 index 0000000000000000000000000000000000000000..b634c9812c4ae532ffb5d5fa0d458fc4578bb25c --- /dev/null +++ b/runtime/interpreter/mterp/arm64/control_flow.S @@ -0,0 +1,223 @@ +%def bincmp(condition=""): + /* + * Generic two-operand compare-and-branch operation. Provide a "condition" + * fragment that specifies the comparison to perform. + * + * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le + */ + /* if-cmp vA, vB, +CCCC */ + lsr w1, wINST, #12 // w1<- B + ubfx w0, wINST, #8, #4 // w0<- A + GET_VREG w3, w1 // w3<- vB + GET_VREG w2, w0 // w2<- vA + FETCH_S wINST, 1 // wINST<- branch offset, in code units + cmp w2, w3 // compare (vA, vB) + b.${condition} MterpCommonTakenBranchNoFlags + cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? + b.eq .L_check_not_taken_osr + FETCH_ADVANCE_INST 2 + GET_INST_OPCODE ip // extract opcode from wINST + GOTO_OPCODE ip // jump to next instruction + +%def zcmp(compare="1", branch=""): + /* + * Generic one-operand compare-and-branch operation. Provide a "condition" + * fragment that specifies the comparison to perform. + * + * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez + */ + /* if-cmp vAA, +BBBB */ + lsr w0, wINST, #8 // w0<- AA + GET_VREG w2, w0 // w2<- vAA + FETCH_S wINST, 1 // w1<- branch offset, in code units + .if ${compare} + cmp w2, #0 // compare (vA, 0) + .endif + ${branch} MterpCommonTakenBranchNoFlags + cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? + b.eq .L_check_not_taken_osr + FETCH_ADVANCE_INST 2 + GET_INST_OPCODE ip // extract opcode from wINST + GOTO_OPCODE ip // jump to next instruction + +%def op_goto(): + /* + * Unconditional branch, 8-bit offset. + * + * The branch distance is a signed code-unit offset, which we need to + * double to get a byte offset. + */ + /* goto +AA */ + sbfx wINST, wINST, #8, #8 // wINST<- ssssssAA (sign-extended) + b MterpCommonTakenBranchNoFlags + +%def op_goto_16(): + /* + * Unconditional branch, 16-bit offset. + * + * The branch distance is a signed code-unit offset, which we need to + * double to get a byte offset. + */ + /* goto/16 +AAAA */ + FETCH_S wINST, 1 // wINST<- ssssAAAA (sign-extended) + b MterpCommonTakenBranchNoFlags + +%def op_goto_32(): + /* + * Unconditional branch, 32-bit offset. + * + * The branch distance is a signed code-unit offset, which we need to + * double to get a byte offset. + * + * Unlike most opcodes, this one is allowed to branch to itself, so + * our "backward branch" test must be "<=0" instead of "<0". Because + * we need the V bit set, we'll use an adds to convert from Dalvik + * offset to byte offset. + */ + /* goto/32 +AAAAAAAA */ + FETCH w0, 1 // w0<- aaaa (lo) + FETCH w1, 2 // w1<- AAAA (hi) + orr wINST, w0, w1, lsl #16 // wINST<- AAAAaaaa + b MterpCommonTakenBranchNoFlags + +%def op_if_eq(): +% bincmp(condition="eq") + +%def op_if_eqz(): +% zcmp(compare="0", branch="cbz w2,") + +%def op_if_ge(): +% bincmp(condition="ge") + +%def op_if_gez(): +% zcmp(compare="0", branch="tbz w2, #31,") + +%def op_if_gt(): +% bincmp(condition="gt") + +%def op_if_gtz(): +% zcmp(branch="b.gt") + +%def op_if_le(): +% bincmp(condition="le") + +%def op_if_lez(): +% zcmp(branch="b.le") + +%def op_if_lt(): +% bincmp(condition="lt") + +%def op_if_ltz(): +% zcmp(compare="0", branch="tbnz w2, #31,") + +%def op_if_ne(): +% bincmp(condition="ne") + +%def op_if_nez(): +% zcmp(compare="0", branch="cbnz w2,") + +%def op_packed_switch(func="MterpDoPackedSwitch"): + /* + * Handle a packed-switch or sparse-switch instruction. In both cases + * we decode it and hand it off to a helper function. + * + * We don't really expect backward branches in a switch statement, but + * they're perfectly legal, so we check for them here. + * + * for: packed-switch, sparse-switch + */ + /* op vAA, +BBBB */ + FETCH w0, 1 // x0<- 000000000000bbbb (lo) + FETCH_S x1, 2 // x1<- ssssssssssssBBBB (hi) + lsr w3, wINST, #8 // w3<- AA + orr x0, x0, x1, lsl #16 // x0<- ssssssssBBBBbbbb + GET_VREG w1, w3 // w1<- vAA + add x0, xPC, x0, lsl #1 // x0<- PC + ssssssssBBBBbbbb*2 + bl $func // w0<- code-unit branch offset + sxtw xINST, w0 + b MterpCommonTakenBranchNoFlags + +%def op_return(): + /* + * Return a 32-bit value. + * + * for: return, return-object + */ + /* op vAA */ + .extern MterpThreadFenceForConstructor + bl MterpThreadFenceForConstructor + ldr w7, [xSELF, #THREAD_FLAGS_OFFSET] + mov x0, xSELF + ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST + b.ne .L${opcode}_check +.L${opcode}_return: + lsr w2, wINST, #8 // r2<- AA + GET_VREG w0, w2 // r0<- vAA + b MterpReturn +.L${opcode}_check: + bl MterpSuspendCheck // (self) + b .L${opcode}_return + +%def op_return_object(): +% op_return() + +%def op_return_void(): + .extern MterpThreadFenceForConstructor + bl MterpThreadFenceForConstructor + ldr w7, [xSELF, #THREAD_FLAGS_OFFSET] + mov x0, xSELF + ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST + b.ne .L${opcode}_check +.L${opcode}_return: + mov x0, #0 + b MterpReturn +.L${opcode}_check: + bl MterpSuspendCheck // (self) + b .L${opcode}_return + +%def op_return_void_no_barrier(): + ldr w7, [xSELF, #THREAD_FLAGS_OFFSET] + mov x0, xSELF + ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST + b.ne .L${opcode}_check +.L${opcode}_return: + mov x0, #0 + b MterpReturn +.L${opcode}_check: + bl MterpSuspendCheck // (self) + b .L${opcode}_return + +%def op_return_wide(): + /* + * Return a 64-bit value. + */ + /* return-wide vAA */ + /* op vAA */ + .extern MterpThreadFenceForConstructor + bl MterpThreadFenceForConstructor + ldr w7, [xSELF, #THREAD_FLAGS_OFFSET] + mov x0, xSELF + ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST + b.ne .L${opcode}_check +.L${opcode}_return: + lsr w2, wINST, #8 // w2<- AA + GET_VREG_WIDE x0, w2 // x0<- vAA + b MterpReturn +.L${opcode}_check: + bl MterpSuspendCheck // (self) + b .L${opcode}_return + +%def op_sparse_switch(): +% op_packed_switch(func="MterpDoSparseSwitch") + +%def op_throw(): + /* + * Throw an exception object in the current thread. + */ + /* throw vAA */ + EXPORT_PC + lsr w2, wINST, #8 // r2<- AA + GET_VREG w1, w2 // r1<- vAA (exception object) + cbz w1, common_errNullObject + str x1, [xSELF, #THREAD_EXCEPTION_OFFSET] // thread->exception<- obj + b MterpException diff --git a/runtime/interpreter/mterp/arm64/entry.S b/runtime/interpreter/mterp/arm64/entry.S deleted file mode 100644 index cf38a2992d5c5554d5fb4560693090ebf2ed4161..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/entry.S +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - .text - -/* - * Interpreter entry point. - * On entry: - * x0 Thread* self/ - * x1 insns_ - * x2 ShadowFrame - * x3 JValue* result_register - * - */ -ENTRY ExecuteMterpImpl - SAVE_TWO_REGS_INCREASE_FRAME xPROFILE, x27, 80 - SAVE_TWO_REGS xIBASE, xREFS, 16 - SAVE_TWO_REGS xSELF, xINST, 32 - SAVE_TWO_REGS xPC, xFP, 48 - SAVE_TWO_REGS fp, lr, 64 - add fp, sp, #64 - - /* Remember the return register */ - str x3, [x2, #SHADOWFRAME_RESULT_REGISTER_OFFSET] - - /* Remember the dex instruction pointer */ - str x1, [x2, #SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET] - - /* set up "named" registers */ - mov xSELF, x0 - ldr w0, [x2, #SHADOWFRAME_NUMBER_OF_VREGS_OFFSET] - add xFP, x2, #SHADOWFRAME_VREGS_OFFSET // point to vregs. - add xREFS, xFP, w0, lsl #2 // point to reference array in shadow frame - ldr w0, [x2, #SHADOWFRAME_DEX_PC_OFFSET] // Get starting dex_pc. - add xPC, x1, w0, lsl #1 // Create direct pointer to 1st dex opcode - CFI_DEFINE_DEX_PC_WITH_OFFSET(CFI_TMP, CFI_DEX, 0) - EXPORT_PC - - /* Starting ibase */ - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] - - /* Set up for backwards branches & osr profiling */ - ldr x0, [xFP, #OFF_FP_METHOD] - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xSELF - bl MterpSetUpHotnessCountdown - mov wPROFILE, w0 // Starting hotness countdown to xPROFILE - - /* start executing the instruction at rPC */ - FETCH_INST // load wINST from rPC - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - /* NOTE: no fallthrough */ diff --git a/runtime/interpreter/mterp/arm64/fallback.S b/runtime/interpreter/mterp/arm64/fallback.S deleted file mode 100644 index 44e7e1220d841247a99eb6ff9ae11f11f0a1ea8e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/fallback.S +++ /dev/null @@ -1,3 +0,0 @@ -/* Transfer stub to alternate interpreter */ - b MterpFallback - diff --git a/runtime/interpreter/mterp/arm64/fbinop.S b/runtime/interpreter/mterp/arm64/fbinop.S deleted file mode 100644 index 926d0783dad22421833383a35b8646cdf2774765..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/fbinop.S +++ /dev/null @@ -1,19 +0,0 @@ -%default {} - /*: - * Generic 32-bit floating-point operation. - * - * For: add-float, sub-float, mul-float, div-float - * form: s0, s0, s1 - */ - /* floatop vAA, vBB, vCC */ - FETCH w0, 1 // r0<- CCBB - lsr w1, w0, #8 // r2<- CC - and w0, w0, #255 // r1<- BB - GET_VREG s1, w1 - GET_VREG s0, w0 - $instr // s0<- op - lsr w1, wINST, #8 // r1<- AA - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG s0, w1 - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/fbinop2addr.S b/runtime/interpreter/mterp/arm64/fbinop2addr.S deleted file mode 100644 index 04236adb812dc7e3cbe3548dabb810d3ffb7e013..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/fbinop2addr.S +++ /dev/null @@ -1,17 +0,0 @@ - /* - * Generic 32-bit floating point "/2addr" binary operation. Provide - * an "instr" line that specifies an instruction that performs - * "s2 = s0 op s1". - * - * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr - */ - /* binop/2addr vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG s1, w3 - GET_VREG s0, w9 - $instr // s2<- op - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG s2, w9 - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/fcmp.S b/runtime/interpreter/mterp/arm64/fcmp.S deleted file mode 100644 index cad63189af3c93e261618dd14257990b89eab532..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/fcmp.S +++ /dev/null @@ -1,19 +0,0 @@ -%default {"wide":"", "r1":"s1", "r2":"s2", "cond":"lt"} - /* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - */ - /* op vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - and w2, w0, #255 // w2<- BB - lsr w3, w0, #8 // w3<- CC - GET_VREG$wide $r1, w2 - GET_VREG$wide $r2, w3 - fcmp $r1, $r2 - cset w0, ne - cneg w0, w0, $cond - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w4 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/field.S b/runtime/interpreter/mterp/arm64/field.S deleted file mode 100644 index 631c8d191bb0a4d7c9f03e6546b656968b058110..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/field.S +++ /dev/null @@ -1,15 +0,0 @@ -%default { } - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern $helper - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl $helper - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/floating_point.S b/runtime/interpreter/mterp/arm64/floating_point.S new file mode 100644 index 0000000000000000000000000000000000000000..04ca6949ff2c7aab5c9d21cd711ce764addc21c4 --- /dev/null +++ b/runtime/interpreter/mterp/arm64/floating_point.S @@ -0,0 +1,269 @@ +%def fbinop(instr=""): + /*: + * Generic 32-bit floating-point operation. + * + * For: add-float, sub-float, mul-float, div-float + * form: s0, s0, s1 + */ + /* floatop vAA, vBB, vCC */ + FETCH w0, 1 // r0<- CCBB + lsr w1, w0, #8 // r2<- CC + and w0, w0, #255 // r1<- BB + GET_VREG s1, w1 + GET_VREG s0, w0 + $instr // s0<- op + lsr w1, wINST, #8 // r1<- AA + FETCH_ADVANCE_INST 2 // advance rPC, load rINST + GET_INST_OPCODE ip // extract opcode from rINST + SET_VREG s0, w1 + GOTO_OPCODE ip // jump to next instruction + +%def fbinop2addr(instr=""): + /* + * Generic 32-bit floating point "/2addr" binary operation. Provide + * an "instr" line that specifies an instruction that performs + * "s2 = s0 op s1". + * + * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr + */ + /* binop/2addr vA, vB */ + lsr w3, wINST, #12 // w3<- B + ubfx w9, wINST, #8, #4 // w9<- A + GET_VREG s1, w3 + GET_VREG s0, w9 + $instr // s2<- op + FETCH_ADVANCE_INST 1 // advance rPC, load rINST + GET_INST_OPCODE ip // extract opcode from rINST + SET_VREG s2, w9 + GOTO_OPCODE ip // jump to next instruction + +%def fcmp(wide="", r1="s1", r2="s2", cond="lt"): + /* + * Compare two floating-point values. Puts 0, 1, or -1 into the + * destination register based on the results of the comparison. + */ + /* op vAA, vBB, vCC */ + FETCH w0, 1 // w0<- CCBB + lsr w4, wINST, #8 // w4<- AA + and w2, w0, #255 // w2<- BB + lsr w3, w0, #8 // w3<- CC + GET_VREG$wide $r1, w2 + GET_VREG$wide $r2, w3 + fcmp $r1, $r2 + cset w0, ne + cneg w0, w0, $cond + FETCH_ADVANCE_INST 2 // advance rPC, load rINST + GET_INST_OPCODE ip // extract opcode from rINST + SET_VREG w0, w4 // vAA<- w0 + GOTO_OPCODE ip // jump to next instruction + +%def funopNarrow(srcreg="s0", tgtreg="d0", instr=""): + /* + * Generic 32bit-to-32bit floating point unary operation. Provide an + * "instr" line that specifies an instruction that performs "$tgtreg = op $srcreg". + * + * For: int-to-float, float-to-int + * TODO: refactor all of the conversions - parameterize width and use same template. + */ + /* unop vA, vB */ + lsr w3, wINST, #12 // w3<- B + ubfx w4, wINST, #8, #4 // w4<- A + GET_VREG $srcreg, w3 + FETCH_ADVANCE_INST 1 // advance rPC, load wINST + $instr // d0<- op + GET_INST_OPCODE ip // extract opcode from wINST + SET_VREG $tgtreg, w4 // vA<- d0 + GOTO_OPCODE ip // jump to next instruction + +%def funopNarrower(srcreg="s0", tgtreg="d0", instr=""): + /* + * Generic 64bit-to-32bit floating point unary operation. Provide an + * "instr" line that specifies an instruction that performs "$tgtreg = op $srcreg". + * + * For: int-to-double, float-to-double, float-to-long + */ + /* unop vA, vB */ + lsr w3, wINST, #12 // w3<- B + ubfx w4, wINST, #8, #4 // w4<- A + GET_VREG_WIDE $srcreg, w3 + FETCH_ADVANCE_INST 1 // advance rPC, load wINST + $instr // d0<- op + GET_INST_OPCODE ip // extract opcode from wINST + SET_VREG $tgtreg, w4 // vA<- d0 + GOTO_OPCODE ip // jump to next instruction + +%def funopWide(srcreg="s0", tgtreg="d0", instr=""): + /* + * Generic 64bit-to-64bit floating point unary operation. Provide an + * "instr" line that specifies an instruction that performs "$tgtreg = op $srcreg". + * + * For: long-to-double, double-to-long + */ + /* unop vA, vB */ + lsr w3, wINST, #12 // w3<- B + ubfx w4, wINST, #8, #4 // w4<- A + GET_VREG_WIDE $srcreg, w3 + FETCH_ADVANCE_INST 1 // advance rPC, load wINST + $instr // d0<- op + GET_INST_OPCODE ip // extract opcode from wINST + SET_VREG_WIDE $tgtreg, w4 // vA<- d0 + GOTO_OPCODE ip // jump to next instruction + +%def funopWider(srcreg="s0", tgtreg="d0", instr=""): + /* + * Generic 32bit-to-64bit floating point unary operation. Provide an + * "instr" line that specifies an instruction that performs "$tgtreg = op $srcreg". + * + * For: int-to-double, float-to-double, float-to-long + */ + /* unop vA, vB */ + lsr w3, wINST, #12 // w3<- B + ubfx w4, wINST, #8, #4 // w4<- A + GET_VREG $srcreg, w3 + FETCH_ADVANCE_INST 1 // advance rPC, load wINST + $instr // d0<- op + GET_INST_OPCODE ip // extract opcode from wINST + SET_VREG_WIDE $tgtreg, w4 // vA<- d0 + GOTO_OPCODE ip // jump to next instruction + +%def op_add_double(): +% binopWide(instr="fadd d0, d1, d2", result="d0", r1="d1", r2="d2") + +%def op_add_double_2addr(): +% binopWide2addr(instr="fadd d0, d0, d1", r0="d0", r1="d1") + +%def op_add_float(): +% fbinop(instr="fadd s0, s0, s1") + +%def op_add_float_2addr(): +% fbinop2addr(instr="fadd s2, s0, s1") + +%def op_cmpg_double(): +% fcmp(wide="_WIDE", r1="d1", r2="d2", cond="cc") + +%def op_cmpg_float(): +% fcmp(wide="", r1="s1", r2="s2", cond="cc") + +%def op_cmpl_double(): +% fcmp(wide="_WIDE", r1="d1", r2="d2", cond="lt") + +%def op_cmpl_float(): +% fcmp(wide="", r1="s1", r2="s2", cond="lt") + +%def op_div_double(): +% binopWide(instr="fdiv d0, d1, d2", result="d0", r1="d1", r2="d2") + +%def op_div_double_2addr(): +% binopWide2addr(instr="fdiv d0, d0, d1", r0="d0", r1="d1") + +%def op_div_float(): +% fbinop(instr="fdiv s0, s0, s1") + +%def op_div_float_2addr(): +% fbinop2addr(instr="fdiv s2, s0, s1") + +%def op_double_to_float(): +% funopNarrower(instr="fcvt s0, d0", srcreg="d0", tgtreg="s0") + +%def op_double_to_int(): +% funopNarrower(instr="fcvtzs w0, d0", srcreg="d0", tgtreg="w0") + +%def op_double_to_long(): +% funopWide(instr="fcvtzs x0, d0", srcreg="d0", tgtreg="x0") + +%def op_float_to_double(): +% funopWider(instr="fcvt d0, s0", srcreg="s0", tgtreg="d0") + +%def op_float_to_int(): +% funopNarrow(instr="fcvtzs w0, s0", srcreg="s0", tgtreg="w0") + +%def op_float_to_long(): +% funopWider(instr="fcvtzs x0, s0", srcreg="s0", tgtreg="x0") + +%def op_int_to_double(): +% funopWider(instr="scvtf d0, w0", srcreg="w0", tgtreg="d0") + +%def op_int_to_float(): +% funopNarrow(instr="scvtf s0, w0", srcreg="w0", tgtreg="s0") + +%def op_long_to_double(): +% funopWide(instr="scvtf d0, x0", srcreg="x0", tgtreg="d0") + +%def op_long_to_float(): +% funopNarrower(instr="scvtf s0, x0", srcreg="x0", tgtreg="s0") + +%def op_mul_double(): +% binopWide(instr="fmul d0, d1, d2", result="d0", r1="d1", r2="d2") + +%def op_mul_double_2addr(): +% binopWide2addr(instr="fmul d0, d0, d1", r0="d0", r1="d1") + +%def op_mul_float(): +% fbinop(instr="fmul s0, s0, s1") + +%def op_mul_float_2addr(): +% fbinop2addr(instr="fmul s2, s0, s1") + +%def op_neg_double(): +% unopWide(instr="eor x0, x0, #0x8000000000000000") + +%def op_neg_float(): +% unop(instr="eor w0, w0, #0x80000000") + +%def op_rem_double(): + /* rem vAA, vBB, vCC */ + FETCH w0, 1 // w0<- CCBB + lsr w2, w0, #8 // w2<- CC + and w1, w0, #255 // w1<- BB + GET_VREG_WIDE d1, w2 // d1<- vCC + GET_VREG_WIDE d0, w1 // d0<- vBB + bl fmod + lsr w4, wINST, #8 // w4<- AA + FETCH_ADVANCE_INST 2 // advance rPC, load rINST + GET_INST_OPCODE ip // extract opcode from rINST + SET_VREG_WIDE d0, w4 // vAA<- result + GOTO_OPCODE ip // jump to next instruction + /* 11-14 instructions */ + +%def op_rem_double_2addr(): + /* rem vA, vB */ + lsr w1, wINST, #12 // w1<- B + ubfx w2, wINST, #8, #4 // w2<- A + GET_VREG_WIDE d1, w1 // d1<- vB + GET_VREG_WIDE d0, w2 // d0<- vA + bl fmod + ubfx w2, wINST, #8, #4 // w2<- A (need to reload - killed across call) + FETCH_ADVANCE_INST 1 // advance rPC, load rINST + GET_INST_OPCODE ip // extract opcode from rINST + SET_VREG_WIDE d0, w2 // vAA<- result + GOTO_OPCODE ip // jump to next instruction + /* 10-13 instructions */ + +%def op_rem_float(): +/* EABI doesn't define a float remainder function, but libm does */ +% fbinop(instr="bl fmodf") + +%def op_rem_float_2addr(): + /* rem vA, vB */ + lsr w3, wINST, #12 // w3<- B + ubfx w9, wINST, #8, #4 // w9<- A + GET_VREG s1, w3 + GET_VREG s0, w9 + bl fmodf + ubfx w9, wINST, #8, #4 // w9<- A + FETCH_ADVANCE_INST 1 // advance rPC, load rINST + GET_INST_OPCODE ip // extract opcode from rINST + SET_VREG s0, w9 + GOTO_OPCODE ip // jump to next instruction + +%def op_sub_double(): +% binopWide(instr="fsub d0, d1, d2", result="d0", r1="d1", r2="d2") + +%def op_sub_double_2addr(): +% binopWide2addr(instr="fsub d0, d0, d1", r0="d0", r1="d1") + +%def op_sub_float(): +% fbinop(instr="fsub s0, s0, s1") + +%def op_sub_float_2addr(): +% fbinop2addr(instr="fsub s2, s0, s1") diff --git a/runtime/interpreter/mterp/arm64/footer.S b/runtime/interpreter/mterp/arm64/footer.S deleted file mode 100644 index 0ce35439116b9f46daebafda83338c9fb4736f53..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/footer.S +++ /dev/null @@ -1,306 +0,0 @@ -/* - * =========================================================================== - * Common subroutines and data - * =========================================================================== - */ - - -/* - * We've detected a condition that will result in an exception, but the exception - * has not yet been thrown. Just bail out to the reference interpreter to deal with it. - * TUNING: for consistency, we may want to just go ahead and handle these here. - */ -common_errDivideByZero: - EXPORT_PC -#if MTERP_LOGGING - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - bl MterpLogDivideByZeroException -#endif - b MterpCommonFallback - -common_errArrayIndex: - EXPORT_PC -#if MTERP_LOGGING - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - bl MterpLogArrayIndexException -#endif - b MterpCommonFallback - -common_errNegativeArraySize: - EXPORT_PC -#if MTERP_LOGGING - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - bl MterpLogNegativeArraySizeException -#endif - b MterpCommonFallback - -common_errNoSuchMethod: - EXPORT_PC -#if MTERP_LOGGING - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - bl MterpLogNoSuchMethodException -#endif - b MterpCommonFallback - -common_errNullObject: - EXPORT_PC -#if MTERP_LOGGING - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - bl MterpLogNullObjectException -#endif - b MterpCommonFallback - -common_exceptionThrown: - EXPORT_PC -#if MTERP_LOGGING - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - bl MterpLogExceptionThrownException -#endif - b MterpCommonFallback - -MterpSuspendFallback: - EXPORT_PC -#if MTERP_LOGGING - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - ldr x2, [xSELF, #THREAD_FLAGS_OFFSET] - bl MterpLogSuspendFallback -#endif - b MterpCommonFallback - -/* - * If we're here, something is out of the ordinary. If there is a pending - * exception, handle it. Otherwise, roll back and retry with the reference - * interpreter. - */ -MterpPossibleException: - ldr x0, [xSELF, #THREAD_EXCEPTION_OFFSET] - cbz x0, MterpFallback // If not, fall back to reference interpreter. - /* intentional fallthrough - handle pending exception. */ -/* - * On return from a runtime helper routine, we've found a pending exception. - * Can we handle it here - or need to bail out to caller? - * - */ -MterpException: - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - bl MterpHandleException // (self, shadow_frame) - cbz w0, MterpExceptionReturn // no local catch, back to caller. - ldr x0, [xFP, #OFF_FP_DEX_INSTRUCTIONS] - ldr w1, [xFP, #OFF_FP_DEX_PC] - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] - add xPC, x0, x1, lsl #1 // generate new dex_pc_ptr - /* Do we need to switch interpreters? */ - bl MterpShouldSwitchInterpreters - cbnz w0, MterpFallback - /* resume execution at catch block */ - EXPORT_PC - FETCH_INST - GET_INST_OPCODE ip - GOTO_OPCODE ip - /* NOTE: no fallthrough */ -/* - * Common handling for branches with support for Jit profiling. - * On entry: - * wINST <= signed offset - * wPROFILE <= signed hotness countdown (expanded to 32 bits) - * condition bits <= set to establish sign of offset (use "NoFlags" entry if not) - * - * We have quite a few different cases for branch profiling, OSR detection and - * suspend check support here. - * - * Taken backward branches: - * If profiling active, do hotness countdown and report if we hit zero. - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * Is there a pending suspend request? If so, suspend. - * - * Taken forward branches and not-taken backward branches: - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * - * Our most common case is expected to be a taken backward branch with active jit profiling, - * but no full OSR check and no pending suspend request. - * Next most common case is not-taken branch with no full OSR check. - * - */ -MterpCommonTakenBranchNoFlags: - cmp wINST, #0 - b.gt .L_forward_branch // don't add forward branches to hotness - tbnz wPROFILE, #31, .L_no_count_backwards // go if negative - subs wPROFILE, wPROFILE, #1 // countdown - b.eq .L_add_batch // counted down to zero - report -.L_resume_backward_branch: - ldr lr, [xSELF, #THREAD_FLAGS_OFFSET] - add w2, wINST, wINST // w2<- byte offset - FETCH_ADVANCE_INST_RB w2 // update rPC, load wINST - REFRESH_IBASE - ands lr, lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - b.ne .L_suspend_request_pending - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - -.L_suspend_request_pending: - EXPORT_PC - mov x0, xSELF - bl MterpSuspendCheck // (self) - cbnz x0, MterpFallback - REFRESH_IBASE // might have changed during suspend - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - -.L_no_count_backwards: - cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? - b.ne .L_resume_backward_branch - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xINST - EXPORT_PC - bl MterpMaybeDoOnStackReplacement // (self, shadow_frame, offset) - cbnz x0, MterpOnStackReplacement - b .L_resume_backward_branch - -.L_forward_branch: - cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? - b.eq .L_check_osr_forward -.L_resume_forward_branch: - add w2, wINST, wINST // w2<- byte offset - FETCH_ADVANCE_INST_RB w2 // update rPC, load wINST - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - -.L_check_osr_forward: - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xINST - EXPORT_PC - bl MterpMaybeDoOnStackReplacement // (self, shadow_frame, offset) - cbnz x0, MterpOnStackReplacement - b .L_resume_forward_branch - -.L_add_batch: - add x1, xFP, #OFF_FP_SHADOWFRAME - strh wPROFILE, [x1, #SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET] - ldr x0, [xFP, #OFF_FP_METHOD] - mov x2, xSELF - bl MterpAddHotnessBatch // (method, shadow_frame, self) - mov wPROFILE, w0 // restore new hotness countdown to wPROFILE - b .L_no_count_backwards - -/* - * Entered from the conditional branch handlers when OSR check request active on - * not-taken path. All Dalvik not-taken conditional branch offsets are 2. - */ -.L_check_not_taken_osr: - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, #2 - EXPORT_PC - bl MterpMaybeDoOnStackReplacement // (self, shadow_frame, offset) - cbnz x0, MterpOnStackReplacement - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - - -/* - * Check for suspend check request. Assumes wINST already loaded, xPC advanced and - * still needs to get the opcode and branch to it, and flags are in lr. - */ -MterpCheckSuspendAndContinue: - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh xIBASE - ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - b.ne check1 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction -check1: - EXPORT_PC - mov x0, xSELF - bl MterpSuspendCheck // (self) - cbnz x0, MterpFallback // Something in the environment changed, switch interpreters - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - -/* - * On-stack replacement has happened, and now we've returned from the compiled method. - */ -MterpOnStackReplacement: -#if MTERP_LOGGING - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - sxtw x2, wINST - bl MterpLogOSR -#endif - mov x0, #1 // Signal normal return - b MterpDone - -/* - * Bail out to reference interpreter. - */ -MterpFallback: - EXPORT_PC -#if MTERP_LOGGING - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - bl MterpLogFallback -#endif -MterpCommonFallback: - mov x0, #0 // signal retry with reference interpreter. - b MterpDone - -/* - * We pushed some registers on the stack in ExecuteMterpImpl, then saved - * SP and LR. Here we restore SP, restore the registers, and then restore - * LR to PC. - * - * On entry: - * uint32_t* xFP (should still be live, pointer to base of vregs) - */ -MterpExceptionReturn: - mov x0, #1 // signal return to caller. - b MterpDone -MterpReturn: - ldr x2, [xFP, #OFF_FP_RESULT_REGISTER] - str x0, [x2] - mov x0, #1 // signal return to caller. -MterpDone: -/* - * At this point, we expect wPROFILE to be non-zero. If negative, hotness is disabled or we're - * checking for OSR. If greater than zero, we might have unreported hotness to register - * (the difference between the ending wPROFILE and the cached hotness counter). wPROFILE - * should only reach zero immediately after a hotness decrement, and is then reset to either - * a negative special state or the new non-zero countdown value. - */ - cmp wPROFILE, #0 - bgt MterpProfileActive // if > 0, we may have some counts to report. - .cfi_remember_state - RESTORE_TWO_REGS fp, lr, 64 - RESTORE_TWO_REGS xPC, xFP, 48 - RESTORE_TWO_REGS xSELF, xINST, 32 - RESTORE_TWO_REGS xIBASE, xREFS, 16 - RESTORE_TWO_REGS_DECREASE_FRAME xPROFILE, x27, 80 - ret - .cfi_restore_state // Reset unwind info so following code unwinds. - .cfi_def_cfa_offset 80 // workaround for clang bug: 31975598 - -MterpProfileActive: - mov xINST, x0 // stash return value - /* Report cached hotness counts */ - ldr x0, [xFP, #OFF_FP_METHOD] - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xSELF - strh wPROFILE, [x1, #SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET] - bl MterpAddHotnessBatch // (method, shadow_frame, self) - mov x0, xINST // restore return value - RESTORE_TWO_REGS fp, lr, 64 - RESTORE_TWO_REGS xPC, xFP, 48 - RESTORE_TWO_REGS xSELF, xINST, 32 - RESTORE_TWO_REGS xIBASE, xREFS, 16 - RESTORE_TWO_REGS_DECREASE_FRAME xPROFILE, x27, 80 - ret - diff --git a/runtime/interpreter/mterp/arm64/funopNarrow.S b/runtime/interpreter/mterp/arm64/funopNarrow.S deleted file mode 100644 index aed830bc23b0d5294c5d234249a8dfaa79be5596..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/funopNarrow.S +++ /dev/null @@ -1,17 +0,0 @@ -%default {"srcreg":"s0", "tgtreg":"d0"} - /* - * Generic 32bit-to-32bit floating point unary operation. Provide an - * "instr" line that specifies an instruction that performs "$tgtreg = op $srcreg". - * - * For: int-to-float, float-to-int - * TODO: refactor all of the conversions - parameterize width and use same template. - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w4, wINST, #8, #4 // w4<- A - GET_VREG $srcreg, w3 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - $instr // d0<- op - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG $tgtreg, w4 // vA<- d0 - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/funopNarrower.S b/runtime/interpreter/mterp/arm64/funopNarrower.S deleted file mode 100644 index 6fddfea979f357b311f8e2e2c818f5c7c35dbb72..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/funopNarrower.S +++ /dev/null @@ -1,16 +0,0 @@ -%default {"srcreg":"s0", "tgtreg":"d0"} - /* - * Generic 64bit-to-32bit floating point unary operation. Provide an - * "instr" line that specifies an instruction that performs "$tgtreg = op $srcreg". - * - * For: int-to-double, float-to-double, float-to-long - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w4, wINST, #8, #4 // w4<- A - GET_VREG_WIDE $srcreg, w3 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - $instr // d0<- op - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG $tgtreg, w4 // vA<- d0 - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/funopWide.S b/runtime/interpreter/mterp/arm64/funopWide.S deleted file mode 100644 index 409e26b6ecc42af2c45f4a0044324c6683d01080..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/funopWide.S +++ /dev/null @@ -1,16 +0,0 @@ -%default {"srcreg":"s0", "tgtreg":"d0"} - /* - * Generic 64bit-to-64bit floating point unary operation. Provide an - * "instr" line that specifies an instruction that performs "$tgtreg = op $srcreg". - * - * For: long-to-double, double-to-long - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w4, wINST, #8, #4 // w4<- A - GET_VREG_WIDE $srcreg, w3 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - $instr // d0<- op - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG_WIDE $tgtreg, w4 // vA<- d0 - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/funopWider.S b/runtime/interpreter/mterp/arm64/funopWider.S deleted file mode 100644 index 4c91ebcdc64254487c7f475bc66f9c04f1094003..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/funopWider.S +++ /dev/null @@ -1,16 +0,0 @@ -%default {"srcreg":"s0", "tgtreg":"d0"} - /* - * Generic 32bit-to-64bit floating point unary operation. Provide an - * "instr" line that specifies an instruction that performs "$tgtreg = op $srcreg". - * - * For: int-to-double, float-to-double, float-to-long - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w4, wINST, #8, #4 // w4<- A - GET_VREG $srcreg, w3 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - $instr // d0<- op - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG_WIDE $tgtreg, w4 // vA<- d0 - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/header.S b/runtime/interpreter/mterp/arm64/header.S deleted file mode 100644 index 072280426560a32c22ca415b4f237f49c23a7332..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/header.S +++ /dev/null @@ -1,353 +0,0 @@ -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - Art assembly interpreter notes: - - First validate assembly code by implementing ExecuteXXXImpl() style body (doesn't - handle invoke, allows higher-level code to create frame & shadow frame. - - Once that's working, support direct entry code & eliminate shadow frame (and - excess locals allocation. - - Some (hopefully) temporary ugliness. We'll treat xFP as pointing to the - base of the vreg array within the shadow frame. Access the other fields, - dex_pc_, method_ and number_of_vregs_ via negative offsets. For now, we'll continue - the shadow frame mechanism of double-storing object references - via xFP & - number_of_vregs_. - - */ - -/* -ARM64 Runtime register usage conventions. - - r0 : w0 is 32-bit return register and x0 is 64-bit. - r0-r7 : Argument registers. - r8-r15 : Caller save registers (used as temporary registers). - r16-r17: Also known as ip0-ip1, respectively. Used as scratch registers by - the linker, by the trampolines and other stubs (the backend uses - these as temporary registers). - r18 : Caller save register (used as temporary register). - r19 : Pointer to thread-local storage. - r20-r29: Callee save registers. - r30 : (lr) is reserved (the link register). - rsp : (sp) is reserved (the stack pointer). - rzr : (zr) is reserved (the zero register). - - Floating-point registers - v0-v31 - - v0 : s0 is return register for singles (32-bit) and d0 for doubles (64-bit). - This is analogous to the C/C++ (hard-float) calling convention. - v0-v7 : Floating-point argument registers in both Dalvik and C/C++ conventions. - Also used as temporary and codegen scratch registers. - - v0-v7 and v16-v31 : trashed across C calls. - v8-v15 : bottom 64-bits preserved across C calls (d8-d15 are preserved). - - v16-v31: Used as codegen temp/scratch. - v8-v15 : Can be used for promotion. - - Must maintain 16-byte stack alignment. - -Mterp notes: - -The following registers have fixed assignments: - - reg nick purpose - x20 xPC interpreted program counter, used for fetching instructions - x21 xFP interpreted frame pointer, used for accessing locals and args - x22 xSELF self (Thread) pointer - x23 xINST first 16-bit code unit of current instruction - x24 xIBASE interpreted instruction base pointer, used for computed goto - x25 xREFS base of object references in shadow frame (ideally, we'll get rid of this later). - x26 wPROFILE jit profile hotness countdown - x16 ip scratch reg - x17 ip2 scratch reg (used by macros) - -Macros are provided for common operations. They MUST NOT alter unspecified registers or condition -codes. -*/ - -/* - * This is a #include, not a %include, because we want the C pre-processor - * to expand the macros into assembler assignment statements. - */ -#include "asm_support.h" -#include "interpreter/cfi_asm_support.h" - -#define MTERP_PROFILE_BRANCHES 1 -#define MTERP_LOGGING 0 - -/* During bringup, we'll use the shadow frame model instead of xFP */ -/* single-purpose registers, given names for clarity */ -#define xPC x20 -#define CFI_DEX 20 // DWARF register number of the register holding dex-pc (xPC). -#define CFI_TMP 0 // DWARF register number of the first argument register (r0). -#define xFP x21 -#define xSELF x22 -#define xINST x23 -#define wINST w23 -#define xIBASE x24 -#define xREFS x25 -#define wPROFILE w26 -#define xPROFILE x26 -#define ip x16 -#define ip2 x17 - -/* - * Instead of holding a pointer to the shadow frame, we keep xFP at the base of the vregs. So, - * to access other shadow frame fields, we need to use a backwards offset. Define those here. - */ -#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) -#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) -#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) -#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) -#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) -#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) -#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) -#define OFF_FP_DEX_INSTRUCTIONS OFF_FP(SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET) -#define OFF_FP_SHADOWFRAME OFF_FP(0) - -/* - * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must - * be done *before* something throws. - * - * It's okay to do this more than once. - * - * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped - * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction - * offset into the code_items_[] array. For effiency, we will "export" the - * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC - * to convert to a dex pc when needed. - */ -.macro EXPORT_PC - str xPC, [xFP, #OFF_FP_DEX_PC_PTR] -.endm - -/* - * Fetch the next instruction from xPC into wINST. Does not advance xPC. - */ -.macro FETCH_INST - ldrh wINST, [xPC] -.endm - -/* - * Fetch the next instruction from the specified offset. Advances xPC - * to point to the next instruction. "_count" is in 16-bit code units. - * - * Because of the limited size of immediate constants on ARM, this is only - * suitable for small forward movements (i.e. don't try to implement "goto" - * with this). - * - * This must come AFTER anything that can throw an exception, or the - * exception catch may miss. (This also implies that it must come after - * EXPORT_PC.) - */ -.macro FETCH_ADVANCE_INST count - ldrh wINST, [xPC, #((\count)*2)]! -.endm - -/* - * The operation performed here is similar to FETCH_ADVANCE_INST, except the - * src and dest registers are parameterized (not hard-wired to xPC and xINST). - */ -.macro PREFETCH_ADVANCE_INST dreg, sreg, count - ldrh \dreg, [\sreg, #((\count)*2)]! -.endm - -/* - * Similar to FETCH_ADVANCE_INST, but does not update xPC. Used to load - * xINST ahead of possible exception point. Be sure to manually advance xPC - * later. - */ -.macro PREFETCH_INST count - ldrh wINST, [xPC, #((\count)*2)] -.endm - -/* Advance xPC by some number of code units. */ -.macro ADVANCE count - add xPC, xPC, #((\count)*2) -.endm - -/* - * Fetch the next instruction from an offset specified by _reg and advance xPC. - * xPC to point to the next instruction. "_reg" must specify the distance - * in bytes, *not* 16-bit code units, and may be a signed value. Must not set flags. - * - */ -.macro FETCH_ADVANCE_INST_RB reg - add xPC, xPC, \reg, sxtw - ldrh wINST, [xPC] -.endm - -/* - * Fetch a half-word code unit from an offset past the current PC. The - * "_count" value is in 16-bit code units. Does not advance xPC. - * - * The "_S" variant works the same but treats the value as signed. - */ -.macro FETCH reg, count - ldrh \reg, [xPC, #((\count)*2)] -.endm - -.macro FETCH_S reg, count - ldrsh \reg, [xPC, #((\count)*2)] -.endm - -/* - * Fetch one byte from an offset past the current PC. Pass in the same - * "_count" as you would for FETCH, and an additional 0/1 indicating which - * byte of the halfword you want (lo/hi). - */ -.macro FETCH_B reg, count, byte - ldrb \reg, [xPC, #((\count)*2+(\byte))] -.endm - -/* - * Put the instruction's opcode field into the specified register. - */ -.macro GET_INST_OPCODE reg - and \reg, xINST, #255 -.endm - -/* - * Put the prefetched instruction's opcode field into the specified register. - */ -.macro GET_PREFETCHED_OPCODE oreg, ireg - and \oreg, \ireg, #255 -.endm - -/* - * Begin executing the opcode in _reg. Clobbers reg - */ - -.macro GOTO_OPCODE reg - add \reg, xIBASE, \reg, lsl #${handler_size_bits} - br \reg -.endm -.macro GOTO_OPCODE_BASE base,reg - add \reg, \base, \reg, lsl #${handler_size_bits} - br \reg -.endm - -/* - * Get/set the 32-bit value from a Dalvik register. - */ -.macro GET_VREG reg, vreg - ldr \reg, [xFP, \vreg, uxtw #2] -.endm -.macro SET_VREG reg, vreg - str \reg, [xFP, \vreg, uxtw #2] - str wzr, [xREFS, \vreg, uxtw #2] -.endm -.macro SET_VREG_OBJECT reg, vreg, tmpreg - str \reg, [xFP, \vreg, uxtw #2] - str \reg, [xREFS, \vreg, uxtw #2] -.endm - -/* - * Get/set the 64-bit value from a Dalvik register. - * TUNING: can we do better here? - */ -.macro GET_VREG_WIDE reg, vreg - add ip2, xFP, \vreg, lsl #2 - ldr \reg, [ip2] -.endm -.macro SET_VREG_WIDE reg, vreg - add ip2, xFP, \vreg, lsl #2 - str \reg, [ip2] - add ip2, xREFS, \vreg, lsl #2 - str xzr, [ip2] -.endm - -/* - * Get the 32-bit value from a Dalvik register and sign-extend to 64-bit. - * Used to avoid an extra instruction in int-to-long. - */ -.macro GET_VREG_S reg, vreg - ldrsw \reg, [xFP, \vreg, uxtw #2] -.endm - -/* - * Convert a virtual register index into an address. - */ -.macro VREG_INDEX_TO_ADDR reg, vreg - add \reg, xFP, \vreg, lsl #2 /* WARNING: handle shadow frame vreg zero if store */ -.endm - -/* - * Refresh handler table. - */ -.macro REFRESH_IBASE - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] -.endm - -/* - * Save two registers to the stack. - */ -.macro SAVE_TWO_REGS reg1, reg2, offset - stp \reg1, \reg2, [sp, #(\offset)] - .cfi_rel_offset \reg1, (\offset) - .cfi_rel_offset \reg2, (\offset) + 8 -.endm - -/* - * Restore two registers from the stack. - */ -.macro RESTORE_TWO_REGS reg1, reg2, offset - ldp \reg1, \reg2, [sp, #(\offset)] - .cfi_restore \reg1 - .cfi_restore \reg2 -.endm - -/* - * Increase frame size and save two registers to the bottom of the stack. - */ -.macro SAVE_TWO_REGS_INCREASE_FRAME reg1, reg2, frame_adjustment - stp \reg1, \reg2, [sp, #-(\frame_adjustment)]! - .cfi_adjust_cfa_offset (\frame_adjustment) - .cfi_rel_offset \reg1, 0 - .cfi_rel_offset \reg2, 8 -.endm - -/* - * Restore two registers from the bottom of the stack and decrease frame size. - */ -.macro RESTORE_TWO_REGS_DECREASE_FRAME reg1, reg2, frame_adjustment - ldp \reg1, \reg2, [sp], #(\frame_adjustment) - .cfi_restore \reg1 - .cfi_restore \reg2 - .cfi_adjust_cfa_offset -(\frame_adjustment) -.endm - -/* - * cfi support macros. - */ -.macro ENTRY name - .type \name, #function - .hidden \name // Hide this as a global symbol, so we do not incur plt calls. - .global \name - /* Cache alignment for function entry */ - .balign 16 -\name: - .cfi_startproc -.endm - -.macro END name - .cfi_endproc - .size \name, .-\name -.endm diff --git a/runtime/interpreter/mterp/arm64/instruction_end.S b/runtime/interpreter/mterp/arm64/instruction_end.S deleted file mode 100644 index f90ebd0221f7ff35964753368888c2576917d112..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/instruction_end.S +++ /dev/null @@ -1,5 +0,0 @@ - - .type artMterpAsmInstructionEnd, #object - .hidden artMterpAsmInstructionEnd - .global artMterpAsmInstructionEnd -artMterpAsmInstructionEnd: diff --git a/runtime/interpreter/mterp/arm64/instruction_end_alt.S b/runtime/interpreter/mterp/arm64/instruction_end_alt.S deleted file mode 100644 index 0b66dbb9479dd5600b5b69aeeb3ed91bcaa09e1f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/instruction_end_alt.S +++ /dev/null @@ -1,5 +0,0 @@ - - .type artMterpAsmAltInstructionEnd, #object - .hidden artMterpAsmAltInstructionEnd - .global artMterpAsmAltInstructionEnd -artMterpAsmAltInstructionEnd: diff --git a/runtime/interpreter/mterp/arm64/instruction_end_sister.S b/runtime/interpreter/mterp/arm64/instruction_end_sister.S deleted file mode 100644 index 71c0300f6d5a139f623fd1397be73b7a6cc01c34..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/instruction_end_sister.S +++ /dev/null @@ -1,5 +0,0 @@ - - .type artMterpAsmSisterEnd, #object - .hidden artMterpAsmSisterEnd - .global artMterpAsmSisterEnd -artMterpAsmSisterEnd: diff --git a/runtime/interpreter/mterp/arm64/instruction_start.S b/runtime/interpreter/mterp/arm64/instruction_start.S deleted file mode 100644 index b7e9cf51e4ff0498942076b0a4de9d13c228a933..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/instruction_start.S +++ /dev/null @@ -1,6 +0,0 @@ - - .type artMterpAsmInstructionStart, #object - .hidden artMterpAsmInstructionStart - .global artMterpAsmInstructionStart -artMterpAsmInstructionStart = .L_op_nop - .text diff --git a/runtime/interpreter/mterp/arm64/instruction_start_alt.S b/runtime/interpreter/mterp/arm64/instruction_start_alt.S deleted file mode 100644 index 7a67ba064c3171e55aad5cabf1458c58c184c5ff..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/instruction_start_alt.S +++ /dev/null @@ -1,6 +0,0 @@ - - .type artMterpAsmAltInstructionStart, #object - .hidden artMterpAsmAltInstructionStart - .global artMterpAsmAltInstructionStart -artMterpAsmAltInstructionStart = .L_ALT_op_nop - .text diff --git a/runtime/interpreter/mterp/arm64/instruction_start_sister.S b/runtime/interpreter/mterp/arm64/instruction_start_sister.S deleted file mode 100644 index 00360616053f769913e829e97a698931958f6b9a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/instruction_start_sister.S +++ /dev/null @@ -1,7 +0,0 @@ - - .type artMterpAsmSisterStart, #object - .hidden artMterpAsmSisterStart - .global artMterpAsmSisterStart - .text - .balign 4 -artMterpAsmSisterStart: diff --git a/runtime/interpreter/mterp/arm64/invoke.S b/runtime/interpreter/mterp/arm64/invoke.S index 7a32df7bcafe44ceb70e2d48e1accad45efd6143..03ac316392ea553d437e5a56c10906eb7c7ee4e9 100644 --- a/runtime/interpreter/mterp/arm64/invoke.S +++ b/runtime/interpreter/mterp/arm64/invoke.S @@ -1,4 +1,4 @@ -%default { "helper":"UndefinedInvokeHandler" } +%def invoke(helper="UndefinedInvokeHandler"): /* * Generic invoke handler wrapper. */ @@ -18,3 +18,93 @@ GET_INST_OPCODE ip GOTO_OPCODE ip + +%def invoke_polymorphic(helper="UndefinedInvokeHandler"): + /* + * invoke-polymorphic handler wrapper. + */ + /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ + /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ + .extern $helper + EXPORT_PC + mov x0, xSELF + add x1, xFP, #OFF_FP_SHADOWFRAME + mov x2, xPC + mov x3, xINST + bl $helper + cbz w0, MterpException + FETCH_ADVANCE_INST 4 + bl MterpShouldSwitchInterpreters + cbnz w0, MterpFallback + GET_INST_OPCODE ip + GOTO_OPCODE ip + +%def op_invoke_custom(): +% invoke(helper="MterpInvokeCustom") + +%def op_invoke_custom_range(): +% invoke(helper="MterpInvokeCustomRange") + +%def op_invoke_direct(): +% invoke(helper="MterpInvokeDirect") + +%def op_invoke_direct_range(): +% invoke(helper="MterpInvokeDirectRange") + +%def op_invoke_interface(): +% invoke(helper="MterpInvokeInterface") + /* + * Handle an interface method call. + * + * for: invoke-interface, invoke-interface/range + */ + /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ + /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ + +%def op_invoke_interface_range(): +% invoke(helper="MterpInvokeInterfaceRange") + +%def op_invoke_polymorphic(): +% invoke_polymorphic(helper="MterpInvokePolymorphic") + +%def op_invoke_polymorphic_range(): +% invoke_polymorphic(helper="MterpInvokePolymorphicRange") + +%def op_invoke_static(): +% invoke(helper="MterpInvokeStatic") + + +%def op_invoke_static_range(): +% invoke(helper="MterpInvokeStaticRange") + +%def op_invoke_super(): +% invoke(helper="MterpInvokeSuper") + /* + * Handle a "super" method call. + * + * for: invoke-super, invoke-super/range + */ + /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ + /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ + +%def op_invoke_super_range(): +% invoke(helper="MterpInvokeSuperRange") + +%def op_invoke_virtual(): +% invoke(helper="MterpInvokeVirtual") + /* + * Handle a virtual method call. + * + * for: invoke-virtual, invoke-virtual/range + */ + /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ + /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ + +%def op_invoke_virtual_quick(): +% invoke(helper="MterpInvokeVirtualQuick") + +%def op_invoke_virtual_range(): +% invoke(helper="MterpInvokeVirtualRange") + +%def op_invoke_virtual_range_quick(): +% invoke(helper="MterpInvokeVirtualQuickRange") diff --git a/runtime/interpreter/mterp/arm64/invoke_polymorphic.S b/runtime/interpreter/mterp/arm64/invoke_polymorphic.S deleted file mode 100644 index 7906f0ada047ace8a0627b44dca534fe4652b2c5..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/invoke_polymorphic.S +++ /dev/null @@ -1,19 +0,0 @@ -%default { "helper":"UndefinedInvokeHandler" } - /* - * invoke-polymorphic handler wrapper. - */ - /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ - .extern $helper - EXPORT_PC - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - mov x3, xINST - bl $helper - cbz w0, MterpException - FETCH_ADVANCE_INST 4 - bl MterpShouldSwitchInterpreters - cbnz w0, MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip diff --git a/runtime/interpreter/mterp/arm64/main.S b/runtime/interpreter/mterp/arm64/main.S new file mode 100644 index 0000000000000000000000000000000000000000..963e724563d82a08f72d325cc0c9836a17317df0 --- /dev/null +++ b/runtime/interpreter/mterp/arm64/main.S @@ -0,0 +1,783 @@ +%def header(): +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + Art assembly interpreter notes: + + First validate assembly code by implementing ExecuteXXXImpl() style body (doesn't + handle invoke, allows higher-level code to create frame & shadow frame. + + Once that's working, support direct entry code & eliminate shadow frame (and + excess locals allocation. + + Some (hopefully) temporary ugliness. We'll treat xFP as pointing to the + base of the vreg array within the shadow frame. Access the other fields, + dex_pc_, method_ and number_of_vregs_ via negative offsets. For now, we'll continue + the shadow frame mechanism of double-storing object references - via xFP & + number_of_vregs_. + + */ + +/* +ARM64 Runtime register usage conventions. + + r0 : w0 is 32-bit return register and x0 is 64-bit. + r0-r7 : Argument registers. + r8-r15 : Caller save registers (used as temporary registers). + r16-r17: Also known as ip0-ip1, respectively. Used as scratch registers by + the linker, by the trampolines and other stubs (the backend uses + these as temporary registers). + r18 : Caller save register (used as temporary register). + r19 : Pointer to thread-local storage. + r20-r29: Callee save registers. + r30 : (lr) is reserved (the link register). + rsp : (sp) is reserved (the stack pointer). + rzr : (zr) is reserved (the zero register). + + Floating-point registers + v0-v31 + + v0 : s0 is return register for singles (32-bit) and d0 for doubles (64-bit). + This is analogous to the C/C++ (hard-float) calling convention. + v0-v7 : Floating-point argument registers in both Dalvik and C/C++ conventions. + Also used as temporary and codegen scratch registers. + + v0-v7 and v16-v31 : trashed across C calls. + v8-v15 : bottom 64-bits preserved across C calls (d8-d15 are preserved). + + v16-v31: Used as codegen temp/scratch. + v8-v15 : Can be used for promotion. + + Must maintain 16-byte stack alignment. + +Mterp notes: + +The following registers have fixed assignments: + + reg nick purpose + x20 xPC interpreted program counter, used for fetching instructions + x21 xFP interpreted frame pointer, used for accessing locals and args + x22 xSELF self (Thread) pointer + x23 xINST first 16-bit code unit of current instruction + x24 xIBASE interpreted instruction base pointer, used for computed goto + x25 xREFS base of object references in shadow frame (ideally, we'll get rid of this later). + x26 wPROFILE jit profile hotness countdown + x16 ip scratch reg + x17 ip2 scratch reg (used by macros) + +Macros are provided for common operations. They MUST NOT alter unspecified registers or condition +codes. +*/ + +/* + * This is a #include, not a %include, because we want the C pre-processor + * to expand the macros into assembler assignment statements. + */ +#include "asm_support.h" +#include "interpreter/cfi_asm_support.h" + +#define MTERP_PROFILE_BRANCHES 1 +#define MTERP_LOGGING 0 + +/* During bringup, we'll use the shadow frame model instead of xFP */ +/* single-purpose registers, given names for clarity */ +#define xPC x20 +#define CFI_DEX 20 // DWARF register number of the register holding dex-pc (xPC). +#define CFI_TMP 0 // DWARF register number of the first argument register (r0). +#define xFP x21 +#define xSELF x22 +#define xINST x23 +#define wINST w23 +#define xIBASE x24 +#define xREFS x25 +#define wPROFILE w26 +#define xPROFILE x26 +#define ip x16 +#define ip2 x17 + +/* + * Instead of holding a pointer to the shadow frame, we keep xFP at the base of the vregs. So, + * to access other shadow frame fields, we need to use a backwards offset. Define those here. + */ +#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) +#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) +#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) +#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) +#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) +#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) +#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) +#define OFF_FP_DEX_INSTRUCTIONS OFF_FP(SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET) +#define OFF_FP_SHADOWFRAME OFF_FP(0) + +/* + * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must + * be done *before* something throws. + * + * It's okay to do this more than once. + * + * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped + * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction + * offset into the code_items_[] array. For effiency, we will "export" the + * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC + * to convert to a dex pc when needed. + */ +.macro EXPORT_PC + str xPC, [xFP, #OFF_FP_DEX_PC_PTR] +.endm + +/* + * Fetch the next instruction from xPC into wINST. Does not advance xPC. + */ +.macro FETCH_INST + ldrh wINST, [xPC] +.endm + +/* + * Fetch the next instruction from the specified offset. Advances xPC + * to point to the next instruction. "_count" is in 16-bit code units. + * + * Because of the limited size of immediate constants on ARM, this is only + * suitable for small forward movements (i.e. don't try to implement "goto" + * with this). + * + * This must come AFTER anything that can throw an exception, or the + * exception catch may miss. (This also implies that it must come after + * EXPORT_PC.) + */ +.macro FETCH_ADVANCE_INST count + ldrh wINST, [xPC, #((\count)*2)]! +.endm + +/* + * The operation performed here is similar to FETCH_ADVANCE_INST, except the + * src and dest registers are parameterized (not hard-wired to xPC and xINST). + */ +.macro PREFETCH_ADVANCE_INST dreg, sreg, count + ldrh \dreg, [\sreg, #((\count)*2)]! +.endm + +/* + * Similar to FETCH_ADVANCE_INST, but does not update xPC. Used to load + * xINST ahead of possible exception point. Be sure to manually advance xPC + * later. + */ +.macro PREFETCH_INST count + ldrh wINST, [xPC, #((\count)*2)] +.endm + +/* Advance xPC by some number of code units. */ +.macro ADVANCE count + add xPC, xPC, #((\count)*2) +.endm + +/* + * Fetch the next instruction from an offset specified by _reg and advance xPC. + * xPC to point to the next instruction. "_reg" must specify the distance + * in bytes, *not* 16-bit code units, and may be a signed value. Must not set flags. + * + */ +.macro FETCH_ADVANCE_INST_RB reg + add xPC, xPC, \reg, sxtw + ldrh wINST, [xPC] +.endm + +/* + * Fetch a half-word code unit from an offset past the current PC. The + * "_count" value is in 16-bit code units. Does not advance xPC. + * + * The "_S" variant works the same but treats the value as signed. + */ +.macro FETCH reg, count + ldrh \reg, [xPC, #((\count)*2)] +.endm + +.macro FETCH_S reg, count + ldrsh \reg, [xPC, #((\count)*2)] +.endm + +/* + * Fetch one byte from an offset past the current PC. Pass in the same + * "_count" as you would for FETCH, and an additional 0/1 indicating which + * byte of the halfword you want (lo/hi). + */ +.macro FETCH_B reg, count, byte + ldrb \reg, [xPC, #((\count)*2+(\byte))] +.endm + +/* + * Put the instruction's opcode field into the specified register. + */ +.macro GET_INST_OPCODE reg + and \reg, xINST, #255 +.endm + +/* + * Put the prefetched instruction's opcode field into the specified register. + */ +.macro GET_PREFETCHED_OPCODE oreg, ireg + and \oreg, \ireg, #255 +.endm + +/* + * Begin executing the opcode in _reg. Clobbers reg + */ + +.macro GOTO_OPCODE reg + add \reg, xIBASE, \reg, lsl #${handler_size_bits} + br \reg +.endm +.macro GOTO_OPCODE_BASE base,reg + add \reg, \base, \reg, lsl #${handler_size_bits} + br \reg +.endm + +/* + * Get/set the 32-bit value from a Dalvik register. + */ +.macro GET_VREG reg, vreg + ldr \reg, [xFP, \vreg, uxtw #2] +.endm +.macro SET_VREG reg, vreg + str \reg, [xFP, \vreg, uxtw #2] + str wzr, [xREFS, \vreg, uxtw #2] +.endm +.macro SET_VREG_OBJECT reg, vreg, tmpreg + str \reg, [xFP, \vreg, uxtw #2] + str \reg, [xREFS, \vreg, uxtw #2] +.endm + +/* + * Get/set the 64-bit value from a Dalvik register. + * TUNING: can we do better here? + */ +.macro GET_VREG_WIDE reg, vreg + add ip2, xFP, \vreg, lsl #2 + ldr \reg, [ip2] +.endm +.macro SET_VREG_WIDE reg, vreg + add ip2, xFP, \vreg, lsl #2 + str \reg, [ip2] + add ip2, xREFS, \vreg, lsl #2 + str xzr, [ip2] +.endm + +/* + * Get the 32-bit value from a Dalvik register and sign-extend to 64-bit. + * Used to avoid an extra instruction in int-to-long. + */ +.macro GET_VREG_S reg, vreg + ldrsw \reg, [xFP, \vreg, uxtw #2] +.endm + +/* + * Convert a virtual register index into an address. + */ +.macro VREG_INDEX_TO_ADDR reg, vreg + add \reg, xFP, \vreg, lsl #2 /* WARNING: handle shadow frame vreg zero if store */ +.endm + +/* + * Refresh handler table. + */ +.macro REFRESH_IBASE + ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] +.endm + +/* + * Save two registers to the stack. + */ +.macro SAVE_TWO_REGS reg1, reg2, offset + stp \reg1, \reg2, [sp, #(\offset)] + .cfi_rel_offset \reg1, (\offset) + .cfi_rel_offset \reg2, (\offset) + 8 +.endm + +/* + * Restore two registers from the stack. + */ +.macro RESTORE_TWO_REGS reg1, reg2, offset + ldp \reg1, \reg2, [sp, #(\offset)] + .cfi_restore \reg1 + .cfi_restore \reg2 +.endm + +/* + * Increase frame size and save two registers to the bottom of the stack. + */ +.macro SAVE_TWO_REGS_INCREASE_FRAME reg1, reg2, frame_adjustment + stp \reg1, \reg2, [sp, #-(\frame_adjustment)]! + .cfi_adjust_cfa_offset (\frame_adjustment) + .cfi_rel_offset \reg1, 0 + .cfi_rel_offset \reg2, 8 +.endm + +/* + * Restore two registers from the bottom of the stack and decrease frame size. + */ +.macro RESTORE_TWO_REGS_DECREASE_FRAME reg1, reg2, frame_adjustment + ldp \reg1, \reg2, [sp], #(\frame_adjustment) + .cfi_restore \reg1 + .cfi_restore \reg2 + .cfi_adjust_cfa_offset -(\frame_adjustment) +.endm + +/* + * cfi support macros. + */ +.macro ENTRY name + .type \name, #function + .hidden \name // Hide this as a global symbol, so we do not incur plt calls. + .global \name + /* Cache alignment for function entry */ + .balign 16 +\name: + .cfi_startproc +.endm + +.macro END name + .cfi_endproc + .size \name, .-\name +.endm + +%def entry(): +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + .text + +/* + * Interpreter entry point. + * On entry: + * x0 Thread* self/ + * x1 insns_ + * x2 ShadowFrame + * x3 JValue* result_register + * + */ +ENTRY ExecuteMterpImpl + SAVE_TWO_REGS_INCREASE_FRAME xPROFILE, x27, 80 + SAVE_TWO_REGS xIBASE, xREFS, 16 + SAVE_TWO_REGS xSELF, xINST, 32 + SAVE_TWO_REGS xPC, xFP, 48 + SAVE_TWO_REGS fp, lr, 64 + add fp, sp, #64 + + /* Remember the return register */ + str x3, [x2, #SHADOWFRAME_RESULT_REGISTER_OFFSET] + + /* Remember the dex instruction pointer */ + str x1, [x2, #SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET] + + /* set up "named" registers */ + mov xSELF, x0 + ldr w0, [x2, #SHADOWFRAME_NUMBER_OF_VREGS_OFFSET] + add xFP, x2, #SHADOWFRAME_VREGS_OFFSET // point to vregs. + add xREFS, xFP, w0, lsl #2 // point to reference array in shadow frame + ldr w0, [x2, #SHADOWFRAME_DEX_PC_OFFSET] // Get starting dex_pc. + add xPC, x1, w0, lsl #1 // Create direct pointer to 1st dex opcode + CFI_DEFINE_DEX_PC_WITH_OFFSET(CFI_TMP, CFI_DEX, 0) + EXPORT_PC + + /* Starting ibase */ + ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] + + /* Set up for backwards branches & osr profiling */ + ldr x0, [xFP, #OFF_FP_METHOD] + add x1, xFP, #OFF_FP_SHADOWFRAME + mov x2, xSELF + bl MterpSetUpHotnessCountdown + mov wPROFILE, w0 // Starting hotness countdown to xPROFILE + + /* start executing the instruction at rPC */ + FETCH_INST // load wINST from rPC + GET_INST_OPCODE ip // extract opcode from wINST + GOTO_OPCODE ip // jump to next instruction + /* NOTE: no fallthrough */ + +%def alt_stub(): +/* + * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle + * any interesting requests and then jump to the real instruction + * handler. Note that the call to MterpCheckBefore is done as a tail call. + */ + .extern MterpCheckBefore + ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. + adr lr, artMterpAsmInstructionStart + (${opnum} * 128) // Addr of primary handler. + mov x0, xSELF + add x1, xFP, #OFF_FP_SHADOWFRAME + mov x2, xPC + b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. + +%def footer(): +// Close out the cfi info. We're treating mterp as a single function. + +END ExecuteMterpImpl + + +%def fallback(): +/* Transfer stub to alternate interpreter */ + b MterpFallback + + +%def helpers(): +/* + * =========================================================================== + * Common subroutines and data + * =========================================================================== + */ + +/* + * We've detected a condition that will result in an exception, but the exception + * has not yet been thrown. Just bail out to the reference interpreter to deal with it. + * TUNING: for consistency, we may want to just go ahead and handle these here. + */ +common_errDivideByZero: + EXPORT_PC +#if MTERP_LOGGING + mov x0, xSELF + add x1, xFP, #OFF_FP_SHADOWFRAME + bl MterpLogDivideByZeroException +#endif + b MterpCommonFallback + +common_errArrayIndex: + EXPORT_PC +#if MTERP_LOGGING + mov x0, xSELF + add x1, xFP, #OFF_FP_SHADOWFRAME + bl MterpLogArrayIndexException +#endif + b MterpCommonFallback + +common_errNegativeArraySize: + EXPORT_PC +#if MTERP_LOGGING + mov x0, xSELF + add x1, xFP, #OFF_FP_SHADOWFRAME + bl MterpLogNegativeArraySizeException +#endif + b MterpCommonFallback + +common_errNoSuchMethod: + EXPORT_PC +#if MTERP_LOGGING + mov x0, xSELF + add x1, xFP, #OFF_FP_SHADOWFRAME + bl MterpLogNoSuchMethodException +#endif + b MterpCommonFallback + +common_errNullObject: + EXPORT_PC +#if MTERP_LOGGING + mov x0, xSELF + add x1, xFP, #OFF_FP_SHADOWFRAME + bl MterpLogNullObjectException +#endif + b MterpCommonFallback + +common_exceptionThrown: + EXPORT_PC +#if MTERP_LOGGING + mov x0, xSELF + add x1, xFP, #OFF_FP_SHADOWFRAME + bl MterpLogExceptionThrownException +#endif + b MterpCommonFallback + +MterpSuspendFallback: + EXPORT_PC +#if MTERP_LOGGING + mov x0, xSELF + add x1, xFP, #OFF_FP_SHADOWFRAME + ldr x2, [xSELF, #THREAD_FLAGS_OFFSET] + bl MterpLogSuspendFallback +#endif + b MterpCommonFallback + +/* + * If we're here, something is out of the ordinary. If there is a pending + * exception, handle it. Otherwise, roll back and retry with the reference + * interpreter. + */ +MterpPossibleException: + ldr x0, [xSELF, #THREAD_EXCEPTION_OFFSET] + cbz x0, MterpFallback // If not, fall back to reference interpreter. + /* intentional fallthrough - handle pending exception. */ +/* + * On return from a runtime helper routine, we've found a pending exception. + * Can we handle it here - or need to bail out to caller? + * + */ +MterpException: + mov x0, xSELF + add x1, xFP, #OFF_FP_SHADOWFRAME + bl MterpHandleException // (self, shadow_frame) + cbz w0, MterpExceptionReturn // no local catch, back to caller. + ldr x0, [xFP, #OFF_FP_DEX_INSTRUCTIONS] + ldr w1, [xFP, #OFF_FP_DEX_PC] + ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] + add xPC, x0, x1, lsl #1 // generate new dex_pc_ptr + /* Do we need to switch interpreters? */ + bl MterpShouldSwitchInterpreters + cbnz w0, MterpFallback + /* resume execution at catch block */ + EXPORT_PC + FETCH_INST + GET_INST_OPCODE ip + GOTO_OPCODE ip + /* NOTE: no fallthrough */ +/* + * Common handling for branches with support for Jit profiling. + * On entry: + * wINST <= signed offset + * wPROFILE <= signed hotness countdown (expanded to 32 bits) + * condition bits <= set to establish sign of offset (use "NoFlags" entry if not) + * + * We have quite a few different cases for branch profiling, OSR detection and + * suspend check support here. + * + * Taken backward branches: + * If profiling active, do hotness countdown and report if we hit zero. + * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. + * Is there a pending suspend request? If so, suspend. + * + * Taken forward branches and not-taken backward branches: + * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. + * + * Our most common case is expected to be a taken backward branch with active jit profiling, + * but no full OSR check and no pending suspend request. + * Next most common case is not-taken branch with no full OSR check. + * + */ +MterpCommonTakenBranchNoFlags: + cmp wINST, #0 + b.gt .L_forward_branch // don't add forward branches to hotness + tbnz wPROFILE, #31, .L_no_count_backwards // go if negative + subs wPROFILE, wPROFILE, #1 // countdown + b.eq .L_add_batch // counted down to zero - report +.L_resume_backward_branch: + ldr lr, [xSELF, #THREAD_FLAGS_OFFSET] + add w2, wINST, wINST // w2<- byte offset + FETCH_ADVANCE_INST_RB w2 // update rPC, load wINST + REFRESH_IBASE + ands lr, lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST + b.ne .L_suspend_request_pending + GET_INST_OPCODE ip // extract opcode from wINST + GOTO_OPCODE ip // jump to next instruction + +.L_suspend_request_pending: + EXPORT_PC + mov x0, xSELF + bl MterpSuspendCheck // (self) + cbnz x0, MterpFallback + REFRESH_IBASE // might have changed during suspend + GET_INST_OPCODE ip // extract opcode from wINST + GOTO_OPCODE ip // jump to next instruction + +.L_no_count_backwards: + cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? + b.ne .L_resume_backward_branch + mov x0, xSELF + add x1, xFP, #OFF_FP_SHADOWFRAME + mov x2, xINST + EXPORT_PC + bl MterpMaybeDoOnStackReplacement // (self, shadow_frame, offset) + cbnz x0, MterpOnStackReplacement + b .L_resume_backward_branch + +.L_forward_branch: + cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? + b.eq .L_check_osr_forward +.L_resume_forward_branch: + add w2, wINST, wINST // w2<- byte offset + FETCH_ADVANCE_INST_RB w2 // update rPC, load wINST + GET_INST_OPCODE ip // extract opcode from wINST + GOTO_OPCODE ip // jump to next instruction + +.L_check_osr_forward: + mov x0, xSELF + add x1, xFP, #OFF_FP_SHADOWFRAME + mov x2, xINST + EXPORT_PC + bl MterpMaybeDoOnStackReplacement // (self, shadow_frame, offset) + cbnz x0, MterpOnStackReplacement + b .L_resume_forward_branch + +.L_add_batch: + add x1, xFP, #OFF_FP_SHADOWFRAME + strh wPROFILE, [x1, #SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET] + ldr x0, [xFP, #OFF_FP_METHOD] + mov x2, xSELF + bl MterpAddHotnessBatch // (method, shadow_frame, self) + mov wPROFILE, w0 // restore new hotness countdown to wPROFILE + b .L_no_count_backwards + +/* + * Entered from the conditional branch handlers when OSR check request active on + * not-taken path. All Dalvik not-taken conditional branch offsets are 2. + */ +.L_check_not_taken_osr: + mov x0, xSELF + add x1, xFP, #OFF_FP_SHADOWFRAME + mov x2, #2 + EXPORT_PC + bl MterpMaybeDoOnStackReplacement // (self, shadow_frame, offset) + cbnz x0, MterpOnStackReplacement + FETCH_ADVANCE_INST 2 + GET_INST_OPCODE ip // extract opcode from wINST + GOTO_OPCODE ip // jump to next instruction + +/* + * Check for suspend check request. Assumes wINST already loaded, xPC advanced and + * still needs to get the opcode and branch to it, and flags are in lr. + */ +MterpCheckSuspendAndContinue: + ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh xIBASE + ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST + b.ne check1 + GET_INST_OPCODE ip // extract opcode from wINST + GOTO_OPCODE ip // jump to next instruction +check1: + EXPORT_PC + mov x0, xSELF + bl MterpSuspendCheck // (self) + cbnz x0, MterpFallback // Something in the environment changed, switch interpreters + GET_INST_OPCODE ip // extract opcode from wINST + GOTO_OPCODE ip // jump to next instruction + +/* + * On-stack replacement has happened, and now we've returned from the compiled method. + */ +MterpOnStackReplacement: +#if MTERP_LOGGING + mov x0, xSELF + add x1, xFP, #OFF_FP_SHADOWFRAME + sxtw x2, wINST + bl MterpLogOSR +#endif + mov x0, #1 // Signal normal return + b MterpDone + +/* + * Bail out to reference interpreter. + */ +MterpFallback: + EXPORT_PC +#if MTERP_LOGGING + mov x0, xSELF + add x1, xFP, #OFF_FP_SHADOWFRAME + bl MterpLogFallback +#endif +MterpCommonFallback: + mov x0, #0 // signal retry with reference interpreter. + b MterpDone + +/* + * We pushed some registers on the stack in ExecuteMterpImpl, then saved + * SP and LR. Here we restore SP, restore the registers, and then restore + * LR to PC. + * + * On entry: + * uint32_t* xFP (should still be live, pointer to base of vregs) + */ +MterpExceptionReturn: + mov x0, #1 // signal return to caller. + b MterpDone +MterpReturn: + ldr x2, [xFP, #OFF_FP_RESULT_REGISTER] + str x0, [x2] + mov x0, #1 // signal return to caller. +MterpDone: +/* + * At this point, we expect wPROFILE to be non-zero. If negative, hotness is disabled or we're + * checking for OSR. If greater than zero, we might have unreported hotness to register + * (the difference between the ending wPROFILE and the cached hotness counter). wPROFILE + * should only reach zero immediately after a hotness decrement, and is then reset to either + * a negative special state or the new non-zero countdown value. + */ + cmp wPROFILE, #0 + bgt MterpProfileActive // if > 0, we may have some counts to report. + .cfi_remember_state + RESTORE_TWO_REGS fp, lr, 64 + RESTORE_TWO_REGS xPC, xFP, 48 + RESTORE_TWO_REGS xSELF, xINST, 32 + RESTORE_TWO_REGS xIBASE, xREFS, 16 + RESTORE_TWO_REGS_DECREASE_FRAME xPROFILE, x27, 80 + ret + .cfi_restore_state // Reset unwind info so following code unwinds. + .cfi_def_cfa_offset 80 // workaround for clang bug: 31975598 + +MterpProfileActive: + mov xINST, x0 // stash return value + /* Report cached hotness counts */ + ldr x0, [xFP, #OFF_FP_METHOD] + add x1, xFP, #OFF_FP_SHADOWFRAME + mov x2, xSELF + strh wPROFILE, [x1, #SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET] + bl MterpAddHotnessBatch // (method, shadow_frame, self) + mov x0, xINST // restore return value + RESTORE_TWO_REGS fp, lr, 64 + RESTORE_TWO_REGS xPC, xFP, 48 + RESTORE_TWO_REGS xSELF, xINST, 32 + RESTORE_TWO_REGS xIBASE, xREFS, 16 + RESTORE_TWO_REGS_DECREASE_FRAME xPROFILE, x27, 80 + ret + + +%def instruction_end(): + + .type artMterpAsmInstructionEnd, #object + .hidden artMterpAsmInstructionEnd + .global artMterpAsmInstructionEnd +artMterpAsmInstructionEnd: + +%def instruction_end_alt(): + + .type artMterpAsmAltInstructionEnd, #object + .hidden artMterpAsmAltInstructionEnd + .global artMterpAsmAltInstructionEnd +artMterpAsmAltInstructionEnd: + +%def instruction_start(): + + .type artMterpAsmInstructionStart, #object + .hidden artMterpAsmInstructionStart + .global artMterpAsmInstructionStart +artMterpAsmInstructionStart = .L_op_nop + .text + +%def instruction_start_alt(): + + .type artMterpAsmAltInstructionStart, #object + .hidden artMterpAsmAltInstructionStart + .global artMterpAsmAltInstructionStart +artMterpAsmAltInstructionStart = .L_ALT_op_nop + .text diff --git a/runtime/interpreter/mterp/arm64/object.S b/runtime/interpreter/mterp/arm64/object.S new file mode 100644 index 0000000000000000000000000000000000000000..388aba57f8ebb7d5e958b0bb36eb7dcdbeb4300b --- /dev/null +++ b/runtime/interpreter/mterp/arm64/object.S @@ -0,0 +1,263 @@ +%def field(helper=""): + /* + * General field read / write (iget-* iput-* sget-* sput-*). + */ + .extern $helper + mov x0, xPC // arg0: Instruction* inst + mov x1, xINST // arg1: uint16_t inst_data + add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf + mov x3, xSELF // arg3: Thread* self + PREFETCH_INST 2 // prefetch next opcode + bl $helper + cbz x0, MterpPossibleException + ADVANCE 2 + GET_INST_OPCODE ip // extract opcode from rINST + GOTO_OPCODE ip // jump to next instruction + +%def op_check_cast(): + /* + * Check to see if a cast from one class to another is allowed. + */ + /* check-cast vAA, class//BBBB */ + EXPORT_PC + FETCH w0, 1 // w0<- BBBB + lsr w1, wINST, #8 // w1<- AA + VREG_INDEX_TO_ADDR x1, w1 // w1<- &object + ldr x2, [xFP, #OFF_FP_METHOD] // w2<- method + mov x3, xSELF // w3<- self + bl MterpCheckCast // (index, &obj, method, self) + PREFETCH_INST 2 + cbnz w0, MterpPossibleException + ADVANCE 2 + GET_INST_OPCODE ip // extract opcode from rINST + GOTO_OPCODE ip // jump to next instruction + +%def op_iget(is_object="0", helper="MterpIGetU32"): +% field(helper=helper) + +%def op_iget_boolean(): +% op_iget(helper="MterpIGetU8") + +%def op_iget_boolean_quick(): +% op_iget_quick(load="ldrb") + +%def op_iget_byte(): +% op_iget(helper="MterpIGetI8") + +%def op_iget_byte_quick(): +% op_iget_quick(load="ldrsb") + +%def op_iget_char(): +% op_iget(helper="MterpIGetU16") + +%def op_iget_char_quick(): +% op_iget_quick(load="ldrh") + +%def op_iget_object(): +% op_iget(is_object="1", helper="MterpIGetObj") + +%def op_iget_object_quick(): + /* For: iget-object-quick */ + /* op vA, vB, offset//CCCC */ + lsr w2, wINST, #12 // w2<- B + FETCH w1, 1 // w1<- field byte offset + EXPORT_PC + GET_VREG w0, w2 // w0<- object we're operating on + bl artIGetObjectFromMterp // (obj, offset) + ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] + ubfx w2, wINST, #8, #4 // w2<- A + PREFETCH_INST 2 + cbnz w3, MterpPossibleException // bail out + SET_VREG_OBJECT w0, w2 // fp[A]<- w0 + ADVANCE 2 // advance rPC + GET_INST_OPCODE ip // extract opcode from wINST + GOTO_OPCODE ip // jump to next instruction + +%def op_iget_quick(load="ldr", extend=""): + /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ + /* op vA, vB, offset//CCCC */ + lsr w2, wINST, #12 // w2<- B + FETCH w1, 1 // w1<- field byte offset + GET_VREG w3, w2 // w3<- object we're operating on + ubfx w2, wINST, #8, #4 // w2<- A + cbz w3, common_errNullObject // object was null + $load w0, [x3, x1] // w0<- obj.field + FETCH_ADVANCE_INST 2 // advance rPC, load rINST + $extend + SET_VREG w0, w2 // fp[A]<- w0 + GET_INST_OPCODE ip // extract opcode from rINST + GOTO_OPCODE ip // jump to next instruction + +%def op_iget_short(): +% op_iget(helper="MterpIGetI16") + +%def op_iget_short_quick(): +% op_iget_quick(load="ldrsh") + +%def op_iget_wide(): +% op_iget(helper="MterpIGetU64") + +%def op_iget_wide_quick(): + /* iget-wide-quick vA, vB, offset//CCCC */ + lsr w2, wINST, #12 // w2<- B + FETCH w4, 1 // w4<- field byte offset + GET_VREG w3, w2 // w3<- object we're operating on + ubfx w2, wINST, #8, #4 // w2<- A + cbz w3, common_errNullObject // object was null + ldr x0, [x3, x4] // x0<- obj.field + FETCH_ADVANCE_INST 2 // advance rPC, load wINST + SET_VREG_WIDE x0, w2 + GET_INST_OPCODE ip // extract opcode from wINST + GOTO_OPCODE ip // jump to next instruction + +%def op_instance_of(): + /* + * Check to see if an object reference is an instance of a class. + * + * Most common situation is a non-null object, being compared against + * an already-resolved class. + */ + /* instance-of vA, vB, class//CCCC */ + EXPORT_PC + FETCH w0, 1 // w0<- CCCC + lsr w1, wINST, #12 // w1<- B + VREG_INDEX_TO_ADDR x1, w1 // w1<- &object + ldr x2, [xFP, #OFF_FP_METHOD] // w2<- method + mov x3, xSELF // w3<- self + bl MterpInstanceOf // (index, &obj, method, self) + ldr x1, [xSELF, #THREAD_EXCEPTION_OFFSET] + ubfx w2, wINST, #8, #4 // w2<- A + PREFETCH_INST 2 + cbnz x1, MterpException + ADVANCE 2 // advance rPC + SET_VREG w0, w2 // vA<- w0 + GET_INST_OPCODE ip // extract opcode from rINST + GOTO_OPCODE ip // jump to next instruction + +%def op_iput(is_object="0", helper="MterpIPutU32"): +% field(helper=helper) + +%def op_iput_boolean(): +% op_iput(helper="MterpIPutU8") + +%def op_iput_boolean_quick(): +% op_iput_quick(store="strb") + +%def op_iput_byte(): +% op_iput(helper="MterpIPutI8") + +%def op_iput_byte_quick(): +% op_iput_quick(store="strb") + +%def op_iput_char(): +% op_iput(helper="MterpIPutU16") + +%def op_iput_char_quick(): +% op_iput_quick(store="strh") + +%def op_iput_object(): +% op_iput(is_object="1", helper="MterpIPutObj") + +%def op_iput_object_quick(): + EXPORT_PC + add x0, xFP, #OFF_FP_SHADOWFRAME + mov x1, xPC + mov w2, wINST + bl MterpIputObjectQuick + cbz w0, MterpException + FETCH_ADVANCE_INST 2 // advance rPC, load rINST + GET_INST_OPCODE ip // extract opcode from rINST + GOTO_OPCODE ip // jump to next instruction + +%def op_iput_quick(store="str"): + /* For: iput-quick, iput-object-quick */ + /* op vA, vB, offset//CCCC */ + lsr w2, wINST, #12 // w2<- B + FETCH w1, 1 // w1<- field byte offset + GET_VREG w3, w2 // w3<- fp[B], the object pointer + ubfx w2, wINST, #8, #4 // w2<- A + cbz w3, common_errNullObject // object was null + GET_VREG w0, w2 // w0<- fp[A] + FETCH_ADVANCE_INST 2 // advance rPC, load rINST + $store w0, [x3, x1] // obj.field<- w0 + GET_INST_OPCODE ip // extract opcode from rINST + GOTO_OPCODE ip // jump to next instruction + +%def op_iput_short(): +% op_iput(helper="MterpIPutI16") + +%def op_iput_short_quick(): +% op_iput_quick(store="strh") + +%def op_iput_wide(): +% op_iput(helper="MterpIPutU64") + +%def op_iput_wide_quick(): + /* iput-wide-quick vA, vB, offset//CCCC */ + lsr w2, wINST, #12 // w2<- B + FETCH w3, 1 // w3<- field byte offset + GET_VREG w2, w2 // w2<- fp[B], the object pointer + ubfx w0, wINST, #8, #4 // w0<- A + cbz w2, common_errNullObject // object was null + GET_VREG_WIDE x0, w0 // x0<- fp[A] + FETCH_ADVANCE_INST 2 // advance rPC, load wINST + str x0, [x2, x3] // obj.field<- x0 + GET_INST_OPCODE ip // extract opcode from wINST + GOTO_OPCODE ip // jump to next instruction + +%def op_new_instance(): + /* + * Create a new instance of a class. + */ + /* new-instance vAA, class//BBBB */ + EXPORT_PC + add x0, xFP, #OFF_FP_SHADOWFRAME + mov x1, xSELF + mov w2, wINST + bl MterpNewInstance // (shadow_frame, self, inst_data) + cbz w0, MterpPossibleException + FETCH_ADVANCE_INST 2 // advance rPC, load rINST + GET_INST_OPCODE ip // extract opcode from rINST + GOTO_OPCODE ip // jump to next instruction + +%def op_sget(is_object="0", helper="MterpSGetU32"): +% field(helper=helper) + +%def op_sget_boolean(): +% op_sget(helper="MterpSGetU8") + +%def op_sget_byte(): +% op_sget(helper="MterpSGetI8") + +%def op_sget_char(): +% op_sget(helper="MterpSGetU16") + +%def op_sget_object(): +% op_sget(is_object="1", helper="MterpSGetObj") + +%def op_sget_short(): +% op_sget(helper="MterpSGetI16") + +%def op_sget_wide(): +% op_sget(helper="MterpSGetU64") + +%def op_sput(is_object="0", helper="MterpSPutU32"): +% field(helper=helper) + +%def op_sput_boolean(): +% op_sput(helper="MterpSPutU8") + +%def op_sput_byte(): +% op_sput(helper="MterpSPutI8") + +%def op_sput_char(): +% op_sput(helper="MterpSPutU16") + +%def op_sput_object(): +% op_sput(is_object="1", helper="MterpSPutObj") + +%def op_sput_short(): +% op_sput(helper="MterpSPutI16") + +%def op_sput_wide(): +% op_sput(helper="MterpSPutU64") diff --git a/runtime/interpreter/mterp/arm64/op_add_double.S b/runtime/interpreter/mterp/arm64/op_add_double.S deleted file mode 100644 index 8509f70309a0052ddeda5ca318f87fb9cd15fd46..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_add_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binopWide.S" {"instr":"fadd d0, d1, d2", "result":"d0", "r1":"d1", "r2":"d2"} diff --git a/runtime/interpreter/mterp/arm64/op_add_double_2addr.S b/runtime/interpreter/mterp/arm64/op_add_double_2addr.S deleted file mode 100644 index 61fd58f4b65c89294375b2d112c46301cb9cfc45..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_add_double_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binopWide2addr.S" {"instr":"fadd d0, d0, d1", "r0":"d0", "r1":"d1"} diff --git a/runtime/interpreter/mterp/arm64/op_add_float.S b/runtime/interpreter/mterp/arm64/op_add_float.S deleted file mode 100644 index 7d09fef10ad7cd752b1990fa9fae4c3b25f82726..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_add_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/fbinop.S" {"instr":"fadd s0, s0, s1"} diff --git a/runtime/interpreter/mterp/arm64/op_add_float_2addr.S b/runtime/interpreter/mterp/arm64/op_add_float_2addr.S deleted file mode 100644 index 7b378e2889e6145782f0994b13ba3b4357a5c63e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_add_float_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/fbinop2addr.S" {"instr":"fadd s2, s0, s1"} diff --git a/runtime/interpreter/mterp/arm64/op_add_int.S b/runtime/interpreter/mterp/arm64/op_add_int.S deleted file mode 100644 index 6eadb5441d2fb50462b3ddbcc0ad9a1d22c95c8e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_add_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binop.S" {"instr":"add w0, w0, w1"} diff --git a/runtime/interpreter/mterp/arm64/op_add_int_2addr.S b/runtime/interpreter/mterp/arm64/op_add_int_2addr.S deleted file mode 100644 index d35bc8ecc91c9eaed1f165b04808734c1a167883..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_add_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binop2addr.S" {"instr":"add w0, w0, w1"} diff --git a/runtime/interpreter/mterp/arm64/op_add_int_lit16.S b/runtime/interpreter/mterp/arm64/op_add_int_lit16.S deleted file mode 100644 index 4930ad77162e7d8b6f7f7beb43b119c71e63dd0b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_add_int_lit16.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binopLit16.S" {"instr":"add w0, w0, w1"} diff --git a/runtime/interpreter/mterp/arm64/op_add_int_lit8.S b/runtime/interpreter/mterp/arm64/op_add_int_lit8.S deleted file mode 100644 index 2dfb8b9b56a9453d958631d74bdbe95750d82ae1..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_add_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binopLit8.S" {"extract":"", "instr":"add w0, w0, w3, asr #8"} diff --git a/runtime/interpreter/mterp/arm64/op_add_long.S b/runtime/interpreter/mterp/arm64/op_add_long.S deleted file mode 100644 index bc334aa3b246d62eaa3e56d66c1c3f50bf1d9af3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_add_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binopWide.S" {"instr":"add x0, x1, x2"} diff --git a/runtime/interpreter/mterp/arm64/op_add_long_2addr.S b/runtime/interpreter/mterp/arm64/op_add_long_2addr.S deleted file mode 100644 index 5e5dbce73becd9fcbbf5a615a7000e754cb5fe7e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_add_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binopWide2addr.S" {"instr":"add x0, x0, x1"} diff --git a/runtime/interpreter/mterp/arm64/op_aget.S b/runtime/interpreter/mterp/arm64/op_aget.S deleted file mode 100644 index 662c9cc7cc4303ae18234120cf2fbb8523add040..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_aget.S +++ /dev/null @@ -1,28 +0,0 @@ -%default { "load":"ldr", "shift":"2", "data_offset":"MIRROR_INT_ARRAY_DATA_OFFSET" } - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B w2, 1, 0 // w2<- BB - lsr w9, wINST, #8 // w9<- AA - FETCH_B w3, 1, 1 // w3<- CC - GET_VREG w0, w2 // w0<- vBB (array object) - GET_VREG w1, w3 // w1<- vCC (requested index) - cbz x0, common_errNullObject // bail if null array object. - ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length - add x0, x0, w1, uxtw #$shift // w0<- arrayObj + index*width - cmp w1, w3 // compare unsigned index, length - bcs common_errArrayIndex // index >= length, bail - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - $load w2, [x0, #$data_offset] // w2<- vBB[vCC] - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w2, w9 // vAA<- w2 - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_aget_boolean.S b/runtime/interpreter/mterp/arm64/op_aget_boolean.S deleted file mode 100644 index 6ab6cc1bff296e5191aed3ef0bb77a33f0da1744..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_aget_boolean.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_aget.S" { "load":"ldrb", "shift":"0", "data_offset":"MIRROR_BOOLEAN_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/arm64/op_aget_byte.S b/runtime/interpreter/mterp/arm64/op_aget_byte.S deleted file mode 100644 index c7f5b23ebfa24ebbb2fc36d77e9fad8cc01b8e9e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_aget_byte.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_aget.S" { "load":"ldrsb", "shift":"0", "data_offset":"MIRROR_BYTE_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/arm64/op_aget_char.S b/runtime/interpreter/mterp/arm64/op_aget_char.S deleted file mode 100644 index 9fddf1787ace54dc3c46d4d8a0dfaae728d70f12..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_aget_char.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_aget.S" { "load":"ldrh", "shift":"1", "data_offset":"MIRROR_CHAR_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/arm64/op_aget_object.S b/runtime/interpreter/mterp/arm64/op_aget_object.S deleted file mode 100644 index 1bbe3e8a3a432b6fe04517e09cdfde5d5f8472b1..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_aget_object.S +++ /dev/null @@ -1,20 +0,0 @@ - /* - * Array object get. vAA <- vBB[vCC]. - * - * for: aget-object - */ - /* op vAA, vBB, vCC */ - FETCH_B w2, 1, 0 // w2<- BB - FETCH_B w3, 1, 1 // w3<- CC - EXPORT_PC - GET_VREG w0, w2 // w0<- vBB (array object) - GET_VREG w1, w3 // w1<- vCC (requested index) - bl artAGetObjectFromMterp // (array, index) - ldr x1, [xSELF, #THREAD_EXCEPTION_OFFSET] - lsr w2, wINST, #8 // w9<- AA - PREFETCH_INST 2 - cbnz w1, MterpException - SET_VREG_OBJECT w0, w2 - ADVANCE 2 - GET_INST_OPCODE ip - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_aget_short.S b/runtime/interpreter/mterp/arm64/op_aget_short.S deleted file mode 100644 index 39554de6e6ec667fcf4c727dbdee23a699191c04..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_aget_short.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_aget.S" { "load":"ldrsh", "shift":"1", "data_offset":"MIRROR_SHORT_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/arm64/op_aget_wide.S b/runtime/interpreter/mterp/arm64/op_aget_wide.S deleted file mode 100644 index 6f990ba0cc02b653c5bd38dab659ae82787dd579..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_aget_wide.S +++ /dev/null @@ -1,21 +0,0 @@ - /* - * Array get, 64 bits. vAA <- vBB[vCC]. - * - */ - /* aget-wide vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - and w2, w0, #255 // w2<- BB - lsr w3, w0, #8 // w3<- CC - GET_VREG w0, w2 // w0<- vBB (array object) - GET_VREG w1, w3 // w1<- vCC (requested index) - cbz w0, common_errNullObject // yes, bail - ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length - add x0, x0, w1, lsl #3 // w0<- arrayObj + index*width - cmp w1, w3 // compare unsigned index, length - bcs common_errArrayIndex // index >= length, bail - FETCH_ADVANCE_INST 2 // advance rPC, load wINST - ldr x2, [x0, #MIRROR_WIDE_ARRAY_DATA_OFFSET] // x2<- vBB[vCC] - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG_WIDE x2, w4 - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_and_int.S b/runtime/interpreter/mterp/arm64/op_and_int.S deleted file mode 100644 index 31f3f73e7a11458a97c89db4a77aebf9a940efb1..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_and_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binop.S" {"instr":"and w0, w0, w1"} diff --git a/runtime/interpreter/mterp/arm64/op_and_int_2addr.S b/runtime/interpreter/mterp/arm64/op_and_int_2addr.S deleted file mode 100644 index e59632cd06bea134609e30fe41aff1e2e095317a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_and_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binop2addr.S" {"instr":"and w0, w0, w1"} diff --git a/runtime/interpreter/mterp/arm64/op_and_int_lit16.S b/runtime/interpreter/mterp/arm64/op_and_int_lit16.S deleted file mode 100644 index 6540f81554285781555836bfd39b1656f7f2d35d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_and_int_lit16.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binopLit16.S" {"instr":"and w0, w0, w1"} diff --git a/runtime/interpreter/mterp/arm64/op_and_int_lit8.S b/runtime/interpreter/mterp/arm64/op_and_int_lit8.S deleted file mode 100644 index 495b5cddd6f512aa54fb655e2ecfa1d403dc8160..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_and_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binopLit8.S" {"extract":"", "instr":"and w0, w0, w3, asr #8"} diff --git a/runtime/interpreter/mterp/arm64/op_and_long.S b/runtime/interpreter/mterp/arm64/op_and_long.S deleted file mode 100644 index ede047d0883b99a1ab8a618d7a1ca522bfb4484c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_and_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binopWide.S" {"instr":"and x0, x1, x2"} diff --git a/runtime/interpreter/mterp/arm64/op_and_long_2addr.S b/runtime/interpreter/mterp/arm64/op_and_long_2addr.S deleted file mode 100644 index d62ccef8919cf3bce201f3fefdbdccaa4521fb73..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_and_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binopWide2addr.S" {"instr":"and x0, x0, x1"} diff --git a/runtime/interpreter/mterp/arm64/op_aput.S b/runtime/interpreter/mterp/arm64/op_aput.S deleted file mode 100644 index 175b483d7d7ca56904d63caf6ab8f691407b00ac..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_aput.S +++ /dev/null @@ -1,28 +0,0 @@ -%default { "store":"str", "shift":"2", "data_offset":"MIRROR_INT_ARRAY_DATA_OFFSET" } - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B w2, 1, 0 // w2<- BB - lsr w9, wINST, #8 // w9<- AA - FETCH_B w3, 1, 1 // w3<- CC - GET_VREG w0, w2 // w0<- vBB (array object) - GET_VREG w1, w3 // w1<- vCC (requested index) - cbz w0, common_errNullObject // bail if null - ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length - add x0, x0, w1, lsl #$shift // w0<- arrayObj + index*width - cmp w1, w3 // compare unsigned index, length - bcs common_errArrayIndex // index >= length, bail - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_VREG w2, w9 // w2<- vAA - GET_INST_OPCODE ip // extract opcode from rINST - $store w2, [x0, #$data_offset] // vBB[vCC]<- w2 - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_aput_boolean.S b/runtime/interpreter/mterp/arm64/op_aput_boolean.S deleted file mode 100644 index 5e7a86f15c46c8bee72563f558eba02f415c9d82..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_aput_boolean.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_aput.S" { "store":"strb", "shift":"0", "data_offset":"MIRROR_BOOLEAN_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/arm64/op_aput_byte.S b/runtime/interpreter/mterp/arm64/op_aput_byte.S deleted file mode 100644 index d659ebc3d026dab82128ea247b25d946dfb25ab3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_aput_byte.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_aput.S" { "store":"strb", "shift":"0", "data_offset":"MIRROR_BYTE_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/arm64/op_aput_char.S b/runtime/interpreter/mterp/arm64/op_aput_char.S deleted file mode 100644 index 7547c808705030eec6796ba744ce01885952d615..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_aput_char.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_aput.S" { "store":"strh", "shift":"1", "data_offset":"MIRROR_CHAR_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/arm64/op_aput_object.S b/runtime/interpreter/mterp/arm64/op_aput_object.S deleted file mode 100644 index 0146fdc95c2f440ed5d6475d1d2f1730a15d3ef4..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_aput_object.S +++ /dev/null @@ -1,13 +0,0 @@ - /* - * Store an object into an array. vBB[vCC] <- vAA. - */ - /* op vAA, vBB, vCC */ - EXPORT_PC - add x0, xFP, #OFF_FP_SHADOWFRAME - mov x1, xPC - mov w2, wINST - bl MterpAputObject - cbz w0, MterpPossibleException - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_aput_short.S b/runtime/interpreter/mterp/arm64/op_aput_short.S deleted file mode 100644 index 8631e280709689116ce8c463512dfb8d0c9037c6..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_aput_short.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_aput.S" { "store":"strh", "shift":"1", "data_offset":"MIRROR_SHORT_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/arm64/op_aput_wide.S b/runtime/interpreter/mterp/arm64/op_aput_wide.S deleted file mode 100644 index e1cf9c1c2f78cffbc7b9967ceae5046a1ee16048..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_aput_wide.S +++ /dev/null @@ -1,21 +0,0 @@ - /* - * Array put, 64 bits. vBB[vCC] <- vAA. - * - */ - /* aput-wide vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - and w2, w0, #255 // w2<- BB - lsr w3, w0, #8 // w3<- CC - GET_VREG w0, w2 // w0<- vBB (array object) - GET_VREG w1, w3 // w1<- vCC (requested index) - cbz w0, common_errNullObject // bail if null - ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length - add x0, x0, w1, lsl #3 // w0<- arrayObj + index*width - cmp w1, w3 // compare unsigned index, length - bcs common_errArrayIndex // index >= length, bail - GET_VREG_WIDE x1, w4 - FETCH_ADVANCE_INST 2 // advance rPC, load wINST - GET_INST_OPCODE ip // extract opcode from wINST - str x1, [x0, #MIRROR_WIDE_ARRAY_DATA_OFFSET] - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_array_length.S b/runtime/interpreter/mterp/arm64/op_array_length.S deleted file mode 100644 index 0cce917ff7dea0cfba4fd3220060665ca0be0fc9..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_array_length.S +++ /dev/null @@ -1,12 +0,0 @@ - /* - * Return the length of an array. - */ - lsr w1, wINST, #12 // w1<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG w0, w1 // w0<- vB (object ref) - cbz w0, common_errNullObject // yup, fail - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- array length - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w3, w2 // vB<- length - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_check_cast.S b/runtime/interpreter/mterp/arm64/op_check_cast.S deleted file mode 100644 index cb9f6068e0e3f028b75aa10b9a6368d2bd479a2c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_check_cast.S +++ /dev/null @@ -1,16 +0,0 @@ - /* - * Check to see if a cast from one class to another is allowed. - */ - /* check-cast vAA, class//BBBB */ - EXPORT_PC - FETCH w0, 1 // w0<- BBBB - lsr w1, wINST, #8 // w1<- AA - VREG_INDEX_TO_ADDR x1, w1 // w1<- &object - ldr x2, [xFP, #OFF_FP_METHOD] // w2<- method - mov x3, xSELF // w3<- self - bl MterpCheckCast // (index, &obj, method, self) - PREFETCH_INST 2 - cbnz w0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_cmp_long.S b/runtime/interpreter/mterp/arm64/op_cmp_long.S deleted file mode 100644 index c4ad984084cde170c2ff4907f73aae34393423c0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_cmp_long.S +++ /dev/null @@ -1,13 +0,0 @@ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - and w2, w0, #255 // w2<- BB - lsr w3, w0, #8 // w3<- CC - GET_VREG_WIDE x1, w2 - GET_VREG_WIDE x2, w3 - cmp x1, x2 - cset w0, ne - cneg w0, w0, lt - FETCH_ADVANCE_INST 2 // advance rPC, load wINST - SET_VREG w0, w4 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_cmpg_double.S b/runtime/interpreter/mterp/arm64/op_cmpg_double.S deleted file mode 100644 index 30cb7ebbe2a9afb3f88abe7ae54ff56fbe9383e9..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_cmpg_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/fcmp.S" {"wide":"_WIDE", "r1":"d1", "r2":"d2", "cond":"cc"} diff --git a/runtime/interpreter/mterp/arm64/op_cmpg_float.S b/runtime/interpreter/mterp/arm64/op_cmpg_float.S deleted file mode 100644 index ba23f434620a16f91b117379c0954f0473815685..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_cmpg_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/fcmp.S" {"wide":"", "r1":"s1", "r2":"s2", "cond":"cc"} diff --git a/runtime/interpreter/mterp/arm64/op_cmpl_double.S b/runtime/interpreter/mterp/arm64/op_cmpl_double.S deleted file mode 100644 index c73968588e451f7dbfd0f896c21bb3a82aebf3bf..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_cmpl_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/fcmp.S" {"wide":"_WIDE", "r1":"d1", "r2":"d2", "cond":"lt"} diff --git a/runtime/interpreter/mterp/arm64/op_cmpl_float.S b/runtime/interpreter/mterp/arm64/op_cmpl_float.S deleted file mode 100644 index 32a931935b5aac894dfcfc6e016d120908dd5c92..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_cmpl_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/fcmp.S" {"wide":"", "r1":"s1", "r2":"s2", "cond":"lt"} diff --git a/runtime/interpreter/mterp/arm64/op_const.S b/runtime/interpreter/mterp/arm64/op_const.S deleted file mode 100644 index 031ede1fb23d6111b7cc051e14bf47d73cf775d8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_const.S +++ /dev/null @@ -1,9 +0,0 @@ - /* const vAA, #+BBBBbbbb */ - lsr w3, wINST, #8 // w3<- AA - FETCH w0, 1 // w0<- bbbb (low - FETCH w1, 2 // w1<- BBBB (high - FETCH_ADVANCE_INST 3 // advance rPC, load wINST - orr w0, w0, w1, lsl #16 // w0<- BBBBbbbb - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG w0, w3 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_const_16.S b/runtime/interpreter/mterp/arm64/op_const_16.S deleted file mode 100644 index f0e81923c5c17136fb37f7953d400f8f3de681ac..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_const_16.S +++ /dev/null @@ -1,7 +0,0 @@ - /* const/16 vAA, #+BBBB */ - FETCH_S w0, 1 // w0<- ssssBBBB (sign-extended) - lsr w3, wINST, #8 // w3<- AA - FETCH_ADVANCE_INST 2 // advance xPC, load wINST - SET_VREG w0, w3 // vAA<- w0 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_const_4.S b/runtime/interpreter/mterp/arm64/op_const_4.S deleted file mode 100644 index 9a36115288617f4b099ea4f6590bdd9e0e0c3c1a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_const_4.S +++ /dev/null @@ -1,7 +0,0 @@ - /* const/4 vA, #+B */ - sbfx w1, wINST, #12, #4 // w1<- sssssssB - ubfx w0, wINST, #8, #4 // w0<- A - FETCH_ADVANCE_INST 1 // advance xPC, load wINST - GET_INST_OPCODE ip // ip<- opcode from xINST - SET_VREG w1, w0 // fp[A]<- w1 - GOTO_OPCODE ip // execute next instruction diff --git a/runtime/interpreter/mterp/arm64/op_const_class.S b/runtime/interpreter/mterp/arm64/op_const_class.S deleted file mode 100644 index 7228245b8fe76d6cd1a5af10cb901cf334b117d9..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_const_class.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/const.S" { "helper":"MterpConstClass" } diff --git a/runtime/interpreter/mterp/arm64/op_const_high16.S b/runtime/interpreter/mterp/arm64/op_const_high16.S deleted file mode 100644 index 3a9edfff91676f703a91e09497adb89e0d168eb5..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_const_high16.S +++ /dev/null @@ -1,8 +0,0 @@ - /* const/high16 vAA, #+BBBB0000 */ - FETCH w0, 1 // r0<- 0000BBBB (zero-extended) - lsr w3, wINST, #8 // r3<- AA - lsl w0, w0, #16 // r0<- BBBB0000 - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - SET_VREG w0, w3 // vAA<- r0 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_const_method_handle.S b/runtime/interpreter/mterp/arm64/op_const_method_handle.S deleted file mode 100644 index 0df0fa67988b361a2982a47dd63ec10efdbb96d0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_const_method_handle.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/const.S" { "helper":"MterpConstMethodHandle" } diff --git a/runtime/interpreter/mterp/arm64/op_const_method_type.S b/runtime/interpreter/mterp/arm64/op_const_method_type.S deleted file mode 100644 index 1adfe5ad659badc90010c2cc3dafcf37f0cb7086..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_const_method_type.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/const.S" { "helper":"MterpConstMethodType" } diff --git a/runtime/interpreter/mterp/arm64/op_const_string.S b/runtime/interpreter/mterp/arm64/op_const_string.S deleted file mode 100644 index 8cf0d6dc358996e7080f34883236a49b3c75b13b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_const_string.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/const.S" { "helper":"MterpConstString" } diff --git a/runtime/interpreter/mterp/arm64/op_const_string_jumbo.S b/runtime/interpreter/mterp/arm64/op_const_string_jumbo.S deleted file mode 100644 index e1a733987d3be2706c87040c111c336446a8fba6..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_const_string_jumbo.S +++ /dev/null @@ -1,14 +0,0 @@ - /* const/string vAA, String//BBBBBBBB */ - EXPORT_PC - FETCH w0, 1 // w0<- bbbb (low - FETCH w2, 2 // w2<- BBBB (high - lsr w1, wINST, #8 // w1<- AA - orr w0, w0, w2, lsl #16 // w1<- BBBBbbbb - add x2, xFP, #OFF_FP_SHADOWFRAME - mov x3, xSELF - bl MterpConstString // (index, tgt_reg, shadow_frame, self) - PREFETCH_INST 3 // advance rPC - cbnz w0, MterpPossibleException // let reference interpreter deal with it. - ADVANCE 3 // advance rPC - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_const_wide.S b/runtime/interpreter/mterp/arm64/op_const_wide.S deleted file mode 100644 index 8f57ddacfd84acda953ec214262b8e1a374e2995..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_const_wide.S +++ /dev/null @@ -1,13 +0,0 @@ - /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ - FETCH w0, 1 // w0<- bbbb (low) - FETCH w1, 2 // w1<- BBBB (low middle) - FETCH w2, 3 // w2<- hhhh (high middle) - FETCH w3, 4 // w3<- HHHH (high) - lsr w4, wINST, #8 // r4<- AA - FETCH_ADVANCE_INST 5 // advance rPC, load wINST - GET_INST_OPCODE ip // extract opcode from wINST - orr w0, w0, w1, lsl #16 // w0<- BBBBbbbb - orr x0, x0, x2, lsl #32 // w0<- hhhhBBBBbbbb - orr x0, x0, x3, lsl #48 // w0<- HHHHhhhhBBBBbbbb - SET_VREG_WIDE x0, w4 - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_const_wide_16.S b/runtime/interpreter/mterp/arm64/op_const_wide_16.S deleted file mode 100644 index 553d4815418c4389233f8788424cf12908571281..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_const_wide_16.S +++ /dev/null @@ -1,7 +0,0 @@ - /* const-wide/16 vAA, #+BBBB */ - FETCH_S x0, 1 // x0<- ssssssssssssBBBB (sign-extended) - lsr w3, wINST, #8 // w3<- AA - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w3 - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_const_wide_32.S b/runtime/interpreter/mterp/arm64/op_const_wide_32.S deleted file mode 100644 index 9dc4fc3867b5a926db67cd4e29d94f97bb25dbf9..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_const_wide_32.S +++ /dev/null @@ -1,9 +0,0 @@ - /* const-wide/32 vAA, #+BBBBbbbb */ - FETCH w0, 1 // x0<- 000000000000bbbb (low) - lsr w3, wINST, #8 // w3<- AA - FETCH_S x2, 2 // x2<- ssssssssssssBBBB (high) - FETCH_ADVANCE_INST 3 // advance rPC, load wINST - GET_INST_OPCODE ip // extract opcode from wINST - orr x0, x0, x2, lsl #16 // x0<- ssssssssBBBBbbbb - SET_VREG_WIDE x0, w3 - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_const_wide_high16.S b/runtime/interpreter/mterp/arm64/op_const_wide_high16.S deleted file mode 100644 index 94ab9876c8ea3729a27805a4fb18e0727a885a2d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_const_wide_high16.S +++ /dev/null @@ -1,8 +0,0 @@ - /* const-wide/high16 vAA, #+BBBB000000000000 */ - FETCH w0, 1 // w0<- 0000BBBB (zero-extended) - lsr w1, wINST, #8 // w1<- AA - FETCH_ADVANCE_INST 2 // advance rPC, load wINST - lsl x0, x0, #48 - SET_VREG_WIDE x0, w1 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_div_double.S b/runtime/interpreter/mterp/arm64/op_div_double.S deleted file mode 100644 index 1f7dad0917fa4c39953bde8daa0991b0b01375c2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_div_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binopWide.S" {"instr":"fdiv d0, d1, d2", "result":"d0", "r1":"d1", "r2":"d2"} diff --git a/runtime/interpreter/mterp/arm64/op_div_double_2addr.S b/runtime/interpreter/mterp/arm64/op_div_double_2addr.S deleted file mode 100644 index 414a17565842dd338f6f0c9bfe6a6560a98f5cb7..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_div_double_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binopWide2addr.S" {"instr":"fdiv d0, d0, d1", "r0":"d0", "r1":"d1"} diff --git a/runtime/interpreter/mterp/arm64/op_div_float.S b/runtime/interpreter/mterp/arm64/op_div_float.S deleted file mode 100644 index f24a26c09bad97e329538e5694542f47a5239032..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_div_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/fbinop.S" {"instr":"fdiv s0, s0, s1"} diff --git a/runtime/interpreter/mterp/arm64/op_div_float_2addr.S b/runtime/interpreter/mterp/arm64/op_div_float_2addr.S deleted file mode 100644 index 2888049c9ea732dfe03a0f51b9001a15b5e4960c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_div_float_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/fbinop2addr.S" {"instr":"fdiv s2, s0, s1"} diff --git a/runtime/interpreter/mterp/arm64/op_div_int.S b/runtime/interpreter/mterp/arm64/op_div_int.S deleted file mode 100644 index 88371c08d9a31a418623fb9efbc0719427e9a812..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_div_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binop.S" {"instr":"sdiv w0, w0, w1", "chkzero":"1"} diff --git a/runtime/interpreter/mterp/arm64/op_div_int_2addr.S b/runtime/interpreter/mterp/arm64/op_div_int_2addr.S deleted file mode 100644 index 5f5a80fe524a26462e3c1d22e378598a57cd54db..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_div_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binop2addr.S" {"instr":"sdiv w0, w0, w1", "chkzero":"1"} diff --git a/runtime/interpreter/mterp/arm64/op_div_int_lit16.S b/runtime/interpreter/mterp/arm64/op_div_int_lit16.S deleted file mode 100644 index dc7a484c6ab1a122c3629d2321d227b81f53eb30..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_div_int_lit16.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binopLit16.S" {"instr":"sdiv w0, w0, w1", "chkzero":"1"} diff --git a/runtime/interpreter/mterp/arm64/op_div_int_lit8.S b/runtime/interpreter/mterp/arm64/op_div_int_lit8.S deleted file mode 100644 index c06521c4bc728dfb11a5565c8ed96698bd3f5493..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_div_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binopLit8.S" {"instr":"sdiv w0, w0, w1", "chkzero":"1"} diff --git a/runtime/interpreter/mterp/arm64/op_div_long.S b/runtime/interpreter/mterp/arm64/op_div_long.S deleted file mode 100644 index 820ae3db6831cab582fb62a3d314cfe523d6a339..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_div_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binopWide.S" {"instr":"sdiv x0, x1, x2", "chkzero":"1"} diff --git a/runtime/interpreter/mterp/arm64/op_div_long_2addr.S b/runtime/interpreter/mterp/arm64/op_div_long_2addr.S deleted file mode 100644 index da7eabdc9d9f449e211e36d8be650a36d036a286..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_div_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binopWide2addr.S" {"instr":"sdiv x0, x0, x1", "chkzero":"1"} diff --git a/runtime/interpreter/mterp/arm64/op_double_to_float.S b/runtime/interpreter/mterp/arm64/op_double_to_float.S deleted file mode 100644 index c1555fdaf9416fcd5d92be0cb68be4665fba23a0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_double_to_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/funopNarrower.S" {"instr":"fcvt s0, d0", "srcreg":"d0", "tgtreg":"s0"} diff --git a/runtime/interpreter/mterp/arm64/op_double_to_int.S b/runtime/interpreter/mterp/arm64/op_double_to_int.S deleted file mode 100644 index 7244bac2fc182c373528e7d6cfe84cbee5c1d5f6..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_double_to_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/funopNarrower.S" {"instr":"fcvtzs w0, d0", "srcreg":"d0", "tgtreg":"w0"} diff --git a/runtime/interpreter/mterp/arm64/op_double_to_long.S b/runtime/interpreter/mterp/arm64/op_double_to_long.S deleted file mode 100644 index 741160b564449bed0f0aec852b18916e77278e26..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_double_to_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/funopWide.S" {"instr":"fcvtzs x0, d0", "srcreg":"d0", "tgtreg":"x0"} diff --git a/runtime/interpreter/mterp/arm64/op_fill_array_data.S b/runtime/interpreter/mterp/arm64/op_fill_array_data.S deleted file mode 100644 index 86fa6dbbd2775f20a4b60a7da0ea9c70857ad775..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_fill_array_data.S +++ /dev/null @@ -1,13 +0,0 @@ - /* fill-array-data vAA, +BBBBBBBB */ - EXPORT_PC - FETCH w0, 1 // x0<- 000000000000bbbb (lo) - FETCH_S x1, 2 // x1<- ssssssssssssBBBB (hi) - lsr w3, wINST, #8 // w3<- AA - orr x1, x0, x1, lsl #16 // x1<- ssssssssBBBBbbbb - GET_VREG w0, w3 // w0<- vAA (array object) - add x1, xPC, x1, lsl #1 // x1<- PC + ssssssssBBBBbbbb*2 (array data off.) - bl MterpFillArrayData // (obj, payload) - cbz w0, MterpPossibleException // exception? - FETCH_ADVANCE_INST 3 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_filled_new_array.S b/runtime/interpreter/mterp/arm64/op_filled_new_array.S deleted file mode 100644 index 806a1b1201862872aad7b472f2718152c3e0a83f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_filled_new_array.S +++ /dev/null @@ -1,18 +0,0 @@ -%default { "helper":"MterpFilledNewArray" } - /* - * Create a new array with elements filled from registers. - * - * for: filled-new-array, filled-new-array/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class//CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, type//BBBB */ - .extern $helper - EXPORT_PC - add x0, xFP, #OFF_FP_SHADOWFRAME - mov x1, xPC - mov x2, xSELF - bl $helper - cbz w0, MterpPossibleException - FETCH_ADVANCE_INST 3 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_filled_new_array_range.S b/runtime/interpreter/mterp/arm64/op_filled_new_array_range.S deleted file mode 100644 index 3c9a419628eef7f011d15e97c9389680ff84df0b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_filled_new_array_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_filled_new_array.S" { "helper":"MterpFilledNewArrayRange" } diff --git a/runtime/interpreter/mterp/arm64/op_float_to_double.S b/runtime/interpreter/mterp/arm64/op_float_to_double.S deleted file mode 100644 index 892feca21b91012fb666048642f24241bc7d3493..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_float_to_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/funopWider.S" {"instr":"fcvt d0, s0", "srcreg":"s0", "tgtreg":"d0"} diff --git a/runtime/interpreter/mterp/arm64/op_float_to_int.S b/runtime/interpreter/mterp/arm64/op_float_to_int.S deleted file mode 100644 index c849d8165d191375ba9ba88d9633bed05cfb259b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_float_to_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/funopNarrow.S" {"instr":"fcvtzs w0, s0", "srcreg":"s0", "tgtreg":"w0"} diff --git a/runtime/interpreter/mterp/arm64/op_float_to_long.S b/runtime/interpreter/mterp/arm64/op_float_to_long.S deleted file mode 100644 index c3de16f9ffa8b1856892bb6fca505703e691ea63..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_float_to_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/funopWider.S" {"instr":"fcvtzs x0, s0", "srcreg":"s0", "tgtreg":"x0"} diff --git a/runtime/interpreter/mterp/arm64/op_goto.S b/runtime/interpreter/mterp/arm64/op_goto.S deleted file mode 100644 index 6381e94fb5167b601487bd50096449c2b6e76b8a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_goto.S +++ /dev/null @@ -1,9 +0,0 @@ - /* - * Unconditional branch, 8-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto +AA */ - sbfx wINST, wINST, #8, #8 // wINST<- ssssssAA (sign-extended) - b MterpCommonTakenBranchNoFlags diff --git a/runtime/interpreter/mterp/arm64/op_goto_16.S b/runtime/interpreter/mterp/arm64/op_goto_16.S deleted file mode 100644 index fb9a80a3c18ff847469f88c6befaad493d7ef12d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_goto_16.S +++ /dev/null @@ -1,9 +0,0 @@ - /* - * Unconditional branch, 16-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto/16 +AAAA */ - FETCH_S wINST, 1 // wINST<- ssssAAAA (sign-extended) - b MterpCommonTakenBranchNoFlags diff --git a/runtime/interpreter/mterp/arm64/op_goto_32.S b/runtime/interpreter/mterp/arm64/op_goto_32.S deleted file mode 100644 index b13cb41bc71e260d6e338bb2915a525525a501b0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_goto_32.S +++ /dev/null @@ -1,16 +0,0 @@ - /* - * Unconditional branch, 32-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - * - * Unlike most opcodes, this one is allowed to branch to itself, so - * our "backward branch" test must be "<=0" instead of "<0". Because - * we need the V bit set, we'll use an adds to convert from Dalvik - * offset to byte offset. - */ - /* goto/32 +AAAAAAAA */ - FETCH w0, 1 // w0<- aaaa (lo) - FETCH w1, 2 // w1<- AAAA (hi) - orr wINST, w0, w1, lsl #16 // wINST<- AAAAaaaa - b MterpCommonTakenBranchNoFlags diff --git a/runtime/interpreter/mterp/arm64/op_if_eq.S b/runtime/interpreter/mterp/arm64/op_if_eq.S deleted file mode 100644 index aa4a0f16a73628b6c0af071a5ad9e0ed824f804d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_if_eq.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/bincmp.S" { "condition":"eq" } diff --git a/runtime/interpreter/mterp/arm64/op_if_eqz.S b/runtime/interpreter/mterp/arm64/op_if_eqz.S deleted file mode 100644 index 47c1dee8cfdff1765fcac9dbdcd736c54ed545ca..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_if_eqz.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/zcmp.S" { "compare":"0", "branch":"cbz w2," } diff --git a/runtime/interpreter/mterp/arm64/op_if_ge.S b/runtime/interpreter/mterp/arm64/op_if_ge.S deleted file mode 100644 index d6ec761bfe9ee3e2b521dae593af5a08826e0fcf..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_if_ge.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/bincmp.S" { "condition":"ge" } diff --git a/runtime/interpreter/mterp/arm64/op_if_gez.S b/runtime/interpreter/mterp/arm64/op_if_gez.S deleted file mode 100644 index 087e094a7632c10294a342c67c379cbbcddbe358..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_if_gez.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/zcmp.S" { "compare":"0", "branch":"tbz w2, #31," } diff --git a/runtime/interpreter/mterp/arm64/op_if_gt.S b/runtime/interpreter/mterp/arm64/op_if_gt.S deleted file mode 100644 index 7db8e9d911c6f1e9c1fd5b10ef4aff405537b2bf..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_if_gt.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/bincmp.S" { "condition":"gt" } diff --git a/runtime/interpreter/mterp/arm64/op_if_gtz.S b/runtime/interpreter/mterp/arm64/op_if_gtz.S deleted file mode 100644 index 476b26543144ffe0e8389a4600b9e13cec2a4377..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_if_gtz.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/zcmp.S" { "branch":"b.gt" } diff --git a/runtime/interpreter/mterp/arm64/op_if_le.S b/runtime/interpreter/mterp/arm64/op_if_le.S deleted file mode 100644 index ca3a83fff7697b04ec94b7429992c99e70b3636e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_if_le.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/bincmp.S" { "condition":"le" } diff --git a/runtime/interpreter/mterp/arm64/op_if_lez.S b/runtime/interpreter/mterp/arm64/op_if_lez.S deleted file mode 100644 index 2717a60ebfa59cb8e298d67134675e4ad194eae8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_if_lez.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/zcmp.S" { "branch":"b.le" } diff --git a/runtime/interpreter/mterp/arm64/op_if_lt.S b/runtime/interpreter/mterp/arm64/op_if_lt.S deleted file mode 100644 index 56450a15ca7a9607a9848722820ac68953e80ae1..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_if_lt.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/bincmp.S" { "condition":"lt" } diff --git a/runtime/interpreter/mterp/arm64/op_if_ltz.S b/runtime/interpreter/mterp/arm64/op_if_ltz.S deleted file mode 100644 index 86089c10ba10f5266d0feb05e87b0adbf9262e9d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_if_ltz.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/zcmp.S" { "compare":"0", "branch":"tbnz w2, #31," } diff --git a/runtime/interpreter/mterp/arm64/op_if_ne.S b/runtime/interpreter/mterp/arm64/op_if_ne.S deleted file mode 100644 index 14d9e13dcf4534a50d9f398b8d708234b23225b4..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_if_ne.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/bincmp.S" { "condition":"ne" } diff --git a/runtime/interpreter/mterp/arm64/op_if_nez.S b/runtime/interpreter/mterp/arm64/op_if_nez.S deleted file mode 100644 index efacc88806de959d0280e0864ff09282c73fbe4a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_if_nez.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/zcmp.S" { "compare":"0", "branch":"cbnz w2," } diff --git a/runtime/interpreter/mterp/arm64/op_iget.S b/runtime/interpreter/mterp/arm64/op_iget.S deleted file mode 100644 index 48b9cad44bd039138c5040232dba399814afacbb..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_iget.S +++ /dev/null @@ -1,2 +0,0 @@ -%default { "is_object":"0", "helper":"MterpIGetU32"} -%include "arm64/field.S" { } diff --git a/runtime/interpreter/mterp/arm64/op_iget_boolean.S b/runtime/interpreter/mterp/arm64/op_iget_boolean.S deleted file mode 100644 index 9a83b2a596e63d58bd31e5a8b2c69978ea22d070..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_iget_boolean.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_iget.S" { "helper":"MterpIGetU8" } diff --git a/runtime/interpreter/mterp/arm64/op_iget_boolean_quick.S b/runtime/interpreter/mterp/arm64/op_iget_boolean_quick.S deleted file mode 100644 index 2ceccb9ef0b9cf2cbd7d0355bcaf872fb1a8e4ee..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_iget_boolean_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_iget_quick.S" { "load":"ldrb" } diff --git a/runtime/interpreter/mterp/arm64/op_iget_byte.S b/runtime/interpreter/mterp/arm64/op_iget_byte.S deleted file mode 100644 index f73e634621bed16174ee7a2e67f15d82b8a61c52..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_iget_byte.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_iget.S" { "helper":"MterpIGetI8" } diff --git a/runtime/interpreter/mterp/arm64/op_iget_byte_quick.S b/runtime/interpreter/mterp/arm64/op_iget_byte_quick.S deleted file mode 100644 index 6e97b721839121a404bd95201eb81c5d0b2a09f9..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_iget_byte_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_iget_quick.S" { "load":"ldrsb" } diff --git a/runtime/interpreter/mterp/arm64/op_iget_char.S b/runtime/interpreter/mterp/arm64/op_iget_char.S deleted file mode 100644 index a5efd9e3ed27ec0fb7a0c12b7d988ce5a6bc6c9b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_iget_char.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_iget.S" { "helper":"MterpIGetU16" } diff --git a/runtime/interpreter/mterp/arm64/op_iget_char_quick.S b/runtime/interpreter/mterp/arm64/op_iget_char_quick.S deleted file mode 100644 index 325dd1cf9e5b05aecf0718ac368617dafb987b93..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_iget_char_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_iget_quick.S" { "load":"ldrh" } diff --git a/runtime/interpreter/mterp/arm64/op_iget_object.S b/runtime/interpreter/mterp/arm64/op_iget_object.S deleted file mode 100644 index 40ddadd97111ce1d542dc18fb3bf0861d08c708f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_iget_object.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_iget.S" { "is_object":"1", "helper":"MterpIGetObj" } diff --git a/runtime/interpreter/mterp/arm64/op_iget_object_quick.S b/runtime/interpreter/mterp/arm64/op_iget_object_quick.S deleted file mode 100644 index e9a797dfe18abd6769ab0fa875973f1bc31571d2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_iget_object_quick.S +++ /dev/null @@ -1,15 +0,0 @@ - /* For: iget-object-quick */ - /* op vA, vB, offset//CCCC */ - lsr w2, wINST, #12 // w2<- B - FETCH w1, 1 // w1<- field byte offset - EXPORT_PC - GET_VREG w0, w2 // w0<- object we're operating on - bl artIGetObjectFromMterp // (obj, offset) - ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] - ubfx w2, wINST, #8, #4 // w2<- A - PREFETCH_INST 2 - cbnz w3, MterpPossibleException // bail out - SET_VREG_OBJECT w0, w2 // fp[A]<- w0 - ADVANCE 2 // advance rPC - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_iget_quick.S b/runtime/interpreter/mterp/arm64/op_iget_quick.S deleted file mode 100644 index 699b2c42293ed3f04a152d37fd270c4844558f9e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_iget_quick.S +++ /dev/null @@ -1,14 +0,0 @@ -%default { "load":"ldr", "extend":"" } - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset//CCCC */ - lsr w2, wINST, #12 // w2<- B - FETCH w1, 1 // w1<- field byte offset - GET_VREG w3, w2 // w3<- object we're operating on - ubfx w2, wINST, #8, #4 // w2<- A - cbz w3, common_errNullObject // object was null - $load w0, [x3, x1] // w0<- obj.field - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - $extend - SET_VREG w0, w2 // fp[A]<- w0 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_iget_short.S b/runtime/interpreter/mterp/arm64/op_iget_short.S deleted file mode 100644 index bb81c1708eea2b1f75289a116925887c15122232..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_iget_short.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_iget.S" { "helper":"MterpIGetI16" } diff --git a/runtime/interpreter/mterp/arm64/op_iget_short_quick.S b/runtime/interpreter/mterp/arm64/op_iget_short_quick.S deleted file mode 100644 index 83670701c1000d8912e73ec141803ea249f706e9..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_iget_short_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_iget_quick.S" { "load":"ldrsh" } diff --git a/runtime/interpreter/mterp/arm64/op_iget_wide.S b/runtime/interpreter/mterp/arm64/op_iget_wide.S deleted file mode 100644 index 70061d65771fcabe99f7d5097a872db38ac4c549..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_iget_wide.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_iget.S" { "helper":"MterpIGetU64" } diff --git a/runtime/interpreter/mterp/arm64/op_iget_wide_quick.S b/runtime/interpreter/mterp/arm64/op_iget_wide_quick.S deleted file mode 100644 index e9388e477db41de5375decdda7240641b84342ff..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_iget_wide_quick.S +++ /dev/null @@ -1,11 +0,0 @@ - /* iget-wide-quick vA, vB, offset//CCCC */ - lsr w2, wINST, #12 // w2<- B - FETCH w4, 1 // w4<- field byte offset - GET_VREG w3, w2 // w3<- object we're operating on - ubfx w2, wINST, #8, #4 // w2<- A - cbz w3, common_errNullObject // object was null - ldr x0, [x3, x4] // x0<- obj.field - FETCH_ADVANCE_INST 2 // advance rPC, load wINST - SET_VREG_WIDE x0, w2 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_instance_of.S b/runtime/interpreter/mterp/arm64/op_instance_of.S deleted file mode 100644 index a56705a68b37ba33e237e5c0cde8596878254240..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_instance_of.S +++ /dev/null @@ -1,22 +0,0 @@ - /* - * Check to see if an object reference is an instance of a class. - * - * Most common situation is a non-null object, being compared against - * an already-resolved class. - */ - /* instance-of vA, vB, class//CCCC */ - EXPORT_PC - FETCH w0, 1 // w0<- CCCC - lsr w1, wINST, #12 // w1<- B - VREG_INDEX_TO_ADDR x1, w1 // w1<- &object - ldr x2, [xFP, #OFF_FP_METHOD] // w2<- method - mov x3, xSELF // w3<- self - bl MterpInstanceOf // (index, &obj, method, self) - ldr x1, [xSELF, #THREAD_EXCEPTION_OFFSET] - ubfx w2, wINST, #8, #4 // w2<- A - PREFETCH_INST 2 - cbnz x1, MterpException - ADVANCE 2 // advance rPC - SET_VREG w0, w2 // vA<- w0 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_int_to_byte.S b/runtime/interpreter/mterp/arm64/op_int_to_byte.S deleted file mode 100644 index 43f814820a4d7d9daa6eedef804e5ccff41f5de8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_int_to_byte.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/unop.S" {"instr":"sxtb w0, w0"} diff --git a/runtime/interpreter/mterp/arm64/op_int_to_char.S b/runtime/interpreter/mterp/arm64/op_int_to_char.S deleted file mode 100644 index f092170681ac6394b9e6cfdeb4bf73add48d65e9..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_int_to_char.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/unop.S" {"instr":"uxth w0, w0"} diff --git a/runtime/interpreter/mterp/arm64/op_int_to_double.S b/runtime/interpreter/mterp/arm64/op_int_to_double.S deleted file mode 100644 index 3dee75a1416d8ca83548e34f3104da6f3a25eea5..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_int_to_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/funopWider.S" {"instr":"scvtf d0, w0", "srcreg":"w0", "tgtreg":"d0"} diff --git a/runtime/interpreter/mterp/arm64/op_int_to_float.S b/runtime/interpreter/mterp/arm64/op_int_to_float.S deleted file mode 100644 index 3ebbdc7cb9b76657135f3e0f7c2e81975db80cb6..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_int_to_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/funopNarrow.S" {"instr":"scvtf s0, w0", "srcreg":"w0", "tgtreg":"s0"} diff --git a/runtime/interpreter/mterp/arm64/op_int_to_long.S b/runtime/interpreter/mterp/arm64/op_int_to_long.S deleted file mode 100644 index 45e31124ff3d55c5a0a829b14e71fe3cb7a625f2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_int_to_long.S +++ /dev/null @@ -1,8 +0,0 @@ - /* int-to-long vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w4, wINST, #8, #4 // w4<- A - GET_VREG_S x0, w3 // x0<- sign_extend(fp[B]) - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG_WIDE x0, w4 // fp[A]<- x0 - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_int_to_short.S b/runtime/interpreter/mterp/arm64/op_int_to_short.S deleted file mode 100644 index 87fb8046682eef0caa126c7455d1fe5f6e938f29..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_int_to_short.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/unop.S" {"instr":"sxth w0, w0"} diff --git a/runtime/interpreter/mterp/arm64/op_invoke_custom.S b/runtime/interpreter/mterp/arm64/op_invoke_custom.S deleted file mode 100644 index 3686584950ccb68f245fb94125efda68cb95ee3e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_invoke_custom.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/invoke.S" { "helper":"MterpInvokeCustom" } diff --git a/runtime/interpreter/mterp/arm64/op_invoke_custom_range.S b/runtime/interpreter/mterp/arm64/op_invoke_custom_range.S deleted file mode 100644 index 06de86a6a06e5752bcafad172385d332746e884f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_invoke_custom_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/invoke.S" { "helper":"MterpInvokeCustomRange" } diff --git a/runtime/interpreter/mterp/arm64/op_invoke_direct.S b/runtime/interpreter/mterp/arm64/op_invoke_direct.S deleted file mode 100644 index c117232d9cad68f98a8c9466616a43260b523840..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_invoke_direct.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/invoke.S" { "helper":"MterpInvokeDirect" } diff --git a/runtime/interpreter/mterp/arm64/op_invoke_direct_range.S b/runtime/interpreter/mterp/arm64/op_invoke_direct_range.S deleted file mode 100644 index efc54c71d92572c8b94dd2060168938cf331eb68..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_invoke_direct_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/invoke.S" { "helper":"MterpInvokeDirectRange" } diff --git a/runtime/interpreter/mterp/arm64/op_invoke_interface.S b/runtime/interpreter/mterp/arm64/op_invoke_interface.S deleted file mode 100644 index 12dfa592d50190086ae10aab4deda8cdf94f163f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_invoke_interface.S +++ /dev/null @@ -1,8 +0,0 @@ -%include "arm64/invoke.S" { "helper":"MterpInvokeInterface" } - /* - * Handle an interface method call. - * - * for: invoke-interface, invoke-interface/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ diff --git a/runtime/interpreter/mterp/arm64/op_invoke_interface_range.S b/runtime/interpreter/mterp/arm64/op_invoke_interface_range.S deleted file mode 100644 index 61caaf47e38be8e0f7bacb1fc2814f18e488a79e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_invoke_interface_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/invoke.S" { "helper":"MterpInvokeInterfaceRange" } diff --git a/runtime/interpreter/mterp/arm64/op_invoke_polymorphic.S b/runtime/interpreter/mterp/arm64/op_invoke_polymorphic.S deleted file mode 100644 index aace98f1a203b073df911487c35f38331f805541..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_invoke_polymorphic.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/invoke_polymorphic.S" { "helper":"MterpInvokePolymorphic" } diff --git a/runtime/interpreter/mterp/arm64/op_invoke_polymorphic_range.S b/runtime/interpreter/mterp/arm64/op_invoke_polymorphic_range.S deleted file mode 100644 index 30c8c09cce199f8ff6b9c405763dac5cf54866be..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_invoke_polymorphic_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/invoke_polymorphic.S" { "helper":"MterpInvokePolymorphicRange" } diff --git a/runtime/interpreter/mterp/arm64/op_invoke_static.S b/runtime/interpreter/mterp/arm64/op_invoke_static.S deleted file mode 100644 index 634eda2736e829f10a39b0159831ba375092cd2b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_invoke_static.S +++ /dev/null @@ -1,2 +0,0 @@ -%include "arm64/invoke.S" { "helper":"MterpInvokeStatic" } - diff --git a/runtime/interpreter/mterp/arm64/op_invoke_static_range.S b/runtime/interpreter/mterp/arm64/op_invoke_static_range.S deleted file mode 100644 index 32cdcddaa489c8df8cb9b79600a508f92921b485..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_invoke_static_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/invoke.S" { "helper":"MterpInvokeStaticRange" } diff --git a/runtime/interpreter/mterp/arm64/op_invoke_super.S b/runtime/interpreter/mterp/arm64/op_invoke_super.S deleted file mode 100644 index def2c552fd0301289631b09008afd97be66702e3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_invoke_super.S +++ /dev/null @@ -1,8 +0,0 @@ -%include "arm64/invoke.S" { "helper":"MterpInvokeSuper" } - /* - * Handle a "super" method call. - * - * for: invoke-super, invoke-super/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ diff --git a/runtime/interpreter/mterp/arm64/op_invoke_super_range.S b/runtime/interpreter/mterp/arm64/op_invoke_super_range.S deleted file mode 100644 index 27fb8591a4c42650d13c16880d73b537a14a407a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_invoke_super_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/invoke.S" { "helper":"MterpInvokeSuperRange" } diff --git a/runtime/interpreter/mterp/arm64/op_invoke_virtual.S b/runtime/interpreter/mterp/arm64/op_invoke_virtual.S deleted file mode 100644 index 66d050217d5d3d5426129bd443a92cef46300e5c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_invoke_virtual.S +++ /dev/null @@ -1,8 +0,0 @@ -%include "arm64/invoke.S" { "helper":"MterpInvokeVirtual" } - /* - * Handle a virtual method call. - * - * for: invoke-virtual, invoke-virtual/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ diff --git a/runtime/interpreter/mterp/arm64/op_invoke_virtual_quick.S b/runtime/interpreter/mterp/arm64/op_invoke_virtual_quick.S deleted file mode 100644 index 4300c34646d82694b5eabd35dc3629a67146f0c6..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_invoke_virtual_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/invoke.S" { "helper":"MterpInvokeVirtualQuick" } diff --git a/runtime/interpreter/mterp/arm64/op_invoke_virtual_range.S b/runtime/interpreter/mterp/arm64/op_invoke_virtual_range.S deleted file mode 100644 index b43955c6d8f891ecab153dbbe715779959b34800..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_invoke_virtual_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/invoke.S" { "helper":"MterpInvokeVirtualRange" } diff --git a/runtime/interpreter/mterp/arm64/op_invoke_virtual_range_quick.S b/runtime/interpreter/mterp/arm64/op_invoke_virtual_range_quick.S deleted file mode 100644 index 90c7b657471fb23013dc215259a0a2c5c0cde741..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_invoke_virtual_range_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/invoke.S" { "helper":"MterpInvokeVirtualQuickRange" } diff --git a/runtime/interpreter/mterp/arm64/op_iput.S b/runtime/interpreter/mterp/arm64/op_iput.S deleted file mode 100644 index 2bc3db9050ca996ce8a756567ee0d5fb5e83605a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_iput.S +++ /dev/null @@ -1,2 +0,0 @@ -%default { "is_object":"0", "helper":"MterpIPutU32" } -%include "arm64/field.S" { } diff --git a/runtime/interpreter/mterp/arm64/op_iput_boolean.S b/runtime/interpreter/mterp/arm64/op_iput_boolean.S deleted file mode 100644 index 12a278ccba3e112b2c2363bda6a9a94d85a0922b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_iput_boolean.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_iput.S" { "helper":"MterpIPutU8" } diff --git a/runtime/interpreter/mterp/arm64/op_iput_boolean_quick.S b/runtime/interpreter/mterp/arm64/op_iput_boolean_quick.S deleted file mode 100644 index 25c61d7c2e118e278e2189ff1cce6a66e518d584..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_iput_boolean_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_iput_quick.S" { "store":"strb" } diff --git a/runtime/interpreter/mterp/arm64/op_iput_byte.S b/runtime/interpreter/mterp/arm64/op_iput_byte.S deleted file mode 100644 index 82b99e976547c25d3ad2900260927c19c3bf4efb..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_iput_byte.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_iput.S" { "helper":"MterpIPutI8" } diff --git a/runtime/interpreter/mterp/arm64/op_iput_byte_quick.S b/runtime/interpreter/mterp/arm64/op_iput_byte_quick.S deleted file mode 100644 index 25c61d7c2e118e278e2189ff1cce6a66e518d584..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_iput_byte_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_iput_quick.S" { "store":"strb" } diff --git a/runtime/interpreter/mterp/arm64/op_iput_char.S b/runtime/interpreter/mterp/arm64/op_iput_char.S deleted file mode 100644 index 427d92d9c0e51076a1a030f0b0df0c22e904ff1a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_iput_char.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_iput.S" { "helper":"MterpIPutU16" } diff --git a/runtime/interpreter/mterp/arm64/op_iput_char_quick.S b/runtime/interpreter/mterp/arm64/op_iput_char_quick.S deleted file mode 100644 index c6ef46ab87a95b617c0c57211c1ae90ada5d7bd6..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_iput_char_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_iput_quick.S" { "store":"strh" } diff --git a/runtime/interpreter/mterp/arm64/op_iput_object.S b/runtime/interpreter/mterp/arm64/op_iput_object.S deleted file mode 100644 index e9bb93f0a5e59894919afadff4006b419798b194..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_iput_object.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_iput.S" { "is_object":"1", "helper":"MterpIPutObj" } diff --git a/runtime/interpreter/mterp/arm64/op_iput_object_quick.S b/runtime/interpreter/mterp/arm64/op_iput_object_quick.S deleted file mode 100644 index 6fbf2b1da311d16b84f5d6af9186a69ece98d563..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_iput_object_quick.S +++ /dev/null @@ -1,9 +0,0 @@ - EXPORT_PC - add x0, xFP, #OFF_FP_SHADOWFRAME - mov x1, xPC - mov w2, wINST - bl MterpIputObjectQuick - cbz w0, MterpException - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_iput_quick.S b/runtime/interpreter/mterp/arm64/op_iput_quick.S deleted file mode 100644 index e95da76283ff90ef216819bd1b0d396506a8d0dc..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_iput_quick.S +++ /dev/null @@ -1,13 +0,0 @@ -%default { "store":"str" } - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset//CCCC */ - lsr w2, wINST, #12 // w2<- B - FETCH w1, 1 // w1<- field byte offset - GET_VREG w3, w2 // w3<- fp[B], the object pointer - ubfx w2, wINST, #8, #4 // w2<- A - cbz w3, common_errNullObject // object was null - GET_VREG w0, w2 // w0<- fp[A] - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - $store w0, [x3, x1] // obj.field<- w0 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_iput_short.S b/runtime/interpreter/mterp/arm64/op_iput_short.S deleted file mode 100644 index 67f1ace8bf569840fe7169f592b78a9e980acd74..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_iput_short.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_iput.S" { "helper":"MterpIPutI16" } diff --git a/runtime/interpreter/mterp/arm64/op_iput_short_quick.S b/runtime/interpreter/mterp/arm64/op_iput_short_quick.S deleted file mode 100644 index c6ef46ab87a95b617c0c57211c1ae90ada5d7bd6..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_iput_short_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_iput_quick.S" { "store":"strh" } diff --git a/runtime/interpreter/mterp/arm64/op_iput_wide.S b/runtime/interpreter/mterp/arm64/op_iput_wide.S deleted file mode 100644 index e1fafad5a7257771ca250f1eec35ec241d1cc452..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_iput_wide.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_iput.S" { "helper":"MterpIPutU64" } diff --git a/runtime/interpreter/mterp/arm64/op_iput_wide_quick.S b/runtime/interpreter/mterp/arm64/op_iput_wide_quick.S deleted file mode 100644 index 28e831a5f8f438419a41f1abc6a79df7a84b6867..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_iput_wide_quick.S +++ /dev/null @@ -1,11 +0,0 @@ - /* iput-wide-quick vA, vB, offset//CCCC */ - lsr w2, wINST, #12 // w2<- B - FETCH w3, 1 // w3<- field byte offset - GET_VREG w2, w2 // w2<- fp[B], the object pointer - ubfx w0, wINST, #8, #4 // w0<- A - cbz w2, common_errNullObject // object was null - GET_VREG_WIDE x0, w0 // x0<- fp[A] - FETCH_ADVANCE_INST 2 // advance rPC, load wINST - str x0, [x2, x3] // obj.field<- x0 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_long_to_double.S b/runtime/interpreter/mterp/arm64/op_long_to_double.S deleted file mode 100644 index a3f59c2048b2d2a30ec6f779b422c2481ebd8725..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_long_to_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/funopWide.S" {"instr":"scvtf d0, x0", "srcreg":"x0", "tgtreg":"d0"} diff --git a/runtime/interpreter/mterp/arm64/op_long_to_float.S b/runtime/interpreter/mterp/arm64/op_long_to_float.S deleted file mode 100644 index e9c9145cee25ba5fb6276f8ad4440923cd065d8a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_long_to_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/funopNarrower.S" {"instr":"scvtf s0, x0", "srcreg":"x0", "tgtreg":"s0"} diff --git a/runtime/interpreter/mterp/arm64/op_long_to_int.S b/runtime/interpreter/mterp/arm64/op_long_to_int.S deleted file mode 100644 index 73f58d896740e4f6e4c25ae97ab70292a3f51e37..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_long_to_int.S +++ /dev/null @@ -1,2 +0,0 @@ -/* we ignore the high word, making this equivalent to a 32-bit reg move */ -%include "arm64/op_move.S" diff --git a/runtime/interpreter/mterp/arm64/op_monitor_enter.S b/runtime/interpreter/mterp/arm64/op_monitor_enter.S deleted file mode 100644 index 6fbd9ae725bd681cab619d12a30d4b3cb62c2da7..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_monitor_enter.S +++ /dev/null @@ -1,13 +0,0 @@ - /* - * Synchronize on an object. - */ - /* monitor-enter vAA */ - EXPORT_PC - lsr w2, wINST, #8 // w2<- AA - GET_VREG w0, w2 // w0<- vAA (object) - mov x1, xSELF // w1<- self - bl artLockObjectFromCode - cbnz w0, MterpException - FETCH_ADVANCE_INST 1 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_monitor_exit.S b/runtime/interpreter/mterp/arm64/op_monitor_exit.S deleted file mode 100644 index 26e2d8d7b124c3639fe7eac0eb8b665eb14b9282..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_monitor_exit.S +++ /dev/null @@ -1,17 +0,0 @@ - /* - * Unlock an object. - * - * Exceptions that occur when unlocking a monitor need to appear as - * if they happened at the following instruction. See the Dalvik - * instruction spec. - */ - /* monitor-exit vAA */ - EXPORT_PC - lsr w2, wINST, #8 // w2<- AA - GET_VREG w0, w2 // w0<- vAA (object) - mov x1, xSELF // w0<- self - bl artUnlockObjectFromCode // w0<- success for unlock(self, obj) - cbnz w0, MterpException - FETCH_ADVANCE_INST 1 // before throw: advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_move.S b/runtime/interpreter/mterp/arm64/op_move.S deleted file mode 100644 index 195b7eb62d9f05fb9c221b4dae5175e1758c28e4..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_move.S +++ /dev/null @@ -1,14 +0,0 @@ -%default { "is_object":"0" } - /* for move, move-object, long-to-int */ - /* op vA, vB */ - lsr w1, wINST, #12 // x1<- B from 15:12 - ubfx w0, wINST, #8, #4 // x0<- A from 11:8 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - GET_VREG w2, w1 // x2<- fp[B] - GET_INST_OPCODE ip // ip<- opcode from wINST - .if $is_object - SET_VREG_OBJECT w2, w0 // fp[A]<- x2 - .else - SET_VREG w2, w0 // fp[A]<- x2 - .endif - GOTO_OPCODE ip // execute next instruction diff --git a/runtime/interpreter/mterp/arm64/op_move_16.S b/runtime/interpreter/mterp/arm64/op_move_16.S deleted file mode 100644 index 5146e3d6e701e17eaef666356c4e79f810e4f0f3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_move_16.S +++ /dev/null @@ -1,14 +0,0 @@ -%default { "is_object":"0" } - /* for: move/16, move-object/16 */ - /* op vAAAA, vBBBB */ - FETCH w1, 2 // w1<- BBBB - FETCH w0, 1 // w0<- AAAA - FETCH_ADVANCE_INST 3 // advance xPC, load xINST - GET_VREG w2, w1 // w2<- fp[BBBB] - GET_INST_OPCODE ip // extract opcode from xINST - .if $is_object - SET_VREG_OBJECT w2, w0 // fp[AAAA]<- w2 - .else - SET_VREG w2, w0 // fp[AAAA]<- w2 - .endif - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_move_exception.S b/runtime/interpreter/mterp/arm64/op_move_exception.S deleted file mode 100644 index b29298fd1498e0b50f6b8cf504fb1f84b16598d6..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_move_exception.S +++ /dev/null @@ -1,9 +0,0 @@ - /* move-exception vAA */ - lsr w2, wINST, #8 // w2<- AA - ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] - mov x1, #0 // w1<- 0 - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - SET_VREG_OBJECT w3, w2 // fp[AA]<- exception obj - GET_INST_OPCODE ip // extract opcode from rINST - str x1, [xSELF, #THREAD_EXCEPTION_OFFSET] // clear exception - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_move_from16.S b/runtime/interpreter/mterp/arm64/op_move_from16.S deleted file mode 100644 index 78f344db6ba17a0d566d11fea28dcef837189b2f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_move_from16.S +++ /dev/null @@ -1,14 +0,0 @@ -%default { "is_object":"0" } - /* for: move/from16, move-object/from16 */ - /* op vAA, vBBBB */ - FETCH w1, 1 // r1<- BBBB - lsr w0, wINST, #8 // r0<- AA - FETCH_ADVANCE_INST 2 // advance rPC, load wINST - GET_VREG w2, w1 // r2<- fp[BBBB] - GET_INST_OPCODE ip // extract opcode from wINST - .if $is_object - SET_VREG_OBJECT w2, w0 // fp[AA]<- r2 - .else - SET_VREG w2, w0 // fp[AA]<- r2 - .endif - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_move_object.S b/runtime/interpreter/mterp/arm64/op_move_object.S deleted file mode 100644 index a5adc59e81d2b89c8ec29c8f57d4d71a8ad40670..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_move_object.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_move.S" {"is_object":"1"} diff --git a/runtime/interpreter/mterp/arm64/op_move_object_16.S b/runtime/interpreter/mterp/arm64/op_move_object_16.S deleted file mode 100644 index ef86c4508b40b1d86d5f463dad2c34a182388f89..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_move_object_16.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_move_16.S" {"is_object":"1"} diff --git a/runtime/interpreter/mterp/arm64/op_move_object_from16.S b/runtime/interpreter/mterp/arm64/op_move_object_from16.S deleted file mode 100644 index 0c73b3b045d0d2de31f69a025cadfab6702cd3ba..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_move_object_from16.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_move_from16.S" {"is_object":"1"} diff --git a/runtime/interpreter/mterp/arm64/op_move_result.S b/runtime/interpreter/mterp/arm64/op_move_result.S deleted file mode 100644 index 06fe96269b6f9d3a4ae38626f05954cb2eb6670f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_move_result.S +++ /dev/null @@ -1,14 +0,0 @@ -%default { "is_object":"0" } - /* for: move-result, move-result-object */ - /* op vAA */ - lsr w2, wINST, #8 // r2<- AA - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - ldr x0, [xFP, #OFF_FP_RESULT_REGISTER] // get pointer to result JType. - ldr w0, [x0] // r0 <- result.i. - GET_INST_OPCODE ip // extract opcode from wINST - .if $is_object - SET_VREG_OBJECT w0, w2, w1 // fp[AA]<- r0 - .else - SET_VREG w0, w2 // fp[AA]<- r0 - .endif - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_move_result_object.S b/runtime/interpreter/mterp/arm64/op_move_result_object.S deleted file mode 100644 index da2bbee665282b088061c78f04a327bf15a093e0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_move_result_object.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_move_result.S" {"is_object":"1"} diff --git a/runtime/interpreter/mterp/arm64/op_move_result_wide.S b/runtime/interpreter/mterp/arm64/op_move_result_wide.S deleted file mode 100644 index f90a33f01f26a5c530ed0c4a87d9d4d182db5d8d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_move_result_wide.S +++ /dev/null @@ -1,9 +0,0 @@ - /* for: move-result-wide */ - /* op vAA */ - lsr w2, wINST, #8 // r2<- AA - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - ldr x0, [xFP, #OFF_FP_RESULT_REGISTER] // get pointer to result JType. - ldr x0, [x0] // r0 <- result.i. - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG_WIDE x0, x2 // fp[AA]<- r0 - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_move_wide.S b/runtime/interpreter/mterp/arm64/op_move_wide.S deleted file mode 100644 index 538f0797366ba844ea02884995937c0bf94d957a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_move_wide.S +++ /dev/null @@ -1,9 +0,0 @@ - /* move-wide vA, vB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - lsr w3, wINST, #12 // w3<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG_WIDE x3, w3 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG_WIDE x3, w2 - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_move_wide_16.S b/runtime/interpreter/mterp/arm64/op_move_wide_16.S deleted file mode 100644 index c79cdc50073f6e8ff51f1bd48ac405a06e0af431..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_move_wide_16.S +++ /dev/null @@ -1,9 +0,0 @@ - /* move-wide/16 vAAAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - FETCH w3, 2 // w3<- BBBB - FETCH w2, 1 // w2<- AAAA - GET_VREG_WIDE x3, w3 - FETCH_ADVANCE_INST 3 // advance rPC, load rINST - SET_VREG_WIDE x3, w2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_move_wide_from16.S b/runtime/interpreter/mterp/arm64/op_move_wide_from16.S deleted file mode 100644 index 70dbe99039353ac3bf3cfbb09e5174d6a93bfa79..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_move_wide_from16.S +++ /dev/null @@ -1,9 +0,0 @@ - /* move-wide/from16 vAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - FETCH w3, 1 // w3<- BBBB - lsr w2, wINST, #8 // w2<- AA - GET_VREG_WIDE x3, w3 - FETCH_ADVANCE_INST 2 // advance rPC, load wINST - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG_WIDE x3, w2 - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_mul_double.S b/runtime/interpreter/mterp/arm64/op_mul_double.S deleted file mode 100644 index 8d35b81b12940518549824ea0d2c8a0197db2eaf..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_mul_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binopWide.S" {"instr":"fmul d0, d1, d2", "result":"d0", "r1":"d1", "r2":"d2"} diff --git a/runtime/interpreter/mterp/arm64/op_mul_double_2addr.S b/runtime/interpreter/mterp/arm64/op_mul_double_2addr.S deleted file mode 100644 index 526cb3bccc23214eca30fd6c8c4b01f4b0170943..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_mul_double_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binopWide2addr.S" {"instr":"fmul d0, d0, d1", "r0":"d0", "r1":"d1"} diff --git a/runtime/interpreter/mterp/arm64/op_mul_float.S b/runtime/interpreter/mterp/arm64/op_mul_float.S deleted file mode 100644 index eea7733dbfce283182aeb1d64f4ae116f9a6a946..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_mul_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/fbinop.S" {"instr":"fmul s0, s0, s1"} diff --git a/runtime/interpreter/mterp/arm64/op_mul_float_2addr.S b/runtime/interpreter/mterp/arm64/op_mul_float_2addr.S deleted file mode 100644 index c1f23765aa70df1c21f0c0ce39c3607c412fef6e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_mul_float_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/fbinop2addr.S" {"instr":"fmul s2, s0, s1"} diff --git a/runtime/interpreter/mterp/arm64/op_mul_int.S b/runtime/interpreter/mterp/arm64/op_mul_int.S deleted file mode 100644 index d14cae12e42198483e0f2a405f3046e113c56916..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_mul_int.S +++ /dev/null @@ -1,2 +0,0 @@ -/* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */ -%include "arm64/binop.S" {"instr":"mul w0, w1, w0"} diff --git a/runtime/interpreter/mterp/arm64/op_mul_int_2addr.S b/runtime/interpreter/mterp/arm64/op_mul_int_2addr.S deleted file mode 100644 index f079118172239b0ff2b42671eca4ea7b6b479582..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_mul_int_2addr.S +++ /dev/null @@ -1,2 +0,0 @@ -/* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */ -%include "arm64/binop2addr.S" {"instr":"mul w0, w1, w0"} diff --git a/runtime/interpreter/mterp/arm64/op_mul_int_lit16.S b/runtime/interpreter/mterp/arm64/op_mul_int_lit16.S deleted file mode 100644 index a3785595415f3bea6b5c948b7cea36672aa37d79..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_mul_int_lit16.S +++ /dev/null @@ -1,2 +0,0 @@ -/* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */ -%include "arm64/binopLit16.S" {"instr":"mul w0, w1, w0"} diff --git a/runtime/interpreter/mterp/arm64/op_mul_int_lit8.S b/runtime/interpreter/mterp/arm64/op_mul_int_lit8.S deleted file mode 100644 index b3d40141ae0523e6c353289abde1838498e82ffe..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_mul_int_lit8.S +++ /dev/null @@ -1,2 +0,0 @@ -/* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */ -%include "arm64/binopLit8.S" {"instr":"mul w0, w1, w0"} diff --git a/runtime/interpreter/mterp/arm64/op_mul_long.S b/runtime/interpreter/mterp/arm64/op_mul_long.S deleted file mode 100644 index bc0dcbd14b72011210518befe46841d4cdbea9c4..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_mul_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binopWide.S" {"instr":"mul x0, x1, x2"} diff --git a/runtime/interpreter/mterp/arm64/op_mul_long_2addr.S b/runtime/interpreter/mterp/arm64/op_mul_long_2addr.S deleted file mode 100644 index fa1cdf8a7233edd9d003080ea4bafa6268473813..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_mul_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binopWide2addr.S" {"instr":"mul x0, x0, x1"} diff --git a/runtime/interpreter/mterp/arm64/op_neg_double.S b/runtime/interpreter/mterp/arm64/op_neg_double.S deleted file mode 100644 index d77859d5701f4965b8b2e2afe32da8845d57a10e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_neg_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/unopWide.S" {"instr":"eor x0, x0, #0x8000000000000000"} diff --git a/runtime/interpreter/mterp/arm64/op_neg_float.S b/runtime/interpreter/mterp/arm64/op_neg_float.S deleted file mode 100644 index 6652aec0ffe08845ccfb6bd82816c71a24967720..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_neg_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/unop.S" {"instr":"eor w0, w0, #0x80000000"} diff --git a/runtime/interpreter/mterp/arm64/op_neg_int.S b/runtime/interpreter/mterp/arm64/op_neg_int.S deleted file mode 100644 index 59c14a9087aad4e21e42a916bfe6c1ca2cff6bb0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_neg_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/unop.S" {"instr":"sub w0, wzr, w0"} diff --git a/runtime/interpreter/mterp/arm64/op_neg_long.S b/runtime/interpreter/mterp/arm64/op_neg_long.S deleted file mode 100644 index 0c71ea7de65e958c4a9cc6dfdc4dc401b37a97a3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_neg_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/unopWide.S" {"instr":"sub x0, xzr, x0"} diff --git a/runtime/interpreter/mterp/arm64/op_new_array.S b/runtime/interpreter/mterp/arm64/op_new_array.S deleted file mode 100644 index 886120a94ebb98fd4a853ea5e090b4e7effcd1e8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_new_array.S +++ /dev/null @@ -1,18 +0,0 @@ - /* - * Allocate an array of objects, specified with the array class - * and a count. - * - * The verifier guarantees that this is an array class, so we don't - * check for it here. - */ - /* new-array vA, vB, class//CCCC */ - EXPORT_PC - add x0, xFP, #OFF_FP_SHADOWFRAME - mov x1, xPC - mov w2, wINST - mov x3, xSELF - bl MterpNewArray - cbz w0, MterpPossibleException - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_new_instance.S b/runtime/interpreter/mterp/arm64/op_new_instance.S deleted file mode 100644 index c171ac58f6b5c54ef936f7aa16a69a0b0f9081cd..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_new_instance.S +++ /dev/null @@ -1,13 +0,0 @@ - /* - * Create a new instance of a class. - */ - /* new-instance vAA, class//BBBB */ - EXPORT_PC - add x0, xFP, #OFF_FP_SHADOWFRAME - mov x1, xSELF - mov w2, wINST - bl MterpNewInstance // (shadow_frame, self, inst_data) - cbz w0, MterpPossibleException - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_nop.S b/runtime/interpreter/mterp/arm64/op_nop.S deleted file mode 100644 index 80c2d452f81d3ee6273d875ced07934dd04e05fd..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_nop.S +++ /dev/null @@ -1,3 +0,0 @@ - FETCH_ADVANCE_INST 1 // advance to next instr, load rINST - GET_INST_OPCODE ip // ip<- opcode from rINST - GOTO_OPCODE ip // execute it diff --git a/runtime/interpreter/mterp/arm64/op_not_int.S b/runtime/interpreter/mterp/arm64/op_not_int.S deleted file mode 100644 index 55d77502aa430843b7c71d4ae3caf882c2f09a6b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_not_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/unop.S" {"instr":"mvn w0, w0"} diff --git a/runtime/interpreter/mterp/arm64/op_not_long.S b/runtime/interpreter/mterp/arm64/op_not_long.S deleted file mode 100644 index e5ebdd6e65a559a7c9e0810ddd3abe3d76cd0bde..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_not_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/unopWide.S" {"instr":"mvn x0, x0"} diff --git a/runtime/interpreter/mterp/arm64/op_or_int.S b/runtime/interpreter/mterp/arm64/op_or_int.S deleted file mode 100644 index 648c1e68503778cfbb40bca20bdefa5c68850b46..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_or_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binop.S" {"instr":"orr w0, w0, w1"} diff --git a/runtime/interpreter/mterp/arm64/op_or_int_2addr.S b/runtime/interpreter/mterp/arm64/op_or_int_2addr.S deleted file mode 100644 index abdf599fe9372f08e609cc84e0937dad0ce31039..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_or_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binop2addr.S" {"instr":"orr w0, w0, w1"} diff --git a/runtime/interpreter/mterp/arm64/op_or_int_lit16.S b/runtime/interpreter/mterp/arm64/op_or_int_lit16.S deleted file mode 100644 index db7f4ffb0a92f693634f25f3500047e08a2eaef5..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_or_int_lit16.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binopLit16.S" {"instr":"orr w0, w0, w1"} diff --git a/runtime/interpreter/mterp/arm64/op_or_int_lit8.S b/runtime/interpreter/mterp/arm64/op_or_int_lit8.S deleted file mode 100644 index 7cb26b7796039df60ec169657d6140123aca5552..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_or_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binopLit8.S" {"extract":"", "instr":"orr w0, w0, w3, asr #8"} diff --git a/runtime/interpreter/mterp/arm64/op_or_long.S b/runtime/interpreter/mterp/arm64/op_or_long.S deleted file mode 100644 index dd137ce85b76ba62116d997d817b48232a9aecbb..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_or_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binopWide.S" {"instr":"orr x0, x1, x2"} diff --git a/runtime/interpreter/mterp/arm64/op_or_long_2addr.S b/runtime/interpreter/mterp/arm64/op_or_long_2addr.S deleted file mode 100644 index f785230e1c53c71daebe533d4b639561f8b7cd41..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_or_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binopWide2addr.S" {"instr":"orr x0, x0, x1"} diff --git a/runtime/interpreter/mterp/arm64/op_packed_switch.S b/runtime/interpreter/mterp/arm64/op_packed_switch.S deleted file mode 100644 index 408e03069b5aaa13e52bed9caec2f067e2e931e3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_packed_switch.S +++ /dev/null @@ -1,20 +0,0 @@ -%default { "func":"MterpDoPackedSwitch" } - /* - * Handle a packed-switch or sparse-switch instruction. In both cases - * we decode it and hand it off to a helper function. - * - * We don't really expect backward branches in a switch statement, but - * they're perfectly legal, so we check for them here. - * - * for: packed-switch, sparse-switch - */ - /* op vAA, +BBBB */ - FETCH w0, 1 // x0<- 000000000000bbbb (lo) - FETCH_S x1, 2 // x1<- ssssssssssssBBBB (hi) - lsr w3, wINST, #8 // w3<- AA - orr x0, x0, x1, lsl #16 // x0<- ssssssssBBBBbbbb - GET_VREG w1, w3 // w1<- vAA - add x0, xPC, x0, lsl #1 // x0<- PC + ssssssssBBBBbbbb*2 - bl $func // w0<- code-unit branch offset - sxtw xINST, w0 - b MterpCommonTakenBranchNoFlags diff --git a/runtime/interpreter/mterp/arm64/op_rem_double.S b/runtime/interpreter/mterp/arm64/op_rem_double.S deleted file mode 100644 index c631ddbfe591378158008d424b385921730f239a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_rem_double.S +++ /dev/null @@ -1,13 +0,0 @@ - /* rem vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w2, w0, #8 // w2<- CC - and w1, w0, #255 // w1<- BB - GET_VREG_WIDE d1, w2 // d1<- vCC - GET_VREG_WIDE d0, w1 // d0<- vBB - bl fmod - lsr w4, wINST, #8 // w4<- AA - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE d0, w4 // vAA<- result - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ diff --git a/runtime/interpreter/mterp/arm64/op_rem_double_2addr.S b/runtime/interpreter/mterp/arm64/op_rem_double_2addr.S deleted file mode 100644 index 9868f4123aef727a7975be301dddfc6dcb8433e1..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_rem_double_2addr.S +++ /dev/null @@ -1,12 +0,0 @@ - /* rem vA, vB */ - lsr w1, wINST, #12 // w1<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG_WIDE d1, w1 // d1<- vB - GET_VREG_WIDE d0, w2 // d0<- vA - bl fmod - ubfx w2, wINST, #8, #4 // w2<- A (need to reload - killed across call) - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE d0, w2 // vAA<- result - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ diff --git a/runtime/interpreter/mterp/arm64/op_rem_float.S b/runtime/interpreter/mterp/arm64/op_rem_float.S deleted file mode 100644 index 73f7060cf547fd32c1985b20fb90477e04207c09..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_rem_float.S +++ /dev/null @@ -1,2 +0,0 @@ -/* EABI doesn't define a float remainder function, but libm does */ -%include "arm64/fbinop.S" {"instr":"bl fmodf"} diff --git a/runtime/interpreter/mterp/arm64/op_rem_float_2addr.S b/runtime/interpreter/mterp/arm64/op_rem_float_2addr.S deleted file mode 100644 index 95f81c5a237dd24e5df92f63f7bfb4c4aaa0323a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_rem_float_2addr.S +++ /dev/null @@ -1,11 +0,0 @@ - /* rem vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG s1, w3 - GET_VREG s0, w9 - bl fmodf - ubfx w9, wINST, #8, #4 // w9<- A - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG s0, w9 - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/arm64/op_rem_int.S b/runtime/interpreter/mterp/arm64/op_rem_int.S deleted file mode 100644 index dd9dfda0883c9e63829f656c8f209cb8a1702477..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_rem_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binop.S" {"preinstr":"sdiv w2, w0, w1", "instr":"msub w0, w2, w1, w0", "chkzero":"1"} diff --git a/runtime/interpreter/mterp/arm64/op_rem_int_2addr.S b/runtime/interpreter/mterp/arm64/op_rem_int_2addr.S deleted file mode 100644 index 57fc4971b9fb87dfd0b2b775099a44c31930ba8d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_rem_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binop2addr.S" {"preinstr":"sdiv w2, w0, w1", "instr":"msub w0, w2, w1, w0", "chkzero":"1"} diff --git a/runtime/interpreter/mterp/arm64/op_rem_int_lit16.S b/runtime/interpreter/mterp/arm64/op_rem_int_lit16.S deleted file mode 100644 index b51a739d2e7bb1264390a1cf4989951fe9d0f6e1..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_rem_int_lit16.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binopLit16.S" {"preinstr":"sdiv w3, w0, w1", "instr":"msub w0, w3, w1, w0", "chkzero":"1"} diff --git a/runtime/interpreter/mterp/arm64/op_rem_int_lit8.S b/runtime/interpreter/mterp/arm64/op_rem_int_lit8.S deleted file mode 100644 index 03ea32420b4a631ef509688df549062875d94e82..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_rem_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binopLit8.S" {"preinstr":"sdiv w3, w0, w1", "instr":"msub w0, w3, w1, w0", "chkzero":"1"} diff --git a/runtime/interpreter/mterp/arm64/op_rem_long.S b/runtime/interpreter/mterp/arm64/op_rem_long.S deleted file mode 100644 index f133f86a6cc190506950b51edc2db96bd5fc18af..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_rem_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binopWide.S" {"preinstr":"sdiv x3, x1, x2","instr":"msub x0, x3, x2, x1", "chkzero":"1"} diff --git a/runtime/interpreter/mterp/arm64/op_rem_long_2addr.S b/runtime/interpreter/mterp/arm64/op_rem_long_2addr.S deleted file mode 100644 index b45e2a95c19495ea59aca960e8e7d2d61937f215..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_rem_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binopWide2addr.S" {"preinstr":"sdiv x3, x0, x1", "instr":"msub x0, x3, x1, x0", "chkzero":"1"} diff --git a/runtime/interpreter/mterp/arm64/op_return.S b/runtime/interpreter/mterp/arm64/op_return.S deleted file mode 100644 index 9f125c7fef5e7ea80a9465447fe9c87f29e3bb36..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_return.S +++ /dev/null @@ -1,19 +0,0 @@ - /* - * Return a 32-bit value. - * - * for: return, return-object - */ - /* op vAA */ - .extern MterpThreadFenceForConstructor - bl MterpThreadFenceForConstructor - ldr w7, [xSELF, #THREAD_FLAGS_OFFSET] - mov x0, xSELF - ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - b.ne .L${opcode}_check -.L${opcode}_return: - lsr w2, wINST, #8 // r2<- AA - GET_VREG w0, w2 // r0<- vAA - b MterpReturn -.L${opcode}_check: - bl MterpSuspendCheck // (self) - b .L${opcode}_return diff --git a/runtime/interpreter/mterp/arm64/op_return_object.S b/runtime/interpreter/mterp/arm64/op_return_object.S deleted file mode 100644 index b6cb532b53140913d14aeab6c5a71552d4b0542b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_return_object.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_return.S" diff --git a/runtime/interpreter/mterp/arm64/op_return_void.S b/runtime/interpreter/mterp/arm64/op_return_void.S deleted file mode 100644 index b2530062e8a32669db15a79cefb1010c4457e833..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_return_void.S +++ /dev/null @@ -1,12 +0,0 @@ - .extern MterpThreadFenceForConstructor - bl MterpThreadFenceForConstructor - ldr w7, [xSELF, #THREAD_FLAGS_OFFSET] - mov x0, xSELF - ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - b.ne .L${opcode}_check -.L${opcode}_return: - mov x0, #0 - b MterpReturn -.L${opcode}_check: - bl MterpSuspendCheck // (self) - b .L${opcode}_return diff --git a/runtime/interpreter/mterp/arm64/op_return_void_no_barrier.S b/runtime/interpreter/mterp/arm64/op_return_void_no_barrier.S deleted file mode 100644 index c8171690705e6bdd2b69972668356c48c91ac92f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_return_void_no_barrier.S +++ /dev/null @@ -1,10 +0,0 @@ - ldr w7, [xSELF, #THREAD_FLAGS_OFFSET] - mov x0, xSELF - ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - b.ne .L${opcode}_check -.L${opcode}_return: - mov x0, #0 - b MterpReturn -.L${opcode}_check: - bl MterpSuspendCheck // (self) - b .L${opcode}_return diff --git a/runtime/interpreter/mterp/arm64/op_return_wide.S b/runtime/interpreter/mterp/arm64/op_return_wide.S deleted file mode 100644 index c47661cd5471cc768de61896fe5b9909a78ac8af..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_return_wide.S +++ /dev/null @@ -1,18 +0,0 @@ - /* - * Return a 64-bit value. - */ - /* return-wide vAA */ - /* op vAA */ - .extern MterpThreadFenceForConstructor - bl MterpThreadFenceForConstructor - ldr w7, [xSELF, #THREAD_FLAGS_OFFSET] - mov x0, xSELF - ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - b.ne .L${opcode}_check -.L${opcode}_return: - lsr w2, wINST, #8 // w2<- AA - GET_VREG_WIDE x0, w2 // x0<- vAA - b MterpReturn -.L${opcode}_check: - bl MterpSuspendCheck // (self) - b .L${opcode}_return diff --git a/runtime/interpreter/mterp/arm64/op_rsub_int.S b/runtime/interpreter/mterp/arm64/op_rsub_int.S deleted file mode 100644 index 3bf45fe654edef5b2a994bada553a7f3ed4d1804..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_rsub_int.S +++ /dev/null @@ -1,2 +0,0 @@ -/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ -%include "arm64/binopLit16.S" {"instr":"sub w0, w1, w0"} diff --git a/runtime/interpreter/mterp/arm64/op_rsub_int_lit8.S b/runtime/interpreter/mterp/arm64/op_rsub_int_lit8.S deleted file mode 100644 index 7a3572b364b7d1c11f14355d5b7516fa37b3df37..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_rsub_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binopLit8.S" {"instr":"sub w0, w1, w0"} diff --git a/runtime/interpreter/mterp/arm64/op_sget.S b/runtime/interpreter/mterp/arm64/op_sget.S deleted file mode 100644 index 78e95b2e7c6d40f3cf4842192d45d14d72c748f1..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_sget.S +++ /dev/null @@ -1,2 +0,0 @@ -%default { "is_object":"0", "helper":"MterpSGetU32" } -%include "arm64/field.S" { } diff --git a/runtime/interpreter/mterp/arm64/op_sget_boolean.S b/runtime/interpreter/mterp/arm64/op_sget_boolean.S deleted file mode 100644 index 0cf9f09681ddcb4e099f2a54ad65ae66bbe3f8b8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_sget_boolean.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_sget.S" {"helper":"MterpSGetU8"} diff --git a/runtime/interpreter/mterp/arm64/op_sget_byte.S b/runtime/interpreter/mterp/arm64/op_sget_byte.S deleted file mode 100644 index 7c88a81faa58c57624fca81a59421b58a6169b6a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_sget_byte.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_sget.S" {"helper":"MterpSGetI8"} diff --git a/runtime/interpreter/mterp/arm64/op_sget_char.S b/runtime/interpreter/mterp/arm64/op_sget_char.S deleted file mode 100644 index 883e944ce5f3728df08d58204cfc3c8386984186..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_sget_char.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_sget.S" {"helper":"MterpSGetU16"} diff --git a/runtime/interpreter/mterp/arm64/op_sget_object.S b/runtime/interpreter/mterp/arm64/op_sget_object.S deleted file mode 100644 index 69d6adb54972da322866bcd476ccd79ee7723bd8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_sget_object.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_sget.S" {"is_object":"1", "helper":"MterpSGetObj"} diff --git a/runtime/interpreter/mterp/arm64/op_sget_short.S b/runtime/interpreter/mterp/arm64/op_sget_short.S deleted file mode 100644 index 6cb918433d31d75c9fc0b17c8d568fdee2526700..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_sget_short.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_sget.S" {"helper":"MterpSGetI16"} diff --git a/runtime/interpreter/mterp/arm64/op_sget_wide.S b/runtime/interpreter/mterp/arm64/op_sget_wide.S deleted file mode 100644 index f5d182e96d07e55cf0d891a15ac79daabe996e12..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_sget_wide.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_sget.S" {"helper":"MterpSGetU64"} diff --git a/runtime/interpreter/mterp/arm64/op_shl_int.S b/runtime/interpreter/mterp/arm64/op_shl_int.S deleted file mode 100644 index 3062a3fad87e13069ac6e17f9cd56dc43f670463..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_shl_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binop.S" {"instr":"lsl w0, w0, w1"} diff --git a/runtime/interpreter/mterp/arm64/op_shl_int_2addr.S b/runtime/interpreter/mterp/arm64/op_shl_int_2addr.S deleted file mode 100644 index 9a7e09f016e605cf8ca045be12ed689ec834cfb7..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_shl_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binop2addr.S" {"instr":"lsl w0, w0, w1"} diff --git a/runtime/interpreter/mterp/arm64/op_shl_int_lit8.S b/runtime/interpreter/mterp/arm64/op_shl_int_lit8.S deleted file mode 100644 index 9c19b55550af21620b4358712fc23f1cf3a7f83f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_shl_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binopLit8.S" {"extract":"ubfx w1, w3, #8, #5", "instr":"lsl w0, w0, w1"} diff --git a/runtime/interpreter/mterp/arm64/op_shl_long.S b/runtime/interpreter/mterp/arm64/op_shl_long.S deleted file mode 100644 index bbf96009539974c1868f6aaf9f16b3fa2526c04b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_shl_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/shiftWide.S" {"opcode":"lsl"} diff --git a/runtime/interpreter/mterp/arm64/op_shl_long_2addr.S b/runtime/interpreter/mterp/arm64/op_shl_long_2addr.S deleted file mode 100644 index a5c4013bf74fa2405a777a4150076436d98716dd..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_shl_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/shiftWide2addr.S" {"opcode":"lsl"} diff --git a/runtime/interpreter/mterp/arm64/op_shr_int.S b/runtime/interpreter/mterp/arm64/op_shr_int.S deleted file mode 100644 index 493b7407f7b4a248fd1e1da8f17dc98062223b1f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_shr_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binop.S" {"instr":"asr w0, w0, w1"} diff --git a/runtime/interpreter/mterp/arm64/op_shr_int_2addr.S b/runtime/interpreter/mterp/arm64/op_shr_int_2addr.S deleted file mode 100644 index 6efe8ee010c5dc338aea75cad94dc42f37d950ca..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_shr_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binop2addr.S" {"instr":"asr w0, w0, w1"} diff --git a/runtime/interpreter/mterp/arm64/op_shr_int_lit8.S b/runtime/interpreter/mterp/arm64/op_shr_int_lit8.S deleted file mode 100644 index c7b61df13d58f9d724628a7ecf53283be1e9dc2b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_shr_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binopLit8.S" {"extract":"ubfx w1, w3, #8, #5", "instr":"asr w0, w0, w1"} diff --git a/runtime/interpreter/mterp/arm64/op_shr_long.S b/runtime/interpreter/mterp/arm64/op_shr_long.S deleted file mode 100644 index 4d332359abb41d7669e2f57f7f224234f5110e83..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_shr_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/shiftWide.S" {"opcode":"asr"} diff --git a/runtime/interpreter/mterp/arm64/op_shr_long_2addr.S b/runtime/interpreter/mterp/arm64/op_shr_long_2addr.S deleted file mode 100644 index 0a4a386c9552e7498257b908ace1c839a175cb90..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_shr_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/shiftWide2addr.S" {"opcode":"asr"} diff --git a/runtime/interpreter/mterp/arm64/op_sparse_switch.S b/runtime/interpreter/mterp/arm64/op_sparse_switch.S deleted file mode 100644 index 5a8d7489bc662bc7e67d010a9486abec0503c316..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_sparse_switch.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_packed_switch.S" { "func":"MterpDoSparseSwitch" } diff --git a/runtime/interpreter/mterp/arm64/op_sput.S b/runtime/interpreter/mterp/arm64/op_sput.S deleted file mode 100644 index d229d0d8994e5daf43a3f06efdaea37c9b2a267d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_sput.S +++ /dev/null @@ -1,2 +0,0 @@ -%default { "is_object":"0", "helper":"MterpSPutU32"} -%include "arm64/field.S" { } diff --git a/runtime/interpreter/mterp/arm64/op_sput_boolean.S b/runtime/interpreter/mterp/arm64/op_sput_boolean.S deleted file mode 100644 index 3d0c7c02621ddd21addb7331b94948d2de8b1774..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_sput_boolean.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_sput.S" {"helper":"MterpSPutU8"} diff --git a/runtime/interpreter/mterp/arm64/op_sput_byte.S b/runtime/interpreter/mterp/arm64/op_sput_byte.S deleted file mode 100644 index 489cf92149d87cfcfd1b450aa6da342b3eb44f8c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_sput_byte.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_sput.S" {"helper":"MterpSPutI8"} diff --git a/runtime/interpreter/mterp/arm64/op_sput_char.S b/runtime/interpreter/mterp/arm64/op_sput_char.S deleted file mode 100644 index f79d311c1783954be8d5fc5acedaa95a717d4acf..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_sput_char.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_sput.S" {"helper":"MterpSPutU16"} diff --git a/runtime/interpreter/mterp/arm64/op_sput_object.S b/runtime/interpreter/mterp/arm64/op_sput_object.S deleted file mode 100644 index 536f1b16b8cd5ff4af178c56d49add8ba5fb020b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_sput_object.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_sput.S" {"is_object":"1", "helper":"MterpSPutObj"} diff --git a/runtime/interpreter/mterp/arm64/op_sput_short.S b/runtime/interpreter/mterp/arm64/op_sput_short.S deleted file mode 100644 index 06482cd7a003c60bafecb858ce117f2cdfc333e0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_sput_short.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_sput.S" {"helper":"MterpSPutI16"} diff --git a/runtime/interpreter/mterp/arm64/op_sput_wide.S b/runtime/interpreter/mterp/arm64/op_sput_wide.S deleted file mode 100644 index b4be6b29877933cc94c73440d8f56fd0ab3de17f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_sput_wide.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/op_sput.S" {"helper":"MterpSPutU64"} diff --git a/runtime/interpreter/mterp/arm64/op_sub_double.S b/runtime/interpreter/mterp/arm64/op_sub_double.S deleted file mode 100644 index e8e3401e17a2b07d1d6f19481e4d3ed93ac425f2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_sub_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binopWide.S" {"instr":"fsub d0, d1, d2", "result":"d0", "r1":"d1", "r2":"d2"} diff --git a/runtime/interpreter/mterp/arm64/op_sub_double_2addr.S b/runtime/interpreter/mterp/arm64/op_sub_double_2addr.S deleted file mode 100644 index ddab55e9fe13b0b9f7f6a703e785da7d28999745..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_sub_double_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binopWide2addr.S" {"instr":"fsub d0, d0, d1", "r0":"d0", "r1":"d1"} diff --git a/runtime/interpreter/mterp/arm64/op_sub_float.S b/runtime/interpreter/mterp/arm64/op_sub_float.S deleted file mode 100644 index 227b15fdf3719cc5ec33cbcf5d602fc3642d8668..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_sub_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/fbinop.S" {"instr":"fsub s0, s0, s1"} diff --git a/runtime/interpreter/mterp/arm64/op_sub_float_2addr.S b/runtime/interpreter/mterp/arm64/op_sub_float_2addr.S deleted file mode 100644 index 19ac8d56162bbbd8232b5eb5bc048dabe37dcf7e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_sub_float_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/fbinop2addr.S" {"instr":"fsub s2, s0, s1"} diff --git a/runtime/interpreter/mterp/arm64/op_sub_int.S b/runtime/interpreter/mterp/arm64/op_sub_int.S deleted file mode 100644 index 0e7ce0e6e57e197cc2db7991df97f919c4fd1cb1..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_sub_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binop.S" {"instr":"sub w0, w0, w1"} diff --git a/runtime/interpreter/mterp/arm64/op_sub_int_2addr.S b/runtime/interpreter/mterp/arm64/op_sub_int_2addr.S deleted file mode 100644 index d2c1bd307aadf90b07d15eb6a81d59bc3a19302e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_sub_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binop2addr.S" {"instr":"sub w0, w0, w1"} diff --git a/runtime/interpreter/mterp/arm64/op_sub_long.S b/runtime/interpreter/mterp/arm64/op_sub_long.S deleted file mode 100644 index 263c70d6e7fc7c0b3cd0a7a4f67b656cf0a82284..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_sub_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binopWide.S" {"instr":"sub x0, x1, x2"} diff --git a/runtime/interpreter/mterp/arm64/op_sub_long_2addr.S b/runtime/interpreter/mterp/arm64/op_sub_long_2addr.S deleted file mode 100644 index 5be3772670f3db4ba0b33c5309b42593b1ce54db..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_sub_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binopWide2addr.S" {"instr":"sub x0, x0, x1"} diff --git a/runtime/interpreter/mterp/arm64/op_throw.S b/runtime/interpreter/mterp/arm64/op_throw.S deleted file mode 100644 index 9a951af30207b3a5ad8881a71542b9805dafeff8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_throw.S +++ /dev/null @@ -1,10 +0,0 @@ - /* - * Throw an exception object in the current thread. - */ - /* throw vAA */ - EXPORT_PC - lsr w2, wINST, #8 // r2<- AA - GET_VREG w1, w2 // r1<- vAA (exception object) - cbz w1, common_errNullObject - str x1, [xSELF, #THREAD_EXCEPTION_OFFSET] // thread->exception<- obj - b MterpException diff --git a/runtime/interpreter/mterp/arm64/op_unused_3e.S b/runtime/interpreter/mterp/arm64/op_unused_3e.S deleted file mode 100644 index 204eceff7eaaadd339b3d6dfcf11dcce31bbc57b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_unused_3e.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/unused.S" diff --git a/runtime/interpreter/mterp/arm64/op_unused_3f.S b/runtime/interpreter/mterp/arm64/op_unused_3f.S deleted file mode 100644 index 204eceff7eaaadd339b3d6dfcf11dcce31bbc57b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_unused_3f.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/unused.S" diff --git a/runtime/interpreter/mterp/arm64/op_unused_40.S b/runtime/interpreter/mterp/arm64/op_unused_40.S deleted file mode 100644 index 204eceff7eaaadd339b3d6dfcf11dcce31bbc57b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_unused_40.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/unused.S" diff --git a/runtime/interpreter/mterp/arm64/op_unused_41.S b/runtime/interpreter/mterp/arm64/op_unused_41.S deleted file mode 100644 index 204eceff7eaaadd339b3d6dfcf11dcce31bbc57b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_unused_41.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/unused.S" diff --git a/runtime/interpreter/mterp/arm64/op_unused_42.S b/runtime/interpreter/mterp/arm64/op_unused_42.S deleted file mode 100644 index 204eceff7eaaadd339b3d6dfcf11dcce31bbc57b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_unused_42.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/unused.S" diff --git a/runtime/interpreter/mterp/arm64/op_unused_43.S b/runtime/interpreter/mterp/arm64/op_unused_43.S deleted file mode 100644 index 204eceff7eaaadd339b3d6dfcf11dcce31bbc57b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_unused_43.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/unused.S" diff --git a/runtime/interpreter/mterp/arm64/op_unused_73.S b/runtime/interpreter/mterp/arm64/op_unused_73.S deleted file mode 100644 index 204eceff7eaaadd339b3d6dfcf11dcce31bbc57b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_unused_73.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/unused.S" diff --git a/runtime/interpreter/mterp/arm64/op_unused_79.S b/runtime/interpreter/mterp/arm64/op_unused_79.S deleted file mode 100644 index 204eceff7eaaadd339b3d6dfcf11dcce31bbc57b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_unused_79.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/unused.S" diff --git a/runtime/interpreter/mterp/arm64/op_unused_7a.S b/runtime/interpreter/mterp/arm64/op_unused_7a.S deleted file mode 100644 index 204eceff7eaaadd339b3d6dfcf11dcce31bbc57b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_unused_7a.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/unused.S" diff --git a/runtime/interpreter/mterp/arm64/op_unused_f3.S b/runtime/interpreter/mterp/arm64/op_unused_f3.S deleted file mode 100644 index 204eceff7eaaadd339b3d6dfcf11dcce31bbc57b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_unused_f3.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/unused.S" diff --git a/runtime/interpreter/mterp/arm64/op_unused_f4.S b/runtime/interpreter/mterp/arm64/op_unused_f4.S deleted file mode 100644 index 204eceff7eaaadd339b3d6dfcf11dcce31bbc57b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_unused_f4.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/unused.S" diff --git a/runtime/interpreter/mterp/arm64/op_unused_f5.S b/runtime/interpreter/mterp/arm64/op_unused_f5.S deleted file mode 100644 index 204eceff7eaaadd339b3d6dfcf11dcce31bbc57b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_unused_f5.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/unused.S" diff --git a/runtime/interpreter/mterp/arm64/op_unused_f6.S b/runtime/interpreter/mterp/arm64/op_unused_f6.S deleted file mode 100644 index 204eceff7eaaadd339b3d6dfcf11dcce31bbc57b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_unused_f6.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/unused.S" diff --git a/runtime/interpreter/mterp/arm64/op_unused_f7.S b/runtime/interpreter/mterp/arm64/op_unused_f7.S deleted file mode 100644 index 204eceff7eaaadd339b3d6dfcf11dcce31bbc57b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_unused_f7.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/unused.S" diff --git a/runtime/interpreter/mterp/arm64/op_unused_f8.S b/runtime/interpreter/mterp/arm64/op_unused_f8.S deleted file mode 100644 index 204eceff7eaaadd339b3d6dfcf11dcce31bbc57b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_unused_f8.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/unused.S" diff --git a/runtime/interpreter/mterp/arm64/op_unused_f9.S b/runtime/interpreter/mterp/arm64/op_unused_f9.S deleted file mode 100644 index 204eceff7eaaadd339b3d6dfcf11dcce31bbc57b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_unused_f9.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/unused.S" diff --git a/runtime/interpreter/mterp/arm64/op_unused_fc.S b/runtime/interpreter/mterp/arm64/op_unused_fc.S deleted file mode 100644 index 204eceff7eaaadd339b3d6dfcf11dcce31bbc57b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_unused_fc.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/unused.S" diff --git a/runtime/interpreter/mterp/arm64/op_unused_fd.S b/runtime/interpreter/mterp/arm64/op_unused_fd.S deleted file mode 100644 index 204eceff7eaaadd339b3d6dfcf11dcce31bbc57b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_unused_fd.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/unused.S" diff --git a/runtime/interpreter/mterp/arm64/op_ushr_int.S b/runtime/interpreter/mterp/arm64/op_ushr_int.S deleted file mode 100644 index 005452b5540c6824adb8bfb53af58173e60468a8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_ushr_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binop.S" {"instr":"lsr w0, w0, w1"} diff --git a/runtime/interpreter/mterp/arm64/op_ushr_int_2addr.S b/runtime/interpreter/mterp/arm64/op_ushr_int_2addr.S deleted file mode 100644 index 1cb8cb74422faaf2603bb6f02a0689c07a7e5925..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_ushr_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binop2addr.S" {"instr":"lsr w0, w0, w1"} diff --git a/runtime/interpreter/mterp/arm64/op_ushr_int_lit8.S b/runtime/interpreter/mterp/arm64/op_ushr_int_lit8.S deleted file mode 100644 index 555ed4eb296d7b5e1abe9e14bf3aa43c7ba75959..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_ushr_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binopLit8.S" {"extract":"ubfx w1, w3, #8, #5", "instr":"lsr w0, w0, w1"} diff --git a/runtime/interpreter/mterp/arm64/op_ushr_long.S b/runtime/interpreter/mterp/arm64/op_ushr_long.S deleted file mode 100644 index e13c86a48bb55de4fa94acb21106e19dbff12b1c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_ushr_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/shiftWide.S" {"opcode":"lsr"} diff --git a/runtime/interpreter/mterp/arm64/op_ushr_long_2addr.S b/runtime/interpreter/mterp/arm64/op_ushr_long_2addr.S deleted file mode 100644 index 67ec91e967d0e092e686b357d49ae70c5230c35c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_ushr_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/shiftWide2addr.S" {"opcode":"lsr"} diff --git a/runtime/interpreter/mterp/arm64/op_xor_int.S b/runtime/interpreter/mterp/arm64/op_xor_int.S deleted file mode 100644 index 74836635fe8f598881f7ed17911ad46082cb1050..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_xor_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binop.S" {"instr":"eor w0, w0, w1"} diff --git a/runtime/interpreter/mterp/arm64/op_xor_int_2addr.S b/runtime/interpreter/mterp/arm64/op_xor_int_2addr.S deleted file mode 100644 index 2f9a2c73594454c60d6996981fe49c0c42b16b70..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_xor_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binop2addr.S" {"instr":"eor w0, w0, w1"} diff --git a/runtime/interpreter/mterp/arm64/op_xor_int_lit16.S b/runtime/interpreter/mterp/arm64/op_xor_int_lit16.S deleted file mode 100644 index 6b72c560f994d466e6af65e031ca200617f913a8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_xor_int_lit16.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binopLit16.S" {"instr":"eor w0, w0, w1"} diff --git a/runtime/interpreter/mterp/arm64/op_xor_int_lit8.S b/runtime/interpreter/mterp/arm64/op_xor_int_lit8.S deleted file mode 100644 index 1d3d93e3f74c86ba06a5518a9d56ab566b4ecf9f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_xor_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binopLit8.S" {"extract":"", "instr":"eor w0, w0, w3, asr #8"} diff --git a/runtime/interpreter/mterp/arm64/op_xor_long.S b/runtime/interpreter/mterp/arm64/op_xor_long.S deleted file mode 100644 index 3880d5d19f70d9b670639213b5cf1480338ea4e8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_xor_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binopWide.S" {"instr":"eor x0, x1, x2"} diff --git a/runtime/interpreter/mterp/arm64/op_xor_long_2addr.S b/runtime/interpreter/mterp/arm64/op_xor_long_2addr.S deleted file mode 100644 index 36905529d514f49f5fef364189dd7519bf232949..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/op_xor_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "arm64/binopWide2addr.S" {"instr":"eor x0, x0, x1"} diff --git a/runtime/interpreter/mterp/arm64/other.S b/runtime/interpreter/mterp/arm64/other.S new file mode 100644 index 0000000000000000000000000000000000000000..024a5c8a075a634addf381e30464dc7ea7a8d931 --- /dev/null +++ b/runtime/interpreter/mterp/arm64/other.S @@ -0,0 +1,355 @@ +%def const(helper="UndefinedConstHandler"): + /* const/class vAA, type@BBBB */ + /* const/method-handle vAA, method_handle@BBBB */ + /* const/method-type vAA, proto@BBBB */ + /* const/string vAA, string@@BBBB */ + .extern $helper + EXPORT_PC + FETCH w0, 1 // w0<- BBBB + lsr w1, wINST, #8 // w1<- AA + add x2, xFP, #OFF_FP_SHADOWFRAME + mov x3, xSELF + bl $helper // (index, tgt_reg, shadow_frame, self) + PREFETCH_INST 2 // load rINST + cbnz w0, MterpPossibleException // let reference interpreter deal with it. + ADVANCE 2 // advance rPC + GET_INST_OPCODE ip // extract opcode from rINST + GOTO_OPCODE ip // jump to next instruction + +%def unused(): +/* + * Bail to reference interpreter to throw. + */ + b MterpFallback + +%def op_const(): + /* const vAA, #+BBBBbbbb */ + lsr w3, wINST, #8 // w3<- AA + FETCH w0, 1 // w0<- bbbb (low + FETCH w1, 2 // w1<- BBBB (high + FETCH_ADVANCE_INST 3 // advance rPC, load wINST + orr w0, w0, w1, lsl #16 // w0<- BBBBbbbb + GET_INST_OPCODE ip // extract opcode from wINST + SET_VREG w0, w3 // vAA<- w0 + GOTO_OPCODE ip // jump to next instruction + +%def op_const_16(): + /* const/16 vAA, #+BBBB */ + FETCH_S w0, 1 // w0<- ssssBBBB (sign-extended) + lsr w3, wINST, #8 // w3<- AA + FETCH_ADVANCE_INST 2 // advance xPC, load wINST + SET_VREG w0, w3 // vAA<- w0 + GET_INST_OPCODE ip // extract opcode from wINST + GOTO_OPCODE ip // jump to next instruction + +%def op_const_4(): + /* const/4 vA, #+B */ + sbfx w1, wINST, #12, #4 // w1<- sssssssB + ubfx w0, wINST, #8, #4 // w0<- A + FETCH_ADVANCE_INST 1 // advance xPC, load wINST + GET_INST_OPCODE ip // ip<- opcode from xINST + SET_VREG w1, w0 // fp[A]<- w1 + GOTO_OPCODE ip // execute next instruction + +%def op_const_class(): +% const(helper="MterpConstClass") + +%def op_const_high16(): + /* const/high16 vAA, #+BBBB0000 */ + FETCH w0, 1 // r0<- 0000BBBB (zero-extended) + lsr w3, wINST, #8 // r3<- AA + lsl w0, w0, #16 // r0<- BBBB0000 + FETCH_ADVANCE_INST 2 // advance rPC, load rINST + SET_VREG w0, w3 // vAA<- r0 + GET_INST_OPCODE ip // extract opcode from rINST + GOTO_OPCODE ip // jump to next instruction + +%def op_const_method_handle(): +% const(helper="MterpConstMethodHandle") + +%def op_const_method_type(): +% const(helper="MterpConstMethodType") + +%def op_const_string(): +% const(helper="MterpConstString") + +%def op_const_string_jumbo(): + /* const/string vAA, String//BBBBBBBB */ + EXPORT_PC + FETCH w0, 1 // w0<- bbbb (low + FETCH w2, 2 // w2<- BBBB (high + lsr w1, wINST, #8 // w1<- AA + orr w0, w0, w2, lsl #16 // w1<- BBBBbbbb + add x2, xFP, #OFF_FP_SHADOWFRAME + mov x3, xSELF + bl MterpConstString // (index, tgt_reg, shadow_frame, self) + PREFETCH_INST 3 // advance rPC + cbnz w0, MterpPossibleException // let reference interpreter deal with it. + ADVANCE 3 // advance rPC + GET_INST_OPCODE ip // extract opcode from rINST + GOTO_OPCODE ip // jump to next instruction + +%def op_const_wide(): + /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ + FETCH w0, 1 // w0<- bbbb (low) + FETCH w1, 2 // w1<- BBBB (low middle) + FETCH w2, 3 // w2<- hhhh (high middle) + FETCH w3, 4 // w3<- HHHH (high) + lsr w4, wINST, #8 // r4<- AA + FETCH_ADVANCE_INST 5 // advance rPC, load wINST + GET_INST_OPCODE ip // extract opcode from wINST + orr w0, w0, w1, lsl #16 // w0<- BBBBbbbb + orr x0, x0, x2, lsl #32 // w0<- hhhhBBBBbbbb + orr x0, x0, x3, lsl #48 // w0<- HHHHhhhhBBBBbbbb + SET_VREG_WIDE x0, w4 + GOTO_OPCODE ip // jump to next instruction + +%def op_const_wide_16(): + /* const-wide/16 vAA, #+BBBB */ + FETCH_S x0, 1 // x0<- ssssssssssssBBBB (sign-extended) + lsr w3, wINST, #8 // w3<- AA + FETCH_ADVANCE_INST 2 // advance rPC, load rINST + GET_INST_OPCODE ip // extract opcode from rINST + SET_VREG_WIDE x0, w3 + GOTO_OPCODE ip // jump to next instruction + +%def op_const_wide_32(): + /* const-wide/32 vAA, #+BBBBbbbb */ + FETCH w0, 1 // x0<- 000000000000bbbb (low) + lsr w3, wINST, #8 // w3<- AA + FETCH_S x2, 2 // x2<- ssssssssssssBBBB (high) + FETCH_ADVANCE_INST 3 // advance rPC, load wINST + GET_INST_OPCODE ip // extract opcode from wINST + orr x0, x0, x2, lsl #16 // x0<- ssssssssBBBBbbbb + SET_VREG_WIDE x0, w3 + GOTO_OPCODE ip // jump to next instruction + +%def op_const_wide_high16(): + /* const-wide/high16 vAA, #+BBBB000000000000 */ + FETCH w0, 1 // w0<- 0000BBBB (zero-extended) + lsr w1, wINST, #8 // w1<- AA + FETCH_ADVANCE_INST 2 // advance rPC, load wINST + lsl x0, x0, #48 + SET_VREG_WIDE x0, w1 + GET_INST_OPCODE ip // extract opcode from wINST + GOTO_OPCODE ip // jump to next instruction + +%def op_monitor_enter(): + /* + * Synchronize on an object. + */ + /* monitor-enter vAA */ + EXPORT_PC + lsr w2, wINST, #8 // w2<- AA + GET_VREG w0, w2 // w0<- vAA (object) + mov x1, xSELF // w1<- self + bl artLockObjectFromCode + cbnz w0, MterpException + FETCH_ADVANCE_INST 1 + GET_INST_OPCODE ip // extract opcode from rINST + GOTO_OPCODE ip // jump to next instruction + +%def op_monitor_exit(): + /* + * Unlock an object. + * + * Exceptions that occur when unlocking a monitor need to appear as + * if they happened at the following instruction. See the Dalvik + * instruction spec. + */ + /* monitor-exit vAA */ + EXPORT_PC + lsr w2, wINST, #8 // w2<- AA + GET_VREG w0, w2 // w0<- vAA (object) + mov x1, xSELF // w0<- self + bl artUnlockObjectFromCode // w0<- success for unlock(self, obj) + cbnz w0, MterpException + FETCH_ADVANCE_INST 1 // before throw: advance rPC, load rINST + GET_INST_OPCODE ip // extract opcode from rINST + GOTO_OPCODE ip // jump to next instruction + +%def op_move(is_object="0"): + /* for move, move-object, long-to-int */ + /* op vA, vB */ + lsr w1, wINST, #12 // x1<- B from 15:12 + ubfx w0, wINST, #8, #4 // x0<- A from 11:8 + FETCH_ADVANCE_INST 1 // advance rPC, load wINST + GET_VREG w2, w1 // x2<- fp[B] + GET_INST_OPCODE ip // ip<- opcode from wINST + .if $is_object + SET_VREG_OBJECT w2, w0 // fp[A]<- x2 + .else + SET_VREG w2, w0 // fp[A]<- x2 + .endif + GOTO_OPCODE ip // execute next instruction + +%def op_move_16(is_object="0"): + /* for: move/16, move-object/16 */ + /* op vAAAA, vBBBB */ + FETCH w1, 2 // w1<- BBBB + FETCH w0, 1 // w0<- AAAA + FETCH_ADVANCE_INST 3 // advance xPC, load xINST + GET_VREG w2, w1 // w2<- fp[BBBB] + GET_INST_OPCODE ip // extract opcode from xINST + .if $is_object + SET_VREG_OBJECT w2, w0 // fp[AAAA]<- w2 + .else + SET_VREG w2, w0 // fp[AAAA]<- w2 + .endif + GOTO_OPCODE ip // jump to next instruction + +%def op_move_exception(): + /* move-exception vAA */ + lsr w2, wINST, #8 // w2<- AA + ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] + mov x1, #0 // w1<- 0 + FETCH_ADVANCE_INST 1 // advance rPC, load rINST + SET_VREG_OBJECT w3, w2 // fp[AA]<- exception obj + GET_INST_OPCODE ip // extract opcode from rINST + str x1, [xSELF, #THREAD_EXCEPTION_OFFSET] // clear exception + GOTO_OPCODE ip // jump to next instruction + +%def op_move_from16(is_object="0"): + /* for: move/from16, move-object/from16 */ + /* op vAA, vBBBB */ + FETCH w1, 1 // r1<- BBBB + lsr w0, wINST, #8 // r0<- AA + FETCH_ADVANCE_INST 2 // advance rPC, load wINST + GET_VREG w2, w1 // r2<- fp[BBBB] + GET_INST_OPCODE ip // extract opcode from wINST + .if $is_object + SET_VREG_OBJECT w2, w0 // fp[AA]<- r2 + .else + SET_VREG w2, w0 // fp[AA]<- r2 + .endif + GOTO_OPCODE ip // jump to next instruction + +%def op_move_object(): +% op_move(is_object="1") + +%def op_move_object_16(): +% op_move_16(is_object="1") + +%def op_move_object_from16(): +% op_move_from16(is_object="1") + +%def op_move_result(is_object="0"): + /* for: move-result, move-result-object */ + /* op vAA */ + lsr w2, wINST, #8 // r2<- AA + FETCH_ADVANCE_INST 1 // advance rPC, load wINST + ldr x0, [xFP, #OFF_FP_RESULT_REGISTER] // get pointer to result JType. + ldr w0, [x0] // r0 <- result.i. + GET_INST_OPCODE ip // extract opcode from wINST + .if $is_object + SET_VREG_OBJECT w0, w2, w1 // fp[AA]<- r0 + .else + SET_VREG w0, w2 // fp[AA]<- r0 + .endif + GOTO_OPCODE ip // jump to next instruction + +%def op_move_result_object(): +% op_move_result(is_object="1") + +%def op_move_result_wide(): + /* for: move-result-wide */ + /* op vAA */ + lsr w2, wINST, #8 // r2<- AA + FETCH_ADVANCE_INST 1 // advance rPC, load wINST + ldr x0, [xFP, #OFF_FP_RESULT_REGISTER] // get pointer to result JType. + ldr x0, [x0] // r0 <- result.i. + GET_INST_OPCODE ip // extract opcode from wINST + SET_VREG_WIDE x0, x2 // fp[AA]<- r0 + GOTO_OPCODE ip // jump to next instruction + +%def op_move_wide(): + /* move-wide vA, vB */ + /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ + lsr w3, wINST, #12 // w3<- B + ubfx w2, wINST, #8, #4 // w2<- A + GET_VREG_WIDE x3, w3 + FETCH_ADVANCE_INST 1 // advance rPC, load wINST + GET_INST_OPCODE ip // extract opcode from wINST + SET_VREG_WIDE x3, w2 + GOTO_OPCODE ip // jump to next instruction + +%def op_move_wide_16(): + /* move-wide/16 vAAAA, vBBBB */ + /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ + FETCH w3, 2 // w3<- BBBB + FETCH w2, 1 // w2<- AAAA + GET_VREG_WIDE x3, w3 + FETCH_ADVANCE_INST 3 // advance rPC, load rINST + SET_VREG_WIDE x3, w2 + GET_INST_OPCODE ip // extract opcode from rINST + GOTO_OPCODE ip // jump to next instruction + +%def op_move_wide_from16(): + /* move-wide/from16 vAA, vBBBB */ + /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ + FETCH w3, 1 // w3<- BBBB + lsr w2, wINST, #8 // w2<- AA + GET_VREG_WIDE x3, w3 + FETCH_ADVANCE_INST 2 // advance rPC, load wINST + GET_INST_OPCODE ip // extract opcode from wINST + SET_VREG_WIDE x3, w2 + GOTO_OPCODE ip // jump to next instruction + +%def op_nop(): + FETCH_ADVANCE_INST 1 // advance to next instr, load rINST + GET_INST_OPCODE ip // ip<- opcode from rINST + GOTO_OPCODE ip // execute it + +%def op_unused_3e(): +% unused() + +%def op_unused_3f(): +% unused() + +%def op_unused_40(): +% unused() + +%def op_unused_41(): +% unused() + +%def op_unused_42(): +% unused() + +%def op_unused_43(): +% unused() + +%def op_unused_73(): +% unused() + +%def op_unused_79(): +% unused() + +%def op_unused_7a(): +% unused() + +%def op_unused_f3(): +% unused() + +%def op_unused_f4(): +% unused() + +%def op_unused_f5(): +% unused() + +%def op_unused_f6(): +% unused() + +%def op_unused_f7(): +% unused() + +%def op_unused_f8(): +% unused() + +%def op_unused_f9(): +% unused() + +%def op_unused_fc(): +% unused() + +%def op_unused_fd(): +% unused() diff --git a/runtime/interpreter/mterp/arm64/shiftWide.S b/runtime/interpreter/mterp/arm64/shiftWide.S deleted file mode 100644 index dcb2fb701a79454129812d2afa5378d87f9e40d8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/shiftWide.S +++ /dev/null @@ -1,19 +0,0 @@ -%default {"opcode":"shl"} - /* - * 64-bit shift operation. - * - * For: shl-long, shr-long, ushr-long - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w3, wINST, #8 // w3<- AA - lsr w2, w0, #8 // w2<- CC - GET_VREG w2, w2 // w2<- vCC (shift count) - and w1, w0, #255 // w1<- BB - GET_VREG_WIDE x1, w1 // x1<- vBB - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - $opcode x0, x1, x2 // Do the shift. Only low 6 bits of x2 are used. - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w3 // vAA<- x0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ diff --git a/runtime/interpreter/mterp/arm64/shiftWide2addr.S b/runtime/interpreter/mterp/arm64/shiftWide2addr.S deleted file mode 100644 index b860dfddd3e749a4fa54672757a4b38d15411886..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/shiftWide2addr.S +++ /dev/null @@ -1,15 +0,0 @@ -%default {"opcode":"lsl"} - /* - * Generic 64-bit shift operation. - */ - /* binop/2addr vA, vB */ - lsr w1, wINST, #12 // w1<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG w1, w1 // x1<- vB - GET_VREG_WIDE x0, w2 // x0<- vA - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - $opcode x0, x0, x1 // Do the shift. Only low 6 bits of x1 are used. - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w2 // vAA<- result - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ diff --git a/runtime/interpreter/mterp/arm64/unop.S b/runtime/interpreter/mterp/arm64/unop.S deleted file mode 100644 index e681968a9fedd0cdc669168902c51d498b1248ae..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/unop.S +++ /dev/null @@ -1,18 +0,0 @@ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op w0". - * This could be an ARM instruction or a function call. - * - * for: neg-int, not-int, neg-float, int-to-float, float-to-int, - * int-to-byte, int-to-char, int-to-short - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - GET_VREG w0, w3 // w0<- vB - ubfx w9, wINST, #8, #4 // w9<- A - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - $instr // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 8-9 instructions */ diff --git a/runtime/interpreter/mterp/arm64/unopWide.S b/runtime/interpreter/mterp/arm64/unopWide.S deleted file mode 100644 index 6ee4f922e19262c93460ab4b9b7eb5c61fc19615..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/unopWide.S +++ /dev/null @@ -1,17 +0,0 @@ -%default {"instr":"sub x0, xzr, x0"} - /* - * Generic 64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op x0". - * - * For: neg-long, not-long - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w4, wINST, #8, #4 // w4<- A - GET_VREG_WIDE x0, w3 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - $instr - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG_WIDE x0, w4 - GOTO_OPCODE ip // jump to next instruction - /* 10-11 instructions */ diff --git a/runtime/interpreter/mterp/arm64/unused.S b/runtime/interpreter/mterp/arm64/unused.S deleted file mode 100644 index ffa00becfdb2bb4ba58ee7659a0609978599110e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/unused.S +++ /dev/null @@ -1,4 +0,0 @@ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback diff --git a/runtime/interpreter/mterp/arm64/zcmp.S b/runtime/interpreter/mterp/arm64/zcmp.S deleted file mode 100644 index 510a3c10cd1bfb36619e75866e5895bd51fac637..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/arm64/zcmp.S +++ /dev/null @@ -1,20 +0,0 @@ -%default { "compare":"1" } - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - lsr w0, wINST, #8 // w0<- AA - GET_VREG w2, w0 // w2<- vAA - FETCH_S wINST, 1 // w1<- branch offset, in code units - .if ${compare} - cmp w2, #0 // compare (vA, 0) - .endif - ${branch} MterpCommonTakenBranchNoFlags - cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? - b.eq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction diff --git a/runtime/interpreter/mterp/common/gen_setup.py b/runtime/interpreter/mterp/common/gen_setup.py new file mode 100644 index 0000000000000000000000000000000000000000..5790a94b3501c9ea39a81acaf33aa87a18505014 --- /dev/null +++ b/runtime/interpreter/mterp/common/gen_setup.py @@ -0,0 +1,75 @@ +# +# Copyright (C) 2016 The Android Open Source Project +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +# Common global variables and helper methods for the in-memory python script. + +import sys, re +from cStringIO import StringIO + +out = StringIO() # File-like in-memory buffer. +handler_size_bytes = "128" +handler_size_bits = "7" +opcode = "" +opnum = "" + +def write_line(line): + out.write(line + "\n") + +def balign(): + write_line(" .balign {}".format(handler_size_bytes)) + +def write_opcode(num, name, write_method, is_alt): + global opnum, opcode + opnum, opcode = str(num), name + if is_alt: + name = "ALT_" + name + write_line("/* ------------------------------ */") + balign() + write_line(".L_{1}: /* {0:#04x} */".format(num, name)) + if is_alt: + alt_stub() + else: + write_method() + write_line("") + opnum, opcode = None, None + +def generate(output_filename): + out.seek(0) + out.truncate() + write_line("/* DO NOT EDIT: This file was generated by gen-mterp.py. */") + header() + entry() + + instruction_start() + opcodes(is_alt = False) + balign() + instruction_end() + + helpers() + + instruction_start_alt() + opcodes(is_alt = True) + balign() + instruction_end_alt() + + footer() + + out.seek(0) + # Squash consequtive empty lines. + text = re.sub(r"(\n\n)(\n)+", r"\1", out.read()) + with open(output_filename, 'w') as output_file: + output_file.write(text) + diff --git a/runtime/interpreter/mterp/config_arm b/runtime/interpreter/mterp/config_arm deleted file mode 100644 index a45efd999ba1c3a6a67af470b6e1d465fd1290c7..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/config_arm +++ /dev/null @@ -1,298 +0,0 @@ -# Copyright (C) 2015 The Android Open Source Project -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -# -# Configuration for ARMv7-A targets. -# - -handler-style computed-goto -handler-size 128 - -# source for alternate entry stub -asm-alt-stub arm/alt_stub.S - -# file header and basic definitions -import arm/header.S - -# arch-specific entry point to interpreter -import arm/entry.S - -# Stub to switch to alternate interpreter -fallback-stub arm/fallback.S - -# opcode list; argument to op-start is default directory -op-start arm - # (override example:) op op_sub_float_2addr arm-vfp - # (fallback example:) op op_sub_float_2addr FALLBACK - - # op op_nop FALLBACK - # op op_move FALLBACK - # op op_move_from16 FALLBACK - # op op_move_16 FALLBACK - # op op_move_wide FALLBACK - # op op_move_wide_from16 FALLBACK - # op op_move_wide_16 FALLBACK - # op op_move_object FALLBACK - # op op_move_object_from16 FALLBACK - # op op_move_object_16 FALLBACK - # op op_move_result FALLBACK - # op op_move_result_wide FALLBACK - # op op_move_result_object FALLBACK - # op op_move_exception FALLBACK - # op op_return_void FALLBACK - # op op_return FALLBACK - # op op_return_wide FALLBACK - # op op_return_object FALLBACK - # op op_const_4 FALLBACK - # op op_const_16 FALLBACK - # op op_const FALLBACK - # op op_const_high16 FALLBACK - # op op_const_wide_16 FALLBACK - # op op_const_wide_32 FALLBACK - # op op_const_wide FALLBACK - # op op_const_wide_high16 FALLBACK - # op op_const_string FALLBACK - # op op_const_string_jumbo FALLBACK - # op op_const_class FALLBACK - # op op_monitor_enter FALLBACK - # op op_monitor_exit FALLBACK - # op op_check_cast FALLBACK - # op op_instance_of FALLBACK - # op op_array_length FALLBACK - # op op_new_instance FALLBACK - # op op_new_array FALLBACK - # op op_filled_new_array FALLBACK - # op op_filled_new_array_range FALLBACK - # op op_fill_array_data FALLBACK - # op op_throw FALLBACK - # op op_goto FALLBACK - # op op_goto_16 FALLBACK - # op op_goto_32 FALLBACK - # op op_packed_switch FALLBACK - # op op_sparse_switch FALLBACK - # op op_cmpl_float FALLBACK - # op op_cmpg_float FALLBACK - # op op_cmpl_double FALLBACK - # op op_cmpg_double FALLBACK - # op op_cmp_long FALLBACK - # op op_if_eq FALLBACK - # op op_if_ne FALLBACK - # op op_if_lt FALLBACK - # op op_if_ge FALLBACK - # op op_if_gt FALLBACK - # op op_if_le FALLBACK - # op op_if_eqz FALLBACK - # op op_if_nez FALLBACK - # op op_if_ltz FALLBACK - # op op_if_gez FALLBACK - # op op_if_gtz FALLBACK - # op op_if_lez FALLBACK - # op op_unused_3e FALLBACK - # op op_unused_3f FALLBACK - # op op_unused_40 FALLBACK - # op op_unused_41 FALLBACK - # op op_unused_42 FALLBACK - # op op_unused_43 FALLBACK - # op op_aget FALLBACK - # op op_aget_wide FALLBACK - # op op_aget_object FALLBACK - # op op_aget_boolean FALLBACK - # op op_aget_byte FALLBACK - # op op_aget_char FALLBACK - # op op_aget_short FALLBACK - # op op_aput FALLBACK - # op op_aput_wide FALLBACK - # op op_aput_object FALLBACK - # op op_aput_boolean FALLBACK - # op op_aput_byte FALLBACK - # op op_aput_char FALLBACK - # op op_aput_short FALLBACK - # op op_iget FALLBACK - # op op_iget_wide FALLBACK - # op op_iget_object FALLBACK - # op op_iget_boolean FALLBACK - # op op_iget_byte FALLBACK - # op op_iget_char FALLBACK - # op op_iget_short FALLBACK - # op op_iput FALLBACK - # op op_iput_wide FALLBACK - # op op_iput_object FALLBACK - # op op_iput_boolean FALLBACK - # op op_iput_byte FALLBACK - # op op_iput_char FALLBACK - # op op_iput_short FALLBACK - # op op_sget FALLBACK - # op op_sget_wide FALLBACK - # op op_sget_object FALLBACK - # op op_sget_boolean FALLBACK - # op op_sget_byte FALLBACK - # op op_sget_char FALLBACK - # op op_sget_short FALLBACK - # op op_sput FALLBACK - # op op_sput_wide FALLBACK - # op op_sput_object FALLBACK - # op op_sput_boolean FALLBACK - # op op_sput_byte FALLBACK - # op op_sput_char FALLBACK - # op op_sput_short FALLBACK - # op op_invoke_virtual FALLBACK - # op op_invoke_super FALLBACK - # op op_invoke_direct FALLBACK - # op op_invoke_static FALLBACK - # op op_invoke_interface FALLBACK - # op op_return_void_no_barrier FALLBACK - # op op_invoke_virtual_range FALLBACK - # op op_invoke_super_range FALLBACK - # op op_invoke_direct_range FALLBACK - # op op_invoke_static_range FALLBACK - # op op_invoke_interface_range FALLBACK - # op op_unused_79 FALLBACK - # op op_unused_7a FALLBACK - # op op_neg_int FALLBACK - # op op_not_int FALLBACK - # op op_neg_long FALLBACK - # op op_not_long FALLBACK - # op op_neg_float FALLBACK - # op op_neg_double FALLBACK - # op op_int_to_long FALLBACK - # op op_int_to_float FALLBACK - # op op_int_to_double FALLBACK - # op op_long_to_int FALLBACK - # op op_long_to_float FALLBACK - # op op_long_to_double FALLBACK - # op op_float_to_int FALLBACK - # op op_float_to_long FALLBACK - # op op_float_to_double FALLBACK - # op op_double_to_int FALLBACK - # op op_double_to_long FALLBACK - # op op_double_to_float FALLBACK - # op op_int_to_byte FALLBACK - # op op_int_to_char FALLBACK - # op op_int_to_short FALLBACK - # op op_add_int FALLBACK - # op op_sub_int FALLBACK - # op op_mul_int FALLBACK - # op op_div_int FALLBACK - # op op_rem_int FALLBACK - # op op_and_int FALLBACK - # op op_or_int FALLBACK - # op op_xor_int FALLBACK - # op op_shl_int FALLBACK - # op op_shr_int FALLBACK - # op op_ushr_int FALLBACK - # op op_add_long FALLBACK - # op op_sub_long FALLBACK - # op op_mul_long FALLBACK - # op op_div_long FALLBACK - # op op_rem_long FALLBACK - # op op_and_long FALLBACK - # op op_or_long FALLBACK - # op op_xor_long FALLBACK - # op op_shl_long FALLBACK - # op op_shr_long FALLBACK - # op op_ushr_long FALLBACK - # op op_add_float FALLBACK - # op op_sub_float FALLBACK - # op op_mul_float FALLBACK - # op op_div_float FALLBACK - # op op_rem_float FALLBACK - # op op_add_double FALLBACK - # op op_sub_double FALLBACK - # op op_mul_double FALLBACK - # op op_div_double FALLBACK - # op op_rem_double FALLBACK - # op op_add_int_2addr FALLBACK - # op op_sub_int_2addr FALLBACK - # op op_mul_int_2addr FALLBACK - # op op_div_int_2addr FALLBACK - # op op_rem_int_2addr FALLBACK - # op op_and_int_2addr FALLBACK - # op op_or_int_2addr FALLBACK - # op op_xor_int_2addr FALLBACK - # op op_shl_int_2addr FALLBACK - # op op_shr_int_2addr FALLBACK - # op op_ushr_int_2addr FALLBACK - # op op_add_long_2addr FALLBACK - # op op_sub_long_2addr FALLBACK - # op op_mul_long_2addr FALLBACK - # op op_div_long_2addr FALLBACK - # op op_rem_long_2addr FALLBACK - # op op_and_long_2addr FALLBACK - # op op_or_long_2addr FALLBACK - # op op_xor_long_2addr FALLBACK - # op op_shl_long_2addr FALLBACK - # op op_shr_long_2addr FALLBACK - # op op_ushr_long_2addr FALLBACK - # op op_add_float_2addr FALLBACK - # op op_sub_float_2addr FALLBACK - # op op_mul_float_2addr FALLBACK - # op op_div_float_2addr FALLBACK - # op op_rem_float_2addr FALLBACK - # op op_add_double_2addr FALLBACK - # op op_sub_double_2addr FALLBACK - # op op_mul_double_2addr FALLBACK - # op op_div_double_2addr FALLBACK - # op op_rem_double_2addr FALLBACK - # op op_add_int_lit16 FALLBACK - # op op_rsub_int FALLBACK - # op op_mul_int_lit16 FALLBACK - # op op_div_int_lit16 FALLBACK - # op op_rem_int_lit16 FALLBACK - # op op_and_int_lit16 FALLBACK - # op op_or_int_lit16 FALLBACK - # op op_xor_int_lit16 FALLBACK - # op op_add_int_lit8 FALLBACK - # op op_rsub_int_lit8 FALLBACK - # op op_mul_int_lit8 FALLBACK - # op op_div_int_lit8 FALLBACK - # op op_rem_int_lit8 FALLBACK - # op op_and_int_lit8 FALLBACK - # op op_or_int_lit8 FALLBACK - # op op_xor_int_lit8 FALLBACK - # op op_shl_int_lit8 FALLBACK - # op op_shr_int_lit8 FALLBACK - # op op_ushr_int_lit8 FALLBACK - # op op_iget_quick FALLBACK - # op op_iget_wide_quick FALLBACK - # op op_iget_object_quick FALLBACK - # op op_iput_quick FALLBACK - # op op_iput_wide_quick FALLBACK - # op op_iput_object_quick FALLBACK - # op op_invoke_virtual_quick FALLBACK - # op op_invoke_virtual_range_quick FALLBACK - # op op_iput_boolean_quick FALLBACK - # op op_iput_byte_quick FALLBACK - # op op_iput_char_quick FALLBACK - # op op_iput_short_quick FALLBACK - # op op_iget_boolean_quick FALLBACK - # op op_iget_byte_quick FALLBACK - # op op_iget_char_quick FALLBACK - # op op_iget_short_quick FALLBACK - # op op_unused_f3 FALLBACK - # op op_unused_f4 FALLBACK - # op op_unused_f5 FALLBACK - # op op_unused_f6 FALLBACK - # op op_unused_f7 FALLBACK - # op op_unused_f8 FALLBACK - # op op_unused_f9 FALLBACK - # op op_invoke_polymorphic FALLBACK - # op op_invoke_polymorphic_range FALLBACK - # op op_invoke_custom FALLBACK - # op op_invoke_custom_range FALLBACK - # op op_const_method_handle FALLBACK - # op op_const_method_type FALLBACK -op-end - -# common subroutines for asm -import arm/footer.S diff --git a/runtime/interpreter/mterp/config_arm64 b/runtime/interpreter/mterp/config_arm64 deleted file mode 100644 index 590363f6e420510b7c7cab163378991d544a08c3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/config_arm64 +++ /dev/null @@ -1,306 +0,0 @@ - -# Copyright (C) 2015 The Android Open Source Project -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -# -# Configuration for ARM64 -# - -handler-style computed-goto -handler-size 128 - -# file header and basic definitions -import arm64/header.S - -# arch-specific entry point to interpreter -import arm64/entry.S - -# Stub to switch to alternate interpreter -fallback-stub arm64/fallback.S - -# opcode list; argument to op-start is default directory -op-start arm64 - # (override example:) op OP_SUB_FLOAT_2ADDR arm-vfp - # (fallback example:) op OP_SUB_FLOAT_2ADDR FALLBACK - - # op op_nop FALLBACK - # op op_move FALLBACK - # op op_move_from16 FALLBACK - # op op_move_16 FALLBACK - # op op_move_wide FALLBACK - # op op_move_wide_from16 FALLBACK - # op op_move_wide_16 FALLBACK - # op op_move_object FALLBACK - # op op_move_object_from16 FALLBACK - # op op_move_object_16 FALLBACK - # op op_move_result FALLBACK - # op op_move_result_wide FALLBACK - # op op_move_result_object FALLBACK - # op op_move_exception FALLBACK - # op op_return_void FALLBACK - # op op_return FALLBACK - # op op_return_wide FALLBACK - # op op_return_object FALLBACK - # op op_const_4 FALLBACK - # op op_const_16 FALLBACK - # op op_const FALLBACK - # op op_const_high16 FALLBACK - # op op_const_wide_16 FALLBACK - # op op_const_wide_32 FALLBACK - # op op_const_wide FALLBACK - # op op_const_wide_high16 FALLBACK - # op op_const_string FALLBACK - # op op_const_string_jumbo FALLBACK - # op op_const_class FALLBACK - # op op_monitor_enter FALLBACK - # op op_monitor_exit FALLBACK - # op op_check_cast FALLBACK - # op op_instance_of FALLBACK - # op op_array_length FALLBACK - # op op_new_instance FALLBACK - # op op_new_array FALLBACK - # op op_filled_new_array FALLBACK - # op op_filled_new_array_range FALLBACK - # op op_fill_array_data FALLBACK - # op op_throw FALLBACK - # op op_goto FALLBACK - # op op_goto_16 FALLBACK - # op op_goto_32 FALLBACK - # op op_packed_switch FALLBACK - # op op_sparse_switch FALLBACK - # op op_cmpl_float FALLBACK - # op op_cmpg_float FALLBACK - # op op_cmpl_double FALLBACK - # op op_cmpg_double FALLBACK - # op op_cmp_long FALLBACK - # op op_if_eq FALLBACK - # op op_if_ne FALLBACK - # op op_if_lt FALLBACK - # op op_if_ge FALLBACK - # op op_if_gt FALLBACK - # op op_if_le FALLBACK - # op op_if_eqz FALLBACK - # op op_if_nez FALLBACK - # op op_if_ltz FALLBACK - # op op_if_gez FALLBACK - # op op_if_gtz FALLBACK - # op op_if_lez FALLBACK - # op op_unused_3e FALLBACK - # op op_unused_3f FALLBACK - # op op_unused_40 FALLBACK - # op op_unused_41 FALLBACK - # op op_unused_42 FALLBACK - # op op_unused_43 FALLBACK - # op op_aget FALLBACK - # op op_aget_wide FALLBACK - # op op_aget_object FALLBACK - # op op_aget_boolean FALLBACK - # op op_aget_byte FALLBACK - # op op_aget_char FALLBACK - # op op_aget_short FALLBACK - # op op_aput FALLBACK - # op op_aput_wide FALLBACK - # op op_aput_object FALLBACK - # op op_aput_boolean FALLBACK - # op op_aput_byte FALLBACK - # op op_aput_char FALLBACK - # op op_aput_short FALLBACK - # op op_iget FALLBACK - # op op_iget_wide FALLBACK - # op op_iget_object FALLBACK - # op op_iget_boolean FALLBACK - # op op_iget_byte FALLBACK - # op op_iget_char FALLBACK - # op op_iget_short FALLBACK - # op op_iput FALLBACK - # op op_iput_wide FALLBACK - # op op_iput_object FALLBACK - # op op_iput_boolean FALLBACK - # op op_iput_byte FALLBACK - # op op_iput_char FALLBACK - # op op_iput_short FALLBACK - # op op_sget FALLBACK - # op op_sget_wide FALLBACK - # op op_sget_object FALLBACK - # op op_sget_boolean FALLBACK - # op op_sget_byte FALLBACK - # op op_sget_char FALLBACK - # op op_sget_short FALLBACK - # op op_sput FALLBACK - # op op_sput_wide FALLBACK - # op op_sput_object FALLBACK - # op op_sput_boolean FALLBACK - # op op_sput_byte FALLBACK - # op op_sput_char FALLBACK - # op op_sput_short FALLBACK - # op op_invoke_virtual FALLBACK - # op op_invoke_super FALLBACK - # op op_invoke_direct FALLBACK - # op op_invoke_static FALLBACK - # op op_invoke_interface FALLBACK - # op op_return_void_no_barrier FALLBACK - # op op_invoke_virtual_range FALLBACK - # op op_invoke_super_range FALLBACK - # op op_invoke_direct_range FALLBACK - # op op_invoke_static_range FALLBACK - # op op_invoke_interface_range FALLBACK - # op op_unused_79 FALLBACK - # op op_unused_7a FALLBACK - # op op_neg_int FALLBACK - # op op_not_int FALLBACK - # op op_neg_long FALLBACK - # op op_not_long FALLBACK - # op op_neg_float FALLBACK - # op op_neg_double FALLBACK - # op op_int_to_long FALLBACK - # op op_int_to_float FALLBACK - # op op_int_to_double FALLBACK - # op op_long_to_int FALLBACK - # op op_long_to_float FALLBACK - # op op_long_to_double FALLBACK - # op op_float_to_int FALLBACK - # op op_float_to_long FALLBACK - # op op_float_to_double FALLBACK - # op op_double_to_int FALLBACK - # op op_double_to_long FALLBACK - # op op_double_to_float FALLBACK - # op op_int_to_byte FALLBACK - # op op_int_to_char FALLBACK - # op op_int_to_short FALLBACK - # op op_add_int FALLBACK - # op op_sub_int FALLBACK - # op op_mul_int FALLBACK - # op op_div_int FALLBACK - # op op_rem_int FALLBACK - # op op_and_int FALLBACK - # op op_or_int FALLBACK - # op op_xor_int FALLBACK - # op op_shl_int FALLBACK - # op op_shr_int FALLBACK - # op op_ushr_int FALLBACK - # op op_add_long FALLBACK - # op op_sub_long FALLBACK - # op op_mul_long FALLBACK - # op op_div_long FALLBACK - # op op_rem_long FALLBACK - # op op_and_long FALLBACK - # op op_or_long FALLBACK - # op op_xor_long FALLBACK - # op op_shl_long FALLBACK - # op op_shr_long FALLBACK - # op op_ushr_long FALLBACK - # op op_add_float FALLBACK - # op op_sub_float FALLBACK - # op op_mul_float FALLBACK - # op op_div_float FALLBACK - # op op_rem_float FALLBACK - # op op_add_double FALLBACK - # op op_sub_double FALLBACK - # op op_mul_double FALLBACK - # op op_div_double FALLBACK - # op op_rem_double FALLBACK - # op op_add_int_2addr FALLBACK - # op op_sub_int_2addr FALLBACK - # op op_mul_int_2addr FALLBACK - # op op_div_int_2addr FALLBACK - # op op_rem_int_2addr FALLBACK - # op op_and_int_2addr FALLBACK - # op op_or_int_2addr FALLBACK - # op op_xor_int_2addr FALLBACK - # op op_shl_int_2addr FALLBACK - # op op_shr_int_2addr FALLBACK - # op op_ushr_int_2addr FALLBACK - # op op_add_long_2addr FALLBACK - # op op_sub_long_2addr FALLBACK - # op op_mul_long_2addr FALLBACK - # op op_div_long_2addr FALLBACK - # op op_rem_long_2addr FALLBACK - # op op_and_long_2addr FALLBACK - # op op_or_long_2addr FALLBACK - # op op_xor_long_2addr FALLBACK - # op op_shl_long_2addr FALLBACK - # op op_shr_long_2addr FALLBACK - # op op_ushr_long_2addr FALLBACK - # op op_add_float_2addr FALLBACK - # op op_sub_float_2addr FALLBACK - # op op_mul_float_2addr FALLBACK - # op op_div_float_2addr FALLBACK - # op op_rem_float_2addr FALLBACK - # op op_add_double_2addr FALLBACK - # op op_sub_double_2addr FALLBACK - # op op_mul_double_2addr FALLBACK - # op op_div_double_2addr FALLBACK - # op op_rem_double_2addr FALLBACK - # op op_add_int_lit16 FALLBACK - # op op_rsub_int FALLBACK - # op op_mul_int_lit16 FALLBACK - # op op_div_int_lit16 FALLBACK - # op op_rem_int_lit16 FALLBACK - # op op_and_int_lit16 FALLBACK - # op op_or_int_lit16 FALLBACK - # op op_xor_int_lit16 FALLBACK - # op op_add_int_lit8 FALLBACK - # op op_rsub_int_lit8 FALLBACK - # op op_mul_int_lit8 FALLBACK - # op op_div_int_lit8 FALLBACK - # op op_rem_int_lit8 FALLBACK - # op op_and_int_lit8 FALLBACK - # op op_or_int_lit8 FALLBACK - # op op_xor_int_lit8 FALLBACK - # op op_shl_int_lit8 FALLBACK - # op op_shr_int_lit8 FALLBACK - # op op_ushr_int_lit8 FALLBACK - # op op_iget_quick FALLBACK - # op op_iget_wide_quick FALLBACK - # op op_iget_object_quick FALLBACK - # op op_iput_quick FALLBACK - # op op_iput_wide_quick FALLBACK - # op op_iput_object_quick FALLBACK - # op op_invoke_virtual_quick FALLBACK - # op op_invoke_virtual_range_quick FALLBACK - # op op_iput_boolean_quick FALLBACK - # op op_iput_byte_quick FALLBACK - # op op_iput_char_quick FALLBACK - # op op_iput_short_quick FALLBACK - # op op_iget_boolean_quick FALLBACK - # op op_iget_byte_quick FALLBACK - # op op_iget_char_quick FALLBACK - # op op_iget_short_quick FALLBACK - # op op_unused_f3 FALLBACK - # op op_unused_f4 FALLBACK - # op op_unused_f5 FALLBACK - # op op_unused_f6 FALLBACK - # op op_unused_f7 FALLBACK - # op op_unused_f8 FALLBACK - # op op_unused_f9 FALLBACK - # op op_invoke_polymorphic FALLBACK - # op op_invoke_polymorphic_range FALLBACK - # op op_invoke_custom FALLBACK - # op op_invoke_custom_range FALLBACK - # op op_const_method_handle FALLBACK - # op op_const_method_type FALLBACK -op-end - -# common subroutines for asm; we emit the footer before alternate -# entry stubs, so that TBZ/TBNZ from ops can reach targets in footer -import arm64/footer.S - -# source for alternate entry stub -asm-alt-stub arm64/alt_stub.S - -# emit alternate entry stubs -alt-ops - -# finish by closing .cfi info -import arm64/close_cfi.S diff --git a/runtime/interpreter/mterp/config_mips b/runtime/interpreter/mterp/config_mips deleted file mode 100644 index d6173daf2ccd62e50e77d591fbbc4468530220cb..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/config_mips +++ /dev/null @@ -1,298 +0,0 @@ -# Copyright (C) 2016 The Android Open Source Project -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -# -# Configuration for MIPS_32 targets. -# - -handler-style computed-goto -handler-size 128 - -# source for alternate entry stub -asm-alt-stub mips/alt_stub.S - -# file header and basic definitions -import mips/header.S - -# arch-specific entry point to interpreter -import mips/entry.S - -# Stub to switch to alternate interpreter -fallback-stub mips/fallback.S - -# opcode list; argument to op-start is default directory -op-start mips - # (override example:) op op_sub_float_2addr arm-vfp - # (fallback example:) op op_sub_float_2addr FALLBACK - - # op op_nop FALLBACK - # op op_move FALLBACK - # op op_move_from16 FALLBACK - # op op_move_16 FALLBACK - # op op_move_wide FALLBACK - # op op_move_wide_from16 FALLBACK - # op op_move_wide_16 FALLBACK - # op op_move_object FALLBACK - # op op_move_object_from16 FALLBACK - # op op_move_object_16 FALLBACK - # op op_move_result FALLBACK - # op op_move_result_wide FALLBACK - # op op_move_result_object FALLBACK - # op op_move_exception FALLBACK - # op op_return_void FALLBACK - # op op_return FALLBACK - # op op_return_wide FALLBACK - # op op_return_object FALLBACK - # op op_const_4 FALLBACK - # op op_const_16 FALLBACK - # op op_const FALLBACK - # op op_const_high16 FALLBACK - # op op_const_wide_16 FALLBACK - # op op_const_wide_32 FALLBACK - # op op_const_wide FALLBACK - # op op_const_wide_high16 FALLBACK - # op op_const_string FALLBACK - # op op_const_string_jumbo FALLBACK - # op op_const_class FALLBACK - # op op_monitor_enter FALLBACK - # op op_monitor_exit FALLBACK - # op op_check_cast FALLBACK - # op op_instance_of FALLBACK - # op op_array_length FALLBACK - # op op_new_instance FALLBACK - # op op_new_array FALLBACK - # op op_filled_new_array FALLBACK - # op op_filled_new_array_range FALLBACK - # op op_fill_array_data FALLBACK - # op op_throw FALLBACK - # op op_goto FALLBACK - # op op_goto_16 FALLBACK - # op op_goto_32 FALLBACK - # op op_packed_switch FALLBACK - # op op_sparse_switch FALLBACK - # op op_cmpl_float FALLBACK - # op op_cmpg_float FALLBACK - # op op_cmpl_double FALLBACK - # op op_cmpg_double FALLBACK - # op op_cmp_long FALLBACK - # op op_if_eq FALLBACK - # op op_if_ne FALLBACK - # op op_if_lt FALLBACK - # op op_if_ge FALLBACK - # op op_if_gt FALLBACK - # op op_if_le FALLBACK - # op op_if_eqz FALLBACK - # op op_if_nez FALLBACK - # op op_if_ltz FALLBACK - # op op_if_gez FALLBACK - # op op_if_gtz FALLBACK - # op op_if_lez FALLBACK - # op op_unused_3e FALLBACK - # op op_unused_3f FALLBACK - # op op_unused_40 FALLBACK - # op op_unused_41 FALLBACK - # op op_unused_42 FALLBACK - # op op_unused_43 FALLBACK - # op op_aget FALLBACK - # op op_aget_wide FALLBACK - # op op_aget_object FALLBACK - # op op_aget_boolean FALLBACK - # op op_aget_byte FALLBACK - # op op_aget_char FALLBACK - # op op_aget_short FALLBACK - # op op_aput FALLBACK - # op op_aput_wide FALLBACK - # op op_aput_object FALLBACK - # op op_aput_boolean FALLBACK - # op op_aput_byte FALLBACK - # op op_aput_char FALLBACK - # op op_aput_short FALLBACK - # op op_iget FALLBACK - # op op_iget_wide FALLBACK - # op op_iget_object FALLBACK - # op op_iget_boolean FALLBACK - # op op_iget_byte FALLBACK - # op op_iget_char FALLBACK - # op op_iget_short FALLBACK - # op op_iput FALLBACK - # op op_iput_wide FALLBACK - # op op_iput_object FALLBACK - # op op_iput_boolean FALLBACK - # op op_iput_byte FALLBACK - # op op_iput_char FALLBACK - # op op_iput_short FALLBACK - # op op_sget FALLBACK - # op op_sget_wide FALLBACK - # op op_sget_object FALLBACK - # op op_sget_boolean FALLBACK - # op op_sget_byte FALLBACK - # op op_sget_char FALLBACK - # op op_sget_short FALLBACK - # op op_sput FALLBACK - # op op_sput_wide FALLBACK - # op op_sput_object FALLBACK - # op op_sput_boolean FALLBACK - # op op_sput_byte FALLBACK - # op op_sput_char FALLBACK - # op op_sput_short FALLBACK - # op op_invoke_virtual FALLBACK - # op op_invoke_super FALLBACK - # op op_invoke_direct FALLBACK - # op op_invoke_static FALLBACK - # op op_invoke_interface FALLBACK - # op op_return_void_no_barrier FALLBACK - # op op_invoke_virtual_range FALLBACK - # op op_invoke_super_range FALLBACK - # op op_invoke_direct_range FALLBACK - # op op_invoke_static_range FALLBACK - # op op_invoke_interface_range FALLBACK - # op op_unused_79 FALLBACK - # op op_unused_7a FALLBACK - # op op_neg_int FALLBACK - # op op_not_int FALLBACK - # op op_neg_long FALLBACK - # op op_not_long FALLBACK - # op op_neg_float FALLBACK - # op op_neg_double FALLBACK - # op op_int_to_long FALLBACK - # op op_int_to_float FALLBACK - # op op_int_to_double FALLBACK - # op op_long_to_int FALLBACK - # op op_long_to_float FALLBACK - # op op_long_to_double FALLBACK - # op op_float_to_int FALLBACK - # op op_float_to_long FALLBACK - # op op_float_to_double FALLBACK - # op op_double_to_int FALLBACK - # op op_double_to_long FALLBACK - # op op_double_to_float FALLBACK - # op op_int_to_byte FALLBACK - # op op_int_to_char FALLBACK - # op op_int_to_short FALLBACK - # op op_add_int FALLBACK - # op op_sub_int FALLBACK - # op op_mul_int FALLBACK - # op op_div_int FALLBACK - # op op_rem_int FALLBACK - # op op_and_int FALLBACK - # op op_or_int FALLBACK - # op op_xor_int FALLBACK - # op op_shl_int FALLBACK - # op op_shr_int FALLBACK - # op op_ushr_int FALLBACK - # op op_add_long FALLBACK - # op op_sub_long FALLBACK - # op op_mul_long FALLBACK - # op op_div_long FALLBACK - # op op_rem_long FALLBACK - # op op_and_long FALLBACK - # op op_or_long FALLBACK - # op op_xor_long FALLBACK - # op op_shl_long FALLBACK - # op op_shr_long FALLBACK - # op op_ushr_long FALLBACK - # op op_add_float FALLBACK - # op op_sub_float FALLBACK - # op op_mul_float FALLBACK - # op op_div_float FALLBACK - # op op_rem_float FALLBACK - # op op_add_double FALLBACK - # op op_sub_double FALLBACK - # op op_mul_double FALLBACK - # op op_div_double FALLBACK - # op op_rem_double FALLBACK - # op op_add_int_2addr FALLBACK - # op op_sub_int_2addr FALLBACK - # op op_mul_int_2addr FALLBACK - # op op_div_int_2addr FALLBACK - # op op_rem_int_2addr FALLBACK - # op op_and_int_2addr FALLBACK - # op op_or_int_2addr FALLBACK - # op op_xor_int_2addr FALLBACK - # op op_shl_int_2addr FALLBACK - # op op_shr_int_2addr FALLBACK - # op op_ushr_int_2addr FALLBACK - # op op_add_long_2addr FALLBACK - # op op_sub_long_2addr FALLBACK - # op op_mul_long_2addr FALLBACK - # op op_div_long_2addr FALLBACK - # op op_rem_long_2addr FALLBACK - # op op_and_long_2addr FALLBACK - # op op_or_long_2addr FALLBACK - # op op_xor_long_2addr FALLBACK - # op op_shl_long_2addr FALLBACK - # op op_shr_long_2addr FALLBACK - # op op_ushr_long_2addr FALLBACK - # op op_add_float_2addr FALLBACK - # op op_sub_float_2addr FALLBACK - # op op_mul_float_2addr FALLBACK - # op op_div_float_2addr FALLBACK - # op op_rem_float_2addr FALLBACK - # op op_add_double_2addr FALLBACK - # op op_sub_double_2addr FALLBACK - # op op_mul_double_2addr FALLBACK - # op op_div_double_2addr FALLBACK - # op op_rem_double_2addr FALLBACK - # op op_add_int_lit16 FALLBACK - # op op_rsub_int FALLBACK - # op op_mul_int_lit16 FALLBACK - # op op_div_int_lit16 FALLBACK - # op op_rem_int_lit16 FALLBACK - # op op_and_int_lit16 FALLBACK - # op op_or_int_lit16 FALLBACK - # op op_xor_int_lit16 FALLBACK - # op op_add_int_lit8 FALLBACK - # op op_rsub_int_lit8 FALLBACK - # op op_mul_int_lit8 FALLBACK - # op op_div_int_lit8 FALLBACK - # op op_rem_int_lit8 FALLBACK - # op op_and_int_lit8 FALLBACK - # op op_or_int_lit8 FALLBACK - # op op_xor_int_lit8 FALLBACK - # op op_shl_int_lit8 FALLBACK - # op op_shr_int_lit8 FALLBACK - # op op_ushr_int_lit8 FALLBACK - # op op_iget_quick FALLBACK - # op op_iget_wide_quick FALLBACK - # op op_iget_object_quick FALLBACK - # op op_iput_quick FALLBACK - # op op_iput_wide_quick FALLBACK - # op op_iput_object_quick FALLBACK - # op op_invoke_virtual_quick FALLBACK - # op op_invoke_virtual_range_quick FALLBACK - # op op_iput_boolean_quick FALLBACK - # op op_iput_byte_quick FALLBACK - # op op_iput_char_quick FALLBACK - # op op_iput_short_quick FALLBACK - # op op_iget_boolean_quick FALLBACK - # op op_iget_byte_quick FALLBACK - # op op_iget_char_quick FALLBACK - # op op_iget_short_quick FALLBACK - # op op_unused_f3 FALLBACK - # op op_unused_f4 FALLBACK - # op op_unused_f5 FALLBACK - # op op_unused_f6 FALLBACK - # op op_unused_f7 FALLBACK - # op op_unused_f8 FALLBACK - # op op_unused_f9 FALLBACK - # op op_invoke_polymorphic FALLBACK - # op op_invoke_polymorphic_range FALLBACK - # op op_invoke_custom FALLBACK - # op op_invoke_custom_range FALLBACK - # op op_const_method_handle FALLBACK - # op op_const_method_type FALLBACK -op-end - -# common subroutines for asm -import mips/footer.S diff --git a/runtime/interpreter/mterp/config_mips64 b/runtime/interpreter/mterp/config_mips64 deleted file mode 100644 index a9bf362ec3f9daa594d17abaa07ed1069b2d9c9a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/config_mips64 +++ /dev/null @@ -1,298 +0,0 @@ -# Copyright (C) 2015 The Android Open Source Project -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -# -# Configuration for MIPS_64 -# - -handler-style computed-goto -handler-size 128 - -# source for alternate entry stub -asm-alt-stub mips64/alt_stub.S - -# file header and basic definitions -import mips64/header.S - -# arch-specific entry point to interpreter -import mips64/entry.S - -# Stub to switch to alternate interpreter -fallback-stub mips64/fallback.S - -# opcode list; argument to op-start is default directory -op-start mips64 - # (override example:) op OP_SUB_FLOAT_2ADDR arm-vfp - # (fallback example:) op OP_SUB_FLOAT_2ADDR FALLBACK - - # op op_nop FALLBACK - # op op_move FALLBACK - # op op_move_from16 FALLBACK - # op op_move_16 FALLBACK - # op op_move_wide FALLBACK - # op op_move_wide_from16 FALLBACK - # op op_move_wide_16 FALLBACK - # op op_move_object FALLBACK - # op op_move_object_from16 FALLBACK - # op op_move_object_16 FALLBACK - # op op_move_result FALLBACK - # op op_move_result_wide FALLBACK - # op op_move_result_object FALLBACK - # op op_move_exception FALLBACK - # op op_return_void FALLBACK - # op op_return FALLBACK - # op op_return_wide FALLBACK - # op op_return_object FALLBACK - # op op_const_4 FALLBACK - # op op_const_16 FALLBACK - # op op_const FALLBACK - # op op_const_high16 FALLBACK - # op op_const_wide_16 FALLBACK - # op op_const_wide_32 FALLBACK - # op op_const_wide FALLBACK - # op op_const_wide_high16 FALLBACK - # op op_const_string FALLBACK - # op op_const_string_jumbo FALLBACK - # op op_const_class FALLBACK - # op op_monitor_enter FALLBACK - # op op_monitor_exit FALLBACK - # op op_check_cast FALLBACK - # op op_instance_of FALLBACK - # op op_array_length FALLBACK - # op op_new_instance FALLBACK - # op op_new_array FALLBACK - # op op_filled_new_array FALLBACK - # op op_filled_new_array_range FALLBACK - # op op_fill_array_data FALLBACK - # op op_throw FALLBACK - # op op_goto FALLBACK - # op op_goto_16 FALLBACK - # op op_goto_32 FALLBACK - # op op_packed_switch FALLBACK - # op op_sparse_switch FALLBACK - # op op_cmpl_float FALLBACK - # op op_cmpg_float FALLBACK - # op op_cmpl_double FALLBACK - # op op_cmpg_double FALLBACK - # op op_cmp_long FALLBACK - # op op_if_eq FALLBACK - # op op_if_ne FALLBACK - # op op_if_lt FALLBACK - # op op_if_ge FALLBACK - # op op_if_gt FALLBACK - # op op_if_le FALLBACK - # op op_if_eqz FALLBACK - # op op_if_nez FALLBACK - # op op_if_ltz FALLBACK - # op op_if_gez FALLBACK - # op op_if_gtz FALLBACK - # op op_if_lez FALLBACK - # op op_unused_3e FALLBACK - # op op_unused_3f FALLBACK - # op op_unused_40 FALLBACK - # op op_unused_41 FALLBACK - # op op_unused_42 FALLBACK - # op op_unused_43 FALLBACK - # op op_aget FALLBACK - # op op_aget_wide FALLBACK - # op op_aget_object FALLBACK - # op op_aget_boolean FALLBACK - # op op_aget_byte FALLBACK - # op op_aget_char FALLBACK - # op op_aget_short FALLBACK - # op op_aput FALLBACK - # op op_aput_wide FALLBACK - # op op_aput_object FALLBACK - # op op_aput_boolean FALLBACK - # op op_aput_byte FALLBACK - # op op_aput_char FALLBACK - # op op_aput_short FALLBACK - # op op_iget FALLBACK - # op op_iget_wide FALLBACK - # op op_iget_object FALLBACK - # op op_iget_boolean FALLBACK - # op op_iget_byte FALLBACK - # op op_iget_char FALLBACK - # op op_iget_short FALLBACK - # op op_iput FALLBACK - # op op_iput_wide FALLBACK - # op op_iput_object FALLBACK - # op op_iput_boolean FALLBACK - # op op_iput_byte FALLBACK - # op op_iput_char FALLBACK - # op op_iput_short FALLBACK - # op op_sget FALLBACK - # op op_sget_wide FALLBACK - # op op_sget_object FALLBACK - # op op_sget_boolean FALLBACK - # op op_sget_byte FALLBACK - # op op_sget_char FALLBACK - # op op_sget_short FALLBACK - # op op_sput FALLBACK - # op op_sput_wide FALLBACK - # op op_sput_object FALLBACK - # op op_sput_boolean FALLBACK - # op op_sput_byte FALLBACK - # op op_sput_char FALLBACK - # op op_sput_short FALLBACK - # op op_invoke_virtual FALLBACK - # op op_invoke_super FALLBACK - # op op_invoke_direct FALLBACK - # op op_invoke_static FALLBACK - # op op_invoke_interface FALLBACK - # op op_return_void_no_barrier FALLBACK - # op op_invoke_virtual_range FALLBACK - # op op_invoke_super_range FALLBACK - # op op_invoke_direct_range FALLBACK - # op op_invoke_static_range FALLBACK - # op op_invoke_interface_range FALLBACK - # op op_unused_79 FALLBACK - # op op_unused_7a FALLBACK - # op op_neg_int FALLBACK - # op op_not_int FALLBACK - # op op_neg_long FALLBACK - # op op_not_long FALLBACK - # op op_neg_float FALLBACK - # op op_neg_double FALLBACK - # op op_int_to_long FALLBACK - # op op_int_to_float FALLBACK - # op op_int_to_double FALLBACK - # op op_long_to_int FALLBACK - # op op_long_to_float FALLBACK - # op op_long_to_double FALLBACK - # op op_float_to_int FALLBACK - # op op_float_to_long FALLBACK - # op op_float_to_double FALLBACK - # op op_double_to_int FALLBACK - # op op_double_to_long FALLBACK - # op op_double_to_float FALLBACK - # op op_int_to_byte FALLBACK - # op op_int_to_char FALLBACK - # op op_int_to_short FALLBACK - # op op_add_int FALLBACK - # op op_sub_int FALLBACK - # op op_mul_int FALLBACK - # op op_div_int FALLBACK - # op op_rem_int FALLBACK - # op op_and_int FALLBACK - # op op_or_int FALLBACK - # op op_xor_int FALLBACK - # op op_shl_int FALLBACK - # op op_shr_int FALLBACK - # op op_ushr_int FALLBACK - # op op_add_long FALLBACK - # op op_sub_long FALLBACK - # op op_mul_long FALLBACK - # op op_div_long FALLBACK - # op op_rem_long FALLBACK - # op op_and_long FALLBACK - # op op_or_long FALLBACK - # op op_xor_long FALLBACK - # op op_shl_long FALLBACK - # op op_shr_long FALLBACK - # op op_ushr_long FALLBACK - # op op_add_float FALLBACK - # op op_sub_float FALLBACK - # op op_mul_float FALLBACK - # op op_div_float FALLBACK - # op op_rem_float FALLBACK - # op op_add_double FALLBACK - # op op_sub_double FALLBACK - # op op_mul_double FALLBACK - # op op_div_double FALLBACK - # op op_rem_double FALLBACK - # op op_add_int_2addr FALLBACK - # op op_sub_int_2addr FALLBACK - # op op_mul_int_2addr FALLBACK - # op op_div_int_2addr FALLBACK - # op op_rem_int_2addr FALLBACK - # op op_and_int_2addr FALLBACK - # op op_or_int_2addr FALLBACK - # op op_xor_int_2addr FALLBACK - # op op_shl_int_2addr FALLBACK - # op op_shr_int_2addr FALLBACK - # op op_ushr_int_2addr FALLBACK - # op op_add_long_2addr FALLBACK - # op op_sub_long_2addr FALLBACK - # op op_mul_long_2addr FALLBACK - # op op_div_long_2addr FALLBACK - # op op_rem_long_2addr FALLBACK - # op op_and_long_2addr FALLBACK - # op op_or_long_2addr FALLBACK - # op op_xor_long_2addr FALLBACK - # op op_shl_long_2addr FALLBACK - # op op_shr_long_2addr FALLBACK - # op op_ushr_long_2addr FALLBACK - # op op_add_float_2addr FALLBACK - # op op_sub_float_2addr FALLBACK - # op op_mul_float_2addr FALLBACK - # op op_div_float_2addr FALLBACK - # op op_rem_float_2addr FALLBACK - # op op_add_double_2addr FALLBACK - # op op_sub_double_2addr FALLBACK - # op op_mul_double_2addr FALLBACK - # op op_div_double_2addr FALLBACK - # op op_rem_double_2addr FALLBACK - # op op_add_int_lit16 FALLBACK - # op op_rsub_int FALLBACK - # op op_mul_int_lit16 FALLBACK - # op op_div_int_lit16 FALLBACK - # op op_rem_int_lit16 FALLBACK - # op op_and_int_lit16 FALLBACK - # op op_or_int_lit16 FALLBACK - # op op_xor_int_lit16 FALLBACK - # op op_add_int_lit8 FALLBACK - # op op_rsub_int_lit8 FALLBACK - # op op_mul_int_lit8 FALLBACK - # op op_div_int_lit8 FALLBACK - # op op_rem_int_lit8 FALLBACK - # op op_and_int_lit8 FALLBACK - # op op_or_int_lit8 FALLBACK - # op op_xor_int_lit8 FALLBACK - # op op_shl_int_lit8 FALLBACK - # op op_shr_int_lit8 FALLBACK - # op op_ushr_int_lit8 FALLBACK - # op op_iget_quick FALLBACK - # op op_iget_wide_quick FALLBACK - # op op_iget_object_quick FALLBACK - # op op_iput_quick FALLBACK - # op op_iput_wide_quick FALLBACK - # op op_iput_object_quick FALLBACK - # op op_invoke_virtual_quick FALLBACK - # op op_invoke_virtual_range_quick FALLBACK - # op op_iput_boolean_quick FALLBACK - # op op_iput_byte_quick FALLBACK - # op op_iput_char_quick FALLBACK - # op op_iput_short_quick FALLBACK - # op op_iget_boolean_quick FALLBACK - # op op_iget_byte_quick FALLBACK - # op op_iget_char_quick FALLBACK - # op op_iget_short_quick FALLBACK - # op op_unused_f3 FALLBACK - # op op_unused_f4 FALLBACK - # op op_unused_f5 FALLBACK - # op op_unused_f6 FALLBACK - # op op_unused_f7 FALLBACK - # op op_unused_f8 FALLBACK - # op op_unused_f9 FALLBACK - # op op_invoke_polymorphic FALLBACK - # op op_invoke_polymorphic_range FALLBACK - # op op_invoke_custom FALLBACK - # op op_invoke_custom_range FALLBACK - # op op_const_method_handle FALLBACK - # op op_const_method_type FALLBACK -op-end - -# common subroutines for asm -import mips64/footer.S diff --git a/runtime/interpreter/mterp/config_x86 b/runtime/interpreter/mterp/config_x86 deleted file mode 100644 index 2417851c11bc14c7a530a6726c43dbfd63b12147..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/config_x86 +++ /dev/null @@ -1,302 +0,0 @@ -# Copyright (C) 2015 The Android Open Source Project -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -# -# Configuration for X86 -# - -handler-style computed-goto -handler-size 128 - -function-type-format FUNCTION_TYPE(%s) -function-size-format SIZE(%s,%s) -global-name-format SYMBOL(%s) - -# source for alternate entry stub -asm-alt-stub x86/alt_stub.S - -# file header and basic definitions -import x86/header.S - -# arch-specific entry point to interpreter -import x86/entry.S - -# Stub to switch to alternate interpreter -fallback-stub x86/fallback.S - -# opcode list; argument to op-start is default directory -op-start x86 - # (override example:) op OP_SUB_FLOAT_2ADDR arm-vfp - # (fallback example:) op OP_SUB_FLOAT_2ADDR FALLBACK - - # op op_nop FALLBACK - # op op_move FALLBACK - # op op_move_from16 FALLBACK - # op op_move_16 FALLBACK - # op op_move_wide FALLBACK - # op op_move_wide_from16 FALLBACK - # op op_move_wide_16 FALLBACK - # op op_move_object FALLBACK - # op op_move_object_from16 FALLBACK - # op op_move_object_16 FALLBACK - # op op_move_result FALLBACK - # op op_move_result_wide FALLBACK - # op op_move_result_object FALLBACK - # op op_move_exception FALLBACK - # op op_return_void FALLBACK - # op op_return FALLBACK - # op op_return_wide FALLBACK - # op op_return_object FALLBACK - # op op_const_4 FALLBACK - # op op_const_16 FALLBACK - # op op_const FALLBACK - # op op_const_high16 FALLBACK - # op op_const_wide_16 FALLBACK - # op op_const_wide_32 FALLBACK - # op op_const_wide FALLBACK - # op op_const_wide_high16 FALLBACK - # op op_const_string FALLBACK - # op op_const_string_jumbo FALLBACK - # op op_const_class FALLBACK - # op op_monitor_enter FALLBACK - # op op_monitor_exit FALLBACK - # op op_check_cast FALLBACK - # op op_instance_of FALLBACK - # op op_array_length FALLBACK - # op op_new_instance FALLBACK - # op op_new_array FALLBACK - # op op_filled_new_array FALLBACK - # op op_filled_new_array_range FALLBACK - # op op_fill_array_data FALLBACK - # op op_throw FALLBACK - # op op_goto FALLBACK - # op op_goto_16 FALLBACK - # op op_goto_32 FALLBACK - # op op_packed_switch FALLBACK - # op op_sparse_switch FALLBACK - # op op_cmpl_float FALLBACK - # op op_cmpg_float FALLBACK - # op op_cmpl_double FALLBACK - # op op_cmpg_double FALLBACK - # op op_cmp_long FALLBACK - # op op_if_eq FALLBACK - # op op_if_ne FALLBACK - # op op_if_lt FALLBACK - # op op_if_ge FALLBACK - # op op_if_gt FALLBACK - # op op_if_le FALLBACK - # op op_if_eqz FALLBACK - # op op_if_nez FALLBACK - # op op_if_ltz FALLBACK - # op op_if_gez FALLBACK - # op op_if_gtz FALLBACK - # op op_if_lez FALLBACK - # op op_unused_3e FALLBACK - # op op_unused_3f FALLBACK - # op op_unused_40 FALLBACK - # op op_unused_41 FALLBACK - # op op_unused_42 FALLBACK - # op op_unused_43 FALLBACK - # op op_aget FALLBACK - # op op_aget_wide FALLBACK - # op op_aget_object FALLBACK - # op op_aget_boolean FALLBACK - # op op_aget_byte FALLBACK - # op op_aget_char FALLBACK - # op op_aget_short FALLBACK - # op op_aput FALLBACK - # op op_aput_wide FALLBACK - # op op_aput_object FALLBACK - # op op_aput_boolean FALLBACK - # op op_aput_byte FALLBACK - # op op_aput_char FALLBACK - # op op_aput_short FALLBACK - # op op_iget FALLBACK - # op op_iget_wide FALLBACK - # op op_iget_object FALLBACK - # op op_iget_boolean FALLBACK - # op op_iget_byte FALLBACK - # op op_iget_char FALLBACK - # op op_iget_short FALLBACK - # op op_iput FALLBACK - # op op_iput_wide FALLBACK - # op op_iput_object FALLBACK - # op op_iput_boolean FALLBACK - # op op_iput_byte FALLBACK - # op op_iput_char FALLBACK - # op op_iput_short FALLBACK - # op op_sget FALLBACK - # op op_sget_wide FALLBACK - # op op_sget_object FALLBACK - # op op_sget_boolean FALLBACK - # op op_sget_byte FALLBACK - # op op_sget_char FALLBACK - # op op_sget_short FALLBACK - # op op_sput FALLBACK - # op op_sput_wide FALLBACK - # op op_sput_object FALLBACK - # op op_sput_boolean FALLBACK - # op op_sput_byte FALLBACK - # op op_sput_char FALLBACK - # op op_sput_short FALLBACK - # op op_invoke_virtual FALLBACK - # op op_invoke_super FALLBACK - # op op_invoke_direct FALLBACK - # op op_invoke_static FALLBACK - # op op_invoke_interface FALLBACK - # op op_return_void_no_barrier FALLBACK - # op op_invoke_virtual_range FALLBACK - # op op_invoke_super_range FALLBACK - # op op_invoke_direct_range FALLBACK - # op op_invoke_static_range FALLBACK - # op op_invoke_interface_range FALLBACK - # op op_unused_79 FALLBACK - # op op_unused_7a FALLBACK - # op op_neg_int FALLBACK - # op op_not_int FALLBACK - # op op_neg_long FALLBACK - # op op_not_long FALLBACK - # op op_neg_float FALLBACK - # op op_neg_double FALLBACK - # op op_int_to_long FALLBACK - # op op_int_to_float FALLBACK - # op op_int_to_double FALLBACK - # op op_long_to_int FALLBACK - # op op_long_to_float FALLBACK - # op op_long_to_double FALLBACK - # op op_float_to_int FALLBACK - # op op_float_to_long FALLBACK - # op op_float_to_double FALLBACK - # op op_double_to_int FALLBACK - # op op_double_to_long FALLBACK - # op op_double_to_float FALLBACK - # op op_int_to_byte FALLBACK - # op op_int_to_char FALLBACK - # op op_int_to_short FALLBACK - # op op_add_int FALLBACK - # op op_sub_int FALLBACK - # op op_mul_int FALLBACK - # op op_div_int FALLBACK - # op op_rem_int FALLBACK - # op op_and_int FALLBACK - # op op_or_int FALLBACK - # op op_xor_int FALLBACK - # op op_shl_int FALLBACK - # op op_shr_int FALLBACK - # op op_ushr_int FALLBACK - # op op_add_long FALLBACK - # op op_sub_long FALLBACK - # op op_mul_long FALLBACK - # op op_div_long FALLBACK - # op op_rem_long FALLBACK - # op op_and_long FALLBACK - # op op_or_long FALLBACK - # op op_xor_long FALLBACK - # op op_shl_long FALLBACK - # op op_shr_long FALLBACK - # op op_ushr_long FALLBACK - # op op_add_float FALLBACK - # op op_sub_float FALLBACK - # op op_mul_float FALLBACK - # op op_div_float FALLBACK - # op op_rem_float FALLBACK - # op op_add_double FALLBACK - # op op_sub_double FALLBACK - # op op_mul_double FALLBACK - # op op_div_double FALLBACK - # op op_rem_double FALLBACK - # op op_add_int_2addr FALLBACK - # op op_sub_int_2addr FALLBACK - # op op_mul_int_2addr FALLBACK - # op op_div_int_2addr FALLBACK - # op op_rem_int_2addr FALLBACK - # op op_and_int_2addr FALLBACK - # op op_or_int_2addr FALLBACK - # op op_xor_int_2addr FALLBACK - # op op_shl_int_2addr FALLBACK - # op op_shr_int_2addr FALLBACK - # op op_ushr_int_2addr FALLBACK - # op op_add_long_2addr FALLBACK - # op op_sub_long_2addr FALLBACK - # op op_mul_long_2addr FALLBACK - # op op_div_long_2addr FALLBACK - # op op_rem_long_2addr FALLBACK - # op op_and_long_2addr FALLBACK - # op op_or_long_2addr FALLBACK - # op op_xor_long_2addr FALLBACK - # op op_shl_long_2addr FALLBACK - # op op_shr_long_2addr FALLBACK - # op op_ushr_long_2addr FALLBACK - # op op_add_float_2addr FALLBACK - # op op_sub_float_2addr FALLBACK - # op op_mul_float_2addr FALLBACK - # op op_div_float_2addr FALLBACK - # op op_rem_float_2addr FALLBACK - # op op_add_double_2addr FALLBACK - # op op_sub_double_2addr FALLBACK - # op op_mul_double_2addr FALLBACK - # op op_div_double_2addr FALLBACK - # op op_rem_double_2addr FALLBACK - # op op_add_int_lit16 FALLBACK - # op op_rsub_int FALLBACK - # op op_mul_int_lit16 FALLBACK - # op op_div_int_lit16 FALLBACK - # op op_rem_int_lit16 FALLBACK - # op op_and_int_lit16 FALLBACK - # op op_or_int_lit16 FALLBACK - # op op_xor_int_lit16 FALLBACK - # op op_add_int_lit8 FALLBACK - # op op_rsub_int_lit8 FALLBACK - # op op_mul_int_lit8 FALLBACK - # op op_div_int_lit8 FALLBACK - # op op_rem_int_lit8 FALLBACK - # op op_and_int_lit8 FALLBACK - # op op_or_int_lit8 FALLBACK - # op op_xor_int_lit8 FALLBACK - # op op_shl_int_lit8 FALLBACK - # op op_shr_int_lit8 FALLBACK - # op op_ushr_int_lit8 FALLBACK - # op op_iget_quick FALLBACK - # op op_iget_wide_quick FALLBACK - # op op_iget_object_quick FALLBACK - # op op_iput_quick FALLBACK - # op op_iput_wide_quick FALLBACK - # op op_iput_object_quick FALLBACK - # op op_invoke_virtual_quick FALLBACK - # op op_invoke_virtual_range_quick FALLBACK - # op op_iput_boolean_quick FALLBACK - # op op_iput_byte_quick FALLBACK - # op op_iput_char_quick FALLBACK - # op op_iput_short_quick FALLBACK - # op op_iget_boolean_quick FALLBACK - # op op_iget_byte_quick FALLBACK - # op op_iget_char_quick FALLBACK - # op op_iget_short_quick FALLBACK - # op op_unused_f3 FALLBACK - # op op_unused_f4 FALLBACK - # op op_unused_f5 FALLBACK - # op op_unused_f6 FALLBACK - # op op_unused_f7 FALLBACK - # op op_unused_f8 FALLBACK - # op op_unused_f9 FALLBACK - # op op_invoke_polymorphic FALLBACK - # op op_invoke_polymorphic_range FALLBACK - # op op_invoke_custom FALLBACK - # op op_invoke_custom_range FALLBACK - # op op_const_method_handle FALLBACK - # op op_const_method_type FALLBACK -op-end - -# common subroutines for asm -import x86/footer.S diff --git a/runtime/interpreter/mterp/config_x86_64 b/runtime/interpreter/mterp/config_x86_64 deleted file mode 100644 index 89fbf43444dc6b18f1111073970a763a87064188..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/config_x86_64 +++ /dev/null @@ -1,302 +0,0 @@ -# Copyright (C) 2015 The Android Open Source Project -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -# -# Configuration for X86_64 -# - -handler-style computed-goto -handler-size 128 - -function-type-format FUNCTION_TYPE(%s) -function-size-format SIZE(%s,%s) -global-name-format SYMBOL(%s) - -# source for alternate entry stub -asm-alt-stub x86_64/alt_stub.S - -# file header and basic definitions -import x86_64/header.S - -# arch-specific entry point to interpreter -import x86_64/entry.S - -# Stub to switch to alternate interpreter -fallback-stub x86_64/fallback.S - -# opcode list; argument to op-start is default directory -op-start x86_64 - # (override example:) op OP_SUB_FLOAT_2ADDR arm-vfp - # (fallback example:) op OP_SUB_FLOAT_2ADDR FALLBACK - - # op op_nop FALLBACK - # op op_move FALLBACK - # op op_move_from16 FALLBACK - # op op_move_16 FALLBACK - # op op_move_wide FALLBACK - # op op_move_wide_from16 FALLBACK - # op op_move_wide_16 FALLBACK - # op op_move_object FALLBACK - # op op_move_object_from16 FALLBACK - # op op_move_object_16 FALLBACK - # op op_move_result FALLBACK - # op op_move_result_wide FALLBACK - # op op_move_result_object FALLBACK - # op op_move_exception FALLBACK - # op op_return_void FALLBACK - # op op_return FALLBACK - # op op_return_wide FALLBACK - # op op_return_object FALLBACK - # op op_const_4 FALLBACK - # op op_const_16 FALLBACK - # op op_const FALLBACK - # op op_const_high16 FALLBACK - # op op_const_wide_16 FALLBACK - # op op_const_wide_32 FALLBACK - # op op_const_wide FALLBACK - # op op_const_wide_high16 FALLBACK - # op op_const_string FALLBACK - # op op_const_string_jumbo FALLBACK - # op op_const_class FALLBACK - # op op_monitor_enter FALLBACK - # op op_monitor_exit FALLBACK - # op op_check_cast FALLBACK - # op op_instance_of FALLBACK - # op op_array_length FALLBACK - # op op_new_instance FALLBACK - # op op_new_array FALLBACK - # op op_filled_new_array FALLBACK - # op op_filled_new_array_range FALLBACK - # op op_fill_array_data FALLBACK - # op op_throw FALLBACK - # op op_goto FALLBACK - # op op_goto_16 FALLBACK - # op op_goto_32 FALLBACK - # op op_packed_switch FALLBACK - # op op_sparse_switch FALLBACK - # op op_cmpl_float FALLBACK - # op op_cmpg_float FALLBACK - # op op_cmpl_double FALLBACK - # op op_cmpg_double FALLBACK - # op op_cmp_long FALLBACK - # op op_if_eq FALLBACK - # op op_if_ne FALLBACK - # op op_if_lt FALLBACK - # op op_if_ge FALLBACK - # op op_if_gt FALLBACK - # op op_if_le FALLBACK - # op op_if_eqz FALLBACK - # op op_if_nez FALLBACK - # op op_if_ltz FALLBACK - # op op_if_gez FALLBACK - # op op_if_gtz FALLBACK - # op op_if_lez FALLBACK - # op op_unused_3e FALLBACK - # op op_unused_3f FALLBACK - # op op_unused_40 FALLBACK - # op op_unused_41 FALLBACK - # op op_unused_42 FALLBACK - # op op_unused_43 FALLBACK - # op op_aget FALLBACK - # op op_aget_wide FALLBACK - # op op_aget_object FALLBACK - # op op_aget_boolean FALLBACK - # op op_aget_byte FALLBACK - # op op_aget_char FALLBACK - # op op_aget_short FALLBACK - # op op_aput FALLBACK - # op op_aput_wide FALLBACK - # op op_aput_object FALLBACK - # op op_aput_boolean FALLBACK - # op op_aput_byte FALLBACK - # op op_aput_char FALLBACK - # op op_aput_short FALLBACK - # op op_iget FALLBACK - # op op_iget_wide FALLBACK - # op op_iget_object FALLBACK - # op op_iget_boolean FALLBACK - # op op_iget_byte FALLBACK - # op op_iget_char FALLBACK - # op op_iget_short FALLBACK - # op op_iput FALLBACK - # op op_iput_wide FALLBACK - # op op_iput_object FALLBACK - # op op_iput_boolean FALLBACK - # op op_iput_byte FALLBACK - # op op_iput_char FALLBACK - # op op_iput_short FALLBACK - # op op_sget FALLBACK - # op op_sget_wide FALLBACK - # op op_sget_object FALLBACK - # op op_sget_boolean FALLBACK - # op op_sget_byte FALLBACK - # op op_sget_char FALLBACK - # op op_sget_short FALLBACK - # op op_sput FALLBACK - # op op_sput_wide FALLBACK - # op op_sput_object FALLBACK - # op op_sput_boolean FALLBACK - # op op_sput_byte FALLBACK - # op op_sput_char FALLBACK - # op op_sput_short FALLBACK - # op op_invoke_virtual FALLBACK - # op op_invoke_super FALLBACK - # op op_invoke_direct FALLBACK - # op op_invoke_static FALLBACK - # op op_invoke_interface FALLBACK - # op op_return_void_no_barrier FALLBACK - # op op_invoke_virtual_range FALLBACK - # op op_invoke_super_range FALLBACK - # op op_invoke_direct_range FALLBACK - # op op_invoke_static_range FALLBACK - # op op_invoke_interface_range FALLBACK - # op op_unused_79 FALLBACK - # op op_unused_7a FALLBACK - # op op_neg_int FALLBACK - # op op_not_int FALLBACK - # op op_neg_long FALLBACK - # op op_not_long FALLBACK - # op op_neg_float FALLBACK - # op op_neg_double FALLBACK - # op op_int_to_long FALLBACK - # op op_int_to_float FALLBACK - # op op_int_to_double FALLBACK - # op op_long_to_int FALLBACK - # op op_long_to_float FALLBACK - # op op_long_to_double FALLBACK - # op op_float_to_int FALLBACK - # op op_float_to_long FALLBACK - # op op_float_to_double FALLBACK - # op op_double_to_int FALLBACK - # op op_double_to_long FALLBACK - # op op_double_to_float FALLBACK - # op op_int_to_byte FALLBACK - # op op_int_to_char FALLBACK - # op op_int_to_short FALLBACK - # op op_add_int FALLBACK - # op op_sub_int FALLBACK - # op op_mul_int FALLBACK - # op op_div_int FALLBACK - # op op_rem_int FALLBACK - # op op_and_int FALLBACK - # op op_or_int FALLBACK - # op op_xor_int FALLBACK - # op op_shl_int FALLBACK - # op op_shr_int FALLBACK - # op op_ushr_int FALLBACK - # op op_add_long FALLBACK - # op op_sub_long FALLBACK - # op op_mul_long FALLBACK - # op op_div_long FALLBACK - # op op_rem_long FALLBACK - # op op_and_long FALLBACK - # op op_or_long FALLBACK - # op op_xor_long FALLBACK - # op op_shl_long FALLBACK - # op op_shr_long FALLBACK - # op op_ushr_long FALLBACK - # op op_add_float FALLBACK - # op op_sub_float FALLBACK - # op op_mul_float FALLBACK - # op op_div_float FALLBACK - # op op_rem_float FALLBACK - # op op_add_double FALLBACK - # op op_sub_double FALLBACK - # op op_mul_double FALLBACK - # op op_div_double FALLBACK - # op op_rem_double FALLBACK - # op op_add_int_2addr FALLBACK - # op op_sub_int_2addr FALLBACK - # op op_mul_int_2addr FALLBACK - # op op_div_int_2addr FALLBACK - # op op_rem_int_2addr FALLBACK - # op op_and_int_2addr FALLBACK - # op op_or_int_2addr FALLBACK - # op op_xor_int_2addr FALLBACK - # op op_shl_int_2addr FALLBACK - # op op_shr_int_2addr FALLBACK - # op op_ushr_int_2addr FALLBACK - # op op_add_long_2addr FALLBACK - # op op_sub_long_2addr FALLBACK - # op op_mul_long_2addr FALLBACK - # op op_div_long_2addr FALLBACK - # op op_rem_long_2addr FALLBACK - # op op_and_long_2addr FALLBACK - # op op_or_long_2addr FALLBACK - # op op_xor_long_2addr FALLBACK - # op op_shl_long_2addr FALLBACK - # op op_shr_long_2addr FALLBACK - # op op_ushr_long_2addr FALLBACK - # op op_add_float_2addr FALLBACK - # op op_sub_float_2addr FALLBACK - # op op_mul_float_2addr FALLBACK - # op op_div_float_2addr FALLBACK - # op op_rem_float_2addr FALLBACK - # op op_add_double_2addr FALLBACK - # op op_sub_double_2addr FALLBACK - # op op_mul_double_2addr FALLBACK - # op op_div_double_2addr FALLBACK - # op op_rem_double_2addr FALLBACK - # op op_add_int_lit16 FALLBACK - # op op_rsub_int FALLBACK - # op op_mul_int_lit16 FALLBACK - # op op_div_int_lit16 FALLBACK - # op op_rem_int_lit16 FALLBACK - # op op_and_int_lit16 FALLBACK - # op op_or_int_lit16 FALLBACK - # op op_xor_int_lit16 FALLBACK - # op op_add_int_lit8 FALLBACK - # op op_rsub_int_lit8 FALLBACK - # op op_mul_int_lit8 FALLBACK - # op op_div_int_lit8 FALLBACK - # op op_rem_int_lit8 FALLBACK - # op op_and_int_lit8 FALLBACK - # op op_or_int_lit8 FALLBACK - # op op_xor_int_lit8 FALLBACK - # op op_shl_int_lit8 FALLBACK - # op op_shr_int_lit8 FALLBACK - # op op_ushr_int_lit8 FALLBACK - # op op_iget_quick FALLBACK - # op op_iget_wide_quick FALLBACK - # op op_iget_object_quick FALLBACK - # op op_iput_quick FALLBACK - # op op_iput_wide_quick FALLBACK - # op op_iput_object_quick FALLBACK - # op op_invoke_virtual_quick FALLBACK - # op op_invoke_virtual_range_quick FALLBACK - # op op_iput_boolean_quick FALLBACK - # op op_iput_byte_quick FALLBACK - # op op_iput_char_quick FALLBACK - # op op_iput_short_quick FALLBACK - # op op_iget_boolean_quick FALLBACK - # op op_iget_byte_quick FALLBACK - # op op_iget_char_quick FALLBACK - # op op_iget_short_quick FALLBACK - # op op_unused_f3 FALLBACK - # op op_unused_f4 FALLBACK - # op op_unused_f5 FALLBACK - # op op_unused_f6 FALLBACK - # op op_unused_f7 FALLBACK - # op op_unused_f8 FALLBACK - # op op_unused_f9 FALLBACK - # op op_invoke_polymorphic FALLBACK - # op op_invoke_polymorphic_range FALLBACK - # op op_invoke_custom FALLBACK - # op op_invoke_custom_range FALLBACK - # op op_const_method_handle FALLBACK - # op op_const_method_type FALLBACK -op-end - -# common subroutines for asm -import x86_64/footer.S diff --git a/runtime/interpreter/mterp/gen_mterp.py b/runtime/interpreter/mterp/gen_mterp.py index 75c5174bcbc487cc29639c0b7f9620d4b5e71130..ad6e8361775e9cdbf26c8c2ac253f03d39a0a4cc 100755 --- a/runtime/interpreter/mterp/gen_mterp.py +++ b/runtime/interpreter/mterp/gen_mterp.py @@ -14,605 +14,85 @@ # See the License for the specific language governing permissions and # limitations under the License. -# -# Using instructions from an architecture-specific config file, generate C -# and assembly source files for the Dalvik interpreter. -# - -import sys, string, re, time -from string import Template - -interp_defs_file = "../../../libdexfile/dex/dex_instruction_list.h" # need opcode list -kNumPackedOpcodes = 256 - -splitops = False -verbose = False -handler_size_bits = -1000 -handler_size_bytes = -1000 -in_op_start = 0 # 0=not started, 1=started, 2=ended -in_alt_op_start = 0 # 0=not started, 1=started, 2=ended -default_op_dir = None -default_alt_stub = None -opcode_locations = {} -alt_opcode_locations = {} -asm_stub_text = [] -fallback_stub_text = [] -label_prefix = ".L" # use ".L" to hide labels from gdb -alt_label_prefix = ".L_ALT" # use ".L" to hide labels from gdb -style = None # interpreter style -generate_alt_table = False -function_type_format = ".type %s, %%function" -function_size_format = ".size %s, .-%s" -global_name_format = "%s" - -# Exception class. -class DataParseError(SyntaxError): - "Failure when parsing data file" - -# -# Set any omnipresent substitution values. -# -def getGlobalSubDict(): - return { "handler_size_bits":handler_size_bits, - "handler_size_bytes":handler_size_bytes } - -# -# Parse arch config file -- -# Set interpreter style. -# -def setHandlerStyle(tokens): - global style - if len(tokens) != 2: - raise DataParseError("handler-style requires one argument") - style = tokens[1] - if style != "computed-goto": - raise DataParseError("handler-style (%s) invalid" % style) - -# -# Parse arch config file -- -# Set handler_size_bytes to the value of tokens[1], and handler_size_bits to -# log2(handler_size_bytes). Throws an exception if "bytes" is not 0 or -# a power of two. -# -def setHandlerSize(tokens): - global handler_size_bits, handler_size_bytes - if style != "computed-goto": - print "Warning: handler-size valid only for computed-goto interpreters" - if len(tokens) != 2: - raise DataParseError("handler-size requires one argument") - if handler_size_bits != -1000: - raise DataParseError("handler-size may only be set once") - - # compute log2(n), and make sure n is 0 or a power of 2 - handler_size_bytes = bytes = int(tokens[1]) - bits = -1 - while bytes > 0: - bytes //= 2 # halve with truncating division - bits += 1 - - if handler_size_bytes == 0 or handler_size_bytes != (1 << bits): - raise DataParseError("handler-size (%d) must be power of 2" \ - % orig_bytes) - handler_size_bits = bits +import sys, re, os +from cStringIO import StringIO -# -# Parse arch config file -- -# Copy a file in to asm output file. -# -def importFile(tokens): - if len(tokens) != 2: - raise DataParseError("import requires one argument") - source = tokens[1] - if source.endswith(".S"): - appendSourceFile(tokens[1], getGlobalSubDict(), asm_fp, None) - else: - raise DataParseError("don't know how to import %s (expecting .cpp/.S)" - % source) - -# -# Parse arch config file -- -# Copy a file in to the C or asm output file. -# -def setAsmStub(tokens): - global asm_stub_text - if len(tokens) != 2: - raise DataParseError("import requires one argument") - try: - stub_fp = open(tokens[1]) - asm_stub_text = stub_fp.readlines() - except IOError, err: - stub_fp.close() - raise DataParseError("unable to load asm-stub: %s" % str(err)) - stub_fp.close() +SCRIPT_DIR = os.path.dirname(sys.argv[0]) +# This file is included verbatim at the start of the in-memory python script. +SCRIPT_SETUP_CODE = SCRIPT_DIR + "/common/gen_setup.py" +INTERP_DEFS_FILE = SCRIPT_DIR + "/../../../libdexfile/dex/dex_instruction_list.h" +NUM_PACKED_OPCODES = 256 -# -# Parse arch config file -- -# Copy a file in to the C or asm output file. -# -def setFallbackStub(tokens): - global fallback_stub_text - if len(tokens) != 2: - raise DataParseError("import requires one argument") - try: - stub_fp = open(tokens[1]) - fallback_stub_text = stub_fp.readlines() - except IOError, err: - stub_fp.close() - raise DataParseError("unable to load fallback-stub: %s" % str(err)) - stub_fp.close() -# -# Parse arch config file -- -# Record location of default alt stub -# -def setAsmAltStub(tokens): - global default_alt_stub, generate_alt_table - if len(tokens) != 2: - raise DataParseError("import requires one argument") - default_alt_stub = tokens[1] - generate_alt_table = True -# -# Change the default function type format -# -def setFunctionTypeFormat(tokens): - global function_type_format - function_type_format = tokens[1] -# -# Change the default function size format -# -def setFunctionSizeFormat(tokens): - global function_size_format - function_size_format = tokens[1] -# -# Change the global name format -# -def setGlobalNameFormat(tokens): - global global_name_format - global_name_format = tokens[1] -# -# Parse arch config file -- -# Start of opcode list. -# -def opStart(tokens): - global in_op_start - global default_op_dir - if len(tokens) != 2: - raise DataParseError("opStart takes a directory name argument") - if in_op_start != 0: - raise DataParseError("opStart can only be specified once") - default_op_dir = tokens[1] - in_op_start = 1 - -# -# Parse arch config file -- -# Set location of a single alt opcode's source file. -# -def altEntry(tokens): - global generate_alt_table - if len(tokens) != 3: - raise DataParseError("alt requires exactly two arguments") - if in_op_start != 1: - raise DataParseError("alt statements must be between opStart/opEnd") - try: - index = opcodes.index(tokens[1]) - except ValueError: - raise DataParseError("unknown opcode %s" % tokens[1]) - if alt_opcode_locations.has_key(tokens[1]): - print "Note: alt overrides earlier %s (%s -> %s)" \ - % (tokens[1], alt_opcode_locations[tokens[1]], tokens[2]) - alt_opcode_locations[tokens[1]] = tokens[2] - generate_alt_table = True - -# -# Parse arch config file -- -# Set location of a single opcode's source file. -# -def opEntry(tokens): - #global opcode_locations - if len(tokens) != 3: - raise DataParseError("op requires exactly two arguments") - if in_op_start != 1: - raise DataParseError("op statements must be between opStart/opEnd") - try: - index = opcodes.index(tokens[1]) - except ValueError: - raise DataParseError("unknown opcode %s" % tokens[1]) - if opcode_locations.has_key(tokens[1]): - print "Note: op overrides earlier %s (%s -> %s)" \ - % (tokens[1], opcode_locations[tokens[1]], tokens[2]) - opcode_locations[tokens[1]] = tokens[2] - -# -# Parse arch config file -- -# End of opcode list; emit instruction blocks. -# -def opEnd(tokens): - global in_op_start - if len(tokens) != 1: - raise DataParseError("opEnd takes no arguments") - if in_op_start != 1: - raise DataParseError("opEnd must follow opStart, and only appear once") - in_op_start = 2 - - loadAndEmitOpcodes() - if splitops == False: - if generate_alt_table: - loadAndEmitAltOpcodes() - -def genaltop(tokens): - if in_op_start != 2: - raise DataParseError("alt-op can be specified only after op-end") - if len(tokens) != 1: - raise DataParseError("opEnd takes no arguments") - if generate_alt_table: - loadAndEmitAltOpcodes() - -# # Extract an ordered list of instructions from the VM sources. We use the -# "goto table" definition macro, which has exactly kNumPackedOpcodes -# entries. -# +# "goto table" definition macro, which has exactly NUM_PACKED_OPCODES entries. def getOpcodeList(): - opcodes = [] - opcode_fp = open(interp_defs_file) - opcode_re = re.compile(r"^\s*V\((....), (\w+),.*", re.DOTALL) - for line in opcode_fp: - match = opcode_re.match(line) - if not match: - continue - opcodes.append("op_" + match.group(2).lower()) - opcode_fp.close() - - if len(opcodes) != kNumPackedOpcodes: - print "ERROR: found %d opcodes in Interp.h (expected %d)" \ - % (len(opcodes), kNumPackedOpcodes) - raise SyntaxError, "bad opcode count" - return opcodes - -def emitAlign(): - if style == "computed-goto": - asm_fp.write(" .balign %d\n" % handler_size_bytes) - -# -# Load and emit opcodes for all kNumPackedOpcodes instructions. -# -def loadAndEmitOpcodes(): - sister_list = [] - assert len(opcodes) == kNumPackedOpcodes - need_dummy_start = False - - loadAndEmitGenericAsm("instruction_start") - - for i in xrange(kNumPackedOpcodes): - op = opcodes[i] - - if opcode_locations.has_key(op): - location = opcode_locations[op] - else: - location = default_op_dir - - if location == "FALLBACK": - emitFallback(i) - else: - loadAndEmitAsm(location, i, sister_list) - - # For a 100% C implementation, there are no asm handlers or stubs. We - # need to have the MterpAsmInstructionStart label point at op_nop, and it's - # too annoying to try to slide it in after the alignment psuedo-op, so - # we take the low road and just emit a dummy op_nop here. - if need_dummy_start: - emitAlign() - asm_fp.write(label_prefix + "_op_nop: /* dummy */\n"); - - emitAlign() - - loadAndEmitGenericAsm("instruction_end") - - if style == "computed-goto": - emitSectionComment("Sister implementations", asm_fp) - loadAndEmitGenericAsm("instruction_start_sister") - asm_fp.writelines(sister_list) - loadAndEmitGenericAsm("instruction_end_sister") - -# -# Load an alternate entry stub -# -def loadAndEmitAltStub(source, opindex): - op = opcodes[opindex] - if verbose: - print " alt emit %s --> stub" % source - dict = getGlobalSubDict() - dict.update({ "opcode":op, "opnum":opindex }) - - emitAsmHeader(asm_fp, dict, alt_label_prefix) - appendSourceFile(source, dict, asm_fp, None) - -# -# Load and emit alternate opcodes for all kNumPackedOpcodes instructions. -# -def loadAndEmitAltOpcodes(): - assert len(opcodes) == kNumPackedOpcodes - start_label = global_name_format % "artMterpAsmAltInstructionStart" - end_label = global_name_format % "artMterpAsmAltInstructionEnd" - - loadAndEmitGenericAsm("instruction_start_alt") - - for i in xrange(kNumPackedOpcodes): - op = opcodes[i] - if alt_opcode_locations.has_key(op): - source = "%s/alt_%s.S" % (alt_opcode_locations[op], op) - else: - source = default_alt_stub - loadAndEmitAltStub(source, i) - - emitAlign() - - loadAndEmitGenericAsm("instruction_end_alt") - -# -# Load an assembly fragment and emit it. -# -def loadAndEmitAsm(location, opindex, sister_list): - op = opcodes[opindex] - source = "%s/%s.S" % (location, op) - dict = getGlobalSubDict() - dict.update({ "opcode":op, "opnum":opindex }) - if verbose: - print " emit %s --> asm" % source - - emitAsmHeader(asm_fp, dict, label_prefix) - appendSourceFile(source, dict, asm_fp, sister_list) - -# -# Load a non-handler assembly fragment and emit it. -# -def loadAndEmitGenericAsm(name): - source = "%s/%s.S" % (default_op_dir, name) - dict = getGlobalSubDict() - appendSourceFile(source, dict, asm_fp, None) - -# -# Emit fallback fragment -# -def emitFallback(opindex): - op = opcodes[opindex] - dict = getGlobalSubDict() - dict.update({ "opcode":op, "opnum":opindex }) - emitAsmHeader(asm_fp, dict, label_prefix) - for line in fallback_stub_text: - asm_fp.write(line) - asm_fp.write("\n") - -# -# Output the alignment directive and label for an assembly piece. -# -def emitAsmHeader(outfp, dict, prefix): - outfp.write("/* ------------------------------ */\n") - # The alignment directive ensures that the handler occupies - # at least the correct amount of space. We don't try to deal - # with overflow here. - emitAlign() - # Emit a label so that gdb will say the right thing. We prepend an - # underscore so the symbol name doesn't clash with the Opcode enum. - outfp.write(prefix + "_%(opcode)s: /* 0x%(opnum)02x */\n" % dict) - -# -# Output a generic instruction stub that updates the "glue" struct and -# calls the C implementation. -# -def emitAsmStub(outfp, dict): - emitAsmHeader(outfp, dict, label_prefix) - for line in asm_stub_text: - templ = Template(line) - outfp.write(templ.substitute(dict)) - -# -# Append the file specified by "source" to the open "outfp". Each line will -# be template-replaced using the substitution dictionary "dict". -# -# If the first line of the file starts with "%" it is taken as a directive. -# A "%include" line contains a filename and, optionally, a Python-style -# dictionary declaration with substitution strings. (This is implemented -# with recursion.) -# -# If "sister_list" is provided, and we find a line that contains only "&", -# all subsequent lines from the file will be appended to sister_list instead -# of copied to the output. -# -# This may modify "dict". -# -def appendSourceFile(source, dict, outfp, sister_list): - outfp.write("/* File: %s */\n" % source) - infp = open(source, "r") - in_sister = False - for line in infp: - if line.startswith("%include"): - # Parse the "include" line - tokens = line.strip().split(' ', 2) - if len(tokens) < 2: - raise DataParseError("malformed %%include in %s" % source) - - alt_source = tokens[1].strip("\"") - if alt_source == source: - raise DataParseError("self-referential %%include in %s" - % source) - - new_dict = dict.copy() - if len(tokens) == 3: - new_dict.update(eval(tokens[2])) - #print " including src=%s dict=%s" % (alt_source, new_dict) - appendSourceFile(alt_source, new_dict, outfp, sister_list) - continue - - elif line.startswith("%default"): - # copy keywords into dictionary - tokens = line.strip().split(' ', 1) - if len(tokens) < 2: - raise DataParseError("malformed %%default in %s" % source) - defaultValues = eval(tokens[1]) - for entry in defaultValues: - dict.setdefault(entry, defaultValues[entry]) - continue - - elif line.startswith("%break") and sister_list != None: - # allow more than one %break, ignoring all following the first - if style == "computed-goto" and not in_sister: - in_sister = True - sister_list.append("\n/* continuation for %(opcode)s */\n"%dict) - continue - - # perform keyword substitution if a dictionary was provided - if dict != None: - templ = Template(line) - try: - subline = templ.substitute(dict) - except KeyError, err: - raise DataParseError("keyword substitution failed in %s: %s" - % (source, str(err))) - except: - print "ERROR: substitution failed: " + line - raise - else: - subline = line - - # write output to appropriate file - if in_sister: - sister_list.append(subline) - else: - outfp.write(subline) - outfp.write("\n") - infp.close() - -# -# Emit a C-style section header comment. -# -def emitSectionComment(str, fp): - equals = "========================================" \ - "===================================" - - fp.write("\n/*\n * %s\n * %s\n * %s\n */\n" % - (equals, str, equals)) - - -# -# =========================================================================== -# "main" code -# - -# -# Check args. -# -if len(sys.argv) != 3: - print "Usage: %s target-arch output-dir" % sys.argv[0] - sys.exit(2) - -target_arch = sys.argv[1] -output_dir = sys.argv[2] - -# -# Extract opcode list. -# -opcodes = getOpcodeList() -#for op in opcodes: -# print " %s" % op - -# -# Open config file. -# -try: - config_fp = open("config_%s" % target_arch) -except: - print "Unable to open config file 'config_%s'" % target_arch - sys.exit(1) - -# -# Open and prepare output files. -# -try: - asm_fp = open("%s/mterp_%s.S" % (output_dir, target_arch), "w") -except: - print "Unable to open output files" - print "Make sure directory '%s' exists and existing files are writable" \ - % output_dir - # Ideally we'd remove the files to avoid confusing "make", but if they - # failed to open we probably won't be able to remove them either. - sys.exit(1) - -print "Generating %s" % (asm_fp.name) - -file_header = """/* - * This file was generated automatically by gen-mterp.py for '%s'. - * - * --> DO NOT EDIT <-- - */ - -""" % (target_arch) - -asm_fp.write(file_header) - -# -# Process the config file. -# -failed = False -try: - for line in config_fp: - line = line.strip() # remove CRLF, leading spaces - tokens = line.split(' ') # tokenize - #print "%d: %s" % (len(tokens), tokens) - if len(tokens[0]) == 0: - #print " blank" - pass - elif tokens[0][0] == '#': - #print " comment" - pass - else: - if tokens[0] == "handler-size": - setHandlerSize(tokens) - elif tokens[0] == "import": - importFile(tokens) - elif tokens[0] == "asm-stub": - setAsmStub(tokens) - elif tokens[0] == "asm-alt-stub": - setAsmAltStub(tokens) - elif tokens[0] == "op-start": - opStart(tokens) - elif tokens[0] == "op-end": - opEnd(tokens) - elif tokens[0] == "alt": - altEntry(tokens) - elif tokens[0] == "op": - opEntry(tokens) - elif tokens[0] == "handler-style": - setHandlerStyle(tokens) - elif tokens[0] == "alt-ops": - genaltop(tokens) - elif tokens[0] == "split-ops": - splitops = True - elif tokens[0] == "fallback-stub": - setFallbackStub(tokens) - elif tokens[0] == "function-type-format": - setFunctionTypeFormat(tokens) - elif tokens[0] == "function-size-format": - setFunctionSizeFormat(tokens) - elif tokens[0] == "global-name-format": - setGlobalNameFormat(tokens) - else: - raise DataParseError, "unrecognized command '%s'" % tokens[0] - if style == None: - print "tokens[0] = %s" % tokens[0] - raise DataParseError, "handler-style must be first command" -except DataParseError, err: - print "Failed: " + str(err) - # TODO: remove output files so "make" doesn't get confused - failed = True - asm_fp.close() - asm_fp = None - -config_fp.close() - -# -# Done! -# -if asm_fp: - asm_fp.close() - -sys.exit(failed) + opcodes = [] + opcode_fp = open(INTERP_DEFS_FILE) + opcode_re = re.compile(r"^\s*V\((....), (\w+),.*", re.DOTALL) + for line in opcode_fp: + match = opcode_re.match(line) + if not match: + continue + opcodes.append("op_" + match.group(2).lower()) + opcode_fp.close() + + if len(opcodes) != NUM_PACKED_OPCODES: + print "ERROR: found %d opcodes in Interp.h (expected %d)" \ + % (len(opcodes), NUM_PACKED_OPCODES) + raise SyntaxError, "bad opcode count" + return opcodes + +indent_re = re.compile(r"^%( *)") + +# Finds variable references in text: $foo or ${foo} +escape_re = re.compile(r''' + (?\w+) # Save the symbol in named group. + (?(1)\}) # Expect } if and only if { was present. +''', re.VERBOSE) + +def generate_script(output_filename, input_filenames): + # Create new python script and write the initial setup code. + script = StringIO() # File-like in-memory buffer. + script.write("# DO NOT EDIT: This file was generated by gen-mterp.py.\n") + script.write(open(SCRIPT_SETUP_CODE, "r").read()) + script.write("def opcodes(is_alt):\n") + for i, opcode in enumerate(getOpcodeList()): + script.write(' write_opcode({0}, "{1}", {1}, is_alt)\n'.format(i, opcode)) + + # Read all template files and translate them into python code. + for input_filename in sorted(input_filenames): + lines = open(input_filename, "r").readlines() + indent = "" + for line in lines: + line = line.rstrip() + if line.startswith("%"): + script.write(line.lstrip("%") + "\n") + indent = indent_re.match(line).group(1) + if line.endswith(":"): + indent += " " + else: + line = escape_re.sub(r"''' + \g + '''", line) + line = line.replace("\\", "\\\\") + line = line.replace("$$", "$") + script.write(indent + "write_line('''" + line + "''')\n") + script.write("\n") + + script.write("generate('''" + output_filename + "''')\n") + script.seek(0) + return script.read() + +if len(sys.argv) <= 3: + print("Usage: output_file input_file(s)") + sys.exit(1) + +# Generate the script and execute it. +output_filename = sys.argv[1] +input_filenames = sys.argv[2:] +script_filename = output_filename + ".py" +script = generate_script(output_filename, input_filenames) +with open(script_filename, "w") as script_file: + script_file.write(script) # Write to disk for debugging. +exec(compile(script, script_filename, mode='exec')) diff --git a/runtime/interpreter/mterp/mips/alt_stub.S b/runtime/interpreter/mterp/mips/alt_stub.S deleted file mode 100644 index de133136e00768f720e36a256c1a1a9e2aba41ed..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/alt_stub.S +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (${opnum} * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) diff --git a/runtime/interpreter/mterp/mips/arithmetic.S b/runtime/interpreter/mterp/mips/arithmetic.S new file mode 100644 index 0000000000000000000000000000000000000000..9ae10f2ba930edbd7569e3cbc2598643f34cb1d1 --- /dev/null +++ b/runtime/interpreter/mterp/mips/arithmetic.S @@ -0,0 +1,803 @@ +%def binop(preinstr="", result="a0", chkzero="0", instr=""): + /* + * Generic 32-bit binary operation. Provide an "instr" line that + * specifies an instruction that performs "result = a0 op a1". + * This could be a MIPS instruction or a function call. (If the result + * comes back in a register other than a0, you can override "result".) + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vCC (a1). Useful for integer division and modulus. Note that we + * *don't* check for (INT_MIN / -1) here, because the CPU handles it + * correctly. + * + * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, + * xor-int, shl-int, shr-int, ushr-int + */ + /* binop vAA, vBB, vCC */ + FETCH(a0, 1) # a0 <- CCBB + GET_OPA(rOBJ) # rOBJ <- AA + srl a3, a0, 8 # a3 <- CC + and a2, a0, 255 # a2 <- BB + GET_VREG(a1, a3) # a1 <- vCC + GET_VREG(a0, a2) # a0 <- vBB + .if $chkzero + # is second operand zero? + beqz a1, common_errDivideByZero + .endif + + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + $preinstr # optional op + $instr # $result <- op, a0-a3 changed + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG_GOTO($result, rOBJ, t0) # vAA <- $result + +%def binop2addr(preinstr="", result="a0", chkzero="0", instr=""): + /* + * Generic 32-bit "/2addr" binary operation. Provide an "instr" line + * that specifies an instruction that performs "result = a0 op a1". + * This could be an MIPS instruction or a function call. + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vCC (a1). Useful for integer division and modulus. + * + * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, + * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, + * shl-int/2addr, shr-int/2addr, ushr-int/2addr + */ + /* binop/2addr vA, vB */ + GET_OPA4(rOBJ) # rOBJ <- A+ + GET_OPB(a3) # a3 <- B + GET_VREG(a0, rOBJ) # a0 <- vA + GET_VREG(a1, a3) # a1 <- vB + .if $chkzero + # is second operand zero? + beqz a1, common_errDivideByZero + .endif + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + + $preinstr # optional op + $instr # $result <- op, a0-a3 changed + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG_GOTO($result, rOBJ, t0) # vA <- $result + +%def binopLit16(preinstr="", result="a0", chkzero="0", instr=""): + /* + * Generic 32-bit "lit16" binary operation. Provide an "instr" line + * that specifies an instruction that performs "result = a0 op a1". + * This could be an MIPS instruction or a function call. (If the result + * comes back in a register other than a0, you can override "result".) + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vCC (a1). Useful for integer division and modulus. + * + * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, + * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 + */ + /* binop/lit16 vA, vB, +CCCC */ + FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) + GET_OPB(a2) # a2 <- B + GET_OPA4(rOBJ) # rOBJ <- A+ + GET_VREG(a0, a2) # a0 <- vB + .if $chkzero + # cmp a1, 0; is second operand zero? + beqz a1, common_errDivideByZero + .endif + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + + $preinstr # optional op + $instr # $result <- op, a0-a3 changed + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG_GOTO($result, rOBJ, t0) # vA <- $result + +%def binopLit8(preinstr="", result="a0", chkzero="0", instr=""): + /* + * Generic 32-bit "lit8" binary operation. Provide an "instr" line + * that specifies an instruction that performs "result = a0 op a1". + * This could be an MIPS instruction or a function call. (If the result + * comes back in a register other than a0, you can override "result".) + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vCC (a1). Useful for integer division and modulus. + * + * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, + * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, + * shl-int/lit8, shr-int/lit8, ushr-int/lit8 + */ + /* binop/lit8 vAA, vBB, +CC */ + FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) + GET_OPA(rOBJ) # rOBJ <- AA + and a2, a3, 255 # a2 <- BB + GET_VREG(a0, a2) # a0 <- vBB + sra a1, a3, 8 # a1 <- ssssssCC (sign extended) + .if $chkzero + # is second operand zero? + beqz a1, common_errDivideByZero + .endif + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + + $preinstr # optional op + $instr # $result <- op, a0-a3 changed + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG_GOTO($result, rOBJ, t0) # vAA <- $result + +%def binopWide(preinstr="", result0="a0", result1="a1", chkzero="0", arg0="a0", arg1="a1", arg2="a2", arg3="a3", instr=""): + /* + * Generic 64-bit binary operation. Provide an "instr" line that + * specifies an instruction that performs "result = a0-a1 op a2-a3". + * This could be a MIPS instruction or a function call. (If the result + * comes back in a register pair other than a0-a1, you can override "result".) + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vCC (a2-a3). Useful for integer division and modulus. + * + * for: add-long, sub-long, div-long, rem-long, and-long, or-long, + * xor-long + * + * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. + */ + /* binop vAA, vBB, vCC */ + FETCH(a0, 1) # a0 <- CCBB + GET_OPA(rOBJ) # rOBJ <- AA + and a2, a0, 255 # a2 <- BB + srl a3, a0, 8 # a3 <- CC + EAS2(a2, rFP, a2) # a2 <- &fp[BB] + EAS2(t1, rFP, a3) # a3 <- &fp[CC] + LOAD64($arg0, $arg1, a2) # a0/a1 <- vBB/vBB+1 + LOAD64($arg2, $arg3, t1) # a2/a3 <- vCC/vCC+1 + .if $chkzero + or t0, $arg2, $arg3 # second arg (a2-a3) is zero? + beqz t0, common_errDivideByZero + .endif + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + + $preinstr # optional op + $instr # result <- op, a0-a3 changed + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG64_GOTO($result0, $result1, rOBJ, t0) # vAA/vAA+1 <- $result0/$result1 + +%def binopWide2addr(preinstr="", result0="a0", result1="a1", chkzero="0", arg0="a0", arg1="a1", arg2="a2", arg3="a3", instr=""): + /* + * Generic 64-bit "/2addr" binary operation. Provide an "instr" line + * that specifies an instruction that performs "result = a0-a1 op a2-a3". + * This could be a MIPS instruction or a function call. (If the result + * comes back in a register pair other than a0-a1, you can override "result".) + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vB (a2-a3). Useful for integer division and modulus. + * + * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, + * and-long/2addr, or-long/2addr, xor-long/2addr + */ + /* binop/2addr vA, vB */ + GET_OPA4(rOBJ) # rOBJ <- A+ + GET_OPB(a1) # a1 <- B + EAS2(a1, rFP, a1) # a1 <- &fp[B] + EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] + LOAD64($arg2, $arg3, a1) # a2/a3 <- vB/vB+1 + LOAD64($arg0, $arg1, t0) # a0/a1 <- vA/vA+1 + .if $chkzero + or t0, $arg2, $arg3 # second arg (a2-a3) is zero? + beqz t0, common_errDivideByZero + .endif + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + + $preinstr # optional op + $instr # result <- op, a0-a3 changed + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG64_GOTO($result0, $result1, rOBJ, t0) # vA/vA+1 <- $result0/$result1 + +%def unop(preinstr="", result0="a0", instr=""): + /* + * Generic 32-bit unary operation. Provide an "instr" line that + * specifies an instruction that performs "result0 = op a0". + * This could be a MIPS instruction or a function call. + * + * for: int-to-byte, int-to-char, int-to-short, + * neg-int, not-int, neg-float + */ + /* unop vA, vB */ + GET_OPB(a3) # a3 <- B + GET_OPA4(t0) # t0 <- A+ + GET_VREG(a0, a3) # a0 <- vB + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + $preinstr # optional op + $instr # a0 <- op, a0-a3 changed + GET_INST_OPCODE(t1) # extract opcode from rINST + SET_VREG_GOTO($result0, t0, t1) # vA <- result0 + +%def unopNarrower(load="LOAD64_F(fa0, fa0f, a3)", instr=""): + /* + * Generic 64bit-to-32bit floating-point unary operation. Provide an "instr" + * line that specifies an instruction that performs "fv0 = op fa0". + * + * For: double-to-float + */ + /* unop vA, vB */ + GET_OPB(a3) # a3 <- B + GET_OPA4(rOBJ) # rOBJ <- A+ + EAS2(a3, rFP, a3) # a3 <- &fp[B] + $load + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + $instr + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG_F_GOTO(fv0, rOBJ, t0) # vA <- fv0 + +%def unopWide(preinstr="", result0="a0", result1="a1", instr=""): + /* + * Generic 64-bit unary operation. Provide an "instr" line that + * specifies an instruction that performs "result0/result1 = op a0/a1". + * This could be MIPS instruction or a function call. + * + * For: neg-long, not-long, neg-double, + */ + /* unop vA, vB */ + GET_OPA4(rOBJ) # rOBJ <- A+ + GET_OPB(a3) # a3 <- B + EAS2(a3, rFP, a3) # a3 <- &fp[B] + LOAD64(a0, a1, a3) # a0/a1 <- vA + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + $preinstr # optional op + $instr # a0/a1 <- op, a2-a3 changed + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG64_GOTO($result0, $result1, rOBJ, t0) # vA/vA+1 <- a0/a1 + +%def unopWider(preinstr="", result0="a0", result1="a1", instr=""): + /* + * Generic 32bit-to-64bit unary operation. Provide an "instr" line + * that specifies an instruction that performs "result0/result1 = op a0". + * + * For: int-to-long + */ + /* unop vA, vB */ + GET_OPA4(rOBJ) # rOBJ <- A+ + GET_OPB(a3) # a3 <- B + GET_VREG(a0, a3) # a0 <- vB + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + $preinstr # optional op + $instr # result <- op, a0-a3 changed + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG64_GOTO($result0, $result1, rOBJ, t0) # vA/vA+1 <- a0/a1 + +%def op_add_int(): +% binop(instr="addu a0, a0, a1") + +%def op_add_int_2addr(): +% binop2addr(instr="addu a0, a0, a1") + +%def op_add_int_lit16(): +% binopLit16(instr="addu a0, a0, a1") + +%def op_add_int_lit8(): +% binopLit8(instr="addu a0, a0, a1") + +%def op_add_long(): +/* + * The compiler generates the following sequence for + * [v1 v0] = [a1 a0] + [a3 a2]; + * addu v0,a2,a0 + * addu a1,a3,a1 + * sltu v1,v0,a2 + * addu v1,v1,a1 + */ +% binopWide(result0="v0", result1="v1", preinstr="addu v0, a2, a0", instr="addu a1, a3, a1; sltu v1, v0, a2; addu v1, v1, a1") + +%def op_add_long_2addr(): +/* + * See op_add_long.S for details + */ +% binopWide2addr(result0="v0", result1="v1", preinstr="addu v0, a2, a0", instr="addu a1, a3, a1; sltu v1, v0, a2; addu v1, v1, a1") + +%def op_and_int(): +% binop(instr="and a0, a0, a1") + +%def op_and_int_2addr(): +% binop2addr(instr="and a0, a0, a1") + +%def op_and_int_lit16(): +% binopLit16(instr="and a0, a0, a1") + +%def op_and_int_lit8(): +% binopLit8(instr="and a0, a0, a1") + +%def op_and_long(): +% binopWide(preinstr="and a0, a0, a2", instr="and a1, a1, a3") + +%def op_and_long_2addr(): +% binopWide2addr(preinstr="and a0, a0, a2", instr="and a1, a1, a3") + +%def op_cmp_long(): + /* + * Compare two 64-bit values + * x = y return 0 + * x < y return -1 + * x > y return 1 + * + * I think I can improve on the ARM code by the following observation + * slt t0, x.hi, y.hi; # (x.hi < y.hi) ? 1:0 + * sgt t1, x.hi, y.hi; # (y.hi > x.hi) ? 1:0 + * subu v0, t0, t1 # v0= -1:1:0 for [ < > = ] + */ + /* cmp-long vAA, vBB, vCC */ + FETCH(a0, 1) # a0 <- CCBB + GET_OPA(rOBJ) # rOBJ <- AA + and a2, a0, 255 # a2 <- BB + srl a3, a0, 8 # a3 <- CC + EAS2(a2, rFP, a2) # a2 <- &fp[BB] + EAS2(a3, rFP, a3) # a3 <- &fp[CC] + LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 + LOAD64(a2, a3, a3) # a2/a3 <- vCC/vCC+1 + + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + slt t0, a1, a3 # compare hi + sgt t1, a1, a3 + subu v0, t1, t0 # v0 <- (-1, 1, 0) + bnez v0, .L${opcode}_finish + # at this point x.hi==y.hi + sltu t0, a0, a2 # compare lo + sgtu t1, a0, a2 + subu v0, t1, t0 # v0 <- (-1, 1, 0) for [< > =] + +.L${opcode}_finish: + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG_GOTO(v0, rOBJ, t0) # vAA <- v0 + +%def op_div_int(): +#ifdef MIPS32REVGE6 +% binop(instr="div a0, a0, a1", chkzero="1") +#else +% binop(preinstr="div zero, a0, a1", instr="mflo a0", chkzero="1") +#endif + +%def op_div_int_2addr(): +#ifdef MIPS32REVGE6 +% binop2addr(instr="div a0, a0, a1", chkzero="1") +#else +% binop2addr(preinstr="div zero, a0, a1", instr="mflo a0", chkzero="1") +#endif + +%def op_div_int_lit16(): +#ifdef MIPS32REVGE6 +% binopLit16(instr="div a0, a0, a1", chkzero="1") +#else +% binopLit16(preinstr="div zero, a0, a1", instr="mflo a0", chkzero="1") +#endif + +%def op_div_int_lit8(): +#ifdef MIPS32REVGE6 +% binopLit8(instr="div a0, a0, a1", chkzero="1") +#else +% binopLit8(preinstr="div zero, a0, a1", instr="mflo a0", chkzero="1") +#endif + +%def op_div_long(): +% binopWide(result0="v0", result1="v1", instr="JAL(__divdi3)", chkzero="1") + +%def op_div_long_2addr(): +% binopWide2addr(result0="v0", result1="v1", instr="JAL(__divdi3)", chkzero="1") + +%def op_int_to_byte(): +% unop(instr="SEB(a0, a0)") + +%def op_int_to_char(): +% unop(preinstr="", instr="and a0, 0xffff") + +%def op_int_to_long(): +% unopWider(instr="sra a1, a0, 31") + +%def op_int_to_short(): +% unop(instr="SEH(a0, a0)") + +%def op_long_to_int(): +/* we ignore the high word, making this equivalent to a 32-bit reg move */ +% op_move() + +%def op_mul_int(): +% binop(instr="mul a0, a0, a1") + +%def op_mul_int_2addr(): +% binop2addr(instr="mul a0, a0, a1") + +%def op_mul_int_lit16(): +% binopLit16(instr="mul a0, a0, a1") + +%def op_mul_int_lit8(): +% binopLit8(instr="mul a0, a0, a1") + +%def op_mul_long(): + /* + * Signed 64-bit integer multiply. + * a1 a0 + * x a3 a2 + * ------------- + * a2a1 a2a0 + * a3a0 + * a3a1 (<= unused) + * --------------- + * v1 v0 + */ + /* mul-long vAA, vBB, vCC */ + FETCH(a0, 1) # a0 <- CCBB + and t0, a0, 255 # a2 <- BB + srl t1, a0, 8 # a3 <- CC + EAS2(t0, rFP, t0) # t0 <- &fp[BB] + LOAD64(a0, a1, t0) # a0/a1 <- vBB/vBB+1 + + EAS2(t1, rFP, t1) # t0 <- &fp[CC] + LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 + + mul v1, a3, a0 # v1= a3a0 +#ifdef MIPS32REVGE6 + mulu v0, a2, a0 # v0= a2a0 + muhu t1, a2, a0 +#else + multu a2, a0 + mfhi t1 + mflo v0 # v0= a2a0 +#endif + mul t0, a2, a1 # t0= a2a1 + addu v1, v1, t1 # v1+= hi(a2a0) + addu v1, v1, t0 # v1= a3a0 + a2a1; + + GET_OPA(a0) # a0 <- AA + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + b .L${opcode}_finish +%def op_mul_long_helper_code(): + +.Lop_mul_long_finish: + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG64_GOTO(v0, v1, a0, t0) # vAA/vAA+1 <- v0(low)/v1(high) + +%def op_mul_long_2addr(): + /* + * See op_mul_long.S for more details + */ + /* mul-long/2addr vA, vB */ + GET_OPA4(rOBJ) # rOBJ <- A+ + + EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] + LOAD64(a0, a1, t0) # vAA.low / high + + GET_OPB(t1) # t1 <- B + EAS2(t1, rFP, t1) # t1 <- &fp[B] + LOAD64(a2, a3, t1) # vBB.low / high + + mul v1, a3, a0 # v1= a3a0 +#ifdef MIPS32REVGE6 + mulu v0, a2, a0 # v0= a2a0 + muhu t1, a2, a0 +#else + multu a2, a0 + mfhi t1 + mflo v0 # v0= a2a0 + #endif + mul t2, a2, a1 # t2= a2a1 + addu v1, v1, t1 # v1= a3a0 + hi(a2a0) + addu v1, v1, t2 # v1= v1 + a2a1; + + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + GET_INST_OPCODE(t1) # extract opcode from rINST + SET_VREG64_GOTO(v0, v1, rOBJ, t1) # vA/vA+1 <- v0(low)/v1(high) + +%def op_neg_int(): +% unop(instr="negu a0, a0") + +%def op_neg_long(): +% unopWide(result0="v0", result1="v1", preinstr="negu v0, a0", instr="negu v1, a1; sltu a0, zero, v0; subu v1, v1, a0") + +%def op_not_int(): +% unop(instr="not a0, a0") + +%def op_not_long(): +% unopWide(preinstr="not a0, a0", instr="not a1, a1") + +%def op_or_int(): +% binop(instr="or a0, a0, a1") + +%def op_or_int_2addr(): +% binop2addr(instr="or a0, a0, a1") + +%def op_or_int_lit16(): +% binopLit16(instr="or a0, a0, a1") + +%def op_or_int_lit8(): +% binopLit8(instr="or a0, a0, a1") + +%def op_or_long(): +% binopWide(preinstr="or a0, a0, a2", instr="or a1, a1, a3") + +%def op_or_long_2addr(): +% binopWide2addr(preinstr="or a0, a0, a2", instr="or a1, a1, a3") + +%def op_rem_int(): +#ifdef MIPS32REVGE6 +% binop(instr="mod a0, a0, a1", chkzero="1") +#else +% binop(preinstr="div zero, a0, a1", instr="mfhi a0", chkzero="1") +#endif + +%def op_rem_int_2addr(): +#ifdef MIPS32REVGE6 +% binop2addr(instr="mod a0, a0, a1", chkzero="1") +#else +% binop2addr(preinstr="div zero, a0, a1", instr="mfhi a0", chkzero="1") +#endif + +%def op_rem_int_lit16(): +#ifdef MIPS32REVGE6 +% binopLit16(instr="mod a0, a0, a1", chkzero="1") +#else +% binopLit16(preinstr="div zero, a0, a1", instr="mfhi a0", chkzero="1") +#endif + +%def op_rem_int_lit8(): +#ifdef MIPS32REVGE6 +% binopLit8(instr="mod a0, a0, a1", chkzero="1") +#else +% binopLit8(preinstr="div zero, a0, a1", instr="mfhi a0", chkzero="1") +#endif + +%def op_rem_long(): +% binopWide(result0="v0", result1="v1", instr="JAL(__moddi3)", chkzero="1") + +%def op_rem_long_2addr(): +% binopWide2addr(result0="v0", result1="v1", instr="JAL(__moddi3)", chkzero="1") + +%def op_rsub_int(): +/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ +% binopLit16(instr="subu a0, a1, a0") + +%def op_rsub_int_lit8(): +% binopLit8(instr="subu a0, a1, a0") + +%def op_shl_int(): +% binop(instr="sll a0, a0, a1") + +%def op_shl_int_2addr(): +% binop2addr(instr="sll a0, a0, a1") + +%def op_shl_int_lit8(): +% binopLit8(instr="sll a0, a0, a1") + +%def op_shl_long(): + /* + * Long integer shift. This is different from the generic 32/64-bit + * binary operations because vAA/vBB are 64-bit but vCC (the shift + * distance) is 32-bit. Also, Dalvik requires us to mask off the low + * 6 bits of the shift distance. + */ + /* shl-long vAA, vBB, vCC */ + FETCH(a0, 1) # a0 <- CCBB + GET_OPA(t2) # t2 <- AA + and a3, a0, 255 # a3 <- BB + srl a0, a0, 8 # a0 <- CC + EAS2(a3, rFP, a3) # a3 <- &fp[BB] + GET_VREG(a2, a0) # a2 <- vCC + LOAD64(a0, a1, a3) # a0/a1 <- vBB/vBB+1 + + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + + andi v1, a2, 0x20 # shift< shift & 0x20 + sll v0, a0, a2 # rlo<- alo << (shift&31) + bnez v1, .L${opcode}_finish + not v1, a2 # rhi<- 31-shift (shift is 5b) + srl a0, 1 + srl a0, v1 # alo<- alo >> (32-(shift&31)) + sll v1, a1, a2 # rhi<- ahi << (shift&31) + or v1, a0 # rhi<- rhi | alo + SET_VREG64_GOTO(v0, v1, t2, t0) # vAA/vAA+1 <- v0/v1 +%def op_shl_long_helper_code(): + +.Lop_shl_long_finish: + SET_VREG64_GOTO(zero, v0, t2, t0) # vAA/vAA+1 <- rlo/rhi + +%def op_shl_long_2addr(): + /* + * Long integer shift, 2addr version. vA is 64-bit value/result, vB is + * 32-bit shift distance. + */ + /* shl-long/2addr vA, vB */ + GET_OPA4(rOBJ) # rOBJ <- A+ + GET_OPB(a3) # a3 <- B + GET_VREG(a2, a3) # a2 <- vB + EAS2(t2, rFP, rOBJ) # t2 <- &fp[A] + LOAD64(a0, a1, t2) # a0/a1 <- vA/vA+1 + + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + + andi v1, a2, 0x20 # shift< shift & 0x20 + sll v0, a0, a2 # rlo<- alo << (shift&31) + bnez v1, .L${opcode}_finish + not v1, a2 # rhi<- 31-shift (shift is 5b) + srl a0, 1 + srl a0, v1 # alo<- alo >> (32-(shift&31)) + sll v1, a1, a2 # rhi<- ahi << (shift&31) + or v1, a0 # rhi<- rhi | alo + SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vA/vA+1 <- v0/v1 +%def op_shl_long_2addr_helper_code(): + +.Lop_shl_long_2addr_finish: + SET_VREG64_GOTO(zero, v0, rOBJ, t0) # vA/vA+1 <- rlo/rhi + +%def op_shr_int(): +% binop(instr="sra a0, a0, a1") + +%def op_shr_int_2addr(): +% binop2addr(instr="sra a0, a0, a1") + +%def op_shr_int_lit8(): +% binopLit8(instr="sra a0, a0, a1") + +%def op_shr_long(): + /* + * Long integer shift. This is different from the generic 32/64-bit + * binary operations because vAA/vBB are 64-bit but vCC (the shift + * distance) is 32-bit. Also, Dalvik requires us to mask off the low + * 6 bits of the shift distance. + */ + /* shr-long vAA, vBB, vCC */ + FETCH(a0, 1) # a0 <- CCBB + GET_OPA(t3) # t3 <- AA + and a3, a0, 255 # a3 <- BB + srl a0, a0, 8 # a0 <- CC + EAS2(a3, rFP, a3) # a3 <- &fp[BB] + GET_VREG(a2, a0) # a2 <- vCC + LOAD64(a0, a1, a3) # a0/a1 <- vBB/vBB+1 + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + + andi v0, a2, 0x20 # shift & 0x20 + sra v1, a1, a2 # rhi<- ahi >> (shift&31) + bnez v0, .L${opcode}_finish + srl v0, a0, a2 # rlo<- alo >> (shift&31) + not a0, a2 # alo<- 31-shift (shift is 5b) + sll a1, 1 + sll a1, a0 # ahi<- ahi << (32-(shift&31)) + or v0, a1 # rlo<- rlo | ahi + SET_VREG64_GOTO(v0, v1, t3, t0) # vAA/VAA+1 <- v0/v1 +%def op_shr_long_helper_code(): + +.Lop_shr_long_finish: + sra a3, a1, 31 # a3<- sign(ah) + SET_VREG64_GOTO(v1, a3, t3, t0) # vAA/VAA+1 <- rlo/rhi + +%def op_shr_long_2addr(): + /* + * Long integer shift, 2addr version. vA is 64-bit value/result, vB is + * 32-bit shift distance. + */ + /* shr-long/2addr vA, vB */ + GET_OPA4(t2) # t2 <- A+ + GET_OPB(a3) # a3 <- B + GET_VREG(a2, a3) # a2 <- vB + EAS2(t0, rFP, t2) # t0 <- &fp[A] + LOAD64(a0, a1, t0) # a0/a1 <- vA/vA+1 + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + + andi v0, a2, 0x20 # shift & 0x20 + sra v1, a1, a2 # rhi<- ahi >> (shift&31) + bnez v0, .L${opcode}_finish + srl v0, a0, a2 # rlo<- alo >> (shift&31) + not a0, a2 # alo<- 31-shift (shift is 5b) + sll a1, 1 + sll a1, a0 # ahi<- ahi << (32-(shift&31)) + or v0, a1 # rlo<- rlo | ahi + SET_VREG64_GOTO(v0, v1, t2, t0) # vA/vA+1 <- v0/v1 +%def op_shr_long_2addr_helper_code(): + +.Lop_shr_long_2addr_finish: + sra a3, a1, 31 # a3<- sign(ah) + SET_VREG64_GOTO(v1, a3, t2, t0) # vA/vA+1 <- rlo/rhi + +%def op_sub_int(): +% binop(instr="subu a0, a0, a1") + +%def op_sub_int_2addr(): +% binop2addr(instr="subu a0, a0, a1") + +%def op_sub_long(): +/* + * For little endian the code sequence looks as follows: + * subu v0,a0,a2 + * subu v1,a1,a3 + * sltu a0,a0,v0 + * subu v1,v1,a0 + */ +% binopWide(result0="v0", result1="v1", preinstr="subu v0, a0, a2", instr="subu v1, a1, a3; sltu a0, a0, v0; subu v1, v1, a0") + +%def op_sub_long_2addr(): +/* + * See op_sub_long.S for more details + */ +% binopWide2addr(result0="v0", result1="v1", preinstr="subu v0, a0, a2", instr="subu v1, a1, a3; sltu a0, a0, v0; subu v1, v1, a0") + +%def op_ushr_int(): +% binop(instr="srl a0, a0, a1") + +%def op_ushr_int_2addr(): +% binop2addr(instr="srl a0, a0, a1 ") + +%def op_ushr_int_lit8(): +% binopLit8(instr="srl a0, a0, a1") + +%def op_ushr_long(): + /* + * Long integer shift. This is different from the generic 32/64-bit + * binary operations because vAA/vBB are 64-bit but vCC (the shift + * distance) is 32-bit. Also, Dalvik requires us to mask off the low + * 6 bits of the shift distance. + */ + /* ushr-long vAA, vBB, vCC */ + FETCH(a0, 1) # a0 <- CCBB + GET_OPA(rOBJ) # rOBJ <- AA + and a3, a0, 255 # a3 <- BB + srl a0, a0, 8 # a0 <- CC + EAS2(a3, rFP, a3) # a3 <- &fp[BB] + GET_VREG(a2, a0) # a2 <- vCC + LOAD64(a0, a1, a3) # a0/a1 <- vBB/vBB+1 + + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + + andi v0, a2, 0x20 # shift & 0x20 + srl v1, a1, a2 # rhi<- ahi >> (shift&31) + bnez v0, .L${opcode}_finish + srl v0, a0, a2 # rlo<- alo >> (shift&31) + not a0, a2 # alo<- 31-n (shift is 5b) + sll a1, 1 + sll a1, a0 # ahi<- ahi << (32-(shift&31)) + or v0, a1 # rlo<- rlo | ahi + SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vAA/vAA+1 <- v0/v1 +%def op_ushr_long_helper_code(): + +.Lop_ushr_long_finish: + SET_VREG64_GOTO(v1, zero, rOBJ, t0) # vAA/vAA+1 <- rlo/rhi + +%def op_ushr_long_2addr(): + /* + * Long integer shift, 2addr version. vA is 64-bit value/result, vB is + * 32-bit shift distance. + */ + /* ushr-long/2addr vA, vB */ + GET_OPA4(t3) # t3 <- A+ + GET_OPB(a3) # a3 <- B + GET_VREG(a2, a3) # a2 <- vB + EAS2(t0, rFP, t3) # t0 <- &fp[A] + LOAD64(a0, a1, t0) # a0/a1 <- vA/vA+1 + + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + + andi v0, a2, 0x20 # shift & 0x20 + srl v1, a1, a2 # rhi<- ahi >> (shift&31) + bnez v0, .L${opcode}_finish + srl v0, a0, a2 # rlo<- alo >> (shift&31) + not a0, a2 # alo<- 31-n (shift is 5b) + sll a1, 1 + sll a1, a0 # ahi<- ahi << (32-(shift&31)) + or v0, a1 # rlo<- rlo | ahi + SET_VREG64_GOTO(v0, v1, t3, t0) # vA/vA+1 <- v0/v1 +%def op_ushr_long_2addr_helper_code(): + +.Lop_ushr_long_2addr_finish: + SET_VREG64_GOTO(v1, zero, t3, t0) # vA/vA+1 <- rlo/rhi + +%def op_xor_int(): +% binop(instr="xor a0, a0, a1") + +%def op_xor_int_2addr(): +% binop2addr(instr="xor a0, a0, a1") + +%def op_xor_int_lit16(): +% binopLit16(instr="xor a0, a0, a1") + +%def op_xor_int_lit8(): +% binopLit8(instr="xor a0, a0, a1") + +%def op_xor_long(): +% binopWide(preinstr="xor a0, a0, a2", instr="xor a1, a1, a3") + +%def op_xor_long_2addr(): +% binopWide2addr(preinstr="xor a0, a0, a2", instr="xor a1, a1, a3") diff --git a/runtime/interpreter/mterp/mips/array.S b/runtime/interpreter/mterp/mips/array.S new file mode 100644 index 0000000000000000000000000000000000000000..57ab14743e16b8173f6df6c0391817184f7b87bd --- /dev/null +++ b/runtime/interpreter/mterp/mips/array.S @@ -0,0 +1,239 @@ +%def op_aget(load="lw", shift="2", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"): + /* + * Array get, 32 bits or less. vAA <- vBB[vCC]. + * + * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 + * instructions. We use a pair of FETCH_Bs instead. + * + * for: aget, aget-boolean, aget-byte, aget-char, aget-short + * + * NOTE: assumes data offset for arrays is the same for all non-wide types. + * If this changes, specialize. + */ + /* op vAA, vBB, vCC */ + FETCH_B(a2, 1, 0) # a2 <- BB + GET_OPA(rOBJ) # rOBJ <- AA + FETCH_B(a3, 1, 1) # a3 <- CC + GET_VREG(a0, a2) # a0 <- vBB (array object) + GET_VREG(a1, a3) # a1 <- vCC (requested index) + # null array object? + beqz a0, common_errNullObject # yes, bail + LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length + EASN(a0, a0, a1, $shift) # a0 <- arrayObj + index*width + # a1 >= a3; compare unsigned index + bgeu a1, a3, common_errArrayIndex # index >= length, bail + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + $load a2, $data_offset(a0) # a2 <- vBB[vCC] + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG_GOTO(a2, rOBJ, t0) # vAA <- a2 + +%def op_aget_boolean(): +% op_aget(load="lbu", shift="0", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") + +%def op_aget_byte(): +% op_aget(load="lb", shift="0", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") + +%def op_aget_char(): +% op_aget(load="lhu", shift="1", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") + +%def op_aget_object(): + /* + * Array object get. vAA <- vBB[vCC]. + * + * for: aget-object + */ + /* op vAA, vBB, vCC */ + FETCH_B(a2, 1, 0) # a2 <- BB + GET_OPA(rOBJ) # rOBJ <- AA + FETCH_B(a3, 1, 1) # a3 <- CC + EXPORT_PC() + GET_VREG(a0, a2) # a0 <- vBB (array object) + GET_VREG(a1, a3) # a1 <- vCC (requested index) + JAL(artAGetObjectFromMterp) # v0 <- GetObj(array, index) + lw a1, THREAD_EXCEPTION_OFFSET(rSELF) + PREFETCH_INST(2) # load rINST + bnez a1, MterpException + ADVANCE(2) # advance rPC + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG_OBJECT_GOTO(v0, rOBJ, t0) # vAA <- v0 + +%def op_aget_short(): +% op_aget(load="lh", shift="1", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") + +%def op_aget_wide(): + /* + * Array get, 64 bits. vAA <- vBB[vCC]. + * + * Arrays of long/double are 64-bit aligned. + */ + /* aget-wide vAA, vBB, vCC */ + FETCH(a0, 1) # a0 <- CCBB + GET_OPA(rOBJ) # rOBJ <- AA + and a2, a0, 255 # a2 <- BB + srl a3, a0, 8 # a3 <- CC + GET_VREG(a0, a2) # a0 <- vBB (array object) + GET_VREG(a1, a3) # a1 <- vCC (requested index) + # null array object? + beqz a0, common_errNullObject # yes, bail + LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length + EAS3(a0, a0, a1) # a0 <- arrayObj + index*width + bgeu a1, a3, common_errArrayIndex # index >= length, bail + + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + LOAD64_off(a2, a3, a0, MIRROR_WIDE_ARRAY_DATA_OFFSET) + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG64_GOTO(a2, a3, rOBJ, t0) # vAA/vAA+1 <- a2/a3 + +%def op_aput(store="sw", shift="2", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"): + + /* + * Array put, 32 bits or less. vBB[vCC] <- vAA. + * + * for: aput, aput-boolean, aput-byte, aput-char, aput-short + * + * NOTE: this assumes data offset for arrays is the same for all non-wide types. + * If this changes, specialize. + */ + /* op vAA, vBB, vCC */ + FETCH_B(a2, 1, 0) # a2 <- BB + GET_OPA(rOBJ) # rOBJ <- AA + FETCH_B(a3, 1, 1) # a3 <- CC + GET_VREG(a0, a2) # a0 <- vBB (array object) + GET_VREG(a1, a3) # a1 <- vCC (requested index) + # null array object? + beqz a0, common_errNullObject # yes, bail + LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length + EASN(a0, a0, a1, $shift) # a0 <- arrayObj + index*width + bgeu a1, a3, common_errArrayIndex # index >= length, bail + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + GET_VREG(a2, rOBJ) # a2 <- vAA + GET_INST_OPCODE(t0) # extract opcode from rINST + GET_OPCODE_TARGET(t0) + $store a2, $data_offset(a0) # vBB[vCC] <- a2 + JR(t0) # jump to next instruction + +%def op_aput_boolean(): +% op_aput(store="sb", shift="0", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") + +%def op_aput_byte(): +% op_aput(store="sb", shift="0", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") + +%def op_aput_char(): +% op_aput(store="sh", shift="1", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") + +%def op_aput_object(): + /* + * Store an object into an array. vBB[vCC] <- vAA. + * + */ + /* op vAA, vBB, vCC */ + EXPORT_PC() + addu a0, rFP, OFF_FP_SHADOWFRAME + move a1, rPC + move a2, rINST + JAL(MterpAputObject) + beqz v0, MterpPossibleException + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + GOTO_OPCODE(t0) # jump to next instruction + +%def op_aput_short(): +% op_aput(store="sh", shift="1", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") + +%def op_aput_wide(): + /* + * Array put, 64 bits. vBB[vCC] <- vAA. + */ + /* aput-wide vAA, vBB, vCC */ + FETCH(a0, 1) # a0 <- CCBB + GET_OPA(t0) # t0 <- AA + and a2, a0, 255 # a2 <- BB + srl a3, a0, 8 # a3 <- CC + GET_VREG(a0, a2) # a0 <- vBB (array object) + GET_VREG(a1, a3) # a1 <- vCC (requested index) + # null array object? + beqz a0, common_errNullObject # yes, bail + LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length + EAS3(a0, a0, a1) # a0 <- arrayObj + index*width + EAS2(rOBJ, rFP, t0) # rOBJ <- &fp[AA] + # compare unsigned index, length + bgeu a1, a3, common_errArrayIndex # index >= length, bail + + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + LOAD64(a2, a3, rOBJ) # a2/a3 <- vAA/vAA+1 + GET_INST_OPCODE(t0) # extract opcode from rINST + GET_OPCODE_TARGET(t0) + STORE64_off(a2, a3, a0, MIRROR_WIDE_ARRAY_DATA_OFFSET) # a2/a3 <- vBB[vCC] + JR(t0) # jump to next instruction + +%def op_array_length(): + /* + * Return the length of an array. + */ + /* array-length vA, vB */ + GET_OPB(a1) # a1 <- B + GET_OPA4(a2) # a2 <- A+ + GET_VREG(a0, a1) # a0 <- vB (object ref) + # is object null? + beqz a0, common_errNullObject # yup, fail + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + LOAD_base_offMirrorArray_length(a3, a0) # a3 <- array length + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG_GOTO(a3, a2, t0) # vA <- length + +%def op_fill_array_data(): + /* fill-array-data vAA, +BBBBBBBB */ + EXPORT_PC() + FETCH(a1, 1) # a1 <- bbbb (lo) + FETCH(a0, 2) # a0 <- BBBB (hi) + GET_OPA(a3) # a3 <- AA + INSERT_HIGH_HALF(a1, a0) # a1 <- BBBBbbbb + GET_VREG(a0, a3) # a0 <- vAA (array object) + EAS1(a1, rPC, a1) # a1 <- PC + BBBBbbbb*2 (array data off.) + JAL(MterpFillArrayData) # v0 <- Mterp(obj, payload) + beqz v0, MterpPossibleException # has exception + FETCH_ADVANCE_INST(3) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + GOTO_OPCODE(t0) # jump to next instruction + +%def op_filled_new_array(helper="MterpFilledNewArray"): + /* + * Create a new array with elements filled from registers. + * + * for: filled-new-array, filled-new-array/range + */ + /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ + /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ + .extern $helper + EXPORT_PC() + addu a0, rFP, OFF_FP_SHADOWFRAME # a0 <- shadow frame + move a1, rPC + move a2, rSELF + JAL($helper) # v0 <- helper(shadow_frame, pc, self) + beqz v0, MterpPossibleException # has exception + FETCH_ADVANCE_INST(3) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + GOTO_OPCODE(t0) # jump to next instruction + +%def op_filled_new_array_range(): +% op_filled_new_array(helper="MterpFilledNewArrayRange") + +%def op_new_array(): + /* + * Allocate an array of objects, specified with the array class + * and a count. + * + * The verifier guarantees that this is an array class, so we don't + * check for it here. + */ + /* new-array vA, vB, class@CCCC */ + EXPORT_PC() + addu a0, rFP, OFF_FP_SHADOWFRAME + move a1, rPC + move a2, rINST + move a3, rSELF + JAL(MterpNewArray) + beqz v0, MterpPossibleException + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + GOTO_OPCODE(t0) # jump to next instruction diff --git a/runtime/interpreter/mterp/mips/bincmp.S b/runtime/interpreter/mterp/mips/bincmp.S deleted file mode 100644 index 68df5c3ff09c1a7288fc6531b6cb5d8befa2a7b3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/bincmp.S +++ /dev/null @@ -1,18 +0,0 @@ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - GET_OPA4(a0) # a0 <- A+ - GET_OPB(a1) # a1 <- B - GET_VREG(a3, a1) # a3 <- vB - GET_VREG(a0, a0) # a0 <- vA - FETCH_S(rINST, 1) # rINST<- branch offset, in code units - b${condition} a0, a3, MterpCommonTakenBranchNoFlags # compare (vA, vB) - li t0, JIT_CHECK_OSR - beq rPROFILE, t0, .L_check_not_taken_osr - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction diff --git a/runtime/interpreter/mterp/mips/binop.S b/runtime/interpreter/mterp/mips/binop.S deleted file mode 100644 index 862d95a736560f5aa68d7c7aa6ef2cff02456688..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/binop.S +++ /dev/null @@ -1,32 +0,0 @@ -%default {"preinstr":"", "result":"a0", "chkzero":"0"} - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - srl a3, a0, 8 # a3 <- CC - and a2, a0, 255 # a2 <- BB - GET_VREG(a1, a3) # a1 <- vCC - GET_VREG(a0, a2) # a0 <- vBB - .if $chkzero - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - $preinstr # optional op - $instr # $result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO($result, rOBJ, t0) # vAA <- $result diff --git a/runtime/interpreter/mterp/mips/binop2addr.S b/runtime/interpreter/mterp/mips/binop2addr.S deleted file mode 100644 index 17aa8eba220f3ebb05401764903cab306fe7d2f9..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/binop2addr.S +++ /dev/null @@ -1,28 +0,0 @@ -%default {"preinstr":"", "result":"a0", "chkzero":"0"} - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a0, rOBJ) # a0 <- vA - GET_VREG(a1, a3) # a1 <- vB - .if $chkzero - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - $preinstr # optional op - $instr # $result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO($result, rOBJ, t0) # vA <- $result diff --git a/runtime/interpreter/mterp/mips/binopLit16.S b/runtime/interpreter/mterp/mips/binopLit16.S deleted file mode 100644 index 0696e7ab9296c1564d49719ef2e68a194fa9f7f4..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/binopLit16.S +++ /dev/null @@ -1,28 +0,0 @@ -%default {"preinstr":"", "result":"a0", "chkzero":"0"} - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, +CCCC */ - FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) - GET_OPB(a2) # a2 <- B - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_VREG(a0, a2) # a0 <- vB - .if $chkzero - # cmp a1, 0; is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - $preinstr # optional op - $instr # $result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO($result, rOBJ, t0) # vA <- $result diff --git a/runtime/interpreter/mterp/mips/binopLit8.S b/runtime/interpreter/mterp/mips/binopLit8.S deleted file mode 100644 index 382dd2b4cdaf6c70477c627865a58946ccab70e7..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/binopLit8.S +++ /dev/null @@ -1,30 +0,0 @@ -%default {"preinstr":"", "result":"a0", "chkzero":"0"} - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, +CC */ - FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a3, 255 # a2 <- BB - GET_VREG(a0, a2) # a0 <- vBB - sra a1, a3, 8 # a1 <- ssssssCC (sign extended) - .if $chkzero - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - $preinstr # optional op - $instr # $result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO($result, rOBJ, t0) # vAA <- $result diff --git a/runtime/interpreter/mterp/mips/binopWide.S b/runtime/interpreter/mterp/mips/binopWide.S deleted file mode 100644 index 604134d25293d9354e7248574ca0d8f8a36068b9..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/binopWide.S +++ /dev/null @@ -1,34 +0,0 @@ -%default {"preinstr":"", "result0":"a0", "result1":"a1", "chkzero":"0", "arg0":"a0", "arg1":"a1", "arg2":"a2", "arg3":"a3"} - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0-a1 op a2-a3". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register pair other than a0-a1, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a2-a3). Useful for integer division and modulus. - * - * for: add-long, sub-long, div-long, rem-long, and-long, or-long, - * xor-long - * - * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 # a3 <- CC - EAS2(a2, rFP, a2) # a2 <- &fp[BB] - EAS2(t1, rFP, a3) # a3 <- &fp[CC] - LOAD64($arg0, $arg1, a2) # a0/a1 <- vBB/vBB+1 - LOAD64($arg2, $arg3, t1) # a2/a3 <- vCC/vCC+1 - .if $chkzero - or t0, $arg2, $arg3 # second arg (a2-a3) is zero? - beqz t0, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - $preinstr # optional op - $instr # result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO($result0, $result1, rOBJ, t0) # vAA/vAA+1 <- $result0/$result1 diff --git a/runtime/interpreter/mterp/mips/binopWide2addr.S b/runtime/interpreter/mterp/mips/binopWide2addr.S deleted file mode 100644 index f96fdb23f07b60da064feb66f220fd89c3e3e3db..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/binopWide2addr.S +++ /dev/null @@ -1,30 +0,0 @@ -%default {"preinstr":"", "result0":"a0", "result1":"a1", "chkzero":"0", "arg0":"a0", "arg1":"a1", "arg2":"a2", "arg3":"a3"} - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0-a1 op a2-a3". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register pair other than a0-a1, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a2-a3). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a1) # a1 <- B - EAS2(a1, rFP, a1) # a1 <- &fp[B] - EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] - LOAD64($arg2, $arg3, a1) # a2/a3 <- vB/vB+1 - LOAD64($arg0, $arg1, t0) # a0/a1 <- vA/vA+1 - .if $chkzero - or t0, $arg2, $arg3 # second arg (a2-a3) is zero? - beqz t0, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - $preinstr # optional op - $instr # result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO($result0, $result1, rOBJ, t0) # vA/vA+1 <- $result0/$result1 diff --git a/runtime/interpreter/mterp/mips/const.S b/runtime/interpreter/mterp/mips/const.S deleted file mode 100644 index 5d8379dfb7a14cfad6a2a7572889948ae794a380..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/const.S +++ /dev/null @@ -1,17 +0,0 @@ -%default { "helper":"UndefinedConstHandler" } - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern $helper - EXPORT_PC() - FETCH(a0, 1) # a0 <- BBBB - GET_OPA(a1) # a1 <- AA - addu a2, rFP, OFF_FP_SHADOWFRAME # a2 <- shadow frame - move a3, rSELF - JAL($helper) # v0 <- Mterp(index, tgt_reg, shadow_frame, self) - PREFETCH_INST(2) # load rINST - bnez v0, MterpPossibleException - ADVANCE(2) # advance rPC - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction diff --git a/runtime/interpreter/mterp/mips/control_flow.S b/runtime/interpreter/mterp/mips/control_flow.S new file mode 100644 index 0000000000000000000000000000000000000000..88e1f0ed4b37af3ab37754e945e0185cc27d2b48 --- /dev/null +++ b/runtime/interpreter/mterp/mips/control_flow.S @@ -0,0 +1,214 @@ +%def bincmp(condition=""): + /* + * Generic two-operand compare-and-branch operation. Provide a "condition" + * fragment that specifies the comparison to perform. + * + * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le + */ + /* if-cmp vA, vB, +CCCC */ + GET_OPA4(a0) # a0 <- A+ + GET_OPB(a1) # a1 <- B + GET_VREG(a3, a1) # a3 <- vB + GET_VREG(a0, a0) # a0 <- vA + FETCH_S(rINST, 1) # rINST<- branch offset, in code units + b${condition} a0, a3, MterpCommonTakenBranchNoFlags # compare (vA, vB) + li t0, JIT_CHECK_OSR + beq rPROFILE, t0, .L_check_not_taken_osr + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + GOTO_OPCODE(t0) # jump to next instruction + +%def zcmp(condition=""): + /* + * Generic one-operand compare-and-branch operation. Provide a "condition" + * fragment that specifies the comparison to perform. + * + * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez + */ + /* if-cmp vAA, +BBBB */ + GET_OPA(a0) # a0 <- AA + GET_VREG(a0, a0) # a0 <- vAA + FETCH_S(rINST, 1) # rINST <- branch offset, in code units + b${condition} a0, zero, MterpCommonTakenBranchNoFlags + li t0, JIT_CHECK_OSR # possible OSR re-entry? + beq rPROFILE, t0, .L_check_not_taken_osr + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + GOTO_OPCODE(t0) # jump to next instruction + +%def op_goto(): + /* + * Unconditional branch, 8-bit offset. + * + * The branch distance is a signed code-unit offset, which we need to + * double to get a byte offset. + */ + /* goto +AA */ + sll a0, rINST, 16 # a0 <- AAxx0000 + sra rINST, a0, 24 # rINST <- ssssssAA (sign-extended) + b MterpCommonTakenBranchNoFlags + +%def op_goto_16(): + /* + * Unconditional branch, 16-bit offset. + * + * The branch distance is a signed code-unit offset, which we need to + * double to get a byte offset. + */ + /* goto/16 +AAAA */ + FETCH_S(rINST, 1) # rINST <- ssssAAAA (sign-extended) + b MterpCommonTakenBranchNoFlags + +%def op_goto_32(): + /* + * Unconditional branch, 32-bit offset. + * + * The branch distance is a signed code-unit offset, which we need to + * double to get a byte offset. + * + * Unlike most opcodes, this one is allowed to branch to itself, so + * our "backward branch" test must be "<=0" instead of "<0". + */ + /* goto/32 +AAAAAAAA */ + FETCH(rINST, 1) # rINST <- aaaa (lo) + FETCH(a1, 2) # a1 <- AAAA (hi) + INSERT_HIGH_HALF(rINST, a1) # rINST <- AAAAaaaa + b MterpCommonTakenBranchNoFlags + +%def op_if_eq(): +% bincmp(condition="eq") + +%def op_if_eqz(): +% zcmp(condition="eq") + +%def op_if_ge(): +% bincmp(condition="ge") + +%def op_if_gez(): +% zcmp(condition="ge") + +%def op_if_gt(): +% bincmp(condition="gt") + +%def op_if_gtz(): +% zcmp(condition="gt") + +%def op_if_le(): +% bincmp(condition="le") + +%def op_if_lez(): +% zcmp(condition="le") + +%def op_if_lt(): +% bincmp(condition="lt") + +%def op_if_ltz(): +% zcmp(condition="lt") + +%def op_if_ne(): +% bincmp(condition="ne") + +%def op_if_nez(): +% zcmp(condition="ne") + +%def op_packed_switch(func="MterpDoPackedSwitch"): + /* + * Handle a packed-switch or sparse-switch instruction. In both cases + * we decode it and hand it off to a helper function. + * + * We don't really expect backward branches in a switch statement, but + * they're perfectly legal, so we check for them here. + * + * for: packed-switch, sparse-switch + */ + /* op vAA, +BBBB */ + FETCH(a0, 1) # a0 <- bbbb (lo) + FETCH(a1, 2) # a1 <- BBBB (hi) + GET_OPA(a3) # a3 <- AA + INSERT_HIGH_HALF(a0, a1) # a0 <- BBBBbbbb + GET_VREG(a1, a3) # a1 <- vAA + EAS1(a0, rPC, a0) # a0 <- PC + BBBBbbbb*2 + JAL($func) # a0 <- code-unit branch offset + move rINST, v0 + b MterpCommonTakenBranchNoFlags + +%def op_return(): + /* + * Return a 32-bit value. + * + * for: return, return-object + */ + /* op vAA */ + .extern MterpThreadFenceForConstructor + JAL(MterpThreadFenceForConstructor) + lw ra, THREAD_FLAGS_OFFSET(rSELF) + move a0, rSELF + and ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST + beqz ra, 1f + JAL(MterpSuspendCheck) # (self) +1: + GET_OPA(a2) # a2 <- AA + GET_VREG(v0, a2) # v0 <- vAA + move v1, zero + b MterpReturn + +%def op_return_object(): +% op_return() + +%def op_return_void(): + .extern MterpThreadFenceForConstructor + JAL(MterpThreadFenceForConstructor) + lw ra, THREAD_FLAGS_OFFSET(rSELF) + move a0, rSELF + and ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST + beqz ra, 1f + JAL(MterpSuspendCheck) # (self) +1: + move v0, zero + move v1, zero + b MterpReturn + +%def op_return_void_no_barrier(): + lw ra, THREAD_FLAGS_OFFSET(rSELF) + move a0, rSELF + and ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST + beqz ra, 1f + JAL(MterpSuspendCheck) # (self) +1: + move v0, zero + move v1, zero + b MterpReturn + +%def op_return_wide(): + /* + * Return a 64-bit value. + */ + /* return-wide vAA */ + .extern MterpThreadFenceForConstructor + JAL(MterpThreadFenceForConstructor) + lw ra, THREAD_FLAGS_OFFSET(rSELF) + move a0, rSELF + and ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST + beqz ra, 1f + JAL(MterpSuspendCheck) # (self) +1: + GET_OPA(a2) # a2 <- AA + EAS2(a2, rFP, a2) # a2 <- &fp[AA] + LOAD64(v0, v1, a2) # v0/v1 <- vAA/vAA+1 + b MterpReturn + +%def op_sparse_switch(): +% op_packed_switch(func="MterpDoSparseSwitch") + +%def op_throw(): + /* + * Throw an exception object in the current thread. + */ + /* throw vAA */ + EXPORT_PC() # exception handler can throw + GET_OPA(a2) # a2 <- AA + GET_VREG(a1, a2) # a1 <- vAA (exception object) + # null object? + beqz a1, common_errNullObject # yes, throw an NPE instead + sw a1, THREAD_EXCEPTION_OFFSET(rSELF) # thread->exception <- obj + b MterpException diff --git a/runtime/interpreter/mterp/mips/entry.S b/runtime/interpreter/mterp/mips/entry.S deleted file mode 100644 index d342354969647d211507a47e5537e30399f847f6..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/entry.S +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -/* - * Interpreter entry point. - */ - - .text - .align 2 - .global ExecuteMterpImpl - .ent ExecuteMterpImpl - .frame sp, STACK_SIZE, ra -/* - * On entry: - * a0 Thread* self - * a1 dex_instructions - * a2 ShadowFrame - * a3 JValue* result_register - * - */ - -ExecuteMterpImpl: - .cfi_startproc - .set noreorder - .cpload t9 - .set reorder -/* Save to the stack. Frame size = STACK_SIZE */ - STACK_STORE_FULL() -/* This directive will make sure all subsequent jal restore gp at a known offset */ - .cprestore STACK_OFFSET_GP - - /* Remember the return register */ - sw a3, SHADOWFRAME_RESULT_REGISTER_OFFSET(a2) - - /* Remember the dex instruction pointer */ - sw a1, SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET(a2) - - /* set up "named" registers */ - move rSELF, a0 - lw a0, SHADOWFRAME_NUMBER_OF_VREGS_OFFSET(a2) - addu rFP, a2, SHADOWFRAME_VREGS_OFFSET # point to vregs. - EAS2(rREFS, rFP, a0) # point to reference array in shadow frame - lw a0, SHADOWFRAME_DEX_PC_OFFSET(a2) # Get starting dex_pc - EAS1(rPC, a1, a0) # Create direct pointer to 1st dex opcode - CFI_DEFINE_DEX_PC_WITH_OFFSET(CFI_TMP, CFI_DEX, 0) - - EXPORT_PC() - - /* Starting ibase */ - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) - - /* Set up for backwards branches & osr profiling */ - lw a0, OFF_FP_METHOD(rFP) - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rSELF - JAL(MterpSetUpHotnessCountdown) # (method, shadow_frame, self) - move rPROFILE, v0 # Starting hotness countdown to rPROFILE - - /* start executing the instruction at rPC */ - FETCH_INST() # load rINST from rPC - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - /* NOTE: no fallthrough */ diff --git a/runtime/interpreter/mterp/mips/fallback.S b/runtime/interpreter/mterp/mips/fallback.S deleted file mode 100644 index 82cbc6348064dc1fd6484f90d00d85c68406ce49..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/fallback.S +++ /dev/null @@ -1,2 +0,0 @@ -/* Transfer stub to alternate interpreter */ - b MterpFallback diff --git a/runtime/interpreter/mterp/mips/fbinop.S b/runtime/interpreter/mterp/mips/fbinop.S deleted file mode 100644 index 6c1468ccfa08def159b1fff3b2b12ef8803057b9..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/fbinop.S +++ /dev/null @@ -1,18 +0,0 @@ - /* - * Generic 32-bit binary float operation. - * - * For: add-fp, sub-fp, mul-fp, div-fp, rem-fp - */ - - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - srl a3, a0, 8 # a3 <- CC - and a2, a0, 255 # a2 <- BB - GET_VREG_F(fa1, a3) # a1 <- vCC - GET_VREG_F(fa0, a2) # a0 <- vBB - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - $instr # f0 = result - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_F_GOTO(fv0, rOBJ, t0) # vAA <- fv0 diff --git a/runtime/interpreter/mterp/mips/fbinop2addr.S b/runtime/interpreter/mterp/mips/fbinop2addr.S deleted file mode 100644 index 2caaf9cbbb046678e4481c9cab208cf2a4b14347..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/fbinop2addr.S +++ /dev/null @@ -1,18 +0,0 @@ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" - * that specifies an instruction that performs "fv0 = fa0 op fa1". - * This could be an MIPS instruction or a function call. - * - * For: add-float/2addr, sub-float/2addr, mul-float/2addr, - * div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG_F(fa0, rOBJ) - GET_VREG_F(fa1, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - $instr - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_F_GOTO(fv0, rOBJ, t0) # vA <- result diff --git a/runtime/interpreter/mterp/mips/fbinopWide.S b/runtime/interpreter/mterp/mips/fbinopWide.S deleted file mode 100644 index a1fe91e25c52a1464dd6e313f5bbf0f1bf3fd5b8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/fbinopWide.S +++ /dev/null @@ -1,23 +0,0 @@ - /* - * Generic 64-bit floating-point binary operation. Provide an "instr" - * line that specifies an instruction that performs "fv0 = fa0 op fa1". - * This could be an MIPS instruction or a function call. - * - * for: add-double, sub-double, mul-double, div-double, - * rem-double - * - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 # a3 <- CC - EAS2(a2, rFP, a2) # a2 <- &fp[BB] - EAS2(t1, rFP, a3) # a3 <- &fp[CC] - LOAD64_F(fa0, fa0f, a2) - LOAD64_F(fa1, fa1f, t1) - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - $instr - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vAA/vAA+1 <- fv0 diff --git a/runtime/interpreter/mterp/mips/fbinopWide2addr.S b/runtime/interpreter/mterp/mips/fbinopWide2addr.S deleted file mode 100644 index 73034411e13c5253bf9b24de1313a22c8161cf6c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/fbinopWide2addr.S +++ /dev/null @@ -1,21 +0,0 @@ - /* - * Generic 64-bit floating-point "/2addr" binary operation. - * Provide an "instr" line that specifies an instruction that - * performs "fv0 = fa0 op fa1". - * This could be an MIPS instruction or a function call. - * - * For: add-double/2addr, sub-double/2addr, mul-double/2addr, - * div-double/2addr, rem-double/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a1) # a1 <- B - EAS2(a1, rFP, a1) # a1 <- &fp[B] - EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] - LOAD64_F(fa0, fa0f, t0) - LOAD64_F(fa1, fa1f, a1) - - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - $instr - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vA/vA+1 <- fv0 diff --git a/runtime/interpreter/mterp/mips/field.S b/runtime/interpreter/mterp/mips/field.S deleted file mode 100644 index 1333ed77b7e1ed056329cae96075dc558158ee69..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/field.S +++ /dev/null @@ -1 +0,0 @@ -TODO diff --git a/runtime/interpreter/mterp/mips/floating_point.S b/runtime/interpreter/mterp/mips/floating_point.S new file mode 100644 index 0000000000000000000000000000000000000000..20df51e292cae12bee824406026f8e7660efbb0b --- /dev/null +++ b/runtime/interpreter/mterp/mips/floating_point.S @@ -0,0 +1,518 @@ +%def fbinop(instr=""): + /* + * Generic 32-bit binary float operation. + * + * For: add-fp, sub-fp, mul-fp, div-fp, rem-fp + */ + + /* binop vAA, vBB, vCC */ + FETCH(a0, 1) # a0 <- CCBB + GET_OPA(rOBJ) # rOBJ <- AA + srl a3, a0, 8 # a3 <- CC + and a2, a0, 255 # a2 <- BB + GET_VREG_F(fa1, a3) # a1 <- vCC + GET_VREG_F(fa0, a2) # a0 <- vBB + + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + $instr # f0 = result + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG_F_GOTO(fv0, rOBJ, t0) # vAA <- fv0 + +%def fbinop2addr(instr=""): + /* + * Generic 32-bit "/2addr" binary operation. Provide an "instr" + * that specifies an instruction that performs "fv0 = fa0 op fa1". + * This could be an MIPS instruction or a function call. + * + * For: add-float/2addr, sub-float/2addr, mul-float/2addr, + * div-float/2addr, rem-float/2addr + */ + /* binop/2addr vA, vB */ + GET_OPA4(rOBJ) # rOBJ <- A+ + GET_OPB(a3) # a3 <- B + GET_VREG_F(fa0, rOBJ) + GET_VREG_F(fa1, a3) + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + + $instr + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG_F_GOTO(fv0, rOBJ, t0) # vA <- result + +%def fbinopWide(instr=""): + /* + * Generic 64-bit floating-point binary operation. Provide an "instr" + * line that specifies an instruction that performs "fv0 = fa0 op fa1". + * This could be an MIPS instruction or a function call. + * + * for: add-double, sub-double, mul-double, div-double, + * rem-double + * + */ + /* binop vAA, vBB, vCC */ + FETCH(a0, 1) # a0 <- CCBB + GET_OPA(rOBJ) # rOBJ <- AA + and a2, a0, 255 # a2 <- BB + srl a3, a0, 8 # a3 <- CC + EAS2(a2, rFP, a2) # a2 <- &fp[BB] + EAS2(t1, rFP, a3) # a3 <- &fp[CC] + LOAD64_F(fa0, fa0f, a2) + LOAD64_F(fa1, fa1f, t1) + + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + $instr + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vAA/vAA+1 <- fv0 + +%def fbinopWide2addr(instr=""): + /* + * Generic 64-bit floating-point "/2addr" binary operation. + * Provide an "instr" line that specifies an instruction that + * performs "fv0 = fa0 op fa1". + * This could be an MIPS instruction or a function call. + * + * For: add-double/2addr, sub-double/2addr, mul-double/2addr, + * div-double/2addr, rem-double/2addr + */ + /* binop/2addr vA, vB */ + GET_OPA4(rOBJ) # rOBJ <- A+ + GET_OPB(a1) # a1 <- B + EAS2(a1, rFP, a1) # a1 <- &fp[B] + EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] + LOAD64_F(fa0, fa0f, t0) + LOAD64_F(fa1, fa1f, a1) + + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + $instr + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vA/vA+1 <- fv0 + +%def funop(instr=""): + /* + * Generic 32-bit floating-point unary operation. Provide an "instr" + * line that specifies an instruction that performs "fv0 = op fa0". + * This could be a MIPS instruction or a function call. + * + * for: int-to-float + */ + /* unop vA, vB */ + GET_OPB(a3) # a3 <- B + GET_OPA4(rOBJ) # rOBJ <- A+ + GET_VREG_F(fa0, a3) + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + $instr + GET_INST_OPCODE(t1) # extract opcode from rINST + SET_VREG_F_GOTO(fv0, rOBJ, t1) # vA <- fv0 + +%def funopWider(instr=""): + /* + * Generic 32bit-to-64bit floating-point unary operation. Provide an "instr" + * line that specifies an instruction that performs "fv0 = op fa0". + * + * For: int-to-double, float-to-double + */ + /* unop vA, vB */ + GET_OPA4(rOBJ) # rOBJ <- A+ + GET_OPB(a3) # a3 <- B + GET_VREG_F(fa0, a3) + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + $instr + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vA/vA+1 <- fv0 + +%def op_add_double(): +% fbinopWide(instr="add.d fv0, fa0, fa1") + +%def op_add_double_2addr(): +% fbinopWide2addr(instr="add.d fv0, fa0, fa1") + +%def op_add_float(): +% fbinop(instr="add.s fv0, fa0, fa1") + +%def op_add_float_2addr(): +% fbinop2addr(instr="add.s fv0, fa0, fa1") + +%def op_cmpg_double(): +% op_cmpl_double(gt_bias="1") + +%def op_cmpg_float(): +% op_cmpl_float(gt_bias="1") + +%def op_cmpl_double(gt_bias="0"): + /* + * Compare two floating-point values. Puts 0(==), 1(>), or -1(<) + * into the destination register based on the comparison results. + * + * For: cmpl-double, cmpg-double + */ + /* op vAA, vBB, vCC */ + + FETCH(a0, 1) # a0 <- CCBB + and rOBJ, a0, 255 # rOBJ <- BB + srl t0, a0, 8 # t0 <- CC + EAS2(rOBJ, rFP, rOBJ) # rOBJ <- &fp[BB] + EAS2(t0, rFP, t0) # t0 <- &fp[CC] + LOAD64_F(ft0, ft0f, rOBJ) + LOAD64_F(ft1, ft1f, t0) +#ifdef MIPS32REVGE6 + cmp.eq.d ft2, ft0, ft1 + li rTEMP, 0 + bc1nez ft2, 1f # done if vBB == vCC (ordered) + .if $gt_bias + cmp.lt.d ft2, ft0, ft1 + li rTEMP, -1 + bc1nez ft2, 1f # done if vBB < vCC (ordered) + li rTEMP, 1 # vBB > vCC or unordered + .else + cmp.lt.d ft2, ft1, ft0 + li rTEMP, 1 + bc1nez ft2, 1f # done if vBB > vCC (ordered) + li rTEMP, -1 # vBB < vCC or unordered + .endif +#else + c.eq.d fcc0, ft0, ft1 + li rTEMP, 0 + bc1t fcc0, 1f # done if vBB == vCC (ordered) + .if $gt_bias + c.olt.d fcc0, ft0, ft1 + li rTEMP, -1 + bc1t fcc0, 1f # done if vBB < vCC (ordered) + li rTEMP, 1 # vBB > vCC or unordered + .else + c.olt.d fcc0, ft1, ft0 + li rTEMP, 1 + bc1t fcc0, 1f # done if vBB > vCC (ordered) + li rTEMP, -1 # vBB < vCC or unordered + .endif +#endif +1: + GET_OPA(rOBJ) + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG_GOTO(rTEMP, rOBJ, t0) # vAA <- rTEMP + +%def op_cmpl_float(gt_bias="0"): + /* + * Compare two floating-point values. Puts 0(==), 1(>), or -1(<) + * into the destination register based on the comparison results. + * + * for: cmpl-float, cmpg-float + */ + /* op vAA, vBB, vCC */ + + FETCH(a0, 1) # a0 <- CCBB + and a2, a0, 255 # a2 <- BB + srl a3, a0, 8 + GET_VREG_F(ft0, a2) + GET_VREG_F(ft1, a3) +#ifdef MIPS32REVGE6 + cmp.eq.s ft2, ft0, ft1 + li rTEMP, 0 + bc1nez ft2, 1f # done if vBB == vCC (ordered) + .if $gt_bias + cmp.lt.s ft2, ft0, ft1 + li rTEMP, -1 + bc1nez ft2, 1f # done if vBB < vCC (ordered) + li rTEMP, 1 # vBB > vCC or unordered + .else + cmp.lt.s ft2, ft1, ft0 + li rTEMP, 1 + bc1nez ft2, 1f # done if vBB > vCC (ordered) + li rTEMP, -1 # vBB < vCC or unordered + .endif +#else + c.eq.s fcc0, ft0, ft1 + li rTEMP, 0 + bc1t fcc0, 1f # done if vBB == vCC (ordered) + .if $gt_bias + c.olt.s fcc0, ft0, ft1 + li rTEMP, -1 + bc1t fcc0, 1f # done if vBB < vCC (ordered) + li rTEMP, 1 # vBB > vCC or unordered + .else + c.olt.s fcc0, ft1, ft0 + li rTEMP, 1 + bc1t fcc0, 1f # done if vBB > vCC (ordered) + li rTEMP, -1 # vBB < vCC or unordered + .endif +#endif +1: + GET_OPA(rOBJ) + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG_GOTO(rTEMP, rOBJ, t0) # vAA <- rTEMP + +%def op_div_double(): +% fbinopWide(instr="div.d fv0, fa0, fa1") + +%def op_div_double_2addr(): +% fbinopWide2addr(instr="div.d fv0, fa0, fa1") + +%def op_div_float(): +% fbinop(instr="div.s fv0, fa0, fa1") + +%def op_div_float_2addr(): +% fbinop2addr(instr="div.s fv0, fa0, fa1") + +%def op_double_to_float(): +% unopNarrower(instr="cvt.s.d fv0, fa0") + +%def op_double_to_int(): + /* + * double-to-int + * + * We have to clip values to int min/max per the specification. The + * expected common case is a "reasonable" value that converts directly + * to modest integer. The EABI convert function isn't doing this for us + * for pre-R6. + */ + /* unop vA, vB */ + GET_OPB(a3) # a3 <- B + GET_OPA4(rOBJ) # rOBJ <- A+ + EAS2(a3, rFP, a3) # a3 <- &fp[B] + LOAD64_F(fa0, fa0f, a3) + FETCH_ADVANCE_INST(1) # advance rPC, load rINST +#ifndef MIPS32REVGE6 + li t0, INT_MIN_AS_DOUBLE_HIGH + mtc1 zero, fa1 + MOVE_TO_FPU_HIGH(t0, fa1, fa1f) + c.ole.d fcc0, fa1, fa0 +#endif + GET_INST_OPCODE(t1) # extract opcode from rINST +#ifndef MIPS32REVGE6 + bc1t fcc0, 1f # if INT_MIN <= vB, proceed to truncation + c.eq.d fcc0, fa0, fa0 + mtc1 zero, fa0 + MOVE_TO_FPU_HIGH(zero, fa0, fa0f) + movt.d fa0, fa1, fcc0 # fa0 = ordered(vB) ? INT_MIN_AS_DOUBLE : 0 +1: +#endif + trunc.w.d fa0, fa0 + SET_VREG_F_GOTO(fa0, rOBJ, t1) # vA <- result + +%def op_double_to_long(): + /* + * double-to-long + * + * We have to clip values to long min/max per the specification. The + * expected common case is a "reasonable" value that converts directly + * to modest integer. The EABI convert function isn't doing this for us + * for pre-R6. + */ + /* unop vA, vB */ + GET_OPA4(rOBJ) # rOBJ <- A+ + GET_OPB(a3) # a3 <- B + EAS2(a3, rFP, a3) # a3 <- &fp[B] + LOAD64_F(fa0, fa0f, a3) + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + +#ifdef MIPS32REVGE6 + GET_INST_OPCODE(t1) # extract opcode from rINST + trunc.l.d fa0, fa0 + SET_VREG64_F_GOTO(fa0, fa0f, rOBJ, t1) # vA <- result +#else + c.eq.d fcc0, fa0, fa0 + li rRESULT0, 0 + li rRESULT1, 0 + bc1f fcc0, .L${opcode}_get_opcode + + li t0, LONG_MIN_AS_DOUBLE_HIGH + mtc1 zero, fa1 + MOVE_TO_FPU_HIGH(t0, fa1, fa1f) + c.ole.d fcc0, fa0, fa1 + li rRESULT1, LONG_MIN_HIGH + bc1t fcc0, .L${opcode}_get_opcode + + neg.d fa1, fa1 + c.ole.d fcc0, fa1, fa0 + nor rRESULT0, rRESULT0, zero + nor rRESULT1, rRESULT1, zero + bc1t fcc0, .L${opcode}_get_opcode + + JAL(__fixdfdi) + GET_INST_OPCODE(t1) # extract opcode from rINST + b .L${opcode}_set_vreg +#endif +%def op_double_to_long_helper_code(): + +#ifndef MIPS32REVGE6 +.Lop_double_to_long_get_opcode: + GET_INST_OPCODE(t1) # extract opcode from rINST +.Lop_double_to_long_set_vreg: + SET_VREG64_GOTO(rRESULT0, rRESULT1, rOBJ, t1) # vA/vA+1 <- v0/v1 +#endif + +%def op_float_to_double(): +% funopWider(instr="cvt.d.s fv0, fa0") + +%def op_float_to_int(): + /* + * float-to-int + * + * We have to clip values to int min/max per the specification. The + * expected common case is a "reasonable" value that converts directly + * to modest integer. The EABI convert function isn't doing this for us + * for pre-R6. + */ + /* unop vA, vB */ + GET_OPB(a3) # a3 <- B + GET_OPA4(rOBJ) # rOBJ <- A+ + GET_VREG_F(fa0, a3) + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + +#ifndef MIPS32REVGE6 + li t0, INT_MIN_AS_FLOAT + mtc1 t0, fa1 + c.ole.s fcc0, fa1, fa0 +#endif + GET_INST_OPCODE(t1) # extract opcode from rINST +#ifndef MIPS32REVGE6 + bc1t fcc0, 1f # if INT_MIN <= vB, proceed to truncation + c.eq.s fcc0, fa0, fa0 + mtc1 zero, fa0 + movt.s fa0, fa1, fcc0 # fa0 = ordered(vB) ? INT_MIN_AS_FLOAT : 0 +1: +#endif + trunc.w.s fa0, fa0 + SET_VREG_F_GOTO(fa0, rOBJ, t1) # vA <- result + +%def op_float_to_long(): + /* + * float-to-long + * + * We have to clip values to long min/max per the specification. The + * expected common case is a "reasonable" value that converts directly + * to modest integer. The EABI convert function isn't doing this for us + * for pre-R6. + */ + /* unop vA, vB */ + GET_OPA4(rOBJ) # rOBJ <- A+ + GET_OPB(a3) # a3 <- B + GET_VREG_F(fa0, a3) + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + +#ifdef MIPS32REVGE6 + GET_INST_OPCODE(t1) # extract opcode from rINST + trunc.l.s fa0, fa0 + SET_VREG64_F_GOTO(fa0, fa0f, rOBJ, t1) # vA <- result +#else + c.eq.s fcc0, fa0, fa0 + li rRESULT0, 0 + li rRESULT1, 0 + bc1f fcc0, .L${opcode}_get_opcode + + li t0, LONG_MIN_AS_FLOAT + mtc1 t0, fa1 + c.ole.s fcc0, fa0, fa1 + li rRESULT1, LONG_MIN_HIGH + bc1t fcc0, .L${opcode}_get_opcode + + neg.s fa1, fa1 + c.ole.s fcc0, fa1, fa0 + nor rRESULT0, rRESULT0, zero + nor rRESULT1, rRESULT1, zero + bc1t fcc0, .L${opcode}_get_opcode + + JAL(__fixsfdi) + GET_INST_OPCODE(t1) # extract opcode from rINST + b .L${opcode}_set_vreg +#endif +%def op_float_to_long_helper_code(): + +#ifndef MIPS32REVGE6 +.Lop_float_to_long_get_opcode: + GET_INST_OPCODE(t1) # extract opcode from rINST +.Lop_float_to_long_set_vreg: + SET_VREG64_GOTO(rRESULT0, rRESULT1, rOBJ, t1) # vA/vA+1 <- v0/v1 +#endif + +%def op_int_to_double(): +% funopWider(instr="cvt.d.w fv0, fa0") + +%def op_int_to_float(): +% funop(instr="cvt.s.w fv0, fa0") + +%def op_long_to_double(): + /* + * long-to-double + */ + /* unop vA, vB */ + GET_OPA4(rOBJ) # rOBJ <- A+ + GET_OPB(a3) # a3 <- B + EAS2(a3, rFP, a3) # a3 <- &fp[B] + +#ifdef MIPS32REVGE6 + LOAD64_F(fv0, fv0f, a3) + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + cvt.d.l fv0, fv0 +#else + LOAD64(rARG0, rARG1, a3) + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + JAL(__floatdidf) # a0/a1 <- op, a2-a3 changed +#endif + + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vA/vA+1 <- result + +%def op_long_to_float(): + /* + * long-to-float + */ + /* unop vA, vB */ + GET_OPB(a3) # a3 <- B + GET_OPA4(rOBJ) # rOBJ <- A+ + EAS2(a3, rFP, a3) # a3 <- &fp[B] + +#ifdef MIPS32REVGE6 + LOAD64_F(fv0, fv0f, a3) + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + cvt.s.l fv0, fv0 +#else + LOAD64(rARG0, rARG1, a3) + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + JAL(__floatdisf) +#endif + + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG_F_GOTO(fv0, rOBJ, t0) # vA <- fv0 + +%def op_mul_double(): +% fbinopWide(instr="mul.d fv0, fa0, fa1") + +%def op_mul_double_2addr(): +% fbinopWide2addr(instr="mul.d fv0, fa0, fa1") + +%def op_mul_float(): +% fbinop(instr="mul.s fv0, fa0, fa1") + +%def op_mul_float_2addr(): +% fbinop2addr(instr="mul.s fv0, fa0, fa1") + +%def op_neg_double(): +% unopWide(instr="addu a1, a1, 0x80000000") + +%def op_neg_float(): +% unop(instr="addu a0, a0, 0x80000000") + +%def op_rem_double(): +% fbinopWide(instr="JAL(fmod)") + +%def op_rem_double_2addr(): +% fbinopWide2addr(instr="JAL(fmod)") + +%def op_rem_float(): +% fbinop(instr="JAL(fmodf)") + +%def op_rem_float_2addr(): +% fbinop2addr(instr="JAL(fmodf)") + +%def op_sub_double(): +% fbinopWide(instr="sub.d fv0, fa0, fa1") + +%def op_sub_double_2addr(): +% fbinopWide2addr(instr="sub.d fv0, fa0, fa1") + +%def op_sub_float(): +% fbinop(instr="sub.s fv0, fa0, fa1") + +%def op_sub_float_2addr(): +% fbinop2addr(instr="sub.s fv0, fa0, fa1") diff --git a/runtime/interpreter/mterp/mips/footer.S b/runtime/interpreter/mterp/mips/footer.S deleted file mode 100644 index 1c784ef188c564748f782e32da03481420c748d1..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/footer.S +++ /dev/null @@ -1,288 +0,0 @@ -/* - * =========================================================================== - * Common subroutines and data - * =========================================================================== - */ - - .text - .align 2 - -/* - * We've detected a condition that will result in an exception, but the exception - * has not yet been thrown. Just bail out to the reference interpreter to deal with it. - * TUNING: for consistency, we may want to just go ahead and handle these here. - */ -common_errDivideByZero: - EXPORT_PC() -#if MTERP_LOGGING - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - JAL(MterpLogDivideByZeroException) -#endif - b MterpCommonFallback - -common_errArrayIndex: - EXPORT_PC() -#if MTERP_LOGGING - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - JAL(MterpLogArrayIndexException) -#endif - b MterpCommonFallback - -common_errNegativeArraySize: - EXPORT_PC() -#if MTERP_LOGGING - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - JAL(MterpLogNegativeArraySizeException) -#endif - b MterpCommonFallback - -common_errNoSuchMethod: - EXPORT_PC() -#if MTERP_LOGGING - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - JAL(MterpLogNoSuchMethodException) -#endif - b MterpCommonFallback - -common_errNullObject: - EXPORT_PC() -#if MTERP_LOGGING - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - JAL(MterpLogNullObjectException) -#endif - b MterpCommonFallback - -common_exceptionThrown: - EXPORT_PC() -#if MTERP_LOGGING - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - JAL(MterpLogExceptionThrownException) -#endif - b MterpCommonFallback - -MterpSuspendFallback: - EXPORT_PC() -#if MTERP_LOGGING - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - lw a2, THREAD_FLAGS_OFFSET(rSELF) - JAL(MterpLogSuspendFallback) -#endif - b MterpCommonFallback - -/* - * If we're here, something is out of the ordinary. If there is a pending - * exception, handle it. Otherwise, roll back and retry with the reference - * interpreter. - */ -MterpPossibleException: - lw a0, THREAD_EXCEPTION_OFFSET(rSELF) - beqz a0, MterpFallback # If exception, fall back to reference interpreter. - /* intentional fallthrough - handle pending exception. */ -/* - * On return from a runtime helper routine, we've found a pending exception. - * Can we handle it here - or need to bail out to caller? - * - */ -MterpException: - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - JAL(MterpHandleException) # (self, shadow_frame) - beqz v0, MterpExceptionReturn # no local catch, back to caller. - lw a0, OFF_FP_DEX_INSTRUCTIONS(rFP) - lw a1, OFF_FP_DEX_PC(rFP) - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) - EAS1(rPC, a0, a1) # generate new dex_pc_ptr - /* Do we need to switch interpreters? */ - JAL(MterpShouldSwitchInterpreters) - bnez v0, MterpFallback - /* resume execution at catch block */ - EXPORT_PC() - FETCH_INST() - GET_INST_OPCODE(t0) - GOTO_OPCODE(t0) - /* NOTE: no fallthrough */ - -/* - * Common handling for branches with support for Jit profiling. - * On entry: - * rINST <= signed offset - * rPROFILE <= signed hotness countdown (expanded to 32 bits) - * - * We have quite a few different cases for branch profiling, OSR detection and - * suspend check support here. - * - * Taken backward branches: - * If profiling active, do hotness countdown and report if we hit zero. - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * Is there a pending suspend request? If so, suspend. - * - * Taken forward branches and not-taken backward branches: - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * - * Our most common case is expected to be a taken backward branch with active jit profiling, - * but no full OSR check and no pending suspend request. - * Next most common case is not-taken branch with no full OSR check. - */ -MterpCommonTakenBranchNoFlags: - bgtz rINST, .L_forward_branch # don't add forward branches to hotness -/* - * We need to subtract 1 from positive values and we should not see 0 here, - * so we may use the result of the comparison with -1. - */ -#if JIT_CHECK_OSR != -1 -# error "JIT_CHECK_OSR must be -1." -#endif - li t0, JIT_CHECK_OSR - beq rPROFILE, t0, .L_osr_check - blt rPROFILE, t0, .L_resume_backward_branch - subu rPROFILE, 1 - beqz rPROFILE, .L_add_batch # counted down to zero - report -.L_resume_backward_branch: - lw ra, THREAD_FLAGS_OFFSET(rSELF) - REFRESH_IBASE() - addu a2, rINST, rINST # a2<- byte offset - FETCH_ADVANCE_INST_RB(a2) # update rPC, load rINST - and ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - bnez ra, .L_suspend_request_pending - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - -.L_suspend_request_pending: - EXPORT_PC() - move a0, rSELF - JAL(MterpSuspendCheck) # (self) - bnez v0, MterpFallback - REFRESH_IBASE() # might have changed during suspend - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - -.L_no_count_backwards: - li t0, JIT_CHECK_OSR # check for possible OSR re-entry - bne rPROFILE, t0, .L_resume_backward_branch -.L_osr_check: - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rINST - EXPORT_PC() - JAL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) - bnez v0, MterpOnStackReplacement - b .L_resume_backward_branch - -.L_forward_branch: - li t0, JIT_CHECK_OSR # check for possible OSR re-entry - beq rPROFILE, t0, .L_check_osr_forward -.L_resume_forward_branch: - add a2, rINST, rINST # a2<- byte offset - FETCH_ADVANCE_INST_RB(a2) # update rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - -.L_check_osr_forward: - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rINST - EXPORT_PC() - JAL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) - bnez v0, MterpOnStackReplacement - b .L_resume_forward_branch - -.L_add_batch: - addu a1, rFP, OFF_FP_SHADOWFRAME - sh rPROFILE, SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET(a1) - lw a0, OFF_FP_METHOD(rFP) - move a2, rSELF - JAL(MterpAddHotnessBatch) # (method, shadow_frame, self) - move rPROFILE, v0 # restore new hotness countdown to rPROFILE - b .L_no_count_backwards - -/* - * Entered from the conditional branch handlers when OSR check request active on - * not-taken path. All Dalvik not-taken conditional branch offsets are 2. - */ -.L_check_not_taken_osr: - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - li a2, 2 - EXPORT_PC() - JAL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) - bnez v0, MterpOnStackReplacement - FETCH_ADVANCE_INST(2) - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - -/* - * On-stack replacement has happened, and now we've returned from the compiled method. - */ -MterpOnStackReplacement: -#if MTERP_LOGGING - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rINST - JAL(MterpLogOSR) -#endif - li v0, 1 # Signal normal return - b MterpDone - -/* - * Bail out to reference interpreter. - */ -MterpFallback: - EXPORT_PC() -#if MTERP_LOGGING - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - JAL(MterpLogFallback) -#endif -MterpCommonFallback: - move v0, zero # signal retry with reference interpreter. - b MterpDone -/* - * We pushed some registers on the stack in ExecuteMterpImpl, then saved - * SP and LR. Here we restore SP, restore the registers, and then restore - * LR to PC. - * - * On entry: - * uint32_t* rFP (should still be live, pointer to base of vregs) - */ -MterpExceptionReturn: - li v0, 1 # signal return to caller. - b MterpDone -MterpReturn: - lw a2, OFF_FP_RESULT_REGISTER(rFP) - sw v0, 0(a2) - sw v1, 4(a2) - li v0, 1 # signal return to caller. -MterpDone: -/* - * At this point, we expect rPROFILE to be non-zero. If negative, hotness is disabled or we're - * checking for OSR. If greater than zero, we might have unreported hotness to register - * (the difference between the ending rPROFILE and the cached hotness counter). rPROFILE - * should only reach zero immediately after a hotness decrement, and is then reset to either - * a negative special state or the new non-zero countdown value. - */ - blez rPROFILE, .L_pop_and_return # if > 0, we may have some counts to report. - -MterpProfileActive: - move rINST, v0 # stash return value - /* Report cached hotness counts */ - lw a0, OFF_FP_METHOD(rFP) - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rSELF - sh rPROFILE, SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET(a1) - JAL(MterpAddHotnessBatch) # (method, shadow_frame, self) - move v0, rINST # restore return value - -.L_pop_and_return: -/* Restore from the stack and return. Frame size = STACK_SIZE */ - STACK_LOAD_FULL() - jalr zero, ra - - .cfi_endproc - .end ExecuteMterpImpl diff --git a/runtime/interpreter/mterp/mips/funop.S b/runtime/interpreter/mterp/mips/funop.S deleted file mode 100644 index b2b22c97946fd692e2680073fc8157661821fafd..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/funop.S +++ /dev/null @@ -1,15 +0,0 @@ - /* - * Generic 32-bit floating-point unary operation. Provide an "instr" - * line that specifies an instruction that performs "fv0 = op fa0". - * This could be a MIPS instruction or a function call. - * - * for: int-to-float - */ - /* unop vA, vB */ - GET_OPB(a3) # a3 <- B - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_VREG_F(fa0, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - $instr - GET_INST_OPCODE(t1) # extract opcode from rINST - SET_VREG_F_GOTO(fv0, rOBJ, t1) # vA <- fv0 diff --git a/runtime/interpreter/mterp/mips/funopWider.S b/runtime/interpreter/mterp/mips/funopWider.S deleted file mode 100644 index 6862e245309782007fcdff23dc759c89a69ab03f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/funopWider.S +++ /dev/null @@ -1,14 +0,0 @@ - /* - * Generic 32bit-to-64bit floating-point unary operation. Provide an "instr" - * line that specifies an instruction that performs "fv0 = op fa0". - * - * For: int-to-double, float-to-double - */ - /* unop vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG_F(fa0, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - $instr - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vA/vA+1 <- fv0 diff --git a/runtime/interpreter/mterp/mips/instruction_end.S b/runtime/interpreter/mterp/mips/instruction_end.S deleted file mode 100644 index 32c725c7d9655633fcd95e67023080ff36bdc515..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/instruction_end.S +++ /dev/null @@ -1,3 +0,0 @@ - - .global artMterpAsmInstructionEnd -artMterpAsmInstructionEnd: diff --git a/runtime/interpreter/mterp/mips/instruction_end_alt.S b/runtime/interpreter/mterp/mips/instruction_end_alt.S deleted file mode 100644 index f90916fc02cda411d0a0c9c40c77bb3c6848793c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/instruction_end_alt.S +++ /dev/null @@ -1,3 +0,0 @@ - - .global artMterpAsmAltInstructionEnd -artMterpAsmAltInstructionEnd: diff --git a/runtime/interpreter/mterp/mips/instruction_end_sister.S b/runtime/interpreter/mterp/mips/instruction_end_sister.S deleted file mode 100644 index c5f4886697bb135e2a6a8bd74cf2fb7df2e5fab0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/instruction_end_sister.S +++ /dev/null @@ -1,3 +0,0 @@ - - .global artMterpAsmSisterEnd -artMterpAsmSisterEnd: diff --git a/runtime/interpreter/mterp/mips/instruction_start.S b/runtime/interpreter/mterp/mips/instruction_start.S deleted file mode 100644 index 8874c205404d9f5012a99d67dfd2ef472160d109..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/instruction_start.S +++ /dev/null @@ -1,4 +0,0 @@ - - .global artMterpAsmInstructionStart -artMterpAsmInstructionStart = .L_op_nop - .text diff --git a/runtime/interpreter/mterp/mips/instruction_start_alt.S b/runtime/interpreter/mterp/mips/instruction_start_alt.S deleted file mode 100644 index 0c9ffdb7d6c01b8470682ee5715d27a475517e5b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/instruction_start_alt.S +++ /dev/null @@ -1,4 +0,0 @@ - - .global artMterpAsmAltInstructionStart -artMterpAsmAltInstructionStart = .L_ALT_op_nop - .text diff --git a/runtime/interpreter/mterp/mips/instruction_start_sister.S b/runtime/interpreter/mterp/mips/instruction_start_sister.S deleted file mode 100644 index 2ec51f7261de40fd2ad0d3ba9ed6826bf532d43e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/instruction_start_sister.S +++ /dev/null @@ -1,5 +0,0 @@ - - .global artMterpAsmSisterStart - .text - .balign 4 -artMterpAsmSisterStart: diff --git a/runtime/interpreter/mterp/mips/invoke.S b/runtime/interpreter/mterp/mips/invoke.S index db3b8af73a7fd69dd7bd0472ade2b451799f7cd9..c77d12b506bc07cc1d40b2d052874ee812bcd331 100644 --- a/runtime/interpreter/mterp/mips/invoke.S +++ b/runtime/interpreter/mterp/mips/invoke.S @@ -1,4 +1,4 @@ -%default { "helper":"UndefinedInvokeHandler" } +%def invoke(helper="UndefinedInvokeHandler"): /* * Generic invoke handler wrapper. */ @@ -17,3 +17,71 @@ bnez v0, MterpFallback GET_INST_OPCODE(t0) GOTO_OPCODE(t0) + +%def invoke_polymorphic(helper="UndefinedInvokeHandler"): + /* + * invoke-polymorphic handler wrapper. + */ + /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ + /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ + .extern $helper + EXPORT_PC() + move a0, rSELF + addu a1, rFP, OFF_FP_SHADOWFRAME + move a2, rPC + move a3, rINST + JAL($helper) + beqz v0, MterpException + FETCH_ADVANCE_INST(4) + JAL(MterpShouldSwitchInterpreters) + bnez v0, MterpFallback + GET_INST_OPCODE(t0) + GOTO_OPCODE(t0) + +%def op_invoke_custom(): +% invoke(helper="MterpInvokeCustom") + +%def op_invoke_custom_range(): +% invoke(helper="MterpInvokeCustomRange") + +%def op_invoke_direct(): +% invoke(helper="MterpInvokeDirect") + +%def op_invoke_direct_range(): +% invoke(helper="MterpInvokeDirectRange") + +%def op_invoke_interface(): +% invoke(helper="MterpInvokeInterface") + +%def op_invoke_interface_range(): +% invoke(helper="MterpInvokeInterfaceRange") + +%def op_invoke_polymorphic(): +% invoke_polymorphic(helper="MterpInvokePolymorphic") + +%def op_invoke_polymorphic_range(): +% invoke_polymorphic(helper="MterpInvokePolymorphicRange") + +%def op_invoke_static(): +% invoke(helper="MterpInvokeStatic") + +%def op_invoke_static_range(): +% invoke(helper="MterpInvokeStaticRange") + +%def op_invoke_super(): +% invoke(helper="MterpInvokeSuper") + +%def op_invoke_super_range(): +% invoke(helper="MterpInvokeSuperRange") + +%def op_invoke_virtual(): +% invoke(helper="MterpInvokeVirtual") + +%def op_invoke_virtual_quick(): +% invoke(helper="MterpInvokeVirtualQuick") + +%def op_invoke_virtual_range(): +% invoke(helper="MterpInvokeVirtualRange") + +%def op_invoke_virtual_range_quick(): +% invoke(helper="MterpInvokeVirtualQuickRange") diff --git a/runtime/interpreter/mterp/mips/invoke_polymorphic.S b/runtime/interpreter/mterp/mips/invoke_polymorphic.S deleted file mode 100644 index 5c963f0314d62a7b1102dafde28619e095ec8984..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/invoke_polymorphic.S +++ /dev/null @@ -1,19 +0,0 @@ -%default { "helper":"UndefinedInvokeHandler" } - /* - * invoke-polymorphic handler wrapper. - */ - /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ - .extern $helper - EXPORT_PC() - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - JAL($helper) - beqz v0, MterpException - FETCH_ADVANCE_INST(4) - JAL(MterpShouldSwitchInterpreters) - bnez v0, MterpFallback - GET_INST_OPCODE(t0) - GOTO_OPCODE(t0) diff --git a/runtime/interpreter/mterp/mips/header.S b/runtime/interpreter/mterp/mips/main.S similarity index 59% rename from runtime/interpreter/mterp/mips/header.S rename to runtime/interpreter/mterp/mips/main.S index bef9eeb7f2d30c74546774bcc33a43dafd034555..02c59b13e0953ca0cfd22a989f4716ea75901510 100644 --- a/runtime/interpreter/mterp/mips/header.S +++ b/runtime/interpreter/mterp/mips/main.S @@ -1,3 +1,4 @@ +%def header(): /* * Copyright (C) 2016 The Android Open Source Project * @@ -663,7 +664,6 @@ #define STORE64_F(rlo, rhi, rbase) STORE64_off_F(rlo, rhi, rbase, 0) #define LOAD64_F(rlo, rhi, rbase) LOAD64_off_F(rlo, rhi, rbase, 0) - #define LOAD_base_offMirrorArray_length(rd, rbase) LOAD_RB_OFF(rd, rbase, MIRROR_ARRAY_LENGTH_OFFSET) #define STACK_STORE(rd, off) sw rd, off(sp) @@ -725,3 +725,423 @@ #define LONG_MIN_HIGH 0x80000000 #define LONG_MIN_AS_FLOAT 0xDF000000 #define LONG_MIN_AS_DOUBLE_HIGH 0xC3E00000 + +%def entry(): +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* + * Interpreter entry point. + */ + + .text + .align 2 + .global ExecuteMterpImpl + .ent ExecuteMterpImpl + .frame sp, STACK_SIZE, ra +/* + * On entry: + * a0 Thread* self + * a1 dex_instructions + * a2 ShadowFrame + * a3 JValue* result_register + * + */ + +ExecuteMterpImpl: + .cfi_startproc + .set noreorder + .cpload t9 + .set reorder +/* Save to the stack. Frame size = STACK_SIZE */ + STACK_STORE_FULL() +/* This directive will make sure all subsequent jal restore gp at a known offset */ + .cprestore STACK_OFFSET_GP + + /* Remember the return register */ + sw a3, SHADOWFRAME_RESULT_REGISTER_OFFSET(a2) + + /* Remember the dex instruction pointer */ + sw a1, SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET(a2) + + /* set up "named" registers */ + move rSELF, a0 + lw a0, SHADOWFRAME_NUMBER_OF_VREGS_OFFSET(a2) + addu rFP, a2, SHADOWFRAME_VREGS_OFFSET # point to vregs. + EAS2(rREFS, rFP, a0) # point to reference array in shadow frame + lw a0, SHADOWFRAME_DEX_PC_OFFSET(a2) # Get starting dex_pc + EAS1(rPC, a1, a0) # Create direct pointer to 1st dex opcode + CFI_DEFINE_DEX_PC_WITH_OFFSET(CFI_TMP, CFI_DEX, 0) + + EXPORT_PC() + + /* Starting ibase */ + lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) + + /* Set up for backwards branches & osr profiling */ + lw a0, OFF_FP_METHOD(rFP) + addu a1, rFP, OFF_FP_SHADOWFRAME + move a2, rSELF + JAL(MterpSetUpHotnessCountdown) # (method, shadow_frame, self) + move rPROFILE, v0 # Starting hotness countdown to rPROFILE + + /* start executing the instruction at rPC */ + FETCH_INST() # load rINST from rPC + GET_INST_OPCODE(t0) # extract opcode from rINST + GOTO_OPCODE(t0) # jump to next instruction + /* NOTE: no fallthrough */ + +%def alt_stub(): +/* + * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle + * any interesting requests and then jump to the real instruction + * handler. Note that the call to MterpCheckBefore is done as a tail call. + */ + .extern MterpCheckBefore + la ra, artMterpAsmInstructionStart + (${opnum} * 128) # Addr of primary handler + lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE + move a0, rSELF # arg0 + addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 + move a2, rPC + la t9, MterpCheckBefore + jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) + +%def fallback(): +/* Transfer stub to alternate interpreter */ + b MterpFallback + +%def helpers(): +% op_float_to_long_helper_code() +% op_double_to_long_helper_code() +% op_mul_long_helper_code() +% op_shl_long_helper_code() +% op_shr_long_helper_code() +% op_ushr_long_helper_code() +% op_shl_long_2addr_helper_code() +% op_shr_long_2addr_helper_code() +% op_ushr_long_2addr_helper_code() + +%def footer(): +/* + * =========================================================================== + * Common subroutines and data + * =========================================================================== + */ + + .text + .align 2 + +/* + * We've detected a condition that will result in an exception, but the exception + * has not yet been thrown. Just bail out to the reference interpreter to deal with it. + * TUNING: for consistency, we may want to just go ahead and handle these here. + */ +common_errDivideByZero: + EXPORT_PC() +#if MTERP_LOGGING + move a0, rSELF + addu a1, rFP, OFF_FP_SHADOWFRAME + JAL(MterpLogDivideByZeroException) +#endif + b MterpCommonFallback + +common_errArrayIndex: + EXPORT_PC() +#if MTERP_LOGGING + move a0, rSELF + addu a1, rFP, OFF_FP_SHADOWFRAME + JAL(MterpLogArrayIndexException) +#endif + b MterpCommonFallback + +common_errNegativeArraySize: + EXPORT_PC() +#if MTERP_LOGGING + move a0, rSELF + addu a1, rFP, OFF_FP_SHADOWFRAME + JAL(MterpLogNegativeArraySizeException) +#endif + b MterpCommonFallback + +common_errNoSuchMethod: + EXPORT_PC() +#if MTERP_LOGGING + move a0, rSELF + addu a1, rFP, OFF_FP_SHADOWFRAME + JAL(MterpLogNoSuchMethodException) +#endif + b MterpCommonFallback + +common_errNullObject: + EXPORT_PC() +#if MTERP_LOGGING + move a0, rSELF + addu a1, rFP, OFF_FP_SHADOWFRAME + JAL(MterpLogNullObjectException) +#endif + b MterpCommonFallback + +common_exceptionThrown: + EXPORT_PC() +#if MTERP_LOGGING + move a0, rSELF + addu a1, rFP, OFF_FP_SHADOWFRAME + JAL(MterpLogExceptionThrownException) +#endif + b MterpCommonFallback + +MterpSuspendFallback: + EXPORT_PC() +#if MTERP_LOGGING + move a0, rSELF + addu a1, rFP, OFF_FP_SHADOWFRAME + lw a2, THREAD_FLAGS_OFFSET(rSELF) + JAL(MterpLogSuspendFallback) +#endif + b MterpCommonFallback + +/* + * If we're here, something is out of the ordinary. If there is a pending + * exception, handle it. Otherwise, roll back and retry with the reference + * interpreter. + */ +MterpPossibleException: + lw a0, THREAD_EXCEPTION_OFFSET(rSELF) + beqz a0, MterpFallback # If exception, fall back to reference interpreter. + /* intentional fallthrough - handle pending exception. */ +/* + * On return from a runtime helper routine, we've found a pending exception. + * Can we handle it here - or need to bail out to caller? + * + */ +MterpException: + move a0, rSELF + addu a1, rFP, OFF_FP_SHADOWFRAME + JAL(MterpHandleException) # (self, shadow_frame) + beqz v0, MterpExceptionReturn # no local catch, back to caller. + lw a0, OFF_FP_DEX_INSTRUCTIONS(rFP) + lw a1, OFF_FP_DEX_PC(rFP) + lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) + EAS1(rPC, a0, a1) # generate new dex_pc_ptr + /* Do we need to switch interpreters? */ + JAL(MterpShouldSwitchInterpreters) + bnez v0, MterpFallback + /* resume execution at catch block */ + EXPORT_PC() + FETCH_INST() + GET_INST_OPCODE(t0) + GOTO_OPCODE(t0) + /* NOTE: no fallthrough */ + +/* + * Common handling for branches with support for Jit profiling. + * On entry: + * rINST <= signed offset + * rPROFILE <= signed hotness countdown (expanded to 32 bits) + * + * We have quite a few different cases for branch profiling, OSR detection and + * suspend check support here. + * + * Taken backward branches: + * If profiling active, do hotness countdown and report if we hit zero. + * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. + * Is there a pending suspend request? If so, suspend. + * + * Taken forward branches and not-taken backward branches: + * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. + * + * Our most common case is expected to be a taken backward branch with active jit profiling, + * but no full OSR check and no pending suspend request. + * Next most common case is not-taken branch with no full OSR check. + */ +MterpCommonTakenBranchNoFlags: + bgtz rINST, .L_forward_branch # don't add forward branches to hotness +/* + * We need to subtract 1 from positive values and we should not see 0 here, + * so we may use the result of the comparison with -1. + */ +#if JIT_CHECK_OSR != -1 +# error "JIT_CHECK_OSR must be -1." +#endif + li t0, JIT_CHECK_OSR + beq rPROFILE, t0, .L_osr_check + blt rPROFILE, t0, .L_resume_backward_branch + subu rPROFILE, 1 + beqz rPROFILE, .L_add_batch # counted down to zero - report +.L_resume_backward_branch: + lw ra, THREAD_FLAGS_OFFSET(rSELF) + REFRESH_IBASE() + addu a2, rINST, rINST # a2<- byte offset + FETCH_ADVANCE_INST_RB(a2) # update rPC, load rINST + and ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST + bnez ra, .L_suspend_request_pending + GET_INST_OPCODE(t0) # extract opcode from rINST + GOTO_OPCODE(t0) # jump to next instruction + +.L_suspend_request_pending: + EXPORT_PC() + move a0, rSELF + JAL(MterpSuspendCheck) # (self) + bnez v0, MterpFallback + REFRESH_IBASE() # might have changed during suspend + GET_INST_OPCODE(t0) # extract opcode from rINST + GOTO_OPCODE(t0) # jump to next instruction + +.L_no_count_backwards: + li t0, JIT_CHECK_OSR # check for possible OSR re-entry + bne rPROFILE, t0, .L_resume_backward_branch +.L_osr_check: + move a0, rSELF + addu a1, rFP, OFF_FP_SHADOWFRAME + move a2, rINST + EXPORT_PC() + JAL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) + bnez v0, MterpOnStackReplacement + b .L_resume_backward_branch + +.L_forward_branch: + li t0, JIT_CHECK_OSR # check for possible OSR re-entry + beq rPROFILE, t0, .L_check_osr_forward +.L_resume_forward_branch: + add a2, rINST, rINST # a2<- byte offset + FETCH_ADVANCE_INST_RB(a2) # update rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + GOTO_OPCODE(t0) # jump to next instruction + +.L_check_osr_forward: + move a0, rSELF + addu a1, rFP, OFF_FP_SHADOWFRAME + move a2, rINST + EXPORT_PC() + JAL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) + bnez v0, MterpOnStackReplacement + b .L_resume_forward_branch + +.L_add_batch: + addu a1, rFP, OFF_FP_SHADOWFRAME + sh rPROFILE, SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET(a1) + lw a0, OFF_FP_METHOD(rFP) + move a2, rSELF + JAL(MterpAddHotnessBatch) # (method, shadow_frame, self) + move rPROFILE, v0 # restore new hotness countdown to rPROFILE + b .L_no_count_backwards + +/* + * Entered from the conditional branch handlers when OSR check request active on + * not-taken path. All Dalvik not-taken conditional branch offsets are 2. + */ +.L_check_not_taken_osr: + move a0, rSELF + addu a1, rFP, OFF_FP_SHADOWFRAME + li a2, 2 + EXPORT_PC() + JAL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) + bnez v0, MterpOnStackReplacement + FETCH_ADVANCE_INST(2) + GET_INST_OPCODE(t0) # extract opcode from rINST + GOTO_OPCODE(t0) # jump to next instruction + +/* + * On-stack replacement has happened, and now we've returned from the compiled method. + */ +MterpOnStackReplacement: +#if MTERP_LOGGING + move a0, rSELF + addu a1, rFP, OFF_FP_SHADOWFRAME + move a2, rINST + JAL(MterpLogOSR) +#endif + li v0, 1 # Signal normal return + b MterpDone + +/* + * Bail out to reference interpreter. + */ +MterpFallback: + EXPORT_PC() +#if MTERP_LOGGING + move a0, rSELF + addu a1, rFP, OFF_FP_SHADOWFRAME + JAL(MterpLogFallback) +#endif +MterpCommonFallback: + move v0, zero # signal retry with reference interpreter. + b MterpDone +/* + * We pushed some registers on the stack in ExecuteMterpImpl, then saved + * SP and LR. Here we restore SP, restore the registers, and then restore + * LR to PC. + * + * On entry: + * uint32_t* rFP (should still be live, pointer to base of vregs) + */ +MterpExceptionReturn: + li v0, 1 # signal return to caller. + b MterpDone +MterpReturn: + lw a2, OFF_FP_RESULT_REGISTER(rFP) + sw v0, 0(a2) + sw v1, 4(a2) + li v0, 1 # signal return to caller. +MterpDone: +/* + * At this point, we expect rPROFILE to be non-zero. If negative, hotness is disabled or we're + * checking for OSR. If greater than zero, we might have unreported hotness to register + * (the difference between the ending rPROFILE and the cached hotness counter). rPROFILE + * should only reach zero immediately after a hotness decrement, and is then reset to either + * a negative special state or the new non-zero countdown value. + */ + blez rPROFILE, .L_pop_and_return # if > 0, we may have some counts to report. + +MterpProfileActive: + move rINST, v0 # stash return value + /* Report cached hotness counts */ + lw a0, OFF_FP_METHOD(rFP) + addu a1, rFP, OFF_FP_SHADOWFRAME + move a2, rSELF + sh rPROFILE, SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET(a1) + JAL(MterpAddHotnessBatch) # (method, shadow_frame, self) + move v0, rINST # restore return value + +.L_pop_and_return: +/* Restore from the stack and return. Frame size = STACK_SIZE */ + STACK_LOAD_FULL() + jalr zero, ra + + .cfi_endproc + .end ExecuteMterpImpl + +%def instruction_end(): + + .global artMterpAsmInstructionEnd +artMterpAsmInstructionEnd: + +%def instruction_end_alt(): + + .global artMterpAsmAltInstructionEnd +artMterpAsmAltInstructionEnd: + +%def instruction_start(): + + .global artMterpAsmInstructionStart +artMterpAsmInstructionStart = .L_op_nop + .text + +%def instruction_start_alt(): + + .global artMterpAsmAltInstructionStart +artMterpAsmAltInstructionStart = .L_ALT_op_nop + .text + diff --git a/runtime/interpreter/mterp/mips/object.S b/runtime/interpreter/mterp/mips/object.S new file mode 100644 index 0000000000000000000000000000000000000000..a98778919fb41f7c6f5d459e0dd4329d587afeec --- /dev/null +++ b/runtime/interpreter/mterp/mips/object.S @@ -0,0 +1,257 @@ +%def field(helper=""): +TODO + +%def op_check_cast(): + /* + * Check to see if a cast from one class to another is allowed. + */ + /* check-cast vAA, class@BBBB */ + EXPORT_PC() + FETCH(a0, 1) # a0 <- BBBB + GET_OPA(a1) # a1 <- AA + EAS2(a1, rFP, a1) # a1 <- &object + lw a2, OFF_FP_METHOD(rFP) # a2 <- method + move a3, rSELF # a3 <- self + JAL(MterpCheckCast) # v0 <- CheckCast(index, &obj, method, self) + PREFETCH_INST(2) + bnez v0, MterpPossibleException + ADVANCE(2) + GET_INST_OPCODE(t0) # extract opcode from rINST + GOTO_OPCODE(t0) # jump to next instruction + +%def op_iget(is_object="0", helper="MterpIGetU32"): +% field(helper=helper) + +%def op_iget_boolean(): +% op_iget(helper="MterpIGetU8") + +%def op_iget_boolean_quick(): +% op_iget_quick(load="lbu") + +%def op_iget_byte(): +% op_iget(helper="MterpIGetI8") + +%def op_iget_byte_quick(): +% op_iget_quick(load="lb") + +%def op_iget_char(): +% op_iget(helper="MterpIGetU16") + +%def op_iget_char_quick(): +% op_iget_quick(load="lhu") + +%def op_iget_object(): +% op_iget(is_object="1", helper="MterpIGetObj") + +%def op_iget_object_quick(): + /* For: iget-object-quick */ + /* op vA, vB, offset@CCCC */ + GET_OPB(a2) # a2 <- B + FETCH(a1, 1) # a1 <- field byte offset + EXPORT_PC() + GET_VREG(a0, a2) # a0 <- object we're operating on + JAL(artIGetObjectFromMterp) # v0 <- GetObj(obj, offset) + lw a3, THREAD_EXCEPTION_OFFSET(rSELF) + GET_OPA4(a2) # a2<- A+ + PREFETCH_INST(2) # load rINST + bnez a3, MterpPossibleException # bail out + ADVANCE(2) # advance rPC + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG_OBJECT_GOTO(v0, a2, t0) # fp[A] <- v0 + +%def op_iget_quick(load="lw"): + /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ + /* op vA, vB, offset@CCCC */ + GET_OPB(a2) # a2 <- B + GET_VREG(a3, a2) # a3 <- object we're operating on + FETCH(a1, 1) # a1 <- field byte offset + GET_OPA4(a2) # a2 <- A(+) + # check object for null + beqz a3, common_errNullObject # object was null + addu t0, a3, a1 + $load a0, 0(t0) # a0 <- obj.field (8/16/32 bits) + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG_GOTO(a0, a2, t0) # fp[A] <- a0 + +%def op_iget_short(): +% op_iget(helper="MterpIGetI16") + +%def op_iget_short_quick(): +% op_iget_quick(load="lh") + +%def op_iget_wide(): +% op_iget(helper="MterpIGetU64") + +%def op_iget_wide_quick(): + /* iget-wide-quick vA, vB, offset@CCCC */ + GET_OPB(a2) # a2 <- B + GET_VREG(a3, a2) # a3 <- object we're operating on + FETCH(a1, 1) # a1 <- field byte offset + GET_OPA4(a2) # a2 <- A(+) + # check object for null + beqz a3, common_errNullObject # object was null + addu t0, a3, a1 # t0 <- a3 + a1 + LOAD64(a0, a1, t0) # a0 <- obj.field (64 bits, aligned) + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG64_GOTO(a0, a1, a2, t0) # fp[A] <- a0/a1 + +%def op_instance_of(): + /* + * Check to see if an object reference is an instance of a class. + * + * Most common situation is a non-null object, being compared against + * an already-resolved class. + */ + /* instance-of vA, vB, class@CCCC */ + EXPORT_PC() + FETCH(a0, 1) # a0 <- CCCC + GET_OPB(a1) # a1 <- B + EAS2(a1, rFP, a1) # a1 <- &object + lw a2, OFF_FP_METHOD(rFP) # a2 <- method + move a3, rSELF # a3 <- self + GET_OPA4(rOBJ) # rOBJ <- A+ + JAL(MterpInstanceOf) # v0 <- Mterp(index, &obj, method, self) + lw a1, THREAD_EXCEPTION_OFFSET(rSELF) + PREFETCH_INST(2) # load rINST + bnez a1, MterpException + ADVANCE(2) # advance rPC + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG_GOTO(v0, rOBJ, t0) # vA <- v0 + +%def op_iput(is_object="0", helper="MterpIPutU32"): +% field(helper=helper) + +%def op_iput_boolean(): +% op_iput(helper="MterpIPutU8") + +%def op_iput_boolean_quick(): +% op_iput_quick(store="sb") + +%def op_iput_byte(): +% op_iput(helper="MterpIPutI8") + +%def op_iput_byte_quick(): +% op_iput_quick(store="sb") + +%def op_iput_char(): +% op_iput(helper="MterpIPutU16") + +%def op_iput_char_quick(): +% op_iput_quick(store="sh") + +%def op_iput_object(): +% op_iput(is_object="1", helper="MterpIPutObj") + +%def op_iput_object_quick(): + /* For: iput-object-quick */ + /* op vA, vB, offset@CCCC */ + EXPORT_PC() + addu a0, rFP, OFF_FP_SHADOWFRAME + move a1, rPC + move a2, rINST + JAL(MterpIputObjectQuick) + beqz v0, MterpException + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + GOTO_OPCODE(t0) # jump to next instruction + +%def op_iput_quick(store="sw"): + /* For: iput-quick, iput-object-quick */ + /* op vA, vB, offset@CCCC */ + GET_OPB(a2) # a2 <- B + GET_VREG(a3, a2) # a3 <- fp[B], the object pointer + FETCH(a1, 1) # a1 <- field byte offset + GET_OPA4(a2) # a2 <- A(+) + beqz a3, common_errNullObject # object was null + GET_VREG(a0, a2) # a0 <- fp[A] + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + addu t0, a3, a1 + GET_INST_OPCODE(t1) # extract opcode from rINST + GET_OPCODE_TARGET(t1) + $store a0, 0(t0) # obj.field (8/16/32 bits) <- a0 + JR(t1) # jump to next instruction + +%def op_iput_short(): +% op_iput(helper="MterpIPutI16") + +%def op_iput_short_quick(): +% op_iput_quick(store="sh") + +%def op_iput_wide(): +% op_iput(helper="MterpIPutU64") + +%def op_iput_wide_quick(): + /* iput-wide-quick vA, vB, offset@CCCC */ + GET_OPA4(a0) # a0 <- A(+) + GET_OPB(a1) # a1 <- B + GET_VREG(a2, a1) # a2 <- fp[B], the object pointer + # check object for null + beqz a2, common_errNullObject # object was null + EAS2(a3, rFP, a0) # a3 <- &fp[A] + LOAD64(a0, a1, a3) # a0/a1 <- fp[A] + FETCH(a3, 1) # a3 <- field byte offset + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + addu a2, a2, a3 # obj.field (64 bits, aligned) <- a0/a1 + GET_INST_OPCODE(t0) # extract opcode from rINST + GET_OPCODE_TARGET(t0) + STORE64(a0, a1, a2) # obj.field (64 bits, aligned) <- a0/a1 + JR(t0) # jump to next instruction + +%def op_new_instance(): + /* + * Create a new instance of a class. + */ + /* new-instance vAA, class@BBBB */ + EXPORT_PC() + addu a0, rFP, OFF_FP_SHADOWFRAME + move a1, rSELF + move a2, rINST + JAL(MterpNewInstance) + beqz v0, MterpPossibleException + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + GOTO_OPCODE(t0) # jump to next instruction + +%def op_sget(is_object="0", helper="MterpSGetU32"): +% field(helper=helper) + +%def op_sget_boolean(): +% op_sget(helper="MterpSGetU8") + +%def op_sget_byte(): +% op_sget(helper="MterpSGetI8") + +%def op_sget_char(): +% op_sget(helper="MterpSGetU16") + +%def op_sget_object(): +% op_sget(is_object="1", helper="MterpSGetObj") + +%def op_sget_short(): +% op_sget(helper="MterpSGetI16") + +%def op_sget_wide(): +% op_sget(helper="MterpSGetU64") + +%def op_sput(is_object="0", helper="MterpSPutU32"): +% field(helper=helper) + +%def op_sput_boolean(): +% op_sput(helper="MterpSPutU8") + +%def op_sput_byte(): +% op_sput(helper="MterpSPutI8") + +%def op_sput_char(): +% op_sput(helper="MterpSPutU16") + +%def op_sput_object(): +% op_sput(is_object="1", helper="MterpSPutObj") + +%def op_sput_short(): +% op_sput(helper="MterpSPutI16") + +%def op_sput_wide(): +% op_sput(helper="MterpSPutU64") diff --git a/runtime/interpreter/mterp/mips/op_add_double.S b/runtime/interpreter/mterp/mips/op_add_double.S deleted file mode 100644 index 12ef0cf3cd7f8539b4860d7c6adbd9a5eeddb20d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_add_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/fbinopWide.S" {"instr":"add.d fv0, fa0, fa1"} diff --git a/runtime/interpreter/mterp/mips/op_add_double_2addr.S b/runtime/interpreter/mterp/mips/op_add_double_2addr.S deleted file mode 100644 index c57add572c980efd79a9d48e94edfecd33bc72f9..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_add_double_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/fbinopWide2addr.S" {"instr":"add.d fv0, fa0, fa1"} diff --git a/runtime/interpreter/mterp/mips/op_add_float.S b/runtime/interpreter/mterp/mips/op_add_float.S deleted file mode 100644 index 6a46cf0ab9b4d03bfe2508bc5cf5ce364a65fb3e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_add_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/fbinop.S" {"instr":"add.s fv0, fa0, fa1"} diff --git a/runtime/interpreter/mterp/mips/op_add_float_2addr.S b/runtime/interpreter/mterp/mips/op_add_float_2addr.S deleted file mode 100644 index 6ab5cc17309f867594133fbcd7ea5c398b29f0ea..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_add_float_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/fbinop2addr.S" {"instr":"add.s fv0, fa0, fa1"} diff --git a/runtime/interpreter/mterp/mips/op_add_int.S b/runtime/interpreter/mterp/mips/op_add_int.S deleted file mode 100644 index 53a0cb128fd1dfd880580c0a6a86524b75224939..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_add_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/binop.S" {"instr":"addu a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips/op_add_int_2addr.S b/runtime/interpreter/mterp/mips/op_add_int_2addr.S deleted file mode 100644 index ddd92145c343513f7e5e04b9e2d43fe4bf9f422e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_add_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/binop2addr.S" {"instr":"addu a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips/op_add_int_lit16.S b/runtime/interpreter/mterp/mips/op_add_int_lit16.S deleted file mode 100644 index 05535c15dc451e058a9934100a781ac59f0f61fc..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_add_int_lit16.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/binopLit16.S" {"instr":"addu a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips/op_add_int_lit8.S b/runtime/interpreter/mterp/mips/op_add_int_lit8.S deleted file mode 100644 index fd021b31a964d15a5dfa21e417bf1b9112c40df9..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_add_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/binopLit8.S" {"instr":"addu a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips/op_add_long.S b/runtime/interpreter/mterp/mips/op_add_long.S deleted file mode 100644 index faacc6a3cc7ce3f4c5abb76e1918f6da6d74a03f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_add_long.S +++ /dev/null @@ -1,9 +0,0 @@ -/* - * The compiler generates the following sequence for - * [v1 v0] = [a1 a0] + [a3 a2]; - * addu v0,a2,a0 - * addu a1,a3,a1 - * sltu v1,v0,a2 - * addu v1,v1,a1 - */ -%include "mips/binopWide.S" { "result0":"v0", "result1":"v1", "preinstr":"addu v0, a2, a0", "instr":"addu a1, a3, a1; sltu v1, v0, a2; addu v1, v1, a1" } diff --git a/runtime/interpreter/mterp/mips/op_add_long_2addr.S b/runtime/interpreter/mterp/mips/op_add_long_2addr.S deleted file mode 100644 index bf827c10d4e3202d59f7fcf1f8a28079e5d3cd8a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_add_long_2addr.S +++ /dev/null @@ -1,4 +0,0 @@ -/* - * See op_add_long.S for details - */ -%include "mips/binopWide2addr.S" { "result0":"v0", "result1":"v1", "preinstr":"addu v0, a2, a0", "instr":"addu a1, a3, a1; sltu v1, v0, a2; addu v1, v1, a1" } diff --git a/runtime/interpreter/mterp/mips/op_aget.S b/runtime/interpreter/mterp/mips/op_aget.S deleted file mode 100644 index e88402c710253e5b072d306de8c2c12695f55cc9..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_aget.S +++ /dev/null @@ -1,28 +0,0 @@ -%default { "load":"lw", "shift":"2", "data_offset":"MIRROR_INT_ARRAY_DATA_OFFSET" } - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B(a2, 1, 0) # a2 <- BB - GET_OPA(rOBJ) # rOBJ <- AA - FETCH_B(a3, 1, 1) # a3 <- CC - GET_VREG(a0, a2) # a0 <- vBB (array object) - GET_VREG(a1, a3) # a1 <- vCC (requested index) - # null array object? - beqz a0, common_errNullObject # yes, bail - LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length - EASN(a0, a0, a1, $shift) # a0 <- arrayObj + index*width - # a1 >= a3; compare unsigned index - bgeu a1, a3, common_errArrayIndex # index >= length, bail - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - $load a2, $data_offset(a0) # a2 <- vBB[vCC] - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a2, rOBJ, t0) # vAA <- a2 diff --git a/runtime/interpreter/mterp/mips/op_aget_boolean.S b/runtime/interpreter/mterp/mips/op_aget_boolean.S deleted file mode 100644 index 59f7f82a84e5490a51b555a6110981f0c0fabcfd..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_aget_boolean.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_aget.S" { "load":"lbu", "shift":"0", "data_offset":"MIRROR_BOOLEAN_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/mips/op_aget_byte.S b/runtime/interpreter/mterp/mips/op_aget_byte.S deleted file mode 100644 index 11038fa7e10296c54347f87288a3469a0705fb35..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_aget_byte.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_aget.S" { "load":"lb", "shift":"0", "data_offset":"MIRROR_BYTE_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/mips/op_aget_char.S b/runtime/interpreter/mterp/mips/op_aget_char.S deleted file mode 100644 index 96f2ab65dc533867267f68db1c739074dcdb9fef..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_aget_char.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_aget.S" { "load":"lhu", "shift":"1", "data_offset":"MIRROR_CHAR_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/mips/op_aget_object.S b/runtime/interpreter/mterp/mips/op_aget_object.S deleted file mode 100644 index 9c49dfeed710833adebc588baf7be73e5bc18a35..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_aget_object.S +++ /dev/null @@ -1,19 +0,0 @@ - /* - * Array object get. vAA <- vBB[vCC]. - * - * for: aget-object - */ - /* op vAA, vBB, vCC */ - FETCH_B(a2, 1, 0) # a2 <- BB - GET_OPA(rOBJ) # rOBJ <- AA - FETCH_B(a3, 1, 1) # a3 <- CC - EXPORT_PC() - GET_VREG(a0, a2) # a0 <- vBB (array object) - GET_VREG(a1, a3) # a1 <- vCC (requested index) - JAL(artAGetObjectFromMterp) # v0 <- GetObj(array, index) - lw a1, THREAD_EXCEPTION_OFFSET(rSELF) - PREFETCH_INST(2) # load rINST - bnez a1, MterpException - ADVANCE(2) # advance rPC - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_OBJECT_GOTO(v0, rOBJ, t0) # vAA <- v0 diff --git a/runtime/interpreter/mterp/mips/op_aget_short.S b/runtime/interpreter/mterp/mips/op_aget_short.S deleted file mode 100644 index cd7f7bf62f968b8c202042660bbb629de270ff9f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_aget_short.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_aget.S" { "load":"lh", "shift":"1", "data_offset":"MIRROR_SHORT_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/mips/op_aget_wide.S b/runtime/interpreter/mterp/mips/op_aget_wide.S deleted file mode 100644 index 08822f56c32a141e6fd348a6fef1e67838873a96..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_aget_wide.S +++ /dev/null @@ -1,22 +0,0 @@ - /* - * Array get, 64 bits. vAA <- vBB[vCC]. - * - * Arrays of long/double are 64-bit aligned. - */ - /* aget-wide vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 # a3 <- CC - GET_VREG(a0, a2) # a0 <- vBB (array object) - GET_VREG(a1, a3) # a1 <- vCC (requested index) - # null array object? - beqz a0, common_errNullObject # yes, bail - LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length - EAS3(a0, a0, a1) # a0 <- arrayObj + index*width - bgeu a1, a3, common_errArrayIndex # index >= length, bail - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - LOAD64_off(a2, a3, a0, MIRROR_WIDE_ARRAY_DATA_OFFSET) - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(a2, a3, rOBJ, t0) # vAA/vAA+1 <- a2/a3 diff --git a/runtime/interpreter/mterp/mips/op_and_int.S b/runtime/interpreter/mterp/mips/op_and_int.S deleted file mode 100644 index 98fe4af7d22032dfc858d3f6a1e112656edf6dfc..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_and_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/binop.S" {"instr":"and a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips/op_and_int_2addr.S b/runtime/interpreter/mterp/mips/op_and_int_2addr.S deleted file mode 100644 index 7f90ed45350b0905b4d4f33edd87d73fb87b1fb2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_and_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/binop2addr.S" {"instr":"and a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips/op_and_int_lit16.S b/runtime/interpreter/mterp/mips/op_and_int_lit16.S deleted file mode 100644 index e46f23ba2e487f4f8e61e28f4eea807e70e8e342..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_and_int_lit16.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/binopLit16.S" {"instr":"and a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips/op_and_int_lit8.S b/runtime/interpreter/mterp/mips/op_and_int_lit8.S deleted file mode 100644 index 3332883dc229507d59f1460c600e2885bb92c636..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_and_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/binopLit8.S" {"instr":"and a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips/op_and_long.S b/runtime/interpreter/mterp/mips/op_and_long.S deleted file mode 100644 index a98a6dfbd8f8d76772300397961783dff895c2b1..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_and_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/binopWide.S" {"preinstr":"and a0, a0, a2", "instr":"and a1, a1, a3"} diff --git a/runtime/interpreter/mterp/mips/op_and_long_2addr.S b/runtime/interpreter/mterp/mips/op_and_long_2addr.S deleted file mode 100644 index 350c044f986c13fa3011e78cae57d7a5c9ec032e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_and_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/binopWide2addr.S" {"preinstr":"and a0, a0, a2", "instr":"and a1, a1, a3"} diff --git a/runtime/interpreter/mterp/mips/op_aput.S b/runtime/interpreter/mterp/mips/op_aput.S deleted file mode 100644 index 46dcaee3a917200e5b7825eb030478be1a22c1a2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_aput.S +++ /dev/null @@ -1,27 +0,0 @@ -%default { "store":"sw", "shift":"2", "data_offset":"MIRROR_INT_ARRAY_DATA_OFFSET" } - - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B(a2, 1, 0) # a2 <- BB - GET_OPA(rOBJ) # rOBJ <- AA - FETCH_B(a3, 1, 1) # a3 <- CC - GET_VREG(a0, a2) # a0 <- vBB (array object) - GET_VREG(a1, a3) # a1 <- vCC (requested index) - # null array object? - beqz a0, common_errNullObject # yes, bail - LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length - EASN(a0, a0, a1, $shift) # a0 <- arrayObj + index*width - bgeu a1, a3, common_errArrayIndex # index >= length, bail - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_VREG(a2, rOBJ) # a2 <- vAA - GET_INST_OPCODE(t0) # extract opcode from rINST - GET_OPCODE_TARGET(t0) - $store a2, $data_offset(a0) # vBB[vCC] <- a2 - JR(t0) # jump to next instruction diff --git a/runtime/interpreter/mterp/mips/op_aput_boolean.S b/runtime/interpreter/mterp/mips/op_aput_boolean.S deleted file mode 100644 index 9cae5efbaf4f0bc0b3fcd79352b3437edeebba48..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_aput_boolean.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_aput.S" { "store":"sb", "shift":"0", "data_offset":"MIRROR_BOOLEAN_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/mips/op_aput_byte.S b/runtime/interpreter/mterp/mips/op_aput_byte.S deleted file mode 100644 index 3bbd12cec110f9346205256b2d40e2d1f7caf166..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_aput_byte.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_aput.S" { "store":"sb", "shift":"0", "data_offset":"MIRROR_BYTE_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/mips/op_aput_char.S b/runtime/interpreter/mterp/mips/op_aput_char.S deleted file mode 100644 index ae697173d79aaab670a315437c59bef3f8c8a10b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_aput_char.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_aput.S" { "store":"sh", "shift":"1", "data_offset":"MIRROR_CHAR_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/mips/op_aput_object.S b/runtime/interpreter/mterp/mips/op_aput_object.S deleted file mode 100644 index 55b13b1449ae7b5ae4b64fc488d56f5d4a9def7d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_aput_object.S +++ /dev/null @@ -1,14 +0,0 @@ - /* - * Store an object into an array. vBB[vCC] <- vAA. - * - */ - /* op vAA, vBB, vCC */ - EXPORT_PC() - addu a0, rFP, OFF_FP_SHADOWFRAME - move a1, rPC - move a2, rINST - JAL(MterpAputObject) - beqz v0, MterpPossibleException - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction diff --git a/runtime/interpreter/mterp/mips/op_aput_short.S b/runtime/interpreter/mterp/mips/op_aput_short.S deleted file mode 100644 index 9586259a240aa68d263d8464594e97acbeaeea18..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_aput_short.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_aput.S" { "store":"sh", "shift":"1", "data_offset":"MIRROR_SHORT_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/mips/op_aput_wide.S b/runtime/interpreter/mterp/mips/op_aput_wide.S deleted file mode 100644 index c3cff56aaab3b505406d31971ec51b0ed265538a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_aput_wide.S +++ /dev/null @@ -1,24 +0,0 @@ - /* - * Array put, 64 bits. vBB[vCC] <- vAA. - */ - /* aput-wide vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(t0) # t0 <- AA - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 # a3 <- CC - GET_VREG(a0, a2) # a0 <- vBB (array object) - GET_VREG(a1, a3) # a1 <- vCC (requested index) - # null array object? - beqz a0, common_errNullObject # yes, bail - LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length - EAS3(a0, a0, a1) # a0 <- arrayObj + index*width - EAS2(rOBJ, rFP, t0) # rOBJ <- &fp[AA] - # compare unsigned index, length - bgeu a1, a3, common_errArrayIndex # index >= length, bail - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - LOAD64(a2, a3, rOBJ) # a2/a3 <- vAA/vAA+1 - GET_INST_OPCODE(t0) # extract opcode from rINST - GET_OPCODE_TARGET(t0) - STORE64_off(a2, a3, a0, MIRROR_WIDE_ARRAY_DATA_OFFSET) # a2/a3 <- vBB[vCC] - JR(t0) # jump to next instruction diff --git a/runtime/interpreter/mterp/mips/op_array_length.S b/runtime/interpreter/mterp/mips/op_array_length.S deleted file mode 100644 index ae2fe68322298c1f560927801178377042b0cd29..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_array_length.S +++ /dev/null @@ -1,13 +0,0 @@ - /* - * Return the length of an array. - */ - /* array-length vA, vB */ - GET_OPB(a1) # a1 <- B - GET_OPA4(a2) # a2 <- A+ - GET_VREG(a0, a1) # a0 <- vB (object ref) - # is object null? - beqz a0, common_errNullObject # yup, fail - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - LOAD_base_offMirrorArray_length(a3, a0) # a3 <- array length - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a3, a2, t0) # vA <- length diff --git a/runtime/interpreter/mterp/mips/op_check_cast.S b/runtime/interpreter/mterp/mips/op_check_cast.S deleted file mode 100644 index 3875ce6fc7c8a4ea6ed12567618587725d3d11f4..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_check_cast.S +++ /dev/null @@ -1,16 +0,0 @@ - /* - * Check to see if a cast from one class to another is allowed. - */ - /* check-cast vAA, class@BBBB */ - EXPORT_PC() - FETCH(a0, 1) # a0 <- BBBB - GET_OPA(a1) # a1 <- AA - EAS2(a1, rFP, a1) # a1 <- &object - lw a2, OFF_FP_METHOD(rFP) # a2 <- method - move a3, rSELF # a3 <- self - JAL(MterpCheckCast) # v0 <- CheckCast(index, &obj, method, self) - PREFETCH_INST(2) - bnez v0, MterpPossibleException - ADVANCE(2) - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction diff --git a/runtime/interpreter/mterp/mips/op_cmp_long.S b/runtime/interpreter/mterp/mips/op_cmp_long.S deleted file mode 100644 index 44806c3d067006ae82682f759be45f0ecfdede61..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_cmp_long.S +++ /dev/null @@ -1,34 +0,0 @@ - /* - * Compare two 64-bit values - * x = y return 0 - * x < y return -1 - * x > y return 1 - * - * I think I can improve on the ARM code by the following observation - * slt t0, x.hi, y.hi; # (x.hi < y.hi) ? 1:0 - * sgt t1, x.hi, y.hi; # (y.hi > x.hi) ? 1:0 - * subu v0, t0, t1 # v0= -1:1:0 for [ < > = ] - */ - /* cmp-long vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 # a3 <- CC - EAS2(a2, rFP, a2) # a2 <- &fp[BB] - EAS2(a3, rFP, a3) # a3 <- &fp[CC] - LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 - LOAD64(a2, a3, a3) # a2/a3 <- vCC/vCC+1 - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - slt t0, a1, a3 # compare hi - sgt t1, a1, a3 - subu v0, t1, t0 # v0 <- (-1, 1, 0) - bnez v0, .L${opcode}_finish - # at this point x.hi==y.hi - sltu t0, a0, a2 # compare lo - sgtu t1, a0, a2 - subu v0, t1, t0 # v0 <- (-1, 1, 0) for [< > =] - -.L${opcode}_finish: - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(v0, rOBJ, t0) # vAA <- v0 diff --git a/runtime/interpreter/mterp/mips/op_cmpg_double.S b/runtime/interpreter/mterp/mips/op_cmpg_double.S deleted file mode 100644 index b2e753219c5263c2c186f1c94a7f8fb0047afd9e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_cmpg_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_cmpl_double.S" { "gt_bias":"1" } diff --git a/runtime/interpreter/mterp/mips/op_cmpg_float.S b/runtime/interpreter/mterp/mips/op_cmpg_float.S deleted file mode 100644 index 76550b56b057d8714091665824e0668a313b8c57..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_cmpg_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_cmpl_float.S" { "gt_bias":"1" } diff --git a/runtime/interpreter/mterp/mips/op_cmpl_double.S b/runtime/interpreter/mterp/mips/op_cmpl_double.S deleted file mode 100644 index 369e5b30fd6b4fcc10115d8eebd3e441112a7f8d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_cmpl_double.S +++ /dev/null @@ -1,52 +0,0 @@ -%default { "gt_bias":"0" } - /* - * Compare two floating-point values. Puts 0(==), 1(>), or -1(<) - * into the destination register based on the comparison results. - * - * For: cmpl-double, cmpg-double - */ - /* op vAA, vBB, vCC */ - - FETCH(a0, 1) # a0 <- CCBB - and rOBJ, a0, 255 # rOBJ <- BB - srl t0, a0, 8 # t0 <- CC - EAS2(rOBJ, rFP, rOBJ) # rOBJ <- &fp[BB] - EAS2(t0, rFP, t0) # t0 <- &fp[CC] - LOAD64_F(ft0, ft0f, rOBJ) - LOAD64_F(ft1, ft1f, t0) -#ifdef MIPS32REVGE6 - cmp.eq.d ft2, ft0, ft1 - li rTEMP, 0 - bc1nez ft2, 1f # done if vBB == vCC (ordered) - .if $gt_bias - cmp.lt.d ft2, ft0, ft1 - li rTEMP, -1 - bc1nez ft2, 1f # done if vBB < vCC (ordered) - li rTEMP, 1 # vBB > vCC or unordered - .else - cmp.lt.d ft2, ft1, ft0 - li rTEMP, 1 - bc1nez ft2, 1f # done if vBB > vCC (ordered) - li rTEMP, -1 # vBB < vCC or unordered - .endif -#else - c.eq.d fcc0, ft0, ft1 - li rTEMP, 0 - bc1t fcc0, 1f # done if vBB == vCC (ordered) - .if $gt_bias - c.olt.d fcc0, ft0, ft1 - li rTEMP, -1 - bc1t fcc0, 1f # done if vBB < vCC (ordered) - li rTEMP, 1 # vBB > vCC or unordered - .else - c.olt.d fcc0, ft1, ft0 - li rTEMP, 1 - bc1t fcc0, 1f # done if vBB > vCC (ordered) - li rTEMP, -1 # vBB < vCC or unordered - .endif -#endif -1: - GET_OPA(rOBJ) - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(rTEMP, rOBJ, t0) # vAA <- rTEMP diff --git a/runtime/interpreter/mterp/mips/op_cmpl_float.S b/runtime/interpreter/mterp/mips/op_cmpl_float.S deleted file mode 100644 index 1dd55067e985b44c70976efe7611441983c61bfd..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_cmpl_float.S +++ /dev/null @@ -1,50 +0,0 @@ -%default { "gt_bias":"0" } - /* - * Compare two floating-point values. Puts 0(==), 1(>), or -1(<) - * into the destination register based on the comparison results. - * - * for: cmpl-float, cmpg-float - */ - /* op vAA, vBB, vCC */ - - FETCH(a0, 1) # a0 <- CCBB - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 - GET_VREG_F(ft0, a2) - GET_VREG_F(ft1, a3) -#ifdef MIPS32REVGE6 - cmp.eq.s ft2, ft0, ft1 - li rTEMP, 0 - bc1nez ft2, 1f # done if vBB == vCC (ordered) - .if $gt_bias - cmp.lt.s ft2, ft0, ft1 - li rTEMP, -1 - bc1nez ft2, 1f # done if vBB < vCC (ordered) - li rTEMP, 1 # vBB > vCC or unordered - .else - cmp.lt.s ft2, ft1, ft0 - li rTEMP, 1 - bc1nez ft2, 1f # done if vBB > vCC (ordered) - li rTEMP, -1 # vBB < vCC or unordered - .endif -#else - c.eq.s fcc0, ft0, ft1 - li rTEMP, 0 - bc1t fcc0, 1f # done if vBB == vCC (ordered) - .if $gt_bias - c.olt.s fcc0, ft0, ft1 - li rTEMP, -1 - bc1t fcc0, 1f # done if vBB < vCC (ordered) - li rTEMP, 1 # vBB > vCC or unordered - .else - c.olt.s fcc0, ft1, ft0 - li rTEMP, 1 - bc1t fcc0, 1f # done if vBB > vCC (ordered) - li rTEMP, -1 # vBB < vCC or unordered - .endif -#endif -1: - GET_OPA(rOBJ) - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(rTEMP, rOBJ, t0) # vAA <- rTEMP diff --git a/runtime/interpreter/mterp/mips/op_const.S b/runtime/interpreter/mterp/mips/op_const.S deleted file mode 100644 index bd9f873fb501dc734398555044fc18d028befc44..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_const.S +++ /dev/null @@ -1,8 +0,0 @@ - /* const vAA, +BBBBbbbb */ - GET_OPA(a3) # a3 <- AA - FETCH(a0, 1) # a0 <- bbbb (low) - FETCH(a1, 2) # a1 <- BBBB (high) - FETCH_ADVANCE_INST(3) # advance rPC, load rINST - INSERT_HIGH_HALF(a0, a1) # a0 <- BBBBbbbb - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, a3, t0) # vAA <- a0 diff --git a/runtime/interpreter/mterp/mips/op_const_16.S b/runtime/interpreter/mterp/mips/op_const_16.S deleted file mode 100644 index 2ffb30f6f11ace01b77d35daae99b04178d8e757..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_const_16.S +++ /dev/null @@ -1,6 +0,0 @@ - /* const/16 vAA, +BBBB */ - FETCH_S(a0, 1) # a0 <- ssssBBBB (sign-extended) - GET_OPA(a3) # a3 <- AA - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, a3, t0) # vAA <- a0 diff --git a/runtime/interpreter/mterp/mips/op_const_4.S b/runtime/interpreter/mterp/mips/op_const_4.S deleted file mode 100644 index 6866c784170177ec45b95739a580f01a3653fc89..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_const_4.S +++ /dev/null @@ -1,8 +0,0 @@ - /* const/4 vA, +B */ - sll a1, rINST, 16 # a1 <- Bxxx0000 - GET_OPA(a0) # a0 <- A+ - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - sra a1, a1, 28 # a1 <- sssssssB (sign-extended) - and a0, a0, 15 - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a1, a0, t0) # fp[A] <- a1 diff --git a/runtime/interpreter/mterp/mips/op_const_class.S b/runtime/interpreter/mterp/mips/op_const_class.S deleted file mode 100644 index 5b3c96819a331471f232a3dba8d9423ec75c7e93..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_const_class.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/const.S" { "helper":"MterpConstClass" } diff --git a/runtime/interpreter/mterp/mips/op_const_high16.S b/runtime/interpreter/mterp/mips/op_const_high16.S deleted file mode 100644 index 51624022603e42932af07abe8182e8a25d90d0e6..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_const_high16.S +++ /dev/null @@ -1,7 +0,0 @@ - /* const/high16 vAA, +BBBB0000 */ - FETCH(a0, 1) # a0 <- 0000BBBB (zero-extended) - GET_OPA(a3) # a3 <- AA - sll a0, a0, 16 # a0 <- BBBB0000 - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, a3, t0) # vAA <- a0 diff --git a/runtime/interpreter/mterp/mips/op_const_method_handle.S b/runtime/interpreter/mterp/mips/op_const_method_handle.S deleted file mode 100644 index 4011e435c4839acf758e19ff415e593bdd12849f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_const_method_handle.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/const.S" { "helper":"MterpConstMethodHandle" } diff --git a/runtime/interpreter/mterp/mips/op_const_method_type.S b/runtime/interpreter/mterp/mips/op_const_method_type.S deleted file mode 100644 index 18a5e0f68804c91c1ca06da3328bcb8028f2afb0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_const_method_type.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/const.S" { "helper":"MterpConstMethodType" } diff --git a/runtime/interpreter/mterp/mips/op_const_string.S b/runtime/interpreter/mterp/mips/op_const_string.S deleted file mode 100644 index 0bab6b40687b41d9a685169ec5039ec6f17b847a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_const_string.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/const.S" { "helper":"MterpConstString" } diff --git a/runtime/interpreter/mterp/mips/op_const_string_jumbo.S b/runtime/interpreter/mterp/mips/op_const_string_jumbo.S deleted file mode 100644 index 54cec977d3fcfaadffd140e282a74ed951022ae0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_const_string_jumbo.S +++ /dev/null @@ -1,14 +0,0 @@ - /* const/string vAA, string@BBBBBBBB */ - EXPORT_PC() - FETCH(a0, 1) # a0 <- bbbb (low) - FETCH(a2, 2) # a2 <- BBBB (high) - GET_OPA(a1) # a1 <- AA - INSERT_HIGH_HALF(a0, a2) # a0 <- BBBBbbbb - addu a2, rFP, OFF_FP_SHADOWFRAME # a2 <- shadow frame - move a3, rSELF - JAL(MterpConstString) # v0 <- Mterp(index, tgt_reg, shadow_frame, self) - PREFETCH_INST(3) # load rINST - bnez v0, MterpPossibleException - ADVANCE(3) # advance rPC - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction diff --git a/runtime/interpreter/mterp/mips/op_const_wide.S b/runtime/interpreter/mterp/mips/op_const_wide.S deleted file mode 100644 index f8911e3a68465f07e7b85246101321aa680a28a0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_const_wide.S +++ /dev/null @@ -1,11 +0,0 @@ - /* const-wide vAA, +HHHHhhhhBBBBbbbb */ - FETCH(a0, 1) # a0 <- bbbb (low) - FETCH(a1, 2) # a1 <- BBBB (low middle) - FETCH(a2, 3) # a2 <- hhhh (high middle) - INSERT_HIGH_HALF(a0, a1) # a0 <- BBBBbbbb (low word) - FETCH(a3, 4) # a3 <- HHHH (high) - GET_OPA(t1) # t1 <- AA - INSERT_HIGH_HALF(a2, a3) # a2 <- HHHHhhhh (high word) - FETCH_ADVANCE_INST(5) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(a0, a2, t1, t0) # vAA/vAA+1 <- a0/a2 diff --git a/runtime/interpreter/mterp/mips/op_const_wide_16.S b/runtime/interpreter/mterp/mips/op_const_wide_16.S deleted file mode 100644 index 2ca5ab927f924c8050ad30a4487c7b5b7a18edb2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_const_wide_16.S +++ /dev/null @@ -1,7 +0,0 @@ - /* const-wide/16 vAA, +BBBB */ - FETCH_S(a0, 1) # a0 <- ssssBBBB (sign-extended) - GET_OPA(a3) # a3 <- AA - sra a1, a0, 31 # a1 <- ssssssss - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(a0, a1, a3, t0) # vAA/vAA+1 <- a0/a1 diff --git a/runtime/interpreter/mterp/mips/op_const_wide_32.S b/runtime/interpreter/mterp/mips/op_const_wide_32.S deleted file mode 100644 index bf802ca17062bd55aae414586df5d872d39a1eb2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_const_wide_32.S +++ /dev/null @@ -1,9 +0,0 @@ - /* const-wide/32 vAA, +BBBBbbbb */ - FETCH(a0, 1) # a0 <- 0000bbbb (low) - GET_OPA(a3) # a3 <- AA - FETCH_S(a2, 2) # a2 <- ssssBBBB (high) - FETCH_ADVANCE_INST(3) # advance rPC, load rINST - INSERT_HIGH_HALF(a0, a2) # a0 <- BBBBbbbb - sra a1, a0, 31 # a1 <- ssssssss - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(a0, a1, a3, t0) # vAA/vAA+1 <- a0/a1 diff --git a/runtime/interpreter/mterp/mips/op_const_wide_high16.S b/runtime/interpreter/mterp/mips/op_const_wide_high16.S deleted file mode 100644 index 04b90fa152544b7dec80e16432da6b8e2b98563e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_const_wide_high16.S +++ /dev/null @@ -1,8 +0,0 @@ - /* const-wide/high16 vAA, +BBBB000000000000 */ - FETCH(a1, 1) # a1 <- 0000BBBB (zero-extended) - GET_OPA(a3) # a3 <- AA - li a0, 0 # a0 <- 00000000 - sll a1, 16 # a1 <- BBBB0000 - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(a0, a1, a3, t0) # vAA/vAA+1 <- a0/a1 diff --git a/runtime/interpreter/mterp/mips/op_div_double.S b/runtime/interpreter/mterp/mips/op_div_double.S deleted file mode 100644 index 84e4c4e3174774b3caa4a5dcee50abf55efe65c3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_div_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/fbinopWide.S" {"instr":"div.d fv0, fa0, fa1"} diff --git a/runtime/interpreter/mterp/mips/op_div_double_2addr.S b/runtime/interpreter/mterp/mips/op_div_double_2addr.S deleted file mode 100644 index 65b92e37db357125247e7252c07ce6c92421db37..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_div_double_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/fbinopWide2addr.S" {"instr":"div.d fv0, fa0, fa1"} diff --git a/runtime/interpreter/mterp/mips/op_div_float.S b/runtime/interpreter/mterp/mips/op_div_float.S deleted file mode 100644 index 44b8d47e0b951ce9b7c4fb9cc4067f967d4e9835..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_div_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/fbinop.S" {"instr":"div.s fv0, fa0, fa1"} diff --git a/runtime/interpreter/mterp/mips/op_div_float_2addr.S b/runtime/interpreter/mterp/mips/op_div_float_2addr.S deleted file mode 100644 index e5fff92c8c5006478954aebc20dca9e2e2c6d1e0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_div_float_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/fbinop2addr.S" {"instr":"div.s fv0, fa0, fa1"} diff --git a/runtime/interpreter/mterp/mips/op_div_int.S b/runtime/interpreter/mterp/mips/op_div_int.S deleted file mode 100644 index 5d28c84d6b09b6c5be52d8707e2139e7c4908515..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_div_int.S +++ /dev/null @@ -1,5 +0,0 @@ -#ifdef MIPS32REVGE6 -%include "mips/binop.S" {"instr":"div a0, a0, a1", "chkzero":"1"} -#else -%include "mips/binop.S" {"preinstr":"div zero, a0, a1", "instr":"mflo a0", "chkzero":"1"} -#endif diff --git a/runtime/interpreter/mterp/mips/op_div_int_2addr.S b/runtime/interpreter/mterp/mips/op_div_int_2addr.S deleted file mode 100644 index 6c079e04c4f9576a8cf2a04a53c24ca39f163ee3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_div_int_2addr.S +++ /dev/null @@ -1,5 +0,0 @@ -#ifdef MIPS32REVGE6 -%include "mips/binop2addr.S" {"instr":"div a0, a0, a1", "chkzero":"1"} -#else -%include "mips/binop2addr.S" {"preinstr":"div zero, a0, a1", "instr":"mflo a0", "chkzero":"1"} -#endif diff --git a/runtime/interpreter/mterp/mips/op_div_int_lit16.S b/runtime/interpreter/mterp/mips/op_div_int_lit16.S deleted file mode 100644 index ee7452ce1a910f138744c8374f3d78786e79ffdf..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_div_int_lit16.S +++ /dev/null @@ -1,5 +0,0 @@ -#ifdef MIPS32REVGE6 -%include "mips/binopLit16.S" {"instr":"div a0, a0, a1", "chkzero":"1"} -#else -%include "mips/binopLit16.S" {"preinstr":"div zero, a0, a1", "instr":"mflo a0", "chkzero":"1"} -#endif diff --git a/runtime/interpreter/mterp/mips/op_div_int_lit8.S b/runtime/interpreter/mterp/mips/op_div_int_lit8.S deleted file mode 100644 index d2964b8065e07ef3f4b2b3ffaab6f9eb9caedad6..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_div_int_lit8.S +++ /dev/null @@ -1,5 +0,0 @@ -#ifdef MIPS32REVGE6 -%include "mips/binopLit8.S" {"instr":"div a0, a0, a1", "chkzero":"1"} -#else -%include "mips/binopLit8.S" {"preinstr":"div zero, a0, a1", "instr":"mflo a0", "chkzero":"1"} -#endif diff --git a/runtime/interpreter/mterp/mips/op_div_long.S b/runtime/interpreter/mterp/mips/op_div_long.S deleted file mode 100644 index 2097866886cfa51aeb90b40516de94097b2ce2fb..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_div_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/binopWide.S" {"result0":"v0", "result1":"v1", "instr":"JAL(__divdi3)", "chkzero":"1"} diff --git a/runtime/interpreter/mterp/mips/op_div_long_2addr.S b/runtime/interpreter/mterp/mips/op_div_long_2addr.S deleted file mode 100644 index c27930514233808c2069587f8ea7ccb067ce017b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_div_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/binopWide2addr.S" {"result0":"v0", "result1":"v1", "instr":"JAL(__divdi3)", "chkzero":"1"} diff --git a/runtime/interpreter/mterp/mips/op_double_to_float.S b/runtime/interpreter/mterp/mips/op_double_to_float.S deleted file mode 100644 index 1d32c2e1e4b84c556f2cdaae433dc4a30a245d9b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_double_to_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/unopNarrower.S" {"instr":"cvt.s.d fv0, fa0"} diff --git a/runtime/interpreter/mterp/mips/op_double_to_int.S b/runtime/interpreter/mterp/mips/op_double_to_int.S deleted file mode 100644 index 6d7c6cae61f1caefa11c3c96ec9e1d3317cf121f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_double_to_int.S +++ /dev/null @@ -1,31 +0,0 @@ - /* - * double-to-int - * - * We have to clip values to int min/max per the specification. The - * expected common case is a "reasonable" value that converts directly - * to modest integer. The EABI convert function isn't doing this for us - * for pre-R6. - */ - /* unop vA, vB */ - GET_OPB(a3) # a3 <- B - GET_OPA4(rOBJ) # rOBJ <- A+ - EAS2(a3, rFP, a3) # a3 <- &fp[B] - LOAD64_F(fa0, fa0f, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST -#ifndef MIPS32REVGE6 - li t0, INT_MIN_AS_DOUBLE_HIGH - mtc1 zero, fa1 - MOVE_TO_FPU_HIGH(t0, fa1, fa1f) - c.ole.d fcc0, fa1, fa0 -#endif - GET_INST_OPCODE(t1) # extract opcode from rINST -#ifndef MIPS32REVGE6 - bc1t fcc0, 1f # if INT_MIN <= vB, proceed to truncation - c.eq.d fcc0, fa0, fa0 - mtc1 zero, fa0 - MOVE_TO_FPU_HIGH(zero, fa0, fa0f) - movt.d fa0, fa1, fcc0 # fa0 = ordered(vB) ? INT_MIN_AS_DOUBLE : 0 -1: -#endif - trunc.w.d fa0, fa0 - SET_VREG_F_GOTO(fa0, rOBJ, t1) # vA <- result diff --git a/runtime/interpreter/mterp/mips/op_double_to_long.S b/runtime/interpreter/mterp/mips/op_double_to_long.S deleted file mode 100644 index 459ab7eed09215592ac1f6274713871b3c103f9a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_double_to_long.S +++ /dev/null @@ -1,50 +0,0 @@ - /* - * double-to-long - * - * We have to clip values to long min/max per the specification. The - * expected common case is a "reasonable" value that converts directly - * to modest integer. The EABI convert function isn't doing this for us - * for pre-R6. - */ - /* unop vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - EAS2(a3, rFP, a3) # a3 <- &fp[B] - LOAD64_F(fa0, fa0f, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - -#ifdef MIPS32REVGE6 - GET_INST_OPCODE(t1) # extract opcode from rINST - trunc.l.d fa0, fa0 - SET_VREG64_F_GOTO(fa0, fa0f, rOBJ, t1) # vA <- result -#else - c.eq.d fcc0, fa0, fa0 - li rRESULT0, 0 - li rRESULT1, 0 - bc1f fcc0, .L${opcode}_get_opcode - - li t0, LONG_MIN_AS_DOUBLE_HIGH - mtc1 zero, fa1 - MOVE_TO_FPU_HIGH(t0, fa1, fa1f) - c.ole.d fcc0, fa0, fa1 - li rRESULT1, LONG_MIN_HIGH - bc1t fcc0, .L${opcode}_get_opcode - - neg.d fa1, fa1 - c.ole.d fcc0, fa1, fa0 - nor rRESULT0, rRESULT0, zero - nor rRESULT1, rRESULT1, zero - bc1t fcc0, .L${opcode}_get_opcode - - JAL(__fixdfdi) - GET_INST_OPCODE(t1) # extract opcode from rINST - b .L${opcode}_set_vreg -#endif -%break - -#ifndef MIPS32REVGE6 -.L${opcode}_get_opcode: - GET_INST_OPCODE(t1) # extract opcode from rINST -.L${opcode}_set_vreg: - SET_VREG64_GOTO(rRESULT0, rRESULT1, rOBJ, t1) # vA/vA+1 <- v0/v1 -#endif diff --git a/runtime/interpreter/mterp/mips/op_fill_array_data.S b/runtime/interpreter/mterp/mips/op_fill_array_data.S deleted file mode 100644 index c3cd371636289f776c2731bbab5940899f024673..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_fill_array_data.S +++ /dev/null @@ -1,13 +0,0 @@ - /* fill-array-data vAA, +BBBBBBBB */ - EXPORT_PC() - FETCH(a1, 1) # a1 <- bbbb (lo) - FETCH(a0, 2) # a0 <- BBBB (hi) - GET_OPA(a3) # a3 <- AA - INSERT_HIGH_HALF(a1, a0) # a1 <- BBBBbbbb - GET_VREG(a0, a3) # a0 <- vAA (array object) - EAS1(a1, rPC, a1) # a1 <- PC + BBBBbbbb*2 (array data off.) - JAL(MterpFillArrayData) # v0 <- Mterp(obj, payload) - beqz v0, MterpPossibleException # has exception - FETCH_ADVANCE_INST(3) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction diff --git a/runtime/interpreter/mterp/mips/op_filled_new_array.S b/runtime/interpreter/mterp/mips/op_filled_new_array.S deleted file mode 100644 index 9511578289f02edac729c9c9b0b191dac312a18c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_filled_new_array.S +++ /dev/null @@ -1,18 +0,0 @@ -%default { "helper":"MterpFilledNewArray" } - /* - * Create a new array with elements filled from registers. - * - * for: filled-new-array, filled-new-array/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ - .extern $helper - EXPORT_PC() - addu a0, rFP, OFF_FP_SHADOWFRAME # a0 <- shadow frame - move a1, rPC - move a2, rSELF - JAL($helper) # v0 <- helper(shadow_frame, pc, self) - beqz v0, MterpPossibleException # has exception - FETCH_ADVANCE_INST(3) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction diff --git a/runtime/interpreter/mterp/mips/op_filled_new_array_range.S b/runtime/interpreter/mterp/mips/op_filled_new_array_range.S deleted file mode 100644 index f8dcb0e03783bd7a7e0d69391174da688c7d2d66..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_filled_new_array_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_filled_new_array.S" { "helper":"MterpFilledNewArrayRange" } diff --git a/runtime/interpreter/mterp/mips/op_float_to_double.S b/runtime/interpreter/mterp/mips/op_float_to_double.S deleted file mode 100644 index 1315255b5c64e4aa47acd1b68cda2d170c5c82d3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_float_to_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/funopWider.S" {"instr":"cvt.d.s fv0, fa0"} diff --git a/runtime/interpreter/mterp/mips/op_float_to_int.S b/runtime/interpreter/mterp/mips/op_float_to_int.S deleted file mode 100644 index 26a0988082a300cd25f114d0409aacb984df02da..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_float_to_int.S +++ /dev/null @@ -1,29 +0,0 @@ - /* - * float-to-int - * - * We have to clip values to int min/max per the specification. The - * expected common case is a "reasonable" value that converts directly - * to modest integer. The EABI convert function isn't doing this for us - * for pre-R6. - */ - /* unop vA, vB */ - GET_OPB(a3) # a3 <- B - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_VREG_F(fa0, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - -#ifndef MIPS32REVGE6 - li t0, INT_MIN_AS_FLOAT - mtc1 t0, fa1 - c.ole.s fcc0, fa1, fa0 -#endif - GET_INST_OPCODE(t1) # extract opcode from rINST -#ifndef MIPS32REVGE6 - bc1t fcc0, 1f # if INT_MIN <= vB, proceed to truncation - c.eq.s fcc0, fa0, fa0 - mtc1 zero, fa0 - movt.s fa0, fa1, fcc0 # fa0 = ordered(vB) ? INT_MIN_AS_FLOAT : 0 -1: -#endif - trunc.w.s fa0, fa0 - SET_VREG_F_GOTO(fa0, rOBJ, t1) # vA <- result diff --git a/runtime/interpreter/mterp/mips/op_float_to_long.S b/runtime/interpreter/mterp/mips/op_float_to_long.S deleted file mode 100644 index b8f8efbdcbc495a251e15ec82fae45883c291fa6..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_float_to_long.S +++ /dev/null @@ -1,48 +0,0 @@ - /* - * float-to-long - * - * We have to clip values to long min/max per the specification. The - * expected common case is a "reasonable" value that converts directly - * to modest integer. The EABI convert function isn't doing this for us - * for pre-R6. - */ - /* unop vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG_F(fa0, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - -#ifdef MIPS32REVGE6 - GET_INST_OPCODE(t1) # extract opcode from rINST - trunc.l.s fa0, fa0 - SET_VREG64_F_GOTO(fa0, fa0f, rOBJ, t1) # vA <- result -#else - c.eq.s fcc0, fa0, fa0 - li rRESULT0, 0 - li rRESULT1, 0 - bc1f fcc0, .L${opcode}_get_opcode - - li t0, LONG_MIN_AS_FLOAT - mtc1 t0, fa1 - c.ole.s fcc0, fa0, fa1 - li rRESULT1, LONG_MIN_HIGH - bc1t fcc0, .L${opcode}_get_opcode - - neg.s fa1, fa1 - c.ole.s fcc0, fa1, fa0 - nor rRESULT0, rRESULT0, zero - nor rRESULT1, rRESULT1, zero - bc1t fcc0, .L${opcode}_get_opcode - - JAL(__fixsfdi) - GET_INST_OPCODE(t1) # extract opcode from rINST - b .L${opcode}_set_vreg -#endif -%break - -#ifndef MIPS32REVGE6 -.L${opcode}_get_opcode: - GET_INST_OPCODE(t1) # extract opcode from rINST -.L${opcode}_set_vreg: - SET_VREG64_GOTO(rRESULT0, rRESULT1, rOBJ, t1) # vA/vA+1 <- v0/v1 -#endif diff --git a/runtime/interpreter/mterp/mips/op_goto.S b/runtime/interpreter/mterp/mips/op_goto.S deleted file mode 100644 index 57182a5b590a870e6c6c1f0335f3c9c9f9c0b798..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_goto.S +++ /dev/null @@ -1,10 +0,0 @@ - /* - * Unconditional branch, 8-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto +AA */ - sll a0, rINST, 16 # a0 <- AAxx0000 - sra rINST, a0, 24 # rINST <- ssssssAA (sign-extended) - b MterpCommonTakenBranchNoFlags diff --git a/runtime/interpreter/mterp/mips/op_goto_16.S b/runtime/interpreter/mterp/mips/op_goto_16.S deleted file mode 100644 index 06c96cd5451644324a18d1748520e67371a0b381..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_goto_16.S +++ /dev/null @@ -1,9 +0,0 @@ - /* - * Unconditional branch, 16-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto/16 +AAAA */ - FETCH_S(rINST, 1) # rINST <- ssssAAAA (sign-extended) - b MterpCommonTakenBranchNoFlags diff --git a/runtime/interpreter/mterp/mips/op_goto_32.S b/runtime/interpreter/mterp/mips/op_goto_32.S deleted file mode 100644 index ef5bf6bc8228bca989a6c532cf8f31c641a11b03..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_goto_32.S +++ /dev/null @@ -1,14 +0,0 @@ - /* - * Unconditional branch, 32-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - * - * Unlike most opcodes, this one is allowed to branch to itself, so - * our "backward branch" test must be "<=0" instead of "<0". - */ - /* goto/32 +AAAAAAAA */ - FETCH(rINST, 1) # rINST <- aaaa (lo) - FETCH(a1, 2) # a1 <- AAAA (hi) - INSERT_HIGH_HALF(rINST, a1) # rINST <- AAAAaaaa - b MterpCommonTakenBranchNoFlags diff --git a/runtime/interpreter/mterp/mips/op_if_eq.S b/runtime/interpreter/mterp/mips/op_if_eq.S deleted file mode 100644 index d6f99871865a1e2d34f7bb0bbf2462d6908f7713..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_if_eq.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/bincmp.S" { "condition":"eq" } diff --git a/runtime/interpreter/mterp/mips/op_if_eqz.S b/runtime/interpreter/mterp/mips/op_if_eqz.S deleted file mode 100644 index c52b76a755999a93323f309eb670d121c0b8b428..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_if_eqz.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/zcmp.S" { "condition":"eq" } diff --git a/runtime/interpreter/mterp/mips/op_if_ge.S b/runtime/interpreter/mterp/mips/op_if_ge.S deleted file mode 100644 index bd06ff5ad49dd61077db9b4de3f175e0e46380c5..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_if_ge.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/bincmp.S" { "condition":"ge" } diff --git a/runtime/interpreter/mterp/mips/op_if_gez.S b/runtime/interpreter/mterp/mips/op_if_gez.S deleted file mode 100644 index 549231a15ff0f5662495c3be463228f538444403..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_if_gez.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/zcmp.S" { "condition":"ge" } diff --git a/runtime/interpreter/mterp/mips/op_if_gt.S b/runtime/interpreter/mterp/mips/op_if_gt.S deleted file mode 100644 index 0be30912edd940b409321963483b282ced27cf41..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_if_gt.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/bincmp.S" { "condition":"gt" } diff --git a/runtime/interpreter/mterp/mips/op_if_gtz.S b/runtime/interpreter/mterp/mips/op_if_gtz.S deleted file mode 100644 index 5c7bcc48b5d247d7c2e8933a4b574ac7b2bf180a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_if_gtz.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/zcmp.S" { "condition":"gt" } diff --git a/runtime/interpreter/mterp/mips/op_if_le.S b/runtime/interpreter/mterp/mips/op_if_le.S deleted file mode 100644 index c35c1a24b7975a2727dc409581e832b2fb2ee551..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_if_le.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/bincmp.S" { "condition":"le" } diff --git a/runtime/interpreter/mterp/mips/op_if_lez.S b/runtime/interpreter/mterp/mips/op_if_lez.S deleted file mode 100644 index 3dc6543d900cd678cfee225218b0ef65772517ea..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_if_lez.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/zcmp.S" { "condition":"le" } diff --git a/runtime/interpreter/mterp/mips/op_if_lt.S b/runtime/interpreter/mterp/mips/op_if_lt.S deleted file mode 100644 index 3f3386c9d266e31b0ee9c838eb0f1ba772a5c732..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_if_lt.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/bincmp.S" { "condition":"lt" } diff --git a/runtime/interpreter/mterp/mips/op_if_ltz.S b/runtime/interpreter/mterp/mips/op_if_ltz.S deleted file mode 100644 index e6d6ed6aa6ce73a38695f29fefea67a7ea28c929..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_if_ltz.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/zcmp.S" { "condition":"lt" } diff --git a/runtime/interpreter/mterp/mips/op_if_ne.S b/runtime/interpreter/mterp/mips/op_if_ne.S deleted file mode 100644 index 3d7bf350f19217d713eca694280f83ab4a0db0a8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_if_ne.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/bincmp.S" { "condition":"ne" } diff --git a/runtime/interpreter/mterp/mips/op_if_nez.S b/runtime/interpreter/mterp/mips/op_if_nez.S deleted file mode 100644 index d121eae930fdd07ed3f7791641dafb8795462d8b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_if_nez.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/zcmp.S" { "condition":"ne" } diff --git a/runtime/interpreter/mterp/mips/op_iget.S b/runtime/interpreter/mterp/mips/op_iget.S deleted file mode 100644 index e21827219632a71bdcf296251fc14def5bee1fbb..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_iget.S +++ /dev/null @@ -1,2 +0,0 @@ -%default { "is_object":"0", "helper":"MterpIGetU32"} -%include "mips/field.S" { } diff --git a/runtime/interpreter/mterp/mips/op_iget_boolean.S b/runtime/interpreter/mterp/mips/op_iget_boolean.S deleted file mode 100644 index f2ef68d8b25cac4d015890957fd3a976b245ce50..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_iget_boolean.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_iget.S" { "helper":"MterpIGetU8" } diff --git a/runtime/interpreter/mterp/mips/op_iget_boolean_quick.S b/runtime/interpreter/mterp/mips/op_iget_boolean_quick.S deleted file mode 100644 index f3032b3d8432cbe52185b7bdb361b5590d417253..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_iget_boolean_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_iget_quick.S" { "load":"lbu" } diff --git a/runtime/interpreter/mterp/mips/op_iget_byte.S b/runtime/interpreter/mterp/mips/op_iget_byte.S deleted file mode 100644 index 0c8fb7cf2c7695e1e141220a776fc363f85565fe..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_iget_byte.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_iget.S" { "helper":"MterpIGetI8" } diff --git a/runtime/interpreter/mterp/mips/op_iget_byte_quick.S b/runtime/interpreter/mterp/mips/op_iget_byte_quick.S deleted file mode 100644 index d93f84486d52a0b33c254917b359d9e1ce939ca0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_iget_byte_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_iget_quick.S" { "load":"lb" } diff --git a/runtime/interpreter/mterp/mips/op_iget_char.S b/runtime/interpreter/mterp/mips/op_iget_char.S deleted file mode 100644 index 69d04c4fa89a306b7e44f6cdcbdefffa257f3226..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_iget_char.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_iget.S" { "helper":"MterpIGetU16" } diff --git a/runtime/interpreter/mterp/mips/op_iget_char_quick.S b/runtime/interpreter/mterp/mips/op_iget_char_quick.S deleted file mode 100644 index 6f6d6088e04474495ceed7535c390aad0e2a067c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_iget_char_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_iget_quick.S" { "load":"lhu" } diff --git a/runtime/interpreter/mterp/mips/op_iget_object.S b/runtime/interpreter/mterp/mips/op_iget_object.S deleted file mode 100644 index bea330a14b69dd2fe2b14c95a4205d18df753802..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_iget_object.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_iget.S" { "is_object":"1", "helper":"MterpIGetObj" } diff --git a/runtime/interpreter/mterp/mips/op_iget_object_quick.S b/runtime/interpreter/mterp/mips/op_iget_object_quick.S deleted file mode 100644 index 95c34d7b3f60ebd4df3685fddf577f9866a377b0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_iget_object_quick.S +++ /dev/null @@ -1,14 +0,0 @@ - /* For: iget-object-quick */ - /* op vA, vB, offset@CCCC */ - GET_OPB(a2) # a2 <- B - FETCH(a1, 1) # a1 <- field byte offset - EXPORT_PC() - GET_VREG(a0, a2) # a0 <- object we're operating on - JAL(artIGetObjectFromMterp) # v0 <- GetObj(obj, offset) - lw a3, THREAD_EXCEPTION_OFFSET(rSELF) - GET_OPA4(a2) # a2<- A+ - PREFETCH_INST(2) # load rINST - bnez a3, MterpPossibleException # bail out - ADVANCE(2) # advance rPC - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_OBJECT_GOTO(v0, a2, t0) # fp[A] <- v0 diff --git a/runtime/interpreter/mterp/mips/op_iget_quick.S b/runtime/interpreter/mterp/mips/op_iget_quick.S deleted file mode 100644 index 46277d30cbfb4ec33e826c6b6c3ed30b04e8a413..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_iget_quick.S +++ /dev/null @@ -1,14 +0,0 @@ -%default { "load":"lw" } - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset@CCCC */ - GET_OPB(a2) # a2 <- B - GET_VREG(a3, a2) # a3 <- object we're operating on - FETCH(a1, 1) # a1 <- field byte offset - GET_OPA4(a2) # a2 <- A(+) - # check object for null - beqz a3, common_errNullObject # object was null - addu t0, a3, a1 - $load a0, 0(t0) # a0 <- obj.field (8/16/32 bits) - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, a2, t0) # fp[A] <- a0 diff --git a/runtime/interpreter/mterp/mips/op_iget_short.S b/runtime/interpreter/mterp/mips/op_iget_short.S deleted file mode 100644 index 357c7918e43150a1b967a51e75367bfdf7cda073..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_iget_short.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_iget.S" { "helper":"MterpIGetI16" } diff --git a/runtime/interpreter/mterp/mips/op_iget_short_quick.S b/runtime/interpreter/mterp/mips/op_iget_short_quick.S deleted file mode 100644 index 899a0feb656acdaefe7b404832959bbeaf2188ce..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_iget_short_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_iget_quick.S" { "load":"lh" } diff --git a/runtime/interpreter/mterp/mips/op_iget_wide.S b/runtime/interpreter/mterp/mips/op_iget_wide.S deleted file mode 100644 index 885372a529b089dd9d0a6bfc80bcdd6375c484b1..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_iget_wide.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_iget.S" { "helper":"MterpIGetU64" } diff --git a/runtime/interpreter/mterp/mips/op_iget_wide_quick.S b/runtime/interpreter/mterp/mips/op_iget_wide_quick.S deleted file mode 100644 index 128be571f8eee86a6d500c0fcecba4134354b59c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_iget_wide_quick.S +++ /dev/null @@ -1,12 +0,0 @@ - /* iget-wide-quick vA, vB, offset@CCCC */ - GET_OPB(a2) # a2 <- B - GET_VREG(a3, a2) # a3 <- object we're operating on - FETCH(a1, 1) # a1 <- field byte offset - GET_OPA4(a2) # a2 <- A(+) - # check object for null - beqz a3, common_errNullObject # object was null - addu t0, a3, a1 # t0 <- a3 + a1 - LOAD64(a0, a1, t0) # a0 <- obj.field (64 bits, aligned) - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(a0, a1, a2, t0) # fp[A] <- a0/a1 diff --git a/runtime/interpreter/mterp/mips/op_instance_of.S b/runtime/interpreter/mterp/mips/op_instance_of.S deleted file mode 100644 index 706dcf37a1e85d778a6bbd8071bbae5409fd780c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_instance_of.S +++ /dev/null @@ -1,21 +0,0 @@ - /* - * Check to see if an object reference is an instance of a class. - * - * Most common situation is a non-null object, being compared against - * an already-resolved class. - */ - /* instance-of vA, vB, class@CCCC */ - EXPORT_PC() - FETCH(a0, 1) # a0 <- CCCC - GET_OPB(a1) # a1 <- B - EAS2(a1, rFP, a1) # a1 <- &object - lw a2, OFF_FP_METHOD(rFP) # a2 <- method - move a3, rSELF # a3 <- self - GET_OPA4(rOBJ) # rOBJ <- A+ - JAL(MterpInstanceOf) # v0 <- Mterp(index, &obj, method, self) - lw a1, THREAD_EXCEPTION_OFFSET(rSELF) - PREFETCH_INST(2) # load rINST - bnez a1, MterpException - ADVANCE(2) # advance rPC - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(v0, rOBJ, t0) # vA <- v0 diff --git a/runtime/interpreter/mterp/mips/op_int_to_byte.S b/runtime/interpreter/mterp/mips/op_int_to_byte.S deleted file mode 100644 index 9266aab020cbf9c744789d3d68c29521c563f7a6..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_int_to_byte.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/unop.S" {"instr":"SEB(a0, a0)"} diff --git a/runtime/interpreter/mterp/mips/op_int_to_char.S b/runtime/interpreter/mterp/mips/op_int_to_char.S deleted file mode 100644 index 1b74a6e2494bb7a5f4a23e08bec5a2f17ae70b14..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_int_to_char.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/unop.S" {"preinstr":"", "instr":"and a0, 0xffff"} diff --git a/runtime/interpreter/mterp/mips/op_int_to_double.S b/runtime/interpreter/mterp/mips/op_int_to_double.S deleted file mode 100644 index 89484ce34ffa12a98f25c4b91f1c5a1169f8eff3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_int_to_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/funopWider.S" {"instr":"cvt.d.w fv0, fa0"} diff --git a/runtime/interpreter/mterp/mips/op_int_to_float.S b/runtime/interpreter/mterp/mips/op_int_to_float.S deleted file mode 100644 index d6f4b3609f893ad71f9b1dcc89a3a9a3d94a7ef3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_int_to_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/funop.S" {"instr":"cvt.s.w fv0, fa0"} diff --git a/runtime/interpreter/mterp/mips/op_int_to_long.S b/runtime/interpreter/mterp/mips/op_int_to_long.S deleted file mode 100644 index 99074639508a73da979508bfe0e1648bfebbaed2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_int_to_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/unopWider.S" {"instr":"sra a1, a0, 31"} diff --git a/runtime/interpreter/mterp/mips/op_int_to_short.S b/runtime/interpreter/mterp/mips/op_int_to_short.S deleted file mode 100644 index 8749cd87173c7cd2f9c939ece4da0713098ae117..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_int_to_short.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/unop.S" {"instr":"SEH(a0, a0)"} diff --git a/runtime/interpreter/mterp/mips/op_invoke_custom.S b/runtime/interpreter/mterp/mips/op_invoke_custom.S deleted file mode 100644 index f9241c43c6a086a4fa45cbf0218bc6d7c10a75ae..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_invoke_custom.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/invoke.S" { "helper":"MterpInvokeCustom" } diff --git a/runtime/interpreter/mterp/mips/op_invoke_custom_range.S b/runtime/interpreter/mterp/mips/op_invoke_custom_range.S deleted file mode 100644 index 862a6144044889985e8389538f01e0e5b7a08a10..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_invoke_custom_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/invoke.S" { "helper":"MterpInvokeCustomRange" } diff --git a/runtime/interpreter/mterp/mips/op_invoke_direct.S b/runtime/interpreter/mterp/mips/op_invoke_direct.S deleted file mode 100644 index 1ef198a43462db4b1b30b8146d9ebc2614627476..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_invoke_direct.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/invoke.S" { "helper":"MterpInvokeDirect" } diff --git a/runtime/interpreter/mterp/mips/op_invoke_direct_range.S b/runtime/interpreter/mterp/mips/op_invoke_direct_range.S deleted file mode 100644 index af7477f2cd82d73cf4d65e0e02d97442ed1c13bd..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_invoke_direct_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/invoke.S" { "helper":"MterpInvokeDirectRange" } diff --git a/runtime/interpreter/mterp/mips/op_invoke_interface.S b/runtime/interpreter/mterp/mips/op_invoke_interface.S deleted file mode 100644 index 80a485a077924dfca16e6dc3279ae29d4a9e2269..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_invoke_interface.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/invoke.S" { "helper":"MterpInvokeInterface" } diff --git a/runtime/interpreter/mterp/mips/op_invoke_interface_range.S b/runtime/interpreter/mterp/mips/op_invoke_interface_range.S deleted file mode 100644 index 8d725dc2049da7cbd0d0ed6fbd8acee20a54b941..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_invoke_interface_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/invoke.S" { "helper":"MterpInvokeInterfaceRange" } diff --git a/runtime/interpreter/mterp/mips/op_invoke_polymorphic.S b/runtime/interpreter/mterp/mips/op_invoke_polymorphic.S deleted file mode 100644 index 85e01e7221f4d63a2dc6415323581350e9258f1b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_invoke_polymorphic.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/invoke_polymorphic.S" { "helper":"MterpInvokePolymorphic" } diff --git a/runtime/interpreter/mterp/mips/op_invoke_polymorphic_range.S b/runtime/interpreter/mterp/mips/op_invoke_polymorphic_range.S deleted file mode 100644 index ce6397837be73c1440636d53b44b7ddd48f8dae3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_invoke_polymorphic_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/invoke_polymorphic.S" { "helper":"MterpInvokePolymorphicRange" } diff --git a/runtime/interpreter/mterp/mips/op_invoke_static.S b/runtime/interpreter/mterp/mips/op_invoke_static.S deleted file mode 100644 index 46253cb3a7ee137169954a6dbb0ad04e55e112ca..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_invoke_static.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/invoke.S" { "helper":"MterpInvokeStatic" } diff --git a/runtime/interpreter/mterp/mips/op_invoke_static_range.S b/runtime/interpreter/mterp/mips/op_invoke_static_range.S deleted file mode 100644 index 96abafe41d9418d88239c7ec21cb1ca84059c621..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_invoke_static_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/invoke.S" { "helper":"MterpInvokeStaticRange" } diff --git a/runtime/interpreter/mterp/mips/op_invoke_super.S b/runtime/interpreter/mterp/mips/op_invoke_super.S deleted file mode 100644 index 473951bcce4ac2366da46483c8fd88e4764da73d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_invoke_super.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/invoke.S" { "helper":"MterpInvokeSuper" } diff --git a/runtime/interpreter/mterp/mips/op_invoke_super_range.S b/runtime/interpreter/mterp/mips/op_invoke_super_range.S deleted file mode 100644 index 963ff27ec5b47896c6aa8b45b971d7afee4000de..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_invoke_super_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/invoke.S" { "helper":"MterpInvokeSuperRange" } diff --git a/runtime/interpreter/mterp/mips/op_invoke_virtual.S b/runtime/interpreter/mterp/mips/op_invoke_virtual.S deleted file mode 100644 index ea51e98abc20d7dbd4d90618466eab1fb2288c84..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_invoke_virtual.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/invoke.S" { "helper":"MterpInvokeVirtual" } diff --git a/runtime/interpreter/mterp/mips/op_invoke_virtual_quick.S b/runtime/interpreter/mterp/mips/op_invoke_virtual_quick.S deleted file mode 100644 index 0c00091219e4a6d56757714a2635a49e674e28bd..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_invoke_virtual_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/invoke.S" { "helper":"MterpInvokeVirtualQuick" } diff --git a/runtime/interpreter/mterp/mips/op_invoke_virtual_range.S b/runtime/interpreter/mterp/mips/op_invoke_virtual_range.S deleted file mode 100644 index 82201e726e45d470db2be51cc1525a5d094f772e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_invoke_virtual_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/invoke.S" { "helper":"MterpInvokeVirtualRange" } diff --git a/runtime/interpreter/mterp/mips/op_invoke_virtual_range_quick.S b/runtime/interpreter/mterp/mips/op_invoke_virtual_range_quick.S deleted file mode 100644 index c783675dae9dbf4fe391f1a0b0ba52734f40bdb8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_invoke_virtual_range_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/invoke.S" { "helper":"MterpInvokeVirtualQuickRange" } diff --git a/runtime/interpreter/mterp/mips/op_iput.S b/runtime/interpreter/mterp/mips/op_iput.S deleted file mode 100644 index efbdfbad78948916a8071c57a5c773319baf2dd3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_iput.S +++ /dev/null @@ -1,2 +0,0 @@ -%default { "is_object":"0", "helper":"MterpIPutU32" } -%include "mips/field.S" { } diff --git a/runtime/interpreter/mterp/mips/op_iput_boolean.S b/runtime/interpreter/mterp/mips/op_iput_boolean.S deleted file mode 100644 index 55ac4cedaaa7a81461fa6d18fa21d15cf63253d1..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_iput_boolean.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_iput.S" { "helper":"MterpIPutU8" } diff --git a/runtime/interpreter/mterp/mips/op_iput_boolean_quick.S b/runtime/interpreter/mterp/mips/op_iput_boolean_quick.S deleted file mode 100644 index 7d5caf6d6af22ac015214277200152d40eec78b8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_iput_boolean_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_iput_quick.S" { "store":"sb" } diff --git a/runtime/interpreter/mterp/mips/op_iput_byte.S b/runtime/interpreter/mterp/mips/op_iput_byte.S deleted file mode 100644 index 61e489be11ed4e128dc885b6be785aeacf73711a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_iput_byte.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_iput.S" { "helper":"MterpIPutI8" } diff --git a/runtime/interpreter/mterp/mips/op_iput_byte_quick.S b/runtime/interpreter/mterp/mips/op_iput_byte_quick.S deleted file mode 100644 index 7d5caf6d6af22ac015214277200152d40eec78b8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_iput_byte_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_iput_quick.S" { "store":"sb" } diff --git a/runtime/interpreter/mterp/mips/op_iput_char.S b/runtime/interpreter/mterp/mips/op_iput_char.S deleted file mode 100644 index 2caad1e0a63040058adfb9d8dd6d29e3415e852e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_iput_char.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_iput.S" { "helper":"MterpIPutU16" } diff --git a/runtime/interpreter/mterp/mips/op_iput_char_quick.S b/runtime/interpreter/mterp/mips/op_iput_char_quick.S deleted file mode 100644 index 4bc84eb581eb55096654695dc85fc876b99e320a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_iput_char_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_iput_quick.S" { "store":"sh" } diff --git a/runtime/interpreter/mterp/mips/op_iput_object.S b/runtime/interpreter/mterp/mips/op_iput_object.S deleted file mode 100644 index 6f7e7b760f2fbb453a1f1cbd78ef137249f85f8c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_iput_object.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_iput.S" { "is_object":"1", "helper":"MterpIPutObj" } diff --git a/runtime/interpreter/mterp/mips/op_iput_object_quick.S b/runtime/interpreter/mterp/mips/op_iput_object_quick.S deleted file mode 100644 index 82044f51c8a776037f287f920b3a71111545ebe5..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_iput_object_quick.S +++ /dev/null @@ -1,11 +0,0 @@ - /* For: iput-object-quick */ - /* op vA, vB, offset@CCCC */ - EXPORT_PC() - addu a0, rFP, OFF_FP_SHADOWFRAME - move a1, rPC - move a2, rINST - JAL(MterpIputObjectQuick) - beqz v0, MterpException - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction diff --git a/runtime/interpreter/mterp/mips/op_iput_quick.S b/runtime/interpreter/mterp/mips/op_iput_quick.S deleted file mode 100644 index d9753b1409d0d22d608cdc16ae4512e25169e009..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_iput_quick.S +++ /dev/null @@ -1,15 +0,0 @@ -%default { "store":"sw" } - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - GET_OPB(a2) # a2 <- B - GET_VREG(a3, a2) # a3 <- fp[B], the object pointer - FETCH(a1, 1) # a1 <- field byte offset - GET_OPA4(a2) # a2 <- A(+) - beqz a3, common_errNullObject # object was null - GET_VREG(a0, a2) # a0 <- fp[A] - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - addu t0, a3, a1 - GET_INST_OPCODE(t1) # extract opcode from rINST - GET_OPCODE_TARGET(t1) - $store a0, 0(t0) # obj.field (8/16/32 bits) <- a0 - JR(t1) # jump to next instruction diff --git a/runtime/interpreter/mterp/mips/op_iput_short.S b/runtime/interpreter/mterp/mips/op_iput_short.S deleted file mode 100644 index 414a15bd70a8e24295fe7df108c2e88682cd95fb..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_iput_short.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_iput.S" { "helper":"MterpIPutI16" } diff --git a/runtime/interpreter/mterp/mips/op_iput_short_quick.S b/runtime/interpreter/mterp/mips/op_iput_short_quick.S deleted file mode 100644 index 4bc84eb581eb55096654695dc85fc876b99e320a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_iput_short_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_iput_quick.S" { "store":"sh" } diff --git a/runtime/interpreter/mterp/mips/op_iput_wide.S b/runtime/interpreter/mterp/mips/op_iput_wide.S deleted file mode 100644 index fc862e4fa741ad342c98231395112346d9938ec0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_iput_wide.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_iput.S" { "helper":"MterpIPutU64" } diff --git a/runtime/interpreter/mterp/mips/op_iput_wide_quick.S b/runtime/interpreter/mterp/mips/op_iput_wide_quick.S deleted file mode 100644 index 0eb228d005ddc55a6ede4ca014f21d52a185459e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_iput_wide_quick.S +++ /dev/null @@ -1,15 +0,0 @@ - /* iput-wide-quick vA, vB, offset@CCCC */ - GET_OPA4(a0) # a0 <- A(+) - GET_OPB(a1) # a1 <- B - GET_VREG(a2, a1) # a2 <- fp[B], the object pointer - # check object for null - beqz a2, common_errNullObject # object was null - EAS2(a3, rFP, a0) # a3 <- &fp[A] - LOAD64(a0, a1, a3) # a0/a1 <- fp[A] - FETCH(a3, 1) # a3 <- field byte offset - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - addu a2, a2, a3 # obj.field (64 bits, aligned) <- a0/a1 - GET_INST_OPCODE(t0) # extract opcode from rINST - GET_OPCODE_TARGET(t0) - STORE64(a0, a1, a2) # obj.field (64 bits, aligned) <- a0/a1 - JR(t0) # jump to next instruction diff --git a/runtime/interpreter/mterp/mips/op_long_to_double.S b/runtime/interpreter/mterp/mips/op_long_to_double.S deleted file mode 100644 index 153f58210adea0c4038a97cc83c2a70296abea4e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_long_to_double.S +++ /dev/null @@ -1,20 +0,0 @@ - /* - * long-to-double - */ - /* unop vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - EAS2(a3, rFP, a3) # a3 <- &fp[B] - -#ifdef MIPS32REVGE6 - LOAD64_F(fv0, fv0f, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - cvt.d.l fv0, fv0 -#else - LOAD64(rARG0, rARG1, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - JAL(__floatdidf) # a0/a1 <- op, a2-a3 changed -#endif - - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vA/vA+1 <- result diff --git a/runtime/interpreter/mterp/mips/op_long_to_float.S b/runtime/interpreter/mterp/mips/op_long_to_float.S deleted file mode 100644 index dd1ab81f4dca88b95ea73a01104834df647a0a32..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_long_to_float.S +++ /dev/null @@ -1,20 +0,0 @@ - /* - * long-to-float - */ - /* unop vA, vB */ - GET_OPB(a3) # a3 <- B - GET_OPA4(rOBJ) # rOBJ <- A+ - EAS2(a3, rFP, a3) # a3 <- &fp[B] - -#ifdef MIPS32REVGE6 - LOAD64_F(fv0, fv0f, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - cvt.s.l fv0, fv0 -#else - LOAD64(rARG0, rARG1, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - JAL(__floatdisf) -#endif - - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_F_GOTO(fv0, rOBJ, t0) # vA <- fv0 diff --git a/runtime/interpreter/mterp/mips/op_long_to_int.S b/runtime/interpreter/mterp/mips/op_long_to_int.S deleted file mode 100644 index 949c180f3121797f275dc426dc5e52164638b457..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_long_to_int.S +++ /dev/null @@ -1,2 +0,0 @@ -/* we ignore the high word, making this equivalent to a 32-bit reg move */ -%include "mips/op_move.S" diff --git a/runtime/interpreter/mterp/mips/op_monitor_enter.S b/runtime/interpreter/mterp/mips/op_monitor_enter.S deleted file mode 100644 index 20d90294ac7fabdf6a6a2089dc19d80056c89907..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_monitor_enter.S +++ /dev/null @@ -1,13 +0,0 @@ - /* - * Synchronize on an object. - */ - /* monitor-enter vAA */ - EXPORT_PC() - GET_OPA(a2) # a2 <- AA - GET_VREG(a0, a2) # a0 <- vAA (object) - move a1, rSELF # a1 <- self - JAL(artLockObjectFromCode) # v0 <- artLockObject(obj, self) - bnez v0, MterpException - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction diff --git a/runtime/interpreter/mterp/mips/op_monitor_exit.S b/runtime/interpreter/mterp/mips/op_monitor_exit.S deleted file mode 100644 index 1eadff923b4df419853b79ea6284bf454766c5bd..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_monitor_exit.S +++ /dev/null @@ -1,17 +0,0 @@ - /* - * Unlock an object. - * - * Exceptions that occur when unlocking a monitor need to appear as - * if they happened at the following instruction. See the Dalvik - * instruction spec. - */ - /* monitor-exit vAA */ - EXPORT_PC() - GET_OPA(a2) # a2 <- AA - GET_VREG(a0, a2) # a0 <- vAA (object) - move a1, rSELF # a1 <- self - JAL(artUnlockObjectFromCode) # v0 <- artUnlockObject(obj, self) - bnez v0, MterpException - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction diff --git a/runtime/interpreter/mterp/mips/op_move.S b/runtime/interpreter/mterp/mips/op_move.S deleted file mode 100644 index 547ea3a18517bf6e4a887dd5fd8196487a52a7e3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_move.S +++ /dev/null @@ -1,13 +0,0 @@ -%default { "is_object":"0" } - /* for move, move-object, long-to-int */ - /* op vA, vB */ - GET_OPB(a1) # a1 <- B from 15:12 - GET_OPA4(a0) # a0 <- A from 11:8 - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - GET_VREG(a2, a1) # a2 <- fp[B] - GET_INST_OPCODE(t0) # t0 <- opcode from rINST - .if $is_object - SET_VREG_OBJECT_GOTO(a2, a0, t0) # fp[A] <- a2 - .else - SET_VREG_GOTO(a2, a0, t0) # fp[A] <- a2 - .endif diff --git a/runtime/interpreter/mterp/mips/op_move_16.S b/runtime/interpreter/mterp/mips/op_move_16.S deleted file mode 100644 index 91b73996b5ed7d03423e88756add8a0cbc20743e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_move_16.S +++ /dev/null @@ -1,13 +0,0 @@ -%default { "is_object":"0" } - /* for: move/16, move-object/16 */ - /* op vAAAA, vBBBB */ - FETCH(a1, 2) # a1 <- BBBB - FETCH(a0, 1) # a0 <- AAAA - FETCH_ADVANCE_INST(3) # advance rPC, load rINST - GET_VREG(a2, a1) # a2 <- fp[BBBB] - GET_INST_OPCODE(t0) # extract opcode from rINST - .if $is_object - SET_VREG_OBJECT_GOTO(a2, a0, t0) # fp[AAAA] <- a2 - .else - SET_VREG_GOTO(a2, a0, t0) # fp[AAAA] <- a2 - .endif diff --git a/runtime/interpreter/mterp/mips/op_move_exception.S b/runtime/interpreter/mterp/mips/op_move_exception.S deleted file mode 100644 index f1bece7be8448d720f34833bded0fb5590da46ea..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_move_exception.S +++ /dev/null @@ -1,9 +0,0 @@ - /* move-exception vAA */ - GET_OPA(a2) # a2 <- AA - lw a3, THREAD_EXCEPTION_OFFSET(rSELF) # get exception obj - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GET_OPCODE_TARGET(t0) - SET_VREG_OBJECT(a3, a2) # fp[AA] <- exception obj - sw zero, THREAD_EXCEPTION_OFFSET(rSELF) # clear exception - JR(t0) # jump to next instruction diff --git a/runtime/interpreter/mterp/mips/op_move_from16.S b/runtime/interpreter/mterp/mips/op_move_from16.S deleted file mode 100644 index 90c25c970569f000b95a692591c8dd121e2c3b7d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_move_from16.S +++ /dev/null @@ -1,13 +0,0 @@ -%default { "is_object":"0" } - /* for: move/from16, move-object/from16 */ - /* op vAA, vBBBB */ - FETCH(a1, 1) # a1 <- BBBB - GET_OPA(a0) # a0 <- AA - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_VREG(a2, a1) # a2 <- fp[BBBB] - GET_INST_OPCODE(t0) # extract opcode from rINST - .if $is_object - SET_VREG_OBJECT_GOTO(a2, a0, t0) # fp[AA] <- a2 - .else - SET_VREG_GOTO(a2, a0, t0) # fp[AA] <- a2 - .endif diff --git a/runtime/interpreter/mterp/mips/op_move_object.S b/runtime/interpreter/mterp/mips/op_move_object.S deleted file mode 100644 index 9420ff359f13a729053bf6094be03726082e0670..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_move_object.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_move.S" {"is_object":"1"} diff --git a/runtime/interpreter/mterp/mips/op_move_object_16.S b/runtime/interpreter/mterp/mips/op_move_object_16.S deleted file mode 100644 index d6454c222d4528831731000ae7a945ce9d137a36..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_move_object_16.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_move_16.S" {"is_object":"1"} diff --git a/runtime/interpreter/mterp/mips/op_move_object_from16.S b/runtime/interpreter/mterp/mips/op_move_object_from16.S deleted file mode 100644 index db0aca1f83a0d4d1963da2d2d8e165c836647055..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_move_object_from16.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_move_from16.S" {"is_object":"1"} diff --git a/runtime/interpreter/mterp/mips/op_move_result.S b/runtime/interpreter/mterp/mips/op_move_result.S deleted file mode 100644 index a4d5bfef6a1c4cc61b894386e12da3833a694e6c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_move_result.S +++ /dev/null @@ -1,13 +0,0 @@ -%default { "is_object":"0" } - /* for: move-result, move-result-object */ - /* op vAA */ - GET_OPA(a2) # a2 <- AA - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - lw a0, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType - lw a0, 0(a0) # a0 <- result.i - GET_INST_OPCODE(t0) # extract opcode from rINST - .if $is_object - SET_VREG_OBJECT_GOTO(a0, a2, t0) # fp[AA] <- a0 - .else - SET_VREG_GOTO(a0, a2, t0) # fp[AA] <- a0 - .endif diff --git a/runtime/interpreter/mterp/mips/op_move_result_object.S b/runtime/interpreter/mterp/mips/op_move_result_object.S deleted file mode 100644 index fcbffee28111d1c09edc3df2e9d2d1c73084219a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_move_result_object.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_move_result.S" {"is_object":"1"} diff --git a/runtime/interpreter/mterp/mips/op_move_result_wide.S b/runtime/interpreter/mterp/mips/op_move_result_wide.S deleted file mode 100644 index 1259218c3485f05e4f480c62cb1ac853e42a6001..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_move_result_wide.S +++ /dev/null @@ -1,7 +0,0 @@ - /* move-result-wide vAA */ - GET_OPA(a2) # a2 <- AA - lw a3, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType - LOAD64(a0, a1, a3) # a0/a1 <- retval.j - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(a0, a1, a2, t0) # fp[AA] <- a0/a1 diff --git a/runtime/interpreter/mterp/mips/op_move_wide.S b/runtime/interpreter/mterp/mips/op_move_wide.S deleted file mode 100644 index 01d094914bbf7fce34e949281eb739c6cd2320aa..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_move_wide.S +++ /dev/null @@ -1,9 +0,0 @@ - /* move-wide vA, vB */ - /* NOTE: regs can overlap, e.g. "move v6, v7" or "move v7, v6" */ - GET_OPA4(a2) # a2 <- A(+) - GET_OPB(a3) # a3 <- B - EAS2(a3, rFP, a3) # a3 <- &fp[B] - LOAD64(a0, a1, a3) # a0/a1 <- fp[B] - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(a0, a1, a2, t0) # fp[A] <- a0/a1 diff --git a/runtime/interpreter/mterp/mips/op_move_wide_16.S b/runtime/interpreter/mterp/mips/op_move_wide_16.S deleted file mode 100644 index 587ba04b9d1f0819375065ba131f81e20e94844e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_move_wide_16.S +++ /dev/null @@ -1,9 +0,0 @@ - /* move-wide/16 vAAAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6, v7" or "move v7, v6" */ - FETCH(a3, 2) # a3 <- BBBB - FETCH(a2, 1) # a2 <- AAAA - EAS2(a3, rFP, a3) # a3 <- &fp[BBBB] - LOAD64(a0, a1, a3) # a0/a1 <- fp[BBBB] - FETCH_ADVANCE_INST(3) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(a0, a1, a2, t0) # fp[AAAA] <- a0/a1 diff --git a/runtime/interpreter/mterp/mips/op_move_wide_from16.S b/runtime/interpreter/mterp/mips/op_move_wide_from16.S deleted file mode 100644 index 5003fbdb2476600b598d1dc893b70b415514aa62..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_move_wide_from16.S +++ /dev/null @@ -1,9 +0,0 @@ - /* move-wide/from16 vAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6, v7" or "move v7, v6" */ - FETCH(a3, 1) # a3 <- BBBB - GET_OPA(a2) # a2 <- AA - EAS2(a3, rFP, a3) # a3 <- &fp[BBBB] - LOAD64(a0, a1, a3) # a0/a1 <- fp[BBBB] - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(a0, a1, a2, t0) # fp[AA] <- a0/a1 diff --git a/runtime/interpreter/mterp/mips/op_mul_double.S b/runtime/interpreter/mterp/mips/op_mul_double.S deleted file mode 100644 index 44a473bac108ff9a8a9e77d09153cd53dc32e0e9..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_mul_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/fbinopWide.S" {"instr":"mul.d fv0, fa0, fa1"} diff --git a/runtime/interpreter/mterp/mips/op_mul_double_2addr.S b/runtime/interpreter/mterp/mips/op_mul_double_2addr.S deleted file mode 100644 index 4e5c230bc5da0344e12b7a010ae1c0e6c560b8b3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_mul_double_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/fbinopWide2addr.S" {"instr":"mul.d fv0, fa0, fa1"} diff --git a/runtime/interpreter/mterp/mips/op_mul_float.S b/runtime/interpreter/mterp/mips/op_mul_float.S deleted file mode 100644 index abc939054382ba5465fcb4b59a51e9a9eceec0a2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_mul_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/fbinop.S" {"instr":"mul.s fv0, fa0, fa1"} diff --git a/runtime/interpreter/mterp/mips/op_mul_float_2addr.S b/runtime/interpreter/mterp/mips/op_mul_float_2addr.S deleted file mode 100644 index 24691095185ada93609a6cfd2aa13499e8c0ebb2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_mul_float_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/fbinop2addr.S" {"instr":"mul.s fv0, fa0, fa1"} diff --git a/runtime/interpreter/mterp/mips/op_mul_int.S b/runtime/interpreter/mterp/mips/op_mul_int.S deleted file mode 100644 index 266823c2c7c03013fa03e9897f980940d9a68195..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_mul_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/binop.S" {"instr":"mul a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips/op_mul_int_2addr.S b/runtime/interpreter/mterp/mips/op_mul_int_2addr.S deleted file mode 100644 index b7dc5d3fb1ba37234ad79f0fc2a664ce61e0dc12..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_mul_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/binop2addr.S" {"instr":"mul a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips/op_mul_int_lit16.S b/runtime/interpreter/mterp/mips/op_mul_int_lit16.S deleted file mode 100644 index fb4c8ec27d2583eec69b540646067508a3769d4e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_mul_int_lit16.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/binopLit16.S" {"instr":"mul a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips/op_mul_int_lit8.S b/runtime/interpreter/mterp/mips/op_mul_int_lit8.S deleted file mode 100644 index 6d2e7ded0cccb920bc6e1909ceb5f82442279706..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_mul_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/binopLit8.S" {"instr":"mul a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips/op_mul_long.S b/runtime/interpreter/mterp/mips/op_mul_long.S deleted file mode 100644 index 74b049a0283bda895a55ce50d3507beabbc6f98a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_mul_long.S +++ /dev/null @@ -1,42 +0,0 @@ - /* - * Signed 64-bit integer multiply. - * a1 a0 - * x a3 a2 - * ------------- - * a2a1 a2a0 - * a3a0 - * a3a1 (<= unused) - * --------------- - * v1 v0 - */ - /* mul-long vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - and t0, a0, 255 # a2 <- BB - srl t1, a0, 8 # a3 <- CC - EAS2(t0, rFP, t0) # t0 <- &fp[BB] - LOAD64(a0, a1, t0) # a0/a1 <- vBB/vBB+1 - - EAS2(t1, rFP, t1) # t0 <- &fp[CC] - LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 - - mul v1, a3, a0 # v1= a3a0 -#ifdef MIPS32REVGE6 - mulu v0, a2, a0 # v0= a2a0 - muhu t1, a2, a0 -#else - multu a2, a0 - mfhi t1 - mflo v0 # v0= a2a0 -#endif - mul t0, a2, a1 # t0= a2a1 - addu v1, v1, t1 # v1+= hi(a2a0) - addu v1, v1, t0 # v1= a3a0 + a2a1; - - GET_OPA(a0) # a0 <- AA - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - b .L${opcode}_finish -%break - -.L${opcode}_finish: - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(v0, v1, a0, t0) # vAA/vAA+1 <- v0(low)/v1(high) diff --git a/runtime/interpreter/mterp/mips/op_mul_long_2addr.S b/runtime/interpreter/mterp/mips/op_mul_long_2addr.S deleted file mode 100644 index 683b055e8495855b03f6b38f35817824d244bdbb..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_mul_long_2addr.S +++ /dev/null @@ -1,29 +0,0 @@ - /* - * See op_mul_long.S for more details - */ - /* mul-long/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - - EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] - LOAD64(a0, a1, t0) # vAA.low / high - - GET_OPB(t1) # t1 <- B - EAS2(t1, rFP, t1) # t1 <- &fp[B] - LOAD64(a2, a3, t1) # vBB.low / high - - mul v1, a3, a0 # v1= a3a0 -#ifdef MIPS32REVGE6 - mulu v0, a2, a0 # v0= a2a0 - muhu t1, a2, a0 -#else - multu a2, a0 - mfhi t1 - mflo v0 # v0= a2a0 - #endif - mul t2, a2, a1 # t2= a2a1 - addu v1, v1, t1 # v1= a3a0 + hi(a2a0) - addu v1, v1, t2 # v1= v1 + a2a1; - - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - GET_INST_OPCODE(t1) # extract opcode from rINST - SET_VREG64_GOTO(v0, v1, rOBJ, t1) # vA/vA+1 <- v0(low)/v1(high) diff --git a/runtime/interpreter/mterp/mips/op_neg_double.S b/runtime/interpreter/mterp/mips/op_neg_double.S deleted file mode 100644 index 89cc918b8048b87644276ed9cd4eb9345a6f90c9..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_neg_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/unopWide.S" {"instr":"addu a1, a1, 0x80000000"} diff --git a/runtime/interpreter/mterp/mips/op_neg_float.S b/runtime/interpreter/mterp/mips/op_neg_float.S deleted file mode 100644 index e702755f11284770e12a424fc3519d834da1bbc0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_neg_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/unop.S" {"instr":"addu a0, a0, 0x80000000"} diff --git a/runtime/interpreter/mterp/mips/op_neg_int.S b/runtime/interpreter/mterp/mips/op_neg_int.S deleted file mode 100644 index 44617314659e9a80be8b8b836b9cbb616ce56c31..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_neg_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/unop.S" {"instr":"negu a0, a0"} diff --git a/runtime/interpreter/mterp/mips/op_neg_long.S b/runtime/interpreter/mterp/mips/op_neg_long.S deleted file mode 100644 index 71e60f59be8b9fafd881901dd18d4c4fa1edbd75..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_neg_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/unopWide.S" {"result0":"v0", "result1":"v1", "preinstr":"negu v0, a0", "instr":"negu v1, a1; sltu a0, zero, v0; subu v1, v1, a0"} diff --git a/runtime/interpreter/mterp/mips/op_new_array.S b/runtime/interpreter/mterp/mips/op_new_array.S deleted file mode 100644 index 4a6512d7c5f3e9fdaefaf8020fa049532404c262..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_new_array.S +++ /dev/null @@ -1,18 +0,0 @@ - /* - * Allocate an array of objects, specified with the array class - * and a count. - * - * The verifier guarantees that this is an array class, so we don't - * check for it here. - */ - /* new-array vA, vB, class@CCCC */ - EXPORT_PC() - addu a0, rFP, OFF_FP_SHADOWFRAME - move a1, rPC - move a2, rINST - move a3, rSELF - JAL(MterpNewArray) - beqz v0, MterpPossibleException - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction diff --git a/runtime/interpreter/mterp/mips/op_new_instance.S b/runtime/interpreter/mterp/mips/op_new_instance.S deleted file mode 100644 index 3c9e83f9b81bc0dd54eb62a5699b03c707fd4326..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_new_instance.S +++ /dev/null @@ -1,13 +0,0 @@ - /* - * Create a new instance of a class. - */ - /* new-instance vAA, class@BBBB */ - EXPORT_PC() - addu a0, rFP, OFF_FP_SHADOWFRAME - move a1, rSELF - move a2, rINST - JAL(MterpNewInstance) - beqz v0, MterpPossibleException - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction diff --git a/runtime/interpreter/mterp/mips/op_nop.S b/runtime/interpreter/mterp/mips/op_nop.S deleted file mode 100644 index 3565631e03bc2b728515bfbe3cc974bc967d42e3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_nop.S +++ /dev/null @@ -1,3 +0,0 @@ - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction diff --git a/runtime/interpreter/mterp/mips/op_not_int.S b/runtime/interpreter/mterp/mips/op_not_int.S deleted file mode 100644 index 55d8cc11d175d2087f989d11c1bcaaa815634e1e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_not_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/unop.S" {"instr":"not a0, a0"} diff --git a/runtime/interpreter/mterp/mips/op_not_long.S b/runtime/interpreter/mterp/mips/op_not_long.S deleted file mode 100644 index 9e7c95bcea19c08fa952750bf106e53954df1770..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_not_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/unopWide.S" {"preinstr":"not a0, a0", "instr":"not a1, a1"} diff --git a/runtime/interpreter/mterp/mips/op_or_int.S b/runtime/interpreter/mterp/mips/op_or_int.S deleted file mode 100644 index c7ce760a73cd134850c3a3ade4d5bc216c94a086..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_or_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/binop.S" {"instr":"or a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips/op_or_int_2addr.S b/runtime/interpreter/mterp/mips/op_or_int_2addr.S deleted file mode 100644 index 192d611e8d826ce4565b2b9852553be8b21980ec..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_or_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/binop2addr.S" {"instr":"or a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips/op_or_int_lit16.S b/runtime/interpreter/mterp/mips/op_or_int_lit16.S deleted file mode 100644 index f4ef75fff8713f44c9a0d751338e041653ea83f6..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_or_int_lit16.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/binopLit16.S" {"instr":"or a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips/op_or_int_lit8.S b/runtime/interpreter/mterp/mips/op_or_int_lit8.S deleted file mode 100644 index f6212e217d6d3b69e60b6eafb5445a0128666bb8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_or_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/binopLit8.S" {"instr":"or a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips/op_or_long.S b/runtime/interpreter/mterp/mips/op_or_long.S deleted file mode 100644 index 0f94486e421770fb73c0790a239a269671ba09cb..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_or_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/binopWide.S" {"preinstr":"or a0, a0, a2", "instr":"or a1, a1, a3"} diff --git a/runtime/interpreter/mterp/mips/op_or_long_2addr.S b/runtime/interpreter/mterp/mips/op_or_long_2addr.S deleted file mode 100644 index 43c3d05d41667add386de2ffe2d82420cc4fac89..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_or_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/binopWide2addr.S" {"preinstr":"or a0, a0, a2", "instr":"or a1, a1, a3"} diff --git a/runtime/interpreter/mterp/mips/op_packed_switch.S b/runtime/interpreter/mterp/mips/op_packed_switch.S deleted file mode 100644 index 0a1ff989c1fdb35eeada087deefb6f77b0981b77..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_packed_switch.S +++ /dev/null @@ -1,20 +0,0 @@ -%default { "func":"MterpDoPackedSwitch" } - /* - * Handle a packed-switch or sparse-switch instruction. In both cases - * we decode it and hand it off to a helper function. - * - * We don't really expect backward branches in a switch statement, but - * they're perfectly legal, so we check for them here. - * - * for: packed-switch, sparse-switch - */ - /* op vAA, +BBBB */ - FETCH(a0, 1) # a0 <- bbbb (lo) - FETCH(a1, 2) # a1 <- BBBB (hi) - GET_OPA(a3) # a3 <- AA - INSERT_HIGH_HALF(a0, a1) # a0 <- BBBBbbbb - GET_VREG(a1, a3) # a1 <- vAA - EAS1(a0, rPC, a0) # a0 <- PC + BBBBbbbb*2 - JAL($func) # a0 <- code-unit branch offset - move rINST, v0 - b MterpCommonTakenBranchNoFlags diff --git a/runtime/interpreter/mterp/mips/op_rem_double.S b/runtime/interpreter/mterp/mips/op_rem_double.S deleted file mode 100644 index a6890a8029ee8430d5bbc2825c625d31af9d61a7..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_rem_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/fbinopWide.S" {"instr":"JAL(fmod)"} diff --git a/runtime/interpreter/mterp/mips/op_rem_double_2addr.S b/runtime/interpreter/mterp/mips/op_rem_double_2addr.S deleted file mode 100644 index a24e1604fac707642b924536ce566101ce10c0c7..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_rem_double_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/fbinopWide2addr.S" {"instr":"JAL(fmod)"} diff --git a/runtime/interpreter/mterp/mips/op_rem_float.S b/runtime/interpreter/mterp/mips/op_rem_float.S deleted file mode 100644 index ac3d50ce75f02afa20a08833289543345cf505d0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_rem_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/fbinop.S" {"instr":"JAL(fmodf)"} diff --git a/runtime/interpreter/mterp/mips/op_rem_float_2addr.S b/runtime/interpreter/mterp/mips/op_rem_float_2addr.S deleted file mode 100644 index 7f0a9320c82fda042d1ba808f5f74bf7e6e4c471..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_rem_float_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/fbinop2addr.S" {"instr":"JAL(fmodf)"} diff --git a/runtime/interpreter/mterp/mips/op_rem_int.S b/runtime/interpreter/mterp/mips/op_rem_int.S deleted file mode 100644 index c2a334a8791a811201c12d5c9ec4647129b52cc6..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_rem_int.S +++ /dev/null @@ -1,5 +0,0 @@ -#ifdef MIPS32REVGE6 -%include "mips/binop.S" {"instr":"mod a0, a0, a1", "chkzero":"1"} -#else -%include "mips/binop.S" {"preinstr":"div zero, a0, a1", "instr":"mfhi a0", "chkzero":"1"} -#endif diff --git a/runtime/interpreter/mterp/mips/op_rem_int_2addr.S b/runtime/interpreter/mterp/mips/op_rem_int_2addr.S deleted file mode 100644 index 46c353fa83f574d79f7a9ff732b6ff104c7397ca..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_rem_int_2addr.S +++ /dev/null @@ -1,5 +0,0 @@ -#ifdef MIPS32REVGE6 -%include "mips/binop2addr.S" {"instr":"mod a0, a0, a1", "chkzero":"1"} -#else -%include "mips/binop2addr.S" {"preinstr":"div zero, a0, a1", "instr":"mfhi a0", "chkzero":"1"} -#endif diff --git a/runtime/interpreter/mterp/mips/op_rem_int_lit16.S b/runtime/interpreter/mterp/mips/op_rem_int_lit16.S deleted file mode 100644 index 2894ad37a29c14fcfe63651a37dcc68b74d1d998..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_rem_int_lit16.S +++ /dev/null @@ -1,5 +0,0 @@ -#ifdef MIPS32REVGE6 -%include "mips/binopLit16.S" {"instr":"mod a0, a0, a1", "chkzero":"1"} -#else -%include "mips/binopLit16.S" {"preinstr":"div zero, a0, a1", "instr":"mfhi a0", "chkzero":"1"} -#endif diff --git a/runtime/interpreter/mterp/mips/op_rem_int_lit8.S b/runtime/interpreter/mterp/mips/op_rem_int_lit8.S deleted file mode 100644 index 582248ba8fe4e70ec50afe53f02ce259f0c7c54f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_rem_int_lit8.S +++ /dev/null @@ -1,5 +0,0 @@ -#ifdef MIPS32REVGE6 -%include "mips/binopLit8.S" {"instr":"mod a0, a0, a1", "chkzero":"1"} -#else -%include "mips/binopLit8.S" {"preinstr":"div zero, a0, a1", "instr":"mfhi a0", "chkzero":"1"} -#endif diff --git a/runtime/interpreter/mterp/mips/op_rem_long.S b/runtime/interpreter/mterp/mips/op_rem_long.S deleted file mode 100644 index e3eb19bed4a5ac0ef5a2749050575a5eac9fe030..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_rem_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/binopWide.S" { "result0":"v0", "result1":"v1", "instr":"JAL(__moddi3)", "chkzero":"1"} diff --git a/runtime/interpreter/mterp/mips/op_rem_long_2addr.S b/runtime/interpreter/mterp/mips/op_rem_long_2addr.S deleted file mode 100644 index 8fc9fdb15f5a1d5983f563719061024c455b470c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_rem_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/binopWide2addr.S" { "result0":"v0", "result1":"v1", "instr":"JAL(__moddi3)", "chkzero":"1"} diff --git a/runtime/interpreter/mterp/mips/op_return.S b/runtime/interpreter/mterp/mips/op_return.S deleted file mode 100644 index 44b93958d2fd3ca8224b2af9bd1c561874894ab0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_return.S +++ /dev/null @@ -1,18 +0,0 @@ - /* - * Return a 32-bit value. - * - * for: return, return-object - */ - /* op vAA */ - .extern MterpThreadFenceForConstructor - JAL(MterpThreadFenceForConstructor) - lw ra, THREAD_FLAGS_OFFSET(rSELF) - move a0, rSELF - and ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - beqz ra, 1f - JAL(MterpSuspendCheck) # (self) -1: - GET_OPA(a2) # a2 <- AA - GET_VREG(v0, a2) # v0 <- vAA - move v1, zero - b MterpReturn diff --git a/runtime/interpreter/mterp/mips/op_return_object.S b/runtime/interpreter/mterp/mips/op_return_object.S deleted file mode 100644 index 7350e008c552a98cf1a7e5aa167cba4309e842cf..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_return_object.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_return.S" diff --git a/runtime/interpreter/mterp/mips/op_return_void.S b/runtime/interpreter/mterp/mips/op_return_void.S deleted file mode 100644 index 1f616ea198b7cb6828052251f92e53e1f0943db5..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_return_void.S +++ /dev/null @@ -1,11 +0,0 @@ - .extern MterpThreadFenceForConstructor - JAL(MterpThreadFenceForConstructor) - lw ra, THREAD_FLAGS_OFFSET(rSELF) - move a0, rSELF - and ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - beqz ra, 1f - JAL(MterpSuspendCheck) # (self) -1: - move v0, zero - move v1, zero - b MterpReturn diff --git a/runtime/interpreter/mterp/mips/op_return_void_no_barrier.S b/runtime/interpreter/mterp/mips/op_return_void_no_barrier.S deleted file mode 100644 index e670c2867ff4a7a8116c6a3f5949a9f2064a0a19..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_return_void_no_barrier.S +++ /dev/null @@ -1,9 +0,0 @@ - lw ra, THREAD_FLAGS_OFFSET(rSELF) - move a0, rSELF - and ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - beqz ra, 1f - JAL(MterpSuspendCheck) # (self) -1: - move v0, zero - move v1, zero - b MterpReturn diff --git a/runtime/interpreter/mterp/mips/op_return_wide.S b/runtime/interpreter/mterp/mips/op_return_wide.S deleted file mode 100644 index f0f679dbde11c50677269772ace410e2c27ea2c9..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_return_wide.S +++ /dev/null @@ -1,16 +0,0 @@ - /* - * Return a 64-bit value. - */ - /* return-wide vAA */ - .extern MterpThreadFenceForConstructor - JAL(MterpThreadFenceForConstructor) - lw ra, THREAD_FLAGS_OFFSET(rSELF) - move a0, rSELF - and ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - beqz ra, 1f - JAL(MterpSuspendCheck) # (self) -1: - GET_OPA(a2) # a2 <- AA - EAS2(a2, rFP, a2) # a2 <- &fp[AA] - LOAD64(v0, v1, a2) # v0/v1 <- vAA/vAA+1 - b MterpReturn diff --git a/runtime/interpreter/mterp/mips/op_rsub_int.S b/runtime/interpreter/mterp/mips/op_rsub_int.S deleted file mode 100644 index f7e61bb2e91b5841b28b3bfd87541ebab9221975..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_rsub_int.S +++ /dev/null @@ -1,2 +0,0 @@ -/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ -%include "mips/binopLit16.S" {"instr":"subu a0, a1, a0"} diff --git a/runtime/interpreter/mterp/mips/op_rsub_int_lit8.S b/runtime/interpreter/mterp/mips/op_rsub_int_lit8.S deleted file mode 100644 index 3968a5ef8ca2e2ac26c20c2a6df8bb6d0a0e11a2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_rsub_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/binopLit8.S" {"instr":"subu a0, a1, a0"} diff --git a/runtime/interpreter/mterp/mips/op_sget.S b/runtime/interpreter/mterp/mips/op_sget.S deleted file mode 100644 index 92d667335b9d361a5590f547b71d760a194195a3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_sget.S +++ /dev/null @@ -1,2 +0,0 @@ -%default { "is_object":"0", "helper":"MterpSGetU32" } -%include "mips/field.S" { } diff --git a/runtime/interpreter/mterp/mips/op_sget_boolean.S b/runtime/interpreter/mterp/mips/op_sget_boolean.S deleted file mode 100644 index 7a7012e81f43bee8e36a8303aec3f2aa3691a9fc..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_sget_boolean.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_sget.S" {"helper":"MterpSGetU8"} diff --git a/runtime/interpreter/mterp/mips/op_sget_byte.S b/runtime/interpreter/mterp/mips/op_sget_byte.S deleted file mode 100644 index a2f1dbf606fd79c8dd7a90f83623834d18f23add..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_sget_byte.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_sget.S" {"helper":"MterpSGetI8"} diff --git a/runtime/interpreter/mterp/mips/op_sget_char.S b/runtime/interpreter/mterp/mips/op_sget_char.S deleted file mode 100644 index 07d40416a3dd06852725dcc13a1d42769ed17eea..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_sget_char.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_sget.S" {"helper":"MterpSGetU16"} diff --git a/runtime/interpreter/mterp/mips/op_sget_object.S b/runtime/interpreter/mterp/mips/op_sget_object.S deleted file mode 100644 index 0a3c9eef886a556058d534a3d60fc17050dd6531..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_sget_object.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_sget.S" {"is_object":"1", "helper":"MterpSGetObj"} diff --git a/runtime/interpreter/mterp/mips/op_sget_short.S b/runtime/interpreter/mterp/mips/op_sget_short.S deleted file mode 100644 index 29604430f2369f2212c2dd112b8609c8358c6d63..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_sget_short.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_sget.S" {"helper":"MterpSGetI16"} diff --git a/runtime/interpreter/mterp/mips/op_sget_wide.S b/runtime/interpreter/mterp/mips/op_sget_wide.S deleted file mode 100644 index be4ae027cb2fefff4cfe796ee0d2a06ce3bfdf1b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_sget_wide.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_sget.S" {"helper":"MterpSGetU64"} diff --git a/runtime/interpreter/mterp/mips/op_shl_int.S b/runtime/interpreter/mterp/mips/op_shl_int.S deleted file mode 100644 index 15cbe94113794a170266f9cb638707e46ea570f0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_shl_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/binop.S" {"instr":"sll a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips/op_shl_int_2addr.S b/runtime/interpreter/mterp/mips/op_shl_int_2addr.S deleted file mode 100644 index ef9bd655ab71fc20df673187430685ca03d49b1f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_shl_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/binop2addr.S" {"instr":"sll a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips/op_shl_int_lit8.S b/runtime/interpreter/mterp/mips/op_shl_int_lit8.S deleted file mode 100644 index d2afb53e14e64359f760501779928554deba2be1..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_shl_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/binopLit8.S" {"instr":"sll a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips/op_shl_long.S b/runtime/interpreter/mterp/mips/op_shl_long.S deleted file mode 100644 index cc0811295b777e6a76b4e518295217a8dfac1fcb..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_shl_long.S +++ /dev/null @@ -1,31 +0,0 @@ - /* - * Long integer shift. This is different from the generic 32/64-bit - * binary operations because vAA/vBB are 64-bit but vCC (the shift - * distance) is 32-bit. Also, Dalvik requires us to mask off the low - * 6 bits of the shift distance. - */ - /* shl-long vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(t2) # t2 <- AA - and a3, a0, 255 # a3 <- BB - srl a0, a0, 8 # a0 <- CC - EAS2(a3, rFP, a3) # a3 <- &fp[BB] - GET_VREG(a2, a0) # a2 <- vCC - LOAD64(a0, a1, a3) # a0/a1 <- vBB/vBB+1 - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - - andi v1, a2, 0x20 # shift< shift & 0x20 - sll v0, a0, a2 # rlo<- alo << (shift&31) - bnez v1, .L${opcode}_finish - not v1, a2 # rhi<- 31-shift (shift is 5b) - srl a0, 1 - srl a0, v1 # alo<- alo >> (32-(shift&31)) - sll v1, a1, a2 # rhi<- ahi << (shift&31) - or v1, a0 # rhi<- rhi | alo - SET_VREG64_GOTO(v0, v1, t2, t0) # vAA/vAA+1 <- v0/v1 -%break - -.L${opcode}_finish: - SET_VREG64_GOTO(zero, v0, t2, t0) # vAA/vAA+1 <- rlo/rhi diff --git a/runtime/interpreter/mterp/mips/op_shl_long_2addr.S b/runtime/interpreter/mterp/mips/op_shl_long_2addr.S deleted file mode 100644 index 93c578353ee74091a8dda75ac7e00c72a90ca530..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_shl_long_2addr.S +++ /dev/null @@ -1,27 +0,0 @@ - /* - * Long integer shift, 2addr version. vA is 64-bit value/result, vB is - * 32-bit shift distance. - */ - /* shl-long/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a2, a3) # a2 <- vB - EAS2(t2, rFP, rOBJ) # t2 <- &fp[A] - LOAD64(a0, a1, t2) # a0/a1 <- vA/vA+1 - - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - - andi v1, a2, 0x20 # shift< shift & 0x20 - sll v0, a0, a2 # rlo<- alo << (shift&31) - bnez v1, .L${opcode}_finish - not v1, a2 # rhi<- 31-shift (shift is 5b) - srl a0, 1 - srl a0, v1 # alo<- alo >> (32-(shift&31)) - sll v1, a1, a2 # rhi<- ahi << (shift&31) - or v1, a0 # rhi<- rhi | alo - SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vA/vA+1 <- v0/v1 -%break - -.L${opcode}_finish: - SET_VREG64_GOTO(zero, v0, rOBJ, t0) # vA/vA+1 <- rlo/rhi diff --git a/runtime/interpreter/mterp/mips/op_shr_int.S b/runtime/interpreter/mterp/mips/op_shr_int.S deleted file mode 100644 index 611083999946fa2ab3a9d28171855393ea0e6232..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_shr_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/binop.S" {"instr":"sra a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips/op_shr_int_2addr.S b/runtime/interpreter/mterp/mips/op_shr_int_2addr.S deleted file mode 100644 index e00ff5b2e6387c829286837c19d5e753a8eade97..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_shr_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/binop2addr.S" {"instr":"sra a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips/op_shr_int_lit8.S b/runtime/interpreter/mterp/mips/op_shr_int_lit8.S deleted file mode 100644 index d058f5862cfbbb9419b1a31925b03a8631c68507..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_shr_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/binopLit8.S" {"instr":"sra a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips/op_shr_long.S b/runtime/interpreter/mterp/mips/op_shr_long.S deleted file mode 100644 index ea032fe9a072f4b7047cb9665173e8eaaad1b049..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_shr_long.S +++ /dev/null @@ -1,31 +0,0 @@ - /* - * Long integer shift. This is different from the generic 32/64-bit - * binary operations because vAA/vBB are 64-bit but vCC (the shift - * distance) is 32-bit. Also, Dalvik requires us to mask off the low - * 6 bits of the shift distance. - */ - /* shr-long vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(t3) # t3 <- AA - and a3, a0, 255 # a3 <- BB - srl a0, a0, 8 # a0 <- CC - EAS2(a3, rFP, a3) # a3 <- &fp[BB] - GET_VREG(a2, a0) # a2 <- vCC - LOAD64(a0, a1, a3) # a0/a1 <- vBB/vBB+1 - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - - andi v0, a2, 0x20 # shift & 0x20 - sra v1, a1, a2 # rhi<- ahi >> (shift&31) - bnez v0, .L${opcode}_finish - srl v0, a0, a2 # rlo<- alo >> (shift&31) - not a0, a2 # alo<- 31-shift (shift is 5b) - sll a1, 1 - sll a1, a0 # ahi<- ahi << (32-(shift&31)) - or v0, a1 # rlo<- rlo | ahi - SET_VREG64_GOTO(v0, v1, t3, t0) # vAA/VAA+1 <- v0/v1 -%break - -.L${opcode}_finish: - sra a3, a1, 31 # a3<- sign(ah) - SET_VREG64_GOTO(v1, a3, t3, t0) # vAA/VAA+1 <- rlo/rhi diff --git a/runtime/interpreter/mterp/mips/op_shr_long_2addr.S b/runtime/interpreter/mterp/mips/op_shr_long_2addr.S deleted file mode 100644 index c805ea424fb254f65a231a07f5682411bcc8222b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_shr_long_2addr.S +++ /dev/null @@ -1,27 +0,0 @@ - /* - * Long integer shift, 2addr version. vA is 64-bit value/result, vB is - * 32-bit shift distance. - */ - /* shr-long/2addr vA, vB */ - GET_OPA4(t2) # t2 <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a2, a3) # a2 <- vB - EAS2(t0, rFP, t2) # t0 <- &fp[A] - LOAD64(a0, a1, t0) # a0/a1 <- vA/vA+1 - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - - andi v0, a2, 0x20 # shift & 0x20 - sra v1, a1, a2 # rhi<- ahi >> (shift&31) - bnez v0, .L${opcode}_finish - srl v0, a0, a2 # rlo<- alo >> (shift&31) - not a0, a2 # alo<- 31-shift (shift is 5b) - sll a1, 1 - sll a1, a0 # ahi<- ahi << (32-(shift&31)) - or v0, a1 # rlo<- rlo | ahi - SET_VREG64_GOTO(v0, v1, t2, t0) # vA/vA+1 <- v0/v1 -%break - -.L${opcode}_finish: - sra a3, a1, 31 # a3<- sign(ah) - SET_VREG64_GOTO(v1, a3, t2, t0) # vA/vA+1 <- rlo/rhi diff --git a/runtime/interpreter/mterp/mips/op_sparse_switch.S b/runtime/interpreter/mterp/mips/op_sparse_switch.S deleted file mode 100644 index 670f4648a8595df099bde21167e0bf68571885c4..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_sparse_switch.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_packed_switch.S" { "func":"MterpDoSparseSwitch" } diff --git a/runtime/interpreter/mterp/mips/op_sput.S b/runtime/interpreter/mterp/mips/op_sput.S deleted file mode 100644 index c858679762d85e9940901f7ce23b52ee3035d464..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_sput.S +++ /dev/null @@ -1,2 +0,0 @@ -%default { "is_object":"0", "helper":"MterpSPutU32"} -%include "mips/field.S" { } diff --git a/runtime/interpreter/mterp/mips/op_sput_boolean.S b/runtime/interpreter/mterp/mips/op_sput_boolean.S deleted file mode 100644 index 0137430acce9cde80365f99d48d649d9e11bf031..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_sput_boolean.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_sput.S" {"helper":"MterpSPutU8"} diff --git a/runtime/interpreter/mterp/mips/op_sput_byte.S b/runtime/interpreter/mterp/mips/op_sput_byte.S deleted file mode 100644 index 5ae4256a989f6aa64676cb853f37fc30aa21cc5f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_sput_byte.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_sput.S" {"helper":"MterpSPutI8"} diff --git a/runtime/interpreter/mterp/mips/op_sput_char.S b/runtime/interpreter/mterp/mips/op_sput_char.S deleted file mode 100644 index 83787a7753a44c2cb131204246baeea876a58a63..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_sput_char.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_sput.S" {"helper":"MterpSPutU16"} diff --git a/runtime/interpreter/mterp/mips/op_sput_object.S b/runtime/interpreter/mterp/mips/op_sput_object.S deleted file mode 100644 index 683b76789d084f9248f0362d7cd8a632cdd9211f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_sput_object.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_sput.S" {"is_object":"1", "helper":"MterpSPutObj"} diff --git a/runtime/interpreter/mterp/mips/op_sput_short.S b/runtime/interpreter/mterp/mips/op_sput_short.S deleted file mode 100644 index df99b4414d7f94c8ed6d6460b7f5631ee34def3b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_sput_short.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_sput.S" {"helper":"MterpSPutI16"} diff --git a/runtime/interpreter/mterp/mips/op_sput_wide.S b/runtime/interpreter/mterp/mips/op_sput_wide.S deleted file mode 100644 index 1d2ed196f30c58e4829c43a4cec4c72dc103d4de..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_sput_wide.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/op_sput.S" {"helper":"MterpSPutU64"} diff --git a/runtime/interpreter/mterp/mips/op_sub_double.S b/runtime/interpreter/mterp/mips/op_sub_double.S deleted file mode 100644 index 9473218e89324e45b4a6c77fce31ce3bed4483f0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_sub_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/fbinopWide.S" {"instr":"sub.d fv0, fa0, fa1"} diff --git a/runtime/interpreter/mterp/mips/op_sub_double_2addr.S b/runtime/interpreter/mterp/mips/op_sub_double_2addr.S deleted file mode 100644 index 7ce7c74330aa83cb4b0849108f43746e557e84a2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_sub_double_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/fbinopWide2addr.S" {"instr":"sub.d fv0, fa0, fa1"} diff --git a/runtime/interpreter/mterp/mips/op_sub_float.S b/runtime/interpreter/mterp/mips/op_sub_float.S deleted file mode 100644 index 04650d9125b24f5fae4ed6d1c7c1d56764795114..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_sub_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/fbinop.S" {"instr":"sub.s fv0, fa0, fa1"} diff --git a/runtime/interpreter/mterp/mips/op_sub_float_2addr.S b/runtime/interpreter/mterp/mips/op_sub_float_2addr.S deleted file mode 100644 index dfe935c8cfec5878c0fdf639585dffc47abeafa8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_sub_float_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/fbinop2addr.S" {"instr":"sub.s fv0, fa0, fa1"} diff --git a/runtime/interpreter/mterp/mips/op_sub_int.S b/runtime/interpreter/mterp/mips/op_sub_int.S deleted file mode 100644 index 43da1b617a853384abdc4122a88edc8f751de104..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_sub_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/binop.S" {"instr":"subu a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips/op_sub_int_2addr.S b/runtime/interpreter/mterp/mips/op_sub_int_2addr.S deleted file mode 100644 index cf34aa69dc4ae5c9980b3943774dd6ddfe693885..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_sub_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/binop2addr.S" {"instr":"subu a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips/op_sub_long.S b/runtime/interpreter/mterp/mips/op_sub_long.S deleted file mode 100644 index 0f58e8e891b41a14884d3721374cc5087b7dbe33..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_sub_long.S +++ /dev/null @@ -1,8 +0,0 @@ -/* - * For little endian the code sequence looks as follows: - * subu v0,a0,a2 - * subu v1,a1,a3 - * sltu a0,a0,v0 - * subu v1,v1,a0 - */ -%include "mips/binopWide.S" { "result0":"v0", "result1":"v1", "preinstr":"subu v0, a0, a2", "instr":"subu v1, a1, a3; sltu a0, a0, v0; subu v1, v1, a0" } diff --git a/runtime/interpreter/mterp/mips/op_sub_long_2addr.S b/runtime/interpreter/mterp/mips/op_sub_long_2addr.S deleted file mode 100644 index aa256c20f86951c95f11de8cec47e31c5c3cb774..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_sub_long_2addr.S +++ /dev/null @@ -1,4 +0,0 @@ -/* - * See op_sub_long.S for more details - */ -%include "mips/binopWide2addr.S" { "result0":"v0", "result1":"v1", "preinstr":"subu v0, a0, a2", "instr":"subu v1, a1, a3; sltu a0, a0, v0; subu v1, v1, a0" } diff --git a/runtime/interpreter/mterp/mips/op_throw.S b/runtime/interpreter/mterp/mips/op_throw.S deleted file mode 100644 index adc8b047cae0cc133f2cc5e362297e9d261e6a24..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_throw.S +++ /dev/null @@ -1,11 +0,0 @@ - /* - * Throw an exception object in the current thread. - */ - /* throw vAA */ - EXPORT_PC() # exception handler can throw - GET_OPA(a2) # a2 <- AA - GET_VREG(a1, a2) # a1 <- vAA (exception object) - # null object? - beqz a1, common_errNullObject # yes, throw an NPE instead - sw a1, THREAD_EXCEPTION_OFFSET(rSELF) # thread->exception <- obj - b MterpException diff --git a/runtime/interpreter/mterp/mips/op_unused_3e.S b/runtime/interpreter/mterp/mips/op_unused_3e.S deleted file mode 100644 index 99ef3cf3082af1624b138c623dd253b795e84c52..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_unused_3e.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/unused.S" diff --git a/runtime/interpreter/mterp/mips/op_unused_3f.S b/runtime/interpreter/mterp/mips/op_unused_3f.S deleted file mode 100644 index 99ef3cf3082af1624b138c623dd253b795e84c52..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_unused_3f.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/unused.S" diff --git a/runtime/interpreter/mterp/mips/op_unused_40.S b/runtime/interpreter/mterp/mips/op_unused_40.S deleted file mode 100644 index 99ef3cf3082af1624b138c623dd253b795e84c52..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_unused_40.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/unused.S" diff --git a/runtime/interpreter/mterp/mips/op_unused_41.S b/runtime/interpreter/mterp/mips/op_unused_41.S deleted file mode 100644 index 99ef3cf3082af1624b138c623dd253b795e84c52..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_unused_41.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/unused.S" diff --git a/runtime/interpreter/mterp/mips/op_unused_42.S b/runtime/interpreter/mterp/mips/op_unused_42.S deleted file mode 100644 index 99ef3cf3082af1624b138c623dd253b795e84c52..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_unused_42.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/unused.S" diff --git a/runtime/interpreter/mterp/mips/op_unused_43.S b/runtime/interpreter/mterp/mips/op_unused_43.S deleted file mode 100644 index 99ef3cf3082af1624b138c623dd253b795e84c52..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_unused_43.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/unused.S" diff --git a/runtime/interpreter/mterp/mips/op_unused_73.S b/runtime/interpreter/mterp/mips/op_unused_73.S deleted file mode 100644 index 99ef3cf3082af1624b138c623dd253b795e84c52..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_unused_73.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/unused.S" diff --git a/runtime/interpreter/mterp/mips/op_unused_79.S b/runtime/interpreter/mterp/mips/op_unused_79.S deleted file mode 100644 index 99ef3cf3082af1624b138c623dd253b795e84c52..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_unused_79.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/unused.S" diff --git a/runtime/interpreter/mterp/mips/op_unused_7a.S b/runtime/interpreter/mterp/mips/op_unused_7a.S deleted file mode 100644 index 99ef3cf3082af1624b138c623dd253b795e84c52..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_unused_7a.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/unused.S" diff --git a/runtime/interpreter/mterp/mips/op_unused_f3.S b/runtime/interpreter/mterp/mips/op_unused_f3.S deleted file mode 100644 index 99ef3cf3082af1624b138c623dd253b795e84c52..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_unused_f3.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/unused.S" diff --git a/runtime/interpreter/mterp/mips/op_unused_f4.S b/runtime/interpreter/mterp/mips/op_unused_f4.S deleted file mode 100644 index 99ef3cf3082af1624b138c623dd253b795e84c52..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_unused_f4.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/unused.S" diff --git a/runtime/interpreter/mterp/mips/op_unused_f5.S b/runtime/interpreter/mterp/mips/op_unused_f5.S deleted file mode 100644 index 99ef3cf3082af1624b138c623dd253b795e84c52..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_unused_f5.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/unused.S" diff --git a/runtime/interpreter/mterp/mips/op_unused_f6.S b/runtime/interpreter/mterp/mips/op_unused_f6.S deleted file mode 100644 index 99ef3cf3082af1624b138c623dd253b795e84c52..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_unused_f6.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/unused.S" diff --git a/runtime/interpreter/mterp/mips/op_unused_f7.S b/runtime/interpreter/mterp/mips/op_unused_f7.S deleted file mode 100644 index 99ef3cf3082af1624b138c623dd253b795e84c52..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_unused_f7.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/unused.S" diff --git a/runtime/interpreter/mterp/mips/op_unused_f8.S b/runtime/interpreter/mterp/mips/op_unused_f8.S deleted file mode 100644 index 99ef3cf3082af1624b138c623dd253b795e84c52..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_unused_f8.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/unused.S" diff --git a/runtime/interpreter/mterp/mips/op_unused_f9.S b/runtime/interpreter/mterp/mips/op_unused_f9.S deleted file mode 100644 index 99ef3cf3082af1624b138c623dd253b795e84c52..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_unused_f9.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/unused.S" diff --git a/runtime/interpreter/mterp/mips/op_unused_fc.S b/runtime/interpreter/mterp/mips/op_unused_fc.S deleted file mode 100644 index 99ef3cf3082af1624b138c623dd253b795e84c52..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_unused_fc.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/unused.S" diff --git a/runtime/interpreter/mterp/mips/op_unused_fd.S b/runtime/interpreter/mterp/mips/op_unused_fd.S deleted file mode 100644 index 99ef3cf3082af1624b138c623dd253b795e84c52..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_unused_fd.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/unused.S" diff --git a/runtime/interpreter/mterp/mips/op_ushr_int.S b/runtime/interpreter/mterp/mips/op_ushr_int.S deleted file mode 100644 index b95472b30e6fe396f4d68d25020562c3b2de6d34..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_ushr_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/binop.S" {"instr":"srl a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips/op_ushr_int_2addr.S b/runtime/interpreter/mterp/mips/op_ushr_int_2addr.S deleted file mode 100644 index fc1777810099328e64836a6aa56f06fa172f89e6..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_ushr_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/binop2addr.S" {"instr":"srl a0, a0, a1 "} diff --git a/runtime/interpreter/mterp/mips/op_ushr_int_lit8.S b/runtime/interpreter/mterp/mips/op_ushr_int_lit8.S deleted file mode 100644 index c82cfba15c37e67b5a6cba15f27976d7dd410242..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_ushr_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/binopLit8.S" {"instr":"srl a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips/op_ushr_long.S b/runtime/interpreter/mterp/mips/op_ushr_long.S deleted file mode 100644 index 2e227a94af674d9a9185aa9f4fa220fbc542000b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_ushr_long.S +++ /dev/null @@ -1,31 +0,0 @@ - /* - * Long integer shift. This is different from the generic 32/64-bit - * binary operations because vAA/vBB are 64-bit but vCC (the shift - * distance) is 32-bit. Also, Dalvik requires us to mask off the low - * 6 bits of the shift distance. - */ - /* ushr-long vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - and a3, a0, 255 # a3 <- BB - srl a0, a0, 8 # a0 <- CC - EAS2(a3, rFP, a3) # a3 <- &fp[BB] - GET_VREG(a2, a0) # a2 <- vCC - LOAD64(a0, a1, a3) # a0/a1 <- vBB/vBB+1 - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - - andi v0, a2, 0x20 # shift & 0x20 - srl v1, a1, a2 # rhi<- ahi >> (shift&31) - bnez v0, .L${opcode}_finish - srl v0, a0, a2 # rlo<- alo >> (shift&31) - not a0, a2 # alo<- 31-n (shift is 5b) - sll a1, 1 - sll a1, a0 # ahi<- ahi << (32-(shift&31)) - or v0, a1 # rlo<- rlo | ahi - SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vAA/vAA+1 <- v0/v1 -%break - -.L${opcode}_finish: - SET_VREG64_GOTO(v1, zero, rOBJ, t0) # vAA/vAA+1 <- rlo/rhi diff --git a/runtime/interpreter/mterp/mips/op_ushr_long_2addr.S b/runtime/interpreter/mterp/mips/op_ushr_long_2addr.S deleted file mode 100644 index 9e93f34cdb6f354ce8f907a9afb1fd1610fad3fb..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_ushr_long_2addr.S +++ /dev/null @@ -1,27 +0,0 @@ - /* - * Long integer shift, 2addr version. vA is 64-bit value/result, vB is - * 32-bit shift distance. - */ - /* ushr-long/2addr vA, vB */ - GET_OPA4(t3) # t3 <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a2, a3) # a2 <- vB - EAS2(t0, rFP, t3) # t0 <- &fp[A] - LOAD64(a0, a1, t0) # a0/a1 <- vA/vA+1 - - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - - andi v0, a2, 0x20 # shift & 0x20 - srl v1, a1, a2 # rhi<- ahi >> (shift&31) - bnez v0, .L${opcode}_finish - srl v0, a0, a2 # rlo<- alo >> (shift&31) - not a0, a2 # alo<- 31-n (shift is 5b) - sll a1, 1 - sll a1, a0 # ahi<- ahi << (32-(shift&31)) - or v0, a1 # rlo<- rlo | ahi - SET_VREG64_GOTO(v0, v1, t3, t0) # vA/vA+1 <- v0/v1 -%break - -.L${opcode}_finish: - SET_VREG64_GOTO(v1, zero, t3, t0) # vA/vA+1 <- rlo/rhi diff --git a/runtime/interpreter/mterp/mips/op_xor_int.S b/runtime/interpreter/mterp/mips/op_xor_int.S deleted file mode 100644 index 6c23f1f3786ac8a4f1770970b8519ab5b7353dc6..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_xor_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/binop.S" {"instr":"xor a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips/op_xor_int_2addr.S b/runtime/interpreter/mterp/mips/op_xor_int_2addr.S deleted file mode 100644 index 5ee1667f8d76feb88be87031cab86796da2b96fb..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_xor_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/binop2addr.S" {"instr":"xor a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips/op_xor_int_lit16.S b/runtime/interpreter/mterp/mips/op_xor_int_lit16.S deleted file mode 100644 index 2af37a611636261e6be2ed69c9edd5ec1507f487..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_xor_int_lit16.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/binopLit16.S" {"instr":"xor a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips/op_xor_int_lit8.S b/runtime/interpreter/mterp/mips/op_xor_int_lit8.S deleted file mode 100644 index 944ed692317d743d075b40b898666584a7553e39..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_xor_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/binopLit8.S" {"instr":"xor a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips/op_xor_long.S b/runtime/interpreter/mterp/mips/op_xor_long.S deleted file mode 100644 index 93f8f70a2143033ce6436c474e081bae7039ca1f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_xor_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/binopWide.S" {"preinstr":"xor a0, a0, a2", "instr":"xor a1, a1, a3"} diff --git a/runtime/interpreter/mterp/mips/op_xor_long_2addr.S b/runtime/interpreter/mterp/mips/op_xor_long_2addr.S deleted file mode 100644 index 49f3fa42f44166ff1fe16b29270ca3e8cd1e300d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/op_xor_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips/binopWide2addr.S" {"preinstr":"xor a0, a0, a2", "instr":"xor a1, a1, a3"} diff --git a/runtime/interpreter/mterp/mips/other.S b/runtime/interpreter/mterp/mips/other.S new file mode 100644 index 0000000000000000000000000000000000000000..500232984b8460479d8f25a512465cf8572f62ce --- /dev/null +++ b/runtime/interpreter/mterp/mips/other.S @@ -0,0 +1,345 @@ +%def const(helper="UndefinedConstHandler"): + /* const/class vAA, type@BBBB */ + /* const/method-handle vAA, method_handle@BBBB */ + /* const/method-type vAA, proto@BBBB */ + /* const/string vAA, string@@BBBB */ + .extern $helper + EXPORT_PC() + FETCH(a0, 1) # a0 <- BBBB + GET_OPA(a1) # a1 <- AA + addu a2, rFP, OFF_FP_SHADOWFRAME # a2 <- shadow frame + move a3, rSELF + JAL($helper) # v0 <- Mterp(index, tgt_reg, shadow_frame, self) + PREFETCH_INST(2) # load rINST + bnez v0, MterpPossibleException + ADVANCE(2) # advance rPC + GET_INST_OPCODE(t0) # extract opcode from rINST + GOTO_OPCODE(t0) # jump to next instruction + +%def unused(): +/* + * Bail to reference interpreter to throw. + */ + b MterpFallback + +%def op_const(): + /* const vAA, +BBBBbbbb */ + GET_OPA(a3) # a3 <- AA + FETCH(a0, 1) # a0 <- bbbb (low) + FETCH(a1, 2) # a1 <- BBBB (high) + FETCH_ADVANCE_INST(3) # advance rPC, load rINST + INSERT_HIGH_HALF(a0, a1) # a0 <- BBBBbbbb + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG_GOTO(a0, a3, t0) # vAA <- a0 + +%def op_const_16(): + /* const/16 vAA, +BBBB */ + FETCH_S(a0, 1) # a0 <- ssssBBBB (sign-extended) + GET_OPA(a3) # a3 <- AA + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG_GOTO(a0, a3, t0) # vAA <- a0 + +%def op_const_4(): + /* const/4 vA, +B */ + sll a1, rINST, 16 # a1 <- Bxxx0000 + GET_OPA(a0) # a0 <- A+ + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + sra a1, a1, 28 # a1 <- sssssssB (sign-extended) + and a0, a0, 15 + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG_GOTO(a1, a0, t0) # fp[A] <- a1 + +%def op_const_class(): +% const(helper="MterpConstClass") + +%def op_const_high16(): + /* const/high16 vAA, +BBBB0000 */ + FETCH(a0, 1) # a0 <- 0000BBBB (zero-extended) + GET_OPA(a3) # a3 <- AA + sll a0, a0, 16 # a0 <- BBBB0000 + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG_GOTO(a0, a3, t0) # vAA <- a0 + +%def op_const_method_handle(): +% const(helper="MterpConstMethodHandle") + +%def op_const_method_type(): +% const(helper="MterpConstMethodType") + +%def op_const_string(): +% const(helper="MterpConstString") + +%def op_const_string_jumbo(): + /* const/string vAA, string@BBBBBBBB */ + EXPORT_PC() + FETCH(a0, 1) # a0 <- bbbb (low) + FETCH(a2, 2) # a2 <- BBBB (high) + GET_OPA(a1) # a1 <- AA + INSERT_HIGH_HALF(a0, a2) # a0 <- BBBBbbbb + addu a2, rFP, OFF_FP_SHADOWFRAME # a2 <- shadow frame + move a3, rSELF + JAL(MterpConstString) # v0 <- Mterp(index, tgt_reg, shadow_frame, self) + PREFETCH_INST(3) # load rINST + bnez v0, MterpPossibleException + ADVANCE(3) # advance rPC + GET_INST_OPCODE(t0) # extract opcode from rINST + GOTO_OPCODE(t0) # jump to next instruction + +%def op_const_wide(): + /* const-wide vAA, +HHHHhhhhBBBBbbbb */ + FETCH(a0, 1) # a0 <- bbbb (low) + FETCH(a1, 2) # a1 <- BBBB (low middle) + FETCH(a2, 3) # a2 <- hhhh (high middle) + INSERT_HIGH_HALF(a0, a1) # a0 <- BBBBbbbb (low word) + FETCH(a3, 4) # a3 <- HHHH (high) + GET_OPA(t1) # t1 <- AA + INSERT_HIGH_HALF(a2, a3) # a2 <- HHHHhhhh (high word) + FETCH_ADVANCE_INST(5) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG64_GOTO(a0, a2, t1, t0) # vAA/vAA+1 <- a0/a2 + +%def op_const_wide_16(): + /* const-wide/16 vAA, +BBBB */ + FETCH_S(a0, 1) # a0 <- ssssBBBB (sign-extended) + GET_OPA(a3) # a3 <- AA + sra a1, a0, 31 # a1 <- ssssssss + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG64_GOTO(a0, a1, a3, t0) # vAA/vAA+1 <- a0/a1 + +%def op_const_wide_32(): + /* const-wide/32 vAA, +BBBBbbbb */ + FETCH(a0, 1) # a0 <- 0000bbbb (low) + GET_OPA(a3) # a3 <- AA + FETCH_S(a2, 2) # a2 <- ssssBBBB (high) + FETCH_ADVANCE_INST(3) # advance rPC, load rINST + INSERT_HIGH_HALF(a0, a2) # a0 <- BBBBbbbb + sra a1, a0, 31 # a1 <- ssssssss + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG64_GOTO(a0, a1, a3, t0) # vAA/vAA+1 <- a0/a1 + +%def op_const_wide_high16(): + /* const-wide/high16 vAA, +BBBB000000000000 */ + FETCH(a1, 1) # a1 <- 0000BBBB (zero-extended) + GET_OPA(a3) # a3 <- AA + li a0, 0 # a0 <- 00000000 + sll a1, 16 # a1 <- BBBB0000 + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG64_GOTO(a0, a1, a3, t0) # vAA/vAA+1 <- a0/a1 + +%def op_monitor_enter(): + /* + * Synchronize on an object. + */ + /* monitor-enter vAA */ + EXPORT_PC() + GET_OPA(a2) # a2 <- AA + GET_VREG(a0, a2) # a0 <- vAA (object) + move a1, rSELF # a1 <- self + JAL(artLockObjectFromCode) # v0 <- artLockObject(obj, self) + bnez v0, MterpException + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + GOTO_OPCODE(t0) # jump to next instruction + +%def op_monitor_exit(): + /* + * Unlock an object. + * + * Exceptions that occur when unlocking a monitor need to appear as + * if they happened at the following instruction. See the Dalvik + * instruction spec. + */ + /* monitor-exit vAA */ + EXPORT_PC() + GET_OPA(a2) # a2 <- AA + GET_VREG(a0, a2) # a0 <- vAA (object) + move a1, rSELF # a1 <- self + JAL(artUnlockObjectFromCode) # v0 <- artUnlockObject(obj, self) + bnez v0, MterpException + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + GOTO_OPCODE(t0) # jump to next instruction + +%def op_move(is_object="0"): + /* for move, move-object, long-to-int */ + /* op vA, vB */ + GET_OPB(a1) # a1 <- B from 15:12 + GET_OPA4(a0) # a0 <- A from 11:8 + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + GET_VREG(a2, a1) # a2 <- fp[B] + GET_INST_OPCODE(t0) # t0 <- opcode from rINST + .if $is_object + SET_VREG_OBJECT_GOTO(a2, a0, t0) # fp[A] <- a2 + .else + SET_VREG_GOTO(a2, a0, t0) # fp[A] <- a2 + .endif + +%def op_move_16(is_object="0"): + /* for: move/16, move-object/16 */ + /* op vAAAA, vBBBB */ + FETCH(a1, 2) # a1 <- BBBB + FETCH(a0, 1) # a0 <- AAAA + FETCH_ADVANCE_INST(3) # advance rPC, load rINST + GET_VREG(a2, a1) # a2 <- fp[BBBB] + GET_INST_OPCODE(t0) # extract opcode from rINST + .if $is_object + SET_VREG_OBJECT_GOTO(a2, a0, t0) # fp[AAAA] <- a2 + .else + SET_VREG_GOTO(a2, a0, t0) # fp[AAAA] <- a2 + .endif + +%def op_move_exception(): + /* move-exception vAA */ + GET_OPA(a2) # a2 <- AA + lw a3, THREAD_EXCEPTION_OFFSET(rSELF) # get exception obj + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + GET_OPCODE_TARGET(t0) + SET_VREG_OBJECT(a3, a2) # fp[AA] <- exception obj + sw zero, THREAD_EXCEPTION_OFFSET(rSELF) # clear exception + JR(t0) # jump to next instruction + +%def op_move_from16(is_object="0"): + /* for: move/from16, move-object/from16 */ + /* op vAA, vBBBB */ + FETCH(a1, 1) # a1 <- BBBB + GET_OPA(a0) # a0 <- AA + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + GET_VREG(a2, a1) # a2 <- fp[BBBB] + GET_INST_OPCODE(t0) # extract opcode from rINST + .if $is_object + SET_VREG_OBJECT_GOTO(a2, a0, t0) # fp[AA] <- a2 + .else + SET_VREG_GOTO(a2, a0, t0) # fp[AA] <- a2 + .endif + +%def op_move_object(): +% op_move(is_object="1") + +%def op_move_object_16(): +% op_move_16(is_object="1") + +%def op_move_object_from16(): +% op_move_from16(is_object="1") + +%def op_move_result(is_object="0"): + /* for: move-result, move-result-object */ + /* op vAA */ + GET_OPA(a2) # a2 <- AA + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + lw a0, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType + lw a0, 0(a0) # a0 <- result.i + GET_INST_OPCODE(t0) # extract opcode from rINST + .if $is_object + SET_VREG_OBJECT_GOTO(a0, a2, t0) # fp[AA] <- a0 + .else + SET_VREG_GOTO(a0, a2, t0) # fp[AA] <- a0 + .endif + +%def op_move_result_object(): +% op_move_result(is_object="1") + +%def op_move_result_wide(): + /* move-result-wide vAA */ + GET_OPA(a2) # a2 <- AA + lw a3, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType + LOAD64(a0, a1, a3) # a0/a1 <- retval.j + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG64_GOTO(a0, a1, a2, t0) # fp[AA] <- a0/a1 + +%def op_move_wide(): + /* move-wide vA, vB */ + /* NOTE: regs can overlap, e.g. "move v6, v7" or "move v7, v6" */ + GET_OPA4(a2) # a2 <- A(+) + GET_OPB(a3) # a3 <- B + EAS2(a3, rFP, a3) # a3 <- &fp[B] + LOAD64(a0, a1, a3) # a0/a1 <- fp[B] + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG64_GOTO(a0, a1, a2, t0) # fp[A] <- a0/a1 + +%def op_move_wide_16(): + /* move-wide/16 vAAAA, vBBBB */ + /* NOTE: regs can overlap, e.g. "move v6, v7" or "move v7, v6" */ + FETCH(a3, 2) # a3 <- BBBB + FETCH(a2, 1) # a2 <- AAAA + EAS2(a3, rFP, a3) # a3 <- &fp[BBBB] + LOAD64(a0, a1, a3) # a0/a1 <- fp[BBBB] + FETCH_ADVANCE_INST(3) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG64_GOTO(a0, a1, a2, t0) # fp[AAAA] <- a0/a1 + +%def op_move_wide_from16(): + /* move-wide/from16 vAA, vBBBB */ + /* NOTE: regs can overlap, e.g. "move v6, v7" or "move v7, v6" */ + FETCH(a3, 1) # a3 <- BBBB + GET_OPA(a2) # a2 <- AA + EAS2(a3, rFP, a3) # a3 <- &fp[BBBB] + LOAD64(a0, a1, a3) # a0/a1 <- fp[BBBB] + FETCH_ADVANCE_INST(2) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + SET_VREG64_GOTO(a0, a1, a2, t0) # fp[AA] <- a0/a1 + +%def op_nop(): + FETCH_ADVANCE_INST(1) # advance rPC, load rINST + GET_INST_OPCODE(t0) # extract opcode from rINST + GOTO_OPCODE(t0) # jump to next instruction + +%def op_unused_3e(): +% unused() + +%def op_unused_3f(): +% unused() + +%def op_unused_40(): +% unused() + +%def op_unused_41(): +% unused() + +%def op_unused_42(): +% unused() + +%def op_unused_43(): +% unused() + +%def op_unused_73(): +% unused() + +%def op_unused_79(): +% unused() + +%def op_unused_7a(): +% unused() + +%def op_unused_f3(): +% unused() + +%def op_unused_f4(): +% unused() + +%def op_unused_f5(): +% unused() + +%def op_unused_f6(): +% unused() + +%def op_unused_f7(): +% unused() + +%def op_unused_f8(): +% unused() + +%def op_unused_f9(): +% unused() + +%def op_unused_fc(): +% unused() + +%def op_unused_fd(): +% unused() diff --git a/runtime/interpreter/mterp/mips/unop.S b/runtime/interpreter/mterp/mips/unop.S deleted file mode 100644 index bc99263adb61bcc71de1a11d119480c820baeb69..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/unop.S +++ /dev/null @@ -1,18 +0,0 @@ -%default {"preinstr":"", "result0":"a0"} - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result0 = op a0". - * This could be a MIPS instruction or a function call. - * - * for: int-to-byte, int-to-char, int-to-short, - * neg-int, not-int, neg-float - */ - /* unop vA, vB */ - GET_OPB(a3) # a3 <- B - GET_OPA4(t0) # t0 <- A+ - GET_VREG(a0, a3) # a0 <- vB - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - $preinstr # optional op - $instr # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t1) # extract opcode from rINST - SET_VREG_GOTO($result0, t0, t1) # vA <- result0 diff --git a/runtime/interpreter/mterp/mips/unopNarrower.S b/runtime/interpreter/mterp/mips/unopNarrower.S deleted file mode 100644 index 0196e27e36fb9be499f5a238f64ed2d64c277589..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/unopNarrower.S +++ /dev/null @@ -1,16 +0,0 @@ -%default {"load":"LOAD64_F(fa0, fa0f, a3)"} - /* - * Generic 64bit-to-32bit floating-point unary operation. Provide an "instr" - * line that specifies an instruction that performs "fv0 = op fa0". - * - * For: double-to-float - */ - /* unop vA, vB */ - GET_OPB(a3) # a3 <- B - GET_OPA4(rOBJ) # rOBJ <- A+ - EAS2(a3, rFP, a3) # a3 <- &fp[B] - $load - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - $instr - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_F_GOTO(fv0, rOBJ, t0) # vA <- fv0 diff --git a/runtime/interpreter/mterp/mips/unopWide.S b/runtime/interpreter/mterp/mips/unopWide.S deleted file mode 100644 index 135d9facdf8a29e019e4df8ac0f4c35afade5cfa..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/unopWide.S +++ /dev/null @@ -1,18 +0,0 @@ -%default {"preinstr":"", "result0":"a0", "result1":"a1"} - /* - * Generic 64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result0/result1 = op a0/a1". - * This could be MIPS instruction or a function call. - * - * For: neg-long, not-long, neg-double, - */ - /* unop vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - EAS2(a3, rFP, a3) # a3 <- &fp[B] - LOAD64(a0, a1, a3) # a0/a1 <- vA - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - $preinstr # optional op - $instr # a0/a1 <- op, a2-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO($result0, $result1, rOBJ, t0) # vA/vA+1 <- a0/a1 diff --git a/runtime/interpreter/mterp/mips/unopWider.S b/runtime/interpreter/mterp/mips/unopWider.S deleted file mode 100644 index ca888ad3fb8cac5f64d188811a9205ae52af880b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/unopWider.S +++ /dev/null @@ -1,16 +0,0 @@ -%default {"preinstr":"", "result0":"a0", "result1":"a1"} - /* - * Generic 32bit-to-64bit unary operation. Provide an "instr" line - * that specifies an instruction that performs "result0/result1 = op a0". - * - * For: int-to-long - */ - /* unop vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a0, a3) # a0 <- vB - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - $preinstr # optional op - $instr # result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO($result0, $result1, rOBJ, t0) # vA/vA+1 <- a0/a1 diff --git a/runtime/interpreter/mterp/mips/unused.S b/runtime/interpreter/mterp/mips/unused.S deleted file mode 100644 index ffa00becfdb2bb4ba58ee7659a0609978599110e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/unused.S +++ /dev/null @@ -1,4 +0,0 @@ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback diff --git a/runtime/interpreter/mterp/mips/zcmp.S b/runtime/interpreter/mterp/mips/zcmp.S deleted file mode 100644 index 8d3a198891ba1fc0b68f195398268dca4e5c8ff4..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips/zcmp.S +++ /dev/null @@ -1,16 +0,0 @@ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - GET_OPA(a0) # a0 <- AA - GET_VREG(a0, a0) # a0 <- vAA - FETCH_S(rINST, 1) # rINST <- branch offset, in code units - b${condition} a0, zero, MterpCommonTakenBranchNoFlags - li t0, JIT_CHECK_OSR # possible OSR re-entry? - beq rPROFILE, t0, .L_check_not_taken_osr - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/alt_stub.S b/runtime/interpreter/mterp/mips64/alt_stub.S deleted file mode 100644 index 12fa84d7d2691db36d400869cbdc863d415a8dfc..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/alt_stub.S +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (${opnum} * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. diff --git a/runtime/interpreter/mterp/mips64/arithmetic.S b/runtime/interpreter/mterp/mips64/arithmetic.S new file mode 100644 index 0000000000000000000000000000000000000000..0b03e02b5ffeddde796a0a8343b7ddae79f5ba19 --- /dev/null +++ b/runtime/interpreter/mterp/mips64/arithmetic.S @@ -0,0 +1,458 @@ +%def binop(preinstr="", result="a0", chkzero="0", instr=""): + /* + * Generic 32-bit binary operation. Provide an "instr" line that + * specifies an instruction that performs "result = a0 op a1". + * This could be a MIPS instruction or a function call. (If the result + * comes back in a register other than a0, you can override "result".) + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vCC (a1). Useful for integer division and modulus. Note that we + * *don't* check for (INT_MIN / -1) here, because the CPU handles it + * correctly. + * + * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, + * xor-int, shl-int, shr-int, ushr-int + */ + /* binop vAA, vBB, vCC */ + srl a4, rINST, 8 # a4 <- AA + lbu a2, 2(rPC) # a2 <- BB + lbu a3, 3(rPC) # a3 <- CC + GET_VREG a0, a2 # a0 <- vBB + GET_VREG a1, a3 # a1 <- vCC + .if $chkzero + beqz a1, common_errDivideByZero # is second operand zero? + .endif + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + $preinstr # optional op + $instr # $result <- op, a0-a3 changed + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG $result, a4 # vAA <- $result + GOTO_OPCODE v0 # jump to next instruction + +%def binop2addr(preinstr="", result="a0", chkzero="0", instr=""): + /* + * Generic 32-bit "/2addr" binary operation. Provide an "instr" line + * that specifies an instruction that performs "result = a0 op a1". + * This could be a MIPS instruction or a function call. (If the result + * comes back in a register other than a0, you can override "result".) + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vB (a1). Useful for integer division and modulus. Note that we + * *don't* check for (INT_MIN / -1) here, because the CPU handles it + * correctly. + * + * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, + * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, + * shl-int/2addr, shr-int/2addr, ushr-int/2addr + */ + /* binop/2addr vA, vB */ + ext a2, rINST, 8, 4 # a2 <- A + ext a3, rINST, 12, 4 # a3 <- B + GET_VREG a0, a2 # a0 <- vA + GET_VREG a1, a3 # a1 <- vB + .if $chkzero + beqz a1, common_errDivideByZero # is second operand zero? + .endif + FETCH_ADVANCE_INST 1 # advance rPC, load rINST + $preinstr # optional op + $instr # $result <- op, a0-a3 changed + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG $result, a2 # vA <- $result + GOTO_OPCODE v0 # jump to next instruction + +%def binopLit16(preinstr="", result="a0", chkzero="0", instr=""): + /* + * Generic 32-bit "lit16" binary operation. Provide an "instr" line + * that specifies an instruction that performs "result = a0 op a1". + * This could be an MIPS instruction or a function call. (If the result + * comes back in a register other than a0, you can override "result".) + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * CCCC (a1). Useful for integer division and modulus. + * + * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, + * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 + */ + /* binop/lit16 vA, vB, #+CCCC */ + lh a1, 2(rPC) # a1 <- sign-extended CCCC + ext a2, rINST, 8, 4 # a2 <- A + ext a3, rINST, 12, 4 # a3 <- B + GET_VREG a0, a3 # a0 <- vB + .if $chkzero + beqz a1, common_errDivideByZero # is second operand zero? + .endif + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + $preinstr # optional op + $instr # $result <- op, a0-a3 changed + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG $result, a2 # vA <- $result + GOTO_OPCODE v0 # jump to next instruction + + +%def binopLit8(preinstr="", result="a0", chkzero="0", instr=""): + /* + * Generic 32-bit "lit8" binary operation. Provide an "instr" line + * that specifies an instruction that performs "result = a0 op a1". + * This could be an MIPS instruction or a function call. (If the result + * comes back in a register other than a0, you can override "result".) + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * CC (a1). Useful for integer division and modulus. + * + * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, + * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, + * shl-int/lit8, shr-int/lit8, ushr-int/lit8 + */ + /* binop/lit8 vAA, vBB, #+CC */ + lbu a3, 2(rPC) # a3 <- BB + lb a1, 3(rPC) # a1 <- sign-extended CC + srl a2, rINST, 8 # a2 <- AA + GET_VREG a0, a3 # a0 <- vBB + .if $chkzero + beqz a1, common_errDivideByZero # is second operand zero? + .endif + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + $preinstr # optional op + $instr # $result <- op, a0-a3 changed + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG $result, a2 # vAA <- $result + GOTO_OPCODE v0 # jump to next instruction + + +%def binopWide(preinstr="", result="a0", chkzero="0", instr=""): + /* + * Generic 64-bit binary operation. Provide an "instr" line that + * specifies an instruction that performs "result = a0 op a1". + * This could be a MIPS instruction or a function call. (If the result + * comes back in a register other than a0, you can override "result".) + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vCC (a1). Useful for integer division and modulus. Note that we + * *don't* check for (LONG_MIN / -1) here, because the CPU handles it + * correctly. + * + * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, + * xor-long, shl-long, shr-long, ushr-long + */ + /* binop vAA, vBB, vCC */ + srl a4, rINST, 8 # a4 <- AA + lbu a2, 2(rPC) # a2 <- BB + lbu a3, 3(rPC) # a3 <- CC + GET_VREG_WIDE a0, a2 # a0 <- vBB + GET_VREG_WIDE a1, a3 # a1 <- vCC + .if $chkzero + beqz a1, common_errDivideByZero # is second operand zero? + .endif + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + $preinstr # optional op + $instr # $result <- op, a0-a3 changed + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG_WIDE $result, a4 # vAA <- $result + GOTO_OPCODE v0 # jump to next instruction + +%def binopWide2addr(preinstr="", result="a0", chkzero="0", instr=""): + /* + * Generic 64-bit "/2addr" binary operation. Provide an "instr" line + * that specifies an instruction that performs "result = a0 op a1". + * This could be a MIPS instruction or a function call. (If the result + * comes back in a register other than a0, you can override "result".) + * + * If "chkzero" is set to 1, we perform a divide-by-zero check on + * vB (a1). Useful for integer division and modulus. Note that we + * *don't* check for (LONG_MIN / -1) here, because the CPU handles it + * correctly. + * + * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, + * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, + * shl-long/2addr, shr-long/2addr, ushr-long/2addr + */ + /* binop/2addr vA, vB */ + ext a2, rINST, 8, 4 # a2 <- A + ext a3, rINST, 12, 4 # a3 <- B + GET_VREG_WIDE a0, a2 # a0 <- vA + GET_VREG_WIDE a1, a3 # a1 <- vB + .if $chkzero + beqz a1, common_errDivideByZero # is second operand zero? + .endif + FETCH_ADVANCE_INST 1 # advance rPC, load rINST + $preinstr # optional op + $instr # $result <- op, a0-a3 changed + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG_WIDE $result, a2 # vA <- $result + GOTO_OPCODE v0 # jump to next instruction + +%def unop(preinstr="", instr=""): + /* + * Generic 32-bit unary operation. Provide an "instr" line that + * specifies an instruction that performs "a0 = op a0". + * + * for: int-to-byte, int-to-char, int-to-short, + * not-int, neg-int + */ + /* unop vA, vB */ + ext a3, rINST, 12, 4 # a3 <- B + GET_VREG a0, a3 # a0 <- vB + ext a2, rINST, 8, 4 # a2 <- A + $preinstr # optional op + FETCH_ADVANCE_INST 1 # advance rPC, load rINST + $instr # a0 <- op, a0-a3 changed + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG a0, a2 # vA <- a0 + GOTO_OPCODE v0 # jump to next instruction + +%def unopWide(preinstr="", instr=""): + /* + * Generic 64-bit unary operation. Provide an "instr" line that + * specifies an instruction that performs "a0 = op a0". + * + * For: not-long, neg-long + */ + /* unop vA, vB */ + ext a3, rINST, 12, 4 # a3 <- B + GET_VREG_WIDE a0, a3 # a0 <- vB + ext a2, rINST, 8, 4 # a2 <- A + $preinstr # optional op + FETCH_ADVANCE_INST 1 # advance rPC, load rINST + $instr # a0 <- op, a0-a3 changed + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG_WIDE a0, a2 # vA <- a0 + GOTO_OPCODE v0 # jump to next instruction + +%def op_add_int(): +% binop(instr="addu a0, a0, a1") + +%def op_add_int_2addr(): +% binop2addr(instr="addu a0, a0, a1") + +%def op_add_int_lit16(): +% binopLit16(instr="addu a0, a0, a1") + +%def op_add_int_lit8(): +% binopLit8(instr="addu a0, a0, a1") + +%def op_add_long(): +% binopWide(instr="daddu a0, a0, a1") + +%def op_add_long_2addr(): +% binopWide2addr(instr="daddu a0, a0, a1") + +%def op_and_int(): +% binop(instr="and a0, a0, a1") + +%def op_and_int_2addr(): +% binop2addr(instr="and a0, a0, a1") + +%def op_and_int_lit16(): +% binopLit16(instr="and a0, a0, a1") + +%def op_and_int_lit8(): +% binopLit8(instr="and a0, a0, a1") + +%def op_and_long(): +% binopWide(instr="and a0, a0, a1") + +%def op_and_long_2addr(): +% binopWide2addr(instr="and a0, a0, a1") + +%def op_cmp_long(): + /* cmp-long vAA, vBB, vCC */ + lbu a2, 2(rPC) # a2 <- BB + lbu a3, 3(rPC) # a3 <- CC + srl a4, rINST, 8 # a4 <- AA + GET_VREG_WIDE a0, a2 # a0 <- vBB + GET_VREG_WIDE a1, a3 # a1 <- vCC + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + slt a2, a0, a1 + slt a0, a1, a0 + subu a0, a0, a2 + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG a0, a4 # vAA <- result + GOTO_OPCODE v0 # jump to next instruction + +%def op_div_int(): +% binop(instr="div a0, a0, a1", chkzero="1") + +%def op_div_int_2addr(): +% binop2addr(instr="div a0, a0, a1", chkzero="1") + +%def op_div_int_lit16(): +% binopLit16(instr="div a0, a0, a1", chkzero="1") + +%def op_div_int_lit8(): +% binopLit8(instr="div a0, a0, a1", chkzero="1") + +%def op_div_long(): +% binopWide(instr="ddiv a0, a0, a1", chkzero="1") + +%def op_div_long_2addr(): +% binopWide2addr(instr="ddiv a0, a0, a1", chkzero="1") + +%def op_int_to_byte(): +% unop(instr="seb a0, a0") + +%def op_int_to_char(): +% unop(instr="and a0, a0, 0xffff") + +%def op_int_to_long(): + /* int-to-long vA, vB */ + ext a3, rINST, 12, 4 # a3 <- B + GET_VREG a0, a3 # a0 <- vB (sign-extended to 64 bits) + ext a2, rINST, 8, 4 # a2 <- A + FETCH_ADVANCE_INST 1 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG_WIDE a0, a2 # vA <- vB + GOTO_OPCODE v0 # jump to next instruction + +%def op_int_to_short(): +% unop(instr="seh a0, a0") + +%def op_long_to_int(): +/* we ignore the high word, making this equivalent to a 32-bit reg move */ +% op_move() + +%def op_mul_int(): +% binop(instr="mul a0, a0, a1") + +%def op_mul_int_2addr(): +% binop2addr(instr="mul a0, a0, a1") + +%def op_mul_int_lit16(): +% binopLit16(instr="mul a0, a0, a1") + +%def op_mul_int_lit8(): +% binopLit8(instr="mul a0, a0, a1") + +%def op_mul_long(): +% binopWide(instr="dmul a0, a0, a1") + +%def op_mul_long_2addr(): +% binopWide2addr(instr="dmul a0, a0, a1") + +%def op_neg_int(): +% unop(instr="subu a0, zero, a0") + +%def op_neg_long(): +% unopWide(instr="dsubu a0, zero, a0") + +%def op_not_int(): +% unop(instr="nor a0, zero, a0") + +%def op_not_long(): +% unopWide(instr="nor a0, zero, a0") + +%def op_or_int(): +% binop(instr="or a0, a0, a1") + +%def op_or_int_2addr(): +% binop2addr(instr="or a0, a0, a1") + +%def op_or_int_lit16(): +% binopLit16(instr="or a0, a0, a1") + +%def op_or_int_lit8(): +% binopLit8(instr="or a0, a0, a1") + +%def op_or_long(): +% binopWide(instr="or a0, a0, a1") + +%def op_or_long_2addr(): +% binopWide2addr(instr="or a0, a0, a1") + +%def op_rem_int(): +% binop(instr="mod a0, a0, a1", chkzero="1") + +%def op_rem_int_2addr(): +% binop2addr(instr="mod a0, a0, a1", chkzero="1") + +%def op_rem_int_lit16(): +% binopLit16(instr="mod a0, a0, a1", chkzero="1") + +%def op_rem_int_lit8(): +% binopLit8(instr="mod a0, a0, a1", chkzero="1") + +%def op_rem_long(): +% binopWide(instr="dmod a0, a0, a1", chkzero="1") + +%def op_rem_long_2addr(): +% binopWide2addr(instr="dmod a0, a0, a1", chkzero="1") + +%def op_rsub_int(): +% binopLit16(instr="subu a0, a1, a0") + +%def op_rsub_int_lit8(): +% binopLit8(instr="subu a0, a1, a0") + +%def op_shl_int(): +% binop(instr="sll a0, a0, a1") + +%def op_shl_int_2addr(): +% binop2addr(instr="sll a0, a0, a1") + +%def op_shl_int_lit8(): +% binopLit8(instr="sll a0, a0, a1") + +%def op_shl_long(): +% binopWide(instr="dsll a0, a0, a1") + +%def op_shl_long_2addr(): +% binopWide2addr(instr="dsll a0, a0, a1") + +%def op_shr_int(): +% binop(instr="sra a0, a0, a1") + +%def op_shr_int_2addr(): +% binop2addr(instr="sra a0, a0, a1") + +%def op_shr_int_lit8(): +% binopLit8(instr="sra a0, a0, a1") + +%def op_shr_long(): +% binopWide(instr="dsra a0, a0, a1") + +%def op_shr_long_2addr(): +% binopWide2addr(instr="dsra a0, a0, a1") + +%def op_sub_int(): +% binop(instr="subu a0, a0, a1") + +%def op_sub_int_2addr(): +% binop2addr(instr="subu a0, a0, a1") + +%def op_sub_long(): +% binopWide(instr="dsubu a0, a0, a1") + +%def op_sub_long_2addr(): +% binopWide2addr(instr="dsubu a0, a0, a1") + +%def op_ushr_int(): +% binop(instr="srl a0, a0, a1") + +%def op_ushr_int_2addr(): +% binop2addr(instr="srl a0, a0, a1") + +%def op_ushr_int_lit8(): +% binopLit8(instr="srl a0, a0, a1") + +%def op_ushr_long(): +% binopWide(instr="dsrl a0, a0, a1") + +%def op_ushr_long_2addr(): +% binopWide2addr(instr="dsrl a0, a0, a1") + +%def op_xor_int(): +% binop(instr="xor a0, a0, a1") + +%def op_xor_int_2addr(): +% binop2addr(instr="xor a0, a0, a1") + +%def op_xor_int_lit16(): +% binopLit16(instr="xor a0, a0, a1") + +%def op_xor_int_lit8(): +% binopLit8(instr="xor a0, a0, a1") + +%def op_xor_long(): +% binopWide(instr="xor a0, a0, a1") + +%def op_xor_long_2addr(): +% binopWide2addr(instr="xor a0, a0, a1") diff --git a/runtime/interpreter/mterp/mips64/array.S b/runtime/interpreter/mterp/mips64/array.S new file mode 100644 index 0000000000000000000000000000000000000000..9d97f0ad8d3ad3bc0aa25c1b87af220ebd5ff334 --- /dev/null +++ b/runtime/interpreter/mterp/mips64/array.S @@ -0,0 +1,241 @@ +%def op_aget(load="lw", shift="2", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"): + /* + * Array get, 32 bits or less. vAA <- vBB[vCC]. + * + * for: aget, aget-boolean, aget-byte, aget-char, aget-short + * + * NOTE: assumes data offset for arrays is the same for all non-wide types. + * If this changes, specialize. + */ + /* op vAA, vBB, vCC */ + lbu a2, 2(rPC) # a2 <- BB + lbu a3, 3(rPC) # a3 <- CC + srl a4, rINST, 8 # a4 <- AA + GET_VREG_U a0, a2 # a0 <- vBB (array object) + GET_VREG a1, a3 # a1 <- vCC (requested index) + beqz a0, common_errNullObject # bail if null array object + lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length + .if $shift + # [d]lsa does not support shift count of 0. + dlsa a0, a1, a0, $shift # a0 <- arrayObj + index*width + .else + daddu a0, a1, a0 # a0 <- arrayObj + index*width + .endif + bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + $load a2, $data_offset(a0) # a2 <- vBB[vCC] + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG a2, a4 # vAA <- a2 + GOTO_OPCODE v0 # jump to next instruction + +%def op_aget_boolean(): +% op_aget(load="lbu", shift="0", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") + +%def op_aget_byte(): +% op_aget(load="lb", shift="0", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") + +%def op_aget_char(): +% op_aget(load="lhu", shift="1", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") + +%def op_aget_object(): + /* + * Array object get. vAA <- vBB[vCC]. + * + * for: aget-object + */ + /* op vAA, vBB, vCC */ + .extern artAGetObjectFromMterp + lbu a2, 2(rPC) # a2 <- BB + lbu a3, 3(rPC) # a3 <- CC + EXPORT_PC + GET_VREG_U a0, a2 # a0 <- vBB (array object) + GET_VREG a1, a3 # a1 <- vCC (requested index) + jal artAGetObjectFromMterp # (array, index) + ld a1, THREAD_EXCEPTION_OFFSET(rSELF) + srl a4, rINST, 8 # a4 <- AA + PREFETCH_INST 2 + bnez a1, MterpException + SET_VREG_OBJECT v0, a4 # vAA <- v0 + ADVANCE 2 + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +%def op_aget_short(): +% op_aget(load="lh", shift="1", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") + +%def op_aget_wide(): + /* + * Array get, 64 bits. vAA <- vBB[vCC]. + * + */ + /* aget-wide vAA, vBB, vCC */ + lbu a2, 2(rPC) # a2 <- BB + lbu a3, 3(rPC) # a3 <- CC + srl a4, rINST, 8 # a4 <- AA + GET_VREG_U a0, a2 # a0 <- vBB (array object) + GET_VREG a1, a3 # a1 <- vCC (requested index) + beqz a0, common_errNullObject # bail if null array object + lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length + dlsa a0, a1, a0, 3 # a0 <- arrayObj + index*width + bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + lw a2, MIRROR_WIDE_ARRAY_DATA_OFFSET(a0) + lw a3, (MIRROR_WIDE_ARRAY_DATA_OFFSET+4)(a0) + dinsu a2, a3, 32, 32 # a2 <- vBB[vCC] + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG_WIDE a2, a4 # vAA <- a2 + GOTO_OPCODE v0 # jump to next instruction + +%def op_aput(store="sw", shift="2", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"): + /* + * Array put, 32 bits or less. vBB[vCC] <- vAA. + * + * for: aput, aput-boolean, aput-byte, aput-char, aput-short + * + * NOTE: this assumes data offset for arrays is the same for all non-wide types. + * If this changes, specialize. + */ + /* op vAA, vBB, vCC */ + lbu a2, 2(rPC) # a2 <- BB + lbu a3, 3(rPC) # a3 <- CC + srl a4, rINST, 8 # a4 <- AA + GET_VREG_U a0, a2 # a0 <- vBB (array object) + GET_VREG a1, a3 # a1 <- vCC (requested index) + beqz a0, common_errNullObject # bail if null array object + lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length + .if $shift + # [d]lsa does not support shift count of 0. + dlsa a0, a1, a0, $shift # a0 <- arrayObj + index*width + .else + daddu a0, a1, a0 # a0 <- arrayObj + index*width + .endif + bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + GET_VREG a2, a4 # a2 <- vAA + GET_INST_OPCODE v0 # extract opcode from rINST + $store a2, $data_offset(a0) # vBB[vCC] <- a2 + GOTO_OPCODE v0 # jump to next instruction + +%def op_aput_boolean(): +% op_aput(store="sb", shift="0", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") + +%def op_aput_byte(): +% op_aput(store="sb", shift="0", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") + +%def op_aput_char(): +% op_aput(store="sh", shift="1", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") + +%def op_aput_object(): + /* + * Store an object into an array. vBB[vCC] <- vAA. + */ + /* op vAA, vBB, vCC */ + .extern MterpAputObject + EXPORT_PC + daddu a0, rFP, OFF_FP_SHADOWFRAME + move a1, rPC + move a2, rINST + jal MterpAputObject + beqzc v0, MterpPossibleException + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +%def op_aput_short(): +% op_aput(store="sh", shift="1", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") + +%def op_aput_wide(): + /* + * Array put, 64 bits. vBB[vCC] <- vAA. + * + */ + /* aput-wide vAA, vBB, vCC */ + lbu a2, 2(rPC) # a2 <- BB + lbu a3, 3(rPC) # a3 <- CC + srl a4, rINST, 8 # a4 <- AA + GET_VREG_U a0, a2 # a0 <- vBB (array object) + GET_VREG a1, a3 # a1 <- vCC (requested index) + beqz a0, common_errNullObject # bail if null array object + lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length + dlsa a0, a1, a0, 3 # a0 <- arrayObj + index*width + bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail + GET_VREG_WIDE a2, a4 # a2 <- vAA + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + sw a2, MIRROR_WIDE_ARRAY_DATA_OFFSET(a0) + dsrl32 a2, a2, 0 + sw a2, (MIRROR_WIDE_ARRAY_DATA_OFFSET+4)(a0) # vBB[vCC] <- a2 + GOTO_OPCODE v0 # jump to next instruction + +%def op_array_length(): + /* + * Return the length of an array. + */ + srl a1, rINST, 12 # a1 <- B + GET_VREG_U a0, a1 # a0 <- vB (object ref) + ext a2, rINST, 8, 4 # a2 <- A + beqz a0, common_errNullObject # yup, fail + FETCH_ADVANCE_INST 1 # advance rPC, load rINST + lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- array length + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG a3, a2 # vB <- length + GOTO_OPCODE v0 # jump to next instruction + +%def op_fill_array_data(): + /* fill-array-data vAA, +BBBBBBBB */ + .extern MterpFillArrayData + EXPORT_PC + lh a1, 2(rPC) # a1 <- bbbb (lo) + lh a0, 4(rPC) # a0 <- BBBB (hi) + srl a3, rINST, 8 # a3 <- AA + ins a1, a0, 16, 16 # a1 <- BBBBbbbb + GET_VREG_U a0, a3 # a0 <- vAA (array object) + dlsa a1, a1, rPC, 1 # a1 <- PC + BBBBbbbb*2 (array data off.) + jal MterpFillArrayData # (obj, payload) + beqzc v0, MterpPossibleException # exception? + FETCH_ADVANCE_INST 3 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +%def op_filled_new_array(helper="MterpFilledNewArray"): + /* + * Create a new array with elements filled from registers. + * + * for: filled-new-array, filled-new-array/range + */ + /* op vB, {vD, vE, vF, vG, vA}, class//CCCC */ + /* op {vCCCC..v(CCCC+AA-1)}, type//BBBB */ + .extern $helper + EXPORT_PC + daddu a0, rFP, OFF_FP_SHADOWFRAME + move a1, rPC + move a2, rSELF + jal $helper + beqzc v0, MterpPossibleException + FETCH_ADVANCE_INST 3 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +%def op_filled_new_array_range(): +% op_filled_new_array(helper="MterpFilledNewArrayRange") + +%def op_new_array(): + /* + * Allocate an array of objects, specified with the array class + * and a count. + * + * The verifier guarantees that this is an array class, so we don't + * check for it here. + */ + /* new-array vA, vB, class//CCCC */ + .extern MterpNewArray + EXPORT_PC + daddu a0, rFP, OFF_FP_SHADOWFRAME + move a1, rPC + move a2, rINST + move a3, rSELF + jal MterpNewArray + beqzc v0, MterpPossibleException + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/bincmp.S b/runtime/interpreter/mterp/mips64/bincmp.S deleted file mode 100644 index c2bca91ebfaf4c32f19ba6a8a69440b6ffc7f49c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/bincmp.S +++ /dev/null @@ -1,19 +0,0 @@ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform, e.g. for - * "if-le" you would use "le". - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - lh rINST, 2(rPC) # rINST <- offset (sign-extended CCCC) - GET_VREG a0, a2 # a0 <- vA - GET_VREG a1, a3 # a1 <- vB - b${condition}c a0, a1, MterpCommonTakenBranchNoFlags - li v0, JIT_CHECK_OSR # possible OSR re-entry? - beqc rPROFILE, v0, .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/binop.S b/runtime/interpreter/mterp/mips64/binop.S deleted file mode 100644 index fab48b73b3d73e93f6ef4e9ec748adf3fde5c5de..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/binop.S +++ /dev/null @@ -1,30 +0,0 @@ -%default {"preinstr":"", "result":"a0", "chkzero":"0"} - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG a0, a2 # a0 <- vBB - GET_VREG a1, a3 # a1 <- vCC - .if $chkzero - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - $preinstr # optional op - $instr # $result <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG $result, a4 # vAA <- $result - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/binop2addr.S b/runtime/interpreter/mterp/mips64/binop2addr.S deleted file mode 100644 index 1ae73f51d45ef2910998a691f096cae627b88374..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/binop2addr.S +++ /dev/null @@ -1,30 +0,0 @@ -%default {"preinstr":"", "result":"a0", "chkzero":"0"} - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a2 # a0 <- vA - GET_VREG a1, a3 # a1 <- vB - .if $chkzero - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - $preinstr # optional op - $instr # $result <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG $result, a2 # vA <- $result - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/binopLit16.S b/runtime/interpreter/mterp/mips64/binopLit16.S deleted file mode 100644 index 925775824cb41eaac65dc757e48a2b48965e7182..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/binopLit16.S +++ /dev/null @@ -1,28 +0,0 @@ -%default {"preinstr":"", "result":"a0", "chkzero":"0"} - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * CCCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - lh a1, 2(rPC) # a1 <- sign-extended CCCC - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a3 # a0 <- vB - .if $chkzero - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - $preinstr # optional op - $instr # $result <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG $result, a2 # vA <- $result - GOTO_OPCODE v0 # jump to next instruction - diff --git a/runtime/interpreter/mterp/mips64/binopLit8.S b/runtime/interpreter/mterp/mips64/binopLit8.S deleted file mode 100644 index f4a0bba9b919eef9b75f6e5ed9e41501ad8f0094..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/binopLit8.S +++ /dev/null @@ -1,29 +0,0 @@ -%default {"preinstr":"", "result":"a0", "chkzero":"0"} - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * CC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - lbu a3, 2(rPC) # a3 <- BB - lb a1, 3(rPC) # a1 <- sign-extended CC - srl a2, rINST, 8 # a2 <- AA - GET_VREG a0, a3 # a0 <- vBB - .if $chkzero - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - $preinstr # optional op - $instr # $result <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG $result, a2 # vAA <- $result - GOTO_OPCODE v0 # jump to next instruction - diff --git a/runtime/interpreter/mterp/mips64/binopWide.S b/runtime/interpreter/mterp/mips64/binopWide.S deleted file mode 100644 index 732f0d60f9da4172d7034daee7f55f56ba8c2b5b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/binopWide.S +++ /dev/null @@ -1,30 +0,0 @@ -%default {"preinstr":"", "result":"a0", "chkzero":"0"} - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, shl-long, shr-long, ushr-long - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_WIDE a0, a2 # a0 <- vBB - GET_VREG_WIDE a1, a3 # a1 <- vCC - .if $chkzero - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - $preinstr # optional op - $instr # $result <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE $result, a4 # vAA <- $result - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/binopWide2addr.S b/runtime/interpreter/mterp/mips64/binopWide2addr.S deleted file mode 100644 index 45d8d829602aec518809939610e2eba9bf5d9896..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/binopWide2addr.S +++ /dev/null @@ -1,30 +0,0 @@ -%default {"preinstr":"", "result":"a0", "chkzero":"0"} - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_WIDE a0, a2 # a0 <- vA - GET_VREG_WIDE a1, a3 # a1 <- vB - .if $chkzero - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - $preinstr # optional op - $instr # $result <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE $result, a2 # vA <- $result - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/const.S b/runtime/interpreter/mterp/mips64/const.S deleted file mode 100644 index 2ec1173a7cc6cae2a1a648359882179e824a08f1..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/const.S +++ /dev/null @@ -1,17 +0,0 @@ -%default { "helper":"UndefinedConstHandler" } - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern $helper - EXPORT_PC - lhu a0, 2(rPC) # a0 <- BBBB - srl a1, rINST, 8 # a1 <- AA - daddu a2, rFP, OFF_FP_SHADOWFRAME - move a3, rSELF - jal $helper # (index, tgt_reg, shadow_frame, self) - PREFETCH_INST 2 # load rINST - bnez v0, MterpPossibleException # let reference interpreter deal with it. - ADVANCE 2 # advance rPC - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/control_flow.S b/runtime/interpreter/mterp/mips64/control_flow.S new file mode 100644 index 0000000000000000000000000000000000000000..457b93894a5546f9f8988590fe9ad328e0f1216f --- /dev/null +++ b/runtime/interpreter/mterp/mips64/control_flow.S @@ -0,0 +1,217 @@ +%def bincmp(condition=""): + /* + * Generic two-operand compare-and-branch operation. Provide a "condition" + * fragment that specifies the comparison to perform, e.g. for + * "if-le" you would use "le". + * + * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le + */ + /* if-cmp vA, vB, +CCCC */ + ext a2, rINST, 8, 4 # a2 <- A + ext a3, rINST, 12, 4 # a3 <- B + lh rINST, 2(rPC) # rINST <- offset (sign-extended CCCC) + GET_VREG a0, a2 # a0 <- vA + GET_VREG a1, a3 # a1 <- vB + b${condition}c a0, a1, MterpCommonTakenBranchNoFlags + li v0, JIT_CHECK_OSR # possible OSR re-entry? + beqc rPROFILE, v0, .L_check_not_taken_osr + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +%def zcmp(condition=""): + /* + * Generic one-operand compare-and-branch operation. Provide a "condition" + * fragment that specifies the comparison to perform, e.g. for + * "if-lez" you would use "le". + * + * For: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez + */ + /* if-cmp vAA, +BBBB */ + srl a2, rINST, 8 # a2 <- AA + lh rINST, 2(rPC) # rINST <- offset (sign-extended BBBB) + GET_VREG a0, a2 # a0 <- vAA + b${condition}zc a0, MterpCommonTakenBranchNoFlags + li v0, JIT_CHECK_OSR # possible OSR re-entry? + beqc rPROFILE, v0, .L_check_not_taken_osr + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +%def op_goto(): + /* + * Unconditional branch, 8-bit offset. + * + * The branch distance is a signed code-unit offset, which we need to + * double to get a byte offset. + */ + /* goto +AA */ + srl rINST, rINST, 8 + seb rINST, rINST # rINST <- offset (sign-extended AA) + b MterpCommonTakenBranchNoFlags + +%def op_goto_16(): + /* + * Unconditional branch, 16-bit offset. + * + * The branch distance is a signed code-unit offset, which we need to + * double to get a byte offset. + */ + /* goto/16 +AAAA */ + lh rINST, 2(rPC) # rINST <- offset (sign-extended AAAA) + b MterpCommonTakenBranchNoFlags + +%def op_goto_32(): + /* + * Unconditional branch, 32-bit offset. + * + * The branch distance is a signed code-unit offset, which we need to + * double to get a byte offset. + * + * Unlike most opcodes, this one is allowed to branch to itself, so + * our "backward branch" test must be "<=0" instead of "<0". + */ + /* goto/32 +AAAAAAAA */ + lh rINST, 2(rPC) # rINST <- aaaa (low) + lh a1, 4(rPC) # a1 <- AAAA (high) + ins rINST, a1, 16, 16 # rINST <- offset (sign-extended AAAAaaaa) + b MterpCommonTakenBranchNoFlags + +%def op_if_eq(): +% bincmp(condition="eq") + +%def op_if_eqz(): +% zcmp(condition="eq") + +%def op_if_ge(): +% bincmp(condition="ge") + +%def op_if_gez(): +% zcmp(condition="ge") + +%def op_if_gt(): +% bincmp(condition="gt") + +%def op_if_gtz(): +% zcmp(condition="gt") + +%def op_if_le(): +% bincmp(condition="le") + +%def op_if_lez(): +% zcmp(condition="le") + +%def op_if_lt(): +% bincmp(condition="lt") + +%def op_if_ltz(): +% zcmp(condition="lt") + +%def op_if_ne(): +% bincmp(condition="ne") + +%def op_if_nez(): +% zcmp(condition="ne") + +%def op_packed_switch(func="MterpDoPackedSwitch"): + /* + * Handle a packed-switch or sparse-switch instruction. In both cases + * we decode it and hand it off to a helper function. + * + * We don't really expect backward branches in a switch statement, but + * they're perfectly legal, so we check for them here. + * + * for: packed-switch, sparse-switch + */ + /* op vAA, +BBBBBBBB */ + .extern $func + lh a0, 2(rPC) # a0 <- bbbb (lo) + lh a1, 4(rPC) # a1 <- BBBB (hi) + srl a3, rINST, 8 # a3 <- AA + ins a0, a1, 16, 16 # a0 <- BBBBbbbb + GET_VREG a1, a3 # a1 <- vAA + dlsa a0, a0, rPC, 1 # a0 <- PC + BBBBbbbb*2 + jal $func # v0 <- code-unit branch offset + move rINST, v0 + b MterpCommonTakenBranchNoFlags + +%def op_return(instr="GET_VREG"): + /* + * Return a 32-bit value. + * + * for: return (sign-extend), return-object (zero-extend) + */ + /* op vAA */ + .extern MterpThreadFenceForConstructor + .extern MterpSuspendCheck + jal MterpThreadFenceForConstructor + lw ra, THREAD_FLAGS_OFFSET(rSELF) + move a0, rSELF + and ra, ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST + beqzc ra, 1f + jal MterpSuspendCheck # (self) +1: + srl a2, rINST, 8 # a2 <- AA + $instr a0, a2 # a0 <- vAA + b MterpReturn + +%def op_return_object(): +% op_return(instr="GET_VREG_U") + +%def op_return_void(): + .extern MterpThreadFenceForConstructor + .extern MterpSuspendCheck + jal MterpThreadFenceForConstructor + lw ra, THREAD_FLAGS_OFFSET(rSELF) + move a0, rSELF + and ra, ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST + beqzc ra, 1f + jal MterpSuspendCheck # (self) +1: + li a0, 0 + b MterpReturn + +%def op_return_void_no_barrier(): + .extern MterpSuspendCheck + lw ra, THREAD_FLAGS_OFFSET(rSELF) + move a0, rSELF + and ra, ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST + beqzc ra, 1f + jal MterpSuspendCheck # (self) +1: + li a0, 0 + b MterpReturn + +%def op_return_wide(): + /* + * Return a 64-bit value. + */ + /* return-wide vAA */ + /* op vAA */ + .extern MterpThreadFenceForConstructor + .extern MterpSuspendCheck + jal MterpThreadFenceForConstructor + lw ra, THREAD_FLAGS_OFFSET(rSELF) + move a0, rSELF + and ra, ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST + beqzc ra, 1f + jal MterpSuspendCheck # (self) +1: + srl a2, rINST, 8 # a2 <- AA + GET_VREG_WIDE a0, a2 # a0 <- vAA + b MterpReturn + +%def op_sparse_switch(): +% op_packed_switch(func="MterpDoSparseSwitch") + +%def op_throw(): + /* + * Throw an exception object in the current thread. + */ + /* throw vAA */ + EXPORT_PC + srl a2, rINST, 8 # a2 <- AA + GET_VREG_U a0, a2 # a0 <- vAA (exception object) + beqzc a0, common_errNullObject + sd a0, THREAD_EXCEPTION_OFFSET(rSELF) # thread->exception <- obj + b MterpException diff --git a/runtime/interpreter/mterp/mips64/entry.S b/runtime/interpreter/mterp/mips64/entry.S deleted file mode 100644 index ed965aa2018ddd062c8e40e24c0a9256d46fd7b0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/entry.S +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * Interpreter entry point. - */ - - .set reorder - - .text - .global ExecuteMterpImpl - .type ExecuteMterpImpl, %function - .balign 16 -/* - * On entry: - * a0 Thread* self - * a1 dex_instructions - * a2 ShadowFrame - * a3 JValue* result_register - * - */ -ExecuteMterpImpl: - .cfi_startproc - .cpsetup t9, t8, ExecuteMterpImpl - - .cfi_def_cfa sp, 0 - daddu sp, sp, -STACK_SIZE - .cfi_adjust_cfa_offset STACK_SIZE - - sd t8, STACK_OFFSET_GP(sp) - .cfi_rel_offset 28, STACK_OFFSET_GP - sd ra, STACK_OFFSET_RA(sp) - .cfi_rel_offset 31, STACK_OFFSET_RA - - sd s0, STACK_OFFSET_S0(sp) - .cfi_rel_offset 16, STACK_OFFSET_S0 - sd s1, STACK_OFFSET_S1(sp) - .cfi_rel_offset 17, STACK_OFFSET_S1 - sd s2, STACK_OFFSET_S2(sp) - .cfi_rel_offset 18, STACK_OFFSET_S2 - sd s3, STACK_OFFSET_S3(sp) - .cfi_rel_offset 19, STACK_OFFSET_S3 - sd s4, STACK_OFFSET_S4(sp) - .cfi_rel_offset 20, STACK_OFFSET_S4 - sd s5, STACK_OFFSET_S5(sp) - .cfi_rel_offset 21, STACK_OFFSET_S5 - sd s6, STACK_OFFSET_S6(sp) - .cfi_rel_offset 22, STACK_OFFSET_S6 - - /* Remember the return register */ - sd a3, SHADOWFRAME_RESULT_REGISTER_OFFSET(a2) - - /* Remember the dex instruction pointer */ - sd a1, SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET(a2) - - /* set up "named" registers */ - move rSELF, a0 - daddu rFP, a2, SHADOWFRAME_VREGS_OFFSET - lw v0, SHADOWFRAME_NUMBER_OF_VREGS_OFFSET(a2) - dlsa rREFS, v0, rFP, 2 - lw v0, SHADOWFRAME_DEX_PC_OFFSET(a2) - dlsa rPC, v0, a1, 1 - CFI_DEFINE_DEX_PC_WITH_OFFSET(CFI_TMP, CFI_DEX, 0) - EXPORT_PC - - /* Starting ibase */ - REFRESH_IBASE - - /* Set up for backwards branches & osr profiling */ - ld a0, OFF_FP_METHOD(rFP) - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rSELF - jal MterpSetUpHotnessCountdown - move rPROFILE, v0 # Starting hotness countdown to rPROFILE - - /* start executing the instruction at rPC */ - FETCH_INST - GET_INST_OPCODE v0 - GOTO_OPCODE v0 - - /* NOTE: no fallthrough */ diff --git a/runtime/interpreter/mterp/mips64/fallback.S b/runtime/interpreter/mterp/mips64/fallback.S deleted file mode 100644 index 560b994b08e568c787b931292a937db1f8ec3ff9..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/fallback.S +++ /dev/null @@ -1,2 +0,0 @@ -/* Transfer stub to alternate interpreter */ - b MterpFallback diff --git a/runtime/interpreter/mterp/mips64/fbinop.S b/runtime/interpreter/mterp/mips64/fbinop.S deleted file mode 100644 index f19dd1c3d9fefc6e8aa40813b583c48b0b25ca68..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/fbinop.S +++ /dev/null @@ -1,18 +0,0 @@ -%default {} - /*: - * Generic 32-bit floating-point operation. - * - * For: add-float, sub-float, mul-float, div-float. - * form: f0, f0, f1 - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_FLOAT f0, a2 # f0 <- vBB - GET_VREG_FLOAT f1, a3 # f1 <- vCC - $instr # f0 <- f0 op f1 - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_FLOAT f0, a4 # vAA <- f0 - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/fbinop2addr.S b/runtime/interpreter/mterp/mips64/fbinop2addr.S deleted file mode 100644 index 2e2cd7e8e9528447d5b578fee3d62c3cc95b1e97..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/fbinop2addr.S +++ /dev/null @@ -1,17 +0,0 @@ -%default {} - /*: - * Generic 32-bit "/2addr" floating-point operation. - * - * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr. - * form: f0, f0, f1 - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_FLOAT f0, a2 # f0 <- vA - GET_VREG_FLOAT f1, a3 # f1 <- vB - $instr # f0 <- f0 op f1 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_FLOAT f0, a2 # vA <- f0 - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/fbinopWide.S b/runtime/interpreter/mterp/mips64/fbinopWide.S deleted file mode 100644 index 8915c9447cf9301f9634c60ed02e8ba4d6d1bbdd..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/fbinopWide.S +++ /dev/null @@ -1,18 +0,0 @@ -%default {} - /*: - * Generic 64-bit floating-point operation. - * - * For: add-double, sub-double, mul-double, div-double. - * form: f0, f0, f1 - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_DOUBLE f0, a2 # f0 <- vBB - GET_VREG_DOUBLE f1, a3 # f1 <- vCC - $instr # f0 <- f0 op f1 - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_DOUBLE f0, a4 # vAA <- f0 - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/fbinopWide2addr.S b/runtime/interpreter/mterp/mips64/fbinopWide2addr.S deleted file mode 100644 index a3f4eaa8cca421ca7fb666ae45d41fa7753b9ffc..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/fbinopWide2addr.S +++ /dev/null @@ -1,17 +0,0 @@ -%default {} - /*: - * Generic 64-bit "/2addr" floating-point operation. - * - * For: add-double/2addr, sub-double/2addr, mul-double/2addr, div-double/2addr. - * form: f0, f0, f1 - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_DOUBLE f0, a2 # f0 <- vA - GET_VREG_DOUBLE f1, a3 # f1 <- vB - $instr # f0 <- f0 op f1 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_DOUBLE f0, a2 # vA <- f0 - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/fcmp.S b/runtime/interpreter/mterp/mips64/fcmp.S deleted file mode 100644 index 2e1a3e4c3d581d736007046ed83b03ca4d3e4e20..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/fcmp.S +++ /dev/null @@ -1,32 +0,0 @@ -%default {} - /* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * For: cmpl-float, cmpg-float - */ - /* op vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_FLOAT f0, a2 # f0 <- vBB - GET_VREG_FLOAT f1, a3 # f1 <- vCC - cmp.eq.s f2, f0, f1 - li a0, 0 - bc1nez f2, 1f # done if vBB == vCC (ordered) - .if $gt_bias - cmp.lt.s f2, f0, f1 - li a0, -1 - bc1nez f2, 1f # done if vBB < vCC (ordered) - li a0, 1 # vBB > vCC or unordered - .else - cmp.lt.s f2, f1, f0 - li a0, 1 - bc1nez f2, 1f # done if vBB > vCC (ordered) - li a0, -1 # vBB < vCC or unordered - .endif -1: - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/fcmpWide.S b/runtime/interpreter/mterp/mips64/fcmpWide.S deleted file mode 100644 index 2a3a341a3d329198ba6066325b35d0196fb811f2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/fcmpWide.S +++ /dev/null @@ -1,32 +0,0 @@ -%default {} - /* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * For: cmpl-double, cmpg-double - */ - /* op vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_DOUBLE f0, a2 # f0 <- vBB - GET_VREG_DOUBLE f1, a3 # f1 <- vCC - cmp.eq.d f2, f0, f1 - li a0, 0 - bc1nez f2, 1f # done if vBB == vCC (ordered) - .if $gt_bias - cmp.lt.d f2, f0, f1 - li a0, -1 - bc1nez f2, 1f # done if vBB < vCC (ordered) - li a0, 1 # vBB > vCC or unordered - .else - cmp.lt.d f2, f1, f0 - li a0, 1 - bc1nez f2, 1f # done if vBB > vCC (ordered) - li a0, -1 # vBB < vCC or unordered - .endif -1: - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/fcvtFooter.S b/runtime/interpreter/mterp/mips64/fcvtFooter.S deleted file mode 100644 index 06e9507817b8400d944a56f9166c153d8719aa0c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/fcvtFooter.S +++ /dev/null @@ -1,18 +0,0 @@ - /* - * Stores a specified register containing the result of conversion - * from or to a floating-point type and jumps to the next instruction. - * - * Expects a1 to contain the destination Dalvik register number. - * a1 is set up by fcvtHeader.S. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - * - * Note that this file can't be included after a break in other files - * and in those files its contents appear as a copy. - * See: float-to-int, float-to-long, double-to-int, double-to-long. - */ - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG$suffix $valreg, a1 - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/fcvtHeader.S b/runtime/interpreter/mterp/mips64/fcvtHeader.S deleted file mode 100644 index 8742e42c393d22c97fefca8c000f4b2c083845f8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/fcvtHeader.S +++ /dev/null @@ -1,15 +0,0 @@ - /* - * Loads a specified register from vB. Used primarily for conversions - * from or to a floating-point type. - * - * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to - * store the result in vA and jump to the next instruction. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - */ - ext a1, rINST, 8, 4 # a1 <- A - srl a2, rINST, 12 # a2 <- B - GET_VREG$suffix $valreg, a2 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST diff --git a/runtime/interpreter/mterp/mips64/field.S b/runtime/interpreter/mterp/mips64/field.S deleted file mode 100644 index 1333ed77b7e1ed056329cae96075dc558158ee69..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/field.S +++ /dev/null @@ -1 +0,0 @@ -TODO diff --git a/runtime/interpreter/mterp/mips64/floating_point.S b/runtime/interpreter/mterp/mips64/floating_point.S new file mode 100644 index 0000000000000000000000000000000000000000..1132a09e7c925b05c0e83ba28d9e8540137f98ba --- /dev/null +++ b/runtime/interpreter/mterp/mips64/floating_point.S @@ -0,0 +1,382 @@ +%def fbinop(instr=""): + /*: + * Generic 32-bit floating-point operation. + * + * For: add-float, sub-float, mul-float, div-float. + * form: f0, f0, f1 + */ + /* binop vAA, vBB, vCC */ + srl a4, rINST, 8 # a4 <- AA + lbu a2, 2(rPC) # a2 <- BB + lbu a3, 3(rPC) # a3 <- CC + GET_VREG_FLOAT f0, a2 # f0 <- vBB + GET_VREG_FLOAT f1, a3 # f1 <- vCC + $instr # f0 <- f0 op f1 + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG_FLOAT f0, a4 # vAA <- f0 + GOTO_OPCODE v0 # jump to next instruction + +%def fbinop2addr(instr=""): + /*: + * Generic 32-bit "/2addr" floating-point operation. + * + * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr. + * form: f0, f0, f1 + */ + /* binop/2addr vA, vB */ + ext a2, rINST, 8, 4 # a2 <- A + ext a3, rINST, 12, 4 # a3 <- B + GET_VREG_FLOAT f0, a2 # f0 <- vA + GET_VREG_FLOAT f1, a3 # f1 <- vB + $instr # f0 <- f0 op f1 + FETCH_ADVANCE_INST 1 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG_FLOAT f0, a2 # vA <- f0 + GOTO_OPCODE v0 # jump to next instruction + +%def fbinopWide(instr=""): + /*: + * Generic 64-bit floating-point operation. + * + * For: add-double, sub-double, mul-double, div-double. + * form: f0, f0, f1 + */ + /* binop vAA, vBB, vCC */ + srl a4, rINST, 8 # a4 <- AA + lbu a2, 2(rPC) # a2 <- BB + lbu a3, 3(rPC) # a3 <- CC + GET_VREG_DOUBLE f0, a2 # f0 <- vBB + GET_VREG_DOUBLE f1, a3 # f1 <- vCC + $instr # f0 <- f0 op f1 + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG_DOUBLE f0, a4 # vAA <- f0 + GOTO_OPCODE v0 # jump to next instruction + +%def fbinopWide2addr(instr=""): + /*: + * Generic 64-bit "/2addr" floating-point operation. + * + * For: add-double/2addr, sub-double/2addr, mul-double/2addr, div-double/2addr. + * form: f0, f0, f1 + */ + /* binop/2addr vA, vB */ + ext a2, rINST, 8, 4 # a2 <- A + ext a3, rINST, 12, 4 # a3 <- B + GET_VREG_DOUBLE f0, a2 # f0 <- vA + GET_VREG_DOUBLE f1, a3 # f1 <- vB + $instr # f0 <- f0 op f1 + FETCH_ADVANCE_INST 1 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG_DOUBLE f0, a2 # vA <- f0 + GOTO_OPCODE v0 # jump to next instruction + +%def fcmp(gt_bias=""): + /* + * Compare two floating-point values. Puts 0, 1, or -1 into the + * destination register based on the results of the comparison. + * + * For: cmpl-float, cmpg-float + */ + /* op vAA, vBB, vCC */ + srl a4, rINST, 8 # a4 <- AA + lbu a2, 2(rPC) # a2 <- BB + lbu a3, 3(rPC) # a3 <- CC + GET_VREG_FLOAT f0, a2 # f0 <- vBB + GET_VREG_FLOAT f1, a3 # f1 <- vCC + cmp.eq.s f2, f0, f1 + li a0, 0 + bc1nez f2, 1f # done if vBB == vCC (ordered) + .if $gt_bias + cmp.lt.s f2, f0, f1 + li a0, -1 + bc1nez f2, 1f # done if vBB < vCC (ordered) + li a0, 1 # vBB > vCC or unordered + .else + cmp.lt.s f2, f1, f0 + li a0, 1 + bc1nez f2, 1f # done if vBB > vCC (ordered) + li a0, -1 # vBB < vCC or unordered + .endif +1: + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG a0, a4 # vAA <- a0 + GOTO_OPCODE v0 # jump to next instruction + +%def fcmpWide(gt_bias=""): + /* + * Compare two floating-point values. Puts 0, 1, or -1 into the + * destination register based on the results of the comparison. + * + * For: cmpl-double, cmpg-double + */ + /* op vAA, vBB, vCC */ + srl a4, rINST, 8 # a4 <- AA + lbu a2, 2(rPC) # a2 <- BB + lbu a3, 3(rPC) # a3 <- CC + GET_VREG_DOUBLE f0, a2 # f0 <- vBB + GET_VREG_DOUBLE f1, a3 # f1 <- vCC + cmp.eq.d f2, f0, f1 + li a0, 0 + bc1nez f2, 1f # done if vBB == vCC (ordered) + .if $gt_bias + cmp.lt.d f2, f0, f1 + li a0, -1 + bc1nez f2, 1f # done if vBB < vCC (ordered) + li a0, 1 # vBB > vCC or unordered + .else + cmp.lt.d f2, f1, f0 + li a0, 1 + bc1nez f2, 1f # done if vBB > vCC (ordered) + li a0, -1 # vBB < vCC or unordered + .endif +1: + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG a0, a4 # vAA <- a0 + GOTO_OPCODE v0 # jump to next instruction + +%def fcvtFooter(suffix="", valreg=""): + /* + * Stores a specified register containing the result of conversion + * from or to a floating-point type and jumps to the next instruction. + * + * Expects a1 to contain the destination Dalvik register number. + * a1 is set up by fcvtHeader.S. + * + * For: int-to-float, int-to-double, long-to-float, long-to-double, + * float-to-int, float-to-long, float-to-double, double-to-int, + * double-to-long, double-to-float, neg-float, neg-double. + * + * Note that this file can't be included after a break in other files + * and in those files its contents appear as a copy. + * See: float-to-int, float-to-long, double-to-int, double-to-long. + */ + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG$suffix $valreg, a1 + GOTO_OPCODE v0 # jump to next instruction + +%def fcvtHeader(suffix="", valreg=""): + /* + * Loads a specified register from vB. Used primarily for conversions + * from or to a floating-point type. + * + * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to + * store the result in vA and jump to the next instruction. + * + * For: int-to-float, int-to-double, long-to-float, long-to-double, + * float-to-int, float-to-long, float-to-double, double-to-int, + * double-to-long, double-to-float, neg-float, neg-double. + */ + ext a1, rINST, 8, 4 # a1 <- A + srl a2, rINST, 12 # a2 <- B + GET_VREG$suffix $valreg, a2 + FETCH_ADVANCE_INST 1 # advance rPC, load rINST + +%def op_add_double(): +% fbinopWide(instr="add.d f0, f0, f1") + +%def op_add_double_2addr(): +% fbinopWide2addr(instr="add.d f0, f0, f1") + +%def op_add_float(): +% fbinop(instr="add.s f0, f0, f1") + +%def op_add_float_2addr(): +% fbinop2addr(instr="add.s f0, f0, f1") + +%def op_cmpg_double(): +% fcmpWide(gt_bias="1") + +%def op_cmpg_float(): +% fcmp(gt_bias="1") + +%def op_cmpl_double(): +% fcmpWide(gt_bias="0") + +%def op_cmpl_float(): +% fcmp(gt_bias="0") + +%def op_div_double(): +% fbinopWide(instr="div.d f0, f0, f1") + +%def op_div_double_2addr(): +% fbinopWide2addr(instr="div.d f0, f0, f1") + +%def op_div_float(): +% fbinop(instr="div.s f0, f0, f1") + +%def op_div_float_2addr(): +% fbinop2addr(instr="div.s f0, f0, f1") + +%def op_double_to_float(): + /* + * Conversion from or to floating-point happens in a floating-point register. + * Therefore we load the input and store the output into or from a + * floating-point register irrespective of the type. + */ +% fcvtHeader(suffix="_DOUBLE", valreg="f0") + cvt.s.d f0, f0 +% fcvtFooter(suffix="_FLOAT", valreg="f0") + +%def op_double_to_int(): +% fcvtHeader(suffix="_DOUBLE", valreg="f0") + trunc.w.d f0, f0 +% fcvtFooter(suffix="_FLOAT", valreg="f0") + +%def op_double_to_long(): +% fcvtHeader(suffix="_DOUBLE", valreg="f0") + trunc.l.d f0, f0 +% fcvtFooter(suffix="_DOUBLE", valreg="f0") + +%def op_float_to_double(): + /* + * Conversion from or to floating-point happens in a floating-point register. + * Therefore we load the input and store the output into or from a + * floating-point register irrespective of the type. + */ +% fcvtHeader(suffix="_FLOAT", valreg="f0") + cvt.d.s f0, f0 +% fcvtFooter(suffix="_DOUBLE", valreg="f0") + +%def op_float_to_int(): +% fcvtHeader(suffix="_FLOAT", valreg="f0") + trunc.w.s f0, f0 +% fcvtFooter(suffix="_FLOAT", valreg="f0") + +%def op_float_to_long(): +% fcvtHeader(suffix="_FLOAT", valreg="f0") + trunc.l.s f0, f0 +% fcvtFooter(suffix="_DOUBLE", valreg="f0") + +%def op_int_to_double(): + /* + * Conversion from or to floating-point happens in a floating-point register. + * Therefore we load the input and store the output into or from a + * floating-point register irrespective of the type. + */ +% fcvtHeader(suffix="_FLOAT", valreg="f0") + cvt.d.w f0, f0 +% fcvtFooter(suffix="_DOUBLE", valreg="f0") + +%def op_int_to_float(): + /* + * Conversion from or to floating-point happens in a floating-point register. + * Therefore we load the input and store the output into or from a + * floating-point register irrespective of the type. + */ +% fcvtHeader(suffix="_FLOAT", valreg="f0") + cvt.s.w f0, f0 +% fcvtFooter(suffix="_FLOAT", valreg="f0") + +%def op_long_to_double(): + /* + * Conversion from or to floating-point happens in a floating-point register. + * Therefore we load the input and store the output into or from a + * floating-point register irrespective of the type. + */ +% fcvtHeader(suffix="_DOUBLE", valreg="f0") + cvt.d.l f0, f0 +% fcvtFooter(suffix="_DOUBLE", valreg="f0") + +%def op_long_to_float(): + /* + * Conversion from or to floating-point happens in a floating-point register. + * Therefore we load the input and store the output into or from a + * floating-point register irrespective of the type. + */ +% fcvtHeader(suffix="_DOUBLE", valreg="f0") + cvt.s.l f0, f0 +% fcvtFooter(suffix="_FLOAT", valreg="f0") + +%def op_mul_double(): +% fbinopWide(instr="mul.d f0, f0, f1") + +%def op_mul_double_2addr(): +% fbinopWide2addr(instr="mul.d f0, f0, f1") + +%def op_mul_float(): +% fbinop(instr="mul.s f0, f0, f1") + +%def op_mul_float_2addr(): +% fbinop2addr(instr="mul.s f0, f0, f1") + +%def op_neg_double(): +% fcvtHeader(suffix="_DOUBLE", valreg="f0") + neg.d f0, f0 +% fcvtFooter(suffix="_DOUBLE", valreg="f0") + +%def op_neg_float(): +% fcvtHeader(suffix="_FLOAT", valreg="f0") + neg.s f0, f0 +% fcvtFooter(suffix="_FLOAT", valreg="f0") + +%def op_rem_double(): + /* rem-double vAA, vBB, vCC */ + .extern fmod + lbu a2, 2(rPC) # a2 <- BB + lbu a3, 3(rPC) # a3 <- CC + GET_VREG_DOUBLE f12, a2 # f12 <- vBB + GET_VREG_DOUBLE f13, a3 # f13 <- vCC + jal fmod # f0 <- f12 op f13 + srl a4, rINST, 8 # a4 <- AA + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG_DOUBLE f0, a4 # vAA <- f0 + GOTO_OPCODE v0 # jump to next instruction + +%def op_rem_double_2addr(): + /* rem-double/2addr vA, vB */ + .extern fmod + ext a2, rINST, 8, 4 # a2 <- A + ext a3, rINST, 12, 4 # a3 <- B + GET_VREG_DOUBLE f12, a2 # f12 <- vA + GET_VREG_DOUBLE f13, a3 # f13 <- vB + jal fmod # f0 <- f12 op f13 + ext a2, rINST, 8, 4 # a2 <- A + FETCH_ADVANCE_INST 1 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG_DOUBLE f0, a2 # vA <- f0 + GOTO_OPCODE v0 # jump to next instruction + +%def op_rem_float(): + /* rem-float vAA, vBB, vCC */ + .extern fmodf + lbu a2, 2(rPC) # a2 <- BB + lbu a3, 3(rPC) # a3 <- CC + GET_VREG_FLOAT f12, a2 # f12 <- vBB + GET_VREG_FLOAT f13, a3 # f13 <- vCC + jal fmodf # f0 <- f12 op f13 + srl a4, rINST, 8 # a4 <- AA + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG_FLOAT f0, a4 # vAA <- f0 + GOTO_OPCODE v0 # jump to next instruction + +%def op_rem_float_2addr(): + /* rem-float/2addr vA, vB */ + .extern fmodf + ext a2, rINST, 8, 4 # a2 <- A + ext a3, rINST, 12, 4 # a3 <- B + GET_VREG_FLOAT f12, a2 # f12 <- vA + GET_VREG_FLOAT f13, a3 # f13 <- vB + jal fmodf # f0 <- f12 op f13 + ext a2, rINST, 8, 4 # a2 <- A + FETCH_ADVANCE_INST 1 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG_FLOAT f0, a2 # vA <- f0 + GOTO_OPCODE v0 # jump to next instruction + +%def op_sub_double(): +% fbinopWide(instr="sub.d f0, f0, f1") + +%def op_sub_double_2addr(): +% fbinopWide2addr(instr="sub.d f0, f0, f1") + +%def op_sub_float(): +% fbinop(instr="sub.s f0, f0, f1") + +%def op_sub_float_2addr(): +% fbinop2addr(instr="sub.s f0, f0, f1") diff --git a/runtime/interpreter/mterp/mips64/footer.S b/runtime/interpreter/mterp/mips64/footer.S deleted file mode 100644 index 779b1fb88fa42dd4544778614bf6c89ccdb61ded..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/footer.S +++ /dev/null @@ -1,276 +0,0 @@ -/* - * We've detected a condition that will result in an exception, but the exception - * has not yet been thrown. Just bail out to the reference interpreter to deal with it. - * TUNING: for consistency, we may want to just go ahead and handle these here. - */ - - .extern MterpLogDivideByZeroException -common_errDivideByZero: - EXPORT_PC -#if MTERP_LOGGING - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - jal MterpLogDivideByZeroException -#endif - b MterpCommonFallback - - .extern MterpLogArrayIndexException -common_errArrayIndex: - EXPORT_PC -#if MTERP_LOGGING - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - jal MterpLogArrayIndexException -#endif - b MterpCommonFallback - - .extern MterpLogNullObjectException -common_errNullObject: - EXPORT_PC -#if MTERP_LOGGING - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - jal MterpLogNullObjectException -#endif - b MterpCommonFallback - -/* - * If we're here, something is out of the ordinary. If there is a pending - * exception, handle it. Otherwise, roll back and retry with the reference - * interpreter. - */ -MterpPossibleException: - ld a0, THREAD_EXCEPTION_OFFSET(rSELF) - beqzc a0, MterpFallback # If not, fall back to reference interpreter. - /* intentional fallthrough - handle pending exception. */ -/* - * On return from a runtime helper routine, we've found a pending exception. - * Can we handle it here - or need to bail out to caller? - * - */ - .extern MterpHandleException - .extern MterpShouldSwitchInterpreters -MterpException: - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - jal MterpHandleException # (self, shadow_frame) - beqzc v0, MterpExceptionReturn # no local catch, back to caller. - ld a0, OFF_FP_DEX_INSTRUCTIONS(rFP) - lwu a1, OFF_FP_DEX_PC(rFP) - REFRESH_IBASE - dlsa rPC, a1, a0, 1 # generate new dex_pc_ptr - /* Do we need to switch interpreters? */ - jal MterpShouldSwitchInterpreters - bnezc v0, MterpFallback - /* resume execution at catch block */ - EXPORT_PC - FETCH_INST - GET_INST_OPCODE v0 - GOTO_OPCODE v0 - /* NOTE: no fallthrough */ - -/* - * Common handling for branches with support for Jit profiling. - * On entry: - * rINST <= signed offset - * rPROFILE <= signed hotness countdown (expanded to 64 bits) - * - * We have quite a few different cases for branch profiling, OSR detection and - * suspend check support here. - * - * Taken backward branches: - * If profiling active, do hotness countdown and report if we hit zero. - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * Is there a pending suspend request? If so, suspend. - * - * Taken forward branches and not-taken backward branches: - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * - * Our most common case is expected to be a taken backward branch with active jit profiling, - * but no full OSR check and no pending suspend request. - * Next most common case is not-taken branch with no full OSR check. - * - */ -MterpCommonTakenBranchNoFlags: - bgtzc rINST, .L_forward_branch # don't add forward branches to hotness -/* - * We need to subtract 1 from positive values and we should not see 0 here, - * so we may use the result of the comparison with -1. - */ - li v0, JIT_CHECK_OSR - beqc rPROFILE, v0, .L_osr_check - bltc rPROFILE, v0, .L_resume_backward_branch - dsubu rPROFILE, 1 - beqzc rPROFILE, .L_add_batch # counted down to zero - report -.L_resume_backward_branch: - lw ra, THREAD_FLAGS_OFFSET(rSELF) - REFRESH_IBASE - daddu a2, rINST, rINST # a2<- byte offset - FETCH_ADVANCE_INST_RB a2 # update rPC, load rINST - and ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - bnezc ra, .L_suspend_request_pending - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -.L_suspend_request_pending: - EXPORT_PC - move a0, rSELF - jal MterpSuspendCheck # (self) - bnezc v0, MterpFallback - REFRESH_IBASE # might have changed during suspend - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -.L_no_count_backwards: - li v0, JIT_CHECK_OSR # check for possible OSR re-entry - bnec rPROFILE, v0, .L_resume_backward_branch -.L_osr_check: - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rINST - EXPORT_PC - jal MterpMaybeDoOnStackReplacement # (self, shadow_frame, offset) - bnezc v0, MterpOnStackReplacement - b .L_resume_backward_branch - -.L_forward_branch: - li v0, JIT_CHECK_OSR # check for possible OSR re-entry - beqc rPROFILE, v0, .L_check_osr_forward -.L_resume_forward_branch: - daddu a2, rINST, rINST # a2<- byte offset - FETCH_ADVANCE_INST_RB a2 # update rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -.L_check_osr_forward: - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rINST - EXPORT_PC - jal MterpMaybeDoOnStackReplacement # (self, shadow_frame, offset) - bnezc v0, MterpOnStackReplacement - b .L_resume_forward_branch - -.L_add_batch: - daddu a1, rFP, OFF_FP_SHADOWFRAME - sh rPROFILE, SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET(a1) - ld a0, OFF_FP_METHOD(rFP) - move a2, rSELF - jal MterpAddHotnessBatch # (method, shadow_frame, self) - move rPROFILE, v0 # restore new hotness countdown to rPROFILE - b .L_no_count_backwards - -/* - * Entered from the conditional branch handlers when OSR check request active on - * not-taken path. All Dalvik not-taken conditional branch offsets are 2. - */ -.L_check_not_taken_osr: - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - li a2, 2 - EXPORT_PC - jal MterpMaybeDoOnStackReplacement # (self, shadow_frame, offset) - bnezc v0, MterpOnStackReplacement - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* - * On-stack replacement has happened, and now we've returned from the compiled method. - */ -MterpOnStackReplacement: -#if MTERP_LOGGING - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rINST # rINST contains offset - jal MterpLogOSR -#endif - li v0, 1 # Signal normal return - b MterpDone - -/* - * Bail out to reference interpreter. - */ - .extern MterpLogFallback -MterpFallback: - EXPORT_PC -#if MTERP_LOGGING - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - jal MterpLogFallback -#endif -MterpCommonFallback: - li v0, 0 # signal retry with reference interpreter. - b MterpDone - -/* - * We pushed some registers on the stack in ExecuteMterpImpl, then saved - * SP and RA. Here we restore SP, restore the registers, and then restore - * RA to PC. - * - * On entry: - * uint32_t* rFP (should still be live, pointer to base of vregs) - */ -MterpExceptionReturn: - li v0, 1 # signal return to caller. - b MterpDone -/* - * Returned value is expected in a0 and if it's not 64-bit, the 32 most - * significant bits of a0 must be zero-extended or sign-extended - * depending on the return type. - */ -MterpReturn: - ld a2, OFF_FP_RESULT_REGISTER(rFP) - sd a0, 0(a2) - li v0, 1 # signal return to caller. -MterpDone: -/* - * At this point, we expect rPROFILE to be non-zero. If negative, hotness is disabled or we're - * checking for OSR. If greater than zero, we might have unreported hotness to register - * (the difference between the ending rPROFILE and the cached hotness counter). rPROFILE - * should only reach zero immediately after a hotness decrement, and is then reset to either - * a negative special state or the new non-zero countdown value. - */ - blez rPROFILE, .L_pop_and_return # if > 0, we may have some counts to report. - -MterpProfileActive: - move rINST, v0 # stash return value - /* Report cached hotness counts */ - ld a0, OFF_FP_METHOD(rFP) - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rSELF - sh rPROFILE, SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET(a1) - jal MterpAddHotnessBatch # (method, shadow_frame, self) - move v0, rINST # restore return value - -.L_pop_and_return: - ld s6, STACK_OFFSET_S6(sp) - .cfi_restore 22 - ld s5, STACK_OFFSET_S5(sp) - .cfi_restore 21 - ld s4, STACK_OFFSET_S4(sp) - .cfi_restore 20 - ld s3, STACK_OFFSET_S3(sp) - .cfi_restore 19 - ld s2, STACK_OFFSET_S2(sp) - .cfi_restore 18 - ld s1, STACK_OFFSET_S1(sp) - .cfi_restore 17 - ld s0, STACK_OFFSET_S0(sp) - .cfi_restore 16 - - ld ra, STACK_OFFSET_RA(sp) - .cfi_restore 31 - - ld t8, STACK_OFFSET_GP(sp) - .cpreturn - .cfi_restore 28 - - .set noreorder - jr ra - daddu sp, sp, STACK_SIZE - .cfi_adjust_cfa_offset -STACK_SIZE - - .cfi_endproc - .set reorder - .size ExecuteMterpImpl, .-ExecuteMterpImpl diff --git a/runtime/interpreter/mterp/mips64/header.S b/runtime/interpreter/mterp/mips64/header.S deleted file mode 100644 index 7e1446c0c62cc199b4c4161dd8f7202d37b2a0a3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/header.S +++ /dev/null @@ -1,328 +0,0 @@ -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#define zero $$0 /* always zero */ -#define AT $$at /* assembler temp */ -#define v0 $$2 /* return value */ -#define v1 $$3 -#define a0 $$4 /* argument registers */ -#define a1 $$5 -#define a2 $$6 -#define a3 $$7 -#define a4 $$8 /* expanded register arguments */ -#define a5 $$9 -#define a6 $$10 -#define a7 $$11 -#define ta0 $$8 /* alias */ -#define ta1 $$9 -#define ta2 $$10 -#define ta3 $$11 -#define t0 $$12 /* temp registers (not saved across subroutine calls) */ -#define t1 $$13 -#define t2 $$14 -#define t3 $$15 - -#define s0 $$16 /* saved across subroutine calls (callee saved) */ -#define s1 $$17 -#define s2 $$18 -#define s3 $$19 -#define s4 $$20 -#define s5 $$21 -#define s6 $$22 -#define s7 $$23 -#define t8 $$24 /* two more temp registers */ -#define t9 $$25 -#define k0 $$26 /* kernel temporary */ -#define k1 $$27 -#define gp $$28 /* global pointer */ -#define sp $$29 /* stack pointer */ -#define s8 $$30 /* one more callee saved */ -#define ra $$31 /* return address */ - -#define f0 $$f0 -#define f1 $$f1 -#define f2 $$f2 -#define f3 $$f3 -#define f12 $$f12 -#define f13 $$f13 - -/* - * It looks like the GNU assembler currently does not support the blec and bgtc - * idioms, which should translate into bgec and bltc respectively with swapped - * left and right register operands. - * TODO: remove these macros when the assembler is fixed. - */ -.macro blec lreg, rreg, target - bgec \rreg, \lreg, \target -.endm -.macro bgtc lreg, rreg, target - bltc \rreg, \lreg, \target -.endm - -/* -Mterp and MIPS64 notes: - -The following registers have fixed assignments: - - reg nick purpose - s0 rPC interpreted program counter, used for fetching instructions - s1 rFP interpreted frame pointer, used for accessing locals and args - s2 rSELF self (Thread) pointer - s3 rINST first 16-bit code unit of current instruction - s4 rIBASE interpreted instruction base pointer, used for computed goto - s5 rREFS base of object references in shadow frame (ideally, we'll get rid of this later). - s6 rPROFILE jit profile hotness countdown -*/ - -/* During bringup, we'll use the shadow frame model instead of rFP */ -/* single-purpose registers, given names for clarity */ -#define rPC s0 -#define CFI_DEX 16 // DWARF register number of the register holding dex-pc (s0). -#define CFI_TMP 4 // DWARF register number of the first argument register (a0). -#define rFP s1 -#define rSELF s2 -#define rINST s3 -#define rIBASE s4 -#define rREFS s5 -#define rPROFILE s6 - -/* - * This is a #include, not a %include, because we want the C pre-processor - * to expand the macros into assembler assignment statements. - */ -#include "asm_support.h" -#include "interpreter/cfi_asm_support.h" - -/* - * Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs. So, - * to access other shadow frame fields, we need to use a backwards offset. Define those here. - */ -#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) -#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) -#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) -#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) -#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) -#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) -#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) -#define OFF_FP_DEX_INSTRUCTIONS OFF_FP(SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET) -#define OFF_FP_SHADOWFRAME OFF_FP(0) - -#define MTERP_PROFILE_BRANCHES 1 -#define MTERP_LOGGING 0 - -/* - * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must - * be done *before* something throws. - * - * It's okay to do this more than once. - * - * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped - * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction - * offset into the code_items_[] array. For effiency, we will "export" the - * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC - * to convert to a dex pc when needed. - */ -.macro EXPORT_PC - sd rPC, OFF_FP_DEX_PC_PTR(rFP) -.endm - -/* - * Refresh handler table. - */ -.macro REFRESH_IBASE - ld rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) -.endm - -/* - * Fetch the next instruction from rPC into rINST. Does not advance rPC. - */ -.macro FETCH_INST - lhu rINST, 0(rPC) -.endm - -/* Advance rPC by some number of code units. */ -.macro ADVANCE count - daddu rPC, rPC, (\count) * 2 -.endm - -/* - * Fetch the next instruction from an offset specified by _reg and advance xPC. - * xPC to point to the next instruction. "_reg" must specify the distance - * in bytes, *not* 16-bit code units, and may be a signed value. Must not set flags. - * - */ -.macro FETCH_ADVANCE_INST_RB reg - daddu rPC, rPC, \reg - FETCH_INST -.endm - -/* - * Fetch the next instruction from the specified offset. Advances rPC - * to point to the next instruction. - * - * This must come AFTER anything that can throw an exception, or the - * exception catch may miss. (This also implies that it must come after - * EXPORT_PC.) - */ -.macro FETCH_ADVANCE_INST count - ADVANCE \count - FETCH_INST -.endm - -/* - * Similar to FETCH_ADVANCE_INST, but does not update rPC. Used to load - * rINST ahead of possible exception point. Be sure to manually advance rPC - * later. - */ -.macro PREFETCH_INST count - lhu rINST, ((\count) * 2)(rPC) -.endm - -/* - * Put the instruction's opcode field into the specified register. - */ -.macro GET_INST_OPCODE reg - and \reg, rINST, 255 -.endm - -/* - * Begin executing the opcode in _reg. - */ -.macro GOTO_OPCODE reg - .set noat - sll AT, \reg, 7 - daddu AT, rIBASE, AT - jic AT, 0 - .set at -.endm - -/* - * Get/set the 32-bit value from a Dalvik register. - * Note, GET_VREG does sign extension to 64 bits while - * GET_VREG_U does zero extension to 64 bits. - * One is useful for arithmetic while the other is - * useful for storing the result value as 64-bit. - */ -.macro GET_VREG reg, vreg - .set noat - dlsa AT, \vreg, rFP, 2 - lw \reg, 0(AT) - .set at -.endm -.macro GET_VREG_U reg, vreg - .set noat - dlsa AT, \vreg, rFP, 2 - lwu \reg, 0(AT) - .set at -.endm -.macro GET_VREG_FLOAT reg, vreg - .set noat - dlsa AT, \vreg, rFP, 2 - lwc1 \reg, 0(AT) - .set at -.endm -.macro SET_VREG reg, vreg - .set noat - dlsa AT, \vreg, rFP, 2 - sw \reg, 0(AT) - dlsa AT, \vreg, rREFS, 2 - sw zero, 0(AT) - .set at -.endm -.macro SET_VREG_OBJECT reg, vreg - .set noat - dlsa AT, \vreg, rFP, 2 - sw \reg, 0(AT) - dlsa AT, \vreg, rREFS, 2 - sw \reg, 0(AT) - .set at -.endm -.macro SET_VREG_FLOAT reg, vreg - .set noat - dlsa AT, \vreg, rFP, 2 - swc1 \reg, 0(AT) - dlsa AT, \vreg, rREFS, 2 - sw zero, 0(AT) - .set at -.endm - -/* - * Get/set the 64-bit value from a Dalvik register. - * Avoid unaligned memory accesses. - * Note, SET_VREG_WIDE clobbers the register containing the value being stored. - * Note, SET_VREG_DOUBLE clobbers the register containing the Dalvik register number. - */ -.macro GET_VREG_WIDE reg, vreg - .set noat - dlsa AT, \vreg, rFP, 2 - lw \reg, 0(AT) - lw AT, 4(AT) - dinsu \reg, AT, 32, 32 - .set at -.endm -.macro GET_VREG_DOUBLE reg, vreg - .set noat - dlsa AT, \vreg, rFP, 2 - lwc1 \reg, 0(AT) - lw AT, 4(AT) - mthc1 AT, \reg - .set at -.endm -.macro SET_VREG_WIDE reg, vreg - .set noat - dlsa AT, \vreg, rFP, 2 - sw \reg, 0(AT) - drotr32 \reg, \reg, 0 - sw \reg, 4(AT) - dlsa AT, \vreg, rREFS, 2 - sw zero, 0(AT) - sw zero, 4(AT) - .set at -.endm -.macro SET_VREG_DOUBLE reg, vreg - .set noat - dlsa AT, \vreg, rREFS, 2 - sw zero, 0(AT) - sw zero, 4(AT) - dlsa AT, \vreg, rFP, 2 - swc1 \reg, 0(AT) - mfhc1 \vreg, \reg - sw \vreg, 4(AT) - .set at -.endm - -/* - * On-stack offsets for spilling/unspilling callee-saved registers - * and the frame size. - */ -#define STACK_OFFSET_RA 0 -#define STACK_OFFSET_GP 8 -#define STACK_OFFSET_S0 16 -#define STACK_OFFSET_S1 24 -#define STACK_OFFSET_S2 32 -#define STACK_OFFSET_S3 40 -#define STACK_OFFSET_S4 48 -#define STACK_OFFSET_S5 56 -#define STACK_OFFSET_S6 64 -#define STACK_SIZE 80 /* needs 16 byte alignment */ - -/* Constants for float/double_to_int/long conversions */ -#define INT_MIN 0x80000000 -#define INT_MIN_AS_FLOAT 0xCF000000 -#define INT_MIN_AS_DOUBLE 0xC1E0000000000000 -#define LONG_MIN 0x8000000000000000 -#define LONG_MIN_AS_FLOAT 0xDF000000 -#define LONG_MIN_AS_DOUBLE 0xC3E0000000000000 diff --git a/runtime/interpreter/mterp/mips64/instruction_end.S b/runtime/interpreter/mterp/mips64/instruction_end.S deleted file mode 100644 index 32c725c7d9655633fcd95e67023080ff36bdc515..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/instruction_end.S +++ /dev/null @@ -1,3 +0,0 @@ - - .global artMterpAsmInstructionEnd -artMterpAsmInstructionEnd: diff --git a/runtime/interpreter/mterp/mips64/instruction_end_alt.S b/runtime/interpreter/mterp/mips64/instruction_end_alt.S deleted file mode 100644 index f90916fc02cda411d0a0c9c40c77bb3c6848793c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/instruction_end_alt.S +++ /dev/null @@ -1,3 +0,0 @@ - - .global artMterpAsmAltInstructionEnd -artMterpAsmAltInstructionEnd: diff --git a/runtime/interpreter/mterp/mips64/instruction_end_sister.S b/runtime/interpreter/mterp/mips64/instruction_end_sister.S deleted file mode 100644 index c5f4886697bb135e2a6a8bd74cf2fb7df2e5fab0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/instruction_end_sister.S +++ /dev/null @@ -1,3 +0,0 @@ - - .global artMterpAsmSisterEnd -artMterpAsmSisterEnd: diff --git a/runtime/interpreter/mterp/mips64/instruction_start.S b/runtime/interpreter/mterp/mips64/instruction_start.S deleted file mode 100644 index 8874c205404d9f5012a99d67dfd2ef472160d109..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/instruction_start.S +++ /dev/null @@ -1,4 +0,0 @@ - - .global artMterpAsmInstructionStart -artMterpAsmInstructionStart = .L_op_nop - .text diff --git a/runtime/interpreter/mterp/mips64/instruction_start_alt.S b/runtime/interpreter/mterp/mips64/instruction_start_alt.S deleted file mode 100644 index 0c9ffdb7d6c01b8470682ee5715d27a475517e5b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/instruction_start_alt.S +++ /dev/null @@ -1,4 +0,0 @@ - - .global artMterpAsmAltInstructionStart -artMterpAsmAltInstructionStart = .L_ALT_op_nop - .text diff --git a/runtime/interpreter/mterp/mips64/instruction_start_sister.S b/runtime/interpreter/mterp/mips64/instruction_start_sister.S deleted file mode 100644 index 2ec51f7261de40fd2ad0d3ba9ed6826bf532d43e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/instruction_start_sister.S +++ /dev/null @@ -1,5 +0,0 @@ - - .global artMterpAsmSisterStart - .text - .balign 4 -artMterpAsmSisterStart: diff --git a/runtime/interpreter/mterp/mips64/invoke.S b/runtime/interpreter/mterp/mips64/invoke.S index be647b618ba946b1c5c3d5189ae584d9d3711859..c2967cfa17f68c4e16b44fd012903ca08d10743b 100644 --- a/runtime/interpreter/mterp/mips64/invoke.S +++ b/runtime/interpreter/mterp/mips64/invoke.S @@ -1,4 +1,4 @@ -%default { "helper":"UndefinedInvokeHandler" } +%def invoke(helper="UndefinedInvokeHandler"): /* * Generic invoke handler wrapper. */ @@ -18,3 +18,93 @@ bnezc v0, MterpFallback GET_INST_OPCODE v0 GOTO_OPCODE v0 + +%def invoke_polymorphic(helper="UndefinedInvokeHandler"): + /* + * invoke-polymorphic handler wrapper. + */ + /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ + /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ + .extern $helper + .extern MterpShouldSwitchInterpreters + EXPORT_PC + move a0, rSELF + daddu a1, rFP, OFF_FP_SHADOWFRAME + move a2, rPC + move a3, rINST + jal $helper + beqzc v0, MterpException + FETCH_ADVANCE_INST 4 + jal MterpShouldSwitchInterpreters + bnezc v0, MterpFallback + GET_INST_OPCODE v0 + GOTO_OPCODE v0 + +%def op_invoke_custom(): +% invoke(helper="MterpInvokeCustom") + +%def op_invoke_custom_range(): +% invoke(helper="MterpInvokeCustomRange") + +%def op_invoke_direct(): +% invoke(helper="MterpInvokeDirect") + +%def op_invoke_direct_range(): +% invoke(helper="MterpInvokeDirectRange") + +%def op_invoke_interface(): +% invoke(helper="MterpInvokeInterface") + /* + * Handle an interface method call. + * + * for: invoke-interface, invoke-interface/range + */ + /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ + /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ + +%def op_invoke_interface_range(): +% invoke(helper="MterpInvokeInterfaceRange") + +%def op_invoke_polymorphic(): +% invoke_polymorphic(helper="MterpInvokePolymorphic") + +%def op_invoke_polymorphic_range(): +% invoke_polymorphic(helper="MterpInvokePolymorphicRange") + +%def op_invoke_static(): +% invoke(helper="MterpInvokeStatic") + +%def op_invoke_static_range(): +% invoke(helper="MterpInvokeStaticRange") + +%def op_invoke_super(): +% invoke(helper="MterpInvokeSuper") + /* + * Handle a "super" method call. + * + * for: invoke-super, invoke-super/range + */ + /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ + /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ + +%def op_invoke_super_range(): +% invoke(helper="MterpInvokeSuperRange") + +%def op_invoke_virtual(): +% invoke(helper="MterpInvokeVirtual") + /* + * Handle a virtual method call. + * + * for: invoke-virtual, invoke-virtual/range + */ + /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ + /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ + +%def op_invoke_virtual_quick(): +% invoke(helper="MterpInvokeVirtualQuick") + +%def op_invoke_virtual_range(): +% invoke(helper="MterpInvokeVirtualRange") + +%def op_invoke_virtual_range_quick(): +% invoke(helper="MterpInvokeVirtualQuickRange") diff --git a/runtime/interpreter/mterp/mips64/invoke_polymorphic.S b/runtime/interpreter/mterp/mips64/invoke_polymorphic.S deleted file mode 100644 index fa82083276a41f5fec1425426094b2d01b423a81..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/invoke_polymorphic.S +++ /dev/null @@ -1,20 +0,0 @@ -%default { "helper":"UndefinedInvokeHandler" } - /* - * invoke-polymorphic handler wrapper. - */ - /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ - .extern $helper - .extern MterpShouldSwitchInterpreters - EXPORT_PC - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - jal $helper - beqzc v0, MterpException - FETCH_ADVANCE_INST 4 - jal MterpShouldSwitchInterpreters - bnezc v0, MterpFallback - GET_INST_OPCODE v0 - GOTO_OPCODE v0 diff --git a/runtime/interpreter/mterp/mips64/main.S b/runtime/interpreter/mterp/mips64/main.S new file mode 100644 index 0000000000000000000000000000000000000000..517bddfa2139580119606178113f10c5f7ea3f75 --- /dev/null +++ b/runtime/interpreter/mterp/mips64/main.S @@ -0,0 +1,748 @@ +%def header(): +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#define zero $$0 /* always zero */ +#define AT $$at /* assembler temp */ +#define v0 $$2 /* return value */ +#define v1 $$3 +#define a0 $$4 /* argument registers */ +#define a1 $$5 +#define a2 $$6 +#define a3 $$7 +#define a4 $$8 /* expanded register arguments */ +#define a5 $$9 +#define a6 $$10 +#define a7 $$11 +#define ta0 $$8 /* alias */ +#define ta1 $$9 +#define ta2 $$10 +#define ta3 $$11 +#define t0 $$12 /* temp registers (not saved across subroutine calls) */ +#define t1 $$13 +#define t2 $$14 +#define t3 $$15 + +#define s0 $$16 /* saved across subroutine calls (callee saved) */ +#define s1 $$17 +#define s2 $$18 +#define s3 $$19 +#define s4 $$20 +#define s5 $$21 +#define s6 $$22 +#define s7 $$23 +#define t8 $$24 /* two more temp registers */ +#define t9 $$25 +#define k0 $$26 /* kernel temporary */ +#define k1 $$27 +#define gp $$28 /* global pointer */ +#define sp $$29 /* stack pointer */ +#define s8 $$30 /* one more callee saved */ +#define ra $$31 /* return address */ + +#define f0 $$f0 +#define f1 $$f1 +#define f2 $$f2 +#define f3 $$f3 +#define f12 $$f12 +#define f13 $$f13 + +/* + * It looks like the GNU assembler currently does not support the blec and bgtc + * idioms, which should translate into bgec and bltc respectively with swapped + * left and right register operands. + * TODO: remove these macros when the assembler is fixed. + */ +.macro blec lreg, rreg, target + bgec \rreg, \lreg, \target +.endm +.macro bgtc lreg, rreg, target + bltc \rreg, \lreg, \target +.endm + +/* +Mterp and MIPS64 notes: + +The following registers have fixed assignments: + + reg nick purpose + s0 rPC interpreted program counter, used for fetching instructions + s1 rFP interpreted frame pointer, used for accessing locals and args + s2 rSELF self (Thread) pointer + s3 rINST first 16-bit code unit of current instruction + s4 rIBASE interpreted instruction base pointer, used for computed goto + s5 rREFS base of object references in shadow frame (ideally, we'll get rid of this later). + s6 rPROFILE jit profile hotness countdown +*/ + +/* During bringup, we'll use the shadow frame model instead of rFP */ +/* single-purpose registers, given names for clarity */ +#define rPC s0 +#define CFI_DEX 16 // DWARF register number of the register holding dex-pc (s0). +#define CFI_TMP 4 // DWARF register number of the first argument register (a0). +#define rFP s1 +#define rSELF s2 +#define rINST s3 +#define rIBASE s4 +#define rREFS s5 +#define rPROFILE s6 + +/* + * This is a #include, not a %include, because we want the C pre-processor + * to expand the macros into assembler assignment statements. + */ +#include "asm_support.h" +#include "interpreter/cfi_asm_support.h" + +/* + * Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs. So, + * to access other shadow frame fields, we need to use a backwards offset. Define those here. + */ +#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) +#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) +#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) +#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) +#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) +#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) +#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) +#define OFF_FP_DEX_INSTRUCTIONS OFF_FP(SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET) +#define OFF_FP_SHADOWFRAME OFF_FP(0) + +#define MTERP_PROFILE_BRANCHES 1 +#define MTERP_LOGGING 0 + +/* + * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must + * be done *before* something throws. + * + * It's okay to do this more than once. + * + * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped + * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction + * offset into the code_items_[] array. For effiency, we will "export" the + * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC + * to convert to a dex pc when needed. + */ +.macro EXPORT_PC + sd rPC, OFF_FP_DEX_PC_PTR(rFP) +.endm + +/* + * Refresh handler table. + */ +.macro REFRESH_IBASE + ld rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) +.endm + +/* + * Fetch the next instruction from rPC into rINST. Does not advance rPC. + */ +.macro FETCH_INST + lhu rINST, 0(rPC) +.endm + +/* Advance rPC by some number of code units. */ +.macro ADVANCE count + daddu rPC, rPC, (\count) * 2 +.endm + +/* + * Fetch the next instruction from an offset specified by _reg and advance xPC. + * xPC to point to the next instruction. "_reg" must specify the distance + * in bytes, *not* 16-bit code units, and may be a signed value. Must not set flags. + * + */ +.macro FETCH_ADVANCE_INST_RB reg + daddu rPC, rPC, \reg + FETCH_INST +.endm + +/* + * Fetch the next instruction from the specified offset. Advances rPC + * to point to the next instruction. + * + * This must come AFTER anything that can throw an exception, or the + * exception catch may miss. (This also implies that it must come after + * EXPORT_PC.) + */ +.macro FETCH_ADVANCE_INST count + ADVANCE \count + FETCH_INST +.endm + +/* + * Similar to FETCH_ADVANCE_INST, but does not update rPC. Used to load + * rINST ahead of possible exception point. Be sure to manually advance rPC + * later. + */ +.macro PREFETCH_INST count + lhu rINST, ((\count) * 2)(rPC) +.endm + +/* + * Put the instruction's opcode field into the specified register. + */ +.macro GET_INST_OPCODE reg + and \reg, rINST, 255 +.endm + +/* + * Begin executing the opcode in _reg. + */ +.macro GOTO_OPCODE reg + .set noat + sll AT, \reg, 7 + daddu AT, rIBASE, AT + jic AT, 0 + .set at +.endm + +/* + * Get/set the 32-bit value from a Dalvik register. + * Note, GET_VREG does sign extension to 64 bits while + * GET_VREG_U does zero extension to 64 bits. + * One is useful for arithmetic while the other is + * useful for storing the result value as 64-bit. + */ +.macro GET_VREG reg, vreg + .set noat + dlsa AT, \vreg, rFP, 2 + lw \reg, 0(AT) + .set at +.endm +.macro GET_VREG_U reg, vreg + .set noat + dlsa AT, \vreg, rFP, 2 + lwu \reg, 0(AT) + .set at +.endm +.macro GET_VREG_FLOAT reg, vreg + .set noat + dlsa AT, \vreg, rFP, 2 + lwc1 \reg, 0(AT) + .set at +.endm +.macro SET_VREG reg, vreg + .set noat + dlsa AT, \vreg, rFP, 2 + sw \reg, 0(AT) + dlsa AT, \vreg, rREFS, 2 + sw zero, 0(AT) + .set at +.endm +.macro SET_VREG_OBJECT reg, vreg + .set noat + dlsa AT, \vreg, rFP, 2 + sw \reg, 0(AT) + dlsa AT, \vreg, rREFS, 2 + sw \reg, 0(AT) + .set at +.endm +.macro SET_VREG_FLOAT reg, vreg + .set noat + dlsa AT, \vreg, rFP, 2 + swc1 \reg, 0(AT) + dlsa AT, \vreg, rREFS, 2 + sw zero, 0(AT) + .set at +.endm + +/* + * Get/set the 64-bit value from a Dalvik register. + * Avoid unaligned memory accesses. + * Note, SET_VREG_WIDE clobbers the register containing the value being stored. + * Note, SET_VREG_DOUBLE clobbers the register containing the Dalvik register number. + */ +.macro GET_VREG_WIDE reg, vreg + .set noat + dlsa AT, \vreg, rFP, 2 + lw \reg, 0(AT) + lw AT, 4(AT) + dinsu \reg, AT, 32, 32 + .set at +.endm +.macro GET_VREG_DOUBLE reg, vreg + .set noat + dlsa AT, \vreg, rFP, 2 + lwc1 \reg, 0(AT) + lw AT, 4(AT) + mthc1 AT, \reg + .set at +.endm +.macro SET_VREG_WIDE reg, vreg + .set noat + dlsa AT, \vreg, rFP, 2 + sw \reg, 0(AT) + drotr32 \reg, \reg, 0 + sw \reg, 4(AT) + dlsa AT, \vreg, rREFS, 2 + sw zero, 0(AT) + sw zero, 4(AT) + .set at +.endm +.macro SET_VREG_DOUBLE reg, vreg + .set noat + dlsa AT, \vreg, rREFS, 2 + sw zero, 0(AT) + sw zero, 4(AT) + dlsa AT, \vreg, rFP, 2 + swc1 \reg, 0(AT) + mfhc1 \vreg, \reg + sw \vreg, 4(AT) + .set at +.endm + +/* + * On-stack offsets for spilling/unspilling callee-saved registers + * and the frame size. + */ +#define STACK_OFFSET_RA 0 +#define STACK_OFFSET_GP 8 +#define STACK_OFFSET_S0 16 +#define STACK_OFFSET_S1 24 +#define STACK_OFFSET_S2 32 +#define STACK_OFFSET_S3 40 +#define STACK_OFFSET_S4 48 +#define STACK_OFFSET_S5 56 +#define STACK_OFFSET_S6 64 +#define STACK_SIZE 80 /* needs 16 byte alignment */ + +/* Constants for float/double_to_int/long conversions */ +#define INT_MIN 0x80000000 +#define INT_MIN_AS_FLOAT 0xCF000000 +#define INT_MIN_AS_DOUBLE 0xC1E0000000000000 +#define LONG_MIN 0x8000000000000000 +#define LONG_MIN_AS_FLOAT 0xDF000000 +#define LONG_MIN_AS_DOUBLE 0xC3E0000000000000 + +%def entry(): +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Interpreter entry point. + */ + + .set reorder + + .text + .global ExecuteMterpImpl + .type ExecuteMterpImpl, %function + .balign 16 +/* + * On entry: + * a0 Thread* self + * a1 dex_instructions + * a2 ShadowFrame + * a3 JValue* result_register + * + */ +ExecuteMterpImpl: + .cfi_startproc + .cpsetup t9, t8, ExecuteMterpImpl + + .cfi_def_cfa sp, 0 + daddu sp, sp, -STACK_SIZE + .cfi_adjust_cfa_offset STACK_SIZE + + sd t8, STACK_OFFSET_GP(sp) + .cfi_rel_offset 28, STACK_OFFSET_GP + sd ra, STACK_OFFSET_RA(sp) + .cfi_rel_offset 31, STACK_OFFSET_RA + + sd s0, STACK_OFFSET_S0(sp) + .cfi_rel_offset 16, STACK_OFFSET_S0 + sd s1, STACK_OFFSET_S1(sp) + .cfi_rel_offset 17, STACK_OFFSET_S1 + sd s2, STACK_OFFSET_S2(sp) + .cfi_rel_offset 18, STACK_OFFSET_S2 + sd s3, STACK_OFFSET_S3(sp) + .cfi_rel_offset 19, STACK_OFFSET_S3 + sd s4, STACK_OFFSET_S4(sp) + .cfi_rel_offset 20, STACK_OFFSET_S4 + sd s5, STACK_OFFSET_S5(sp) + .cfi_rel_offset 21, STACK_OFFSET_S5 + sd s6, STACK_OFFSET_S6(sp) + .cfi_rel_offset 22, STACK_OFFSET_S6 + + /* Remember the return register */ + sd a3, SHADOWFRAME_RESULT_REGISTER_OFFSET(a2) + + /* Remember the dex instruction pointer */ + sd a1, SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET(a2) + + /* set up "named" registers */ + move rSELF, a0 + daddu rFP, a2, SHADOWFRAME_VREGS_OFFSET + lw v0, SHADOWFRAME_NUMBER_OF_VREGS_OFFSET(a2) + dlsa rREFS, v0, rFP, 2 + lw v0, SHADOWFRAME_DEX_PC_OFFSET(a2) + dlsa rPC, v0, a1, 1 + CFI_DEFINE_DEX_PC_WITH_OFFSET(CFI_TMP, CFI_DEX, 0) + EXPORT_PC + + /* Starting ibase */ + REFRESH_IBASE + + /* Set up for backwards branches & osr profiling */ + ld a0, OFF_FP_METHOD(rFP) + daddu a1, rFP, OFF_FP_SHADOWFRAME + move a2, rSELF + jal MterpSetUpHotnessCountdown + move rPROFILE, v0 # Starting hotness countdown to rPROFILE + + /* start executing the instruction at rPC */ + FETCH_INST + GET_INST_OPCODE v0 + GOTO_OPCODE v0 + + /* NOTE: no fallthrough */ + +%def alt_stub(): +/* + * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle + * any interesting requests and then jump to the real instruction + * handler. Note that the call to MterpCheckBefore is done as a tail call. + */ + .extern MterpCheckBefore + REFRESH_IBASE + dla ra, artMterpAsmInstructionStart + dla t9, MterpCheckBefore + move a0, rSELF + daddu a1, rFP, OFF_FP_SHADOWFRAME + move a2, rPC + daddu ra, ra, (${opnum} * 128) # Addr of primary handler. + jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. + +%def fallback(): +/* Transfer stub to alternate interpreter */ + b MterpFallback + +%def helpers(): +% pass + +%def footer(): +/* + * We've detected a condition that will result in an exception, but the exception + * has not yet been thrown. Just bail out to the reference interpreter to deal with it. + * TUNING: for consistency, we may want to just go ahead and handle these here. + */ + + .extern MterpLogDivideByZeroException +common_errDivideByZero: + EXPORT_PC +#if MTERP_LOGGING + move a0, rSELF + daddu a1, rFP, OFF_FP_SHADOWFRAME + jal MterpLogDivideByZeroException +#endif + b MterpCommonFallback + + .extern MterpLogArrayIndexException +common_errArrayIndex: + EXPORT_PC +#if MTERP_LOGGING + move a0, rSELF + daddu a1, rFP, OFF_FP_SHADOWFRAME + jal MterpLogArrayIndexException +#endif + b MterpCommonFallback + + .extern MterpLogNullObjectException +common_errNullObject: + EXPORT_PC +#if MTERP_LOGGING + move a0, rSELF + daddu a1, rFP, OFF_FP_SHADOWFRAME + jal MterpLogNullObjectException +#endif + b MterpCommonFallback + +/* + * If we're here, something is out of the ordinary. If there is a pending + * exception, handle it. Otherwise, roll back and retry with the reference + * interpreter. + */ +MterpPossibleException: + ld a0, THREAD_EXCEPTION_OFFSET(rSELF) + beqzc a0, MterpFallback # If not, fall back to reference interpreter. + /* intentional fallthrough - handle pending exception. */ +/* + * On return from a runtime helper routine, we've found a pending exception. + * Can we handle it here - or need to bail out to caller? + * + */ + .extern MterpHandleException + .extern MterpShouldSwitchInterpreters +MterpException: + move a0, rSELF + daddu a1, rFP, OFF_FP_SHADOWFRAME + jal MterpHandleException # (self, shadow_frame) + beqzc v0, MterpExceptionReturn # no local catch, back to caller. + ld a0, OFF_FP_DEX_INSTRUCTIONS(rFP) + lwu a1, OFF_FP_DEX_PC(rFP) + REFRESH_IBASE + dlsa rPC, a1, a0, 1 # generate new dex_pc_ptr + /* Do we need to switch interpreters? */ + jal MterpShouldSwitchInterpreters + bnezc v0, MterpFallback + /* resume execution at catch block */ + EXPORT_PC + FETCH_INST + GET_INST_OPCODE v0 + GOTO_OPCODE v0 + /* NOTE: no fallthrough */ + +/* + * Common handling for branches with support for Jit profiling. + * On entry: + * rINST <= signed offset + * rPROFILE <= signed hotness countdown (expanded to 64 bits) + * + * We have quite a few different cases for branch profiling, OSR detection and + * suspend check support here. + * + * Taken backward branches: + * If profiling active, do hotness countdown and report if we hit zero. + * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. + * Is there a pending suspend request? If so, suspend. + * + * Taken forward branches and not-taken backward branches: + * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. + * + * Our most common case is expected to be a taken backward branch with active jit profiling, + * but no full OSR check and no pending suspend request. + * Next most common case is not-taken branch with no full OSR check. + * + */ +MterpCommonTakenBranchNoFlags: + bgtzc rINST, .L_forward_branch # don't add forward branches to hotness +/* + * We need to subtract 1 from positive values and we should not see 0 here, + * so we may use the result of the comparison with -1. + */ + li v0, JIT_CHECK_OSR + beqc rPROFILE, v0, .L_osr_check + bltc rPROFILE, v0, .L_resume_backward_branch + dsubu rPROFILE, 1 + beqzc rPROFILE, .L_add_batch # counted down to zero - report +.L_resume_backward_branch: + lw ra, THREAD_FLAGS_OFFSET(rSELF) + REFRESH_IBASE + daddu a2, rINST, rINST # a2<- byte offset + FETCH_ADVANCE_INST_RB a2 # update rPC, load rINST + and ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST + bnezc ra, .L_suspend_request_pending + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +.L_suspend_request_pending: + EXPORT_PC + move a0, rSELF + jal MterpSuspendCheck # (self) + bnezc v0, MterpFallback + REFRESH_IBASE # might have changed during suspend + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +.L_no_count_backwards: + li v0, JIT_CHECK_OSR # check for possible OSR re-entry + bnec rPROFILE, v0, .L_resume_backward_branch +.L_osr_check: + move a0, rSELF + daddu a1, rFP, OFF_FP_SHADOWFRAME + move a2, rINST + EXPORT_PC + jal MterpMaybeDoOnStackReplacement # (self, shadow_frame, offset) + bnezc v0, MterpOnStackReplacement + b .L_resume_backward_branch + +.L_forward_branch: + li v0, JIT_CHECK_OSR # check for possible OSR re-entry + beqc rPROFILE, v0, .L_check_osr_forward +.L_resume_forward_branch: + daddu a2, rINST, rINST # a2<- byte offset + FETCH_ADVANCE_INST_RB a2 # update rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +.L_check_osr_forward: + move a0, rSELF + daddu a1, rFP, OFF_FP_SHADOWFRAME + move a2, rINST + EXPORT_PC + jal MterpMaybeDoOnStackReplacement # (self, shadow_frame, offset) + bnezc v0, MterpOnStackReplacement + b .L_resume_forward_branch + +.L_add_batch: + daddu a1, rFP, OFF_FP_SHADOWFRAME + sh rPROFILE, SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET(a1) + ld a0, OFF_FP_METHOD(rFP) + move a2, rSELF + jal MterpAddHotnessBatch # (method, shadow_frame, self) + move rPROFILE, v0 # restore new hotness countdown to rPROFILE + b .L_no_count_backwards + +/* + * Entered from the conditional branch handlers when OSR check request active on + * not-taken path. All Dalvik not-taken conditional branch offsets are 2. + */ +.L_check_not_taken_osr: + move a0, rSELF + daddu a1, rFP, OFF_FP_SHADOWFRAME + li a2, 2 + EXPORT_PC + jal MterpMaybeDoOnStackReplacement # (self, shadow_frame, offset) + bnezc v0, MterpOnStackReplacement + FETCH_ADVANCE_INST 2 + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +/* + * On-stack replacement has happened, and now we've returned from the compiled method. + */ +MterpOnStackReplacement: +#if MTERP_LOGGING + move a0, rSELF + daddu a1, rFP, OFF_FP_SHADOWFRAME + move a2, rINST # rINST contains offset + jal MterpLogOSR +#endif + li v0, 1 # Signal normal return + b MterpDone + +/* + * Bail out to reference interpreter. + */ + .extern MterpLogFallback +MterpFallback: + EXPORT_PC +#if MTERP_LOGGING + move a0, rSELF + daddu a1, rFP, OFF_FP_SHADOWFRAME + jal MterpLogFallback +#endif +MterpCommonFallback: + li v0, 0 # signal retry with reference interpreter. + b MterpDone + +/* + * We pushed some registers on the stack in ExecuteMterpImpl, then saved + * SP and RA. Here we restore SP, restore the registers, and then restore + * RA to PC. + * + * On entry: + * uint32_t* rFP (should still be live, pointer to base of vregs) + */ +MterpExceptionReturn: + li v0, 1 # signal return to caller. + b MterpDone +/* + * Returned value is expected in a0 and if it's not 64-bit, the 32 most + * significant bits of a0 must be zero-extended or sign-extended + * depending on the return type. + */ +MterpReturn: + ld a2, OFF_FP_RESULT_REGISTER(rFP) + sd a0, 0(a2) + li v0, 1 # signal return to caller. +MterpDone: +/* + * At this point, we expect rPROFILE to be non-zero. If negative, hotness is disabled or we're + * checking for OSR. If greater than zero, we might have unreported hotness to register + * (the difference between the ending rPROFILE and the cached hotness counter). rPROFILE + * should only reach zero immediately after a hotness decrement, and is then reset to either + * a negative special state or the new non-zero countdown value. + */ + blez rPROFILE, .L_pop_and_return # if > 0, we may have some counts to report. + +MterpProfileActive: + move rINST, v0 # stash return value + /* Report cached hotness counts */ + ld a0, OFF_FP_METHOD(rFP) + daddu a1, rFP, OFF_FP_SHADOWFRAME + move a2, rSELF + sh rPROFILE, SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET(a1) + jal MterpAddHotnessBatch # (method, shadow_frame, self) + move v0, rINST # restore return value + +.L_pop_and_return: + ld s6, STACK_OFFSET_S6(sp) + .cfi_restore 22 + ld s5, STACK_OFFSET_S5(sp) + .cfi_restore 21 + ld s4, STACK_OFFSET_S4(sp) + .cfi_restore 20 + ld s3, STACK_OFFSET_S3(sp) + .cfi_restore 19 + ld s2, STACK_OFFSET_S2(sp) + .cfi_restore 18 + ld s1, STACK_OFFSET_S1(sp) + .cfi_restore 17 + ld s0, STACK_OFFSET_S0(sp) + .cfi_restore 16 + + ld ra, STACK_OFFSET_RA(sp) + .cfi_restore 31 + + ld t8, STACK_OFFSET_GP(sp) + .cpreturn + .cfi_restore 28 + + .set noreorder + jr ra + daddu sp, sp, STACK_SIZE + .cfi_adjust_cfa_offset -STACK_SIZE + + .cfi_endproc + .set reorder + .size ExecuteMterpImpl, .-ExecuteMterpImpl + +%def instruction_end(): + + .global artMterpAsmInstructionEnd +artMterpAsmInstructionEnd: + +%def instruction_end_alt(): + + .global artMterpAsmAltInstructionEnd +artMterpAsmAltInstructionEnd: + +%def instruction_start(): + + .global artMterpAsmInstructionStart +artMterpAsmInstructionStart = .L_op_nop + .text + +%def instruction_start_alt(): + + .global artMterpAsmAltInstructionStart +artMterpAsmAltInstructionStart = .L_ALT_op_nop + .text diff --git a/runtime/interpreter/mterp/mips64/object.S b/runtime/interpreter/mterp/mips64/object.S new file mode 100644 index 0000000000000000000000000000000000000000..a5a2b3d1db85a33032e4fda69c525f2e0dc1a860 --- /dev/null +++ b/runtime/interpreter/mterp/mips64/object.S @@ -0,0 +1,262 @@ +%def field(helper=""): +TODO + +%def op_check_cast(): + /* + * Check to see if a cast from one class to another is allowed. + */ + /* check-cast vAA, class//BBBB */ + .extern MterpCheckCast + EXPORT_PC + lhu a0, 2(rPC) # a0 <- BBBB + srl a1, rINST, 8 # a1 <- AA + dlsa a1, a1, rFP, 2 # a1 <- &object + ld a2, OFF_FP_METHOD(rFP) # a2 <- method + move a3, rSELF # a3 <- self + jal MterpCheckCast # (index, &obj, method, self) + PREFETCH_INST 2 + bnez v0, MterpPossibleException + ADVANCE 2 + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +%def op_iget(is_object="0", helper="MterpIGetU32"): +% field(helper=helper) + +%def op_iget_boolean(): +% op_iget(helper="MterpIGetU8") + +%def op_iget_boolean_quick(): +% op_iget_quick(load="lbu") + +%def op_iget_byte(): +% op_iget(helper="MterpIGetI8") + +%def op_iget_byte_quick(): +% op_iget_quick(load="lb") + +%def op_iget_char(): +% op_iget(helper="MterpIGetU16") + +%def op_iget_char_quick(): +% op_iget_quick(load="lhu") + +%def op_iget_object(): +% op_iget(is_object="1", helper="MterpIGetObj") + +%def op_iget_object_quick(): + /* For: iget-object-quick */ + /* op vA, vB, offset//CCCC */ + .extern artIGetObjectFromMterp + srl a2, rINST, 12 # a2 <- B + lhu a1, 2(rPC) # a1 <- field byte offset + EXPORT_PC + GET_VREG_U a0, a2 # a0 <- object we're operating on + jal artIGetObjectFromMterp # (obj, offset) + ld a3, THREAD_EXCEPTION_OFFSET(rSELF) + ext a2, rINST, 8, 4 # a2 <- A + PREFETCH_INST 2 + bnez a3, MterpPossibleException # bail out + SET_VREG_OBJECT v0, a2 # fp[A] <- v0 + ADVANCE 2 # advance rPC + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +%def op_iget_quick(load="lw"): + /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ + /* op vA, vB, offset//CCCC */ + srl a2, rINST, 12 # a2 <- B + lhu a1, 2(rPC) # a1 <- field byte offset + GET_VREG_U a3, a2 # a3 <- object we're operating on + ext a4, rINST, 8, 4 # a4 <- A + daddu a1, a1, a3 + beqz a3, common_errNullObject # object was null + $load a0, 0(a1) # a0 <- obj.field + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + SET_VREG a0, a4 # fp[A] <- a0 + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +%def op_iget_short(): +% op_iget(helper="MterpIGetI16") + +%def op_iget_short_quick(): +% op_iget_quick(load="lh") + +%def op_iget_wide(): +% op_iget(helper="MterpIGetU64") + +%def op_iget_wide_quick(): + /* iget-wide-quick vA, vB, offset//CCCC */ + srl a2, rINST, 12 # a2 <- B + lhu a4, 2(rPC) # a4 <- field byte offset + GET_VREG_U a3, a2 # a3 <- object we're operating on + ext a2, rINST, 8, 4 # a2 <- A + beqz a3, common_errNullObject # object was null + daddu a4, a3, a4 # create direct pointer + lw a0, 0(a4) + lw a1, 4(a4) + dinsu a0, a1, 32, 32 + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + SET_VREG_WIDE a0, a2 + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +%def op_instance_of(): + /* + * Check to see if an object reference is an instance of a class. + * + * Most common situation is a non-null object, being compared against + * an already-resolved class. + */ + /* instance-of vA, vB, class//CCCC */ + .extern MterpInstanceOf + EXPORT_PC + lhu a0, 2(rPC) # a0 <- CCCC + srl a1, rINST, 12 # a1 <- B + dlsa a1, a1, rFP, 2 # a1 <- &object + ld a2, OFF_FP_METHOD(rFP) # a2 <- method + move a3, rSELF # a3 <- self + jal MterpInstanceOf # (index, &obj, method, self) + ld a1, THREAD_EXCEPTION_OFFSET(rSELF) + ext a2, rINST, 8, 4 # a2 <- A + PREFETCH_INST 2 + bnez a1, MterpException + ADVANCE 2 # advance rPC + SET_VREG v0, a2 # vA <- v0 + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +%def op_iput(is_object="0", helper="MterpIPutU32"): +% field(helper=helper) + +%def op_iput_boolean(): +% op_iput(helper="MterpIPutU8") + +%def op_iput_boolean_quick(): +% op_iput_quick(store="sb") + +%def op_iput_byte(): +% op_iput(helper="MterpIPutI8") + +%def op_iput_byte_quick(): +% op_iput_quick(store="sb") + +%def op_iput_char(): +% op_iput(helper="MterpIPutU16") + +%def op_iput_char_quick(): +% op_iput_quick(store="sh") + +%def op_iput_object(): +% op_iput(is_object="1", helper="MterpIPutObj") + +%def op_iput_object_quick(): + .extern MterpIputObjectQuick + EXPORT_PC + daddu a0, rFP, OFF_FP_SHADOWFRAME + move a1, rPC + move a2, rINST + jal MterpIputObjectQuick + beqzc v0, MterpException + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +%def op_iput_quick(store="sw"): + /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */ + /* op vA, vB, offset//CCCC */ + srl a2, rINST, 12 # a2 <- B + lhu a1, 2(rPC) # a1 <- field byte offset + GET_VREG_U a3, a2 # a3 <- fp[B], the object pointer + ext a2, rINST, 8, 4 # a2 <- A + beqz a3, common_errNullObject # object was null + GET_VREG a0, a2 # a0 <- fp[A] + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + daddu a1, a1, a3 + $store a0, 0(a1) # obj.field <- a0 + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +%def op_iput_short(): +% op_iput(helper="MterpIPutI16") + +%def op_iput_short_quick(): +% op_iput_quick(store="sh") + +%def op_iput_wide(): +% op_iput(helper="MterpIPutU64") + +%def op_iput_wide_quick(): + /* iput-wide-quick vA, vB, offset//CCCC */ + srl a2, rINST, 12 # a2 <- B + lhu a3, 2(rPC) # a3 <- field byte offset + GET_VREG_U a2, a2 # a2 <- fp[B], the object pointer + ext a0, rINST, 8, 4 # a0 <- A + beqz a2, common_errNullObject # object was null + GET_VREG_WIDE a0, a0 # a0 <- fp[A] + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + daddu a1, a2, a3 # create a direct pointer + sw a0, 0(a1) + dsrl32 a0, a0, 0 + sw a0, 4(a1) + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +%def op_new_instance(): + /* + * Create a new instance of a class. + */ + /* new-instance vAA, class//BBBB */ + .extern MterpNewInstance + EXPORT_PC + daddu a0, rFP, OFF_FP_SHADOWFRAME + move a1, rSELF + move a2, rINST + jal MterpNewInstance # (shadow_frame, self, inst_data) + beqzc v0, MterpPossibleException + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +%def op_sget(is_object="0", helper="MterpSGetU32"): +% field(helper=helper) + +%def op_sget_boolean(): +% op_sget(helper="MterpSGetU8") + +%def op_sget_byte(): +% op_sget(helper="MterpSGetI8") + +%def op_sget_char(): +% op_sget(helper="MterpSGetU16") + +%def op_sget_object(): +% op_sget(is_object="1", helper="MterpSGetObj") + +%def op_sget_short(): +% op_sget(helper="MterpSGetI16") + +%def op_sget_wide(): +% op_sget(helper="MterpSGetU64") + +%def op_sput(is_object="0", helper="MterpSPutU32"): +% field(helper=helper) + +%def op_sput_boolean(): +% op_sput(helper="MterpSPutU8") + +%def op_sput_byte(): +% op_sput(helper="MterpSPutI8") + +%def op_sput_char(): +% op_sput(helper="MterpSPutU16") + +%def op_sput_object(): +% op_sput(is_object="1", helper="MterpSPutObj") + +%def op_sput_short(): +% op_sput(helper="MterpSPutI16") + +%def op_sput_wide(): +% op_sput(helper="MterpSPutU64") diff --git a/runtime/interpreter/mterp/mips64/op_add_double.S b/runtime/interpreter/mterp/mips64/op_add_double.S deleted file mode 100644 index 1520e325f7f9a8b791a7b0eebfd45358900d2388..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_add_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/fbinopWide.S" {"instr":"add.d f0, f0, f1"} diff --git a/runtime/interpreter/mterp/mips64/op_add_double_2addr.S b/runtime/interpreter/mterp/mips64/op_add_double_2addr.S deleted file mode 100644 index c14382ef20e275e6ba2d90ed06b9d2892596c67a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_add_double_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/fbinopWide2addr.S" {"instr":"add.d f0, f0, f1"} diff --git a/runtime/interpreter/mterp/mips64/op_add_float.S b/runtime/interpreter/mterp/mips64/op_add_float.S deleted file mode 100644 index c6ed558dc3b46e8fd0a5d3b714b08709009d28a8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_add_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/fbinop.S" {"instr":"add.s f0, f0, f1"} diff --git a/runtime/interpreter/mterp/mips64/op_add_float_2addr.S b/runtime/interpreter/mterp/mips64/op_add_float_2addr.S deleted file mode 100644 index 4c20547b227d7979e9a87cc9b753c32c44234fb5..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_add_float_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/fbinop2addr.S" {"instr":"add.s f0, f0, f1"} diff --git a/runtime/interpreter/mterp/mips64/op_add_int.S b/runtime/interpreter/mterp/mips64/op_add_int.S deleted file mode 100644 index 6e569de71a5d8061cff7e809a7010647146fff63..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_add_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binop.S" {"instr":"addu a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_add_int_2addr.S b/runtime/interpreter/mterp/mips64/op_add_int_2addr.S deleted file mode 100644 index 2a84124a3a802371d2f22c7f9b8d14491f1d9e0a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_add_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binop2addr.S" {"instr":"addu a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_add_int_lit16.S b/runtime/interpreter/mterp/mips64/op_add_int_lit16.S deleted file mode 100644 index 94b053bba3b64e2ead7e4e3649e7019f512c2868..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_add_int_lit16.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binopLit16.S" {"instr":"addu a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_add_int_lit8.S b/runtime/interpreter/mterp/mips64/op_add_int_lit8.S deleted file mode 100644 index 3b6d734723c1b750b95b2ab0f91556ed37b5f1f4..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_add_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binopLit8.S" {"instr":"addu a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_add_long.S b/runtime/interpreter/mterp/mips64/op_add_long.S deleted file mode 100644 index c8d702f29fdf93ec94c7e37c1988233aa9604abf..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_add_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binopWide.S" {"instr":"daddu a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_add_long_2addr.S b/runtime/interpreter/mterp/mips64/op_add_long_2addr.S deleted file mode 100644 index 928ff545659b06e61fb7503e8ec3af02196352e0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_add_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binopWide2addr.S" {"instr":"daddu a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_aget.S b/runtime/interpreter/mterp/mips64/op_aget.S deleted file mode 100644 index 0472a0616bcaab47442574a33d2e8e0004472d88..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_aget.S +++ /dev/null @@ -1,29 +0,0 @@ -%default { "load":"lw", "shift":"2", "data_offset":"MIRROR_INT_ARRAY_DATA_OFFSET" } - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - srl a4, rINST, 8 # a4 <- AA - GET_VREG_U a0, a2 # a0 <- vBB (array object) - GET_VREG a1, a3 # a1 <- vCC (requested index) - beqz a0, common_errNullObject # bail if null array object - lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length - .if $shift - # [d]lsa does not support shift count of 0. - dlsa a0, a1, a0, $shift # a0 <- arrayObj + index*width - .else - daddu a0, a1, a0 # a0 <- arrayObj + index*width - .endif - bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - $load a2, $data_offset(a0) # a2 <- vBB[vCC] - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a2, a4 # vAA <- a2 - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_aget_boolean.S b/runtime/interpreter/mterp/mips64/op_aget_boolean.S deleted file mode 100644 index d5be01b7c5b1b7c1d1ca9e8d208d0207e477b7dd..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_aget_boolean.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_aget.S" { "load":"lbu", "shift":"0", "data_offset":"MIRROR_BOOLEAN_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/mips64/op_aget_byte.S b/runtime/interpreter/mterp/mips64/op_aget_byte.S deleted file mode 100644 index 084de8d4df54bbce503b5db306d4f588ef6cbe3f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_aget_byte.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_aget.S" { "load":"lb", "shift":"0", "data_offset":"MIRROR_BYTE_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/mips64/op_aget_char.S b/runtime/interpreter/mterp/mips64/op_aget_char.S deleted file mode 100644 index 6c99ed52ade1dfeb21e6b8a48fec150045b4d966..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_aget_char.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_aget.S" { "load":"lhu", "shift":"1", "data_offset":"MIRROR_CHAR_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/mips64/op_aget_object.S b/runtime/interpreter/mterp/mips64/op_aget_object.S deleted file mode 100644 index 6374a05e7b8b32e9b9e03088a12fc67096768641..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_aget_object.S +++ /dev/null @@ -1,21 +0,0 @@ - /* - * Array object get. vAA <- vBB[vCC]. - * - * for: aget-object - */ - /* op vAA, vBB, vCC */ - .extern artAGetObjectFromMterp - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - EXPORT_PC - GET_VREG_U a0, a2 # a0 <- vBB (array object) - GET_VREG a1, a3 # a1 <- vCC (requested index) - jal artAGetObjectFromMterp # (array, index) - ld a1, THREAD_EXCEPTION_OFFSET(rSELF) - srl a4, rINST, 8 # a4 <- AA - PREFETCH_INST 2 - bnez a1, MterpException - SET_VREG_OBJECT v0, a4 # vAA <- v0 - ADVANCE 2 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_aget_short.S b/runtime/interpreter/mterp/mips64/op_aget_short.S deleted file mode 100644 index 0158b0a1a171a6d12f96954412deaef183ba5add..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_aget_short.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_aget.S" { "load":"lh", "shift":"1", "data_offset":"MIRROR_SHORT_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/mips64/op_aget_wide.S b/runtime/interpreter/mterp/mips64/op_aget_wide.S deleted file mode 100644 index 0945acae5a6d87b8c98f8cadd9bb984736da2fb8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_aget_wide.S +++ /dev/null @@ -1,21 +0,0 @@ - /* - * Array get, 64 bits. vAA <- vBB[vCC]. - * - */ - /* aget-wide vAA, vBB, vCC */ - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - srl a4, rINST, 8 # a4 <- AA - GET_VREG_U a0, a2 # a0 <- vBB (array object) - GET_VREG a1, a3 # a1 <- vCC (requested index) - beqz a0, common_errNullObject # bail if null array object - lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length - dlsa a0, a1, a0, 3 # a0 <- arrayObj + index*width - bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - lw a2, MIRROR_WIDE_ARRAY_DATA_OFFSET(a0) - lw a3, (MIRROR_WIDE_ARRAY_DATA_OFFSET+4)(a0) - dinsu a2, a3, 32, 32 # a2 <- vBB[vCC] - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a2, a4 # vAA <- a2 - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_and_int.S b/runtime/interpreter/mterp/mips64/op_and_int.S deleted file mode 100644 index f0792a8351653a2629a7b5dfc7e9df03db1b845b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_and_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binop.S" {"instr":"and a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_and_int_2addr.S b/runtime/interpreter/mterp/mips64/op_and_int_2addr.S deleted file mode 100644 index 08dc615518989987eed96af039f6ed721df4ccb3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_and_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binop2addr.S" {"instr":"and a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_and_int_lit16.S b/runtime/interpreter/mterp/mips64/op_and_int_lit16.S deleted file mode 100644 index 65d28ad20cf6703dbb34c5de13f7645c19f6d97c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_and_int_lit16.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binopLit16.S" {"instr":"and a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_and_int_lit8.S b/runtime/interpreter/mterp/mips64/op_and_int_lit8.S deleted file mode 100644 index ab84bb7ce25d121ffb8d40e142c5ddaf3b938ca4..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_and_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binopLit8.S" {"instr":"and a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_and_long.S b/runtime/interpreter/mterp/mips64/op_and_long.S deleted file mode 100644 index e383ba00caab2778453f603d9cd3bd0f03b575ba..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_and_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binopWide.S" {"instr":"and a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_and_long_2addr.S b/runtime/interpreter/mterp/mips64/op_and_long_2addr.S deleted file mode 100644 index f863bb9275d0e7f293ff49c52465c28b16f77150..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_and_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binopWide2addr.S" {"instr":"and a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_aput.S b/runtime/interpreter/mterp/mips64/op_aput.S deleted file mode 100644 index 9bfda97d05967530fcdfa7d2129685852375e23c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_aput.S +++ /dev/null @@ -1,29 +0,0 @@ -%default { "store":"sw", "shift":"2", "data_offset":"MIRROR_INT_ARRAY_DATA_OFFSET" } - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - srl a4, rINST, 8 # a4 <- AA - GET_VREG_U a0, a2 # a0 <- vBB (array object) - GET_VREG a1, a3 # a1 <- vCC (requested index) - beqz a0, common_errNullObject # bail if null array object - lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length - .if $shift - # [d]lsa does not support shift count of 0. - dlsa a0, a1, a0, $shift # a0 <- arrayObj + index*width - .else - daddu a0, a1, a0 # a0 <- arrayObj + index*width - .endif - bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_VREG a2, a4 # a2 <- vAA - GET_INST_OPCODE v0 # extract opcode from rINST - $store a2, $data_offset(a0) # vBB[vCC] <- a2 - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_aput_boolean.S b/runtime/interpreter/mterp/mips64/op_aput_boolean.S deleted file mode 100644 index 6707a1f11da9c8c0e57755723ef63d1a8abc10eb..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_aput_boolean.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_aput.S" { "store":"sb", "shift":"0", "data_offset":"MIRROR_BOOLEAN_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/mips64/op_aput_byte.S b/runtime/interpreter/mterp/mips64/op_aput_byte.S deleted file mode 100644 index 7b9ce483799fb5d7268eb9bda5046b425c6da279..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_aput_byte.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_aput.S" { "store":"sb", "shift":"0", "data_offset":"MIRROR_BYTE_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/mips64/op_aput_char.S b/runtime/interpreter/mterp/mips64/op_aput_char.S deleted file mode 100644 index 82bc8f7818504603ad356b9f4ed2b6238562ab01..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_aput_char.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_aput.S" { "store":"sh", "shift":"1", "data_offset":"MIRROR_CHAR_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/mips64/op_aput_object.S b/runtime/interpreter/mterp/mips64/op_aput_object.S deleted file mode 100644 index b132456a182fc183324e4d605a2ab83e7fe3609a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_aput_object.S +++ /dev/null @@ -1,14 +0,0 @@ - /* - * Store an object into an array. vBB[vCC] <- vAA. - */ - /* op vAA, vBB, vCC */ - .extern MterpAputObject - EXPORT_PC - daddu a0, rFP, OFF_FP_SHADOWFRAME - move a1, rPC - move a2, rINST - jal MterpAputObject - beqzc v0, MterpPossibleException - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_aput_short.S b/runtime/interpreter/mterp/mips64/op_aput_short.S deleted file mode 100644 index a7af2945b1ac21866e8d913904b95737979734be..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_aput_short.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_aput.S" { "store":"sh", "shift":"1", "data_offset":"MIRROR_SHORT_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/mips64/op_aput_wide.S b/runtime/interpreter/mterp/mips64/op_aput_wide.S deleted file mode 100644 index a1d7a3b51ea333857defaa2caedf983546d28b18..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_aput_wide.S +++ /dev/null @@ -1,21 +0,0 @@ - /* - * Array put, 64 bits. vBB[vCC] <- vAA. - * - */ - /* aput-wide vAA, vBB, vCC */ - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - srl a4, rINST, 8 # a4 <- AA - GET_VREG_U a0, a2 # a0 <- vBB (array object) - GET_VREG a1, a3 # a1 <- vCC (requested index) - beqz a0, common_errNullObject # bail if null array object - lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length - dlsa a0, a1, a0, 3 # a0 <- arrayObj + index*width - bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail - GET_VREG_WIDE a2, a4 # a2 <- vAA - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - sw a2, MIRROR_WIDE_ARRAY_DATA_OFFSET(a0) - dsrl32 a2, a2, 0 - sw a2, (MIRROR_WIDE_ARRAY_DATA_OFFSET+4)(a0) # vBB[vCC] <- a2 - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_array_length.S b/runtime/interpreter/mterp/mips64/op_array_length.S deleted file mode 100644 index 2d9e172d1863f8eb38d1be287b71531007fdcdcf..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_array_length.S +++ /dev/null @@ -1,12 +0,0 @@ - /* - * Return the length of an array. - */ - srl a1, rINST, 12 # a1 <- B - GET_VREG_U a0, a1 # a0 <- vB (object ref) - ext a2, rINST, 8, 4 # a2 <- A - beqz a0, common_errNullObject # yup, fail - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- array length - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a3, a2 # vB <- length - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_check_cast.S b/runtime/interpreter/mterp/mips64/op_check_cast.S deleted file mode 100644 index 472595d8242f9f6948ee87c43c188174650546b0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_check_cast.S +++ /dev/null @@ -1,17 +0,0 @@ - /* - * Check to see if a cast from one class to another is allowed. - */ - /* check-cast vAA, class//BBBB */ - .extern MterpCheckCast - EXPORT_PC - lhu a0, 2(rPC) # a0 <- BBBB - srl a1, rINST, 8 # a1 <- AA - dlsa a1, a1, rFP, 2 # a1 <- &object - ld a2, OFF_FP_METHOD(rFP) # a2 <- method - move a3, rSELF # a3 <- self - jal MterpCheckCast # (index, &obj, method, self) - PREFETCH_INST 2 - bnez v0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_cmp_long.S b/runtime/interpreter/mterp/mips64/op_cmp_long.S deleted file mode 100644 index 6e9376cfabe84b4fde6a29d2bb5592094b283252..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_cmp_long.S +++ /dev/null @@ -1,13 +0,0 @@ - /* cmp-long vAA, vBB, vCC */ - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - srl a4, rINST, 8 # a4 <- AA - GET_VREG_WIDE a0, a2 # a0 <- vBB - GET_VREG_WIDE a1, a3 # a1 <- vCC - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - slt a2, a0, a1 - slt a0, a1, a0 - subu a0, a0, a2 - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a4 # vAA <- result - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_cmpg_double.S b/runtime/interpreter/mterp/mips64/op_cmpg_double.S deleted file mode 100644 index a8e2ef9867cdb3f8cd95454a52f9d7089246e343..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_cmpg_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/fcmpWide.S" {"gt_bias":"1"} diff --git a/runtime/interpreter/mterp/mips64/op_cmpg_float.S b/runtime/interpreter/mterp/mips64/op_cmpg_float.S deleted file mode 100644 index 0c93eac7de11abe92dc221443e9f4bedf99d95b0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_cmpg_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/fcmp.S" {"gt_bias":"1"} diff --git a/runtime/interpreter/mterp/mips64/op_cmpl_double.S b/runtime/interpreter/mterp/mips64/op_cmpl_double.S deleted file mode 100644 index 9111b067f63e8b98b34ff7d6896592672d76cd0e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_cmpl_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/fcmpWide.S" {"gt_bias":"0"} diff --git a/runtime/interpreter/mterp/mips64/op_cmpl_float.S b/runtime/interpreter/mterp/mips64/op_cmpl_float.S deleted file mode 100644 index b047451842536f1ed97227e366ac12058bd0eaac..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_cmpl_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/fcmp.S" {"gt_bias":"0"} diff --git a/runtime/interpreter/mterp/mips64/op_const.S b/runtime/interpreter/mterp/mips64/op_const.S deleted file mode 100644 index 4b0d69b763ba4ce8249d3da814cddc1f5f4c4ed3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_const.S +++ /dev/null @@ -1,9 +0,0 @@ - /* const vAA, #+BBBBbbbb */ - srl a2, rINST, 8 # a2 <- AA - lh a0, 2(rPC) # a0 <- bbbb (low) - lh a1, 4(rPC) # a1 <- BBBB (high) - FETCH_ADVANCE_INST 3 # advance rPC, load rINST - ins a0, a1, 16, 16 # a0 = BBBBbbbb - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vAA <- +BBBBbbbb - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_const_16.S b/runtime/interpreter/mterp/mips64/op_const_16.S deleted file mode 100644 index 51e68a7df77d7f58be781af3e144abf79373a6dc..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_const_16.S +++ /dev/null @@ -1,7 +0,0 @@ - /* const/16 vAA, #+BBBB */ - srl a2, rINST, 8 # a2 <- AA - lh a0, 2(rPC) # a0 <- sign-extended BBBB - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vAA <- +BBBB - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_const_4.S b/runtime/interpreter/mterp/mips64/op_const_4.S deleted file mode 100644 index 0a58bff7b7d65ac3866cc6e3ea5c8f93360f7509..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_const_4.S +++ /dev/null @@ -1,8 +0,0 @@ - /* const/4 vA, #+B */ - ext a2, rINST, 8, 4 # a2 <- A - seh a0, rINST # sign extend B in rINST - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - sra a0, a0, 12 # shift B into its final position - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- +B - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_const_class.S b/runtime/interpreter/mterp/mips64/op_const_class.S deleted file mode 100644 index 3f0c716d5ec344a925552129350a51aa39d0c1cd..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_const_class.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/const.S" { "helper":"MterpConstClass" } diff --git a/runtime/interpreter/mterp/mips64/op_const_high16.S b/runtime/interpreter/mterp/mips64/op_const_high16.S deleted file mode 100644 index 43effb6f60a2f9b074f022330144e120fc104d7a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_const_high16.S +++ /dev/null @@ -1,8 +0,0 @@ - /* const/high16 vAA, #+BBBB0000 */ - srl a2, rINST, 8 # a2 <- AA - lh a0, 2(rPC) # a0 <- BBBB - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - sll a0, a0, 16 # a0 <- BBBB0000 - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vAA <- +BBBB0000 - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_const_method_handle.S b/runtime/interpreter/mterp/mips64/op_const_method_handle.S deleted file mode 100644 index 43584d179c03a8e7815dc08aa428ea45601deb26..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_const_method_handle.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/const.S" { "helper":"MterpConstMethodHandle" } diff --git a/runtime/interpreter/mterp/mips64/op_const_method_type.S b/runtime/interpreter/mterp/mips64/op_const_method_type.S deleted file mode 100644 index 553b28424a70fd7152f1c1c281ceac1d0a827b88..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_const_method_type.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/const.S" { "helper":"MterpConstMethodType" } diff --git a/runtime/interpreter/mterp/mips64/op_const_string.S b/runtime/interpreter/mterp/mips64/op_const_string.S deleted file mode 100644 index 96cbb5a23ae706bb78a79d9a4dc13fb53f5e0376..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_const_string.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/const.S" { "helper":"MterpConstString" } diff --git a/runtime/interpreter/mterp/mips64/op_const_string_jumbo.S b/runtime/interpreter/mterp/mips64/op_const_string_jumbo.S deleted file mode 100644 index 47f2101c881e128157a58bba36ff3ab597baf6f5..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_const_string_jumbo.S +++ /dev/null @@ -1,15 +0,0 @@ - /* const/string vAA, String//BBBBBBBB */ - .extern MterpConstString - EXPORT_PC - lh a0, 2(rPC) # a0 <- bbbb (low) - lh a4, 4(rPC) # a4 <- BBBB (high) - srl a1, rINST, 8 # a1 <- AA - ins a0, a4, 16, 16 # a0 <- BBBBbbbb - daddu a2, rFP, OFF_FP_SHADOWFRAME - move a3, rSELF - jal MterpConstString # (index, tgt_reg, shadow_frame, self) - PREFETCH_INST 3 # load rINST - bnez v0, MterpPossibleException # let reference interpreter deal with it. - ADVANCE 3 # advance rPC - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_const_wide.S b/runtime/interpreter/mterp/mips64/op_const_wide.S deleted file mode 100644 index f7eaf7c23110fe5ed61328807b77c59dbcddf6df..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_const_wide.S +++ /dev/null @@ -1,13 +0,0 @@ - /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ - srl a4, rINST, 8 # a4 <- AA - lh a0, 2(rPC) # a0 <- bbbb (low) - lh a1, 4(rPC) # a1 <- BBBB (low middle) - lh a2, 6(rPC) # a2 <- hhhh (high middle) - lh a3, 8(rPC) # a3 <- HHHH (high) - FETCH_ADVANCE_INST 5 # advance rPC, load rINST - ins a0, a1, 16, 16 # a0 = BBBBbbbb - ins a2, a3, 16, 16 # a2 = HHHHhhhh - dinsu a0, a2, 32, 32 # a0 = HHHHhhhhBBBBbbbb - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a4 # vAA <- +HHHHhhhhBBBBbbbb - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_const_wide_16.S b/runtime/interpreter/mterp/mips64/op_const_wide_16.S deleted file mode 100644 index 3a70937973202d341c05b304b276c41eab5b154d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_const_wide_16.S +++ /dev/null @@ -1,7 +0,0 @@ - /* const-wide/16 vAA, #+BBBB */ - srl a2, rINST, 8 # a2 <- AA - lh a0, 2(rPC) # a0 <- sign-extended BBBB - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vAA <- +BBBB - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_const_wide_32.S b/runtime/interpreter/mterp/mips64/op_const_wide_32.S deleted file mode 100644 index 867197ce139f90c0122ec8690763a7b055581c35..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_const_wide_32.S +++ /dev/null @@ -1,9 +0,0 @@ - /* const-wide/32 vAA, #+BBBBbbbb */ - srl a2, rINST, 8 # a2 <- AA - lh a0, 2(rPC) # a0 <- bbbb (low) - lh a1, 4(rPC) # a1 <- BBBB (high) - FETCH_ADVANCE_INST 3 # advance rPC, load rINST - ins a0, a1, 16, 16 # a0 = BBBBbbbb - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vAA <- +BBBBbbbb - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_const_wide_high16.S b/runtime/interpreter/mterp/mips64/op_const_wide_high16.S deleted file mode 100644 index d741631bcbfc4025079a725ec3dd11edb2c9df82..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_const_wide_high16.S +++ /dev/null @@ -1,8 +0,0 @@ - /* const-wide/high16 vAA, #+BBBB000000000000 */ - srl a2, rINST, 8 # a2 <- AA - lh a0, 2(rPC) # a0 <- BBBB - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - dsll32 a0, a0, 16 # a0 <- BBBB000000000000 - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vAA <- +BBBB000000000000 - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_div_double.S b/runtime/interpreter/mterp/mips64/op_div_double.S deleted file mode 100644 index 44998f0c29838742f1e1e74f25bfc67592c8e4ee..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_div_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/fbinopWide.S" {"instr":"div.d f0, f0, f1"} diff --git a/runtime/interpreter/mterp/mips64/op_div_double_2addr.S b/runtime/interpreter/mterp/mips64/op_div_double_2addr.S deleted file mode 100644 index 396af798f6c2d849860804a0a71684a74059f118..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_div_double_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/fbinopWide2addr.S" {"instr":"div.d f0, f0, f1"} diff --git a/runtime/interpreter/mterp/mips64/op_div_float.S b/runtime/interpreter/mterp/mips64/op_div_float.S deleted file mode 100644 index 7b09d52f02e8832d2bc864e14713f0b422e3f592..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_div_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/fbinop.S" {"instr":"div.s f0, f0, f1"} diff --git a/runtime/interpreter/mterp/mips64/op_div_float_2addr.S b/runtime/interpreter/mterp/mips64/op_div_float_2addr.S deleted file mode 100644 index e74fddae6dc56678da44dc5debadf11ef386ddf4..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_div_float_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/fbinop2addr.S" {"instr":"div.s f0, f0, f1"} diff --git a/runtime/interpreter/mterp/mips64/op_div_int.S b/runtime/interpreter/mterp/mips64/op_div_int.S deleted file mode 100644 index fb04acbff8a86ffb25f0304634e2f70a99aafdd1..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_div_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binop.S" {"instr":"div a0, a0, a1", "chkzero":"1"} diff --git a/runtime/interpreter/mterp/mips64/op_div_int_2addr.S b/runtime/interpreter/mterp/mips64/op_div_int_2addr.S deleted file mode 100644 index db29b844fb23b4e412fffab95aaa9643b5990a52..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_div_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binop2addr.S" {"instr":"div a0, a0, a1", "chkzero":"1"} diff --git a/runtime/interpreter/mterp/mips64/op_div_int_lit16.S b/runtime/interpreter/mterp/mips64/op_div_int_lit16.S deleted file mode 100644 index e903ddee2c726874ad46bf6ab2546b9271d80983..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_div_int_lit16.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binopLit16.S" {"instr":"div a0, a0, a1", "chkzero":"1"} diff --git a/runtime/interpreter/mterp/mips64/op_div_int_lit8.S b/runtime/interpreter/mterp/mips64/op_div_int_lit8.S deleted file mode 100644 index 055960546fdb1bc71845a045d7b9069d55ae61d5..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_div_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binopLit8.S" {"instr":"div a0, a0, a1", "chkzero":"1"} diff --git a/runtime/interpreter/mterp/mips64/op_div_long.S b/runtime/interpreter/mterp/mips64/op_div_long.S deleted file mode 100644 index 01fc2b281a50e2a9140afaa9caba469fc0a0625a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_div_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binopWide.S" {"instr":"ddiv a0, a0, a1", "chkzero":"1"} diff --git a/runtime/interpreter/mterp/mips64/op_div_long_2addr.S b/runtime/interpreter/mterp/mips64/op_div_long_2addr.S deleted file mode 100644 index 9627ab8a2487a9b5e8a3d4a4a8e9c9ee5a6dfa2e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_div_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binopWide2addr.S" {"instr":"ddiv a0, a0, a1", "chkzero":"1"} diff --git a/runtime/interpreter/mterp/mips64/op_double_to_float.S b/runtime/interpreter/mterp/mips64/op_double_to_float.S deleted file mode 100644 index 2b2acee59147f8b8c6eb8482ebfa90dce3bf272f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_double_to_float.S +++ /dev/null @@ -1,8 +0,0 @@ - /* - * Conversion from or to floating-point happens in a floating-point register. - * Therefore we load the input and store the output into or from a - * floating-point register irrespective of the type. - */ -%include "mips64/fcvtHeader.S" { "suffix":"_DOUBLE", "valreg":"f0" } - cvt.s.d f0, f0 -%include "mips64/fcvtFooter.S" { "suffix":"_FLOAT", "valreg":"f0" } diff --git a/runtime/interpreter/mterp/mips64/op_double_to_int.S b/runtime/interpreter/mterp/mips64/op_double_to_int.S deleted file mode 100644 index d09952233cbe1e4582904417231bea4d0021b1ab..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_double_to_int.S +++ /dev/null @@ -1,3 +0,0 @@ -%include "mips64/fcvtHeader.S" { "suffix":"_DOUBLE", "valreg":"f0" } - trunc.w.d f0, f0 -%include "mips64/fcvtFooter.S" { "suffix":"_FLOAT", "valreg":"f0" } diff --git a/runtime/interpreter/mterp/mips64/op_double_to_long.S b/runtime/interpreter/mterp/mips64/op_double_to_long.S deleted file mode 100644 index 9b65da56020ce3a3f93ffcd7e74212fff7800789..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_double_to_long.S +++ /dev/null @@ -1,3 +0,0 @@ -%include "mips64/fcvtHeader.S" { "suffix":"_DOUBLE", "valreg":"f0" } - trunc.l.d f0, f0 -%include "mips64/fcvtFooter.S" { "suffix":"_DOUBLE", "valreg":"f0" } diff --git a/runtime/interpreter/mterp/mips64/op_fill_array_data.S b/runtime/interpreter/mterp/mips64/op_fill_array_data.S deleted file mode 100644 index c90f0b90ada33d3e6c269c8e1db221542d7570d9..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_fill_array_data.S +++ /dev/null @@ -1,14 +0,0 @@ - /* fill-array-data vAA, +BBBBBBBB */ - .extern MterpFillArrayData - EXPORT_PC - lh a1, 2(rPC) # a1 <- bbbb (lo) - lh a0, 4(rPC) # a0 <- BBBB (hi) - srl a3, rINST, 8 # a3 <- AA - ins a1, a0, 16, 16 # a1 <- BBBBbbbb - GET_VREG_U a0, a3 # a0 <- vAA (array object) - dlsa a1, a1, rPC, 1 # a1 <- PC + BBBBbbbb*2 (array data off.) - jal MterpFillArrayData # (obj, payload) - beqzc v0, MterpPossibleException # exception? - FETCH_ADVANCE_INST 3 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_filled_new_array.S b/runtime/interpreter/mterp/mips64/op_filled_new_array.S deleted file mode 100644 index 35f55c27a6d6a02b72aacac56e2c22d7c345122b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_filled_new_array.S +++ /dev/null @@ -1,18 +0,0 @@ -%default { "helper":"MterpFilledNewArray" } - /* - * Create a new array with elements filled from registers. - * - * for: filled-new-array, filled-new-array/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class//CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, type//BBBB */ - .extern $helper - EXPORT_PC - daddu a0, rFP, OFF_FP_SHADOWFRAME - move a1, rPC - move a2, rSELF - jal $helper - beqzc v0, MterpPossibleException - FETCH_ADVANCE_INST 3 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_filled_new_array_range.S b/runtime/interpreter/mterp/mips64/op_filled_new_array_range.S deleted file mode 100644 index a4e18f68d6d70fe8c9d71fb45865144a6f7eef73..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_filled_new_array_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_filled_new_array.S" { "helper":"MterpFilledNewArrayRange" } diff --git a/runtime/interpreter/mterp/mips64/op_float_to_double.S b/runtime/interpreter/mterp/mips64/op_float_to_double.S deleted file mode 100644 index 6accfeeff6e8d76900f271f641f5afd04d523f50..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_float_to_double.S +++ /dev/null @@ -1,8 +0,0 @@ - /* - * Conversion from or to floating-point happens in a floating-point register. - * Therefore we load the input and store the output into or from a - * floating-point register irrespective of the type. - */ -%include "mips64/fcvtHeader.S" { "suffix":"_FLOAT", "valreg":"f0" } - cvt.d.s f0, f0 -%include "mips64/fcvtFooter.S" { "suffix":"_DOUBLE", "valreg":"f0" } diff --git a/runtime/interpreter/mterp/mips64/op_float_to_int.S b/runtime/interpreter/mterp/mips64/op_float_to_int.S deleted file mode 100644 index 28069739354ed53a55aa070b6c840ab28ef7e7ac..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_float_to_int.S +++ /dev/null @@ -1,3 +0,0 @@ -%include "mips64/fcvtHeader.S" { "suffix":"_FLOAT", "valreg":"f0" } - trunc.w.s f0, f0 -%include "mips64/fcvtFooter.S" { "suffix":"_FLOAT", "valreg":"f0" } diff --git a/runtime/interpreter/mterp/mips64/op_float_to_long.S b/runtime/interpreter/mterp/mips64/op_float_to_long.S deleted file mode 100644 index c40c8a6680e63ac82fd81cdc1c50ebc95ba334ab..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_float_to_long.S +++ /dev/null @@ -1,3 +0,0 @@ -%include "mips64/fcvtHeader.S" { "suffix":"_FLOAT", "valreg":"f0" } - trunc.l.s f0, f0 -%include "mips64/fcvtFooter.S" { "suffix":"_DOUBLE", "valreg":"f0" } diff --git a/runtime/interpreter/mterp/mips64/op_goto.S b/runtime/interpreter/mterp/mips64/op_goto.S deleted file mode 100644 index 68fc83d0caf00a1f51f2c65bcc49bc247f6eb457..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_goto.S +++ /dev/null @@ -1,10 +0,0 @@ - /* - * Unconditional branch, 8-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto +AA */ - srl rINST, rINST, 8 - seb rINST, rINST # rINST <- offset (sign-extended AA) - b MterpCommonTakenBranchNoFlags diff --git a/runtime/interpreter/mterp/mips64/op_goto_16.S b/runtime/interpreter/mterp/mips64/op_goto_16.S deleted file mode 100644 index ae560663522183cf3f2d471d1da6e7eb5c333554..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_goto_16.S +++ /dev/null @@ -1,9 +0,0 @@ - /* - * Unconditional branch, 16-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto/16 +AAAA */ - lh rINST, 2(rPC) # rINST <- offset (sign-extended AAAA) - b MterpCommonTakenBranchNoFlags diff --git a/runtime/interpreter/mterp/mips64/op_goto_32.S b/runtime/interpreter/mterp/mips64/op_goto_32.S deleted file mode 100644 index 498b6d60ae7270990a4fc3e9a0893af660cf46bd..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_goto_32.S +++ /dev/null @@ -1,14 +0,0 @@ - /* - * Unconditional branch, 32-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - * - * Unlike most opcodes, this one is allowed to branch to itself, so - * our "backward branch" test must be "<=0" instead of "<0". - */ - /* goto/32 +AAAAAAAA */ - lh rINST, 2(rPC) # rINST <- aaaa (low) - lh a1, 4(rPC) # a1 <- AAAA (high) - ins rINST, a1, 16, 16 # rINST <- offset (sign-extended AAAAaaaa) - b MterpCommonTakenBranchNoFlags diff --git a/runtime/interpreter/mterp/mips64/op_if_eq.S b/runtime/interpreter/mterp/mips64/op_if_eq.S deleted file mode 100644 index aa35cadf17dbd00f1a0ff8862e345788ad0f0893..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_if_eq.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/bincmp.S" { "condition":"eq" } diff --git a/runtime/interpreter/mterp/mips64/op_if_eqz.S b/runtime/interpreter/mterp/mips64/op_if_eqz.S deleted file mode 100644 index 0fe34187a0fb51c86c06b3436b7d36c47ecd7a09..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_if_eqz.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/zcmp.S" { "condition":"eq" } diff --git a/runtime/interpreter/mterp/mips64/op_if_ge.S b/runtime/interpreter/mterp/mips64/op_if_ge.S deleted file mode 100644 index 59fdcc5b3394f9ed51ddae2ef9d8e44fc4d0b153..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_if_ge.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/bincmp.S" { "condition":"ge" } diff --git a/runtime/interpreter/mterp/mips64/op_if_gez.S b/runtime/interpreter/mterp/mips64/op_if_gez.S deleted file mode 100644 index 57f1f66ecdfaebe3f00fd54d4d3e3b340586566e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_if_gez.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/zcmp.S" { "condition":"ge" } diff --git a/runtime/interpreter/mterp/mips64/op_if_gt.S b/runtime/interpreter/mterp/mips64/op_if_gt.S deleted file mode 100644 index 26cc1195b5b35b721517e31ef5ad2ca27e9d0bfc..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_if_gt.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/bincmp.S" { "condition":"gt" } diff --git a/runtime/interpreter/mterp/mips64/op_if_gtz.S b/runtime/interpreter/mterp/mips64/op_if_gtz.S deleted file mode 100644 index 69fcacb82dc07cebfb054b71f87a73e7f4e711f4..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_if_gtz.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/zcmp.S" { "condition":"gt" } diff --git a/runtime/interpreter/mterp/mips64/op_if_le.S b/runtime/interpreter/mterp/mips64/op_if_le.S deleted file mode 100644 index a7fce17c40750c2a5e1c9374e3dfaa4f7babb530..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_if_le.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/bincmp.S" { "condition":"le" } diff --git a/runtime/interpreter/mterp/mips64/op_if_lez.S b/runtime/interpreter/mterp/mips64/op_if_lez.S deleted file mode 100644 index f3edcc6d994efc6b00bb7d6f0f94326badfa7aea..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_if_lez.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/zcmp.S" { "condition":"le" } diff --git a/runtime/interpreter/mterp/mips64/op_if_lt.S b/runtime/interpreter/mterp/mips64/op_if_lt.S deleted file mode 100644 index a975a31b57b597b4d3026f160b24c1a52ffffba8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_if_lt.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/bincmp.S" { "condition":"lt" } diff --git a/runtime/interpreter/mterp/mips64/op_if_ltz.S b/runtime/interpreter/mterp/mips64/op_if_ltz.S deleted file mode 100644 index c1d730d43f8a504099b1979abb0dd154f6175908..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_if_ltz.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/zcmp.S" { "condition":"lt" } diff --git a/runtime/interpreter/mterp/mips64/op_if_ne.S b/runtime/interpreter/mterp/mips64/op_if_ne.S deleted file mode 100644 index f143ee917e2e8a76593191c42ad88b6d24572c2c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_if_ne.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/bincmp.S" { "condition":"ne" } diff --git a/runtime/interpreter/mterp/mips64/op_if_nez.S b/runtime/interpreter/mterp/mips64/op_if_nez.S deleted file mode 100644 index 1856b96dbcd8460b71fdb1116b320470ad29fa45..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_if_nez.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/zcmp.S" { "condition":"ne" } diff --git a/runtime/interpreter/mterp/mips64/op_iget.S b/runtime/interpreter/mterp/mips64/op_iget.S deleted file mode 100644 index e91f09923bb072bc42a5a86823dcdb0820040cf9..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_iget.S +++ /dev/null @@ -1,2 +0,0 @@ -%default { "is_object":"0", "helper":"MterpIGetU32"} -%include "mips64/field.S" { } diff --git a/runtime/interpreter/mterp/mips64/op_iget_boolean.S b/runtime/interpreter/mterp/mips64/op_iget_boolean.S deleted file mode 100644 index dc2a42ad7628f010a175fc5d89ec35af4990988b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_iget_boolean.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_iget.S" { "helper":"MterpIGetU8" } diff --git a/runtime/interpreter/mterp/mips64/op_iget_boolean_quick.S b/runtime/interpreter/mterp/mips64/op_iget_boolean_quick.S deleted file mode 100644 index 979dc7079e09a9bda6e2ad0699b4e9a75db0d313..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_iget_boolean_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_iget_quick.S" { "load":"lbu" } diff --git a/runtime/interpreter/mterp/mips64/op_iget_byte.S b/runtime/interpreter/mterp/mips64/op_iget_byte.S deleted file mode 100644 index c5bf6506e6c2086dbacbbb32439ae50005e5e62c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_iget_byte.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_iget.S" { "helper":"MterpIGetI8" } diff --git a/runtime/interpreter/mterp/mips64/op_iget_byte_quick.S b/runtime/interpreter/mterp/mips64/op_iget_byte_quick.S deleted file mode 100644 index cb355567216eea69e1a840fc89d40a2ce783a873..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_iget_byte_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_iget_quick.S" { "load":"lb" } diff --git a/runtime/interpreter/mterp/mips64/op_iget_char.S b/runtime/interpreter/mterp/mips64/op_iget_char.S deleted file mode 100644 index 3bf0c5aab9d29ac518a5abcf8b51266dbed0ef55..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_iget_char.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_iget.S" { "helper":"MterpIGetU16" } diff --git a/runtime/interpreter/mterp/mips64/op_iget_char_quick.S b/runtime/interpreter/mterp/mips64/op_iget_char_quick.S deleted file mode 100644 index 603456775b89e17d81816c24914cc01a0681e62a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_iget_char_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_iget_quick.S" { "load":"lhu" } diff --git a/runtime/interpreter/mterp/mips64/op_iget_object.S b/runtime/interpreter/mterp/mips64/op_iget_object.S deleted file mode 100644 index 23fa187192b8c37df805f944603320c150739304..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_iget_object.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_iget.S" { "is_object":"1", "helper":"MterpIGetObj" } diff --git a/runtime/interpreter/mterp/mips64/op_iget_object_quick.S b/runtime/interpreter/mterp/mips64/op_iget_object_quick.S deleted file mode 100644 index 171d54301b26f04e704a9662bfe08d97d8dc6d38..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_iget_object_quick.S +++ /dev/null @@ -1,16 +0,0 @@ - /* For: iget-object-quick */ - /* op vA, vB, offset//CCCC */ - .extern artIGetObjectFromMterp - srl a2, rINST, 12 # a2 <- B - lhu a1, 2(rPC) # a1 <- field byte offset - EXPORT_PC - GET_VREG_U a0, a2 # a0 <- object we're operating on - jal artIGetObjectFromMterp # (obj, offset) - ld a3, THREAD_EXCEPTION_OFFSET(rSELF) - ext a2, rINST, 8, 4 # a2 <- A - PREFETCH_INST 2 - bnez a3, MterpPossibleException # bail out - SET_VREG_OBJECT v0, a2 # fp[A] <- v0 - ADVANCE 2 # advance rPC - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_iget_quick.S b/runtime/interpreter/mterp/mips64/op_iget_quick.S deleted file mode 100644 index fee6ab738c3d4c0775c8af962be4d65082c6d755..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_iget_quick.S +++ /dev/null @@ -1,14 +0,0 @@ -%default { "load":"lw" } - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset//CCCC */ - srl a2, rINST, 12 # a2 <- B - lhu a1, 2(rPC) # a1 <- field byte offset - GET_VREG_U a3, a2 # a3 <- object we're operating on - ext a4, rINST, 8, 4 # a4 <- A - daddu a1, a1, a3 - beqz a3, common_errNullObject # object was null - $load a0, 0(a1) # a0 <- obj.field - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - SET_VREG a0, a4 # fp[A] <- a0 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_iget_short.S b/runtime/interpreter/mterp/mips64/op_iget_short.S deleted file mode 100644 index a9927fc982c67a9c7b394aeb392aff744fd27e0a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_iget_short.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_iget.S" { "helper":"MterpIGetI16" } diff --git a/runtime/interpreter/mterp/mips64/op_iget_short_quick.S b/runtime/interpreter/mterp/mips64/op_iget_short_quick.S deleted file mode 100644 index 6e152dbf48b539bd93040ad73488a1a2a5626910..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_iget_short_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_iget_quick.S" { "load":"lh" } diff --git a/runtime/interpreter/mterp/mips64/op_iget_wide.S b/runtime/interpreter/mterp/mips64/op_iget_wide.S deleted file mode 100644 index 40f364571fc6ad9b00f6be97d0e56a2f3b2323e3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_iget_wide.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_iget.S" { "helper":"MterpIGetU64" } diff --git a/runtime/interpreter/mterp/mips64/op_iget_wide_quick.S b/runtime/interpreter/mterp/mips64/op_iget_wide_quick.S deleted file mode 100644 index 2adc6adf15bfadea294a2946f4a7492a149f8d5a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_iget_wide_quick.S +++ /dev/null @@ -1,14 +0,0 @@ - /* iget-wide-quick vA, vB, offset//CCCC */ - srl a2, rINST, 12 # a2 <- B - lhu a4, 2(rPC) # a4 <- field byte offset - GET_VREG_U a3, a2 # a3 <- object we're operating on - ext a2, rINST, 8, 4 # a2 <- A - beqz a3, common_errNullObject # object was null - daddu a4, a3, a4 # create direct pointer - lw a0, 0(a4) - lw a1, 4(a4) - dinsu a0, a1, 32, 32 - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - SET_VREG_WIDE a0, a2 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_instance_of.S b/runtime/interpreter/mterp/mips64/op_instance_of.S deleted file mode 100644 index 39a5dc7c265977e398b85a40ca59dcbb245a6ff7..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_instance_of.S +++ /dev/null @@ -1,23 +0,0 @@ - /* - * Check to see if an object reference is an instance of a class. - * - * Most common situation is a non-null object, being compared against - * an already-resolved class. - */ - /* instance-of vA, vB, class//CCCC */ - .extern MterpInstanceOf - EXPORT_PC - lhu a0, 2(rPC) # a0 <- CCCC - srl a1, rINST, 12 # a1 <- B - dlsa a1, a1, rFP, 2 # a1 <- &object - ld a2, OFF_FP_METHOD(rFP) # a2 <- method - move a3, rSELF # a3 <- self - jal MterpInstanceOf # (index, &obj, method, self) - ld a1, THREAD_EXCEPTION_OFFSET(rSELF) - ext a2, rINST, 8, 4 # a2 <- A - PREFETCH_INST 2 - bnez a1, MterpException - ADVANCE 2 # advance rPC - SET_VREG v0, a2 # vA <- v0 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_int_to_byte.S b/runtime/interpreter/mterp/mips64/op_int_to_byte.S deleted file mode 100644 index 1993e076a6cc2bd5ce4ff16f6fb29d7d647a0ad7..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_int_to_byte.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/unop.S" {"instr":"seb a0, a0"} diff --git a/runtime/interpreter/mterp/mips64/op_int_to_char.S b/runtime/interpreter/mterp/mips64/op_int_to_char.S deleted file mode 100644 index 8f03acd3f60100d225d6d803a1f566c02bd9afde..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_int_to_char.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/unop.S" {"instr":"and a0, a0, 0xffff"} diff --git a/runtime/interpreter/mterp/mips64/op_int_to_double.S b/runtime/interpreter/mterp/mips64/op_int_to_double.S deleted file mode 100644 index 6df71be39486ac707da30852b9df717cf6218361..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_int_to_double.S +++ /dev/null @@ -1,8 +0,0 @@ - /* - * Conversion from or to floating-point happens in a floating-point register. - * Therefore we load the input and store the output into or from a - * floating-point register irrespective of the type. - */ -%include "mips64/fcvtHeader.S" { "suffix":"_FLOAT", "valreg":"f0" } - cvt.d.w f0, f0 -%include "mips64/fcvtFooter.S" { "suffix":"_DOUBLE", "valreg":"f0" } diff --git a/runtime/interpreter/mterp/mips64/op_int_to_float.S b/runtime/interpreter/mterp/mips64/op_int_to_float.S deleted file mode 100644 index 77e9eba53ac0fd5e6141e9955787b1c9e1f2d4b4..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_int_to_float.S +++ /dev/null @@ -1,8 +0,0 @@ - /* - * Conversion from or to floating-point happens in a floating-point register. - * Therefore we load the input and store the output into or from a - * floating-point register irrespective of the type. - */ -%include "mips64/fcvtHeader.S" { "suffix":"_FLOAT", "valreg":"f0" } - cvt.s.w f0, f0 -%include "mips64/fcvtFooter.S" { "suffix":"_FLOAT", "valreg":"f0" } diff --git a/runtime/interpreter/mterp/mips64/op_int_to_long.S b/runtime/interpreter/mterp/mips64/op_int_to_long.S deleted file mode 100644 index 7b9ad86fdc8f9b2f427fc0ecf2d2ee03d8d603a3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_int_to_long.S +++ /dev/null @@ -1,8 +0,0 @@ - /* int-to-long vA, vB */ - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a3 # a0 <- vB (sign-extended to 64 bits) - ext a2, rINST, 8, 4 # a2 <- A - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vA <- vB - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_int_to_short.S b/runtime/interpreter/mterp/mips64/op_int_to_short.S deleted file mode 100644 index 4a3f2346cf8ee49967e6e99eb8f1893ee9994e22..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_int_to_short.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/unop.S" {"instr":"seh a0, a0"} diff --git a/runtime/interpreter/mterp/mips64/op_invoke_custom.S b/runtime/interpreter/mterp/mips64/op_invoke_custom.S deleted file mode 100644 index 964253d8b7fc58aa64783aa9271d36394d2684b3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_invoke_custom.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/invoke.S" { "helper":"MterpInvokeCustom" } diff --git a/runtime/interpreter/mterp/mips64/op_invoke_custom_range.S b/runtime/interpreter/mterp/mips64/op_invoke_custom_range.S deleted file mode 100644 index e6585e3646d497af3ce9258153b55d6c0dd5b14c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_invoke_custom_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/invoke.S" { "helper":"MterpInvokeCustomRange" } diff --git a/runtime/interpreter/mterp/mips64/op_invoke_direct.S b/runtime/interpreter/mterp/mips64/op_invoke_direct.S deleted file mode 100644 index 5047118e48aa7b3a51bb09eefbd1d1a6ba1f0f69..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_invoke_direct.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/invoke.S" { "helper":"MterpInvokeDirect" } diff --git a/runtime/interpreter/mterp/mips64/op_invoke_direct_range.S b/runtime/interpreter/mterp/mips64/op_invoke_direct_range.S deleted file mode 100644 index 5c9b95f5be6c47cfaa9b64d430d4b1c9438b6d8c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_invoke_direct_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/invoke.S" { "helper":"MterpInvokeDirectRange" } diff --git a/runtime/interpreter/mterp/mips64/op_invoke_interface.S b/runtime/interpreter/mterp/mips64/op_invoke_interface.S deleted file mode 100644 index ed148adcbb613d34db8001a22547e686e9553f6f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_invoke_interface.S +++ /dev/null @@ -1,8 +0,0 @@ -%include "mips64/invoke.S" { "helper":"MterpInvokeInterface" } - /* - * Handle an interface method call. - * - * for: invoke-interface, invoke-interface/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ diff --git a/runtime/interpreter/mterp/mips64/op_invoke_interface_range.S b/runtime/interpreter/mterp/mips64/op_invoke_interface_range.S deleted file mode 100644 index 91c231e0f4d0138e1b5a754834f93c7c986d1e0d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_invoke_interface_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/invoke.S" { "helper":"MterpInvokeInterfaceRange" } diff --git a/runtime/interpreter/mterp/mips64/op_invoke_polymorphic.S b/runtime/interpreter/mterp/mips64/op_invoke_polymorphic.S deleted file mode 100644 index d9324d73bfd4250613f419dd716f9446452e8e70..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_invoke_polymorphic.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/invoke_polymorphic.S" { "helper":"MterpInvokePolymorphic" } diff --git a/runtime/interpreter/mterp/mips64/op_invoke_polymorphic_range.S b/runtime/interpreter/mterp/mips64/op_invoke_polymorphic_range.S deleted file mode 100644 index 8e0ecb570af580f4899a30ff47658a8c7513c768..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_invoke_polymorphic_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/invoke_polymorphic.S" { "helper":"MterpInvokePolymorphicRange" } diff --git a/runtime/interpreter/mterp/mips64/op_invoke_static.S b/runtime/interpreter/mterp/mips64/op_invoke_static.S deleted file mode 100644 index 44f5cb7a78a6407efd2d1fdf4394c1f0c5f171fb..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_invoke_static.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/invoke.S" { "helper":"MterpInvokeStatic" } diff --git a/runtime/interpreter/mterp/mips64/op_invoke_static_range.S b/runtime/interpreter/mterp/mips64/op_invoke_static_range.S deleted file mode 100644 index 289e5aa97750945bc5d032f50bf05d2bbfe51073..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_invoke_static_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/invoke.S" { "helper":"MterpInvokeStaticRange" } diff --git a/runtime/interpreter/mterp/mips64/op_invoke_super.S b/runtime/interpreter/mterp/mips64/op_invoke_super.S deleted file mode 100644 index b13fffe7144ff3893b4b9b9202ffb5decea5786d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_invoke_super.S +++ /dev/null @@ -1,8 +0,0 @@ -%include "mips64/invoke.S" { "helper":"MterpInvokeSuper" } - /* - * Handle a "super" method call. - * - * for: invoke-super, invoke-super/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ diff --git a/runtime/interpreter/mterp/mips64/op_invoke_super_range.S b/runtime/interpreter/mterp/mips64/op_invoke_super_range.S deleted file mode 100644 index 350b9757ba9a59cc2ecf9cabf6393ccd535321d2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_invoke_super_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/invoke.S" { "helper":"MterpInvokeSuperRange" } diff --git a/runtime/interpreter/mterp/mips64/op_invoke_virtual.S b/runtime/interpreter/mterp/mips64/op_invoke_virtual.S deleted file mode 100644 index 0d26cda812a369e7607dc9b4a0744466b5a5ac5b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_invoke_virtual.S +++ /dev/null @@ -1,8 +0,0 @@ -%include "mips64/invoke.S" { "helper":"MterpInvokeVirtual" } - /* - * Handle a virtual method call. - * - * for: invoke-virtual, invoke-virtual/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ diff --git a/runtime/interpreter/mterp/mips64/op_invoke_virtual_quick.S b/runtime/interpreter/mterp/mips64/op_invoke_virtual_quick.S deleted file mode 100644 index f39562c199cfb937df89466a7139ef3f77b8b02c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_invoke_virtual_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/invoke.S" { "helper":"MterpInvokeVirtualQuick" } diff --git a/runtime/interpreter/mterp/mips64/op_invoke_virtual_range.S b/runtime/interpreter/mterp/mips64/op_invoke_virtual_range.S deleted file mode 100644 index 0bb43f8fccf68066290bcaf0b844949079646968..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_invoke_virtual_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/invoke.S" { "helper":"MterpInvokeVirtualRange" } diff --git a/runtime/interpreter/mterp/mips64/op_invoke_virtual_range_quick.S b/runtime/interpreter/mterp/mips64/op_invoke_virtual_range_quick.S deleted file mode 100644 index c4488513bd9e12c4b7d0baf767e7d83c0797f3af..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_invoke_virtual_range_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/invoke.S" { "helper":"MterpInvokeVirtualQuickRange" } diff --git a/runtime/interpreter/mterp/mips64/op_iput.S b/runtime/interpreter/mterp/mips64/op_iput.S deleted file mode 100644 index 81ab911b5e7923dd571fab5c6fd6b4ba3db6ba82..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_iput.S +++ /dev/null @@ -1,2 +0,0 @@ -%default { "is_object":"0", "helper":"MterpIPutU32" } -%include "mips64/field.S" { } diff --git a/runtime/interpreter/mterp/mips64/op_iput_boolean.S b/runtime/interpreter/mterp/mips64/op_iput_boolean.S deleted file mode 100644 index 8e1d08375993cdc1b8534767795a515e974659bf..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_iput_boolean.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_iput.S" { "helper":"MterpIPutU8" } diff --git a/runtime/interpreter/mterp/mips64/op_iput_boolean_quick.S b/runtime/interpreter/mterp/mips64/op_iput_boolean_quick.S deleted file mode 100644 index df99948e4032f95628421366f3d1298ac31a2de9..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_iput_boolean_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_iput_quick.S" { "store":"sb" } diff --git a/runtime/interpreter/mterp/mips64/op_iput_byte.S b/runtime/interpreter/mterp/mips64/op_iput_byte.S deleted file mode 100644 index ce3b614b0cc47a1204526e359034261030436087..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_iput_byte.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_iput.S" { "helper":"MterpIPutI8" } diff --git a/runtime/interpreter/mterp/mips64/op_iput_byte_quick.S b/runtime/interpreter/mterp/mips64/op_iput_byte_quick.S deleted file mode 100644 index df99948e4032f95628421366f3d1298ac31a2de9..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_iput_byte_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_iput_quick.S" { "store":"sb" } diff --git a/runtime/interpreter/mterp/mips64/op_iput_char.S b/runtime/interpreter/mterp/mips64/op_iput_char.S deleted file mode 100644 index 1d587fad6b1311970980814576bb1714ff29e8d0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_iput_char.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_iput.S" { "helper":"MterpIPutU16" } diff --git a/runtime/interpreter/mterp/mips64/op_iput_char_quick.S b/runtime/interpreter/mterp/mips64/op_iput_char_quick.S deleted file mode 100644 index a6286b7b970fe268cfb8c78cc4dbb70e22f54582..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_iput_char_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_iput_quick.S" { "store":"sh" } diff --git a/runtime/interpreter/mterp/mips64/op_iput_object.S b/runtime/interpreter/mterp/mips64/op_iput_object.S deleted file mode 100644 index d3316dd7567344e8170befe23a1472d38df9278d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_iput_object.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_iput.S" { "is_object":"1", "helper":"MterpIPutObj" } diff --git a/runtime/interpreter/mterp/mips64/op_iput_object_quick.S b/runtime/interpreter/mterp/mips64/op_iput_object_quick.S deleted file mode 100644 index 658ef42a190c466715c968eacbd86baf788b1079..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_iput_object_quick.S +++ /dev/null @@ -1,10 +0,0 @@ - .extern MterpIputObjectQuick - EXPORT_PC - daddu a0, rFP, OFF_FP_SHADOWFRAME - move a1, rPC - move a2, rINST - jal MterpIputObjectQuick - beqzc v0, MterpException - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_iput_quick.S b/runtime/interpreter/mterp/mips64/op_iput_quick.S deleted file mode 100644 index b95adfcd4fe8f14d1a7de9981fab3d5b9e2e1ae8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_iput_quick.S +++ /dev/null @@ -1,14 +0,0 @@ -%default { "store":"sw" } - /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */ - /* op vA, vB, offset//CCCC */ - srl a2, rINST, 12 # a2 <- B - lhu a1, 2(rPC) # a1 <- field byte offset - GET_VREG_U a3, a2 # a3 <- fp[B], the object pointer - ext a2, rINST, 8, 4 # a2 <- A - beqz a3, common_errNullObject # object was null - GET_VREG a0, a2 # a0 <- fp[A] - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - daddu a1, a1, a3 - $store a0, 0(a1) # obj.field <- a0 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_iput_short.S b/runtime/interpreter/mterp/mips64/op_iput_short.S deleted file mode 100644 index dd68bbeaaa72b0068b3568991699e6a8d3be8467..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_iput_short.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_iput.S" { "helper":"MterpIPutI16" } diff --git a/runtime/interpreter/mterp/mips64/op_iput_short_quick.S b/runtime/interpreter/mterp/mips64/op_iput_short_quick.S deleted file mode 100644 index a6286b7b970fe268cfb8c78cc4dbb70e22f54582..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_iput_short_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_iput_quick.S" { "store":"sh" } diff --git a/runtime/interpreter/mterp/mips64/op_iput_wide.S b/runtime/interpreter/mterp/mips64/op_iput_wide.S deleted file mode 100644 index 05194b33f33c7846cf997682481ea27309a571f8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_iput_wide.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_iput.S" { "helper":"MterpIPutU64" } diff --git a/runtime/interpreter/mterp/mips64/op_iput_wide_quick.S b/runtime/interpreter/mterp/mips64/op_iput_wide_quick.S deleted file mode 100644 index 95a8ad8f9c14178aee611081f6a27bacf69f99c0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_iput_wide_quick.S +++ /dev/null @@ -1,14 +0,0 @@ - /* iput-wide-quick vA, vB, offset//CCCC */ - srl a2, rINST, 12 # a2 <- B - lhu a3, 2(rPC) # a3 <- field byte offset - GET_VREG_U a2, a2 # a2 <- fp[B], the object pointer - ext a0, rINST, 8, 4 # a0 <- A - beqz a2, common_errNullObject # object was null - GET_VREG_WIDE a0, a0 # a0 <- fp[A] - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - daddu a1, a2, a3 # create a direct pointer - sw a0, 0(a1) - dsrl32 a0, a0, 0 - sw a0, 4(a1) - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_long_to_double.S b/runtime/interpreter/mterp/mips64/op_long_to_double.S deleted file mode 100644 index 8503e769b9b6b20a7435203fee0556f178cf56cb..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_long_to_double.S +++ /dev/null @@ -1,8 +0,0 @@ - /* - * Conversion from or to floating-point happens in a floating-point register. - * Therefore we load the input and store the output into or from a - * floating-point register irrespective of the type. - */ -%include "mips64/fcvtHeader.S" { "suffix":"_DOUBLE", "valreg":"f0" } - cvt.d.l f0, f0 -%include "mips64/fcvtFooter.S" { "suffix":"_DOUBLE", "valreg":"f0" } diff --git a/runtime/interpreter/mterp/mips64/op_long_to_float.S b/runtime/interpreter/mterp/mips64/op_long_to_float.S deleted file mode 100644 index 31f5c0e9b02653a342cc090ff6245edac42c747a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_long_to_float.S +++ /dev/null @@ -1,8 +0,0 @@ - /* - * Conversion from or to floating-point happens in a floating-point register. - * Therefore we load the input and store the output into or from a - * floating-point register irrespective of the type. - */ -%include "mips64/fcvtHeader.S" { "suffix":"_DOUBLE", "valreg":"f0" } - cvt.s.l f0, f0 -%include "mips64/fcvtFooter.S" { "suffix":"_FLOAT", "valreg":"f0" } diff --git a/runtime/interpreter/mterp/mips64/op_long_to_int.S b/runtime/interpreter/mterp/mips64/op_long_to_int.S deleted file mode 100644 index 4ef4b512dce23f3433e0b65eda0bebbe6d8883d9..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_long_to_int.S +++ /dev/null @@ -1,2 +0,0 @@ -/* we ignore the high word, making this equivalent to a 32-bit reg move */ -%include "mips64/op_move.S" diff --git a/runtime/interpreter/mterp/mips64/op_monitor_enter.S b/runtime/interpreter/mterp/mips64/op_monitor_enter.S deleted file mode 100644 index 36ae50346e611bf6297b858763f9d6864feef1b5..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_monitor_enter.S +++ /dev/null @@ -1,14 +0,0 @@ - /* - * Synchronize on an object. - */ - /* monitor-enter vAA */ - .extern artLockObjectFromCode - EXPORT_PC - srl a2, rINST, 8 # a2 <- AA - GET_VREG_U a0, a2 # a0 <- vAA (object) - move a1, rSELF # a1 <- self - jal artLockObjectFromCode - bnezc v0, MterpException - FETCH_ADVANCE_INST 1 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_monitor_exit.S b/runtime/interpreter/mterp/mips64/op_monitor_exit.S deleted file mode 100644 index 99459520179587f907eeb0fdd2b24eff28028c85..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_monitor_exit.S +++ /dev/null @@ -1,18 +0,0 @@ - /* - * Unlock an object. - * - * Exceptions that occur when unlocking a monitor need to appear as - * if they happened at the following instruction. See the Dalvik - * instruction spec. - */ - /* monitor-exit vAA */ - .extern artUnlockObjectFromCode - EXPORT_PC - srl a2, rINST, 8 # a2 <- AA - GET_VREG_U a0, a2 # a0 <- vAA (object) - move a1, rSELF # a1 <- self - jal artUnlockObjectFromCode # v0 <- success for unlock(self, obj) - bnezc v0, MterpException - FETCH_ADVANCE_INST 1 # before throw: advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_move.S b/runtime/interpreter/mterp/mips64/op_move.S deleted file mode 100644 index c79f6cde8d4ccc632861a745bb3371fb2b047351..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_move.S +++ /dev/null @@ -1,14 +0,0 @@ -%default { "is_object":"0" } - /* for move, move-object, long-to-int */ - /* op vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_VREG a0, a3 # a0 <- vB - GET_INST_OPCODE v0 # extract opcode from rINST - .if $is_object - SET_VREG_OBJECT a0, a2 # vA <- vB - .else - SET_VREG a0, a2 # vA <- vB - .endif - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_move_16.S b/runtime/interpreter/mterp/mips64/op_move_16.S deleted file mode 100644 index 9d5c4dce8cf2a60af2980f21c2858cc1617610da..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_move_16.S +++ /dev/null @@ -1,14 +0,0 @@ -%default { "is_object":"0" } - /* for: move/16, move-object/16 */ - /* op vAAAA, vBBBB */ - lhu a3, 4(rPC) # a3 <- BBBB - lhu a2, 2(rPC) # a2 <- AAAA - FETCH_ADVANCE_INST 3 # advance rPC, load rINST - GET_VREG a0, a3 # a0 <- vBBBB - GET_INST_OPCODE v0 # extract opcode from rINST - .if $is_object - SET_VREG_OBJECT a0, a2 # vAAAA <- vBBBB - .else - SET_VREG a0, a2 # vAAAA <- vBBBB - .endif - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_move_exception.S b/runtime/interpreter/mterp/mips64/op_move_exception.S deleted file mode 100644 index d226718c8f67cf80f40cc370a086d6615a239fe8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_move_exception.S +++ /dev/null @@ -1,8 +0,0 @@ - /* move-exception vAA */ - srl a2, rINST, 8 # a2 <- AA - ld a0, THREAD_EXCEPTION_OFFSET(rSELF) # load exception obj - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - SET_VREG_OBJECT a0, a2 # vAA <- exception obj - GET_INST_OPCODE v0 # extract opcode from rINST - sd zero, THREAD_EXCEPTION_OFFSET(rSELF) # clear exception - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_move_from16.S b/runtime/interpreter/mterp/mips64/op_move_from16.S deleted file mode 100644 index 6d6bde007fd6a36dd0a64c68f92ab119abe87f5e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_move_from16.S +++ /dev/null @@ -1,14 +0,0 @@ -%default { "is_object":"0" } - /* for: move/from16, move-object/from16 */ - /* op vAA, vBBBB */ - lhu a3, 2(rPC) # a3 <- BBBB - srl a2, rINST, 8 # a2 <- AA - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_VREG a0, a3 # a0 <- vBBBB - GET_INST_OPCODE v0 # extract opcode from rINST - .if $is_object - SET_VREG_OBJECT a0, a2 # vAA <- vBBBB - .else - SET_VREG a0, a2 # vAA <- vBBBB - .endif - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_move_object.S b/runtime/interpreter/mterp/mips64/op_move_object.S deleted file mode 100644 index 47e0272a6c4c22f7c5d47705e7bb23cb8f0dc19e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_move_object.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_move.S" {"is_object":"1"} diff --git a/runtime/interpreter/mterp/mips64/op_move_object_16.S b/runtime/interpreter/mterp/mips64/op_move_object_16.S deleted file mode 100644 index a777dcdaf863b807388dcc3dcc7c28bee1c976f3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_move_object_16.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_move_16.S" {"is_object":"1"} diff --git a/runtime/interpreter/mterp/mips64/op_move_object_from16.S b/runtime/interpreter/mterp/mips64/op_move_object_from16.S deleted file mode 100644 index ab55ebd646f5b916ff150d5785c095923297017a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_move_object_from16.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_move_from16.S" {"is_object":"1"} diff --git a/runtime/interpreter/mterp/mips64/op_move_result.S b/runtime/interpreter/mterp/mips64/op_move_result.S deleted file mode 100644 index 1ec28cb6d8820be81703e18cf90cfcc4a2815118..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_move_result.S +++ /dev/null @@ -1,14 +0,0 @@ -%default { "is_object":"0" } - /* for: move-result, move-result-object */ - /* op vAA */ - srl a2, rINST, 8 # a2 <- AA - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - ld a0, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType - lw a0, 0(a0) # a0 <- result.i - GET_INST_OPCODE v0 # extract opcode from rINST - .if $is_object - SET_VREG_OBJECT a0, a2 # vAA <- result - .else - SET_VREG a0, a2 # vAA <- result - .endif - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_move_result_object.S b/runtime/interpreter/mterp/mips64/op_move_result_object.S deleted file mode 100644 index e76bc22c1124d42304dd88fa69b256ca6e2b55c3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_move_result_object.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_move_result.S" {"is_object":"1"} diff --git a/runtime/interpreter/mterp/mips64/op_move_result_wide.S b/runtime/interpreter/mterp/mips64/op_move_result_wide.S deleted file mode 100644 index 3ba0d7288b588cfe2f6a320f23989671e19942c4..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_move_result_wide.S +++ /dev/null @@ -1,9 +0,0 @@ - /* for: move-result-wide */ - /* op vAA */ - srl a2, rINST, 8 # a2 <- AA - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - ld a0, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType - ld a0, 0(a0) # a0 <- result.j - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vAA <- result - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_move_wide.S b/runtime/interpreter/mterp/mips64/op_move_wide.S deleted file mode 100644 index ea23f87ff025daee4e3c3434bf16e0e10290a09f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_move_wide.S +++ /dev/null @@ -1,9 +0,0 @@ - /* move-wide vA, vB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - ext a3, rINST, 12, 4 # a3 <- B - ext a2, rINST, 8, 4 # a2 <- A - GET_VREG_WIDE a0, a3 # a0 <- vB - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vA <- vB - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_move_wide_16.S b/runtime/interpreter/mterp/mips64/op_move_wide_16.S deleted file mode 100644 index 8ec606834b9d0f5d6efb2cc2502ea13115e1bbb6..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_move_wide_16.S +++ /dev/null @@ -1,9 +0,0 @@ - /* move-wide/16 vAAAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - lhu a3, 4(rPC) # a3 <- BBBB - lhu a2, 2(rPC) # a2 <- AAAA - GET_VREG_WIDE a0, a3 # a0 <- vBBBB - FETCH_ADVANCE_INST 3 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vAAAA <- vBBBB - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_move_wide_from16.S b/runtime/interpreter/mterp/mips64/op_move_wide_from16.S deleted file mode 100644 index 11d5603fe135b6cb33637ead73d3910fb8e7d8f3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_move_wide_from16.S +++ /dev/null @@ -1,9 +0,0 @@ - /* move-wide/from16 vAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - lhu a3, 2(rPC) # a3 <- BBBB - srl a2, rINST, 8 # a2 <- AA - GET_VREG_WIDE a0, a3 # a0 <- vBBBB - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vAA <- vBBBB - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_mul_double.S b/runtime/interpreter/mterp/mips64/op_mul_double.S deleted file mode 100644 index e7e17f7ece518e0fb02652b3c4bcb0f798365fe2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_mul_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/fbinopWide.S" {"instr":"mul.d f0, f0, f1"} diff --git a/runtime/interpreter/mterp/mips64/op_mul_double_2addr.S b/runtime/interpreter/mterp/mips64/op_mul_double_2addr.S deleted file mode 100644 index f404d4688d3fbcc2ea79fc128bda136e7c5c42ed..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_mul_double_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/fbinopWide2addr.S" {"instr":"mul.d f0, f0, f1"} diff --git a/runtime/interpreter/mterp/mips64/op_mul_float.S b/runtime/interpreter/mterp/mips64/op_mul_float.S deleted file mode 100644 index 9a695fca1682dd0a211cfee501e584e61240e70b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_mul_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/fbinop.S" {"instr":"mul.s f0, f0, f1"} diff --git a/runtime/interpreter/mterp/mips64/op_mul_float_2addr.S b/runtime/interpreter/mterp/mips64/op_mul_float_2addr.S deleted file mode 100644 index a134a34253be231c0e1e58885611297035fc2bf7..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_mul_float_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/fbinop2addr.S" {"instr":"mul.s f0, f0, f1"} diff --git a/runtime/interpreter/mterp/mips64/op_mul_int.S b/runtime/interpreter/mterp/mips64/op_mul_int.S deleted file mode 100644 index e1b90ff4e920429e85f1c35f0fe33fb7a57cc830..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_mul_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binop.S" {"instr":"mul a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_mul_int_2addr.S b/runtime/interpreter/mterp/mips64/op_mul_int_2addr.S deleted file mode 100644 index c0c4063d548ed1c9ea90e54a3369125db8df17d6..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_mul_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binop2addr.S" {"instr":"mul a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_mul_int_lit16.S b/runtime/interpreter/mterp/mips64/op_mul_int_lit16.S deleted file mode 100644 index bb4fff874703c0832692252e10e203007a197e57..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_mul_int_lit16.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binopLit16.S" {"instr":"mul a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_mul_int_lit8.S b/runtime/interpreter/mterp/mips64/op_mul_int_lit8.S deleted file mode 100644 index da11ea9295738537ecf2ce06d8d0602fdd506f5b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_mul_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binopLit8.S" {"instr":"mul a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_mul_long.S b/runtime/interpreter/mterp/mips64/op_mul_long.S deleted file mode 100644 index ec3285060632eb4a9e899f6df113cded816ea898..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_mul_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binopWide.S" {"instr":"dmul a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_mul_long_2addr.S b/runtime/interpreter/mterp/mips64/op_mul_long_2addr.S deleted file mode 100644 index eb50cda03ce18ee3e856063642f0e95e6914b4c3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_mul_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binopWide2addr.S" {"instr":"dmul a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_neg_double.S b/runtime/interpreter/mterp/mips64/op_neg_double.S deleted file mode 100644 index a135d611730fe62fb785af5d59f18f6aa2a61a77..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_neg_double.S +++ /dev/null @@ -1,3 +0,0 @@ -%include "mips64/fcvtHeader.S" { "suffix":"_DOUBLE", "valreg":"f0" } - neg.d f0, f0 -%include "mips64/fcvtFooter.S" { "suffix":"_DOUBLE", "valreg":"f0" } diff --git a/runtime/interpreter/mterp/mips64/op_neg_float.S b/runtime/interpreter/mterp/mips64/op_neg_float.S deleted file mode 100644 index 78019f03d8ef872724a2d98ba896e29adab6ca4b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_neg_float.S +++ /dev/null @@ -1,3 +0,0 @@ -%include "mips64/fcvtHeader.S" { "suffix":"_FLOAT", "valreg":"f0" } - neg.s f0, f0 -%include "mips64/fcvtFooter.S" { "suffix":"_FLOAT", "valreg":"f0" } diff --git a/runtime/interpreter/mterp/mips64/op_neg_int.S b/runtime/interpreter/mterp/mips64/op_neg_int.S deleted file mode 100644 index 31538c0caa2cf5ef1c4fc76be261f3be1af1160a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_neg_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/unop.S" {"instr":"subu a0, zero, a0"} diff --git a/runtime/interpreter/mterp/mips64/op_neg_long.S b/runtime/interpreter/mterp/mips64/op_neg_long.S deleted file mode 100644 index bc80d0623f19576d16c7419d7750e8dae9d0ec1d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_neg_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/unopWide.S" {"instr":"dsubu a0, zero, a0"} diff --git a/runtime/interpreter/mterp/mips64/op_new_array.S b/runtime/interpreter/mterp/mips64/op_new_array.S deleted file mode 100644 index d78b4ac32ef4a0024cba32559fb6f1cf55641250..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_new_array.S +++ /dev/null @@ -1,19 +0,0 @@ - /* - * Allocate an array of objects, specified with the array class - * and a count. - * - * The verifier guarantees that this is an array class, so we don't - * check for it here. - */ - /* new-array vA, vB, class//CCCC */ - .extern MterpNewArray - EXPORT_PC - daddu a0, rFP, OFF_FP_SHADOWFRAME - move a1, rPC - move a2, rINST - move a3, rSELF - jal MterpNewArray - beqzc v0, MterpPossibleException - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_new_instance.S b/runtime/interpreter/mterp/mips64/op_new_instance.S deleted file mode 100644 index cc5e13e00d201aeefc2c5f17b42f5b628ed8707d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_new_instance.S +++ /dev/null @@ -1,14 +0,0 @@ - /* - * Create a new instance of a class. - */ - /* new-instance vAA, class//BBBB */ - .extern MterpNewInstance - EXPORT_PC - daddu a0, rFP, OFF_FP_SHADOWFRAME - move a1, rSELF - move a2, rINST - jal MterpNewInstance # (shadow_frame, self, inst_data) - beqzc v0, MterpPossibleException - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_nop.S b/runtime/interpreter/mterp/mips64/op_nop.S deleted file mode 100644 index cc803a791a6e3100800aca2bbe461c2c78aa5f0c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_nop.S +++ /dev/null @@ -1,3 +0,0 @@ - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_not_int.S b/runtime/interpreter/mterp/mips64/op_not_int.S deleted file mode 100644 index 59540950cdb0efc5008007ef5775e7e9d2a038f6..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_not_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/unop.S" {"instr":"nor a0, zero, a0"} diff --git a/runtime/interpreter/mterp/mips64/op_not_long.S b/runtime/interpreter/mterp/mips64/op_not_long.S deleted file mode 100644 index c8f5da7e82aff11647de579c125e7a9d11e1c773..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_not_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/unopWide.S" {"instr":"nor a0, zero, a0"} diff --git a/runtime/interpreter/mterp/mips64/op_or_int.S b/runtime/interpreter/mterp/mips64/op_or_int.S deleted file mode 100644 index 0102355c55d137d4b69f46e289f247056fa4d368..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_or_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binop.S" {"instr":"or a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_or_int_2addr.S b/runtime/interpreter/mterp/mips64/op_or_int_2addr.S deleted file mode 100644 index eed89008c048dc2e084b201d6720c868b507431e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_or_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binop2addr.S" {"instr":"or a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_or_int_lit16.S b/runtime/interpreter/mterp/mips64/op_or_int_lit16.S deleted file mode 100644 index 16a0f3e1a22f7847bf963ed74b108fee4fade095..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_or_int_lit16.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binopLit16.S" {"instr":"or a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_or_int_lit8.S b/runtime/interpreter/mterp/mips64/op_or_int_lit8.S deleted file mode 100644 index dbbf7904c6a4a8b424d8cb557e931ecc78bd0a3f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_or_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binopLit8.S" {"instr":"or a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_or_long.S b/runtime/interpreter/mterp/mips64/op_or_long.S deleted file mode 100644 index e6f8639e5258e71488d41cf57e70152124031557..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_or_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binopWide.S" {"instr":"or a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_or_long_2addr.S b/runtime/interpreter/mterp/mips64/op_or_long_2addr.S deleted file mode 100644 index ad5e6c8e993d1625606df57ec4306a1a6a5017d0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_or_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binopWide2addr.S" {"instr":"or a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_packed_switch.S b/runtime/interpreter/mterp/mips64/op_packed_switch.S deleted file mode 100644 index 44e77a41d89c62336e7d2dce5decf508097acd15..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_packed_switch.S +++ /dev/null @@ -1,21 +0,0 @@ -%default { "func":"MterpDoPackedSwitch" } - /* - * Handle a packed-switch or sparse-switch instruction. In both cases - * we decode it and hand it off to a helper function. - * - * We don't really expect backward branches in a switch statement, but - * they're perfectly legal, so we check for them here. - * - * for: packed-switch, sparse-switch - */ - /* op vAA, +BBBBBBBB */ - .extern $func - lh a0, 2(rPC) # a0 <- bbbb (lo) - lh a1, 4(rPC) # a1 <- BBBB (hi) - srl a3, rINST, 8 # a3 <- AA - ins a0, a1, 16, 16 # a0 <- BBBBbbbb - GET_VREG a1, a3 # a1 <- vAA - dlsa a0, a0, rPC, 1 # a0 <- PC + BBBBbbbb*2 - jal $func # v0 <- code-unit branch offset - move rINST, v0 - b MterpCommonTakenBranchNoFlags diff --git a/runtime/interpreter/mterp/mips64/op_rem_double.S b/runtime/interpreter/mterp/mips64/op_rem_double.S deleted file mode 100644 index ba61cfdc71a12078072b52ea13108e8aeda41086..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_rem_double.S +++ /dev/null @@ -1,12 +0,0 @@ - /* rem-double vAA, vBB, vCC */ - .extern fmod - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_DOUBLE f12, a2 # f12 <- vBB - GET_VREG_DOUBLE f13, a3 # f13 <- vCC - jal fmod # f0 <- f12 op f13 - srl a4, rINST, 8 # a4 <- AA - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_DOUBLE f0, a4 # vAA <- f0 - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_rem_double_2addr.S b/runtime/interpreter/mterp/mips64/op_rem_double_2addr.S deleted file mode 100644 index c649f0d62cef2139ed0c7a4a8ad7210658088f26..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_rem_double_2addr.S +++ /dev/null @@ -1,12 +0,0 @@ - /* rem-double/2addr vA, vB */ - .extern fmod - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_DOUBLE f12, a2 # f12 <- vA - GET_VREG_DOUBLE f13, a3 # f13 <- vB - jal fmod # f0 <- f12 op f13 - ext a2, rINST, 8, 4 # a2 <- A - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_DOUBLE f0, a2 # vA <- f0 - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_rem_float.S b/runtime/interpreter/mterp/mips64/op_rem_float.S deleted file mode 100644 index 3967b0b02c2cfa73dee3e2290efad02419b58542..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_rem_float.S +++ /dev/null @@ -1,12 +0,0 @@ - /* rem-float vAA, vBB, vCC */ - .extern fmodf - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_FLOAT f12, a2 # f12 <- vBB - GET_VREG_FLOAT f13, a3 # f13 <- vCC - jal fmodf # f0 <- f12 op f13 - srl a4, rINST, 8 # a4 <- AA - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_FLOAT f0, a4 # vAA <- f0 - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_rem_float_2addr.S b/runtime/interpreter/mterp/mips64/op_rem_float_2addr.S deleted file mode 100644 index 3fed41e8510985d1fbd2c4b9959a3977ae81f266..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_rem_float_2addr.S +++ /dev/null @@ -1,12 +0,0 @@ - /* rem-float/2addr vA, vB */ - .extern fmodf - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_FLOAT f12, a2 # f12 <- vA - GET_VREG_FLOAT f13, a3 # f13 <- vB - jal fmodf # f0 <- f12 op f13 - ext a2, rINST, 8, 4 # a2 <- A - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_FLOAT f0, a2 # vA <- f0 - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/op_rem_int.S b/runtime/interpreter/mterp/mips64/op_rem_int.S deleted file mode 100644 index c05e9c49fcf0b3ccbfc03743640e244f013a6207..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_rem_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binop.S" {"instr":"mod a0, a0, a1", "chkzero":"1"} diff --git a/runtime/interpreter/mterp/mips64/op_rem_int_2addr.S b/runtime/interpreter/mterp/mips64/op_rem_int_2addr.S deleted file mode 100644 index a4e162d3fa0d9a130b18bc959a4b1c4859584121..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_rem_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binop2addr.S" {"instr":"mod a0, a0, a1", "chkzero":"1"} diff --git a/runtime/interpreter/mterp/mips64/op_rem_int_lit16.S b/runtime/interpreter/mterp/mips64/op_rem_int_lit16.S deleted file mode 100644 index 3284f1473c7de5e54c0a3ca04546bcbe9684973b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_rem_int_lit16.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binopLit16.S" {"instr":"mod a0, a0, a1", "chkzero":"1"} diff --git a/runtime/interpreter/mterp/mips64/op_rem_int_lit8.S b/runtime/interpreter/mterp/mips64/op_rem_int_lit8.S deleted file mode 100644 index 1e6a584be52af5da3fb60b7c8144c5eed2fa82f9..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_rem_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binopLit8.S" {"instr":"mod a0, a0, a1", "chkzero":"1"} diff --git a/runtime/interpreter/mterp/mips64/op_rem_long.S b/runtime/interpreter/mterp/mips64/op_rem_long.S deleted file mode 100644 index 32b2d1916dcde7cb454c4db4de4891c39b92210d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_rem_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binopWide.S" {"instr":"dmod a0, a0, a1", "chkzero":"1"} diff --git a/runtime/interpreter/mterp/mips64/op_rem_long_2addr.S b/runtime/interpreter/mterp/mips64/op_rem_long_2addr.S deleted file mode 100644 index ad658e1fde096e23b714004dd9517a02c63d2497..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_rem_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binopWide2addr.S" {"instr":"dmod a0, a0, a1", "chkzero":"1"} diff --git a/runtime/interpreter/mterp/mips64/op_return.S b/runtime/interpreter/mterp/mips64/op_return.S deleted file mode 100644 index edd795f561e5451c8eb9211ca7340743bec84710..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_return.S +++ /dev/null @@ -1,19 +0,0 @@ -%default {"instr":"GET_VREG"} - /* - * Return a 32-bit value. - * - * for: return (sign-extend), return-object (zero-extend) - */ - /* op vAA */ - .extern MterpThreadFenceForConstructor - .extern MterpSuspendCheck - jal MterpThreadFenceForConstructor - lw ra, THREAD_FLAGS_OFFSET(rSELF) - move a0, rSELF - and ra, ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - beqzc ra, 1f - jal MterpSuspendCheck # (self) -1: - srl a2, rINST, 8 # a2 <- AA - $instr a0, a2 # a0 <- vAA - b MterpReturn diff --git a/runtime/interpreter/mterp/mips64/op_return_object.S b/runtime/interpreter/mterp/mips64/op_return_object.S deleted file mode 100644 index b69b8806d1c8ec8b474dd7d5da03eaa5caa48920..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_return_object.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_return.S" {"instr":"GET_VREG_U"} diff --git a/runtime/interpreter/mterp/mips64/op_return_void.S b/runtime/interpreter/mterp/mips64/op_return_void.S deleted file mode 100644 index f6eee915a5c340d348b82a181fe3bdc928a312f8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_return_void.S +++ /dev/null @@ -1,11 +0,0 @@ - .extern MterpThreadFenceForConstructor - .extern MterpSuspendCheck - jal MterpThreadFenceForConstructor - lw ra, THREAD_FLAGS_OFFSET(rSELF) - move a0, rSELF - and ra, ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - beqzc ra, 1f - jal MterpSuspendCheck # (self) -1: - li a0, 0 - b MterpReturn diff --git a/runtime/interpreter/mterp/mips64/op_return_void_no_barrier.S b/runtime/interpreter/mterp/mips64/op_return_void_no_barrier.S deleted file mode 100644 index 4e9b6402268b25a4a2aaae0854642610402ea3f7..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_return_void_no_barrier.S +++ /dev/null @@ -1,9 +0,0 @@ - .extern MterpSuspendCheck - lw ra, THREAD_FLAGS_OFFSET(rSELF) - move a0, rSELF - and ra, ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - beqzc ra, 1f - jal MterpSuspendCheck # (self) -1: - li a0, 0 - b MterpReturn diff --git a/runtime/interpreter/mterp/mips64/op_return_wide.S b/runtime/interpreter/mterp/mips64/op_return_wide.S deleted file mode 100644 index 91ca1fae59e0b775d803c8c9b6c66d8e39055e9d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_return_wide.S +++ /dev/null @@ -1,17 +0,0 @@ - /* - * Return a 64-bit value. - */ - /* return-wide vAA */ - /* op vAA */ - .extern MterpThreadFenceForConstructor - .extern MterpSuspendCheck - jal MterpThreadFenceForConstructor - lw ra, THREAD_FLAGS_OFFSET(rSELF) - move a0, rSELF - and ra, ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - beqzc ra, 1f - jal MterpSuspendCheck # (self) -1: - srl a2, rINST, 8 # a2 <- AA - GET_VREG_WIDE a0, a2 # a0 <- vAA - b MterpReturn diff --git a/runtime/interpreter/mterp/mips64/op_rsub_int.S b/runtime/interpreter/mterp/mips64/op_rsub_int.S deleted file mode 100644 index fa31a0af5fa14c92ca6b4277d04c05e2412050f3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_rsub_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binopLit16.S" {"instr":"subu a0, a1, a0"} diff --git a/runtime/interpreter/mterp/mips64/op_rsub_int_lit8.S b/runtime/interpreter/mterp/mips64/op_rsub_int_lit8.S deleted file mode 100644 index c31ff32060ebf13c62b787a5f88ade40c00f7914..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_rsub_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binopLit8.S" {"instr":"subu a0, a1, a0"} diff --git a/runtime/interpreter/mterp/mips64/op_sget.S b/runtime/interpreter/mterp/mips64/op_sget.S deleted file mode 100644 index 200da35a12ad640109be25f849609883c27150bd..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_sget.S +++ /dev/null @@ -1,2 +0,0 @@ -%default { "is_object":"0", "helper":"MterpSGetU32" } -%include "mips64/field.S" { } diff --git a/runtime/interpreter/mterp/mips64/op_sget_boolean.S b/runtime/interpreter/mterp/mips64/op_sget_boolean.S deleted file mode 100644 index 8abb396c579fda7e209bebeb8c0a47177644510a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_sget_boolean.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_sget.S" {"helper":"MterpSGetU8"} diff --git a/runtime/interpreter/mterp/mips64/op_sget_byte.S b/runtime/interpreter/mterp/mips64/op_sget_byte.S deleted file mode 100644 index 68623f604c450923aa455a32f3bf6e0a39b0b466..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_sget_byte.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_sget.S" {"helper":"MterpSGetI8"} diff --git a/runtime/interpreter/mterp/mips64/op_sget_char.S b/runtime/interpreter/mterp/mips64/op_sget_char.S deleted file mode 100644 index 3c7b9628135f76e0e75a3436e66981a82513a86e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_sget_char.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_sget.S" {"helper":"MterpSGetU16"} diff --git a/runtime/interpreter/mterp/mips64/op_sget_object.S b/runtime/interpreter/mterp/mips64/op_sget_object.S deleted file mode 100644 index 3b260e6ee200a2cec49f725c0a0c0bcb3ea3cc51..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_sget_object.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_sget.S" {"is_object":"1", "helper":"MterpSGetObj"} diff --git a/runtime/interpreter/mterp/mips64/op_sget_short.S b/runtime/interpreter/mterp/mips64/op_sget_short.S deleted file mode 100644 index 9a8579ba5b00ee3312075c4d8596b037e6ea5e7d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_sget_short.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_sget.S" {"helper":"MterpSGetI16"} diff --git a/runtime/interpreter/mterp/mips64/op_sget_wide.S b/runtime/interpreter/mterp/mips64/op_sget_wide.S deleted file mode 100644 index 14f232c0739b24292042560d2bd1b9164fd2a0cb..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_sget_wide.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_sget.S" {"helper":"MterpSGetU64"} diff --git a/runtime/interpreter/mterp/mips64/op_shl_int.S b/runtime/interpreter/mterp/mips64/op_shl_int.S deleted file mode 100644 index 784481f335df310a6e90760bb53d9b52690c7130..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_shl_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binop.S" {"instr":"sll a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_shl_int_2addr.S b/runtime/interpreter/mterp/mips64/op_shl_int_2addr.S deleted file mode 100644 index a6c8a78ff683eccdd6bc9a43f05a912528bd8176..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_shl_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binop2addr.S" {"instr":"sll a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_shl_int_lit8.S b/runtime/interpreter/mterp/mips64/op_shl_int_lit8.S deleted file mode 100644 index 36ef207edf94e456a97c540c6b3715ffd5dea981..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_shl_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binopLit8.S" {"instr":"sll a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_shl_long.S b/runtime/interpreter/mterp/mips64/op_shl_long.S deleted file mode 100644 index 225a2cbc2a945895c9cce3d7302afb48a6c9e1dc..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_shl_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binopWide.S" {"instr":"dsll a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_shl_long_2addr.S b/runtime/interpreter/mterp/mips64/op_shl_long_2addr.S deleted file mode 100644 index c04d8823f4fb4a352f9b9270f9ae47a5d2279f0a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_shl_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binopWide2addr.S" {"instr":"dsll a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_shr_int.S b/runtime/interpreter/mterp/mips64/op_shr_int.S deleted file mode 100644 index eded0373b14c04100c0e50f6d6fdf3d0e55bcc11..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_shr_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binop.S" {"instr":"sra a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_shr_int_2addr.S b/runtime/interpreter/mterp/mips64/op_shr_int_2addr.S deleted file mode 100644 index 5b4d96f187bb64837999bb68874c22bcf44e1ec2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_shr_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binop2addr.S" {"instr":"sra a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_shr_int_lit8.S b/runtime/interpreter/mterp/mips64/op_shr_int_lit8.S deleted file mode 100644 index 175eb8633af6e62b02f0a9df00a19abb3b502456..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_shr_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binopLit8.S" {"instr":"sra a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_shr_long.S b/runtime/interpreter/mterp/mips64/op_shr_long.S deleted file mode 100644 index 0db38c8510f4cf90ed4d8cc5052e81aa433f9e6b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_shr_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binopWide.S" {"instr":"dsra a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_shr_long_2addr.S b/runtime/interpreter/mterp/mips64/op_shr_long_2addr.S deleted file mode 100644 index 48131ad7e47b7c93f3d7e7a5b32a098d2ae26c93..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_shr_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binopWide2addr.S" {"instr":"dsra a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_sparse_switch.S b/runtime/interpreter/mterp/mips64/op_sparse_switch.S deleted file mode 100644 index b065aaa95b3f915f2ecdf30b5ae52e47b2bce475..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_sparse_switch.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_packed_switch.S" { "func":"MterpDoSparseSwitch" } diff --git a/runtime/interpreter/mterp/mips64/op_sput.S b/runtime/interpreter/mterp/mips64/op_sput.S deleted file mode 100644 index 0bd683767ff64fa3061650473e20c960adf02380..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_sput.S +++ /dev/null @@ -1,2 +0,0 @@ -%default { "is_object":"0", "helper":"MterpSPutU32"} -%include "mips64/field.S" { } diff --git a/runtime/interpreter/mterp/mips64/op_sput_boolean.S b/runtime/interpreter/mterp/mips64/op_sput_boolean.S deleted file mode 100644 index 2e769d5e1a98b91d54aa1025d8718a012b74833d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_sput_boolean.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_sput.S" {"helper":"MterpSPutU8"} diff --git a/runtime/interpreter/mterp/mips64/op_sput_byte.S b/runtime/interpreter/mterp/mips64/op_sput_byte.S deleted file mode 100644 index 0b04b590eebb22522699354d87ffb9e32e6e27bd..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_sput_byte.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_sput.S" {"helper":"MterpSPutI8"} diff --git a/runtime/interpreter/mterp/mips64/op_sput_char.S b/runtime/interpreter/mterp/mips64/op_sput_char.S deleted file mode 100644 index 4a80375d659b0b8b77541aa96c57210a8d453b7a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_sput_char.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_sput.S" {"helper":"MterpSPutU16"} diff --git a/runtime/interpreter/mterp/mips64/op_sput_object.S b/runtime/interpreter/mterp/mips64/op_sput_object.S deleted file mode 100644 index 09bd0fb7ba448cd1fcbeae604481cd36af07f92a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_sput_object.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_sput.S" {"is_object":"1", "helper":"MterpSPutObj"} diff --git a/runtime/interpreter/mterp/mips64/op_sput_short.S b/runtime/interpreter/mterp/mips64/op_sput_short.S deleted file mode 100644 index c00043b6b7f04c9bfc58ea0e83fb7d7f65ff4545..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_sput_short.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_sput.S" {"helper":"MterpSPutI16"} diff --git a/runtime/interpreter/mterp/mips64/op_sput_wide.S b/runtime/interpreter/mterp/mips64/op_sput_wide.S deleted file mode 100644 index 070d17ff4d3498972abf70adf83bb8dbe0521c9c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_sput_wide.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/op_sput.S" {"helper":"MterpSPutU64"} diff --git a/runtime/interpreter/mterp/mips64/op_sub_double.S b/runtime/interpreter/mterp/mips64/op_sub_double.S deleted file mode 100644 index 40a6c89a1002f8f61a418bb6ef4a830d666275a6..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_sub_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/fbinopWide.S" {"instr":"sub.d f0, f0, f1"} diff --git a/runtime/interpreter/mterp/mips64/op_sub_double_2addr.S b/runtime/interpreter/mterp/mips64/op_sub_double_2addr.S deleted file mode 100644 index 984737e553a81fc67f8e6edd0754fe5bf91f79fb..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_sub_double_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/fbinopWide2addr.S" {"instr":"sub.d f0, f0, f1"} diff --git a/runtime/interpreter/mterp/mips64/op_sub_float.S b/runtime/interpreter/mterp/mips64/op_sub_float.S deleted file mode 100644 index 9010592116aba7e6afefccc0eab60654eb45fb90..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_sub_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/fbinop.S" {"instr":"sub.s f0, f0, f1"} diff --git a/runtime/interpreter/mterp/mips64/op_sub_float_2addr.S b/runtime/interpreter/mterp/mips64/op_sub_float_2addr.S deleted file mode 100644 index e7d4ffe1ae957bbede8d44d875039464f276928e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_sub_float_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/fbinop2addr.S" {"instr":"sub.s f0, f0, f1"} diff --git a/runtime/interpreter/mterp/mips64/op_sub_int.S b/runtime/interpreter/mterp/mips64/op_sub_int.S deleted file mode 100644 index 609ea0575dad3ec04beb83ab1f6f542dfa8adb0d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_sub_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binop.S" {"instr":"subu a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_sub_int_2addr.S b/runtime/interpreter/mterp/mips64/op_sub_int_2addr.S deleted file mode 100644 index ba2f1e875b6f10724015491e85d6d80a2d72923d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_sub_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binop2addr.S" {"instr":"subu a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_sub_long.S b/runtime/interpreter/mterp/mips64/op_sub_long.S deleted file mode 100644 index 09a6afd26ec9756b29aaf30191d29fb125220aa6..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_sub_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binopWide.S" {"instr":"dsubu a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_sub_long_2addr.S b/runtime/interpreter/mterp/mips64/op_sub_long_2addr.S deleted file mode 100644 index b9ec82a19b782e631cc97bdc460208e48e11f914..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_sub_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binopWide2addr.S" {"instr":"dsubu a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_throw.S b/runtime/interpreter/mterp/mips64/op_throw.S deleted file mode 100644 index 6418d57ecc1e17840e3d7effe9b893f9b14f62b2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_throw.S +++ /dev/null @@ -1,10 +0,0 @@ - /* - * Throw an exception object in the current thread. - */ - /* throw vAA */ - EXPORT_PC - srl a2, rINST, 8 # a2 <- AA - GET_VREG_U a0, a2 # a0 <- vAA (exception object) - beqzc a0, common_errNullObject - sd a0, THREAD_EXCEPTION_OFFSET(rSELF) # thread->exception <- obj - b MterpException diff --git a/runtime/interpreter/mterp/mips64/op_unused_3e.S b/runtime/interpreter/mterp/mips64/op_unused_3e.S deleted file mode 100644 index 29463d73fc3694e352e27c79541e24c6ea1c4e1c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_unused_3e.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/unused.S" diff --git a/runtime/interpreter/mterp/mips64/op_unused_3f.S b/runtime/interpreter/mterp/mips64/op_unused_3f.S deleted file mode 100644 index 29463d73fc3694e352e27c79541e24c6ea1c4e1c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_unused_3f.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/unused.S" diff --git a/runtime/interpreter/mterp/mips64/op_unused_40.S b/runtime/interpreter/mterp/mips64/op_unused_40.S deleted file mode 100644 index 29463d73fc3694e352e27c79541e24c6ea1c4e1c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_unused_40.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/unused.S" diff --git a/runtime/interpreter/mterp/mips64/op_unused_41.S b/runtime/interpreter/mterp/mips64/op_unused_41.S deleted file mode 100644 index 29463d73fc3694e352e27c79541e24c6ea1c4e1c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_unused_41.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/unused.S" diff --git a/runtime/interpreter/mterp/mips64/op_unused_42.S b/runtime/interpreter/mterp/mips64/op_unused_42.S deleted file mode 100644 index 29463d73fc3694e352e27c79541e24c6ea1c4e1c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_unused_42.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/unused.S" diff --git a/runtime/interpreter/mterp/mips64/op_unused_43.S b/runtime/interpreter/mterp/mips64/op_unused_43.S deleted file mode 100644 index 29463d73fc3694e352e27c79541e24c6ea1c4e1c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_unused_43.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/unused.S" diff --git a/runtime/interpreter/mterp/mips64/op_unused_79.S b/runtime/interpreter/mterp/mips64/op_unused_79.S deleted file mode 100644 index 29463d73fc3694e352e27c79541e24c6ea1c4e1c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_unused_79.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/unused.S" diff --git a/runtime/interpreter/mterp/mips64/op_unused_7a.S b/runtime/interpreter/mterp/mips64/op_unused_7a.S deleted file mode 100644 index 29463d73fc3694e352e27c79541e24c6ea1c4e1c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_unused_7a.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/unused.S" diff --git a/runtime/interpreter/mterp/mips64/op_unused_f3.S b/runtime/interpreter/mterp/mips64/op_unused_f3.S deleted file mode 100644 index 29463d73fc3694e352e27c79541e24c6ea1c4e1c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_unused_f3.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/unused.S" diff --git a/runtime/interpreter/mterp/mips64/op_unused_f4.S b/runtime/interpreter/mterp/mips64/op_unused_f4.S deleted file mode 100644 index 29463d73fc3694e352e27c79541e24c6ea1c4e1c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_unused_f4.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/unused.S" diff --git a/runtime/interpreter/mterp/mips64/op_unused_f5.S b/runtime/interpreter/mterp/mips64/op_unused_f5.S deleted file mode 100644 index 29463d73fc3694e352e27c79541e24c6ea1c4e1c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_unused_f5.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/unused.S" diff --git a/runtime/interpreter/mterp/mips64/op_unused_f6.S b/runtime/interpreter/mterp/mips64/op_unused_f6.S deleted file mode 100644 index 29463d73fc3694e352e27c79541e24c6ea1c4e1c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_unused_f6.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/unused.S" diff --git a/runtime/interpreter/mterp/mips64/op_unused_f7.S b/runtime/interpreter/mterp/mips64/op_unused_f7.S deleted file mode 100644 index 29463d73fc3694e352e27c79541e24c6ea1c4e1c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_unused_f7.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/unused.S" diff --git a/runtime/interpreter/mterp/mips64/op_unused_f8.S b/runtime/interpreter/mterp/mips64/op_unused_f8.S deleted file mode 100644 index 29463d73fc3694e352e27c79541e24c6ea1c4e1c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_unused_f8.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/unused.S" diff --git a/runtime/interpreter/mterp/mips64/op_unused_f9.S b/runtime/interpreter/mterp/mips64/op_unused_f9.S deleted file mode 100644 index 29463d73fc3694e352e27c79541e24c6ea1c4e1c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_unused_f9.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/unused.S" diff --git a/runtime/interpreter/mterp/mips64/op_unused_fc.S b/runtime/interpreter/mterp/mips64/op_unused_fc.S deleted file mode 100644 index 29463d73fc3694e352e27c79541e24c6ea1c4e1c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_unused_fc.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/unused.S" diff --git a/runtime/interpreter/mterp/mips64/op_unused_fd.S b/runtime/interpreter/mterp/mips64/op_unused_fd.S deleted file mode 100644 index 29463d73fc3694e352e27c79541e24c6ea1c4e1c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_unused_fd.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/unused.S" diff --git a/runtime/interpreter/mterp/mips64/op_ushr_int.S b/runtime/interpreter/mterp/mips64/op_ushr_int.S deleted file mode 100644 index 37c90cb7ec4db6c72c6eafc5fb0a6c2b5747252c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_ushr_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binop.S" {"instr":"srl a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_ushr_int_2addr.S b/runtime/interpreter/mterp/mips64/op_ushr_int_2addr.S deleted file mode 100644 index d6bf4135dc5e6f4d8e55ad4051c2f3c8d6b22b4f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_ushr_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binop2addr.S" {"instr":"srl a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_ushr_int_lit8.S b/runtime/interpreter/mterp/mips64/op_ushr_int_lit8.S deleted file mode 100644 index 2a2d843c8aadf3d149abe56368ee652c39325c14..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_ushr_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binopLit8.S" {"instr":"srl a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_ushr_long.S b/runtime/interpreter/mterp/mips64/op_ushr_long.S deleted file mode 100644 index e724405f1f9bf9251021429f9c69bb9fac95d233..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_ushr_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binopWide.S" {"instr":"dsrl a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_ushr_long_2addr.S b/runtime/interpreter/mterp/mips64/op_ushr_long_2addr.S deleted file mode 100644 index d2cf1355666e81758e5e784e926258fa75d2ef21..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_ushr_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binopWide2addr.S" {"instr":"dsrl a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_xor_int.S b/runtime/interpreter/mterp/mips64/op_xor_int.S deleted file mode 100644 index ee25ebc925375dd34097b592989c1394625de66d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_xor_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binop.S" {"instr":"xor a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_xor_int_2addr.S b/runtime/interpreter/mterp/mips64/op_xor_int_2addr.S deleted file mode 100644 index 0f0496729aae7f18c3fbc2fbc2fa128f4583323c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_xor_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binop2addr.S" {"instr":"xor a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_xor_int_lit16.S b/runtime/interpreter/mterp/mips64/op_xor_int_lit16.S deleted file mode 100644 index ecb21aee07e1c5e56cc18831b298f7a5ba244c88..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_xor_int_lit16.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binopLit16.S" {"instr":"xor a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_xor_int_lit8.S b/runtime/interpreter/mterp/mips64/op_xor_int_lit8.S deleted file mode 100644 index 115ae99917c06474806c37262f4521f92242a62d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_xor_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binopLit8.S" {"instr":"xor a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_xor_long.S b/runtime/interpreter/mterp/mips64/op_xor_long.S deleted file mode 100644 index 7ebabc2710bc131e83e0105a6a6da32b6733ac30..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_xor_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binopWide.S" {"instr":"xor a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/op_xor_long_2addr.S b/runtime/interpreter/mterp/mips64/op_xor_long_2addr.S deleted file mode 100644 index 0f1919a21efcb34c641c8418f9ac59d14fc940af..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/op_xor_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "mips64/binopWide2addr.S" {"instr":"xor a0, a0, a1"} diff --git a/runtime/interpreter/mterp/mips64/other.S b/runtime/interpreter/mterp/mips64/other.S new file mode 100644 index 0000000000000000000000000000000000000000..789efeeaa1482c521265f979492ef3782e51e837 --- /dev/null +++ b/runtime/interpreter/mterp/mips64/other.S @@ -0,0 +1,355 @@ +%def const(helper="UndefinedConstHandler"): + /* const/class vAA, type@BBBB */ + /* const/method-handle vAA, method_handle@BBBB */ + /* const/method-type vAA, proto@BBBB */ + /* const/string vAA, string@@BBBB */ + .extern $helper + EXPORT_PC + lhu a0, 2(rPC) # a0 <- BBBB + srl a1, rINST, 8 # a1 <- AA + daddu a2, rFP, OFF_FP_SHADOWFRAME + move a3, rSELF + jal $helper # (index, tgt_reg, shadow_frame, self) + PREFETCH_INST 2 # load rINST + bnez v0, MterpPossibleException # let reference interpreter deal with it. + ADVANCE 2 # advance rPC + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +%def unused(): +/* + * Bail to reference interpreter to throw. + */ + b MterpFallback + +%def op_const(): + /* const vAA, #+BBBBbbbb */ + srl a2, rINST, 8 # a2 <- AA + lh a0, 2(rPC) # a0 <- bbbb (low) + lh a1, 4(rPC) # a1 <- BBBB (high) + FETCH_ADVANCE_INST 3 # advance rPC, load rINST + ins a0, a1, 16, 16 # a0 = BBBBbbbb + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG a0, a2 # vAA <- +BBBBbbbb + GOTO_OPCODE v0 # jump to next instruction + +%def op_const_16(): + /* const/16 vAA, #+BBBB */ + srl a2, rINST, 8 # a2 <- AA + lh a0, 2(rPC) # a0 <- sign-extended BBBB + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG a0, a2 # vAA <- +BBBB + GOTO_OPCODE v0 # jump to next instruction + +%def op_const_4(): + /* const/4 vA, #+B */ + ext a2, rINST, 8, 4 # a2 <- A + seh a0, rINST # sign extend B in rINST + FETCH_ADVANCE_INST 1 # advance rPC, load rINST + sra a0, a0, 12 # shift B into its final position + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG a0, a2 # vA <- +B + GOTO_OPCODE v0 # jump to next instruction + +%def op_const_class(): +% const(helper="MterpConstClass") + +%def op_const_high16(): + /* const/high16 vAA, #+BBBB0000 */ + srl a2, rINST, 8 # a2 <- AA + lh a0, 2(rPC) # a0 <- BBBB + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + sll a0, a0, 16 # a0 <- BBBB0000 + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG a0, a2 # vAA <- +BBBB0000 + GOTO_OPCODE v0 # jump to next instruction + +%def op_const_method_handle(): +% const(helper="MterpConstMethodHandle") + +%def op_const_method_type(): +% const(helper="MterpConstMethodType") + +%def op_const_string(): +% const(helper="MterpConstString") + +%def op_const_string_jumbo(): + /* const/string vAA, String//BBBBBBBB */ + .extern MterpConstString + EXPORT_PC + lh a0, 2(rPC) # a0 <- bbbb (low) + lh a4, 4(rPC) # a4 <- BBBB (high) + srl a1, rINST, 8 # a1 <- AA + ins a0, a4, 16, 16 # a0 <- BBBBbbbb + daddu a2, rFP, OFF_FP_SHADOWFRAME + move a3, rSELF + jal MterpConstString # (index, tgt_reg, shadow_frame, self) + PREFETCH_INST 3 # load rINST + bnez v0, MterpPossibleException # let reference interpreter deal with it. + ADVANCE 3 # advance rPC + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +%def op_const_wide(): + /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ + srl a4, rINST, 8 # a4 <- AA + lh a0, 2(rPC) # a0 <- bbbb (low) + lh a1, 4(rPC) # a1 <- BBBB (low middle) + lh a2, 6(rPC) # a2 <- hhhh (high middle) + lh a3, 8(rPC) # a3 <- HHHH (high) + FETCH_ADVANCE_INST 5 # advance rPC, load rINST + ins a0, a1, 16, 16 # a0 = BBBBbbbb + ins a2, a3, 16, 16 # a2 = HHHHhhhh + dinsu a0, a2, 32, 32 # a0 = HHHHhhhhBBBBbbbb + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG_WIDE a0, a4 # vAA <- +HHHHhhhhBBBBbbbb + GOTO_OPCODE v0 # jump to next instruction + +%def op_const_wide_16(): + /* const-wide/16 vAA, #+BBBB */ + srl a2, rINST, 8 # a2 <- AA + lh a0, 2(rPC) # a0 <- sign-extended BBBB + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG_WIDE a0, a2 # vAA <- +BBBB + GOTO_OPCODE v0 # jump to next instruction + +%def op_const_wide_32(): + /* const-wide/32 vAA, #+BBBBbbbb */ + srl a2, rINST, 8 # a2 <- AA + lh a0, 2(rPC) # a0 <- bbbb (low) + lh a1, 4(rPC) # a1 <- BBBB (high) + FETCH_ADVANCE_INST 3 # advance rPC, load rINST + ins a0, a1, 16, 16 # a0 = BBBBbbbb + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG_WIDE a0, a2 # vAA <- +BBBBbbbb + GOTO_OPCODE v0 # jump to next instruction + +%def op_const_wide_high16(): + /* const-wide/high16 vAA, #+BBBB000000000000 */ + srl a2, rINST, 8 # a2 <- AA + lh a0, 2(rPC) # a0 <- BBBB + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + dsll32 a0, a0, 16 # a0 <- BBBB000000000000 + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG_WIDE a0, a2 # vAA <- +BBBB000000000000 + GOTO_OPCODE v0 # jump to next instruction + +%def op_monitor_enter(): + /* + * Synchronize on an object. + */ + /* monitor-enter vAA */ + .extern artLockObjectFromCode + EXPORT_PC + srl a2, rINST, 8 # a2 <- AA + GET_VREG_U a0, a2 # a0 <- vAA (object) + move a1, rSELF # a1 <- self + jal artLockObjectFromCode + bnezc v0, MterpException + FETCH_ADVANCE_INST 1 + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +%def op_monitor_exit(): + /* + * Unlock an object. + * + * Exceptions that occur when unlocking a monitor need to appear as + * if they happened at the following instruction. See the Dalvik + * instruction spec. + */ + /* monitor-exit vAA */ + .extern artUnlockObjectFromCode + EXPORT_PC + srl a2, rINST, 8 # a2 <- AA + GET_VREG_U a0, a2 # a0 <- vAA (object) + move a1, rSELF # a1 <- self + jal artUnlockObjectFromCode # v0 <- success for unlock(self, obj) + bnezc v0, MterpException + FETCH_ADVANCE_INST 1 # before throw: advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +%def op_move(is_object="0"): + /* for move, move-object, long-to-int */ + /* op vA, vB */ + ext a2, rINST, 8, 4 # a2 <- A + ext a3, rINST, 12, 4 # a3 <- B + FETCH_ADVANCE_INST 1 # advance rPC, load rINST + GET_VREG a0, a3 # a0 <- vB + GET_INST_OPCODE v0 # extract opcode from rINST + .if $is_object + SET_VREG_OBJECT a0, a2 # vA <- vB + .else + SET_VREG a0, a2 # vA <- vB + .endif + GOTO_OPCODE v0 # jump to next instruction + +%def op_move_16(is_object="0"): + /* for: move/16, move-object/16 */ + /* op vAAAA, vBBBB */ + lhu a3, 4(rPC) # a3 <- BBBB + lhu a2, 2(rPC) # a2 <- AAAA + FETCH_ADVANCE_INST 3 # advance rPC, load rINST + GET_VREG a0, a3 # a0 <- vBBBB + GET_INST_OPCODE v0 # extract opcode from rINST + .if $is_object + SET_VREG_OBJECT a0, a2 # vAAAA <- vBBBB + .else + SET_VREG a0, a2 # vAAAA <- vBBBB + .endif + GOTO_OPCODE v0 # jump to next instruction + +%def op_move_exception(): + /* move-exception vAA */ + srl a2, rINST, 8 # a2 <- AA + ld a0, THREAD_EXCEPTION_OFFSET(rSELF) # load exception obj + FETCH_ADVANCE_INST 1 # advance rPC, load rINST + SET_VREG_OBJECT a0, a2 # vAA <- exception obj + GET_INST_OPCODE v0 # extract opcode from rINST + sd zero, THREAD_EXCEPTION_OFFSET(rSELF) # clear exception + GOTO_OPCODE v0 # jump to next instruction + +%def op_move_from16(is_object="0"): + /* for: move/from16, move-object/from16 */ + /* op vAA, vBBBB */ + lhu a3, 2(rPC) # a3 <- BBBB + srl a2, rINST, 8 # a2 <- AA + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + GET_VREG a0, a3 # a0 <- vBBBB + GET_INST_OPCODE v0 # extract opcode from rINST + .if $is_object + SET_VREG_OBJECT a0, a2 # vAA <- vBBBB + .else + SET_VREG a0, a2 # vAA <- vBBBB + .endif + GOTO_OPCODE v0 # jump to next instruction + +%def op_move_object(): +% op_move(is_object="1") + +%def op_move_object_16(): +% op_move_16(is_object="1") + +%def op_move_object_from16(): +% op_move_from16(is_object="1") + +%def op_move_result(is_object="0"): + /* for: move-result, move-result-object */ + /* op vAA */ + srl a2, rINST, 8 # a2 <- AA + FETCH_ADVANCE_INST 1 # advance rPC, load rINST + ld a0, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType + lw a0, 0(a0) # a0 <- result.i + GET_INST_OPCODE v0 # extract opcode from rINST + .if $is_object + SET_VREG_OBJECT a0, a2 # vAA <- result + .else + SET_VREG a0, a2 # vAA <- result + .endif + GOTO_OPCODE v0 # jump to next instruction + +%def op_move_result_object(): +% op_move_result(is_object="1") + +%def op_move_result_wide(): + /* for: move-result-wide */ + /* op vAA */ + srl a2, rINST, 8 # a2 <- AA + FETCH_ADVANCE_INST 1 # advance rPC, load rINST + ld a0, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType + ld a0, 0(a0) # a0 <- result.j + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG_WIDE a0, a2 # vAA <- result + GOTO_OPCODE v0 # jump to next instruction + +%def op_move_wide(): + /* move-wide vA, vB */ + /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ + ext a3, rINST, 12, 4 # a3 <- B + ext a2, rINST, 8, 4 # a2 <- A + GET_VREG_WIDE a0, a3 # a0 <- vB + FETCH_ADVANCE_INST 1 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG_WIDE a0, a2 # vA <- vB + GOTO_OPCODE v0 # jump to next instruction + +%def op_move_wide_16(): + /* move-wide/16 vAAAA, vBBBB */ + /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ + lhu a3, 4(rPC) # a3 <- BBBB + lhu a2, 2(rPC) # a2 <- AAAA + GET_VREG_WIDE a0, a3 # a0 <- vBBBB + FETCH_ADVANCE_INST 3 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG_WIDE a0, a2 # vAAAA <- vBBBB + GOTO_OPCODE v0 # jump to next instruction + +%def op_move_wide_from16(): + /* move-wide/from16 vAA, vBBBB */ + /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ + lhu a3, 2(rPC) # a3 <- BBBB + srl a2, rINST, 8 # a2 <- AA + GET_VREG_WIDE a0, a3 # a0 <- vBBBB + FETCH_ADVANCE_INST 2 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + SET_VREG_WIDE a0, a2 # vAA <- vBBBB + GOTO_OPCODE v0 # jump to next instruction + +%def op_nop(): + FETCH_ADVANCE_INST 1 # advance rPC, load rINST + GET_INST_OPCODE v0 # extract opcode from rINST + GOTO_OPCODE v0 # jump to next instruction + +%def op_unused_3e(): +% unused() + +%def op_unused_3f(): +% unused() + +%def op_unused_40(): +% unused() + +%def op_unused_41(): +% unused() + +%def op_unused_42(): +% unused() + +%def op_unused_43(): +% unused() + +%def op_unused_79(): +% unused() + +%def op_unused_7a(): +% unused() + +%def op_unused_f3(): +% unused() + +%def op_unused_f4(): +% unused() + +%def op_unused_f5(): +% unused() + +%def op_unused_f6(): +% unused() + +%def op_unused_f7(): +% unused() + +%def op_unused_f8(): +% unused() + +%def op_unused_f9(): +% unused() + +%def op_unused_fc(): +% unused() + +%def op_unused_fd(): +% unused() diff --git a/runtime/interpreter/mterp/mips64/unop.S b/runtime/interpreter/mterp/mips64/unop.S deleted file mode 100644 index e3f7ea0eda286915f2ba2ad5f3565f6082f1cb6a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/unop.S +++ /dev/null @@ -1,18 +0,0 @@ -%default {"preinstr":""} - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "a0 = op a0". - * - * for: int-to-byte, int-to-char, int-to-short, - * not-int, neg-int - */ - /* unop vA, vB */ - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a3 # a0 <- vB - ext a2, rINST, 8, 4 # a2 <- A - $preinstr # optional op - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - $instr # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/unopWide.S b/runtime/interpreter/mterp/mips64/unopWide.S deleted file mode 100644 index c0dd1aa1d3e2c23722293974222ac23ff1d827ed..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/unopWide.S +++ /dev/null @@ -1,17 +0,0 @@ -%default {"preinstr":""} - /* - * Generic 64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "a0 = op a0". - * - * For: not-long, neg-long - */ - /* unop vA, vB */ - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_WIDE a0, a3 # a0 <- vB - ext a2, rINST, 8, 4 # a2 <- A - $preinstr # optional op - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - $instr # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/mips64/unused.S b/runtime/interpreter/mterp/mips64/unused.S deleted file mode 100644 index 30d38bd6cdcdde3096d36fbddfb6760de2ea9781..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/unused.S +++ /dev/null @@ -1,4 +0,0 @@ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback diff --git a/runtime/interpreter/mterp/mips64/zcmp.S b/runtime/interpreter/mterp/mips64/zcmp.S deleted file mode 100644 index 75db49edd499c560256c17adf94febb6ebfdee46..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/mips64/zcmp.S +++ /dev/null @@ -1,17 +0,0 @@ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform, e.g. for - * "if-lez" you would use "le". - * - * For: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - srl a2, rINST, 8 # a2 <- AA - lh rINST, 2(rPC) # rINST <- offset (sign-extended BBBB) - GET_VREG a0, a2 # a0 <- vAA - b${condition}zc a0, MterpCommonTakenBranchNoFlags - li v0, JIT_CHECK_OSR # possible OSR re-entry? - beqc rPROFILE, v0, .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction diff --git a/runtime/interpreter/mterp/out/mterp_arm.S b/runtime/interpreter/mterp/out/mterp_arm.S deleted file mode 100644 index 25512aec375961a64705dc827042bdab8192981c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/out/mterp_arm.S +++ /dev/null @@ -1,12409 +0,0 @@ -/* - * This file was generated automatically by gen-mterp.py for 'arm'. - * - * --> DO NOT EDIT <-- - */ - -/* File: arm/header.S */ -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - Art assembly interpreter notes: - - First validate assembly code by implementing ExecuteXXXImpl() style body (doesn't - handle invoke, allows higher-level code to create frame & shadow frame. - - Once that's working, support direct entry code & eliminate shadow frame (and - excess locals allocation. - - Some (hopefully) temporary ugliness. We'll treat rFP as pointing to the - base of the vreg array within the shadow frame. Access the other fields, - dex_pc_, method_ and number_of_vregs_ via negative offsets. For now, we'll continue - the shadow frame mechanism of double-storing object references - via rFP & - number_of_vregs_. - - */ - -/* -ARM EABI general notes: - -r0-r3 hold first 4 args to a method; they are not preserved across method calls -r4-r8 are available for general use -r9 is given special treatment in some situations, but not for us -r10 (sl) seems to be generally available -r11 (fp) is used by gcc (unless -fomit-frame-pointer is set) -r12 (ip) is scratch -- not preserved across method calls -r13 (sp) should be managed carefully in case a signal arrives -r14 (lr) must be preserved -r15 (pc) can be tinkered with directly - -r0 holds returns of <= 4 bytes -r0-r1 hold returns of 8 bytes, low word in r0 - -Callee must save/restore r4+ (except r12) if it modifies them. If VFP -is present, registers s16-s31 (a/k/a d8-d15, a/k/a q4-q7) must be preserved, -s0-s15 (d0-d7, q0-a3) do not need to be. - -Stack is "full descending". Only the arguments that don't fit in the first 4 -registers are placed on the stack. "sp" points at the first stacked argument -(i.e. the 5th arg). - -VFP: single-precision results in s0, double-precision results in d0. - -In the EABI, "sp" must be 64-bit aligned on entry to a function, and any -64-bit quantities (long long, double) must be 64-bit aligned. -*/ - -/* -Mterp and ARM notes: - -The following registers have fixed assignments: - - reg nick purpose - r4 rPC interpreted program counter, used for fetching instructions - r5 rFP interpreted frame pointer, used for accessing locals and args - r6 rSELF self (Thread) pointer - r7 rINST first 16-bit code unit of current instruction - r8 rIBASE interpreted instruction base pointer, used for computed goto - r10 rPROFILE branch profiling countdown - r11 rREFS base of object references in shadow frame (ideally, we'll get rid of this later). - -Macros are provided for common operations. Each macro MUST emit only -one instruction to make instruction-counting easier. They MUST NOT alter -unspecified registers or condition codes. -*/ - -/* - * This is a #include, not a %include, because we want the C pre-processor - * to expand the macros into assembler assignment statements. - */ -#include "asm_support.h" -#include "interpreter/cfi_asm_support.h" - -#define MTERP_PROFILE_BRANCHES 1 -#define MTERP_LOGGING 0 - -/* During bringup, we'll use the shadow frame model instead of rFP */ -/* single-purpose registers, given names for clarity */ -#define rPC r4 -#define CFI_DEX 4 // DWARF register number of the register holding dex-pc (xPC). -#define CFI_TMP 0 // DWARF register number of the first argument register (r0). -#define rFP r5 -#define rSELF r6 -#define rINST r7 -#define rIBASE r8 -#define rPROFILE r10 -#define rREFS r11 - -/* - * Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs. So, - * to access other shadow frame fields, we need to use a backwards offset. Define those here. - */ -#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) -#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) -#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) -#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) -#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) -#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) -#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) -#define OFF_FP_DEX_INSTRUCTIONS OFF_FP(SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET) -#define OFF_FP_SHADOWFRAME OFF_FP(0) - -/* - * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must - * be done *before* something throws. - * - * It's okay to do this more than once. - * - * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped - * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction - * offset into the code_items_[] array. For effiency, we will "export" the - * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC - * to convert to a dex pc when needed. - */ -.macro EXPORT_PC - str rPC, [rFP, #OFF_FP_DEX_PC_PTR] -.endm - -.macro EXPORT_DEX_PC tmp - ldr \tmp, [rFP, #OFF_FP_DEX_INSTRUCTIONS] - str rPC, [rFP, #OFF_FP_DEX_PC_PTR] - sub \tmp, rPC, \tmp - asr \tmp, #1 - str \tmp, [rFP, #OFF_FP_DEX_PC] -.endm - -/* - * Fetch the next instruction from rPC into rINST. Does not advance rPC. - */ -.macro FETCH_INST - ldrh rINST, [rPC] -.endm - -/* - * Fetch the next instruction from the specified offset. Advances rPC - * to point to the next instruction. "_count" is in 16-bit code units. - * - * Because of the limited size of immediate constants on ARM, this is only - * suitable for small forward movements (i.e. don't try to implement "goto" - * with this). - * - * This must come AFTER anything that can throw an exception, or the - * exception catch may miss. (This also implies that it must come after - * EXPORT_PC.) - */ -.macro FETCH_ADVANCE_INST count - ldrh rINST, [rPC, #((\count)*2)]! -.endm - -/* - * The operation performed here is similar to FETCH_ADVANCE_INST, except the - * src and dest registers are parameterized (not hard-wired to rPC and rINST). - */ -.macro PREFETCH_ADVANCE_INST dreg, sreg, count - ldrh \dreg, [\sreg, #((\count)*2)]! -.endm - -/* - * Similar to FETCH_ADVANCE_INST, but does not update rPC. Used to load - * rINST ahead of possible exception point. Be sure to manually advance rPC - * later. - */ -.macro PREFETCH_INST count - ldrh rINST, [rPC, #((\count)*2)] -.endm - -/* Advance rPC by some number of code units. */ -.macro ADVANCE count - add rPC, #((\count)*2) -.endm - -/* - * Fetch the next instruction from an offset specified by _reg. Updates - * rPC to point to the next instruction. "_reg" must specify the distance - * in bytes, *not* 16-bit code units, and may be a signed value. - * - * We want to write "ldrh rINST, [rPC, _reg, lsl #1]!", but some of the - * bits that hold the shift distance are used for the half/byte/sign flags. - * In some cases we can pre-double _reg for free, so we require a byte offset - * here. - */ -.macro FETCH_ADVANCE_INST_RB reg - ldrh rINST, [rPC, \reg]! -.endm - -/* - * Fetch a half-word code unit from an offset past the current PC. The - * "_count" value is in 16-bit code units. Does not advance rPC. - * - * The "_S" variant works the same but treats the value as signed. - */ -.macro FETCH reg, count - ldrh \reg, [rPC, #((\count)*2)] -.endm - -.macro FETCH_S reg, count - ldrsh \reg, [rPC, #((\count)*2)] -.endm - -/* - * Fetch one byte from an offset past the current PC. Pass in the same - * "_count" as you would for FETCH, and an additional 0/1 indicating which - * byte of the halfword you want (lo/hi). - */ -.macro FETCH_B reg, count, byte - ldrb \reg, [rPC, #((\count)*2+(\byte))] -.endm - -/* - * Put the instruction's opcode field into the specified register. - */ -.macro GET_INST_OPCODE reg - and \reg, rINST, #255 -.endm - -/* - * Put the prefetched instruction's opcode field into the specified register. - */ -.macro GET_PREFETCHED_OPCODE oreg, ireg - and \oreg, \ireg, #255 -.endm - -/* - * Begin executing the opcode in _reg. Because this only jumps within the - * interpreter, we don't have to worry about pre-ARMv5 THUMB interwork. - */ -.macro GOTO_OPCODE reg - add pc, rIBASE, \reg, lsl #7 -.endm -.macro GOTO_OPCODE_BASE base,reg - add pc, \base, \reg, lsl #7 -.endm - -/* - * Get/set the 32-bit value from a Dalvik register. - */ -.macro GET_VREG reg, vreg - ldr \reg, [rFP, \vreg, lsl #2] -.endm -.macro SET_VREG reg, vreg - str \reg, [rFP, \vreg, lsl #2] - mov \reg, #0 - str \reg, [rREFS, \vreg, lsl #2] -.endm -.macro SET_VREG_OBJECT reg, vreg, tmpreg - str \reg, [rFP, \vreg, lsl #2] - str \reg, [rREFS, \vreg, lsl #2] -.endm -.macro SET_VREG_SHADOW reg, vreg - str \reg, [rREFS, \vreg, lsl #2] -.endm - -/* - * Clear the corresponding shadow regs for a vreg pair - */ -.macro CLEAR_SHADOW_PAIR vreg, tmp1, tmp2 - mov \tmp1, #0 - add \tmp2, \vreg, #1 - SET_VREG_SHADOW \tmp1, \vreg - SET_VREG_SHADOW \tmp1, \tmp2 -.endm - -/* - * Convert a virtual register index into an address. - */ -.macro VREG_INDEX_TO_ADDR reg, vreg - add \reg, rFP, \vreg, lsl #2 /* WARNING/FIXME: handle shadow frame vreg zero if store */ -.endm - -/* - * Refresh handler table. - */ -.macro REFRESH_IBASE - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] -.endm - -/* - * cfi support macros. - */ -.macro ENTRY name - .arm - .type \name, #function - .hidden \name // Hide this as a global symbol, so we do not incur plt calls. - .global \name - /* Cache alignment for function entry */ - .balign 16 -\name: - .cfi_startproc - .fnstart -.endm - -.macro END name - .fnend - .cfi_endproc - .size \name, .-\name -.endm - -/* File: arm/entry.S */ -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -/* - * Interpreter entry point. - */ - - .text - .align 2 - -/* - * On entry: - * r0 Thread* self/ - * r1 insns_ - * r2 ShadowFrame - * r3 JValue* result_register - * - */ - -ENTRY ExecuteMterpImpl - stmfd sp!, {r3-r10,fp,lr} @ save 10 regs, (r3 just to align 64) - .cfi_adjust_cfa_offset 40 - .cfi_rel_offset r3, 0 - .cfi_rel_offset r4, 4 - .cfi_rel_offset r5, 8 - .cfi_rel_offset r6, 12 - .cfi_rel_offset r7, 16 - .cfi_rel_offset r8, 20 - .cfi_rel_offset r9, 24 - .cfi_rel_offset r10, 28 - .cfi_rel_offset fp, 32 - .cfi_rel_offset lr, 36 - - /* Remember the return register */ - str r3, [r2, #SHADOWFRAME_RESULT_REGISTER_OFFSET] - - /* Remember the dex instruction pointer */ - str r1, [r2, #SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET] - - /* set up "named" registers */ - mov rSELF, r0 - ldr r0, [r2, #SHADOWFRAME_NUMBER_OF_VREGS_OFFSET] - add rFP, r2, #SHADOWFRAME_VREGS_OFFSET @ point to vregs. - VREG_INDEX_TO_ADDR rREFS, r0 @ point to reference array in shadow frame - ldr r0, [r2, #SHADOWFRAME_DEX_PC_OFFSET] @ Get starting dex_pc. - add rPC, r1, r0, lsl #1 @ Create direct pointer to 1st dex opcode - CFI_DEFINE_DEX_PC_WITH_OFFSET(CFI_TMP, CFI_DEX, 0) - EXPORT_PC - - /* Starting ibase */ - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] - - /* Set up for backwards branches & osr profiling */ - ldr r0, [rFP, #OFF_FP_METHOD] - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rSELF - bl MterpSetUpHotnessCountdown - mov rPROFILE, r0 @ Starting hotness countdown to rPROFILE - - /* start executing the instruction at rPC */ - FETCH_INST @ load rINST from rPC - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - /* NOTE: no fallthrough */ - -/* File: arm/instruction_start.S */ - - .type artMterpAsmInstructionStart, #object - .hidden artMterpAsmInstructionStart - .global artMterpAsmInstructionStart -artMterpAsmInstructionStart = .L_op_nop - .text - -/* ------------------------------ */ - .balign 128 -.L_op_nop: /* 0x00 */ -/* File: arm/op_nop.S */ - FETCH_ADVANCE_INST 1 @ advance to next instr, load rINST - GET_INST_OPCODE ip @ ip<- opcode from rINST - GOTO_OPCODE ip @ execute it - -/* ------------------------------ */ - .balign 128 -.L_op_move: /* 0x01 */ -/* File: arm/op_move.S */ - /* for move, move-object, long-to-int */ - /* op vA, vB */ - mov r1, rINST, lsr #12 @ r1<- B from 15:12 - ubfx r0, rINST, #8, #4 @ r0<- A from 11:8 - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - GET_VREG r2, r1 @ r2<- fp[B] - GET_INST_OPCODE ip @ ip<- opcode from rINST - .if 0 - SET_VREG_OBJECT r2, r0 @ fp[A]<- r2 - .else - SET_VREG r2, r0 @ fp[A]<- r2 - .endif - GOTO_OPCODE ip @ execute next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_from16: /* 0x02 */ -/* File: arm/op_move_from16.S */ - /* for: move/from16, move-object/from16 */ - /* op vAA, vBBBB */ - FETCH r1, 1 @ r1<- BBBB - mov r0, rINST, lsr #8 @ r0<- AA - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - GET_VREG r2, r1 @ r2<- fp[BBBB] - GET_INST_OPCODE ip @ extract opcode from rINST - .if 0 - SET_VREG_OBJECT r2, r0 @ fp[AA]<- r2 - .else - SET_VREG r2, r0 @ fp[AA]<- r2 - .endif - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_16: /* 0x03 */ -/* File: arm/op_move_16.S */ - /* for: move/16, move-object/16 */ - /* op vAAAA, vBBBB */ - FETCH r1, 2 @ r1<- BBBB - FETCH r0, 1 @ r0<- AAAA - FETCH_ADVANCE_INST 3 @ advance rPC, load rINST - GET_VREG r2, r1 @ r2<- fp[BBBB] - GET_INST_OPCODE ip @ extract opcode from rINST - .if 0 - SET_VREG_OBJECT r2, r0 @ fp[AAAA]<- r2 - .else - SET_VREG r2, r0 @ fp[AAAA]<- r2 - .endif - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_wide: /* 0x04 */ -/* File: arm/op_move_wide.S */ - /* move-wide vA, vB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx rINST, rINST, #8, #4 @ rINST<- A - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] - VREG_INDEX_TO_ADDR r2, rINST @ r2<- &fp[A] - ldmia r3, {r0-r1} @ r0/r1<- fp[B] - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r2, {r0-r1} @ fp[A]<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_wide_from16: /* 0x05 */ -/* File: arm/op_move_wide_from16.S */ - /* move-wide/from16 vAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - FETCH r3, 1 @ r3<- BBBB - mov rINST, rINST, lsr #8 @ rINST<- AA - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[BBBB] - VREG_INDEX_TO_ADDR r2, rINST @ r2<- &fp[AA] - ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r2, {r0-r1} @ fp[AA]<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_wide_16: /* 0x06 */ -/* File: arm/op_move_wide_16.S */ - /* move-wide/16 vAAAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - FETCH r3, 2 @ r3<- BBBB - FETCH r2, 1 @ r2<- AAAA - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[BBBB] - VREG_INDEX_TO_ADDR lr, r2 @ r2<- &fp[AAAA] - ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] - FETCH_ADVANCE_INST 3 @ advance rPC, load rINST - CLEAR_SHADOW_PAIR r2, r3, ip @ Zero out the shadow regs - stmia lr, {r0-r1} @ fp[AAAA]<- r0/r1 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_object: /* 0x07 */ -/* File: arm/op_move_object.S */ -/* File: arm/op_move.S */ - /* for move, move-object, long-to-int */ - /* op vA, vB */ - mov r1, rINST, lsr #12 @ r1<- B from 15:12 - ubfx r0, rINST, #8, #4 @ r0<- A from 11:8 - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - GET_VREG r2, r1 @ r2<- fp[B] - GET_INST_OPCODE ip @ ip<- opcode from rINST - .if 1 - SET_VREG_OBJECT r2, r0 @ fp[A]<- r2 - .else - SET_VREG r2, r0 @ fp[A]<- r2 - .endif - GOTO_OPCODE ip @ execute next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_move_object_from16: /* 0x08 */ -/* File: arm/op_move_object_from16.S */ -/* File: arm/op_move_from16.S */ - /* for: move/from16, move-object/from16 */ - /* op vAA, vBBBB */ - FETCH r1, 1 @ r1<- BBBB - mov r0, rINST, lsr #8 @ r0<- AA - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - GET_VREG r2, r1 @ r2<- fp[BBBB] - GET_INST_OPCODE ip @ extract opcode from rINST - .if 1 - SET_VREG_OBJECT r2, r0 @ fp[AA]<- r2 - .else - SET_VREG r2, r0 @ fp[AA]<- r2 - .endif - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_move_object_16: /* 0x09 */ -/* File: arm/op_move_object_16.S */ -/* File: arm/op_move_16.S */ - /* for: move/16, move-object/16 */ - /* op vAAAA, vBBBB */ - FETCH r1, 2 @ r1<- BBBB - FETCH r0, 1 @ r0<- AAAA - FETCH_ADVANCE_INST 3 @ advance rPC, load rINST - GET_VREG r2, r1 @ r2<- fp[BBBB] - GET_INST_OPCODE ip @ extract opcode from rINST - .if 1 - SET_VREG_OBJECT r2, r0 @ fp[AAAA]<- r2 - .else - SET_VREG r2, r0 @ fp[AAAA]<- r2 - .endif - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_move_result: /* 0x0a */ -/* File: arm/op_move_result.S */ - /* for: move-result, move-result-object */ - /* op vAA */ - mov r2, rINST, lsr #8 @ r2<- AA - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - ldr r0, [rFP, #OFF_FP_RESULT_REGISTER] @ get pointer to result JType. - ldr r0, [r0] @ r0 <- result.i. - GET_INST_OPCODE ip @ extract opcode from rINST - .if 0 - SET_VREG_OBJECT r0, r2, r1 @ fp[AA]<- r0 - .else - SET_VREG r0, r2 @ fp[AA]<- r0 - .endif - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_result_wide: /* 0x0b */ -/* File: arm/op_move_result_wide.S */ - /* move-result-wide vAA */ - mov rINST, rINST, lsr #8 @ rINST<- AA - ldr r3, [rFP, #OFF_FP_RESULT_REGISTER] - VREG_INDEX_TO_ADDR r2, rINST @ r2<- &fp[AA] - ldmia r3, {r0-r1} @ r0/r1<- retval.j - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - stmia r2, {r0-r1} @ fp[AA]<- r0/r1 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_result_object: /* 0x0c */ -/* File: arm/op_move_result_object.S */ -/* File: arm/op_move_result.S */ - /* for: move-result, move-result-object */ - /* op vAA */ - mov r2, rINST, lsr #8 @ r2<- AA - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - ldr r0, [rFP, #OFF_FP_RESULT_REGISTER] @ get pointer to result JType. - ldr r0, [r0] @ r0 <- result.i. - GET_INST_OPCODE ip @ extract opcode from rINST - .if 1 - SET_VREG_OBJECT r0, r2, r1 @ fp[AA]<- r0 - .else - SET_VREG r0, r2 @ fp[AA]<- r0 - .endif - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_move_exception: /* 0x0d */ -/* File: arm/op_move_exception.S */ - /* move-exception vAA */ - mov r2, rINST, lsr #8 @ r2<- AA - ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] - mov r1, #0 @ r1<- 0 - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - SET_VREG_OBJECT r3, r2 @ fp[AA]<- exception obj - GET_INST_OPCODE ip @ extract opcode from rINST - str r1, [rSELF, #THREAD_EXCEPTION_OFFSET] @ clear exception - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_return_void: /* 0x0e */ -/* File: arm/op_return_void.S */ - .extern MterpThreadFenceForConstructor - bl MterpThreadFenceForConstructor - ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] - mov r0, rSELF - ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - blne MterpSuspendCheck @ (self) - mov r0, #0 - mov r1, #0 - b MterpReturn - -/* ------------------------------ */ - .balign 128 -.L_op_return: /* 0x0f */ -/* File: arm/op_return.S */ - /* - * Return a 32-bit value. - * - * for: return, return-object - */ - /* op vAA */ - .extern MterpThreadFenceForConstructor - bl MterpThreadFenceForConstructor - ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] - mov r0, rSELF - ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - blne MterpSuspendCheck @ (self) - mov r2, rINST, lsr #8 @ r2<- AA - GET_VREG r0, r2 @ r0<- vAA - mov r1, #0 - b MterpReturn - -/* ------------------------------ */ - .balign 128 -.L_op_return_wide: /* 0x10 */ -/* File: arm/op_return_wide.S */ - /* - * Return a 64-bit value. - */ - /* return-wide vAA */ - .extern MterpThreadFenceForConstructor - bl MterpThreadFenceForConstructor - ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] - mov r0, rSELF - ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - blne MterpSuspendCheck @ (self) - mov r2, rINST, lsr #8 @ r2<- AA - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[AA] - ldmia r2, {r0-r1} @ r0/r1 <- vAA/vAA+1 - b MterpReturn - -/* ------------------------------ */ - .balign 128 -.L_op_return_object: /* 0x11 */ -/* File: arm/op_return_object.S */ -/* File: arm/op_return.S */ - /* - * Return a 32-bit value. - * - * for: return, return-object - */ - /* op vAA */ - .extern MterpThreadFenceForConstructor - bl MterpThreadFenceForConstructor - ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] - mov r0, rSELF - ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - blne MterpSuspendCheck @ (self) - mov r2, rINST, lsr #8 @ r2<- AA - GET_VREG r0, r2 @ r0<- vAA - mov r1, #0 - b MterpReturn - - -/* ------------------------------ */ - .balign 128 -.L_op_const_4: /* 0x12 */ -/* File: arm/op_const_4.S */ - /* const/4 vA, #+B */ - sbfx r1, rINST, #12, #4 @ r1<- sssssssB (sign-extended) - ubfx r0, rINST, #8, #4 @ r0<- A - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - GET_INST_OPCODE ip @ ip<- opcode from rINST - SET_VREG r1, r0 @ fp[A]<- r1 - GOTO_OPCODE ip @ execute next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_16: /* 0x13 */ -/* File: arm/op_const_16.S */ - /* const/16 vAA, #+BBBB */ - FETCH_S r0, 1 @ r0<- ssssBBBB (sign-extended) - mov r3, rINST, lsr #8 @ r3<- AA - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - SET_VREG r0, r3 @ vAA<- r0 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const: /* 0x14 */ -/* File: arm/op_const.S */ - /* const vAA, #+BBBBbbbb */ - mov r3, rINST, lsr #8 @ r3<- AA - FETCH r0, 1 @ r0<- bbbb (low) - FETCH r1, 2 @ r1<- BBBB (high) - FETCH_ADVANCE_INST 3 @ advance rPC, load rINST - orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r3 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_high16: /* 0x15 */ -/* File: arm/op_const_high16.S */ - /* const/high16 vAA, #+BBBB0000 */ - FETCH r0, 1 @ r0<- 0000BBBB (zero-extended) - mov r3, rINST, lsr #8 @ r3<- AA - mov r0, r0, lsl #16 @ r0<- BBBB0000 - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - SET_VREG r0, r3 @ vAA<- r0 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_wide_16: /* 0x16 */ -/* File: arm/op_const_wide_16.S */ - /* const-wide/16 vAA, #+BBBB */ - FETCH_S r0, 1 @ r0<- ssssBBBB (sign-extended) - mov r3, rINST, lsr #8 @ r3<- AA - mov r1, r0, asr #31 @ r1<- ssssssss - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - CLEAR_SHADOW_PAIR r3, r2, lr @ Zero out the shadow regs - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[AA] - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r3, {r0-r1} @ vAA<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_wide_32: /* 0x17 */ -/* File: arm/op_const_wide_32.S */ - /* const-wide/32 vAA, #+BBBBbbbb */ - FETCH r0, 1 @ r0<- 0000bbbb (low) - mov r3, rINST, lsr #8 @ r3<- AA - FETCH_S r2, 2 @ r2<- ssssBBBB (high) - FETCH_ADVANCE_INST 3 @ advance rPC, load rINST - orr r0, r0, r2, lsl #16 @ r0<- BBBBbbbb - CLEAR_SHADOW_PAIR r3, r2, lr @ Zero out the shadow regs - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[AA] - mov r1, r0, asr #31 @ r1<- ssssssss - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r3, {r0-r1} @ vAA<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_wide: /* 0x18 */ -/* File: arm/op_const_wide.S */ - /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ - FETCH r0, 1 @ r0<- bbbb (low) - FETCH r1, 2 @ r1<- BBBB (low middle) - FETCH r2, 3 @ r2<- hhhh (high middle) - orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb (low word) - FETCH r3, 4 @ r3<- HHHH (high) - mov r9, rINST, lsr #8 @ r9<- AA - orr r1, r2, r3, lsl #16 @ r1<- HHHHhhhh (high word) - CLEAR_SHADOW_PAIR r9, r2, r3 @ Zero out the shadow regs - FETCH_ADVANCE_INST 5 @ advance rPC, load rINST - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vAA<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_wide_high16: /* 0x19 */ -/* File: arm/op_const_wide_high16.S */ - /* const-wide/high16 vAA, #+BBBB000000000000 */ - FETCH r1, 1 @ r1<- 0000BBBB (zero-extended) - mov r3, rINST, lsr #8 @ r3<- AA - mov r0, #0 @ r0<- 00000000 - mov r1, r1, lsl #16 @ r1<- BBBB0000 - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - CLEAR_SHADOW_PAIR r3, r0, r2 @ Zero shadow regs - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[AA] - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r3, {r0-r1} @ vAA<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_string: /* 0x1a */ -/* File: arm/op_const_string.S */ -/* File: arm/const.S */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstString - EXPORT_PC - FETCH r0, 1 @ r0<- BBBB - mov r1, rINST, lsr #8 @ r1<- AA - add r2, rFP, #OFF_FP_SHADOWFRAME - mov r3, rSELF - bl MterpConstString @ (index, tgt_reg, shadow_frame, self) - PREFETCH_INST 2 @ load rINST - cmp r0, #0 @ fail? - bne MterpPossibleException @ let reference interpreter deal with it. - ADVANCE 2 @ advance rPC - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_const_string_jumbo: /* 0x1b */ -/* File: arm/op_const_string_jumbo.S */ - /* const/string vAA, String@BBBBBBBB */ - EXPORT_PC - FETCH r0, 1 @ r0<- bbbb (low) - FETCH r2, 2 @ r2<- BBBB (high) - mov r1, rINST, lsr #8 @ r1<- AA - orr r0, r0, r2, lsl #16 @ r1<- BBBBbbbb - add r2, rFP, #OFF_FP_SHADOWFRAME - mov r3, rSELF - bl MterpConstString @ (index, tgt_reg, shadow_frame, self) - PREFETCH_INST 3 @ advance rPC - cmp r0, #0 @ fail? - bne MterpPossibleException @ let reference interpreter deal with it. - ADVANCE 3 @ advance rPC - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_class: /* 0x1c */ -/* File: arm/op_const_class.S */ -/* File: arm/const.S */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstClass - EXPORT_PC - FETCH r0, 1 @ r0<- BBBB - mov r1, rINST, lsr #8 @ r1<- AA - add r2, rFP, #OFF_FP_SHADOWFRAME - mov r3, rSELF - bl MterpConstClass @ (index, tgt_reg, shadow_frame, self) - PREFETCH_INST 2 @ load rINST - cmp r0, #0 @ fail? - bne MterpPossibleException @ let reference interpreter deal with it. - ADVANCE 2 @ advance rPC - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_monitor_enter: /* 0x1d */ -/* File: arm/op_monitor_enter.S */ - /* - * Synchronize on an object. - */ - /* monitor-enter vAA */ - EXPORT_PC - mov r2, rINST, lsr #8 @ r2<- AA - GET_VREG r0, r2 @ r0<- vAA (object) - mov r1, rSELF @ r1<- self - bl artLockObjectFromCode - cmp r0, #0 - bne MterpException - FETCH_ADVANCE_INST 1 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_monitor_exit: /* 0x1e */ -/* File: arm/op_monitor_exit.S */ - /* - * Unlock an object. - * - * Exceptions that occur when unlocking a monitor need to appear as - * if they happened at the following instruction. See the Dalvik - * instruction spec. - */ - /* monitor-exit vAA */ - EXPORT_PC - mov r2, rINST, lsr #8 @ r2<- AA - GET_VREG r0, r2 @ r0<- vAA (object) - mov r1, rSELF @ r0<- self - bl artUnlockObjectFromCode @ r0<- success for unlock(self, obj) - cmp r0, #0 @ failed? - bne MterpException - FETCH_ADVANCE_INST 1 @ before throw: advance rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_check_cast: /* 0x1f */ -/* File: arm/op_check_cast.S */ - /* - * Check to see if a cast from one class to another is allowed. - */ - /* check-cast vAA, class@BBBB */ - EXPORT_PC - FETCH r0, 1 @ r0<- BBBB - mov r1, rINST, lsr #8 @ r1<- AA - VREG_INDEX_TO_ADDR r1, r1 @ r1<- &object - ldr r2, [rFP, #OFF_FP_METHOD] @ r2<- method - mov r3, rSELF @ r3<- self - bl MterpCheckCast @ (index, &obj, method, self) - PREFETCH_INST 2 - cmp r0, #0 - bne MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_instance_of: /* 0x20 */ -/* File: arm/op_instance_of.S */ - /* - * Check to see if an object reference is an instance of a class. - * - * Most common situation is a non-null object, being compared against - * an already-resolved class. - */ - /* instance-of vA, vB, class@CCCC */ - EXPORT_PC - FETCH r0, 1 @ r0<- CCCC - mov r1, rINST, lsr #12 @ r1<- B - VREG_INDEX_TO_ADDR r1, r1 @ r1<- &object - ldr r2, [rFP, #OFF_FP_METHOD] @ r2<- method - mov r3, rSELF @ r3<- self - bl MterpInstanceOf @ (index, &obj, method, self) - ldr r1, [rSELF, #THREAD_EXCEPTION_OFFSET] - ubfx r9, rINST, #8, #4 @ r9<- A - PREFETCH_INST 2 - cmp r1, #0 @ exception pending? - bne MterpException - ADVANCE 2 @ advance rPC - SET_VREG r0, r9 @ vA<- r0 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_array_length: /* 0x21 */ -/* File: arm/op_array_length.S */ - /* - * Return the length of an array. - */ - mov r1, rINST, lsr #12 @ r1<- B - ubfx r2, rINST, #8, #4 @ r2<- A - GET_VREG r0, r1 @ r0<- vB (object ref) - cmp r0, #0 @ is object null? - beq common_errNullObject @ yup, fail - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- array length - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r3, r2 @ vB<- length - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_new_instance: /* 0x22 */ -/* File: arm/op_new_instance.S */ - /* - * Create a new instance of a class. - */ - /* new-instance vAA, class@BBBB */ - EXPORT_PC - add r0, rFP, #OFF_FP_SHADOWFRAME - mov r1, rSELF - mov r2, rINST - bl MterpNewInstance @ (shadow_frame, self, inst_data) - cmp r0, #0 - beq MterpPossibleException - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_new_array: /* 0x23 */ -/* File: arm/op_new_array.S */ - /* - * Allocate an array of objects, specified with the array class - * and a count. - * - * The verifier guarantees that this is an array class, so we don't - * check for it here. - */ - /* new-array vA, vB, class@CCCC */ - EXPORT_PC - add r0, rFP, #OFF_FP_SHADOWFRAME - mov r1, rPC - mov r2, rINST - mov r3, rSELF - bl MterpNewArray - cmp r0, #0 - beq MterpPossibleException - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_filled_new_array: /* 0x24 */ -/* File: arm/op_filled_new_array.S */ - /* - * Create a new array with elements filled from registers. - * - * for: filled-new-array, filled-new-array/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ - .extern MterpFilledNewArray - EXPORT_PC - add r0, rFP, #OFF_FP_SHADOWFRAME - mov r1, rPC - mov r2, rSELF - bl MterpFilledNewArray - cmp r0, #0 - beq MterpPossibleException - FETCH_ADVANCE_INST 3 @ advance rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_filled_new_array_range: /* 0x25 */ -/* File: arm/op_filled_new_array_range.S */ -/* File: arm/op_filled_new_array.S */ - /* - * Create a new array with elements filled from registers. - * - * for: filled-new-array, filled-new-array/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ - .extern MterpFilledNewArrayRange - EXPORT_PC - add r0, rFP, #OFF_FP_SHADOWFRAME - mov r1, rPC - mov r2, rSELF - bl MterpFilledNewArrayRange - cmp r0, #0 - beq MterpPossibleException - FETCH_ADVANCE_INST 3 @ advance rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_fill_array_data: /* 0x26 */ -/* File: arm/op_fill_array_data.S */ - /* fill-array-data vAA, +BBBBBBBB */ - EXPORT_PC - FETCH r0, 1 @ r0<- bbbb (lo) - FETCH r1, 2 @ r1<- BBBB (hi) - mov r3, rINST, lsr #8 @ r3<- AA - orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb - GET_VREG r0, r3 @ r0<- vAA (array object) - add r1, rPC, r1, lsl #1 @ r1<- PC + BBBBbbbb*2 (array data off.) - bl MterpFillArrayData @ (obj, payload) - cmp r0, #0 @ 0 means an exception is thrown - beq MterpPossibleException @ exception? - FETCH_ADVANCE_INST 3 @ advance rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_throw: /* 0x27 */ -/* File: arm/op_throw.S */ - /* - * Throw an exception object in the current thread. - */ - /* throw vAA */ - EXPORT_PC - mov r2, rINST, lsr #8 @ r2<- AA - GET_VREG r1, r2 @ r1<- vAA (exception object) - cmp r1, #0 @ null object? - beq common_errNullObject @ yes, throw an NPE instead - str r1, [rSELF, #THREAD_EXCEPTION_OFFSET] @ thread->exception<- obj - b MterpException - -/* ------------------------------ */ - .balign 128 -.L_op_goto: /* 0x28 */ -/* File: arm/op_goto.S */ - /* - * Unconditional branch, 8-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto +AA */ - sbfx rINST, rINST, #8, #8 @ rINST<- ssssssAA (sign-extended) - b MterpCommonTakenBranchNoFlags - -/* ------------------------------ */ - .balign 128 -.L_op_goto_16: /* 0x29 */ -/* File: arm/op_goto_16.S */ - /* - * Unconditional branch, 16-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto/16 +AAAA */ - FETCH_S rINST, 1 @ rINST<- ssssAAAA (sign-extended) - b MterpCommonTakenBranchNoFlags - -/* ------------------------------ */ - .balign 128 -.L_op_goto_32: /* 0x2a */ -/* File: arm/op_goto_32.S */ - /* - * Unconditional branch, 32-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - * - * Unlike most opcodes, this one is allowed to branch to itself, so - * our "backward branch" test must be "<=0" instead of "<0". Because - * we need the V bit set, we'll use an adds to convert from Dalvik - * offset to byte offset. - */ - /* goto/32 +AAAAAAAA */ - FETCH r0, 1 @ r0<- aaaa (lo) - FETCH r3, 2 @ r1<- AAAA (hi) - orrs rINST, r0, r3, lsl #16 @ rINST<- AAAAaaaa - b MterpCommonTakenBranch - -/* ------------------------------ */ - .balign 128 -.L_op_packed_switch: /* 0x2b */ -/* File: arm/op_packed_switch.S */ - /* - * Handle a packed-switch or sparse-switch instruction. In both cases - * we decode it and hand it off to a helper function. - * - * We don't really expect backward branches in a switch statement, but - * they're perfectly legal, so we check for them here. - * - * for: packed-switch, sparse-switch - */ - /* op vAA, +BBBB */ - FETCH r0, 1 @ r0<- bbbb (lo) - FETCH r1, 2 @ r1<- BBBB (hi) - mov r3, rINST, lsr #8 @ r3<- AA - orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb - GET_VREG r1, r3 @ r1<- vAA - add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 - bl MterpDoPackedSwitch @ r0<- code-unit branch offset - movs rINST, r0 - b MterpCommonTakenBranch - -/* ------------------------------ */ - .balign 128 -.L_op_sparse_switch: /* 0x2c */ -/* File: arm/op_sparse_switch.S */ -/* File: arm/op_packed_switch.S */ - /* - * Handle a packed-switch or sparse-switch instruction. In both cases - * we decode it and hand it off to a helper function. - * - * We don't really expect backward branches in a switch statement, but - * they're perfectly legal, so we check for them here. - * - * for: packed-switch, sparse-switch - */ - /* op vAA, +BBBB */ - FETCH r0, 1 @ r0<- bbbb (lo) - FETCH r1, 2 @ r1<- BBBB (hi) - mov r3, rINST, lsr #8 @ r3<- AA - orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb - GET_VREG r1, r3 @ r1<- vAA - add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 - bl MterpDoSparseSwitch @ r0<- code-unit branch offset - movs rINST, r0 - b MterpCommonTakenBranch - - -/* ------------------------------ */ - .balign 128 -.L_op_cmpl_float: /* 0x2d */ -/* File: arm/op_cmpl_float.S */ - /* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * int compare(x, y) { - * if (x == y) { - * return 0; - * } else if (x > y) { - * return 1; - * } else if (x < y) { - * return -1; - * } else { - * return -1; - * } - * } - */ - /* op vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC - flds s0, [r2] @ s0<- vBB - flds s1, [r3] @ s1<- vCC - vcmpe.f32 s0, s1 @ compare (vBB, vCC) - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - mvn r0, #0 @ r0<- -1 (default) - GET_INST_OPCODE ip @ extract opcode from rINST - fmstat @ export status flags - movgt r0, #1 @ (greater than) r1<- 1 - moveq r0, #0 @ (equal) r1<- 0 - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_cmpg_float: /* 0x2e */ -/* File: arm/op_cmpg_float.S */ - /* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * int compare(x, y) { - * if (x == y) { - * return 0; - * } else if (x < y) { - * return -1; - * } else if (x > y) { - * return 1; - * } else { - * return 1; - * } - * } - */ - /* op vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC - flds s0, [r2] @ s0<- vBB - flds s1, [r3] @ s1<- vCC - vcmpe.f32 s0, s1 @ compare (vBB, vCC) - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - mov r0, #1 @ r0<- 1 (default) - GET_INST_OPCODE ip @ extract opcode from rINST - fmstat @ export status flags - mvnmi r0, #0 @ (less than) r1<- -1 - moveq r0, #0 @ (equal) r1<- 0 - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_cmpl_double: /* 0x2f */ -/* File: arm/op_cmpl_double.S */ - /* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * int compare(x, y) { - * if (x == y) { - * return 0; - * } else if (x > y) { - * return 1; - * } else if (x < y) { - * return -1; - * } else { - * return -1; - * } - * } - */ - /* op vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC - fldd d0, [r2] @ d0<- vBB - fldd d1, [r3] @ d1<- vCC - vcmpe.f64 d0, d1 @ compare (vBB, vCC) - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - mvn r0, #0 @ r0<- -1 (default) - GET_INST_OPCODE ip @ extract opcode from rINST - fmstat @ export status flags - movgt r0, #1 @ (greater than) r1<- 1 - moveq r0, #0 @ (equal) r1<- 0 - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_cmpg_double: /* 0x30 */ -/* File: arm/op_cmpg_double.S */ - /* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * int compare(x, y) { - * if (x == y) { - * return 0; - * } else if (x < y) { - * return -1; - * } else if (x > y) { - * return 1; - * } else { - * return 1; - * } - * } - */ - /* op vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC - fldd d0, [r2] @ d0<- vBB - fldd d1, [r3] @ d1<- vCC - vcmpe.f64 d0, d1 @ compare (vBB, vCC) - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - mov r0, #1 @ r0<- 1 (default) - GET_INST_OPCODE ip @ extract opcode from rINST - fmstat @ export status flags - mvnmi r0, #0 @ (less than) r1<- -1 - moveq r0, #0 @ (equal) r1<- 0 - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_cmp_long: /* 0x31 */ -/* File: arm/op_cmp_long.S */ - /* - * Compare two 64-bit values. Puts 0, 1, or -1 into the destination - * register based on the results of the comparison. - */ - /* cmp-long vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] - ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 - ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 - cmp r0, r2 - sbcs ip, r1, r3 @ Sets correct CCs for checking LT (but not EQ/NE) - mov ip, #0 - mvnlt ip, #0 @ -1 - cmpeq r0, r2 @ For correct EQ/NE, we may need to repeat the first CMP - orrne ip, #1 - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - SET_VREG ip, r9 @ vAA<- ip - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_eq: /* 0x32 */ -/* File: arm/op_if_eq.S */ -/* File: arm/bincmp.S */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - mov r1, rINST, lsr #12 @ r1<- B - ubfx r0, rINST, #8, #4 @ r0<- A - GET_VREG r3, r1 @ r3<- vB - GET_VREG r0, r0 @ r0<- vA - FETCH_S rINST, 1 @ rINST<- branch offset, in code units - cmp r0, r3 @ compare (vA, vB) - beq MterpCommonTakenBranchNoFlags - cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? - beq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_ne: /* 0x33 */ -/* File: arm/op_if_ne.S */ -/* File: arm/bincmp.S */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - mov r1, rINST, lsr #12 @ r1<- B - ubfx r0, rINST, #8, #4 @ r0<- A - GET_VREG r3, r1 @ r3<- vB - GET_VREG r0, r0 @ r0<- vA - FETCH_S rINST, 1 @ rINST<- branch offset, in code units - cmp r0, r3 @ compare (vA, vB) - bne MterpCommonTakenBranchNoFlags - cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? - beq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_lt: /* 0x34 */ -/* File: arm/op_if_lt.S */ -/* File: arm/bincmp.S */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - mov r1, rINST, lsr #12 @ r1<- B - ubfx r0, rINST, #8, #4 @ r0<- A - GET_VREG r3, r1 @ r3<- vB - GET_VREG r0, r0 @ r0<- vA - FETCH_S rINST, 1 @ rINST<- branch offset, in code units - cmp r0, r3 @ compare (vA, vB) - blt MterpCommonTakenBranchNoFlags - cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? - beq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_ge: /* 0x35 */ -/* File: arm/op_if_ge.S */ -/* File: arm/bincmp.S */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - mov r1, rINST, lsr #12 @ r1<- B - ubfx r0, rINST, #8, #4 @ r0<- A - GET_VREG r3, r1 @ r3<- vB - GET_VREG r0, r0 @ r0<- vA - FETCH_S rINST, 1 @ rINST<- branch offset, in code units - cmp r0, r3 @ compare (vA, vB) - bge MterpCommonTakenBranchNoFlags - cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? - beq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_gt: /* 0x36 */ -/* File: arm/op_if_gt.S */ -/* File: arm/bincmp.S */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - mov r1, rINST, lsr #12 @ r1<- B - ubfx r0, rINST, #8, #4 @ r0<- A - GET_VREG r3, r1 @ r3<- vB - GET_VREG r0, r0 @ r0<- vA - FETCH_S rINST, 1 @ rINST<- branch offset, in code units - cmp r0, r3 @ compare (vA, vB) - bgt MterpCommonTakenBranchNoFlags - cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? - beq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_le: /* 0x37 */ -/* File: arm/op_if_le.S */ -/* File: arm/bincmp.S */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - mov r1, rINST, lsr #12 @ r1<- B - ubfx r0, rINST, #8, #4 @ r0<- A - GET_VREG r3, r1 @ r3<- vB - GET_VREG r0, r0 @ r0<- vA - FETCH_S rINST, 1 @ rINST<- branch offset, in code units - cmp r0, r3 @ compare (vA, vB) - ble MterpCommonTakenBranchNoFlags - cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? - beq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_eqz: /* 0x38 */ -/* File: arm/op_if_eqz.S */ -/* File: arm/zcmp.S */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - mov r0, rINST, lsr #8 @ r0<- AA - GET_VREG r0, r0 @ r0<- vAA - FETCH_S rINST, 1 @ rINST<- branch offset, in code units - cmp r0, #0 @ compare (vA, 0) - beq MterpCommonTakenBranchNoFlags - cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? - beq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_nez: /* 0x39 */ -/* File: arm/op_if_nez.S */ -/* File: arm/zcmp.S */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - mov r0, rINST, lsr #8 @ r0<- AA - GET_VREG r0, r0 @ r0<- vAA - FETCH_S rINST, 1 @ rINST<- branch offset, in code units - cmp r0, #0 @ compare (vA, 0) - bne MterpCommonTakenBranchNoFlags - cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? - beq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_ltz: /* 0x3a */ -/* File: arm/op_if_ltz.S */ -/* File: arm/zcmp.S */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - mov r0, rINST, lsr #8 @ r0<- AA - GET_VREG r0, r0 @ r0<- vAA - FETCH_S rINST, 1 @ rINST<- branch offset, in code units - cmp r0, #0 @ compare (vA, 0) - blt MterpCommonTakenBranchNoFlags - cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? - beq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_gez: /* 0x3b */ -/* File: arm/op_if_gez.S */ -/* File: arm/zcmp.S */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - mov r0, rINST, lsr #8 @ r0<- AA - GET_VREG r0, r0 @ r0<- vAA - FETCH_S rINST, 1 @ rINST<- branch offset, in code units - cmp r0, #0 @ compare (vA, 0) - bge MterpCommonTakenBranchNoFlags - cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? - beq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_gtz: /* 0x3c */ -/* File: arm/op_if_gtz.S */ -/* File: arm/zcmp.S */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - mov r0, rINST, lsr #8 @ r0<- AA - GET_VREG r0, r0 @ r0<- vAA - FETCH_S rINST, 1 @ rINST<- branch offset, in code units - cmp r0, #0 @ compare (vA, 0) - bgt MterpCommonTakenBranchNoFlags - cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? - beq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_lez: /* 0x3d */ -/* File: arm/op_if_lez.S */ -/* File: arm/zcmp.S */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - mov r0, rINST, lsr #8 @ r0<- AA - GET_VREG r0, r0 @ r0<- vAA - FETCH_S rINST, 1 @ rINST<- branch offset, in code units - cmp r0, #0 @ compare (vA, 0) - ble MterpCommonTakenBranchNoFlags - cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? - beq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_3e: /* 0x3e */ -/* File: arm/op_unused_3e.S */ -/* File: arm/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_3f: /* 0x3f */ -/* File: arm/op_unused_3f.S */ -/* File: arm/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_40: /* 0x40 */ -/* File: arm/op_unused_40.S */ -/* File: arm/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_41: /* 0x41 */ -/* File: arm/op_unused_41.S */ -/* File: arm/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_42: /* 0x42 */ -/* File: arm/op_unused_42.S */ -/* File: arm/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_43: /* 0x43 */ -/* File: arm/op_unused_43.S */ -/* File: arm/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_aget: /* 0x44 */ -/* File: arm/op_aget.S */ - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B r2, 1, 0 @ r2<- BB - mov r9, rINST, lsr #8 @ r9<- AA - FETCH_B r3, 1, 1 @ r3<- CC - GET_VREG r0, r2 @ r0<- vBB (array object) - GET_VREG r1, r3 @ r1<- vCC (requested index) - cmp r0, #0 @ null array object? - beq common_errNullObject @ yes, bail - ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length - add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width - cmp r1, r3 @ compare unsigned index, length - bcs common_errArrayIndex @ index >= length, bail - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - ldr r2, [r0, #MIRROR_INT_ARRAY_DATA_OFFSET] @ r2<- vBB[vCC] - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r2, r9 @ vAA<- r2 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aget_wide: /* 0x45 */ -/* File: arm/op_aget_wide.S */ - /* - * Array get, 64 bits. vAA <- vBB[vCC]. - * - * Arrays of long/double are 64-bit aligned, so it's okay to use LDRD. - */ - /* aget-wide vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - GET_VREG r0, r2 @ r0<- vBB (array object) - GET_VREG r1, r3 @ r1<- vCC (requested index) - cmp r0, #0 @ null array object? - beq common_errNullObject @ yes, bail - ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length - add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width - cmp r1, r3 @ compare unsigned index, length - bcs common_errArrayIndex @ index >= length, bail - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs - ldrd r2, [r0, #MIRROR_WIDE_ARRAY_DATA_OFFSET] @ r2/r3<- vBB[vCC] - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r2-r3} @ vAA/vAA+1<- r2/r3 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aget_object: /* 0x46 */ -/* File: arm/op_aget_object.S */ - /* - * Array object get. vAA <- vBB[vCC]. - * - * for: aget-object - */ - /* op vAA, vBB, vCC */ - FETCH_B r2, 1, 0 @ r2<- BB - mov r9, rINST, lsr #8 @ r9<- AA - FETCH_B r3, 1, 1 @ r3<- CC - EXPORT_PC - GET_VREG r0, r2 @ r0<- vBB (array object) - GET_VREG r1, r3 @ r1<- vCC (requested index) - bl artAGetObjectFromMterp @ (array, index) - ldr r1, [rSELF, #THREAD_EXCEPTION_OFFSET] - PREFETCH_INST 2 - cmp r1, #0 - bne MterpException - SET_VREG_OBJECT r0, r9 - ADVANCE 2 - GET_INST_OPCODE ip - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aget_boolean: /* 0x47 */ -/* File: arm/op_aget_boolean.S */ -/* File: arm/op_aget.S */ - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B r2, 1, 0 @ r2<- BB - mov r9, rINST, lsr #8 @ r9<- AA - FETCH_B r3, 1, 1 @ r3<- CC - GET_VREG r0, r2 @ r0<- vBB (array object) - GET_VREG r1, r3 @ r1<- vCC (requested index) - cmp r0, #0 @ null array object? - beq common_errNullObject @ yes, bail - ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length - add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width - cmp r1, r3 @ compare unsigned index, length - bcs common_errArrayIndex @ index >= length, bail - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - ldrb r2, [r0, #MIRROR_BOOLEAN_ARRAY_DATA_OFFSET] @ r2<- vBB[vCC] - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r2, r9 @ vAA<- r2 - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_aget_byte: /* 0x48 */ -/* File: arm/op_aget_byte.S */ -/* File: arm/op_aget.S */ - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B r2, 1, 0 @ r2<- BB - mov r9, rINST, lsr #8 @ r9<- AA - FETCH_B r3, 1, 1 @ r3<- CC - GET_VREG r0, r2 @ r0<- vBB (array object) - GET_VREG r1, r3 @ r1<- vCC (requested index) - cmp r0, #0 @ null array object? - beq common_errNullObject @ yes, bail - ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length - add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width - cmp r1, r3 @ compare unsigned index, length - bcs common_errArrayIndex @ index >= length, bail - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - ldrsb r2, [r0, #MIRROR_BYTE_ARRAY_DATA_OFFSET] @ r2<- vBB[vCC] - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r2, r9 @ vAA<- r2 - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_aget_char: /* 0x49 */ -/* File: arm/op_aget_char.S */ -/* File: arm/op_aget.S */ - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B r2, 1, 0 @ r2<- BB - mov r9, rINST, lsr #8 @ r9<- AA - FETCH_B r3, 1, 1 @ r3<- CC - GET_VREG r0, r2 @ r0<- vBB (array object) - GET_VREG r1, r3 @ r1<- vCC (requested index) - cmp r0, #0 @ null array object? - beq common_errNullObject @ yes, bail - ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length - add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width - cmp r1, r3 @ compare unsigned index, length - bcs common_errArrayIndex @ index >= length, bail - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - ldrh r2, [r0, #MIRROR_CHAR_ARRAY_DATA_OFFSET] @ r2<- vBB[vCC] - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r2, r9 @ vAA<- r2 - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_aget_short: /* 0x4a */ -/* File: arm/op_aget_short.S */ -/* File: arm/op_aget.S */ - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B r2, 1, 0 @ r2<- BB - mov r9, rINST, lsr #8 @ r9<- AA - FETCH_B r3, 1, 1 @ r3<- CC - GET_VREG r0, r2 @ r0<- vBB (array object) - GET_VREG r1, r3 @ r1<- vCC (requested index) - cmp r0, #0 @ null array object? - beq common_errNullObject @ yes, bail - ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length - add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width - cmp r1, r3 @ compare unsigned index, length - bcs common_errArrayIndex @ index >= length, bail - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - ldrsh r2, [r0, #MIRROR_SHORT_ARRAY_DATA_OFFSET] @ r2<- vBB[vCC] - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r2, r9 @ vAA<- r2 - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_aput: /* 0x4b */ -/* File: arm/op_aput.S */ - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B r2, 1, 0 @ r2<- BB - mov r9, rINST, lsr #8 @ r9<- AA - FETCH_B r3, 1, 1 @ r3<- CC - GET_VREG r0, r2 @ r0<- vBB (array object) - GET_VREG r1, r3 @ r1<- vCC (requested index) - cmp r0, #0 @ null array object? - beq common_errNullObject @ yes, bail - ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length - add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width - cmp r1, r3 @ compare unsigned index, length - bcs common_errArrayIndex @ index >= length, bail - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - GET_VREG r2, r9 @ r2<- vAA - GET_INST_OPCODE ip @ extract opcode from rINST - str r2, [r0, #MIRROR_INT_ARRAY_DATA_OFFSET] @ vBB[vCC]<- r2 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aput_wide: /* 0x4c */ -/* File: arm/op_aput_wide.S */ - /* - * Array put, 64 bits. vBB[vCC] <- vAA. - * - * Arrays of long/double are 64-bit aligned, so it's okay to use STRD. - */ - /* aput-wide vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - GET_VREG r0, r2 @ r0<- vBB (array object) - GET_VREG r1, r3 @ r1<- vCC (requested index) - cmp r0, #0 @ null array object? - beq common_errNullObject @ yes, bail - ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length - add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width - cmp r1, r3 @ compare unsigned index, length - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] - bcs common_errArrayIndex @ index >= length, bail - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - ldmia r9, {r2-r3} @ r2/r3<- vAA/vAA+1 - GET_INST_OPCODE ip @ extract opcode from rINST - strd r2, [r0, #MIRROR_WIDE_ARRAY_DATA_OFFSET] @ r2/r3<- vBB[vCC] - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aput_object: /* 0x4d */ -/* File: arm/op_aput_object.S */ - /* - * Store an object into an array. vBB[vCC] <- vAA. - */ - /* op vAA, vBB, vCC */ - EXPORT_PC - add r0, rFP, #OFF_FP_SHADOWFRAME - mov r1, rPC - mov r2, rINST - bl MterpAputObject - cmp r0, #0 - beq MterpPossibleException - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aput_boolean: /* 0x4e */ -/* File: arm/op_aput_boolean.S */ -/* File: arm/op_aput.S */ - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B r2, 1, 0 @ r2<- BB - mov r9, rINST, lsr #8 @ r9<- AA - FETCH_B r3, 1, 1 @ r3<- CC - GET_VREG r0, r2 @ r0<- vBB (array object) - GET_VREG r1, r3 @ r1<- vCC (requested index) - cmp r0, #0 @ null array object? - beq common_errNullObject @ yes, bail - ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length - add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width - cmp r1, r3 @ compare unsigned index, length - bcs common_errArrayIndex @ index >= length, bail - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - GET_VREG r2, r9 @ r2<- vAA - GET_INST_OPCODE ip @ extract opcode from rINST - strb r2, [r0, #MIRROR_BOOLEAN_ARRAY_DATA_OFFSET] @ vBB[vCC]<- r2 - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_aput_byte: /* 0x4f */ -/* File: arm/op_aput_byte.S */ -/* File: arm/op_aput.S */ - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B r2, 1, 0 @ r2<- BB - mov r9, rINST, lsr #8 @ r9<- AA - FETCH_B r3, 1, 1 @ r3<- CC - GET_VREG r0, r2 @ r0<- vBB (array object) - GET_VREG r1, r3 @ r1<- vCC (requested index) - cmp r0, #0 @ null array object? - beq common_errNullObject @ yes, bail - ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length - add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width - cmp r1, r3 @ compare unsigned index, length - bcs common_errArrayIndex @ index >= length, bail - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - GET_VREG r2, r9 @ r2<- vAA - GET_INST_OPCODE ip @ extract opcode from rINST - strb r2, [r0, #MIRROR_BYTE_ARRAY_DATA_OFFSET] @ vBB[vCC]<- r2 - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_aput_char: /* 0x50 */ -/* File: arm/op_aput_char.S */ -/* File: arm/op_aput.S */ - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B r2, 1, 0 @ r2<- BB - mov r9, rINST, lsr #8 @ r9<- AA - FETCH_B r3, 1, 1 @ r3<- CC - GET_VREG r0, r2 @ r0<- vBB (array object) - GET_VREG r1, r3 @ r1<- vCC (requested index) - cmp r0, #0 @ null array object? - beq common_errNullObject @ yes, bail - ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length - add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width - cmp r1, r3 @ compare unsigned index, length - bcs common_errArrayIndex @ index >= length, bail - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - GET_VREG r2, r9 @ r2<- vAA - GET_INST_OPCODE ip @ extract opcode from rINST - strh r2, [r0, #MIRROR_CHAR_ARRAY_DATA_OFFSET] @ vBB[vCC]<- r2 - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_aput_short: /* 0x51 */ -/* File: arm/op_aput_short.S */ -/* File: arm/op_aput.S */ - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B r2, 1, 0 @ r2<- BB - mov r9, rINST, lsr #8 @ r9<- AA - FETCH_B r3, 1, 1 @ r3<- CC - GET_VREG r0, r2 @ r0<- vBB (array object) - GET_VREG r1, r3 @ r1<- vCC (requested index) - cmp r0, #0 @ null array object? - beq common_errNullObject @ yes, bail - ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length - add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width - cmp r1, r3 @ compare unsigned index, length - bcs common_errArrayIndex @ index >= length, bail - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - GET_VREG r2, r9 @ r2<- vAA - GET_INST_OPCODE ip @ extract opcode from rINST - strh r2, [r0, #MIRROR_SHORT_ARRAY_DATA_OFFSET] @ vBB[vCC]<- r2 - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_iget: /* 0x52 */ -/* File: arm/op_iget.S */ -/* File: arm/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetU32 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpIGetU32 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_wide: /* 0x53 */ -/* File: arm/op_iget_wide.S */ -/* File: arm/op_iget.S */ -/* File: arm/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetU64 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpIGetU64 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_object: /* 0x54 */ -/* File: arm/op_iget_object.S */ -/* File: arm/op_iget.S */ -/* File: arm/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetObj - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpIGetObj - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_boolean: /* 0x55 */ -/* File: arm/op_iget_boolean.S */ -/* File: arm/op_iget.S */ -/* File: arm/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetU8 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpIGetU8 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_byte: /* 0x56 */ -/* File: arm/op_iget_byte.S */ -/* File: arm/op_iget.S */ -/* File: arm/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetI8 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpIGetI8 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_char: /* 0x57 */ -/* File: arm/op_iget_char.S */ -/* File: arm/op_iget.S */ -/* File: arm/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetU16 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpIGetU16 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_short: /* 0x58 */ -/* File: arm/op_iget_short.S */ -/* File: arm/op_iget.S */ -/* File: arm/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetI16 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpIGetI16 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_iput: /* 0x59 */ -/* File: arm/op_iput.S */ -/* File: arm/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutU32 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpIPutU32 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_wide: /* 0x5a */ -/* File: arm/op_iput_wide.S */ -/* File: arm/op_iput.S */ -/* File: arm/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutU64 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpIPutU64 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_object: /* 0x5b */ -/* File: arm/op_iput_object.S */ -/* File: arm/op_iput.S */ -/* File: arm/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutObj - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpIPutObj - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_boolean: /* 0x5c */ -/* File: arm/op_iput_boolean.S */ -/* File: arm/op_iput.S */ -/* File: arm/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutU8 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpIPutU8 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_byte: /* 0x5d */ -/* File: arm/op_iput_byte.S */ -/* File: arm/op_iput.S */ -/* File: arm/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutI8 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpIPutI8 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_char: /* 0x5e */ -/* File: arm/op_iput_char.S */ -/* File: arm/op_iput.S */ -/* File: arm/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutU16 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpIPutU16 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_short: /* 0x5f */ -/* File: arm/op_iput_short.S */ -/* File: arm/op_iput.S */ -/* File: arm/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutI16 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpIPutI16 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_sget: /* 0x60 */ -/* File: arm/op_sget.S */ -/* File: arm/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetU32 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpSGetU32 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_sget_wide: /* 0x61 */ -/* File: arm/op_sget_wide.S */ -/* File: arm/op_sget.S */ -/* File: arm/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetU64 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpSGetU64 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_sget_object: /* 0x62 */ -/* File: arm/op_sget_object.S */ -/* File: arm/op_sget.S */ -/* File: arm/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetObj - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpSGetObj - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_sget_boolean: /* 0x63 */ -/* File: arm/op_sget_boolean.S */ -/* File: arm/op_sget.S */ -/* File: arm/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetU8 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpSGetU8 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_sget_byte: /* 0x64 */ -/* File: arm/op_sget_byte.S */ -/* File: arm/op_sget.S */ -/* File: arm/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetI8 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpSGetI8 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_sget_char: /* 0x65 */ -/* File: arm/op_sget_char.S */ -/* File: arm/op_sget.S */ -/* File: arm/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetU16 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpSGetU16 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_sget_short: /* 0x66 */ -/* File: arm/op_sget_short.S */ -/* File: arm/op_sget.S */ -/* File: arm/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetI16 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpSGetI16 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_sput: /* 0x67 */ -/* File: arm/op_sput.S */ -/* File: arm/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutU32 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpSPutU32 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_sput_wide: /* 0x68 */ -/* File: arm/op_sput_wide.S */ -/* File: arm/op_sput.S */ -/* File: arm/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutU64 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpSPutU64 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_sput_object: /* 0x69 */ -/* File: arm/op_sput_object.S */ -/* File: arm/op_sput.S */ -/* File: arm/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutObj - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpSPutObj - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_sput_boolean: /* 0x6a */ -/* File: arm/op_sput_boolean.S */ -/* File: arm/op_sput.S */ -/* File: arm/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutU8 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpSPutU8 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_sput_byte: /* 0x6b */ -/* File: arm/op_sput_byte.S */ -/* File: arm/op_sput.S */ -/* File: arm/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutI8 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpSPutI8 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_sput_char: /* 0x6c */ -/* File: arm/op_sput_char.S */ -/* File: arm/op_sput.S */ -/* File: arm/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutU16 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpSPutU16 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_sput_short: /* 0x6d */ -/* File: arm/op_sput_short.S */ -/* File: arm/op_sput.S */ -/* File: arm/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutI16 - mov r0, rPC @ arg0: Instruction* inst - mov r1, rINST @ arg1: uint16_t inst_data - add r2, rFP, #OFF_FP_SHADOWFRAME @ arg2: ShadowFrame* sf - mov r3, rSELF @ arg3: Thread* self - PREFETCH_INST 2 @ prefetch next opcode - bl MterpSPutI16 - cmp r0, #0 - beq MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual: /* 0x6e */ -/* File: arm/op_invoke_virtual.S */ -/* File: arm/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtual - EXPORT_PC - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - mov r3, rINST - bl MterpInvokeVirtual - cmp r0, #0 - beq MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cmp r0, #0 - bne MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - - - /* - * Handle a virtual method call. - * - * for: invoke-virtual, invoke-virtual/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_super: /* 0x6f */ -/* File: arm/op_invoke_super.S */ -/* File: arm/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeSuper - EXPORT_PC - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - mov r3, rINST - bl MterpInvokeSuper - cmp r0, #0 - beq MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cmp r0, #0 - bne MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - - - /* - * Handle a "super" method call. - * - * for: invoke-super, invoke-super/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_direct: /* 0x70 */ -/* File: arm/op_invoke_direct.S */ -/* File: arm/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeDirect - EXPORT_PC - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - mov r3, rINST - bl MterpInvokeDirect - cmp r0, #0 - beq MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cmp r0, #0 - bne MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_static: /* 0x71 */ -/* File: arm/op_invoke_static.S */ -/* File: arm/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeStatic - EXPORT_PC - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - mov r3, rINST - bl MterpInvokeStatic - cmp r0, #0 - beq MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cmp r0, #0 - bne MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - - - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_interface: /* 0x72 */ -/* File: arm/op_invoke_interface.S */ -/* File: arm/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeInterface - EXPORT_PC - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - mov r3, rINST - bl MterpInvokeInterface - cmp r0, #0 - beq MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cmp r0, #0 - bne MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - - - /* - * Handle an interface method call. - * - * for: invoke-interface, invoke-interface/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - -/* ------------------------------ */ - .balign 128 -.L_op_return_void_no_barrier: /* 0x73 */ -/* File: arm/op_return_void_no_barrier.S */ - ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] - mov r0, rSELF - ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - blne MterpSuspendCheck @ (self) - mov r0, #0 - mov r1, #0 - b MterpReturn - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual_range: /* 0x74 */ -/* File: arm/op_invoke_virtual_range.S */ -/* File: arm/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtualRange - EXPORT_PC - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - mov r3, rINST - bl MterpInvokeVirtualRange - cmp r0, #0 - beq MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cmp r0, #0 - bne MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_super_range: /* 0x75 */ -/* File: arm/op_invoke_super_range.S */ -/* File: arm/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeSuperRange - EXPORT_PC - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - mov r3, rINST - bl MterpInvokeSuperRange - cmp r0, #0 - beq MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cmp r0, #0 - bne MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_direct_range: /* 0x76 */ -/* File: arm/op_invoke_direct_range.S */ -/* File: arm/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeDirectRange - EXPORT_PC - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - mov r3, rINST - bl MterpInvokeDirectRange - cmp r0, #0 - beq MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cmp r0, #0 - bne MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_static_range: /* 0x77 */ -/* File: arm/op_invoke_static_range.S */ -/* File: arm/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeStaticRange - EXPORT_PC - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - mov r3, rINST - bl MterpInvokeStaticRange - cmp r0, #0 - beq MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cmp r0, #0 - bne MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_interface_range: /* 0x78 */ -/* File: arm/op_invoke_interface_range.S */ -/* File: arm/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeInterfaceRange - EXPORT_PC - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - mov r3, rINST - bl MterpInvokeInterfaceRange - cmp r0, #0 - beq MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cmp r0, #0 - bne MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_79: /* 0x79 */ -/* File: arm/op_unused_79.S */ -/* File: arm/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_7a: /* 0x7a */ -/* File: arm/op_unused_7a.S */ -/* File: arm/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_neg_int: /* 0x7b */ -/* File: arm/op_neg_int.S */ -/* File: arm/unop.S */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op r0". - * This could be an ARM instruction or a function call. - * - * for: neg-int, not-int, neg-float, int-to-float, float-to-int, - * int-to-byte, int-to-char, int-to-short - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r0, r3 @ r0<- vB - @ optional op; may set condition codes - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - rsb r0, r0, #0 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 8-9 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_not_int: /* 0x7c */ -/* File: arm/op_not_int.S */ -/* File: arm/unop.S */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op r0". - * This could be an ARM instruction or a function call. - * - * for: neg-int, not-int, neg-float, int-to-float, float-to-int, - * int-to-byte, int-to-char, int-to-short - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r0, r3 @ r0<- vB - @ optional op; may set condition codes - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - mvn r0, r0 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 8-9 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_neg_long: /* 0x7d */ -/* File: arm/op_neg_long.S */ -/* File: arm/unopWide.S */ - /* - * Generic 64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op r0/r1". - * This could be an ARM instruction or a function call. - * - * For: neg-long, not-long, neg-double, long-to-double, double-to-long - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx rINST, rINST, #8, #4 @ rINST<- A - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] - ldmia r3, {r0-r1} @ r0/r1<- vAA - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - rsbs r0, r0, #0 @ optional op; may set condition codes - rsc r1, r1, #0 @ r0/r1<- op, r2-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vAA<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 10-11 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_not_long: /* 0x7e */ -/* File: arm/op_not_long.S */ -/* File: arm/unopWide.S */ - /* - * Generic 64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op r0/r1". - * This could be an ARM instruction or a function call. - * - * For: neg-long, not-long, neg-double, long-to-double, double-to-long - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx rINST, rINST, #8, #4 @ rINST<- A - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] - ldmia r3, {r0-r1} @ r0/r1<- vAA - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - mvn r0, r0 @ optional op; may set condition codes - mvn r1, r1 @ r0/r1<- op, r2-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vAA<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 10-11 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_neg_float: /* 0x7f */ -/* File: arm/op_neg_float.S */ -/* File: arm/unop.S */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op r0". - * This could be an ARM instruction or a function call. - * - * for: neg-int, not-int, neg-float, int-to-float, float-to-int, - * int-to-byte, int-to-char, int-to-short - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r0, r3 @ r0<- vB - @ optional op; may set condition codes - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - add r0, r0, #0x80000000 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 8-9 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_neg_double: /* 0x80 */ -/* File: arm/op_neg_double.S */ -/* File: arm/unopWide.S */ - /* - * Generic 64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op r0/r1". - * This could be an ARM instruction or a function call. - * - * For: neg-long, not-long, neg-double, long-to-double, double-to-long - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx rINST, rINST, #8, #4 @ rINST<- A - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] - ldmia r3, {r0-r1} @ r0/r1<- vAA - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - @ optional op; may set condition codes - add r1, r1, #0x80000000 @ r0/r1<- op, r2-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vAA<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 10-11 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_long: /* 0x81 */ -/* File: arm/op_int_to_long.S */ -/* File: arm/unopWider.S */ - /* - * Generic 32bit-to-64bit unary operation. Provide an "instr" line - * that specifies an instruction that performs "result = op r0", where - * "result" is a 64-bit quantity in r0/r1. - * - * For: int-to-long, int-to-double, float-to-long, float-to-double - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx rINST, rINST, #8, #4 @ rINST<- A - GET_VREG r0, r3 @ r0<- vB - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] - @ optional op; may set condition codes - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - mov r1, r0, asr #31 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 9-10 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_float: /* 0x82 */ -/* File: arm/op_int_to_float.S */ -/* File: arm/funop.S */ - /* - * Generic 32-bit unary floating-point operation. Provide an "instr" - * line that specifies an instruction that performs "s1 = op s0". - * - * for: int-to-float, float-to-int - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB - flds s0, [r3] @ s0<- vB - ubfx r9, rINST, #8, #4 @ r9<- A - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - fsitos s1, s0 @ s1<- op - GET_INST_OPCODE ip @ extract opcode from rINST - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA - fsts s1, [r9] @ vA<- s1 - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_double: /* 0x83 */ -/* File: arm/op_int_to_double.S */ -/* File: arm/funopWider.S */ - /* - * Generic 32bit-to-64bit floating point unary operation. Provide an - * "instr" line that specifies an instruction that performs "d0 = op s0". - * - * For: int-to-double, float-to-double - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB - flds s0, [r3] @ s0<- vB - ubfx r9, rINST, #8, #4 @ r9<- A - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - fsitod d0, s0 @ d0<- op - CLEAR_SHADOW_PAIR r9, ip, lr @ Zero shadow regs - GET_INST_OPCODE ip @ extract opcode from rINST - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA - fstd d0, [r9] @ vA<- d0 - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_long_to_int: /* 0x84 */ -/* File: arm/op_long_to_int.S */ -/* we ignore the high word, making this equivalent to a 32-bit reg move */ -/* File: arm/op_move.S */ - /* for move, move-object, long-to-int */ - /* op vA, vB */ - mov r1, rINST, lsr #12 @ r1<- B from 15:12 - ubfx r0, rINST, #8, #4 @ r0<- A from 11:8 - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - GET_VREG r2, r1 @ r2<- fp[B] - GET_INST_OPCODE ip @ ip<- opcode from rINST - .if 0 - SET_VREG_OBJECT r2, r0 @ fp[A]<- r2 - .else - SET_VREG r2, r0 @ fp[A]<- r2 - .endif - GOTO_OPCODE ip @ execute next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_long_to_float: /* 0x85 */ -/* File: arm/op_long_to_float.S */ -/* File: arm/unopNarrower.S */ - /* - * Generic 64bit-to-32bit unary operation. Provide an "instr" line - * that specifies an instruction that performs "result = op r0/r1", where - * "result" is a 32-bit quantity in r0. - * - * For: long-to-float, double-to-int, double-to-float - * - * (This would work for long-to-int, but that instruction is actually - * an exact match for op_move.) - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] - ldmia r3, {r0-r1} @ r0/r1<- vB/vB+1 - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - @ optional op; may set condition codes - bl __aeabi_l2f @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 9-10 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_long_to_double: /* 0x86 */ -/* File: arm/op_long_to_double.S */ - /* - * Specialised 64-bit floating point operation. - * - * Note: The result will be returned in d2. - * - * For: long-to-double - */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[A] - vldr d0, [r3] @ d0<- vAA - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - - vcvt.f64.s32 d1, s1 @ d1<- (double)(vAAh) - vcvt.f64.u32 d2, s0 @ d2<- (double)(vAAl) - vldr d3, constvalop_long_to_double - vmla.f64 d2, d1, d3 @ d2<- vAAh*2^32 + vAAl - - GET_INST_OPCODE ip @ extract opcode from rINST - vstr.64 d2, [r9] @ vAA<- d2 - GOTO_OPCODE ip @ jump to next instruction - - /* literal pool helper */ -constvalop_long_to_double: - .8byte 0x41f0000000000000 - -/* ------------------------------ */ - .balign 128 -.L_op_float_to_int: /* 0x87 */ -/* File: arm/op_float_to_int.S */ -/* File: arm/funop.S */ - /* - * Generic 32-bit unary floating-point operation. Provide an "instr" - * line that specifies an instruction that performs "s1 = op s0". - * - * for: int-to-float, float-to-int - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB - flds s0, [r3] @ s0<- vB - ubfx r9, rINST, #8, #4 @ r9<- A - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - ftosizs s1, s0 @ s1<- op - GET_INST_OPCODE ip @ extract opcode from rINST - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA - fsts s1, [r9] @ vA<- s1 - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_float_to_long: /* 0x88 */ -/* File: arm/op_float_to_long.S */ -/* File: arm/unopWider.S */ - /* - * Generic 32bit-to-64bit unary operation. Provide an "instr" line - * that specifies an instruction that performs "result = op r0", where - * "result" is a 64-bit quantity in r0/r1. - * - * For: int-to-long, int-to-double, float-to-long, float-to-double - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx rINST, rINST, #8, #4 @ rINST<- A - GET_VREG r0, r3 @ r0<- vB - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] - @ optional op; may set condition codes - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - bl f2l_doconv @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 9-10 instructions */ - - - -/* ------------------------------ */ - .balign 128 -.L_op_float_to_double: /* 0x89 */ -/* File: arm/op_float_to_double.S */ -/* File: arm/funopWider.S */ - /* - * Generic 32bit-to-64bit floating point unary operation. Provide an - * "instr" line that specifies an instruction that performs "d0 = op s0". - * - * For: int-to-double, float-to-double - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB - flds s0, [r3] @ s0<- vB - ubfx r9, rINST, #8, #4 @ r9<- A - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - vcvt.f64.f32 d0, s0 @ d0<- op - CLEAR_SHADOW_PAIR r9, ip, lr @ Zero shadow regs - GET_INST_OPCODE ip @ extract opcode from rINST - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA - fstd d0, [r9] @ vA<- d0 - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_double_to_int: /* 0x8a */ -/* File: arm/op_double_to_int.S */ -/* File: arm/funopNarrower.S */ - /* - * Generic 64bit-to-32bit unary floating point operation. Provide an - * "instr" line that specifies an instruction that performs "s0 = op d0". - * - * For: double-to-int, double-to-float - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB - fldd d0, [r3] @ d0<- vB - ubfx r9, rINST, #8, #4 @ r9<- A - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - ftosizd s0, d0 @ s0<- op - GET_INST_OPCODE ip @ extract opcode from rINST - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA - fsts s0, [r9] @ vA<- s0 - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_double_to_long: /* 0x8b */ -/* File: arm/op_double_to_long.S */ -/* File: arm/unopWide.S */ - /* - * Generic 64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op r0/r1". - * This could be an ARM instruction or a function call. - * - * For: neg-long, not-long, neg-double, long-to-double, double-to-long - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx rINST, rINST, #8, #4 @ rINST<- A - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] - ldmia r3, {r0-r1} @ r0/r1<- vAA - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - @ optional op; may set condition codes - bl d2l_doconv @ r0/r1<- op, r2-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vAA<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 10-11 instructions */ - - - -/* ------------------------------ */ - .balign 128 -.L_op_double_to_float: /* 0x8c */ -/* File: arm/op_double_to_float.S */ -/* File: arm/funopNarrower.S */ - /* - * Generic 64bit-to-32bit unary floating point operation. Provide an - * "instr" line that specifies an instruction that performs "s0 = op d0". - * - * For: double-to-int, double-to-float - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB - fldd d0, [r3] @ d0<- vB - ubfx r9, rINST, #8, #4 @ r9<- A - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - vcvt.f32.f64 s0, d0 @ s0<- op - GET_INST_OPCODE ip @ extract opcode from rINST - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA - fsts s0, [r9] @ vA<- s0 - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_byte: /* 0x8d */ -/* File: arm/op_int_to_byte.S */ -/* File: arm/unop.S */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op r0". - * This could be an ARM instruction or a function call. - * - * for: neg-int, not-int, neg-float, int-to-float, float-to-int, - * int-to-byte, int-to-char, int-to-short - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r0, r3 @ r0<- vB - @ optional op; may set condition codes - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - sxtb r0, r0 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 8-9 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_char: /* 0x8e */ -/* File: arm/op_int_to_char.S */ -/* File: arm/unop.S */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op r0". - * This could be an ARM instruction or a function call. - * - * for: neg-int, not-int, neg-float, int-to-float, float-to-int, - * int-to-byte, int-to-char, int-to-short - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r0, r3 @ r0<- vB - @ optional op; may set condition codes - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - uxth r0, r0 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 8-9 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_short: /* 0x8f */ -/* File: arm/op_int_to_short.S */ -/* File: arm/unop.S */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op r0". - * This could be an ARM instruction or a function call. - * - * for: neg-int, not-int, neg-float, int-to-float, float-to-int, - * int-to-byte, int-to-char, int-to-short - */ - /* unop vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r0, r3 @ r0<- vB - @ optional op; may set condition codes - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - sxth r0, r0 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 8-9 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_add_int: /* 0x90 */ -/* File: arm/op_add_int.S */ -/* File: arm/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - GET_VREG r1, r3 @ r1<- vCC - GET_VREG r0, r2 @ r0<- vBB - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - @ optional op; may set condition codes - add r0, r0, r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 11-14 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_int: /* 0x91 */ -/* File: arm/op_sub_int.S */ -/* File: arm/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - GET_VREG r1, r3 @ r1<- vCC - GET_VREG r0, r2 @ r0<- vBB - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - @ optional op; may set condition codes - sub r0, r0, r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 11-14 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int: /* 0x92 */ -/* File: arm/op_mul_int.S */ -/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ -/* File: arm/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - GET_VREG r1, r3 @ r1<- vCC - GET_VREG r0, r2 @ r0<- vBB - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - @ optional op; may set condition codes - mul r0, r1, r0 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 11-14 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_div_int: /* 0x93 */ -/* File: arm/op_div_int.S */ - /* - * Specialized 32-bit binary operation - * - * Performs "r0 = r0 div r1". The selection between sdiv or the gcc helper - * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for - * ARMv7 CPUs that have hardware division support). - * - * div-int - * - */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - GET_VREG r1, r3 @ r1<- vCC - GET_VREG r0, r2 @ r0<- vBB - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST -#ifdef __ARM_ARCH_EXT_IDIV__ - sdiv r0, r0, r1 @ r0<- op -#else - bl __aeabi_idiv @ r0<- op, r0-r3 changed -#endif - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 11-14 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int: /* 0x94 */ -/* File: arm/op_rem_int.S */ - /* - * Specialized 32-bit binary operation - * - * Performs "r1 = r0 rem r1". The selection between sdiv block or the gcc helper - * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for - * ARMv7 CPUs that have hardware division support). - * - * NOTE: idivmod returns quotient in r0 and remainder in r1 - * - * rem-int - * - */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - GET_VREG r1, r3 @ r1<- vCC - GET_VREG r0, r2 @ r0<- vBB - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST -#ifdef __ARM_ARCH_EXT_IDIV__ - sdiv r2, r0, r1 - mls r1, r1, r2, r0 @ r1<- op, r0-r2 changed -#else - bl __aeabi_idivmod @ r1<- op, r0-r3 changed -#endif - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r1, r9 @ vAA<- r1 - GOTO_OPCODE ip @ jump to next instruction - /* 11-14 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_and_int: /* 0x95 */ -/* File: arm/op_and_int.S */ -/* File: arm/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - GET_VREG r1, r3 @ r1<- vCC - GET_VREG r0, r2 @ r0<- vBB - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - @ optional op; may set condition codes - and r0, r0, r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 11-14 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_or_int: /* 0x96 */ -/* File: arm/op_or_int.S */ -/* File: arm/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - GET_VREG r1, r3 @ r1<- vCC - GET_VREG r0, r2 @ r0<- vBB - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - @ optional op; may set condition codes - orr r0, r0, r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 11-14 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int: /* 0x97 */ -/* File: arm/op_xor_int.S */ -/* File: arm/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - GET_VREG r1, r3 @ r1<- vCC - GET_VREG r0, r2 @ r0<- vBB - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - @ optional op; may set condition codes - eor r0, r0, r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 11-14 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_shl_int: /* 0x98 */ -/* File: arm/op_shl_int.S */ -/* File: arm/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - GET_VREG r1, r3 @ r1<- vCC - GET_VREG r0, r2 @ r0<- vBB - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - and r1, r1, #31 @ optional op; may set condition codes - mov r0, r0, asl r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 11-14 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_shr_int: /* 0x99 */ -/* File: arm/op_shr_int.S */ -/* File: arm/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - GET_VREG r1, r3 @ r1<- vCC - GET_VREG r0, r2 @ r0<- vBB - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - and r1, r1, #31 @ optional op; may set condition codes - mov r0, r0, asr r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 11-14 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_int: /* 0x9a */ -/* File: arm/op_ushr_int.S */ -/* File: arm/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - GET_VREG r1, r3 @ r1<- vCC - GET_VREG r0, r2 @ r0<- vBB - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - and r1, r1, #31 @ optional op; may set condition codes - mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 11-14 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_add_long: /* 0x9b */ -/* File: arm/op_add_long.S */ -/* File: arm/binopWide.S */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = r0-r1 op r2-r3". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * for: add-long, sub-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, - * rem-double - * - * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. - */ - /* binop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov rINST, rINST, lsr #8 @ rINST<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[AA] - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] - ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 - ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 - .if 0 - orrs ip, r2, r3 @ second arg (r2-r3) is zero? - beq common_errDivideByZero - .endif - CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - adds r0, r0, r2 @ optional op; may set condition codes - adc r1, r1, r3 @ result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 14-17 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_long: /* 0x9c */ -/* File: arm/op_sub_long.S */ -/* File: arm/binopWide.S */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = r0-r1 op r2-r3". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * for: add-long, sub-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, - * rem-double - * - * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. - */ - /* binop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov rINST, rINST, lsr #8 @ rINST<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[AA] - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] - ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 - ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 - .if 0 - orrs ip, r2, r3 @ second arg (r2-r3) is zero? - beq common_errDivideByZero - .endif - CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - subs r0, r0, r2 @ optional op; may set condition codes - sbc r1, r1, r3 @ result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 14-17 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_long: /* 0x9d */ -/* File: arm/op_mul_long.S */ - /* - * Signed 64-bit integer multiply. - * - * Consider WXxYZ (r1r0 x r3r2) with a long multiply: - * WX - * x YZ - * -------- - * ZW ZX - * YW YX - * - * The low word of the result holds ZX, the high word holds - * (ZW+YX) + (the high overflow from ZX). YW doesn't matter because - * it doesn't fit in the low 64 bits. - * - * Unlike most ARM math operations, multiply instructions have - * restrictions on using the same register more than once (Rd and Rm - * cannot be the same). - */ - /* mul-long vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] - ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 - ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 - mul ip, r2, r1 @ ip<- ZxW - umull r1, lr, r2, r0 @ r1/lr <- ZxX - mla r2, r0, r3, ip @ r2<- YxX + (ZxW) - mov r0, rINST, lsr #8 @ r0<- AA - add r2, r2, lr @ r2<- lr + low(ZxW + (YxX)) - CLEAR_SHADOW_PAIR r0, lr, ip @ Zero out the shadow regs - VREG_INDEX_TO_ADDR r0, r0 @ r0<- &fp[AA] - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r0, {r1-r2 } @ vAA/vAA+1<- r1/r2 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_div_long: /* 0x9e */ -/* File: arm/op_div_long.S */ -/* File: arm/binopWide.S */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = r0-r1 op r2-r3". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * for: add-long, sub-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, - * rem-double - * - * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. - */ - /* binop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov rINST, rINST, lsr #8 @ rINST<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[AA] - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] - ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 - ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 - .if 1 - orrs ip, r2, r3 @ second arg (r2-r3) is zero? - beq common_errDivideByZero - .endif - CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - @ optional op; may set condition codes - bl __aeabi_ldivmod @ result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 14-17 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_long: /* 0x9f */ -/* File: arm/op_rem_long.S */ -/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ -/* File: arm/binopWide.S */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = r0-r1 op r2-r3". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * for: add-long, sub-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, - * rem-double - * - * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. - */ - /* binop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov rINST, rINST, lsr #8 @ rINST<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[AA] - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] - ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 - ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 - .if 1 - orrs ip, r2, r3 @ second arg (r2-r3) is zero? - beq common_errDivideByZero - .endif - CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - @ optional op; may set condition codes - bl __aeabi_ldivmod @ result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3 - GOTO_OPCODE ip @ jump to next instruction - /* 14-17 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_and_long: /* 0xa0 */ -/* File: arm/op_and_long.S */ -/* File: arm/binopWide.S */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = r0-r1 op r2-r3". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * for: add-long, sub-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, - * rem-double - * - * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. - */ - /* binop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov rINST, rINST, lsr #8 @ rINST<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[AA] - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] - ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 - ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 - .if 0 - orrs ip, r2, r3 @ second arg (r2-r3) is zero? - beq common_errDivideByZero - .endif - CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - and r0, r0, r2 @ optional op; may set condition codes - and r1, r1, r3 @ result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 14-17 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_or_long: /* 0xa1 */ -/* File: arm/op_or_long.S */ -/* File: arm/binopWide.S */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = r0-r1 op r2-r3". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * for: add-long, sub-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, - * rem-double - * - * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. - */ - /* binop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov rINST, rINST, lsr #8 @ rINST<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[AA] - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] - ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 - ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 - .if 0 - orrs ip, r2, r3 @ second arg (r2-r3) is zero? - beq common_errDivideByZero - .endif - CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - orr r0, r0, r2 @ optional op; may set condition codes - orr r1, r1, r3 @ result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 14-17 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_xor_long: /* 0xa2 */ -/* File: arm/op_xor_long.S */ -/* File: arm/binopWide.S */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = r0-r1 op r2-r3". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * for: add-long, sub-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, - * rem-double - * - * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. - */ - /* binop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov rINST, rINST, lsr #8 @ rINST<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[AA] - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] - ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 - ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 - .if 0 - orrs ip, r2, r3 @ second arg (r2-r3) is zero? - beq common_errDivideByZero - .endif - CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - eor r0, r0, r2 @ optional op; may set condition codes - eor r1, r1, r3 @ result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 14-17 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_shl_long: /* 0xa3 */ -/* File: arm/op_shl_long.S */ - /* - * Long integer shift. This is different from the generic 32/64-bit - * binary operations because vAA/vBB are 64-bit but vCC (the shift - * distance) is 32-bit. Also, Dalvik requires us to mask off the low - * 6 bits of the shift distance. - */ - /* shl-long vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - and r3, r0, #255 @ r3<- BB - mov r0, r0, lsr #8 @ r0<- CC - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[BB] - GET_VREG r2, r0 @ r2<- vCC - ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 - CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs - and r2, r2, #63 @ r2<- r2 & 0x3f - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] - mov r1, r1, asl r2 @ r1<- r1 << r2 - rsb r3, r2, #32 @ r3<- 32 - r2 - orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) - subs ip, r2, #32 @ ip<- r2 - 32 - movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - mov r0, r0, asl r2 @ r0<- r0 << r2 - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_shr_long: /* 0xa4 */ -/* File: arm/op_shr_long.S */ - /* - * Long integer shift. This is different from the generic 32/64-bit - * binary operations because vAA/vBB are 64-bit but vCC (the shift - * distance) is 32-bit. Also, Dalvik requires us to mask off the low - * 6 bits of the shift distance. - */ - /* shr-long vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - and r3, r0, #255 @ r3<- BB - mov r0, r0, lsr #8 @ r0<- CC - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[BB] - GET_VREG r2, r0 @ r2<- vCC - ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 - CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs - and r2, r2, #63 @ r0<- r0 & 0x3f - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] - mov r0, r0, lsr r2 @ r0<- r2 >> r2 - rsb r3, r2, #32 @ r3<- 32 - r2 - orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) - subs ip, r2, #32 @ ip<- r2 - 32 - movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - mov r1, r1, asr r2 @ r1<- r1 >> r2 - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_long: /* 0xa5 */ -/* File: arm/op_ushr_long.S */ - /* - * Long integer shift. This is different from the generic 32/64-bit - * binary operations because vAA/vBB are 64-bit but vCC (the shift - * distance) is 32-bit. Also, Dalvik requires us to mask off the low - * 6 bits of the shift distance. - */ - /* ushr-long vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - and r3, r0, #255 @ r3<- BB - mov r0, r0, lsr #8 @ r0<- CC - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[BB] - GET_VREG r2, r0 @ r2<- vCC - ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 - CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs - and r2, r2, #63 @ r0<- r0 & 0x3f - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] - mov r0, r0, lsr r2 @ r0<- r2 >> r2 - rsb r3, r2, #32 @ r3<- 32 - r2 - orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) - subs ip, r2, #32 @ ip<- r2 - 32 - movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - mov r1, r1, lsr r2 @ r1<- r1 >>> r2 - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_add_float: /* 0xa6 */ -/* File: arm/op_add_float.S */ -/* File: arm/fbinop.S */ - /* - * Generic 32-bit floating-point operation. Provide an "instr" line that - * specifies an instruction that performs "s2 = s0 op s1". Because we - * use the "softfp" ABI, this must be an instruction, not a function call. - * - * For: add-float, sub-float, mul-float, div-float - */ - /* floatop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB - flds s1, [r3] @ s1<- vCC - flds s0, [r2] @ s0<- vBB - - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - fadds s2, s0, s1 @ s2<- op - GET_INST_OPCODE ip @ extract opcode from rINST - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA - fsts s2, [r9] @ vAA<- s2 - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_float: /* 0xa7 */ -/* File: arm/op_sub_float.S */ -/* File: arm/fbinop.S */ - /* - * Generic 32-bit floating-point operation. Provide an "instr" line that - * specifies an instruction that performs "s2 = s0 op s1". Because we - * use the "softfp" ABI, this must be an instruction, not a function call. - * - * For: add-float, sub-float, mul-float, div-float - */ - /* floatop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB - flds s1, [r3] @ s1<- vCC - flds s0, [r2] @ s0<- vBB - - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - fsubs s2, s0, s1 @ s2<- op - GET_INST_OPCODE ip @ extract opcode from rINST - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA - fsts s2, [r9] @ vAA<- s2 - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_float: /* 0xa8 */ -/* File: arm/op_mul_float.S */ -/* File: arm/fbinop.S */ - /* - * Generic 32-bit floating-point operation. Provide an "instr" line that - * specifies an instruction that performs "s2 = s0 op s1". Because we - * use the "softfp" ABI, this must be an instruction, not a function call. - * - * For: add-float, sub-float, mul-float, div-float - */ - /* floatop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB - flds s1, [r3] @ s1<- vCC - flds s0, [r2] @ s0<- vBB - - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - fmuls s2, s0, s1 @ s2<- op - GET_INST_OPCODE ip @ extract opcode from rINST - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA - fsts s2, [r9] @ vAA<- s2 - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_div_float: /* 0xa9 */ -/* File: arm/op_div_float.S */ -/* File: arm/fbinop.S */ - /* - * Generic 32-bit floating-point operation. Provide an "instr" line that - * specifies an instruction that performs "s2 = s0 op s1". Because we - * use the "softfp" ABI, this must be an instruction, not a function call. - * - * For: add-float, sub-float, mul-float, div-float - */ - /* floatop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB - flds s1, [r3] @ s1<- vCC - flds s0, [r2] @ s0<- vBB - - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - fdivs s2, s0, s1 @ s2<- op - GET_INST_OPCODE ip @ extract opcode from rINST - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA - fsts s2, [r9] @ vAA<- s2 - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_float: /* 0xaa */ -/* File: arm/op_rem_float.S */ -/* EABI doesn't define a float remainder function, but libm does */ -/* File: arm/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - GET_VREG r1, r3 @ r1<- vCC - GET_VREG r0, r2 @ r0<- vBB - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - @ optional op; may set condition codes - bl fmodf @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 11-14 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_add_double: /* 0xab */ -/* File: arm/op_add_double.S */ -/* File: arm/fbinopWide.S */ - /* - * Generic 64-bit double-precision floating point binary operation. - * Provide an "instr" line that specifies an instruction that performs - * "d2 = d0 op d1". - * - * for: add-double, sub-double, mul-double, div-double - */ - /* doubleop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB - fldd d1, [r3] @ d1<- vCC - fldd d0, [r2] @ d0<- vBB - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - faddd d2, d0, d1 @ s2<- op - CLEAR_SHADOW_PAIR r9, ip, lr @ Zero shadow regs - GET_INST_OPCODE ip @ extract opcode from rINST - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA - fstd d2, [r9] @ vAA<- d2 - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_double: /* 0xac */ -/* File: arm/op_sub_double.S */ -/* File: arm/fbinopWide.S */ - /* - * Generic 64-bit double-precision floating point binary operation. - * Provide an "instr" line that specifies an instruction that performs - * "d2 = d0 op d1". - * - * for: add-double, sub-double, mul-double, div-double - */ - /* doubleop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB - fldd d1, [r3] @ d1<- vCC - fldd d0, [r2] @ d0<- vBB - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - fsubd d2, d0, d1 @ s2<- op - CLEAR_SHADOW_PAIR r9, ip, lr @ Zero shadow regs - GET_INST_OPCODE ip @ extract opcode from rINST - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA - fstd d2, [r9] @ vAA<- d2 - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_double: /* 0xad */ -/* File: arm/op_mul_double.S */ -/* File: arm/fbinopWide.S */ - /* - * Generic 64-bit double-precision floating point binary operation. - * Provide an "instr" line that specifies an instruction that performs - * "d2 = d0 op d1". - * - * for: add-double, sub-double, mul-double, div-double - */ - /* doubleop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB - fldd d1, [r3] @ d1<- vCC - fldd d0, [r2] @ d0<- vBB - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - fmuld d2, d0, d1 @ s2<- op - CLEAR_SHADOW_PAIR r9, ip, lr @ Zero shadow regs - GET_INST_OPCODE ip @ extract opcode from rINST - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA - fstd d2, [r9] @ vAA<- d2 - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_div_double: /* 0xae */ -/* File: arm/op_div_double.S */ -/* File: arm/fbinopWide.S */ - /* - * Generic 64-bit double-precision floating point binary operation. - * Provide an "instr" line that specifies an instruction that performs - * "d2 = d0 op d1". - * - * for: add-double, sub-double, mul-double, div-double - */ - /* doubleop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA - mov r3, r0, lsr #8 @ r3<- CC - and r2, r0, #255 @ r2<- BB - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB - fldd d1, [r3] @ d1<- vCC - fldd d0, [r2] @ d0<- vBB - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - fdivd d2, d0, d1 @ s2<- op - CLEAR_SHADOW_PAIR r9, ip, lr @ Zero shadow regs - GET_INST_OPCODE ip @ extract opcode from rINST - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA - fstd d2, [r9] @ vAA<- d2 - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_double: /* 0xaf */ -/* File: arm/op_rem_double.S */ -/* EABI doesn't define a double remainder function, but libm does */ -/* File: arm/binopWide.S */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = r0-r1 op r2-r3". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * for: add-long, sub-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, - * rem-double - * - * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. - */ - /* binop vAA, vBB, vCC */ - FETCH r0, 1 @ r0<- CCBB - mov rINST, rINST, lsr #8 @ rINST<- AA - and r2, r0, #255 @ r2<- BB - mov r3, r0, lsr #8 @ r3<- CC - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[AA] - VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] - ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 - ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 - .if 0 - orrs ip, r2, r3 @ second arg (r2-r3) is zero? - beq common_errDivideByZero - .endif - CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - @ optional op; may set condition codes - bl fmod @ result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 14-17 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_add_int_2addr: /* 0xb0 */ -/* File: arm/op_add_int_2addr.S */ -/* File: arm/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r1, r3 @ r1<- vB - GET_VREG r0, r9 @ r0<- vA - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - - @ optional op; may set condition codes - add r0, r0, r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_int_2addr: /* 0xb1 */ -/* File: arm/op_sub_int_2addr.S */ -/* File: arm/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r1, r3 @ r1<- vB - GET_VREG r0, r9 @ r0<- vA - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - - @ optional op; may set condition codes - sub r0, r0, r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int_2addr: /* 0xb2 */ -/* File: arm/op_mul_int_2addr.S */ -/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ -/* File: arm/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r1, r3 @ r1<- vB - GET_VREG r0, r9 @ r0<- vA - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - - @ optional op; may set condition codes - mul r0, r1, r0 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_div_int_2addr: /* 0xb3 */ -/* File: arm/op_div_int_2addr.S */ - /* - * Specialized 32-bit binary operation - * - * Performs "r0 = r0 div r1". The selection between sdiv or the gcc helper - * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for - * ARMv7 CPUs that have hardware division support). - * - * div-int/2addr - * - */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r1, r3 @ r1<- vB - GET_VREG r0, r9 @ r0<- vA - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - -#ifdef __ARM_ARCH_EXT_IDIV__ - sdiv r0, r0, r1 @ r0<- op -#else - bl __aeabi_idiv @ r0<- op, r0-r3 changed -#endif - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int_2addr: /* 0xb4 */ -/* File: arm/op_rem_int_2addr.S */ - /* - * Specialized 32-bit binary operation - * - * Performs "r1 = r0 rem r1". The selection between sdiv block or the gcc helper - * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for - * ARMv7 CPUs that have hardware division support). - * - * NOTE: idivmod returns quotient in r0 and remainder in r1 - * - * rem-int/2addr - * - */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r1, r3 @ r1<- vB - GET_VREG r0, r9 @ r0<- vA - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - -#ifdef __ARM_ARCH_EXT_IDIV__ - sdiv r2, r0, r1 - mls r1, r1, r2, r0 @ r1<- op -#else - bl __aeabi_idivmod @ r1<- op, r0-r3 changed -#endif - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r1, r9 @ vAA<- r1 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_and_int_2addr: /* 0xb5 */ -/* File: arm/op_and_int_2addr.S */ -/* File: arm/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r1, r3 @ r1<- vB - GET_VREG r0, r9 @ r0<- vA - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - - @ optional op; may set condition codes - and r0, r0, r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_or_int_2addr: /* 0xb6 */ -/* File: arm/op_or_int_2addr.S */ -/* File: arm/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r1, r3 @ r1<- vB - GET_VREG r0, r9 @ r0<- vA - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - - @ optional op; may set condition codes - orr r0, r0, r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int_2addr: /* 0xb7 */ -/* File: arm/op_xor_int_2addr.S */ -/* File: arm/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r1, r3 @ r1<- vB - GET_VREG r0, r9 @ r0<- vA - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - - @ optional op; may set condition codes - eor r0, r0, r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_shl_int_2addr: /* 0xb8 */ -/* File: arm/op_shl_int_2addr.S */ -/* File: arm/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r1, r3 @ r1<- vB - GET_VREG r0, r9 @ r0<- vA - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - - and r1, r1, #31 @ optional op; may set condition codes - mov r0, r0, asl r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_shr_int_2addr: /* 0xb9 */ -/* File: arm/op_shr_int_2addr.S */ -/* File: arm/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r1, r3 @ r1<- vB - GET_VREG r0, r9 @ r0<- vA - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - - and r1, r1, #31 @ optional op; may set condition codes - mov r0, r0, asr r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_int_2addr: /* 0xba */ -/* File: arm/op_ushr_int_2addr.S */ -/* File: arm/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r1, r3 @ r1<- vB - GET_VREG r0, r9 @ r0<- vA - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - - and r1, r1, #31 @ optional op; may set condition codes - mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_add_long_2addr: /* 0xbb */ -/* File: arm/op_add_long_2addr.S */ -/* File: arm/binopWide2addr.S */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0-r1 op r2-r3". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, - * rem-double/2addr - */ - /* binop/2addr vA, vB */ - mov r1, rINST, lsr #12 @ r1<- B - ubfx rINST, rINST, #8, #4 @ rINST<- A - VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] - ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 - ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 - .if 0 - orrs ip, r2, r3 @ second arg (r2-r3) is zero? - beq common_errDivideByZero - .endif - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - adds r0, r0, r2 @ optional op; may set condition codes - adc r1, r1, r3 @ result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 12-15 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_long_2addr: /* 0xbc */ -/* File: arm/op_sub_long_2addr.S */ -/* File: arm/binopWide2addr.S */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0-r1 op r2-r3". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, - * rem-double/2addr - */ - /* binop/2addr vA, vB */ - mov r1, rINST, lsr #12 @ r1<- B - ubfx rINST, rINST, #8, #4 @ rINST<- A - VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] - ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 - ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 - .if 0 - orrs ip, r2, r3 @ second arg (r2-r3) is zero? - beq common_errDivideByZero - .endif - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - subs r0, r0, r2 @ optional op; may set condition codes - sbc r1, r1, r3 @ result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 12-15 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_long_2addr: /* 0xbd */ -/* File: arm/op_mul_long_2addr.S */ - /* - * Signed 64-bit integer multiply, "/2addr" version. - * - * See op_mul_long for an explanation. - * - * We get a little tight on registers, so to avoid looking up &fp[A] - * again we stuff it into rINST. - */ - /* mul-long/2addr vA, vB */ - mov r1, rINST, lsr #12 @ r1<- B - ubfx r9, rINST, #8, #4 @ r9<- A - VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] - VREG_INDEX_TO_ADDR rINST, r9 @ rINST<- &fp[A] - ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 - ldmia rINST, {r0-r1} @ r0/r1<- vAA/vAA+1 - mul ip, r2, r1 @ ip<- ZxW - umull r1, lr, r2, r0 @ r1/lr <- ZxX - mla r2, r0, r3, ip @ r2<- YxX + (ZxW) - mov r0, rINST @ r0<- &fp[A] (free up rINST) - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - add r2, r2, lr @ r2<- r2 + low(ZxW + (YxX)) - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r0, {r1-r2} @ vAA/vAA+1<- r1/r2 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_div_long_2addr: /* 0xbe */ -/* File: arm/op_div_long_2addr.S */ -/* File: arm/binopWide2addr.S */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0-r1 op r2-r3". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, - * rem-double/2addr - */ - /* binop/2addr vA, vB */ - mov r1, rINST, lsr #12 @ r1<- B - ubfx rINST, rINST, #8, #4 @ rINST<- A - VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] - ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 - ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 - .if 1 - orrs ip, r2, r3 @ second arg (r2-r3) is zero? - beq common_errDivideByZero - .endif - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - @ optional op; may set condition codes - bl __aeabi_ldivmod @ result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 12-15 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_long_2addr: /* 0xbf */ -/* File: arm/op_rem_long_2addr.S */ -/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ -/* File: arm/binopWide2addr.S */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0-r1 op r2-r3". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, - * rem-double/2addr - */ - /* binop/2addr vA, vB */ - mov r1, rINST, lsr #12 @ r1<- B - ubfx rINST, rINST, #8, #4 @ rINST<- A - VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] - ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 - ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 - .if 1 - orrs ip, r2, r3 @ second arg (r2-r3) is zero? - beq common_errDivideByZero - .endif - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - @ optional op; may set condition codes - bl __aeabi_ldivmod @ result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3 - GOTO_OPCODE ip @ jump to next instruction - /* 12-15 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_and_long_2addr: /* 0xc0 */ -/* File: arm/op_and_long_2addr.S */ -/* File: arm/binopWide2addr.S */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0-r1 op r2-r3". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, - * rem-double/2addr - */ - /* binop/2addr vA, vB */ - mov r1, rINST, lsr #12 @ r1<- B - ubfx rINST, rINST, #8, #4 @ rINST<- A - VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] - ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 - ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 - .if 0 - orrs ip, r2, r3 @ second arg (r2-r3) is zero? - beq common_errDivideByZero - .endif - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - and r0, r0, r2 @ optional op; may set condition codes - and r1, r1, r3 @ result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 12-15 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_or_long_2addr: /* 0xc1 */ -/* File: arm/op_or_long_2addr.S */ -/* File: arm/binopWide2addr.S */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0-r1 op r2-r3". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, - * rem-double/2addr - */ - /* binop/2addr vA, vB */ - mov r1, rINST, lsr #12 @ r1<- B - ubfx rINST, rINST, #8, #4 @ rINST<- A - VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] - ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 - ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 - .if 0 - orrs ip, r2, r3 @ second arg (r2-r3) is zero? - beq common_errDivideByZero - .endif - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - orr r0, r0, r2 @ optional op; may set condition codes - orr r1, r1, r3 @ result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 12-15 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_xor_long_2addr: /* 0xc2 */ -/* File: arm/op_xor_long_2addr.S */ -/* File: arm/binopWide2addr.S */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0-r1 op r2-r3". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, - * rem-double/2addr - */ - /* binop/2addr vA, vB */ - mov r1, rINST, lsr #12 @ r1<- B - ubfx rINST, rINST, #8, #4 @ rINST<- A - VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] - ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 - ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 - .if 0 - orrs ip, r2, r3 @ second arg (r2-r3) is zero? - beq common_errDivideByZero - .endif - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - eor r0, r0, r2 @ optional op; may set condition codes - eor r1, r1, r3 @ result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 12-15 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_shl_long_2addr: /* 0xc3 */ -/* File: arm/op_shl_long_2addr.S */ - /* - * Long integer shift, 2addr version. vA is 64-bit value/result, vB is - * 32-bit shift distance. - */ - /* shl-long/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r2, r3 @ r2<- vB - CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[A] - and r2, r2, #63 @ r2<- r2 & 0x3f - ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 - mov r1, r1, asl r2 @ r1<- r1 << r2 - rsb r3, r2, #32 @ r3<- 32 - r2 - orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) - subs ip, r2, #32 @ ip<- r2 - 32 - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) - mov r0, r0, asl r2 @ r0<- r0 << r2 - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_shr_long_2addr: /* 0xc4 */ -/* File: arm/op_shr_long_2addr.S */ - /* - * Long integer shift, 2addr version. vA is 64-bit value/result, vB is - * 32-bit shift distance. - */ - /* shr-long/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r2, r3 @ r2<- vB - CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[A] - and r2, r2, #63 @ r2<- r2 & 0x3f - ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 - mov r0, r0, lsr r2 @ r0<- r2 >> r2 - rsb r3, r2, #32 @ r3<- 32 - r2 - orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) - subs ip, r2, #32 @ ip<- r2 - 32 - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) - mov r1, r1, asr r2 @ r1<- r1 >> r2 - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_long_2addr: /* 0xc5 */ -/* File: arm/op_ushr_long_2addr.S */ - /* - * Long integer shift, 2addr version. vA is 64-bit value/result, vB is - * 32-bit shift distance. - */ - /* ushr-long/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r2, r3 @ r2<- vB - CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[A] - and r2, r2, #63 @ r2<- r2 & 0x3f - ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 - mov r0, r0, lsr r2 @ r0<- r2 >> r2 - rsb r3, r2, #32 @ r3<- 32 - r2 - orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) - subs ip, r2, #32 @ ip<- r2 - 32 - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) - mov r1, r1, lsr r2 @ r1<- r1 >>> r2 - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_add_float_2addr: /* 0xc6 */ -/* File: arm/op_add_float_2addr.S */ -/* File: arm/fbinop2addr.S */ - /* - * Generic 32-bit floating point "/2addr" binary operation. Provide - * an "instr" line that specifies an instruction that performs - * "s2 = s0 op s1". - * - * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr - */ - /* binop/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA - flds s1, [r3] @ s1<- vB - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - flds s0, [r9] @ s0<- vA - fadds s2, s0, s1 @ s2<- op - GET_INST_OPCODE ip @ extract opcode from rINST - fsts s2, [r9] @ vAA<- s2 - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_float_2addr: /* 0xc7 */ -/* File: arm/op_sub_float_2addr.S */ -/* File: arm/fbinop2addr.S */ - /* - * Generic 32-bit floating point "/2addr" binary operation. Provide - * an "instr" line that specifies an instruction that performs - * "s2 = s0 op s1". - * - * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr - */ - /* binop/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA - flds s1, [r3] @ s1<- vB - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - flds s0, [r9] @ s0<- vA - fsubs s2, s0, s1 @ s2<- op - GET_INST_OPCODE ip @ extract opcode from rINST - fsts s2, [r9] @ vAA<- s2 - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_float_2addr: /* 0xc8 */ -/* File: arm/op_mul_float_2addr.S */ -/* File: arm/fbinop2addr.S */ - /* - * Generic 32-bit floating point "/2addr" binary operation. Provide - * an "instr" line that specifies an instruction that performs - * "s2 = s0 op s1". - * - * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr - */ - /* binop/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA - flds s1, [r3] @ s1<- vB - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - flds s0, [r9] @ s0<- vA - fmuls s2, s0, s1 @ s2<- op - GET_INST_OPCODE ip @ extract opcode from rINST - fsts s2, [r9] @ vAA<- s2 - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_div_float_2addr: /* 0xc9 */ -/* File: arm/op_div_float_2addr.S */ -/* File: arm/fbinop2addr.S */ - /* - * Generic 32-bit floating point "/2addr" binary operation. Provide - * an "instr" line that specifies an instruction that performs - * "s2 = s0 op s1". - * - * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr - */ - /* binop/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA - flds s1, [r3] @ s1<- vB - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - flds s0, [r9] @ s0<- vA - fdivs s2, s0, s1 @ s2<- op - GET_INST_OPCODE ip @ extract opcode from rINST - fsts s2, [r9] @ vAA<- s2 - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_float_2addr: /* 0xca */ -/* File: arm/op_rem_float_2addr.S */ -/* EABI doesn't define a float remainder function, but libm does */ -/* File: arm/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r1, r3 @ r1<- vB - GET_VREG r0, r9 @ r0<- vA - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - - @ optional op; may set condition codes - bl fmodf @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_add_double_2addr: /* 0xcb */ -/* File: arm/op_add_double_2addr.S */ -/* File: arm/fbinopWide2addr.S */ - /* - * Generic 64-bit floating point "/2addr" binary operation. Provide - * an "instr" line that specifies an instruction that performs - * "d2 = d0 op d1". - * - * For: add-double/2addr, sub-double/2addr, mul-double/2addr, - * div-double/2addr - */ - /* binop/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB - CLEAR_SHADOW_PAIR r9, ip, r0 @ Zero out shadow regs - fldd d1, [r3] @ d1<- vB - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - fldd d0, [r9] @ d0<- vA - faddd d2, d0, d1 @ d2<- op - GET_INST_OPCODE ip @ extract opcode from rINST - fstd d2, [r9] @ vAA<- d2 - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_double_2addr: /* 0xcc */ -/* File: arm/op_sub_double_2addr.S */ -/* File: arm/fbinopWide2addr.S */ - /* - * Generic 64-bit floating point "/2addr" binary operation. Provide - * an "instr" line that specifies an instruction that performs - * "d2 = d0 op d1". - * - * For: add-double/2addr, sub-double/2addr, mul-double/2addr, - * div-double/2addr - */ - /* binop/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB - CLEAR_SHADOW_PAIR r9, ip, r0 @ Zero out shadow regs - fldd d1, [r3] @ d1<- vB - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - fldd d0, [r9] @ d0<- vA - fsubd d2, d0, d1 @ d2<- op - GET_INST_OPCODE ip @ extract opcode from rINST - fstd d2, [r9] @ vAA<- d2 - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_double_2addr: /* 0xcd */ -/* File: arm/op_mul_double_2addr.S */ -/* File: arm/fbinopWide2addr.S */ - /* - * Generic 64-bit floating point "/2addr" binary operation. Provide - * an "instr" line that specifies an instruction that performs - * "d2 = d0 op d1". - * - * For: add-double/2addr, sub-double/2addr, mul-double/2addr, - * div-double/2addr - */ - /* binop/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB - CLEAR_SHADOW_PAIR r9, ip, r0 @ Zero out shadow regs - fldd d1, [r3] @ d1<- vB - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - fldd d0, [r9] @ d0<- vA - fmuld d2, d0, d1 @ d2<- op - GET_INST_OPCODE ip @ extract opcode from rINST - fstd d2, [r9] @ vAA<- d2 - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_div_double_2addr: /* 0xce */ -/* File: arm/op_div_double_2addr.S */ -/* File: arm/fbinopWide2addr.S */ - /* - * Generic 64-bit floating point "/2addr" binary operation. Provide - * an "instr" line that specifies an instruction that performs - * "d2 = d0 op d1". - * - * For: add-double/2addr, sub-double/2addr, mul-double/2addr, - * div-double/2addr - */ - /* binop/2addr vA, vB */ - mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A - VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB - CLEAR_SHADOW_PAIR r9, ip, r0 @ Zero out shadow regs - fldd d1, [r3] @ d1<- vB - VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - fldd d0, [r9] @ d0<- vA - fdivd d2, d0, d1 @ d2<- op - GET_INST_OPCODE ip @ extract opcode from rINST - fstd d2, [r9] @ vAA<- d2 - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_double_2addr: /* 0xcf */ -/* File: arm/op_rem_double_2addr.S */ -/* EABI doesn't define a double remainder function, but libm does */ -/* File: arm/binopWide2addr.S */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0-r1 op r2-r3". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, - * rem-double/2addr - */ - /* binop/2addr vA, vB */ - mov r1, rINST, lsr #12 @ r1<- B - ubfx rINST, rINST, #8, #4 @ rINST<- A - VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] - VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] - ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 - ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 - .if 0 - orrs ip, r2, r3 @ second arg (r2-r3) is zero? - beq common_errDivideByZero - .endif - CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs - FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - @ optional op; may set condition codes - bl fmod @ result<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - /* 12-15 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_add_int_lit16: /* 0xd0 */ -/* File: arm/op_add_int_lit16.S */ -/* File: arm/binopLit16.S */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) - mov r2, rINST, lsr #12 @ r2<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r0, r2 @ r0<- vB - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - - add r0, r0, r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_rsub_int: /* 0xd1 */ -/* File: arm/op_rsub_int.S */ -/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ -/* File: arm/binopLit16.S */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) - mov r2, rINST, lsr #12 @ r2<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r0, r2 @ r0<- vB - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - - rsb r0, r0, r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int_lit16: /* 0xd2 */ -/* File: arm/op_mul_int_lit16.S */ -/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ -/* File: arm/binopLit16.S */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) - mov r2, rINST, lsr #12 @ r2<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r0, r2 @ r0<- vB - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - - mul r0, r1, r0 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_div_int_lit16: /* 0xd3 */ -/* File: arm/op_div_int_lit16.S */ - /* - * Specialized 32-bit binary operation - * - * Performs "r0 = r0 div r1". The selection between sdiv or the gcc helper - * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for - * ARMv7 CPUs that have hardware division support). - * - * div-int/lit16 - * - */ - FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) - mov r2, rINST, lsr #12 @ r2<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r0, r2 @ r0<- vB - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - -#ifdef __ARM_ARCH_EXT_IDIV__ - sdiv r0, r0, r1 @ r0<- op -#else - bl __aeabi_idiv @ r0<- op, r0-r3 changed -#endif - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int_lit16: /* 0xd4 */ -/* File: arm/op_rem_int_lit16.S */ - /* - * Specialized 32-bit binary operation - * - * Performs "r1 = r0 rem r1". The selection between sdiv block or the gcc helper - * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for - * ARMv7 CPUs that have hardware division support). - * - * NOTE: idivmod returns quotient in r0 and remainder in r1 - * - * rem-int/lit16 - * - */ - FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) - mov r2, rINST, lsr #12 @ r2<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r0, r2 @ r0<- vB - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - -#ifdef __ARM_ARCH_EXT_IDIV__ - sdiv r2, r0, r1 - mls r1, r1, r2, r0 @ r1<- op -#else - bl __aeabi_idivmod @ r1<- op, r0-r3 changed -#endif - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r1, r9 @ vAA<- r1 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_and_int_lit16: /* 0xd5 */ -/* File: arm/op_and_int_lit16.S */ -/* File: arm/binopLit16.S */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) - mov r2, rINST, lsr #12 @ r2<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r0, r2 @ r0<- vB - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - - and r0, r0, r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_or_int_lit16: /* 0xd6 */ -/* File: arm/op_or_int_lit16.S */ -/* File: arm/binopLit16.S */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) - mov r2, rINST, lsr #12 @ r2<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r0, r2 @ r0<- vB - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - - orr r0, r0, r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int_lit16: /* 0xd7 */ -/* File: arm/op_xor_int_lit16.S */ -/* File: arm/binopLit16.S */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) - mov r2, rINST, lsr #12 @ r2<- B - ubfx r9, rINST, #8, #4 @ r9<- A - GET_VREG r0, r2 @ r0<- vB - .if 0 - cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - - eor r0, r0, r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_add_int_lit8: /* 0xd8 */ -/* File: arm/op_add_int_lit8.S */ -/* File: arm/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from r3 to r1 is not the default "asr r1, r3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r3, #255 @ r2<- BB - GET_VREG r0, r2 @ r0<- vBB - @ optional; typically r1<- ssssssCC (sign extended) - .if 0 - @cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - - add r0, r0, r3, asr #8 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-12 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_rsub_int_lit8: /* 0xd9 */ -/* File: arm/op_rsub_int_lit8.S */ -/* File: arm/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from r3 to r1 is not the default "asr r1, r3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r3, #255 @ r2<- BB - GET_VREG r0, r2 @ r0<- vBB - @ optional; typically r1<- ssssssCC (sign extended) - .if 0 - @cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - - rsb r0, r0, r3, asr #8 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-12 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int_lit8: /* 0xda */ -/* File: arm/op_mul_int_lit8.S */ -/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ -/* File: arm/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from r3 to r1 is not the default "asr r1, r3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r3, #255 @ r2<- BB - GET_VREG r0, r2 @ r0<- vBB - asr r1, r3, #8 @ optional; typically r1<- ssssssCC (sign extended) - .if 0 - @cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - - mul r0, r1, r0 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-12 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_div_int_lit8: /* 0xdb */ -/* File: arm/op_div_int_lit8.S */ - /* - * Specialized 32-bit binary operation - * - * Performs "r0 = r0 div r1". The selection between sdiv or the gcc helper - * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for - * ARMv7 CPUs that have hardware division support). - * - * div-int/lit8 - * - */ - FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r3, #255 @ r2<- BB - GET_VREG r0, r2 @ r0<- vBB - movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) - @cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - -#ifdef __ARM_ARCH_EXT_IDIV__ - sdiv r0, r0, r1 @ r0<- op -#else - bl __aeabi_idiv @ r0<- op, r0-r3 changed -#endif - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-12 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int_lit8: /* 0xdc */ -/* File: arm/op_rem_int_lit8.S */ - /* - * Specialized 32-bit binary operation - * - * Performs "r1 = r0 rem r1". The selection between sdiv block or the gcc helper - * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for - * ARMv7 CPUs that have hardware division support). - * - * NOTE: idivmod returns quotient in r0 and remainder in r1 - * - * rem-int/lit8 - * - */ - FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r3, #255 @ r2<- BB - GET_VREG r0, r2 @ r0<- vBB - movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) - @cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - -#ifdef __ARM_ARCH_EXT_IDIV__ - sdiv r2, r0, r1 - mls r1, r1, r2, r0 @ r1<- op -#else - bl __aeabi_idivmod @ r1<- op, r0-r3 changed -#endif - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r1, r9 @ vAA<- r1 - GOTO_OPCODE ip @ jump to next instruction - /* 10-12 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_and_int_lit8: /* 0xdd */ -/* File: arm/op_and_int_lit8.S */ -/* File: arm/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from r3 to r1 is not the default "asr r1, r3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r3, #255 @ r2<- BB - GET_VREG r0, r2 @ r0<- vBB - @ optional; typically r1<- ssssssCC (sign extended) - .if 0 - @cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - - and r0, r0, r3, asr #8 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-12 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_or_int_lit8: /* 0xde */ -/* File: arm/op_or_int_lit8.S */ -/* File: arm/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from r3 to r1 is not the default "asr r1, r3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r3, #255 @ r2<- BB - GET_VREG r0, r2 @ r0<- vBB - @ optional; typically r1<- ssssssCC (sign extended) - .if 0 - @cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - - orr r0, r0, r3, asr #8 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-12 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int_lit8: /* 0xdf */ -/* File: arm/op_xor_int_lit8.S */ -/* File: arm/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from r3 to r1 is not the default "asr r1, r3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r3, #255 @ r2<- BB - GET_VREG r0, r2 @ r0<- vBB - @ optional; typically r1<- ssssssCC (sign extended) - .if 0 - @cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - - eor r0, r0, r3, asr #8 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-12 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_shl_int_lit8: /* 0xe0 */ -/* File: arm/op_shl_int_lit8.S */ -/* File: arm/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from r3 to r1 is not the default "asr r1, r3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r3, #255 @ r2<- BB - GET_VREG r0, r2 @ r0<- vBB - ubfx r1, r3, #8, #5 @ optional; typically r1<- ssssssCC (sign extended) - .if 0 - @cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - - mov r0, r0, asl r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-12 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_shr_int_lit8: /* 0xe1 */ -/* File: arm/op_shr_int_lit8.S */ -/* File: arm/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from r3 to r1 is not the default "asr r1, r3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r3, #255 @ r2<- BB - GET_VREG r0, r2 @ r0<- vBB - ubfx r1, r3, #8, #5 @ optional; typically r1<- ssssssCC (sign extended) - .if 0 - @cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - - mov r0, r0, asr r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-12 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_int_lit8: /* 0xe2 */ -/* File: arm/op_ushr_int_lit8.S */ -/* File: arm/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from r3 to r1 is not the default "asr r1, r3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (r1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) - mov r9, rINST, lsr #8 @ r9<- AA - and r2, r3, #255 @ r2<- BB - GET_VREG r0, r2 @ r0<- vBB - ubfx r1, r3, #8, #5 @ optional; typically r1<- ssssssCC (sign extended) - .if 0 - @cmp r1, #0 @ is second operand zero? - beq common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - - mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed - GET_INST_OPCODE ip @ extract opcode from rINST - SET_VREG r0, r9 @ vAA<- r0 - GOTO_OPCODE ip @ jump to next instruction - /* 10-12 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_quick: /* 0xe3 */ -/* File: arm/op_iget_quick.S */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset@CCCC */ - mov r2, rINST, lsr #12 @ r2<- B - FETCH r1, 1 @ r1<- field byte offset - GET_VREG r3, r2 @ r3<- object we're operating on - ubfx r2, rINST, #8, #4 @ r2<- A - cmp r3, #0 @ check object for null - beq common_errNullObject @ object was null - ldr r0, [r3, r1] @ r0<- obj.field - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - SET_VREG r0, r2 @ fp[A]<- r0 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iget_wide_quick: /* 0xe4 */ -/* File: arm/op_iget_wide_quick.S */ - /* iget-wide-quick vA, vB, offset@CCCC */ - mov r2, rINST, lsr #12 @ r2<- B - FETCH ip, 1 @ ip<- field byte offset - GET_VREG r3, r2 @ r3<- object we're operating on - ubfx r2, rINST, #8, #4 @ r2<- A - cmp r3, #0 @ check object for null - beq common_errNullObject @ object was null - ldrd r0, [r3, ip] @ r0<- obj.field (64 bits, aligned) - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - VREG_INDEX_TO_ADDR r3, r2 @ r3<- &fp[A] - CLEAR_SHADOW_PAIR r2, ip, lr @ Zero out the shadow regs - GET_INST_OPCODE ip @ extract opcode from rINST - stmia r3, {r0-r1} @ fp[A]<- r0/r1 - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iget_object_quick: /* 0xe5 */ -/* File: arm/op_iget_object_quick.S */ - /* For: iget-object-quick */ - /* op vA, vB, offset@CCCC */ - mov r2, rINST, lsr #12 @ r2<- B - FETCH r1, 1 @ r1<- field byte offset - EXPORT_PC - GET_VREG r0, r2 @ r0<- object we're operating on - bl artIGetObjectFromMterp @ (obj, offset) - ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] - ubfx r2, rINST, #8, #4 @ r2<- A - PREFETCH_INST 2 - cmp r3, #0 - bne MterpPossibleException @ bail out - SET_VREG_OBJECT r0, r2 @ fp[A]<- r0 - ADVANCE 2 @ advance rPC - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_quick: /* 0xe6 */ -/* File: arm/op_iput_quick.S */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - mov r2, rINST, lsr #12 @ r2<- B - FETCH r1, 1 @ r1<- field byte offset - GET_VREG r3, r2 @ r3<- fp[B], the object pointer - ubfx r2, rINST, #8, #4 @ r2<- A - cmp r3, #0 @ check object for null - beq common_errNullObject @ object was null - GET_VREG r0, r2 @ r0<- fp[A] - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - str r0, [r3, r1] @ obj.field<- r0 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_wide_quick: /* 0xe7 */ -/* File: arm/op_iput_wide_quick.S */ - /* iput-wide-quick vA, vB, offset@CCCC */ - mov r2, rINST, lsr #12 @ r2<- B - FETCH r3, 1 @ r3<- field byte offset - GET_VREG r2, r2 @ r2<- fp[B], the object pointer - ubfx r0, rINST, #8, #4 @ r0<- A - cmp r2, #0 @ check object for null - beq common_errNullObject @ object was null - VREG_INDEX_TO_ADDR r0, r0 @ r0<- &fp[A] - ldmia r0, {r0-r1} @ r0/r1<- fp[A]/fp[A+1] - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - strd r0, [r2, r3] @ obj.field<- r0/r1 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_object_quick: /* 0xe8 */ -/* File: arm/op_iput_object_quick.S */ - EXPORT_PC - add r0, rFP, #OFF_FP_SHADOWFRAME - mov r1, rPC - mov r2, rINST - bl MterpIputObjectQuick - cmp r0, #0 - beq MterpException - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual_quick: /* 0xe9 */ -/* File: arm/op_invoke_virtual_quick.S */ -/* File: arm/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtualQuick - EXPORT_PC - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - mov r3, rINST - bl MterpInvokeVirtualQuick - cmp r0, #0 - beq MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cmp r0, #0 - bne MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual_range_quick: /* 0xea */ -/* File: arm/op_invoke_virtual_range_quick.S */ -/* File: arm/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtualQuickRange - EXPORT_PC - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - mov r3, rINST - bl MterpInvokeVirtualQuickRange - cmp r0, #0 - beq MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cmp r0, #0 - bne MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_boolean_quick: /* 0xeb */ -/* File: arm/op_iput_boolean_quick.S */ -/* File: arm/op_iput_quick.S */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - mov r2, rINST, lsr #12 @ r2<- B - FETCH r1, 1 @ r1<- field byte offset - GET_VREG r3, r2 @ r3<- fp[B], the object pointer - ubfx r2, rINST, #8, #4 @ r2<- A - cmp r3, #0 @ check object for null - beq common_errNullObject @ object was null - GET_VREG r0, r2 @ r0<- fp[A] - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - strb r0, [r3, r1] @ obj.field<- r0 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_byte_quick: /* 0xec */ -/* File: arm/op_iput_byte_quick.S */ -/* File: arm/op_iput_quick.S */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - mov r2, rINST, lsr #12 @ r2<- B - FETCH r1, 1 @ r1<- field byte offset - GET_VREG r3, r2 @ r3<- fp[B], the object pointer - ubfx r2, rINST, #8, #4 @ r2<- A - cmp r3, #0 @ check object for null - beq common_errNullObject @ object was null - GET_VREG r0, r2 @ r0<- fp[A] - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - strb r0, [r3, r1] @ obj.field<- r0 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_char_quick: /* 0xed */ -/* File: arm/op_iput_char_quick.S */ -/* File: arm/op_iput_quick.S */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - mov r2, rINST, lsr #12 @ r2<- B - FETCH r1, 1 @ r1<- field byte offset - GET_VREG r3, r2 @ r3<- fp[B], the object pointer - ubfx r2, rINST, #8, #4 @ r2<- A - cmp r3, #0 @ check object for null - beq common_errNullObject @ object was null - GET_VREG r0, r2 @ r0<- fp[A] - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - strh r0, [r3, r1] @ obj.field<- r0 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_short_quick: /* 0xee */ -/* File: arm/op_iput_short_quick.S */ -/* File: arm/op_iput_quick.S */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - mov r2, rINST, lsr #12 @ r2<- B - FETCH r1, 1 @ r1<- field byte offset - GET_VREG r3, r2 @ r3<- fp[B], the object pointer - ubfx r2, rINST, #8, #4 @ r2<- A - cmp r3, #0 @ check object for null - beq common_errNullObject @ object was null - GET_VREG r0, r2 @ r0<- fp[A] - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - strh r0, [r3, r1] @ obj.field<- r0 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_boolean_quick: /* 0xef */ -/* File: arm/op_iget_boolean_quick.S */ -/* File: arm/op_iget_quick.S */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset@CCCC */ - mov r2, rINST, lsr #12 @ r2<- B - FETCH r1, 1 @ r1<- field byte offset - GET_VREG r3, r2 @ r3<- object we're operating on - ubfx r2, rINST, #8, #4 @ r2<- A - cmp r3, #0 @ check object for null - beq common_errNullObject @ object was null - ldrb r0, [r3, r1] @ r0<- obj.field - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - SET_VREG r0, r2 @ fp[A]<- r0 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_byte_quick: /* 0xf0 */ -/* File: arm/op_iget_byte_quick.S */ -/* File: arm/op_iget_quick.S */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset@CCCC */ - mov r2, rINST, lsr #12 @ r2<- B - FETCH r1, 1 @ r1<- field byte offset - GET_VREG r3, r2 @ r3<- object we're operating on - ubfx r2, rINST, #8, #4 @ r2<- A - cmp r3, #0 @ check object for null - beq common_errNullObject @ object was null - ldrsb r0, [r3, r1] @ r0<- obj.field - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - SET_VREG r0, r2 @ fp[A]<- r0 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_char_quick: /* 0xf1 */ -/* File: arm/op_iget_char_quick.S */ -/* File: arm/op_iget_quick.S */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset@CCCC */ - mov r2, rINST, lsr #12 @ r2<- B - FETCH r1, 1 @ r1<- field byte offset - GET_VREG r3, r2 @ r3<- object we're operating on - ubfx r2, rINST, #8, #4 @ r2<- A - cmp r3, #0 @ check object for null - beq common_errNullObject @ object was null - ldrh r0, [r3, r1] @ r0<- obj.field - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - SET_VREG r0, r2 @ fp[A]<- r0 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_short_quick: /* 0xf2 */ -/* File: arm/op_iget_short_quick.S */ -/* File: arm/op_iget_quick.S */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset@CCCC */ - mov r2, rINST, lsr #12 @ r2<- B - FETCH r1, 1 @ r1<- field byte offset - GET_VREG r3, r2 @ r3<- object we're operating on - ubfx r2, rINST, #8, #4 @ r2<- A - cmp r3, #0 @ check object for null - beq common_errNullObject @ object was null - ldrsh r0, [r3, r1] @ r0<- obj.field - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - SET_VREG r0, r2 @ fp[A]<- r0 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f3: /* 0xf3 */ -/* File: arm/op_unused_f3.S */ -/* File: arm/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f4: /* 0xf4 */ -/* File: arm/op_unused_f4.S */ -/* File: arm/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f5: /* 0xf5 */ -/* File: arm/op_unused_f5.S */ -/* File: arm/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f6: /* 0xf6 */ -/* File: arm/op_unused_f6.S */ -/* File: arm/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f7: /* 0xf7 */ -/* File: arm/op_unused_f7.S */ -/* File: arm/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f8: /* 0xf8 */ -/* File: arm/op_unused_f8.S */ -/* File: arm/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f9: /* 0xf9 */ -/* File: arm/op_unused_f9.S */ -/* File: arm/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_polymorphic: /* 0xfa */ -/* File: arm/op_invoke_polymorphic.S */ -/* File: arm/invoke_polymorphic.S */ - /* - * invoke-polymorphic handler wrapper. - */ - /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ - .extern MterpInvokePolymorphic - EXPORT_PC - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - mov r3, rINST - bl MterpInvokePolymorphic - cmp r0, #0 - beq MterpException - FETCH_ADVANCE_INST 4 - bl MterpShouldSwitchInterpreters - cmp r0, #0 - bne MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_polymorphic_range: /* 0xfb */ -/* File: arm/op_invoke_polymorphic_range.S */ -/* File: arm/invoke_polymorphic.S */ - /* - * invoke-polymorphic handler wrapper. - */ - /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ - .extern MterpInvokePolymorphicRange - EXPORT_PC - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - mov r3, rINST - bl MterpInvokePolymorphicRange - cmp r0, #0 - beq MterpException - FETCH_ADVANCE_INST 4 - bl MterpShouldSwitchInterpreters - cmp r0, #0 - bne MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_custom: /* 0xfc */ -/* File: arm/op_invoke_custom.S */ -/* File: arm/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeCustom - EXPORT_PC - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - mov r3, rINST - bl MterpInvokeCustom - cmp r0, #0 - beq MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cmp r0, #0 - bne MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - - - /* - * Handle an invoke-custom invocation. - * - * for: invoke-custom, invoke-custom/range - */ - /* op vB, {vD, vE, vF, vG, vA}, call_site@BBBB */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, call_site@BBBB */ - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_custom_range: /* 0xfd */ -/* File: arm/op_invoke_custom_range.S */ -/* File: arm/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeCustomRange - EXPORT_PC - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - mov r3, rINST - bl MterpInvokeCustomRange - cmp r0, #0 - beq MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cmp r0, #0 - bne MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - - - -/* ------------------------------ */ - .balign 128 -.L_op_const_method_handle: /* 0xfe */ -/* File: arm/op_const_method_handle.S */ -/* File: arm/const.S */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstMethodHandle - EXPORT_PC - FETCH r0, 1 @ r0<- BBBB - mov r1, rINST, lsr #8 @ r1<- AA - add r2, rFP, #OFF_FP_SHADOWFRAME - mov r3, rSELF - bl MterpConstMethodHandle @ (index, tgt_reg, shadow_frame, self) - PREFETCH_INST 2 @ load rINST - cmp r0, #0 @ fail? - bne MterpPossibleException @ let reference interpreter deal with it. - ADVANCE 2 @ advance rPC - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_const_method_type: /* 0xff */ -/* File: arm/op_const_method_type.S */ -/* File: arm/const.S */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstMethodType - EXPORT_PC - FETCH r0, 1 @ r0<- BBBB - mov r1, rINST, lsr #8 @ r1<- AA - add r2, rFP, #OFF_FP_SHADOWFRAME - mov r3, rSELF - bl MterpConstMethodType @ (index, tgt_reg, shadow_frame, self) - PREFETCH_INST 2 @ load rINST - cmp r0, #0 @ fail? - bne MterpPossibleException @ let reference interpreter deal with it. - ADVANCE 2 @ advance rPC - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - - - .balign 128 -/* File: arm/instruction_end.S */ - - .type artMterpAsmInstructionEnd, #object - .hidden artMterpAsmInstructionEnd - .global artMterpAsmInstructionEnd -artMterpAsmInstructionEnd: - - -/* - * =========================================================================== - * Sister implementations - * =========================================================================== - */ -/* File: arm/instruction_start_sister.S */ - - .type artMterpAsmSisterStart, #object - .hidden artMterpAsmSisterStart - .global artMterpAsmSisterStart - .text - .balign 4 -artMterpAsmSisterStart: - - -/* continuation for op_float_to_long */ -/* - * Convert the float in r0 to a long in r0/r1. - * - * We have to clip values to long min/max per the specification. The - * expected common case is a "reasonable" value that converts directly - * to modest integer. The EABI convert function isn't doing this for us. - */ -f2l_doconv: - ubfx r2, r0, #23, #8 @ grab the exponent - cmp r2, #0xbe @ MININT < x > MAXINT? - bhs f2l_special_cases - b __aeabi_f2lz @ tail call to convert float to long -f2l_special_cases: - cmp r2, #0xff @ NaN or infinity? - beq f2l_maybeNaN -f2l_notNaN: - adds r0, r0, r0 @ sign bit to carry - mov r0, #0xffffffff @ assume maxlong for lsw - mov r1, #0x7fffffff @ assume maxlong for msw - adc r0, r0, #0 - adc r1, r1, #0 @ convert maxlong to minlong if exp negative - bx lr @ return -f2l_maybeNaN: - lsls r3, r0, #9 - beq f2l_notNaN @ if fraction is non-zero, it's a NaN - mov r0, #0 - mov r1, #0 - bx lr @ return 0 for NaN - -/* continuation for op_double_to_long */ -/* - * Convert the double in r0/r1 to a long in r0/r1. - * - * We have to clip values to long min/max per the specification. The - * expected common case is a "reasonable" value that converts directly - * to modest integer. The EABI convert function isn't doing this for us. - */ -d2l_doconv: - ubfx r2, r1, #20, #11 @ grab the exponent - movw r3, #0x43e - cmp r2, r3 @ MINLONG < x > MAXLONG? - bhs d2l_special_cases - b __aeabi_d2lz @ tail call to convert double to long -d2l_special_cases: - movw r3, #0x7ff - cmp r2, r3 - beq d2l_maybeNaN @ NaN? -d2l_notNaN: - adds r1, r1, r1 @ sign bit to carry - mov r0, #0xffffffff @ assume maxlong for lsw - mov r1, #0x7fffffff @ assume maxlong for msw - adc r0, r0, #0 - adc r1, r1, #0 @ convert maxlong to minlong if exp negative - bx lr @ return -d2l_maybeNaN: - orrs r3, r0, r1, lsl #12 - beq d2l_notNaN @ if fraction is non-zero, it's a NaN - mov r0, #0 - mov r1, #0 - bx lr @ return 0 for NaN -/* File: arm/instruction_end_sister.S */ - - .type artMterpAsmSisterEnd, #object - .hidden artMterpAsmSisterEnd - .global artMterpAsmSisterEnd -artMterpAsmSisterEnd: - -/* File: arm/instruction_start_alt.S */ - - .type artMterpAsmAltInstructionStart, #object - .hidden artMterpAsmAltInstructionStart - .global artMterpAsmAltInstructionStart -artMterpAsmAltInstructionStart = .L_ALT_op_nop - .text - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_nop: /* 0x00 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_nop - sub lr, lr, #(.L_ALT_op_nop - .L_op_nop) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move: /* 0x01 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_move - sub lr, lr, #(.L_ALT_op_move - .L_op_move) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_from16: /* 0x02 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_move_from16 - sub lr, lr, #(.L_ALT_op_move_from16 - .L_op_move_from16) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_16: /* 0x03 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_move_16 - sub lr, lr, #(.L_ALT_op_move_16 - .L_op_move_16) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_wide: /* 0x04 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_move_wide - sub lr, lr, #(.L_ALT_op_move_wide - .L_op_move_wide) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_wide_from16: /* 0x05 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_move_wide_from16 - sub lr, lr, #(.L_ALT_op_move_wide_from16 - .L_op_move_wide_from16) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_wide_16: /* 0x06 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_move_wide_16 - sub lr, lr, #(.L_ALT_op_move_wide_16 - .L_op_move_wide_16) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_object: /* 0x07 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_move_object - sub lr, lr, #(.L_ALT_op_move_object - .L_op_move_object) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_object_from16: /* 0x08 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_move_object_from16 - sub lr, lr, #(.L_ALT_op_move_object_from16 - .L_op_move_object_from16) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_object_16: /* 0x09 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_move_object_16 - sub lr, lr, #(.L_ALT_op_move_object_16 - .L_op_move_object_16) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_result: /* 0x0a */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_move_result - sub lr, lr, #(.L_ALT_op_move_result - .L_op_move_result) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_result_wide: /* 0x0b */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_move_result_wide - sub lr, lr, #(.L_ALT_op_move_result_wide - .L_op_move_result_wide) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_result_object: /* 0x0c */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_move_result_object - sub lr, lr, #(.L_ALT_op_move_result_object - .L_op_move_result_object) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_exception: /* 0x0d */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_move_exception - sub lr, lr, #(.L_ALT_op_move_exception - .L_op_move_exception) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_void: /* 0x0e */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_return_void - sub lr, lr, #(.L_ALT_op_return_void - .L_op_return_void) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return: /* 0x0f */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_return - sub lr, lr, #(.L_ALT_op_return - .L_op_return) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_wide: /* 0x10 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_return_wide - sub lr, lr, #(.L_ALT_op_return_wide - .L_op_return_wide) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_object: /* 0x11 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_return_object - sub lr, lr, #(.L_ALT_op_return_object - .L_op_return_object) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_4: /* 0x12 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_const_4 - sub lr, lr, #(.L_ALT_op_const_4 - .L_op_const_4) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_16: /* 0x13 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_const_16 - sub lr, lr, #(.L_ALT_op_const_16 - .L_op_const_16) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const: /* 0x14 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_const - sub lr, lr, #(.L_ALT_op_const - .L_op_const) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_high16: /* 0x15 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_const_high16 - sub lr, lr, #(.L_ALT_op_const_high16 - .L_op_const_high16) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide_16: /* 0x16 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_const_wide_16 - sub lr, lr, #(.L_ALT_op_const_wide_16 - .L_op_const_wide_16) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide_32: /* 0x17 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_const_wide_32 - sub lr, lr, #(.L_ALT_op_const_wide_32 - .L_op_const_wide_32) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide: /* 0x18 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_const_wide - sub lr, lr, #(.L_ALT_op_const_wide - .L_op_const_wide) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide_high16: /* 0x19 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_const_wide_high16 - sub lr, lr, #(.L_ALT_op_const_wide_high16 - .L_op_const_wide_high16) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_string: /* 0x1a */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_const_string - sub lr, lr, #(.L_ALT_op_const_string - .L_op_const_string) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_string_jumbo: /* 0x1b */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_const_string_jumbo - sub lr, lr, #(.L_ALT_op_const_string_jumbo - .L_op_const_string_jumbo) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_class: /* 0x1c */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_const_class - sub lr, lr, #(.L_ALT_op_const_class - .L_op_const_class) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_monitor_enter: /* 0x1d */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_monitor_enter - sub lr, lr, #(.L_ALT_op_monitor_enter - .L_op_monitor_enter) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_monitor_exit: /* 0x1e */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_monitor_exit - sub lr, lr, #(.L_ALT_op_monitor_exit - .L_op_monitor_exit) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_check_cast: /* 0x1f */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_check_cast - sub lr, lr, #(.L_ALT_op_check_cast - .L_op_check_cast) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_instance_of: /* 0x20 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_instance_of - sub lr, lr, #(.L_ALT_op_instance_of - .L_op_instance_of) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_array_length: /* 0x21 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_array_length - sub lr, lr, #(.L_ALT_op_array_length - .L_op_array_length) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_new_instance: /* 0x22 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_new_instance - sub lr, lr, #(.L_ALT_op_new_instance - .L_op_new_instance) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_new_array: /* 0x23 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_new_array - sub lr, lr, #(.L_ALT_op_new_array - .L_op_new_array) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_filled_new_array: /* 0x24 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_filled_new_array - sub lr, lr, #(.L_ALT_op_filled_new_array - .L_op_filled_new_array) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_filled_new_array_range: /* 0x25 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_filled_new_array_range - sub lr, lr, #(.L_ALT_op_filled_new_array_range - .L_op_filled_new_array_range) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_fill_array_data: /* 0x26 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_fill_array_data - sub lr, lr, #(.L_ALT_op_fill_array_data - .L_op_fill_array_data) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_throw: /* 0x27 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_throw - sub lr, lr, #(.L_ALT_op_throw - .L_op_throw) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_goto: /* 0x28 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_goto - sub lr, lr, #(.L_ALT_op_goto - .L_op_goto) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_goto_16: /* 0x29 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_goto_16 - sub lr, lr, #(.L_ALT_op_goto_16 - .L_op_goto_16) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_goto_32: /* 0x2a */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_goto_32 - sub lr, lr, #(.L_ALT_op_goto_32 - .L_op_goto_32) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_packed_switch: /* 0x2b */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_packed_switch - sub lr, lr, #(.L_ALT_op_packed_switch - .L_op_packed_switch) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sparse_switch: /* 0x2c */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sparse_switch - sub lr, lr, #(.L_ALT_op_sparse_switch - .L_op_sparse_switch) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpl_float: /* 0x2d */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_cmpl_float - sub lr, lr, #(.L_ALT_op_cmpl_float - .L_op_cmpl_float) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpg_float: /* 0x2e */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_cmpg_float - sub lr, lr, #(.L_ALT_op_cmpg_float - .L_op_cmpg_float) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpl_double: /* 0x2f */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_cmpl_double - sub lr, lr, #(.L_ALT_op_cmpl_double - .L_op_cmpl_double) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpg_double: /* 0x30 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_cmpg_double - sub lr, lr, #(.L_ALT_op_cmpg_double - .L_op_cmpg_double) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmp_long: /* 0x31 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_cmp_long - sub lr, lr, #(.L_ALT_op_cmp_long - .L_op_cmp_long) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_eq: /* 0x32 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_if_eq - sub lr, lr, #(.L_ALT_op_if_eq - .L_op_if_eq) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_ne: /* 0x33 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_if_ne - sub lr, lr, #(.L_ALT_op_if_ne - .L_op_if_ne) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_lt: /* 0x34 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_if_lt - sub lr, lr, #(.L_ALT_op_if_lt - .L_op_if_lt) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_ge: /* 0x35 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_if_ge - sub lr, lr, #(.L_ALT_op_if_ge - .L_op_if_ge) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_gt: /* 0x36 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_if_gt - sub lr, lr, #(.L_ALT_op_if_gt - .L_op_if_gt) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_le: /* 0x37 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_if_le - sub lr, lr, #(.L_ALT_op_if_le - .L_op_if_le) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_eqz: /* 0x38 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_if_eqz - sub lr, lr, #(.L_ALT_op_if_eqz - .L_op_if_eqz) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_nez: /* 0x39 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_if_nez - sub lr, lr, #(.L_ALT_op_if_nez - .L_op_if_nez) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_ltz: /* 0x3a */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_if_ltz - sub lr, lr, #(.L_ALT_op_if_ltz - .L_op_if_ltz) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_gez: /* 0x3b */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_if_gez - sub lr, lr, #(.L_ALT_op_if_gez - .L_op_if_gez) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_gtz: /* 0x3c */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_if_gtz - sub lr, lr, #(.L_ALT_op_if_gtz - .L_op_if_gtz) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_lez: /* 0x3d */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_if_lez - sub lr, lr, #(.L_ALT_op_if_lez - .L_op_if_lez) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_3e: /* 0x3e */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_unused_3e - sub lr, lr, #(.L_ALT_op_unused_3e - .L_op_unused_3e) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_3f: /* 0x3f */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_unused_3f - sub lr, lr, #(.L_ALT_op_unused_3f - .L_op_unused_3f) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_40: /* 0x40 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_unused_40 - sub lr, lr, #(.L_ALT_op_unused_40 - .L_op_unused_40) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_41: /* 0x41 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_unused_41 - sub lr, lr, #(.L_ALT_op_unused_41 - .L_op_unused_41) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_42: /* 0x42 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_unused_42 - sub lr, lr, #(.L_ALT_op_unused_42 - .L_op_unused_42) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_43: /* 0x43 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_unused_43 - sub lr, lr, #(.L_ALT_op_unused_43 - .L_op_unused_43) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget: /* 0x44 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_aget - sub lr, lr, #(.L_ALT_op_aget - .L_op_aget) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_wide: /* 0x45 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_aget_wide - sub lr, lr, #(.L_ALT_op_aget_wide - .L_op_aget_wide) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_object: /* 0x46 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_aget_object - sub lr, lr, #(.L_ALT_op_aget_object - .L_op_aget_object) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_boolean: /* 0x47 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_aget_boolean - sub lr, lr, #(.L_ALT_op_aget_boolean - .L_op_aget_boolean) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_byte: /* 0x48 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_aget_byte - sub lr, lr, #(.L_ALT_op_aget_byte - .L_op_aget_byte) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_char: /* 0x49 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_aget_char - sub lr, lr, #(.L_ALT_op_aget_char - .L_op_aget_char) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_short: /* 0x4a */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_aget_short - sub lr, lr, #(.L_ALT_op_aget_short - .L_op_aget_short) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput: /* 0x4b */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_aput - sub lr, lr, #(.L_ALT_op_aput - .L_op_aput) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_wide: /* 0x4c */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_aput_wide - sub lr, lr, #(.L_ALT_op_aput_wide - .L_op_aput_wide) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_object: /* 0x4d */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_aput_object - sub lr, lr, #(.L_ALT_op_aput_object - .L_op_aput_object) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_boolean: /* 0x4e */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_aput_boolean - sub lr, lr, #(.L_ALT_op_aput_boolean - .L_op_aput_boolean) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_byte: /* 0x4f */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_aput_byte - sub lr, lr, #(.L_ALT_op_aput_byte - .L_op_aput_byte) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_char: /* 0x50 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_aput_char - sub lr, lr, #(.L_ALT_op_aput_char - .L_op_aput_char) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_short: /* 0x51 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_aput_short - sub lr, lr, #(.L_ALT_op_aput_short - .L_op_aput_short) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget: /* 0x52 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iget - sub lr, lr, #(.L_ALT_op_iget - .L_op_iget) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_wide: /* 0x53 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iget_wide - sub lr, lr, #(.L_ALT_op_iget_wide - .L_op_iget_wide) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_object: /* 0x54 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iget_object - sub lr, lr, #(.L_ALT_op_iget_object - .L_op_iget_object) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_boolean: /* 0x55 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iget_boolean - sub lr, lr, #(.L_ALT_op_iget_boolean - .L_op_iget_boolean) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_byte: /* 0x56 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iget_byte - sub lr, lr, #(.L_ALT_op_iget_byte - .L_op_iget_byte) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_char: /* 0x57 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iget_char - sub lr, lr, #(.L_ALT_op_iget_char - .L_op_iget_char) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_short: /* 0x58 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iget_short - sub lr, lr, #(.L_ALT_op_iget_short - .L_op_iget_short) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput: /* 0x59 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iput - sub lr, lr, #(.L_ALT_op_iput - .L_op_iput) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_wide: /* 0x5a */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iput_wide - sub lr, lr, #(.L_ALT_op_iput_wide - .L_op_iput_wide) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_object: /* 0x5b */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iput_object - sub lr, lr, #(.L_ALT_op_iput_object - .L_op_iput_object) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_boolean: /* 0x5c */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iput_boolean - sub lr, lr, #(.L_ALT_op_iput_boolean - .L_op_iput_boolean) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_byte: /* 0x5d */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iput_byte - sub lr, lr, #(.L_ALT_op_iput_byte - .L_op_iput_byte) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_char: /* 0x5e */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iput_char - sub lr, lr, #(.L_ALT_op_iput_char - .L_op_iput_char) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_short: /* 0x5f */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iput_short - sub lr, lr, #(.L_ALT_op_iput_short - .L_op_iput_short) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget: /* 0x60 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sget - sub lr, lr, #(.L_ALT_op_sget - .L_op_sget) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_wide: /* 0x61 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sget_wide - sub lr, lr, #(.L_ALT_op_sget_wide - .L_op_sget_wide) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_object: /* 0x62 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sget_object - sub lr, lr, #(.L_ALT_op_sget_object - .L_op_sget_object) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_boolean: /* 0x63 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sget_boolean - sub lr, lr, #(.L_ALT_op_sget_boolean - .L_op_sget_boolean) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_byte: /* 0x64 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sget_byte - sub lr, lr, #(.L_ALT_op_sget_byte - .L_op_sget_byte) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_char: /* 0x65 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sget_char - sub lr, lr, #(.L_ALT_op_sget_char - .L_op_sget_char) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_short: /* 0x66 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sget_short - sub lr, lr, #(.L_ALT_op_sget_short - .L_op_sget_short) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput: /* 0x67 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sput - sub lr, lr, #(.L_ALT_op_sput - .L_op_sput) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_wide: /* 0x68 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sput_wide - sub lr, lr, #(.L_ALT_op_sput_wide - .L_op_sput_wide) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_object: /* 0x69 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sput_object - sub lr, lr, #(.L_ALT_op_sput_object - .L_op_sput_object) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_boolean: /* 0x6a */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sput_boolean - sub lr, lr, #(.L_ALT_op_sput_boolean - .L_op_sput_boolean) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_byte: /* 0x6b */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sput_byte - sub lr, lr, #(.L_ALT_op_sput_byte - .L_op_sput_byte) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_char: /* 0x6c */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sput_char - sub lr, lr, #(.L_ALT_op_sput_char - .L_op_sput_char) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_short: /* 0x6d */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sput_short - sub lr, lr, #(.L_ALT_op_sput_short - .L_op_sput_short) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual: /* 0x6e */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_invoke_virtual - sub lr, lr, #(.L_ALT_op_invoke_virtual - .L_op_invoke_virtual) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_super: /* 0x6f */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_invoke_super - sub lr, lr, #(.L_ALT_op_invoke_super - .L_op_invoke_super) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_direct: /* 0x70 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_invoke_direct - sub lr, lr, #(.L_ALT_op_invoke_direct - .L_op_invoke_direct) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_static: /* 0x71 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_invoke_static - sub lr, lr, #(.L_ALT_op_invoke_static - .L_op_invoke_static) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_interface: /* 0x72 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_invoke_interface - sub lr, lr, #(.L_ALT_op_invoke_interface - .L_op_invoke_interface) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_void_no_barrier: /* 0x73 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_return_void_no_barrier - sub lr, lr, #(.L_ALT_op_return_void_no_barrier - .L_op_return_void_no_barrier) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual_range: /* 0x74 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_invoke_virtual_range - sub lr, lr, #(.L_ALT_op_invoke_virtual_range - .L_op_invoke_virtual_range) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_super_range: /* 0x75 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_invoke_super_range - sub lr, lr, #(.L_ALT_op_invoke_super_range - .L_op_invoke_super_range) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_direct_range: /* 0x76 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_invoke_direct_range - sub lr, lr, #(.L_ALT_op_invoke_direct_range - .L_op_invoke_direct_range) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_static_range: /* 0x77 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_invoke_static_range - sub lr, lr, #(.L_ALT_op_invoke_static_range - .L_op_invoke_static_range) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_interface_range: /* 0x78 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_invoke_interface_range - sub lr, lr, #(.L_ALT_op_invoke_interface_range - .L_op_invoke_interface_range) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_79: /* 0x79 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_unused_79 - sub lr, lr, #(.L_ALT_op_unused_79 - .L_op_unused_79) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_7a: /* 0x7a */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_unused_7a - sub lr, lr, #(.L_ALT_op_unused_7a - .L_op_unused_7a) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_int: /* 0x7b */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_neg_int - sub lr, lr, #(.L_ALT_op_neg_int - .L_op_neg_int) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_not_int: /* 0x7c */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_not_int - sub lr, lr, #(.L_ALT_op_not_int - .L_op_not_int) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_long: /* 0x7d */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_neg_long - sub lr, lr, #(.L_ALT_op_neg_long - .L_op_neg_long) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_not_long: /* 0x7e */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_not_long - sub lr, lr, #(.L_ALT_op_not_long - .L_op_not_long) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_float: /* 0x7f */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_neg_float - sub lr, lr, #(.L_ALT_op_neg_float - .L_op_neg_float) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_double: /* 0x80 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_neg_double - sub lr, lr, #(.L_ALT_op_neg_double - .L_op_neg_double) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_long: /* 0x81 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_int_to_long - sub lr, lr, #(.L_ALT_op_int_to_long - .L_op_int_to_long) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_float: /* 0x82 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_int_to_float - sub lr, lr, #(.L_ALT_op_int_to_float - .L_op_int_to_float) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_double: /* 0x83 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_int_to_double - sub lr, lr, #(.L_ALT_op_int_to_double - .L_op_int_to_double) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_long_to_int: /* 0x84 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_long_to_int - sub lr, lr, #(.L_ALT_op_long_to_int - .L_op_long_to_int) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_long_to_float: /* 0x85 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_long_to_float - sub lr, lr, #(.L_ALT_op_long_to_float - .L_op_long_to_float) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_long_to_double: /* 0x86 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_long_to_double - sub lr, lr, #(.L_ALT_op_long_to_double - .L_op_long_to_double) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_float_to_int: /* 0x87 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_float_to_int - sub lr, lr, #(.L_ALT_op_float_to_int - .L_op_float_to_int) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_float_to_long: /* 0x88 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_float_to_long - sub lr, lr, #(.L_ALT_op_float_to_long - .L_op_float_to_long) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_float_to_double: /* 0x89 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_float_to_double - sub lr, lr, #(.L_ALT_op_float_to_double - .L_op_float_to_double) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_double_to_int: /* 0x8a */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_double_to_int - sub lr, lr, #(.L_ALT_op_double_to_int - .L_op_double_to_int) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_double_to_long: /* 0x8b */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_double_to_long - sub lr, lr, #(.L_ALT_op_double_to_long - .L_op_double_to_long) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_double_to_float: /* 0x8c */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_double_to_float - sub lr, lr, #(.L_ALT_op_double_to_float - .L_op_double_to_float) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_byte: /* 0x8d */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_int_to_byte - sub lr, lr, #(.L_ALT_op_int_to_byte - .L_op_int_to_byte) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_char: /* 0x8e */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_int_to_char - sub lr, lr, #(.L_ALT_op_int_to_char - .L_op_int_to_char) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_short: /* 0x8f */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_int_to_short - sub lr, lr, #(.L_ALT_op_int_to_short - .L_op_int_to_short) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int: /* 0x90 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_add_int - sub lr, lr, #(.L_ALT_op_add_int - .L_op_add_int) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_int: /* 0x91 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sub_int - sub lr, lr, #(.L_ALT_op_sub_int - .L_op_sub_int) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int: /* 0x92 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_mul_int - sub lr, lr, #(.L_ALT_op_mul_int - .L_op_mul_int) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int: /* 0x93 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_div_int - sub lr, lr, #(.L_ALT_op_div_int - .L_op_div_int) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int: /* 0x94 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_rem_int - sub lr, lr, #(.L_ALT_op_rem_int - .L_op_rem_int) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int: /* 0x95 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_and_int - sub lr, lr, #(.L_ALT_op_and_int - .L_op_and_int) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int: /* 0x96 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_or_int - sub lr, lr, #(.L_ALT_op_or_int - .L_op_or_int) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int: /* 0x97 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_xor_int - sub lr, lr, #(.L_ALT_op_xor_int - .L_op_xor_int) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_int: /* 0x98 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_shl_int - sub lr, lr, #(.L_ALT_op_shl_int - .L_op_shl_int) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_int: /* 0x99 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_shr_int - sub lr, lr, #(.L_ALT_op_shr_int - .L_op_shr_int) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_int: /* 0x9a */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_ushr_int - sub lr, lr, #(.L_ALT_op_ushr_int - .L_op_ushr_int) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_long: /* 0x9b */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_add_long - sub lr, lr, #(.L_ALT_op_add_long - .L_op_add_long) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_long: /* 0x9c */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sub_long - sub lr, lr, #(.L_ALT_op_sub_long - .L_op_sub_long) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_long: /* 0x9d */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_mul_long - sub lr, lr, #(.L_ALT_op_mul_long - .L_op_mul_long) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_long: /* 0x9e */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_div_long - sub lr, lr, #(.L_ALT_op_div_long - .L_op_div_long) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_long: /* 0x9f */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_rem_long - sub lr, lr, #(.L_ALT_op_rem_long - .L_op_rem_long) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_long: /* 0xa0 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_and_long - sub lr, lr, #(.L_ALT_op_and_long - .L_op_and_long) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_long: /* 0xa1 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_or_long - sub lr, lr, #(.L_ALT_op_or_long - .L_op_or_long) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_long: /* 0xa2 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_xor_long - sub lr, lr, #(.L_ALT_op_xor_long - .L_op_xor_long) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_long: /* 0xa3 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_shl_long - sub lr, lr, #(.L_ALT_op_shl_long - .L_op_shl_long) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_long: /* 0xa4 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_shr_long - sub lr, lr, #(.L_ALT_op_shr_long - .L_op_shr_long) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_long: /* 0xa5 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_ushr_long - sub lr, lr, #(.L_ALT_op_ushr_long - .L_op_ushr_long) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_float: /* 0xa6 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_add_float - sub lr, lr, #(.L_ALT_op_add_float - .L_op_add_float) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_float: /* 0xa7 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sub_float - sub lr, lr, #(.L_ALT_op_sub_float - .L_op_sub_float) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_float: /* 0xa8 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_mul_float - sub lr, lr, #(.L_ALT_op_mul_float - .L_op_mul_float) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_float: /* 0xa9 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_div_float - sub lr, lr, #(.L_ALT_op_div_float - .L_op_div_float) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_float: /* 0xaa */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_rem_float - sub lr, lr, #(.L_ALT_op_rem_float - .L_op_rem_float) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_double: /* 0xab */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_add_double - sub lr, lr, #(.L_ALT_op_add_double - .L_op_add_double) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_double: /* 0xac */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sub_double - sub lr, lr, #(.L_ALT_op_sub_double - .L_op_sub_double) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_double: /* 0xad */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_mul_double - sub lr, lr, #(.L_ALT_op_mul_double - .L_op_mul_double) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_double: /* 0xae */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_div_double - sub lr, lr, #(.L_ALT_op_div_double - .L_op_div_double) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_double: /* 0xaf */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_rem_double - sub lr, lr, #(.L_ALT_op_rem_double - .L_op_rem_double) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int_2addr: /* 0xb0 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_add_int_2addr - sub lr, lr, #(.L_ALT_op_add_int_2addr - .L_op_add_int_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_int_2addr: /* 0xb1 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sub_int_2addr - sub lr, lr, #(.L_ALT_op_sub_int_2addr - .L_op_sub_int_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int_2addr: /* 0xb2 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_mul_int_2addr - sub lr, lr, #(.L_ALT_op_mul_int_2addr - .L_op_mul_int_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int_2addr: /* 0xb3 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_div_int_2addr - sub lr, lr, #(.L_ALT_op_div_int_2addr - .L_op_div_int_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int_2addr: /* 0xb4 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_rem_int_2addr - sub lr, lr, #(.L_ALT_op_rem_int_2addr - .L_op_rem_int_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int_2addr: /* 0xb5 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_and_int_2addr - sub lr, lr, #(.L_ALT_op_and_int_2addr - .L_op_and_int_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int_2addr: /* 0xb6 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_or_int_2addr - sub lr, lr, #(.L_ALT_op_or_int_2addr - .L_op_or_int_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int_2addr: /* 0xb7 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_xor_int_2addr - sub lr, lr, #(.L_ALT_op_xor_int_2addr - .L_op_xor_int_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_int_2addr: /* 0xb8 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_shl_int_2addr - sub lr, lr, #(.L_ALT_op_shl_int_2addr - .L_op_shl_int_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_int_2addr: /* 0xb9 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_shr_int_2addr - sub lr, lr, #(.L_ALT_op_shr_int_2addr - .L_op_shr_int_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_int_2addr: /* 0xba */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_ushr_int_2addr - sub lr, lr, #(.L_ALT_op_ushr_int_2addr - .L_op_ushr_int_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_long_2addr: /* 0xbb */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_add_long_2addr - sub lr, lr, #(.L_ALT_op_add_long_2addr - .L_op_add_long_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_long_2addr: /* 0xbc */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sub_long_2addr - sub lr, lr, #(.L_ALT_op_sub_long_2addr - .L_op_sub_long_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_long_2addr: /* 0xbd */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_mul_long_2addr - sub lr, lr, #(.L_ALT_op_mul_long_2addr - .L_op_mul_long_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_long_2addr: /* 0xbe */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_div_long_2addr - sub lr, lr, #(.L_ALT_op_div_long_2addr - .L_op_div_long_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_long_2addr: /* 0xbf */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_rem_long_2addr - sub lr, lr, #(.L_ALT_op_rem_long_2addr - .L_op_rem_long_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_long_2addr: /* 0xc0 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_and_long_2addr - sub lr, lr, #(.L_ALT_op_and_long_2addr - .L_op_and_long_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_long_2addr: /* 0xc1 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_or_long_2addr - sub lr, lr, #(.L_ALT_op_or_long_2addr - .L_op_or_long_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_long_2addr: /* 0xc2 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_xor_long_2addr - sub lr, lr, #(.L_ALT_op_xor_long_2addr - .L_op_xor_long_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_long_2addr: /* 0xc3 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_shl_long_2addr - sub lr, lr, #(.L_ALT_op_shl_long_2addr - .L_op_shl_long_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_long_2addr: /* 0xc4 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_shr_long_2addr - sub lr, lr, #(.L_ALT_op_shr_long_2addr - .L_op_shr_long_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_long_2addr: /* 0xc5 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_ushr_long_2addr - sub lr, lr, #(.L_ALT_op_ushr_long_2addr - .L_op_ushr_long_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_float_2addr: /* 0xc6 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_add_float_2addr - sub lr, lr, #(.L_ALT_op_add_float_2addr - .L_op_add_float_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_float_2addr: /* 0xc7 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sub_float_2addr - sub lr, lr, #(.L_ALT_op_sub_float_2addr - .L_op_sub_float_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_float_2addr: /* 0xc8 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_mul_float_2addr - sub lr, lr, #(.L_ALT_op_mul_float_2addr - .L_op_mul_float_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_float_2addr: /* 0xc9 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_div_float_2addr - sub lr, lr, #(.L_ALT_op_div_float_2addr - .L_op_div_float_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_float_2addr: /* 0xca */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_rem_float_2addr - sub lr, lr, #(.L_ALT_op_rem_float_2addr - .L_op_rem_float_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_double_2addr: /* 0xcb */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_add_double_2addr - sub lr, lr, #(.L_ALT_op_add_double_2addr - .L_op_add_double_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_double_2addr: /* 0xcc */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_sub_double_2addr - sub lr, lr, #(.L_ALT_op_sub_double_2addr - .L_op_sub_double_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_double_2addr: /* 0xcd */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_mul_double_2addr - sub lr, lr, #(.L_ALT_op_mul_double_2addr - .L_op_mul_double_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_double_2addr: /* 0xce */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_div_double_2addr - sub lr, lr, #(.L_ALT_op_div_double_2addr - .L_op_div_double_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_double_2addr: /* 0xcf */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_rem_double_2addr - sub lr, lr, #(.L_ALT_op_rem_double_2addr - .L_op_rem_double_2addr) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int_lit16: /* 0xd0 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_add_int_lit16 - sub lr, lr, #(.L_ALT_op_add_int_lit16 - .L_op_add_int_lit16) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rsub_int: /* 0xd1 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_rsub_int - sub lr, lr, #(.L_ALT_op_rsub_int - .L_op_rsub_int) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int_lit16: /* 0xd2 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_mul_int_lit16 - sub lr, lr, #(.L_ALT_op_mul_int_lit16 - .L_op_mul_int_lit16) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int_lit16: /* 0xd3 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_div_int_lit16 - sub lr, lr, #(.L_ALT_op_div_int_lit16 - .L_op_div_int_lit16) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int_lit16: /* 0xd4 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_rem_int_lit16 - sub lr, lr, #(.L_ALT_op_rem_int_lit16 - .L_op_rem_int_lit16) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int_lit16: /* 0xd5 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_and_int_lit16 - sub lr, lr, #(.L_ALT_op_and_int_lit16 - .L_op_and_int_lit16) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int_lit16: /* 0xd6 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_or_int_lit16 - sub lr, lr, #(.L_ALT_op_or_int_lit16 - .L_op_or_int_lit16) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int_lit16: /* 0xd7 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_xor_int_lit16 - sub lr, lr, #(.L_ALT_op_xor_int_lit16 - .L_op_xor_int_lit16) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int_lit8: /* 0xd8 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_add_int_lit8 - sub lr, lr, #(.L_ALT_op_add_int_lit8 - .L_op_add_int_lit8) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rsub_int_lit8: /* 0xd9 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_rsub_int_lit8 - sub lr, lr, #(.L_ALT_op_rsub_int_lit8 - .L_op_rsub_int_lit8) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int_lit8: /* 0xda */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_mul_int_lit8 - sub lr, lr, #(.L_ALT_op_mul_int_lit8 - .L_op_mul_int_lit8) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int_lit8: /* 0xdb */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_div_int_lit8 - sub lr, lr, #(.L_ALT_op_div_int_lit8 - .L_op_div_int_lit8) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int_lit8: /* 0xdc */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_rem_int_lit8 - sub lr, lr, #(.L_ALT_op_rem_int_lit8 - .L_op_rem_int_lit8) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int_lit8: /* 0xdd */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_and_int_lit8 - sub lr, lr, #(.L_ALT_op_and_int_lit8 - .L_op_and_int_lit8) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int_lit8: /* 0xde */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_or_int_lit8 - sub lr, lr, #(.L_ALT_op_or_int_lit8 - .L_op_or_int_lit8) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int_lit8: /* 0xdf */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_xor_int_lit8 - sub lr, lr, #(.L_ALT_op_xor_int_lit8 - .L_op_xor_int_lit8) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_int_lit8: /* 0xe0 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_shl_int_lit8 - sub lr, lr, #(.L_ALT_op_shl_int_lit8 - .L_op_shl_int_lit8) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_int_lit8: /* 0xe1 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_shr_int_lit8 - sub lr, lr, #(.L_ALT_op_shr_int_lit8 - .L_op_shr_int_lit8) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_int_lit8: /* 0xe2 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_ushr_int_lit8 - sub lr, lr, #(.L_ALT_op_ushr_int_lit8 - .L_op_ushr_int_lit8) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_quick: /* 0xe3 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iget_quick - sub lr, lr, #(.L_ALT_op_iget_quick - .L_op_iget_quick) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_wide_quick: /* 0xe4 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iget_wide_quick - sub lr, lr, #(.L_ALT_op_iget_wide_quick - .L_op_iget_wide_quick) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_object_quick: /* 0xe5 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iget_object_quick - sub lr, lr, #(.L_ALT_op_iget_object_quick - .L_op_iget_object_quick) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_quick: /* 0xe6 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iput_quick - sub lr, lr, #(.L_ALT_op_iput_quick - .L_op_iput_quick) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_wide_quick: /* 0xe7 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iput_wide_quick - sub lr, lr, #(.L_ALT_op_iput_wide_quick - .L_op_iput_wide_quick) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_object_quick: /* 0xe8 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iput_object_quick - sub lr, lr, #(.L_ALT_op_iput_object_quick - .L_op_iput_object_quick) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual_quick: /* 0xe9 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_invoke_virtual_quick - sub lr, lr, #(.L_ALT_op_invoke_virtual_quick - .L_op_invoke_virtual_quick) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual_range_quick: /* 0xea */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_invoke_virtual_range_quick - sub lr, lr, #(.L_ALT_op_invoke_virtual_range_quick - .L_op_invoke_virtual_range_quick) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_boolean_quick: /* 0xeb */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iput_boolean_quick - sub lr, lr, #(.L_ALT_op_iput_boolean_quick - .L_op_iput_boolean_quick) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_byte_quick: /* 0xec */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iput_byte_quick - sub lr, lr, #(.L_ALT_op_iput_byte_quick - .L_op_iput_byte_quick) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_char_quick: /* 0xed */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iput_char_quick - sub lr, lr, #(.L_ALT_op_iput_char_quick - .L_op_iput_char_quick) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_short_quick: /* 0xee */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iput_short_quick - sub lr, lr, #(.L_ALT_op_iput_short_quick - .L_op_iput_short_quick) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_boolean_quick: /* 0xef */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iget_boolean_quick - sub lr, lr, #(.L_ALT_op_iget_boolean_quick - .L_op_iget_boolean_quick) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_byte_quick: /* 0xf0 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iget_byte_quick - sub lr, lr, #(.L_ALT_op_iget_byte_quick - .L_op_iget_byte_quick) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_char_quick: /* 0xf1 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iget_char_quick - sub lr, lr, #(.L_ALT_op_iget_char_quick - .L_op_iget_char_quick) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_short_quick: /* 0xf2 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_iget_short_quick - sub lr, lr, #(.L_ALT_op_iget_short_quick - .L_op_iget_short_quick) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f3: /* 0xf3 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_unused_f3 - sub lr, lr, #(.L_ALT_op_unused_f3 - .L_op_unused_f3) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f4: /* 0xf4 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_unused_f4 - sub lr, lr, #(.L_ALT_op_unused_f4 - .L_op_unused_f4) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f5: /* 0xf5 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_unused_f5 - sub lr, lr, #(.L_ALT_op_unused_f5 - .L_op_unused_f5) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f6: /* 0xf6 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_unused_f6 - sub lr, lr, #(.L_ALT_op_unused_f6 - .L_op_unused_f6) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f7: /* 0xf7 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_unused_f7 - sub lr, lr, #(.L_ALT_op_unused_f7 - .L_op_unused_f7) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f8: /* 0xf8 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_unused_f8 - sub lr, lr, #(.L_ALT_op_unused_f8 - .L_op_unused_f8) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f9: /* 0xf9 */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_unused_f9 - sub lr, lr, #(.L_ALT_op_unused_f9 - .L_op_unused_f9) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_polymorphic: /* 0xfa */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_invoke_polymorphic - sub lr, lr, #(.L_ALT_op_invoke_polymorphic - .L_op_invoke_polymorphic) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_polymorphic_range: /* 0xfb */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_invoke_polymorphic_range - sub lr, lr, #(.L_ALT_op_invoke_polymorphic_range - .L_op_invoke_polymorphic_range) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_custom: /* 0xfc */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_invoke_custom - sub lr, lr, #(.L_ALT_op_invoke_custom - .L_op_invoke_custom) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_custom_range: /* 0xfd */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_invoke_custom_range - sub lr, lr, #(.L_ALT_op_invoke_custom_range - .L_op_invoke_custom_range) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_method_handle: /* 0xfe */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_const_method_handle - sub lr, lr, #(.L_ALT_op_const_method_handle - .L_op_const_method_handle) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_method_type: /* 0xff */ -/* File: arm/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. - adr lr, .L_ALT_op_const_method_type - sub lr, lr, #(.L_ALT_op_const_method_type - .L_op_const_method_type) @ Addr of primary handler. - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rPC - b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. - - .balign 128 -/* File: arm/instruction_end_alt.S */ - - .type artMterpAsmAltInstructionEnd, #object - .hidden artMterpAsmAltInstructionEnd - .global artMterpAsmAltInstructionEnd -artMterpAsmAltInstructionEnd: - -/* File: arm/footer.S */ -/* - * =========================================================================== - * Common subroutines and data - * =========================================================================== - */ - - .text - .align 2 - -/* - * We've detected a condition that will result in an exception, but the exception - * has not yet been thrown. Just bail out to the reference interpreter to deal with it. - * TUNING: for consistency, we may want to just go ahead and handle these here. - */ -common_errDivideByZero: - EXPORT_PC -#if MTERP_LOGGING - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - bl MterpLogDivideByZeroException -#endif - b MterpCommonFallback - -common_errArrayIndex: - EXPORT_PC -#if MTERP_LOGGING - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - bl MterpLogArrayIndexException -#endif - b MterpCommonFallback - -common_errNegativeArraySize: - EXPORT_PC -#if MTERP_LOGGING - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - bl MterpLogNegativeArraySizeException -#endif - b MterpCommonFallback - -common_errNoSuchMethod: - EXPORT_PC -#if MTERP_LOGGING - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - bl MterpLogNoSuchMethodException -#endif - b MterpCommonFallback - -common_errNullObject: - EXPORT_PC -#if MTERP_LOGGING - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - bl MterpLogNullObjectException -#endif - b MterpCommonFallback - -common_exceptionThrown: - EXPORT_PC -#if MTERP_LOGGING - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - bl MterpLogExceptionThrownException -#endif - b MterpCommonFallback - -MterpSuspendFallback: - EXPORT_PC -#if MTERP_LOGGING - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - ldr r2, [rSELF, #THREAD_FLAGS_OFFSET] - bl MterpLogSuspendFallback -#endif - b MterpCommonFallback - -/* - * If we're here, something is out of the ordinary. If there is a pending - * exception, handle it. Otherwise, roll back and retry with the reference - * interpreter. - */ -MterpPossibleException: - ldr r0, [rSELF, #THREAD_EXCEPTION_OFFSET] - cmp r0, #0 @ Exception pending? - beq MterpFallback @ If not, fall back to reference interpreter. - /* intentional fallthrough - handle pending exception. */ -/* - * On return from a runtime helper routine, we've found a pending exception. - * Can we handle it here - or need to bail out to caller? - * - */ -MterpException: - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - bl MterpHandleException @ (self, shadow_frame) - cmp r0, #0 - beq MterpExceptionReturn @ no local catch, back to caller. - ldr r0, [rFP, #OFF_FP_DEX_INSTRUCTIONS] - ldr r1, [rFP, #OFF_FP_DEX_PC] - ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] - add rPC, r0, r1, lsl #1 @ generate new dex_pc_ptr - /* Do we need to switch interpreters? */ - bl MterpShouldSwitchInterpreters - cmp r0, #0 - bne MterpFallback - /* resume execution at catch block */ - EXPORT_PC - FETCH_INST - GET_INST_OPCODE ip - GOTO_OPCODE ip - /* NOTE: no fallthrough */ - -/* - * Common handling for branches with support for Jit profiling. - * On entry: - * rINST <= signed offset - * rPROFILE <= signed hotness countdown (expanded to 32 bits) - * condition bits <= set to establish sign of offset (use "NoFlags" entry if not) - * - * We have quite a few different cases for branch profiling, OSR detection and - * suspend check support here. - * - * Taken backward branches: - * If profiling active, do hotness countdown and report if we hit zero. - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * Is there a pending suspend request? If so, suspend. - * - * Taken forward branches and not-taken backward branches: - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * - * Our most common case is expected to be a taken backward branch with active jit profiling, - * but no full OSR check and no pending suspend request. - * Next most common case is not-taken branch with no full OSR check. - * - */ -MterpCommonTakenBranchNoFlags: - cmp rINST, #0 -MterpCommonTakenBranch: - bgt .L_forward_branch @ don't add forward branches to hotness -/* - * We need to subtract 1 from positive values and we should not see 0 here, - * so we may use the result of the comparison with -1. - */ -#if JIT_CHECK_OSR != -1 -# error "JIT_CHECK_OSR must be -1." -#endif - cmp rPROFILE, #JIT_CHECK_OSR - beq .L_osr_check - subsgt rPROFILE, #1 - beq .L_add_batch @ counted down to zero - report -.L_resume_backward_branch: - ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] - REFRESH_IBASE - add r2, rINST, rINST @ r2<- byte offset - FETCH_ADVANCE_INST_RB r2 @ update rPC, load rINST - ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - bne .L_suspend_request_pending - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -.L_suspend_request_pending: - EXPORT_PC - mov r0, rSELF - bl MterpSuspendCheck @ (self) - cmp r0, #0 - bne MterpFallback - REFRESH_IBASE @ might have changed during suspend - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -.L_no_count_backwards: - cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? - bne .L_resume_backward_branch -.L_osr_check: - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rINST - EXPORT_PC - bl MterpMaybeDoOnStackReplacement @ (self, shadow_frame, offset) - cmp r0, #0 - bne MterpOnStackReplacement - b .L_resume_backward_branch - -.L_forward_branch: - cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? - beq .L_check_osr_forward -.L_resume_forward_branch: - add r2, rINST, rINST @ r2<- byte offset - FETCH_ADVANCE_INST_RB r2 @ update rPC, load rINST - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -.L_check_osr_forward: - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rINST - EXPORT_PC - bl MterpMaybeDoOnStackReplacement @ (self, shadow_frame, offset) - cmp r0, #0 - bne MterpOnStackReplacement - b .L_resume_forward_branch - -.L_add_batch: - add r1, rFP, #OFF_FP_SHADOWFRAME - strh rPROFILE, [r1, #SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET] - ldr r0, [rFP, #OFF_FP_METHOD] - mov r2, rSELF - bl MterpAddHotnessBatch @ (method, shadow_frame, self) - mov rPROFILE, r0 @ restore new hotness countdown to rPROFILE - b .L_no_count_backwards - -/* - * Entered from the conditional branch handlers when OSR check request active on - * not-taken path. All Dalvik not-taken conditional branch offsets are 2. - */ -.L_check_not_taken_osr: - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, #2 - EXPORT_PC - bl MterpMaybeDoOnStackReplacement @ (self, shadow_frame, offset) - cmp r0, #0 - bne MterpOnStackReplacement - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip @ extract opcode from rINST - GOTO_OPCODE ip @ jump to next instruction - -/* - * On-stack replacement has happened, and now we've returned from the compiled method. - */ -MterpOnStackReplacement: -#if MTERP_LOGGING - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rINST - bl MterpLogOSR -#endif - mov r0, #1 @ Signal normal return - b MterpDone - -/* - * Bail out to reference interpreter. - */ -MterpFallback: - EXPORT_PC -#if MTERP_LOGGING - mov r0, rSELF - add r1, rFP, #OFF_FP_SHADOWFRAME - bl MterpLogFallback -#endif -MterpCommonFallback: - mov r0, #0 @ signal retry with reference interpreter. - b MterpDone - -/* - * We pushed some registers on the stack in ExecuteMterpImpl, then saved - * SP and LR. Here we restore SP, restore the registers, and then restore - * LR to PC. - * - * On entry: - * uint32_t* rFP (should still be live, pointer to base of vregs) - */ -MterpExceptionReturn: - mov r0, #1 @ signal return to caller. - b MterpDone -MterpReturn: - ldr r2, [rFP, #OFF_FP_RESULT_REGISTER] - str r0, [r2] - str r1, [r2, #4] - mov r0, #1 @ signal return to caller. -MterpDone: -/* - * At this point, we expect rPROFILE to be non-zero. If negative, hotness is disabled or we're - * checking for OSR. If greater than zero, we might have unreported hotness to register - * (the difference between the ending rPROFILE and the cached hotness counter). rPROFILE - * should only reach zero immediately after a hotness decrement, and is then reset to either - * a negative special state or the new non-zero countdown value. - */ - cmp rPROFILE, #0 - bgt MterpProfileActive @ if > 0, we may have some counts to report. - ldmfd sp!, {r3-r10,fp,pc} @ restore 10 regs and return - -MterpProfileActive: - mov rINST, r0 @ stash return value - /* Report cached hotness counts */ - ldr r0, [rFP, #OFF_FP_METHOD] - add r1, rFP, #OFF_FP_SHADOWFRAME - mov r2, rSELF - strh rPROFILE, [r1, #SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET] - bl MterpAddHotnessBatch @ (method, shadow_frame, self) - mov r0, rINST @ restore return value - ldmfd sp!, {r3-r10,fp,pc} @ restore 10 regs and return - - END ExecuteMterpImpl - - diff --git a/runtime/interpreter/mterp/out/mterp_arm64.S b/runtime/interpreter/mterp/out/mterp_arm64.S deleted file mode 100644 index fd60c95a373cddd6cba58c62df96f24d3423dfb0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/out/mterp_arm64.S +++ /dev/null @@ -1,11662 +0,0 @@ -/* - * This file was generated automatically by gen-mterp.py for 'arm64'. - * - * --> DO NOT EDIT <-- - */ - -/* File: arm64/header.S */ -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - Art assembly interpreter notes: - - First validate assembly code by implementing ExecuteXXXImpl() style body (doesn't - handle invoke, allows higher-level code to create frame & shadow frame. - - Once that's working, support direct entry code & eliminate shadow frame (and - excess locals allocation. - - Some (hopefully) temporary ugliness. We'll treat xFP as pointing to the - base of the vreg array within the shadow frame. Access the other fields, - dex_pc_, method_ and number_of_vregs_ via negative offsets. For now, we'll continue - the shadow frame mechanism of double-storing object references - via xFP & - number_of_vregs_. - - */ - -/* -ARM64 Runtime register usage conventions. - - r0 : w0 is 32-bit return register and x0 is 64-bit. - r0-r7 : Argument registers. - r8-r15 : Caller save registers (used as temporary registers). - r16-r17: Also known as ip0-ip1, respectively. Used as scratch registers by - the linker, by the trampolines and other stubs (the backend uses - these as temporary registers). - r18 : Caller save register (used as temporary register). - r19 : Pointer to thread-local storage. - r20-r29: Callee save registers. - r30 : (lr) is reserved (the link register). - rsp : (sp) is reserved (the stack pointer). - rzr : (zr) is reserved (the zero register). - - Floating-point registers - v0-v31 - - v0 : s0 is return register for singles (32-bit) and d0 for doubles (64-bit). - This is analogous to the C/C++ (hard-float) calling convention. - v0-v7 : Floating-point argument registers in both Dalvik and C/C++ conventions. - Also used as temporary and codegen scratch registers. - - v0-v7 and v16-v31 : trashed across C calls. - v8-v15 : bottom 64-bits preserved across C calls (d8-d15 are preserved). - - v16-v31: Used as codegen temp/scratch. - v8-v15 : Can be used for promotion. - - Must maintain 16-byte stack alignment. - -Mterp notes: - -The following registers have fixed assignments: - - reg nick purpose - x20 xPC interpreted program counter, used for fetching instructions - x21 xFP interpreted frame pointer, used for accessing locals and args - x22 xSELF self (Thread) pointer - x23 xINST first 16-bit code unit of current instruction - x24 xIBASE interpreted instruction base pointer, used for computed goto - x25 xREFS base of object references in shadow frame (ideally, we'll get rid of this later). - x26 wPROFILE jit profile hotness countdown - x16 ip scratch reg - x17 ip2 scratch reg (used by macros) - -Macros are provided for common operations. They MUST NOT alter unspecified registers or condition -codes. -*/ - -/* - * This is a #include, not a %include, because we want the C pre-processor - * to expand the macros into assembler assignment statements. - */ -#include "asm_support.h" -#include "interpreter/cfi_asm_support.h" - -#define MTERP_PROFILE_BRANCHES 1 -#define MTERP_LOGGING 0 - -/* During bringup, we'll use the shadow frame model instead of xFP */ -/* single-purpose registers, given names for clarity */ -#define xPC x20 -#define CFI_DEX 20 // DWARF register number of the register holding dex-pc (xPC). -#define CFI_TMP 0 // DWARF register number of the first argument register (r0). -#define xFP x21 -#define xSELF x22 -#define xINST x23 -#define wINST w23 -#define xIBASE x24 -#define xREFS x25 -#define wPROFILE w26 -#define xPROFILE x26 -#define ip x16 -#define ip2 x17 - -/* - * Instead of holding a pointer to the shadow frame, we keep xFP at the base of the vregs. So, - * to access other shadow frame fields, we need to use a backwards offset. Define those here. - */ -#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) -#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) -#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) -#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) -#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) -#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) -#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) -#define OFF_FP_DEX_INSTRUCTIONS OFF_FP(SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET) -#define OFF_FP_SHADOWFRAME OFF_FP(0) - -/* - * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must - * be done *before* something throws. - * - * It's okay to do this more than once. - * - * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped - * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction - * offset into the code_items_[] array. For effiency, we will "export" the - * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC - * to convert to a dex pc when needed. - */ -.macro EXPORT_PC - str xPC, [xFP, #OFF_FP_DEX_PC_PTR] -.endm - -/* - * Fetch the next instruction from xPC into wINST. Does not advance xPC. - */ -.macro FETCH_INST - ldrh wINST, [xPC] -.endm - -/* - * Fetch the next instruction from the specified offset. Advances xPC - * to point to the next instruction. "_count" is in 16-bit code units. - * - * Because of the limited size of immediate constants on ARM, this is only - * suitable for small forward movements (i.e. don't try to implement "goto" - * with this). - * - * This must come AFTER anything that can throw an exception, or the - * exception catch may miss. (This also implies that it must come after - * EXPORT_PC.) - */ -.macro FETCH_ADVANCE_INST count - ldrh wINST, [xPC, #((\count)*2)]! -.endm - -/* - * The operation performed here is similar to FETCH_ADVANCE_INST, except the - * src and dest registers are parameterized (not hard-wired to xPC and xINST). - */ -.macro PREFETCH_ADVANCE_INST dreg, sreg, count - ldrh \dreg, [\sreg, #((\count)*2)]! -.endm - -/* - * Similar to FETCH_ADVANCE_INST, but does not update xPC. Used to load - * xINST ahead of possible exception point. Be sure to manually advance xPC - * later. - */ -.macro PREFETCH_INST count - ldrh wINST, [xPC, #((\count)*2)] -.endm - -/* Advance xPC by some number of code units. */ -.macro ADVANCE count - add xPC, xPC, #((\count)*2) -.endm - -/* - * Fetch the next instruction from an offset specified by _reg and advance xPC. - * xPC to point to the next instruction. "_reg" must specify the distance - * in bytes, *not* 16-bit code units, and may be a signed value. Must not set flags. - * - */ -.macro FETCH_ADVANCE_INST_RB reg - add xPC, xPC, \reg, sxtw - ldrh wINST, [xPC] -.endm - -/* - * Fetch a half-word code unit from an offset past the current PC. The - * "_count" value is in 16-bit code units. Does not advance xPC. - * - * The "_S" variant works the same but treats the value as signed. - */ -.macro FETCH reg, count - ldrh \reg, [xPC, #((\count)*2)] -.endm - -.macro FETCH_S reg, count - ldrsh \reg, [xPC, #((\count)*2)] -.endm - -/* - * Fetch one byte from an offset past the current PC. Pass in the same - * "_count" as you would for FETCH, and an additional 0/1 indicating which - * byte of the halfword you want (lo/hi). - */ -.macro FETCH_B reg, count, byte - ldrb \reg, [xPC, #((\count)*2+(\byte))] -.endm - -/* - * Put the instruction's opcode field into the specified register. - */ -.macro GET_INST_OPCODE reg - and \reg, xINST, #255 -.endm - -/* - * Put the prefetched instruction's opcode field into the specified register. - */ -.macro GET_PREFETCHED_OPCODE oreg, ireg - and \oreg, \ireg, #255 -.endm - -/* - * Begin executing the opcode in _reg. Clobbers reg - */ - -.macro GOTO_OPCODE reg - add \reg, xIBASE, \reg, lsl #7 - br \reg -.endm -.macro GOTO_OPCODE_BASE base,reg - add \reg, \base, \reg, lsl #7 - br \reg -.endm - -/* - * Get/set the 32-bit value from a Dalvik register. - */ -.macro GET_VREG reg, vreg - ldr \reg, [xFP, \vreg, uxtw #2] -.endm -.macro SET_VREG reg, vreg - str \reg, [xFP, \vreg, uxtw #2] - str wzr, [xREFS, \vreg, uxtw #2] -.endm -.macro SET_VREG_OBJECT reg, vreg, tmpreg - str \reg, [xFP, \vreg, uxtw #2] - str \reg, [xREFS, \vreg, uxtw #2] -.endm - -/* - * Get/set the 64-bit value from a Dalvik register. - * TUNING: can we do better here? - */ -.macro GET_VREG_WIDE reg, vreg - add ip2, xFP, \vreg, lsl #2 - ldr \reg, [ip2] -.endm -.macro SET_VREG_WIDE reg, vreg - add ip2, xFP, \vreg, lsl #2 - str \reg, [ip2] - add ip2, xREFS, \vreg, lsl #2 - str xzr, [ip2] -.endm - -/* - * Get the 32-bit value from a Dalvik register and sign-extend to 64-bit. - * Used to avoid an extra instruction in int-to-long. - */ -.macro GET_VREG_S reg, vreg - ldrsw \reg, [xFP, \vreg, uxtw #2] -.endm - -/* - * Convert a virtual register index into an address. - */ -.macro VREG_INDEX_TO_ADDR reg, vreg - add \reg, xFP, \vreg, lsl #2 /* WARNING: handle shadow frame vreg zero if store */ -.endm - -/* - * Refresh handler table. - */ -.macro REFRESH_IBASE - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] -.endm - -/* - * Save two registers to the stack. - */ -.macro SAVE_TWO_REGS reg1, reg2, offset - stp \reg1, \reg2, [sp, #(\offset)] - .cfi_rel_offset \reg1, (\offset) - .cfi_rel_offset \reg2, (\offset) + 8 -.endm - -/* - * Restore two registers from the stack. - */ -.macro RESTORE_TWO_REGS reg1, reg2, offset - ldp \reg1, \reg2, [sp, #(\offset)] - .cfi_restore \reg1 - .cfi_restore \reg2 -.endm - -/* - * Increase frame size and save two registers to the bottom of the stack. - */ -.macro SAVE_TWO_REGS_INCREASE_FRAME reg1, reg2, frame_adjustment - stp \reg1, \reg2, [sp, #-(\frame_adjustment)]! - .cfi_adjust_cfa_offset (\frame_adjustment) - .cfi_rel_offset \reg1, 0 - .cfi_rel_offset \reg2, 8 -.endm - -/* - * Restore two registers from the bottom of the stack and decrease frame size. - */ -.macro RESTORE_TWO_REGS_DECREASE_FRAME reg1, reg2, frame_adjustment - ldp \reg1, \reg2, [sp], #(\frame_adjustment) - .cfi_restore \reg1 - .cfi_restore \reg2 - .cfi_adjust_cfa_offset -(\frame_adjustment) -.endm - -/* - * cfi support macros. - */ -.macro ENTRY name - .type \name, #function - .hidden \name // Hide this as a global symbol, so we do not incur plt calls. - .global \name - /* Cache alignment for function entry */ - .balign 16 -\name: - .cfi_startproc -.endm - -.macro END name - .cfi_endproc - .size \name, .-\name -.endm - -/* File: arm64/entry.S */ -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - .text - -/* - * Interpreter entry point. - * On entry: - * x0 Thread* self/ - * x1 insns_ - * x2 ShadowFrame - * x3 JValue* result_register - * - */ -ENTRY ExecuteMterpImpl - SAVE_TWO_REGS_INCREASE_FRAME xPROFILE, x27, 80 - SAVE_TWO_REGS xIBASE, xREFS, 16 - SAVE_TWO_REGS xSELF, xINST, 32 - SAVE_TWO_REGS xPC, xFP, 48 - SAVE_TWO_REGS fp, lr, 64 - add fp, sp, #64 - - /* Remember the return register */ - str x3, [x2, #SHADOWFRAME_RESULT_REGISTER_OFFSET] - - /* Remember the dex instruction pointer */ - str x1, [x2, #SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET] - - /* set up "named" registers */ - mov xSELF, x0 - ldr w0, [x2, #SHADOWFRAME_NUMBER_OF_VREGS_OFFSET] - add xFP, x2, #SHADOWFRAME_VREGS_OFFSET // point to vregs. - add xREFS, xFP, w0, lsl #2 // point to reference array in shadow frame - ldr w0, [x2, #SHADOWFRAME_DEX_PC_OFFSET] // Get starting dex_pc. - add xPC, x1, w0, lsl #1 // Create direct pointer to 1st dex opcode - CFI_DEFINE_DEX_PC_WITH_OFFSET(CFI_TMP, CFI_DEX, 0) - EXPORT_PC - - /* Starting ibase */ - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] - - /* Set up for backwards branches & osr profiling */ - ldr x0, [xFP, #OFF_FP_METHOD] - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xSELF - bl MterpSetUpHotnessCountdown - mov wPROFILE, w0 // Starting hotness countdown to xPROFILE - - /* start executing the instruction at rPC */ - FETCH_INST // load wINST from rPC - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - /* NOTE: no fallthrough */ - -/* File: arm64/instruction_start.S */ - - .type artMterpAsmInstructionStart, #object - .hidden artMterpAsmInstructionStart - .global artMterpAsmInstructionStart -artMterpAsmInstructionStart = .L_op_nop - .text - -/* ------------------------------ */ - .balign 128 -.L_op_nop: /* 0x00 */ -/* File: arm64/op_nop.S */ - FETCH_ADVANCE_INST 1 // advance to next instr, load rINST - GET_INST_OPCODE ip // ip<- opcode from rINST - GOTO_OPCODE ip // execute it - -/* ------------------------------ */ - .balign 128 -.L_op_move: /* 0x01 */ -/* File: arm64/op_move.S */ - /* for move, move-object, long-to-int */ - /* op vA, vB */ - lsr w1, wINST, #12 // x1<- B from 15:12 - ubfx w0, wINST, #8, #4 // x0<- A from 11:8 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - GET_VREG w2, w1 // x2<- fp[B] - GET_INST_OPCODE ip // ip<- opcode from wINST - .if 0 - SET_VREG_OBJECT w2, w0 // fp[A]<- x2 - .else - SET_VREG w2, w0 // fp[A]<- x2 - .endif - GOTO_OPCODE ip // execute next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_from16: /* 0x02 */ -/* File: arm64/op_move_from16.S */ - /* for: move/from16, move-object/from16 */ - /* op vAA, vBBBB */ - FETCH w1, 1 // r1<- BBBB - lsr w0, wINST, #8 // r0<- AA - FETCH_ADVANCE_INST 2 // advance rPC, load wINST - GET_VREG w2, w1 // r2<- fp[BBBB] - GET_INST_OPCODE ip // extract opcode from wINST - .if 0 - SET_VREG_OBJECT w2, w0 // fp[AA]<- r2 - .else - SET_VREG w2, w0 // fp[AA]<- r2 - .endif - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_16: /* 0x03 */ -/* File: arm64/op_move_16.S */ - /* for: move/16, move-object/16 */ - /* op vAAAA, vBBBB */ - FETCH w1, 2 // w1<- BBBB - FETCH w0, 1 // w0<- AAAA - FETCH_ADVANCE_INST 3 // advance xPC, load xINST - GET_VREG w2, w1 // w2<- fp[BBBB] - GET_INST_OPCODE ip // extract opcode from xINST - .if 0 - SET_VREG_OBJECT w2, w0 // fp[AAAA]<- w2 - .else - SET_VREG w2, w0 // fp[AAAA]<- w2 - .endif - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_wide: /* 0x04 */ -/* File: arm64/op_move_wide.S */ - /* move-wide vA, vB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - lsr w3, wINST, #12 // w3<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG_WIDE x3, w3 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG_WIDE x3, w2 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_wide_from16: /* 0x05 */ -/* File: arm64/op_move_wide_from16.S */ - /* move-wide/from16 vAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - FETCH w3, 1 // w3<- BBBB - lsr w2, wINST, #8 // w2<- AA - GET_VREG_WIDE x3, w3 - FETCH_ADVANCE_INST 2 // advance rPC, load wINST - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG_WIDE x3, w2 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_wide_16: /* 0x06 */ -/* File: arm64/op_move_wide_16.S */ - /* move-wide/16 vAAAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - FETCH w3, 2 // w3<- BBBB - FETCH w2, 1 // w2<- AAAA - GET_VREG_WIDE x3, w3 - FETCH_ADVANCE_INST 3 // advance rPC, load rINST - SET_VREG_WIDE x3, w2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_object: /* 0x07 */ -/* File: arm64/op_move_object.S */ -/* File: arm64/op_move.S */ - /* for move, move-object, long-to-int */ - /* op vA, vB */ - lsr w1, wINST, #12 // x1<- B from 15:12 - ubfx w0, wINST, #8, #4 // x0<- A from 11:8 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - GET_VREG w2, w1 // x2<- fp[B] - GET_INST_OPCODE ip // ip<- opcode from wINST - .if 1 - SET_VREG_OBJECT w2, w0 // fp[A]<- x2 - .else - SET_VREG w2, w0 // fp[A]<- x2 - .endif - GOTO_OPCODE ip // execute next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_move_object_from16: /* 0x08 */ -/* File: arm64/op_move_object_from16.S */ -/* File: arm64/op_move_from16.S */ - /* for: move/from16, move-object/from16 */ - /* op vAA, vBBBB */ - FETCH w1, 1 // r1<- BBBB - lsr w0, wINST, #8 // r0<- AA - FETCH_ADVANCE_INST 2 // advance rPC, load wINST - GET_VREG w2, w1 // r2<- fp[BBBB] - GET_INST_OPCODE ip // extract opcode from wINST - .if 1 - SET_VREG_OBJECT w2, w0 // fp[AA]<- r2 - .else - SET_VREG w2, w0 // fp[AA]<- r2 - .endif - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_move_object_16: /* 0x09 */ -/* File: arm64/op_move_object_16.S */ -/* File: arm64/op_move_16.S */ - /* for: move/16, move-object/16 */ - /* op vAAAA, vBBBB */ - FETCH w1, 2 // w1<- BBBB - FETCH w0, 1 // w0<- AAAA - FETCH_ADVANCE_INST 3 // advance xPC, load xINST - GET_VREG w2, w1 // w2<- fp[BBBB] - GET_INST_OPCODE ip // extract opcode from xINST - .if 1 - SET_VREG_OBJECT w2, w0 // fp[AAAA]<- w2 - .else - SET_VREG w2, w0 // fp[AAAA]<- w2 - .endif - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_move_result: /* 0x0a */ -/* File: arm64/op_move_result.S */ - /* for: move-result, move-result-object */ - /* op vAA */ - lsr w2, wINST, #8 // r2<- AA - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - ldr x0, [xFP, #OFF_FP_RESULT_REGISTER] // get pointer to result JType. - ldr w0, [x0] // r0 <- result.i. - GET_INST_OPCODE ip // extract opcode from wINST - .if 0 - SET_VREG_OBJECT w0, w2, w1 // fp[AA]<- r0 - .else - SET_VREG w0, w2 // fp[AA]<- r0 - .endif - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_result_wide: /* 0x0b */ -/* File: arm64/op_move_result_wide.S */ - /* for: move-result-wide */ - /* op vAA */ - lsr w2, wINST, #8 // r2<- AA - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - ldr x0, [xFP, #OFF_FP_RESULT_REGISTER] // get pointer to result JType. - ldr x0, [x0] // r0 <- result.i. - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG_WIDE x0, x2 // fp[AA]<- r0 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_result_object: /* 0x0c */ -/* File: arm64/op_move_result_object.S */ -/* File: arm64/op_move_result.S */ - /* for: move-result, move-result-object */ - /* op vAA */ - lsr w2, wINST, #8 // r2<- AA - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - ldr x0, [xFP, #OFF_FP_RESULT_REGISTER] // get pointer to result JType. - ldr w0, [x0] // r0 <- result.i. - GET_INST_OPCODE ip // extract opcode from wINST - .if 1 - SET_VREG_OBJECT w0, w2, w1 // fp[AA]<- r0 - .else - SET_VREG w0, w2 // fp[AA]<- r0 - .endif - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_move_exception: /* 0x0d */ -/* File: arm64/op_move_exception.S */ - /* move-exception vAA */ - lsr w2, wINST, #8 // w2<- AA - ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] - mov x1, #0 // w1<- 0 - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - SET_VREG_OBJECT w3, w2 // fp[AA]<- exception obj - GET_INST_OPCODE ip // extract opcode from rINST - str x1, [xSELF, #THREAD_EXCEPTION_OFFSET] // clear exception - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_return_void: /* 0x0e */ -/* File: arm64/op_return_void.S */ - .extern MterpThreadFenceForConstructor - bl MterpThreadFenceForConstructor - ldr w7, [xSELF, #THREAD_FLAGS_OFFSET] - mov x0, xSELF - ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - b.ne .Lop_return_void_check -.Lop_return_void_return: - mov x0, #0 - b MterpReturn -.Lop_return_void_check: - bl MterpSuspendCheck // (self) - b .Lop_return_void_return - -/* ------------------------------ */ - .balign 128 -.L_op_return: /* 0x0f */ -/* File: arm64/op_return.S */ - /* - * Return a 32-bit value. - * - * for: return, return-object - */ - /* op vAA */ - .extern MterpThreadFenceForConstructor - bl MterpThreadFenceForConstructor - ldr w7, [xSELF, #THREAD_FLAGS_OFFSET] - mov x0, xSELF - ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - b.ne .Lop_return_check -.Lop_return_return: - lsr w2, wINST, #8 // r2<- AA - GET_VREG w0, w2 // r0<- vAA - b MterpReturn -.Lop_return_check: - bl MterpSuspendCheck // (self) - b .Lop_return_return - -/* ------------------------------ */ - .balign 128 -.L_op_return_wide: /* 0x10 */ -/* File: arm64/op_return_wide.S */ - /* - * Return a 64-bit value. - */ - /* return-wide vAA */ - /* op vAA */ - .extern MterpThreadFenceForConstructor - bl MterpThreadFenceForConstructor - ldr w7, [xSELF, #THREAD_FLAGS_OFFSET] - mov x0, xSELF - ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - b.ne .Lop_return_wide_check -.Lop_return_wide_return: - lsr w2, wINST, #8 // w2<- AA - GET_VREG_WIDE x0, w2 // x0<- vAA - b MterpReturn -.Lop_return_wide_check: - bl MterpSuspendCheck // (self) - b .Lop_return_wide_return - -/* ------------------------------ */ - .balign 128 -.L_op_return_object: /* 0x11 */ -/* File: arm64/op_return_object.S */ -/* File: arm64/op_return.S */ - /* - * Return a 32-bit value. - * - * for: return, return-object - */ - /* op vAA */ - .extern MterpThreadFenceForConstructor - bl MterpThreadFenceForConstructor - ldr w7, [xSELF, #THREAD_FLAGS_OFFSET] - mov x0, xSELF - ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - b.ne .Lop_return_object_check -.Lop_return_object_return: - lsr w2, wINST, #8 // r2<- AA - GET_VREG w0, w2 // r0<- vAA - b MterpReturn -.Lop_return_object_check: - bl MterpSuspendCheck // (self) - b .Lop_return_object_return - - -/* ------------------------------ */ - .balign 128 -.L_op_const_4: /* 0x12 */ -/* File: arm64/op_const_4.S */ - /* const/4 vA, #+B */ - sbfx w1, wINST, #12, #4 // w1<- sssssssB - ubfx w0, wINST, #8, #4 // w0<- A - FETCH_ADVANCE_INST 1 // advance xPC, load wINST - GET_INST_OPCODE ip // ip<- opcode from xINST - SET_VREG w1, w0 // fp[A]<- w1 - GOTO_OPCODE ip // execute next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_16: /* 0x13 */ -/* File: arm64/op_const_16.S */ - /* const/16 vAA, #+BBBB */ - FETCH_S w0, 1 // w0<- ssssBBBB (sign-extended) - lsr w3, wINST, #8 // w3<- AA - FETCH_ADVANCE_INST 2 // advance xPC, load wINST - SET_VREG w0, w3 // vAA<- w0 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const: /* 0x14 */ -/* File: arm64/op_const.S */ - /* const vAA, #+BBBBbbbb */ - lsr w3, wINST, #8 // w3<- AA - FETCH w0, 1 // w0<- bbbb (low - FETCH w1, 2 // w1<- BBBB (high - FETCH_ADVANCE_INST 3 // advance rPC, load wINST - orr w0, w0, w1, lsl #16 // w0<- BBBBbbbb - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG w0, w3 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_high16: /* 0x15 */ -/* File: arm64/op_const_high16.S */ - /* const/high16 vAA, #+BBBB0000 */ - FETCH w0, 1 // r0<- 0000BBBB (zero-extended) - lsr w3, wINST, #8 // r3<- AA - lsl w0, w0, #16 // r0<- BBBB0000 - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - SET_VREG w0, w3 // vAA<- r0 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_wide_16: /* 0x16 */ -/* File: arm64/op_const_wide_16.S */ - /* const-wide/16 vAA, #+BBBB */ - FETCH_S x0, 1 // x0<- ssssssssssssBBBB (sign-extended) - lsr w3, wINST, #8 // w3<- AA - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w3 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_wide_32: /* 0x17 */ -/* File: arm64/op_const_wide_32.S */ - /* const-wide/32 vAA, #+BBBBbbbb */ - FETCH w0, 1 // x0<- 000000000000bbbb (low) - lsr w3, wINST, #8 // w3<- AA - FETCH_S x2, 2 // x2<- ssssssssssssBBBB (high) - FETCH_ADVANCE_INST 3 // advance rPC, load wINST - GET_INST_OPCODE ip // extract opcode from wINST - orr x0, x0, x2, lsl #16 // x0<- ssssssssBBBBbbbb - SET_VREG_WIDE x0, w3 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_wide: /* 0x18 */ -/* File: arm64/op_const_wide.S */ - /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ - FETCH w0, 1 // w0<- bbbb (low) - FETCH w1, 2 // w1<- BBBB (low middle) - FETCH w2, 3 // w2<- hhhh (high middle) - FETCH w3, 4 // w3<- HHHH (high) - lsr w4, wINST, #8 // r4<- AA - FETCH_ADVANCE_INST 5 // advance rPC, load wINST - GET_INST_OPCODE ip // extract opcode from wINST - orr w0, w0, w1, lsl #16 // w0<- BBBBbbbb - orr x0, x0, x2, lsl #32 // w0<- hhhhBBBBbbbb - orr x0, x0, x3, lsl #48 // w0<- HHHHhhhhBBBBbbbb - SET_VREG_WIDE x0, w4 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_wide_high16: /* 0x19 */ -/* File: arm64/op_const_wide_high16.S */ - /* const-wide/high16 vAA, #+BBBB000000000000 */ - FETCH w0, 1 // w0<- 0000BBBB (zero-extended) - lsr w1, wINST, #8 // w1<- AA - FETCH_ADVANCE_INST 2 // advance rPC, load wINST - lsl x0, x0, #48 - SET_VREG_WIDE x0, w1 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_string: /* 0x1a */ -/* File: arm64/op_const_string.S */ -/* File: arm64/const.S */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstString - EXPORT_PC - FETCH w0, 1 // w0<- BBBB - lsr w1, wINST, #8 // w1<- AA - add x2, xFP, #OFF_FP_SHADOWFRAME - mov x3, xSELF - bl MterpConstString // (index, tgt_reg, shadow_frame, self) - PREFETCH_INST 2 // load rINST - cbnz w0, MterpPossibleException // let reference interpreter deal with it. - ADVANCE 2 // advance rPC - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_const_string_jumbo: /* 0x1b */ -/* File: arm64/op_const_string_jumbo.S */ - /* const/string vAA, String//BBBBBBBB */ - EXPORT_PC - FETCH w0, 1 // w0<- bbbb (low - FETCH w2, 2 // w2<- BBBB (high - lsr w1, wINST, #8 // w1<- AA - orr w0, w0, w2, lsl #16 // w1<- BBBBbbbb - add x2, xFP, #OFF_FP_SHADOWFRAME - mov x3, xSELF - bl MterpConstString // (index, tgt_reg, shadow_frame, self) - PREFETCH_INST 3 // advance rPC - cbnz w0, MterpPossibleException // let reference interpreter deal with it. - ADVANCE 3 // advance rPC - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_class: /* 0x1c */ -/* File: arm64/op_const_class.S */ -/* File: arm64/const.S */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstClass - EXPORT_PC - FETCH w0, 1 // w0<- BBBB - lsr w1, wINST, #8 // w1<- AA - add x2, xFP, #OFF_FP_SHADOWFRAME - mov x3, xSELF - bl MterpConstClass // (index, tgt_reg, shadow_frame, self) - PREFETCH_INST 2 // load rINST - cbnz w0, MterpPossibleException // let reference interpreter deal with it. - ADVANCE 2 // advance rPC - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_monitor_enter: /* 0x1d */ -/* File: arm64/op_monitor_enter.S */ - /* - * Synchronize on an object. - */ - /* monitor-enter vAA */ - EXPORT_PC - lsr w2, wINST, #8 // w2<- AA - GET_VREG w0, w2 // w0<- vAA (object) - mov x1, xSELF // w1<- self - bl artLockObjectFromCode - cbnz w0, MterpException - FETCH_ADVANCE_INST 1 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_monitor_exit: /* 0x1e */ -/* File: arm64/op_monitor_exit.S */ - /* - * Unlock an object. - * - * Exceptions that occur when unlocking a monitor need to appear as - * if they happened at the following instruction. See the Dalvik - * instruction spec. - */ - /* monitor-exit vAA */ - EXPORT_PC - lsr w2, wINST, #8 // w2<- AA - GET_VREG w0, w2 // w0<- vAA (object) - mov x1, xSELF // w0<- self - bl artUnlockObjectFromCode // w0<- success for unlock(self, obj) - cbnz w0, MterpException - FETCH_ADVANCE_INST 1 // before throw: advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_check_cast: /* 0x1f */ -/* File: arm64/op_check_cast.S */ - /* - * Check to see if a cast from one class to another is allowed. - */ - /* check-cast vAA, class//BBBB */ - EXPORT_PC - FETCH w0, 1 // w0<- BBBB - lsr w1, wINST, #8 // w1<- AA - VREG_INDEX_TO_ADDR x1, w1 // w1<- &object - ldr x2, [xFP, #OFF_FP_METHOD] // w2<- method - mov x3, xSELF // w3<- self - bl MterpCheckCast // (index, &obj, method, self) - PREFETCH_INST 2 - cbnz w0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_instance_of: /* 0x20 */ -/* File: arm64/op_instance_of.S */ - /* - * Check to see if an object reference is an instance of a class. - * - * Most common situation is a non-null object, being compared against - * an already-resolved class. - */ - /* instance-of vA, vB, class//CCCC */ - EXPORT_PC - FETCH w0, 1 // w0<- CCCC - lsr w1, wINST, #12 // w1<- B - VREG_INDEX_TO_ADDR x1, w1 // w1<- &object - ldr x2, [xFP, #OFF_FP_METHOD] // w2<- method - mov x3, xSELF // w3<- self - bl MterpInstanceOf // (index, &obj, method, self) - ldr x1, [xSELF, #THREAD_EXCEPTION_OFFSET] - ubfx w2, wINST, #8, #4 // w2<- A - PREFETCH_INST 2 - cbnz x1, MterpException - ADVANCE 2 // advance rPC - SET_VREG w0, w2 // vA<- w0 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_array_length: /* 0x21 */ -/* File: arm64/op_array_length.S */ - /* - * Return the length of an array. - */ - lsr w1, wINST, #12 // w1<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG w0, w1 // w0<- vB (object ref) - cbz w0, common_errNullObject // yup, fail - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- array length - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w3, w2 // vB<- length - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_new_instance: /* 0x22 */ -/* File: arm64/op_new_instance.S */ - /* - * Create a new instance of a class. - */ - /* new-instance vAA, class//BBBB */ - EXPORT_PC - add x0, xFP, #OFF_FP_SHADOWFRAME - mov x1, xSELF - mov w2, wINST - bl MterpNewInstance // (shadow_frame, self, inst_data) - cbz w0, MterpPossibleException - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_new_array: /* 0x23 */ -/* File: arm64/op_new_array.S */ - /* - * Allocate an array of objects, specified with the array class - * and a count. - * - * The verifier guarantees that this is an array class, so we don't - * check for it here. - */ - /* new-array vA, vB, class//CCCC */ - EXPORT_PC - add x0, xFP, #OFF_FP_SHADOWFRAME - mov x1, xPC - mov w2, wINST - mov x3, xSELF - bl MterpNewArray - cbz w0, MterpPossibleException - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_filled_new_array: /* 0x24 */ -/* File: arm64/op_filled_new_array.S */ - /* - * Create a new array with elements filled from registers. - * - * for: filled-new-array, filled-new-array/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class//CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, type//BBBB */ - .extern MterpFilledNewArray - EXPORT_PC - add x0, xFP, #OFF_FP_SHADOWFRAME - mov x1, xPC - mov x2, xSELF - bl MterpFilledNewArray - cbz w0, MterpPossibleException - FETCH_ADVANCE_INST 3 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_filled_new_array_range: /* 0x25 */ -/* File: arm64/op_filled_new_array_range.S */ -/* File: arm64/op_filled_new_array.S */ - /* - * Create a new array with elements filled from registers. - * - * for: filled-new-array, filled-new-array/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class//CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, type//BBBB */ - .extern MterpFilledNewArrayRange - EXPORT_PC - add x0, xFP, #OFF_FP_SHADOWFRAME - mov x1, xPC - mov x2, xSELF - bl MterpFilledNewArrayRange - cbz w0, MterpPossibleException - FETCH_ADVANCE_INST 3 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_fill_array_data: /* 0x26 */ -/* File: arm64/op_fill_array_data.S */ - /* fill-array-data vAA, +BBBBBBBB */ - EXPORT_PC - FETCH w0, 1 // x0<- 000000000000bbbb (lo) - FETCH_S x1, 2 // x1<- ssssssssssssBBBB (hi) - lsr w3, wINST, #8 // w3<- AA - orr x1, x0, x1, lsl #16 // x1<- ssssssssBBBBbbbb - GET_VREG w0, w3 // w0<- vAA (array object) - add x1, xPC, x1, lsl #1 // x1<- PC + ssssssssBBBBbbbb*2 (array data off.) - bl MterpFillArrayData // (obj, payload) - cbz w0, MterpPossibleException // exception? - FETCH_ADVANCE_INST 3 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_throw: /* 0x27 */ -/* File: arm64/op_throw.S */ - /* - * Throw an exception object in the current thread. - */ - /* throw vAA */ - EXPORT_PC - lsr w2, wINST, #8 // r2<- AA - GET_VREG w1, w2 // r1<- vAA (exception object) - cbz w1, common_errNullObject - str x1, [xSELF, #THREAD_EXCEPTION_OFFSET] // thread->exception<- obj - b MterpException - -/* ------------------------------ */ - .balign 128 -.L_op_goto: /* 0x28 */ -/* File: arm64/op_goto.S */ - /* - * Unconditional branch, 8-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto +AA */ - sbfx wINST, wINST, #8, #8 // wINST<- ssssssAA (sign-extended) - b MterpCommonTakenBranchNoFlags - -/* ------------------------------ */ - .balign 128 -.L_op_goto_16: /* 0x29 */ -/* File: arm64/op_goto_16.S */ - /* - * Unconditional branch, 16-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto/16 +AAAA */ - FETCH_S wINST, 1 // wINST<- ssssAAAA (sign-extended) - b MterpCommonTakenBranchNoFlags - -/* ------------------------------ */ - .balign 128 -.L_op_goto_32: /* 0x2a */ -/* File: arm64/op_goto_32.S */ - /* - * Unconditional branch, 32-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - * - * Unlike most opcodes, this one is allowed to branch to itself, so - * our "backward branch" test must be "<=0" instead of "<0". Because - * we need the V bit set, we'll use an adds to convert from Dalvik - * offset to byte offset. - */ - /* goto/32 +AAAAAAAA */ - FETCH w0, 1 // w0<- aaaa (lo) - FETCH w1, 2 // w1<- AAAA (hi) - orr wINST, w0, w1, lsl #16 // wINST<- AAAAaaaa - b MterpCommonTakenBranchNoFlags - -/* ------------------------------ */ - .balign 128 -.L_op_packed_switch: /* 0x2b */ -/* File: arm64/op_packed_switch.S */ - /* - * Handle a packed-switch or sparse-switch instruction. In both cases - * we decode it and hand it off to a helper function. - * - * We don't really expect backward branches in a switch statement, but - * they're perfectly legal, so we check for them here. - * - * for: packed-switch, sparse-switch - */ - /* op vAA, +BBBB */ - FETCH w0, 1 // x0<- 000000000000bbbb (lo) - FETCH_S x1, 2 // x1<- ssssssssssssBBBB (hi) - lsr w3, wINST, #8 // w3<- AA - orr x0, x0, x1, lsl #16 // x0<- ssssssssBBBBbbbb - GET_VREG w1, w3 // w1<- vAA - add x0, xPC, x0, lsl #1 // x0<- PC + ssssssssBBBBbbbb*2 - bl MterpDoPackedSwitch // w0<- code-unit branch offset - sxtw xINST, w0 - b MterpCommonTakenBranchNoFlags - -/* ------------------------------ */ - .balign 128 -.L_op_sparse_switch: /* 0x2c */ -/* File: arm64/op_sparse_switch.S */ -/* File: arm64/op_packed_switch.S */ - /* - * Handle a packed-switch or sparse-switch instruction. In both cases - * we decode it and hand it off to a helper function. - * - * We don't really expect backward branches in a switch statement, but - * they're perfectly legal, so we check for them here. - * - * for: packed-switch, sparse-switch - */ - /* op vAA, +BBBB */ - FETCH w0, 1 // x0<- 000000000000bbbb (lo) - FETCH_S x1, 2 // x1<- ssssssssssssBBBB (hi) - lsr w3, wINST, #8 // w3<- AA - orr x0, x0, x1, lsl #16 // x0<- ssssssssBBBBbbbb - GET_VREG w1, w3 // w1<- vAA - add x0, xPC, x0, lsl #1 // x0<- PC + ssssssssBBBBbbbb*2 - bl MterpDoSparseSwitch // w0<- code-unit branch offset - sxtw xINST, w0 - b MterpCommonTakenBranchNoFlags - - -/* ------------------------------ */ - .balign 128 -.L_op_cmpl_float: /* 0x2d */ -/* File: arm64/op_cmpl_float.S */ -/* File: arm64/fcmp.S */ - /* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - */ - /* op vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - and w2, w0, #255 // w2<- BB - lsr w3, w0, #8 // w3<- CC - GET_VREG s1, w2 - GET_VREG s2, w3 - fcmp s1, s2 - cset w0, ne - cneg w0, w0, lt - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w4 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_cmpg_float: /* 0x2e */ -/* File: arm64/op_cmpg_float.S */ -/* File: arm64/fcmp.S */ - /* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - */ - /* op vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - and w2, w0, #255 // w2<- BB - lsr w3, w0, #8 // w3<- CC - GET_VREG s1, w2 - GET_VREG s2, w3 - fcmp s1, s2 - cset w0, ne - cneg w0, w0, cc - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w4 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_cmpl_double: /* 0x2f */ -/* File: arm64/op_cmpl_double.S */ -/* File: arm64/fcmp.S */ - /* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - */ - /* op vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - and w2, w0, #255 // w2<- BB - lsr w3, w0, #8 // w3<- CC - GET_VREG_WIDE d1, w2 - GET_VREG_WIDE d2, w3 - fcmp d1, d2 - cset w0, ne - cneg w0, w0, lt - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w4 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_cmpg_double: /* 0x30 */ -/* File: arm64/op_cmpg_double.S */ -/* File: arm64/fcmp.S */ - /* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - */ - /* op vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - and w2, w0, #255 // w2<- BB - lsr w3, w0, #8 // w3<- CC - GET_VREG_WIDE d1, w2 - GET_VREG_WIDE d2, w3 - fcmp d1, d2 - cset w0, ne - cneg w0, w0, cc - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w4 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_cmp_long: /* 0x31 */ -/* File: arm64/op_cmp_long.S */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - and w2, w0, #255 // w2<- BB - lsr w3, w0, #8 // w3<- CC - GET_VREG_WIDE x1, w2 - GET_VREG_WIDE x2, w3 - cmp x1, x2 - cset w0, ne - cneg w0, w0, lt - FETCH_ADVANCE_INST 2 // advance rPC, load wINST - SET_VREG w0, w4 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_eq: /* 0x32 */ -/* File: arm64/op_if_eq.S */ -/* File: arm64/bincmp.S */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - lsr w1, wINST, #12 // w1<- B - ubfx w0, wINST, #8, #4 // w0<- A - GET_VREG w3, w1 // w3<- vB - GET_VREG w2, w0 // w2<- vA - FETCH_S wINST, 1 // wINST<- branch offset, in code units - cmp w2, w3 // compare (vA, vB) - b.eq MterpCommonTakenBranchNoFlags - cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? - b.eq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_ne: /* 0x33 */ -/* File: arm64/op_if_ne.S */ -/* File: arm64/bincmp.S */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - lsr w1, wINST, #12 // w1<- B - ubfx w0, wINST, #8, #4 // w0<- A - GET_VREG w3, w1 // w3<- vB - GET_VREG w2, w0 // w2<- vA - FETCH_S wINST, 1 // wINST<- branch offset, in code units - cmp w2, w3 // compare (vA, vB) - b.ne MterpCommonTakenBranchNoFlags - cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? - b.eq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_lt: /* 0x34 */ -/* File: arm64/op_if_lt.S */ -/* File: arm64/bincmp.S */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - lsr w1, wINST, #12 // w1<- B - ubfx w0, wINST, #8, #4 // w0<- A - GET_VREG w3, w1 // w3<- vB - GET_VREG w2, w0 // w2<- vA - FETCH_S wINST, 1 // wINST<- branch offset, in code units - cmp w2, w3 // compare (vA, vB) - b.lt MterpCommonTakenBranchNoFlags - cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? - b.eq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_ge: /* 0x35 */ -/* File: arm64/op_if_ge.S */ -/* File: arm64/bincmp.S */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - lsr w1, wINST, #12 // w1<- B - ubfx w0, wINST, #8, #4 // w0<- A - GET_VREG w3, w1 // w3<- vB - GET_VREG w2, w0 // w2<- vA - FETCH_S wINST, 1 // wINST<- branch offset, in code units - cmp w2, w3 // compare (vA, vB) - b.ge MterpCommonTakenBranchNoFlags - cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? - b.eq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_gt: /* 0x36 */ -/* File: arm64/op_if_gt.S */ -/* File: arm64/bincmp.S */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - lsr w1, wINST, #12 // w1<- B - ubfx w0, wINST, #8, #4 // w0<- A - GET_VREG w3, w1 // w3<- vB - GET_VREG w2, w0 // w2<- vA - FETCH_S wINST, 1 // wINST<- branch offset, in code units - cmp w2, w3 // compare (vA, vB) - b.gt MterpCommonTakenBranchNoFlags - cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? - b.eq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_le: /* 0x37 */ -/* File: arm64/op_if_le.S */ -/* File: arm64/bincmp.S */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - lsr w1, wINST, #12 // w1<- B - ubfx w0, wINST, #8, #4 // w0<- A - GET_VREG w3, w1 // w3<- vB - GET_VREG w2, w0 // w2<- vA - FETCH_S wINST, 1 // wINST<- branch offset, in code units - cmp w2, w3 // compare (vA, vB) - b.le MterpCommonTakenBranchNoFlags - cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? - b.eq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_eqz: /* 0x38 */ -/* File: arm64/op_if_eqz.S */ -/* File: arm64/zcmp.S */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - lsr w0, wINST, #8 // w0<- AA - GET_VREG w2, w0 // w2<- vAA - FETCH_S wINST, 1 // w1<- branch offset, in code units - .if 0 - cmp w2, #0 // compare (vA, 0) - .endif - cbz w2, MterpCommonTakenBranchNoFlags - cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? - b.eq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_nez: /* 0x39 */ -/* File: arm64/op_if_nez.S */ -/* File: arm64/zcmp.S */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - lsr w0, wINST, #8 // w0<- AA - GET_VREG w2, w0 // w2<- vAA - FETCH_S wINST, 1 // w1<- branch offset, in code units - .if 0 - cmp w2, #0 // compare (vA, 0) - .endif - cbnz w2, MterpCommonTakenBranchNoFlags - cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? - b.eq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_ltz: /* 0x3a */ -/* File: arm64/op_if_ltz.S */ -/* File: arm64/zcmp.S */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - lsr w0, wINST, #8 // w0<- AA - GET_VREG w2, w0 // w2<- vAA - FETCH_S wINST, 1 // w1<- branch offset, in code units - .if 0 - cmp w2, #0 // compare (vA, 0) - .endif - tbnz w2, #31, MterpCommonTakenBranchNoFlags - cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? - b.eq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_gez: /* 0x3b */ -/* File: arm64/op_if_gez.S */ -/* File: arm64/zcmp.S */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - lsr w0, wINST, #8 // w0<- AA - GET_VREG w2, w0 // w2<- vAA - FETCH_S wINST, 1 // w1<- branch offset, in code units - .if 0 - cmp w2, #0 // compare (vA, 0) - .endif - tbz w2, #31, MterpCommonTakenBranchNoFlags - cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? - b.eq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_gtz: /* 0x3c */ -/* File: arm64/op_if_gtz.S */ -/* File: arm64/zcmp.S */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - lsr w0, wINST, #8 // w0<- AA - GET_VREG w2, w0 // w2<- vAA - FETCH_S wINST, 1 // w1<- branch offset, in code units - .if 1 - cmp w2, #0 // compare (vA, 0) - .endif - b.gt MterpCommonTakenBranchNoFlags - cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? - b.eq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_lez: /* 0x3d */ -/* File: arm64/op_if_lez.S */ -/* File: arm64/zcmp.S */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - lsr w0, wINST, #8 // w0<- AA - GET_VREG w2, w0 // w2<- vAA - FETCH_S wINST, 1 // w1<- branch offset, in code units - .if 1 - cmp w2, #0 // compare (vA, 0) - .endif - b.le MterpCommonTakenBranchNoFlags - cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? - b.eq .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_3e: /* 0x3e */ -/* File: arm64/op_unused_3e.S */ -/* File: arm64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_3f: /* 0x3f */ -/* File: arm64/op_unused_3f.S */ -/* File: arm64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_40: /* 0x40 */ -/* File: arm64/op_unused_40.S */ -/* File: arm64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_41: /* 0x41 */ -/* File: arm64/op_unused_41.S */ -/* File: arm64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_42: /* 0x42 */ -/* File: arm64/op_unused_42.S */ -/* File: arm64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_43: /* 0x43 */ -/* File: arm64/op_unused_43.S */ -/* File: arm64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_aget: /* 0x44 */ -/* File: arm64/op_aget.S */ - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B w2, 1, 0 // w2<- BB - lsr w9, wINST, #8 // w9<- AA - FETCH_B w3, 1, 1 // w3<- CC - GET_VREG w0, w2 // w0<- vBB (array object) - GET_VREG w1, w3 // w1<- vCC (requested index) - cbz x0, common_errNullObject // bail if null array object. - ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length - add x0, x0, w1, uxtw #2 // w0<- arrayObj + index*width - cmp w1, w3 // compare unsigned index, length - bcs common_errArrayIndex // index >= length, bail - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - ldr w2, [x0, #MIRROR_INT_ARRAY_DATA_OFFSET] // w2<- vBB[vCC] - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w2, w9 // vAA<- w2 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aget_wide: /* 0x45 */ -/* File: arm64/op_aget_wide.S */ - /* - * Array get, 64 bits. vAA <- vBB[vCC]. - * - */ - /* aget-wide vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - and w2, w0, #255 // w2<- BB - lsr w3, w0, #8 // w3<- CC - GET_VREG w0, w2 // w0<- vBB (array object) - GET_VREG w1, w3 // w1<- vCC (requested index) - cbz w0, common_errNullObject // yes, bail - ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length - add x0, x0, w1, lsl #3 // w0<- arrayObj + index*width - cmp w1, w3 // compare unsigned index, length - bcs common_errArrayIndex // index >= length, bail - FETCH_ADVANCE_INST 2 // advance rPC, load wINST - ldr x2, [x0, #MIRROR_WIDE_ARRAY_DATA_OFFSET] // x2<- vBB[vCC] - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG_WIDE x2, w4 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aget_object: /* 0x46 */ -/* File: arm64/op_aget_object.S */ - /* - * Array object get. vAA <- vBB[vCC]. - * - * for: aget-object - */ - /* op vAA, vBB, vCC */ - FETCH_B w2, 1, 0 // w2<- BB - FETCH_B w3, 1, 1 // w3<- CC - EXPORT_PC - GET_VREG w0, w2 // w0<- vBB (array object) - GET_VREG w1, w3 // w1<- vCC (requested index) - bl artAGetObjectFromMterp // (array, index) - ldr x1, [xSELF, #THREAD_EXCEPTION_OFFSET] - lsr w2, wINST, #8 // w9<- AA - PREFETCH_INST 2 - cbnz w1, MterpException - SET_VREG_OBJECT w0, w2 - ADVANCE 2 - GET_INST_OPCODE ip - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aget_boolean: /* 0x47 */ -/* File: arm64/op_aget_boolean.S */ -/* File: arm64/op_aget.S */ - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B w2, 1, 0 // w2<- BB - lsr w9, wINST, #8 // w9<- AA - FETCH_B w3, 1, 1 // w3<- CC - GET_VREG w0, w2 // w0<- vBB (array object) - GET_VREG w1, w3 // w1<- vCC (requested index) - cbz x0, common_errNullObject // bail if null array object. - ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length - add x0, x0, w1, uxtw #0 // w0<- arrayObj + index*width - cmp w1, w3 // compare unsigned index, length - bcs common_errArrayIndex // index >= length, bail - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - ldrb w2, [x0, #MIRROR_BOOLEAN_ARRAY_DATA_OFFSET] // w2<- vBB[vCC] - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w2, w9 // vAA<- w2 - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_aget_byte: /* 0x48 */ -/* File: arm64/op_aget_byte.S */ -/* File: arm64/op_aget.S */ - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B w2, 1, 0 // w2<- BB - lsr w9, wINST, #8 // w9<- AA - FETCH_B w3, 1, 1 // w3<- CC - GET_VREG w0, w2 // w0<- vBB (array object) - GET_VREG w1, w3 // w1<- vCC (requested index) - cbz x0, common_errNullObject // bail if null array object. - ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length - add x0, x0, w1, uxtw #0 // w0<- arrayObj + index*width - cmp w1, w3 // compare unsigned index, length - bcs common_errArrayIndex // index >= length, bail - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - ldrsb w2, [x0, #MIRROR_BYTE_ARRAY_DATA_OFFSET] // w2<- vBB[vCC] - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w2, w9 // vAA<- w2 - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_aget_char: /* 0x49 */ -/* File: arm64/op_aget_char.S */ -/* File: arm64/op_aget.S */ - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B w2, 1, 0 // w2<- BB - lsr w9, wINST, #8 // w9<- AA - FETCH_B w3, 1, 1 // w3<- CC - GET_VREG w0, w2 // w0<- vBB (array object) - GET_VREG w1, w3 // w1<- vCC (requested index) - cbz x0, common_errNullObject // bail if null array object. - ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length - add x0, x0, w1, uxtw #1 // w0<- arrayObj + index*width - cmp w1, w3 // compare unsigned index, length - bcs common_errArrayIndex // index >= length, bail - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - ldrh w2, [x0, #MIRROR_CHAR_ARRAY_DATA_OFFSET] // w2<- vBB[vCC] - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w2, w9 // vAA<- w2 - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_aget_short: /* 0x4a */ -/* File: arm64/op_aget_short.S */ -/* File: arm64/op_aget.S */ - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B w2, 1, 0 // w2<- BB - lsr w9, wINST, #8 // w9<- AA - FETCH_B w3, 1, 1 // w3<- CC - GET_VREG w0, w2 // w0<- vBB (array object) - GET_VREG w1, w3 // w1<- vCC (requested index) - cbz x0, common_errNullObject // bail if null array object. - ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length - add x0, x0, w1, uxtw #1 // w0<- arrayObj + index*width - cmp w1, w3 // compare unsigned index, length - bcs common_errArrayIndex // index >= length, bail - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - ldrsh w2, [x0, #MIRROR_SHORT_ARRAY_DATA_OFFSET] // w2<- vBB[vCC] - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w2, w9 // vAA<- w2 - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_aput: /* 0x4b */ -/* File: arm64/op_aput.S */ - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B w2, 1, 0 // w2<- BB - lsr w9, wINST, #8 // w9<- AA - FETCH_B w3, 1, 1 // w3<- CC - GET_VREG w0, w2 // w0<- vBB (array object) - GET_VREG w1, w3 // w1<- vCC (requested index) - cbz w0, common_errNullObject // bail if null - ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length - add x0, x0, w1, lsl #2 // w0<- arrayObj + index*width - cmp w1, w3 // compare unsigned index, length - bcs common_errArrayIndex // index >= length, bail - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_VREG w2, w9 // w2<- vAA - GET_INST_OPCODE ip // extract opcode from rINST - str w2, [x0, #MIRROR_INT_ARRAY_DATA_OFFSET] // vBB[vCC]<- w2 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aput_wide: /* 0x4c */ -/* File: arm64/op_aput_wide.S */ - /* - * Array put, 64 bits. vBB[vCC] <- vAA. - * - */ - /* aput-wide vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - and w2, w0, #255 // w2<- BB - lsr w3, w0, #8 // w3<- CC - GET_VREG w0, w2 // w0<- vBB (array object) - GET_VREG w1, w3 // w1<- vCC (requested index) - cbz w0, common_errNullObject // bail if null - ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length - add x0, x0, w1, lsl #3 // w0<- arrayObj + index*width - cmp w1, w3 // compare unsigned index, length - bcs common_errArrayIndex // index >= length, bail - GET_VREG_WIDE x1, w4 - FETCH_ADVANCE_INST 2 // advance rPC, load wINST - GET_INST_OPCODE ip // extract opcode from wINST - str x1, [x0, #MIRROR_WIDE_ARRAY_DATA_OFFSET] - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aput_object: /* 0x4d */ -/* File: arm64/op_aput_object.S */ - /* - * Store an object into an array. vBB[vCC] <- vAA. - */ - /* op vAA, vBB, vCC */ - EXPORT_PC - add x0, xFP, #OFF_FP_SHADOWFRAME - mov x1, xPC - mov w2, wINST - bl MterpAputObject - cbz w0, MterpPossibleException - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aput_boolean: /* 0x4e */ -/* File: arm64/op_aput_boolean.S */ -/* File: arm64/op_aput.S */ - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B w2, 1, 0 // w2<- BB - lsr w9, wINST, #8 // w9<- AA - FETCH_B w3, 1, 1 // w3<- CC - GET_VREG w0, w2 // w0<- vBB (array object) - GET_VREG w1, w3 // w1<- vCC (requested index) - cbz w0, common_errNullObject // bail if null - ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length - add x0, x0, w1, lsl #0 // w0<- arrayObj + index*width - cmp w1, w3 // compare unsigned index, length - bcs common_errArrayIndex // index >= length, bail - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_VREG w2, w9 // w2<- vAA - GET_INST_OPCODE ip // extract opcode from rINST - strb w2, [x0, #MIRROR_BOOLEAN_ARRAY_DATA_OFFSET] // vBB[vCC]<- w2 - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_aput_byte: /* 0x4f */ -/* File: arm64/op_aput_byte.S */ -/* File: arm64/op_aput.S */ - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B w2, 1, 0 // w2<- BB - lsr w9, wINST, #8 // w9<- AA - FETCH_B w3, 1, 1 // w3<- CC - GET_VREG w0, w2 // w0<- vBB (array object) - GET_VREG w1, w3 // w1<- vCC (requested index) - cbz w0, common_errNullObject // bail if null - ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length - add x0, x0, w1, lsl #0 // w0<- arrayObj + index*width - cmp w1, w3 // compare unsigned index, length - bcs common_errArrayIndex // index >= length, bail - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_VREG w2, w9 // w2<- vAA - GET_INST_OPCODE ip // extract opcode from rINST - strb w2, [x0, #MIRROR_BYTE_ARRAY_DATA_OFFSET] // vBB[vCC]<- w2 - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_aput_char: /* 0x50 */ -/* File: arm64/op_aput_char.S */ -/* File: arm64/op_aput.S */ - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B w2, 1, 0 // w2<- BB - lsr w9, wINST, #8 // w9<- AA - FETCH_B w3, 1, 1 // w3<- CC - GET_VREG w0, w2 // w0<- vBB (array object) - GET_VREG w1, w3 // w1<- vCC (requested index) - cbz w0, common_errNullObject // bail if null - ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length - add x0, x0, w1, lsl #1 // w0<- arrayObj + index*width - cmp w1, w3 // compare unsigned index, length - bcs common_errArrayIndex // index >= length, bail - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_VREG w2, w9 // w2<- vAA - GET_INST_OPCODE ip // extract opcode from rINST - strh w2, [x0, #MIRROR_CHAR_ARRAY_DATA_OFFSET] // vBB[vCC]<- w2 - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_aput_short: /* 0x51 */ -/* File: arm64/op_aput_short.S */ -/* File: arm64/op_aput.S */ - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B w2, 1, 0 // w2<- BB - lsr w9, wINST, #8 // w9<- AA - FETCH_B w3, 1, 1 // w3<- CC - GET_VREG w0, w2 // w0<- vBB (array object) - GET_VREG w1, w3 // w1<- vCC (requested index) - cbz w0, common_errNullObject // bail if null - ldr w3, [x0, #MIRROR_ARRAY_LENGTH_OFFSET] // w3<- arrayObj->length - add x0, x0, w1, lsl #1 // w0<- arrayObj + index*width - cmp w1, w3 // compare unsigned index, length - bcs common_errArrayIndex // index >= length, bail - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_VREG w2, w9 // w2<- vAA - GET_INST_OPCODE ip // extract opcode from rINST - strh w2, [x0, #MIRROR_SHORT_ARRAY_DATA_OFFSET] // vBB[vCC]<- w2 - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_iget: /* 0x52 */ -/* File: arm64/op_iget.S */ -/* File: arm64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetU32 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpIGetU32 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_wide: /* 0x53 */ -/* File: arm64/op_iget_wide.S */ -/* File: arm64/op_iget.S */ -/* File: arm64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetU64 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpIGetU64 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_object: /* 0x54 */ -/* File: arm64/op_iget_object.S */ -/* File: arm64/op_iget.S */ -/* File: arm64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetObj - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpIGetObj - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_boolean: /* 0x55 */ -/* File: arm64/op_iget_boolean.S */ -/* File: arm64/op_iget.S */ -/* File: arm64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetU8 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpIGetU8 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_byte: /* 0x56 */ -/* File: arm64/op_iget_byte.S */ -/* File: arm64/op_iget.S */ -/* File: arm64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetI8 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpIGetI8 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_char: /* 0x57 */ -/* File: arm64/op_iget_char.S */ -/* File: arm64/op_iget.S */ -/* File: arm64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetU16 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpIGetU16 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_short: /* 0x58 */ -/* File: arm64/op_iget_short.S */ -/* File: arm64/op_iget.S */ -/* File: arm64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetI16 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpIGetI16 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_iput: /* 0x59 */ -/* File: arm64/op_iput.S */ -/* File: arm64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutU32 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpIPutU32 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_wide: /* 0x5a */ -/* File: arm64/op_iput_wide.S */ -/* File: arm64/op_iput.S */ -/* File: arm64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutU64 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpIPutU64 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_object: /* 0x5b */ -/* File: arm64/op_iput_object.S */ -/* File: arm64/op_iput.S */ -/* File: arm64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutObj - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpIPutObj - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_boolean: /* 0x5c */ -/* File: arm64/op_iput_boolean.S */ -/* File: arm64/op_iput.S */ -/* File: arm64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutU8 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpIPutU8 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_byte: /* 0x5d */ -/* File: arm64/op_iput_byte.S */ -/* File: arm64/op_iput.S */ -/* File: arm64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutI8 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpIPutI8 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_char: /* 0x5e */ -/* File: arm64/op_iput_char.S */ -/* File: arm64/op_iput.S */ -/* File: arm64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutU16 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpIPutU16 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_short: /* 0x5f */ -/* File: arm64/op_iput_short.S */ -/* File: arm64/op_iput.S */ -/* File: arm64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutI16 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpIPutI16 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_sget: /* 0x60 */ -/* File: arm64/op_sget.S */ -/* File: arm64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetU32 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpSGetU32 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_sget_wide: /* 0x61 */ -/* File: arm64/op_sget_wide.S */ -/* File: arm64/op_sget.S */ -/* File: arm64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetU64 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpSGetU64 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_sget_object: /* 0x62 */ -/* File: arm64/op_sget_object.S */ -/* File: arm64/op_sget.S */ -/* File: arm64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetObj - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpSGetObj - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_sget_boolean: /* 0x63 */ -/* File: arm64/op_sget_boolean.S */ -/* File: arm64/op_sget.S */ -/* File: arm64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetU8 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpSGetU8 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_sget_byte: /* 0x64 */ -/* File: arm64/op_sget_byte.S */ -/* File: arm64/op_sget.S */ -/* File: arm64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetI8 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpSGetI8 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_sget_char: /* 0x65 */ -/* File: arm64/op_sget_char.S */ -/* File: arm64/op_sget.S */ -/* File: arm64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetU16 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpSGetU16 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_sget_short: /* 0x66 */ -/* File: arm64/op_sget_short.S */ -/* File: arm64/op_sget.S */ -/* File: arm64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetI16 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpSGetI16 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_sput: /* 0x67 */ -/* File: arm64/op_sput.S */ -/* File: arm64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutU32 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpSPutU32 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_sput_wide: /* 0x68 */ -/* File: arm64/op_sput_wide.S */ -/* File: arm64/op_sput.S */ -/* File: arm64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutU64 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpSPutU64 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_sput_object: /* 0x69 */ -/* File: arm64/op_sput_object.S */ -/* File: arm64/op_sput.S */ -/* File: arm64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutObj - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpSPutObj - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_sput_boolean: /* 0x6a */ -/* File: arm64/op_sput_boolean.S */ -/* File: arm64/op_sput.S */ -/* File: arm64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutU8 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpSPutU8 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_sput_byte: /* 0x6b */ -/* File: arm64/op_sput_byte.S */ -/* File: arm64/op_sput.S */ -/* File: arm64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutI8 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpSPutI8 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_sput_char: /* 0x6c */ -/* File: arm64/op_sput_char.S */ -/* File: arm64/op_sput.S */ -/* File: arm64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutU16 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpSPutU16 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_sput_short: /* 0x6d */ -/* File: arm64/op_sput_short.S */ -/* File: arm64/op_sput.S */ -/* File: arm64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutI16 - mov x0, xPC // arg0: Instruction* inst - mov x1, xINST // arg1: uint16_t inst_data - add x2, xFP, #OFF_FP_SHADOWFRAME // arg2: ShadowFrame* sf - mov x3, xSELF // arg3: Thread* self - PREFETCH_INST 2 // prefetch next opcode - bl MterpSPutI16 - cbz x0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual: /* 0x6e */ -/* File: arm64/op_invoke_virtual.S */ -/* File: arm64/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtual - EXPORT_PC - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - mov x3, xINST - bl MterpInvokeVirtual - cbz w0, MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cbnz w0, MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - - - /* - * Handle a virtual method call. - * - * for: invoke-virtual, invoke-virtual/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_super: /* 0x6f */ -/* File: arm64/op_invoke_super.S */ -/* File: arm64/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeSuper - EXPORT_PC - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - mov x3, xINST - bl MterpInvokeSuper - cbz w0, MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cbnz w0, MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - - - /* - * Handle a "super" method call. - * - * for: invoke-super, invoke-super/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_direct: /* 0x70 */ -/* File: arm64/op_invoke_direct.S */ -/* File: arm64/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeDirect - EXPORT_PC - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - mov x3, xINST - bl MterpInvokeDirect - cbz w0, MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cbnz w0, MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_static: /* 0x71 */ -/* File: arm64/op_invoke_static.S */ -/* File: arm64/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeStatic - EXPORT_PC - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - mov x3, xINST - bl MterpInvokeStatic - cbz w0, MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cbnz w0, MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - - - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_interface: /* 0x72 */ -/* File: arm64/op_invoke_interface.S */ -/* File: arm64/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeInterface - EXPORT_PC - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - mov x3, xINST - bl MterpInvokeInterface - cbz w0, MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cbnz w0, MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - - - /* - * Handle an interface method call. - * - * for: invoke-interface, invoke-interface/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - -/* ------------------------------ */ - .balign 128 -.L_op_return_void_no_barrier: /* 0x73 */ -/* File: arm64/op_return_void_no_barrier.S */ - ldr w7, [xSELF, #THREAD_FLAGS_OFFSET] - mov x0, xSELF - ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - b.ne .Lop_return_void_no_barrier_check -.Lop_return_void_no_barrier_return: - mov x0, #0 - b MterpReturn -.Lop_return_void_no_barrier_check: - bl MterpSuspendCheck // (self) - b .Lop_return_void_no_barrier_return - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual_range: /* 0x74 */ -/* File: arm64/op_invoke_virtual_range.S */ -/* File: arm64/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtualRange - EXPORT_PC - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - mov x3, xINST - bl MterpInvokeVirtualRange - cbz w0, MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cbnz w0, MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_super_range: /* 0x75 */ -/* File: arm64/op_invoke_super_range.S */ -/* File: arm64/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeSuperRange - EXPORT_PC - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - mov x3, xINST - bl MterpInvokeSuperRange - cbz w0, MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cbnz w0, MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_direct_range: /* 0x76 */ -/* File: arm64/op_invoke_direct_range.S */ -/* File: arm64/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeDirectRange - EXPORT_PC - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - mov x3, xINST - bl MterpInvokeDirectRange - cbz w0, MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cbnz w0, MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_static_range: /* 0x77 */ -/* File: arm64/op_invoke_static_range.S */ -/* File: arm64/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeStaticRange - EXPORT_PC - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - mov x3, xINST - bl MterpInvokeStaticRange - cbz w0, MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cbnz w0, MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_interface_range: /* 0x78 */ -/* File: arm64/op_invoke_interface_range.S */ -/* File: arm64/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeInterfaceRange - EXPORT_PC - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - mov x3, xINST - bl MterpInvokeInterfaceRange - cbz w0, MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cbnz w0, MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_79: /* 0x79 */ -/* File: arm64/op_unused_79.S */ -/* File: arm64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_7a: /* 0x7a */ -/* File: arm64/op_unused_7a.S */ -/* File: arm64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_neg_int: /* 0x7b */ -/* File: arm64/op_neg_int.S */ -/* File: arm64/unop.S */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op w0". - * This could be an ARM instruction or a function call. - * - * for: neg-int, not-int, neg-float, int-to-float, float-to-int, - * int-to-byte, int-to-char, int-to-short - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - GET_VREG w0, w3 // w0<- vB - ubfx w9, wINST, #8, #4 // w9<- A - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - sub w0, wzr, w0 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 8-9 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_not_int: /* 0x7c */ -/* File: arm64/op_not_int.S */ -/* File: arm64/unop.S */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op w0". - * This could be an ARM instruction or a function call. - * - * for: neg-int, not-int, neg-float, int-to-float, float-to-int, - * int-to-byte, int-to-char, int-to-short - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - GET_VREG w0, w3 // w0<- vB - ubfx w9, wINST, #8, #4 // w9<- A - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - mvn w0, w0 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 8-9 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_neg_long: /* 0x7d */ -/* File: arm64/op_neg_long.S */ -/* File: arm64/unopWide.S */ - /* - * Generic 64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op x0". - * - * For: neg-long, not-long - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w4, wINST, #8, #4 // w4<- A - GET_VREG_WIDE x0, w3 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - sub x0, xzr, x0 - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG_WIDE x0, w4 - GOTO_OPCODE ip // jump to next instruction - /* 10-11 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_not_long: /* 0x7e */ -/* File: arm64/op_not_long.S */ -/* File: arm64/unopWide.S */ - /* - * Generic 64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op x0". - * - * For: neg-long, not-long - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w4, wINST, #8, #4 // w4<- A - GET_VREG_WIDE x0, w3 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - mvn x0, x0 - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG_WIDE x0, w4 - GOTO_OPCODE ip // jump to next instruction - /* 10-11 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_neg_float: /* 0x7f */ -/* File: arm64/op_neg_float.S */ -/* File: arm64/unop.S */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op w0". - * This could be an ARM instruction or a function call. - * - * for: neg-int, not-int, neg-float, int-to-float, float-to-int, - * int-to-byte, int-to-char, int-to-short - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - GET_VREG w0, w3 // w0<- vB - ubfx w9, wINST, #8, #4 // w9<- A - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - eor w0, w0, #0x80000000 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 8-9 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_neg_double: /* 0x80 */ -/* File: arm64/op_neg_double.S */ -/* File: arm64/unopWide.S */ - /* - * Generic 64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op x0". - * - * For: neg-long, not-long - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w4, wINST, #8, #4 // w4<- A - GET_VREG_WIDE x0, w3 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - eor x0, x0, #0x8000000000000000 - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG_WIDE x0, w4 - GOTO_OPCODE ip // jump to next instruction - /* 10-11 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_long: /* 0x81 */ -/* File: arm64/op_int_to_long.S */ - /* int-to-long vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w4, wINST, #8, #4 // w4<- A - GET_VREG_S x0, w3 // x0<- sign_extend(fp[B]) - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG_WIDE x0, w4 // fp[A]<- x0 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_float: /* 0x82 */ -/* File: arm64/op_int_to_float.S */ -/* File: arm64/funopNarrow.S */ - /* - * Generic 32bit-to-32bit floating point unary operation. Provide an - * "instr" line that specifies an instruction that performs "s0 = op w0". - * - * For: int-to-float, float-to-int - * TODO: refactor all of the conversions - parameterize width and use same template. - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w4, wINST, #8, #4 // w4<- A - GET_VREG w0, w3 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - scvtf s0, w0 // d0<- op - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG s0, w4 // vA<- d0 - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_double: /* 0x83 */ -/* File: arm64/op_int_to_double.S */ -/* File: arm64/funopWider.S */ - /* - * Generic 32bit-to-64bit floating point unary operation. Provide an - * "instr" line that specifies an instruction that performs "d0 = op w0". - * - * For: int-to-double, float-to-double, float-to-long - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w4, wINST, #8, #4 // w4<- A - GET_VREG w0, w3 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - scvtf d0, w0 // d0<- op - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG_WIDE d0, w4 // vA<- d0 - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_long_to_int: /* 0x84 */ -/* File: arm64/op_long_to_int.S */ -/* we ignore the high word, making this equivalent to a 32-bit reg move */ -/* File: arm64/op_move.S */ - /* for move, move-object, long-to-int */ - /* op vA, vB */ - lsr w1, wINST, #12 // x1<- B from 15:12 - ubfx w0, wINST, #8, #4 // x0<- A from 11:8 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - GET_VREG w2, w1 // x2<- fp[B] - GET_INST_OPCODE ip // ip<- opcode from wINST - .if 0 - SET_VREG_OBJECT w2, w0 // fp[A]<- x2 - .else - SET_VREG w2, w0 // fp[A]<- x2 - .endif - GOTO_OPCODE ip // execute next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_long_to_float: /* 0x85 */ -/* File: arm64/op_long_to_float.S */ -/* File: arm64/funopNarrower.S */ - /* - * Generic 64bit-to-32bit floating point unary operation. Provide an - * "instr" line that specifies an instruction that performs "s0 = op x0". - * - * For: int-to-double, float-to-double, float-to-long - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w4, wINST, #8, #4 // w4<- A - GET_VREG_WIDE x0, w3 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - scvtf s0, x0 // d0<- op - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG s0, w4 // vA<- d0 - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_long_to_double: /* 0x86 */ -/* File: arm64/op_long_to_double.S */ -/* File: arm64/funopWide.S */ - /* - * Generic 64bit-to-64bit floating point unary operation. Provide an - * "instr" line that specifies an instruction that performs "d0 = op x0". - * - * For: long-to-double, double-to-long - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w4, wINST, #8, #4 // w4<- A - GET_VREG_WIDE x0, w3 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - scvtf d0, x0 // d0<- op - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG_WIDE d0, w4 // vA<- d0 - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_float_to_int: /* 0x87 */ -/* File: arm64/op_float_to_int.S */ -/* File: arm64/funopNarrow.S */ - /* - * Generic 32bit-to-32bit floating point unary operation. Provide an - * "instr" line that specifies an instruction that performs "w0 = op s0". - * - * For: int-to-float, float-to-int - * TODO: refactor all of the conversions - parameterize width and use same template. - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w4, wINST, #8, #4 // w4<- A - GET_VREG s0, w3 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - fcvtzs w0, s0 // d0<- op - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG w0, w4 // vA<- d0 - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_float_to_long: /* 0x88 */ -/* File: arm64/op_float_to_long.S */ -/* File: arm64/funopWider.S */ - /* - * Generic 32bit-to-64bit floating point unary operation. Provide an - * "instr" line that specifies an instruction that performs "x0 = op s0". - * - * For: int-to-double, float-to-double, float-to-long - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w4, wINST, #8, #4 // w4<- A - GET_VREG s0, w3 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - fcvtzs x0, s0 // d0<- op - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG_WIDE x0, w4 // vA<- d0 - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_float_to_double: /* 0x89 */ -/* File: arm64/op_float_to_double.S */ -/* File: arm64/funopWider.S */ - /* - * Generic 32bit-to-64bit floating point unary operation. Provide an - * "instr" line that specifies an instruction that performs "d0 = op s0". - * - * For: int-to-double, float-to-double, float-to-long - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w4, wINST, #8, #4 // w4<- A - GET_VREG s0, w3 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - fcvt d0, s0 // d0<- op - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG_WIDE d0, w4 // vA<- d0 - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_double_to_int: /* 0x8a */ -/* File: arm64/op_double_to_int.S */ -/* File: arm64/funopNarrower.S */ - /* - * Generic 64bit-to-32bit floating point unary operation. Provide an - * "instr" line that specifies an instruction that performs "w0 = op d0". - * - * For: int-to-double, float-to-double, float-to-long - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w4, wINST, #8, #4 // w4<- A - GET_VREG_WIDE d0, w3 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - fcvtzs w0, d0 // d0<- op - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG w0, w4 // vA<- d0 - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_double_to_long: /* 0x8b */ -/* File: arm64/op_double_to_long.S */ -/* File: arm64/funopWide.S */ - /* - * Generic 64bit-to-64bit floating point unary operation. Provide an - * "instr" line that specifies an instruction that performs "x0 = op d0". - * - * For: long-to-double, double-to-long - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w4, wINST, #8, #4 // w4<- A - GET_VREG_WIDE d0, w3 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - fcvtzs x0, d0 // d0<- op - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG_WIDE x0, w4 // vA<- d0 - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_double_to_float: /* 0x8c */ -/* File: arm64/op_double_to_float.S */ -/* File: arm64/funopNarrower.S */ - /* - * Generic 64bit-to-32bit floating point unary operation. Provide an - * "instr" line that specifies an instruction that performs "s0 = op d0". - * - * For: int-to-double, float-to-double, float-to-long - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w4, wINST, #8, #4 // w4<- A - GET_VREG_WIDE d0, w3 - FETCH_ADVANCE_INST 1 // advance rPC, load wINST - fcvt s0, d0 // d0<- op - GET_INST_OPCODE ip // extract opcode from wINST - SET_VREG s0, w4 // vA<- d0 - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_byte: /* 0x8d */ -/* File: arm64/op_int_to_byte.S */ -/* File: arm64/unop.S */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op w0". - * This could be an ARM instruction or a function call. - * - * for: neg-int, not-int, neg-float, int-to-float, float-to-int, - * int-to-byte, int-to-char, int-to-short - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - GET_VREG w0, w3 // w0<- vB - ubfx w9, wINST, #8, #4 // w9<- A - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - sxtb w0, w0 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 8-9 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_char: /* 0x8e */ -/* File: arm64/op_int_to_char.S */ -/* File: arm64/unop.S */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op w0". - * This could be an ARM instruction or a function call. - * - * for: neg-int, not-int, neg-float, int-to-float, float-to-int, - * int-to-byte, int-to-char, int-to-short - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - GET_VREG w0, w3 // w0<- vB - ubfx w9, wINST, #8, #4 // w9<- A - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - uxth w0, w0 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 8-9 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_short: /* 0x8f */ -/* File: arm64/op_int_to_short.S */ -/* File: arm64/unop.S */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op w0". - * This could be an ARM instruction or a function call. - * - * for: neg-int, not-int, neg-float, int-to-float, float-to-int, - * int-to-byte, int-to-char, int-to-short - */ - /* unop vA, vB */ - lsr w3, wINST, #12 // w3<- B - GET_VREG w0, w3 // w0<- vB - ubfx w9, wINST, #8, #4 // w9<- A - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - sxth w0, w0 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 8-9 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_add_int: /* 0x90 */ -/* File: arm64/op_add_int.S */ -/* File: arm64/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w9, wINST, #8 // w9<- AA - lsr w3, w0, #8 // w3<- CC - and w2, w0, #255 // w2<- BB - GET_VREG w1, w3 // w1<- vCC - GET_VREG w0, w2 // w0<- vBB - .if 0 - cbz w1, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - // optional op; may set condition codes - add w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_int: /* 0x91 */ -/* File: arm64/op_sub_int.S */ -/* File: arm64/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w9, wINST, #8 // w9<- AA - lsr w3, w0, #8 // w3<- CC - and w2, w0, #255 // w2<- BB - GET_VREG w1, w3 // w1<- vCC - GET_VREG w0, w2 // w0<- vBB - .if 0 - cbz w1, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - // optional op; may set condition codes - sub w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int: /* 0x92 */ -/* File: arm64/op_mul_int.S */ -/* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */ -/* File: arm64/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w9, wINST, #8 // w9<- AA - lsr w3, w0, #8 // w3<- CC - and w2, w0, #255 // w2<- BB - GET_VREG w1, w3 // w1<- vCC - GET_VREG w0, w2 // w0<- vBB - .if 0 - cbz w1, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - // optional op; may set condition codes - mul w0, w1, w0 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_div_int: /* 0x93 */ -/* File: arm64/op_div_int.S */ -/* File: arm64/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w9, wINST, #8 // w9<- AA - lsr w3, w0, #8 // w3<- CC - and w2, w0, #255 // w2<- BB - GET_VREG w1, w3 // w1<- vCC - GET_VREG w0, w2 // w0<- vBB - .if 1 - cbz w1, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - // optional op; may set condition codes - sdiv w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int: /* 0x94 */ -/* File: arm64/op_rem_int.S */ -/* File: arm64/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w9, wINST, #8 // w9<- AA - lsr w3, w0, #8 // w3<- CC - and w2, w0, #255 // w2<- BB - GET_VREG w1, w3 // w1<- vCC - GET_VREG w0, w2 // w0<- vBB - .if 1 - cbz w1, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - sdiv w2, w0, w1 // optional op; may set condition codes - msub w0, w2, w1, w0 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_and_int: /* 0x95 */ -/* File: arm64/op_and_int.S */ -/* File: arm64/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w9, wINST, #8 // w9<- AA - lsr w3, w0, #8 // w3<- CC - and w2, w0, #255 // w2<- BB - GET_VREG w1, w3 // w1<- vCC - GET_VREG w0, w2 // w0<- vBB - .if 0 - cbz w1, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - // optional op; may set condition codes - and w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_or_int: /* 0x96 */ -/* File: arm64/op_or_int.S */ -/* File: arm64/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w9, wINST, #8 // w9<- AA - lsr w3, w0, #8 // w3<- CC - and w2, w0, #255 // w2<- BB - GET_VREG w1, w3 // w1<- vCC - GET_VREG w0, w2 // w0<- vBB - .if 0 - cbz w1, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - // optional op; may set condition codes - orr w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int: /* 0x97 */ -/* File: arm64/op_xor_int.S */ -/* File: arm64/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w9, wINST, #8 // w9<- AA - lsr w3, w0, #8 // w3<- CC - and w2, w0, #255 // w2<- BB - GET_VREG w1, w3 // w1<- vCC - GET_VREG w0, w2 // w0<- vBB - .if 0 - cbz w1, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - // optional op; may set condition codes - eor w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_shl_int: /* 0x98 */ -/* File: arm64/op_shl_int.S */ -/* File: arm64/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w9, wINST, #8 // w9<- AA - lsr w3, w0, #8 // w3<- CC - and w2, w0, #255 // w2<- BB - GET_VREG w1, w3 // w1<- vCC - GET_VREG w0, w2 // w0<- vBB - .if 0 - cbz w1, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - // optional op; may set condition codes - lsl w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_shr_int: /* 0x99 */ -/* File: arm64/op_shr_int.S */ -/* File: arm64/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w9, wINST, #8 // w9<- AA - lsr w3, w0, #8 // w3<- CC - and w2, w0, #255 // w2<- BB - GET_VREG w1, w3 // w1<- vCC - GET_VREG w0, w2 // w0<- vBB - .if 0 - cbz w1, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - // optional op; may set condition codes - asr w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_int: /* 0x9a */ -/* File: arm64/op_ushr_int.S */ -/* File: arm64/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the ARM math lib - * handles it correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, - * mul-float, div-float, rem-float - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w9, wINST, #8 // w9<- AA - lsr w3, w0, #8 // w3<- CC - and w2, w0, #255 // w2<- BB - GET_VREG w1, w3 // w1<- vCC - GET_VREG w0, w2 // w0<- vBB - .if 0 - cbz w1, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - // optional op; may set condition codes - lsr w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_add_long: /* 0x9b */ -/* File: arm64/op_add_long.S */ -/* File: arm64/binopWide.S */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = x1 op x2". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than x0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, rem-double - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - lsr w2, w0, #8 // w2<- CC - and w1, w0, #255 // w1<- BB - GET_VREG_WIDE x2, w2 // w2<- vCC - GET_VREG_WIDE x1, w1 // w1<- vBB - .if 0 - cbz x2, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - add x0, x1, x2 // x0<- op, w0-w4 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w4 // vAA<- x0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_long: /* 0x9c */ -/* File: arm64/op_sub_long.S */ -/* File: arm64/binopWide.S */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = x1 op x2". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than x0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, rem-double - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - lsr w2, w0, #8 // w2<- CC - and w1, w0, #255 // w1<- BB - GET_VREG_WIDE x2, w2 // w2<- vCC - GET_VREG_WIDE x1, w1 // w1<- vBB - .if 0 - cbz x2, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - sub x0, x1, x2 // x0<- op, w0-w4 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w4 // vAA<- x0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_long: /* 0x9d */ -/* File: arm64/op_mul_long.S */ -/* File: arm64/binopWide.S */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = x1 op x2". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than x0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, rem-double - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - lsr w2, w0, #8 // w2<- CC - and w1, w0, #255 // w1<- BB - GET_VREG_WIDE x2, w2 // w2<- vCC - GET_VREG_WIDE x1, w1 // w1<- vBB - .if 0 - cbz x2, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - mul x0, x1, x2 // x0<- op, w0-w4 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w4 // vAA<- x0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_div_long: /* 0x9e */ -/* File: arm64/op_div_long.S */ -/* File: arm64/binopWide.S */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = x1 op x2". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than x0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, rem-double - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - lsr w2, w0, #8 // w2<- CC - and w1, w0, #255 // w1<- BB - GET_VREG_WIDE x2, w2 // w2<- vCC - GET_VREG_WIDE x1, w1 // w1<- vBB - .if 1 - cbz x2, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - sdiv x0, x1, x2 // x0<- op, w0-w4 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w4 // vAA<- x0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_long: /* 0x9f */ -/* File: arm64/op_rem_long.S */ -/* File: arm64/binopWide.S */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = x1 op x2". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than x0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, rem-double - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - lsr w2, w0, #8 // w2<- CC - and w1, w0, #255 // w1<- BB - GET_VREG_WIDE x2, w2 // w2<- vCC - GET_VREG_WIDE x1, w1 // w1<- vBB - .if 1 - cbz x2, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - sdiv x3, x1, x2 - msub x0, x3, x2, x1 // x0<- op, w0-w4 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w4 // vAA<- x0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_and_long: /* 0xa0 */ -/* File: arm64/op_and_long.S */ -/* File: arm64/binopWide.S */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = x1 op x2". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than x0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, rem-double - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - lsr w2, w0, #8 // w2<- CC - and w1, w0, #255 // w1<- BB - GET_VREG_WIDE x2, w2 // w2<- vCC - GET_VREG_WIDE x1, w1 // w1<- vBB - .if 0 - cbz x2, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - and x0, x1, x2 // x0<- op, w0-w4 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w4 // vAA<- x0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_or_long: /* 0xa1 */ -/* File: arm64/op_or_long.S */ -/* File: arm64/binopWide.S */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = x1 op x2". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than x0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, rem-double - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - lsr w2, w0, #8 // w2<- CC - and w1, w0, #255 // w1<- BB - GET_VREG_WIDE x2, w2 // w2<- vCC - GET_VREG_WIDE x1, w1 // w1<- vBB - .if 0 - cbz x2, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - orr x0, x1, x2 // x0<- op, w0-w4 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w4 // vAA<- x0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_xor_long: /* 0xa2 */ -/* File: arm64/op_xor_long.S */ -/* File: arm64/binopWide.S */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = x1 op x2". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than x0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, rem-double - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - lsr w2, w0, #8 // w2<- CC - and w1, w0, #255 // w1<- BB - GET_VREG_WIDE x2, w2 // w2<- vCC - GET_VREG_WIDE x1, w1 // w1<- vBB - .if 0 - cbz x2, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - eor x0, x1, x2 // x0<- op, w0-w4 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w4 // vAA<- x0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_shl_long: /* 0xa3 */ -/* File: arm64/op_shl_long.S */ -/* File: arm64/shiftWide.S */ - /* - * 64-bit shift operation. - * - * For: shl-long, shr-long, ushr-long - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w3, wINST, #8 // w3<- AA - lsr w2, w0, #8 // w2<- CC - GET_VREG w2, w2 // w2<- vCC (shift count) - and w1, w0, #255 // w1<- BB - GET_VREG_WIDE x1, w1 // x1<- vBB - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - lsl x0, x1, x2 // Do the shift. Only low 6 bits of x2 are used. - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w3 // vAA<- x0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_shr_long: /* 0xa4 */ -/* File: arm64/op_shr_long.S */ -/* File: arm64/shiftWide.S */ - /* - * 64-bit shift operation. - * - * For: shl-long, shr-long, ushr-long - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w3, wINST, #8 // w3<- AA - lsr w2, w0, #8 // w2<- CC - GET_VREG w2, w2 // w2<- vCC (shift count) - and w1, w0, #255 // w1<- BB - GET_VREG_WIDE x1, w1 // x1<- vBB - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - asr x0, x1, x2 // Do the shift. Only low 6 bits of x2 are used. - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w3 // vAA<- x0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_long: /* 0xa5 */ -/* File: arm64/op_ushr_long.S */ -/* File: arm64/shiftWide.S */ - /* - * 64-bit shift operation. - * - * For: shl-long, shr-long, ushr-long - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w3, wINST, #8 // w3<- AA - lsr w2, w0, #8 // w2<- CC - GET_VREG w2, w2 // w2<- vCC (shift count) - and w1, w0, #255 // w1<- BB - GET_VREG_WIDE x1, w1 // x1<- vBB - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - lsr x0, x1, x2 // Do the shift. Only low 6 bits of x2 are used. - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w3 // vAA<- x0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_add_float: /* 0xa6 */ -/* File: arm64/op_add_float.S */ -/* File: arm64/fbinop.S */ - /*: - * Generic 32-bit floating-point operation. - * - * For: add-float, sub-float, mul-float, div-float - * form: s0, s0, s1 - */ - /* floatop vAA, vBB, vCC */ - FETCH w0, 1 // r0<- CCBB - lsr w1, w0, #8 // r2<- CC - and w0, w0, #255 // r1<- BB - GET_VREG s1, w1 - GET_VREG s0, w0 - fadd s0, s0, s1 // s0<- op - lsr w1, wINST, #8 // r1<- AA - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG s0, w1 - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_float: /* 0xa7 */ -/* File: arm64/op_sub_float.S */ -/* File: arm64/fbinop.S */ - /*: - * Generic 32-bit floating-point operation. - * - * For: add-float, sub-float, mul-float, div-float - * form: s0, s0, s1 - */ - /* floatop vAA, vBB, vCC */ - FETCH w0, 1 // r0<- CCBB - lsr w1, w0, #8 // r2<- CC - and w0, w0, #255 // r1<- BB - GET_VREG s1, w1 - GET_VREG s0, w0 - fsub s0, s0, s1 // s0<- op - lsr w1, wINST, #8 // r1<- AA - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG s0, w1 - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_float: /* 0xa8 */ -/* File: arm64/op_mul_float.S */ -/* File: arm64/fbinop.S */ - /*: - * Generic 32-bit floating-point operation. - * - * For: add-float, sub-float, mul-float, div-float - * form: s0, s0, s1 - */ - /* floatop vAA, vBB, vCC */ - FETCH w0, 1 // r0<- CCBB - lsr w1, w0, #8 // r2<- CC - and w0, w0, #255 // r1<- BB - GET_VREG s1, w1 - GET_VREG s0, w0 - fmul s0, s0, s1 // s0<- op - lsr w1, wINST, #8 // r1<- AA - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG s0, w1 - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_div_float: /* 0xa9 */ -/* File: arm64/op_div_float.S */ -/* File: arm64/fbinop.S */ - /*: - * Generic 32-bit floating-point operation. - * - * For: add-float, sub-float, mul-float, div-float - * form: s0, s0, s1 - */ - /* floatop vAA, vBB, vCC */ - FETCH w0, 1 // r0<- CCBB - lsr w1, w0, #8 // r2<- CC - and w0, w0, #255 // r1<- BB - GET_VREG s1, w1 - GET_VREG s0, w0 - fdiv s0, s0, s1 // s0<- op - lsr w1, wINST, #8 // r1<- AA - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG s0, w1 - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_float: /* 0xaa */ -/* File: arm64/op_rem_float.S */ -/* EABI doesn't define a float remainder function, but libm does */ -/* File: arm64/fbinop.S */ - /*: - * Generic 32-bit floating-point operation. - * - * For: add-float, sub-float, mul-float, div-float - * form: s0, s0, s1 - */ - /* floatop vAA, vBB, vCC */ - FETCH w0, 1 // r0<- CCBB - lsr w1, w0, #8 // r2<- CC - and w0, w0, #255 // r1<- BB - GET_VREG s1, w1 - GET_VREG s0, w0 - bl fmodf // s0<- op - lsr w1, wINST, #8 // r1<- AA - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG s0, w1 - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_add_double: /* 0xab */ -/* File: arm64/op_add_double.S */ -/* File: arm64/binopWide.S */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = x1 op x2". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than x0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, rem-double - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - lsr w2, w0, #8 // w2<- CC - and w1, w0, #255 // w1<- BB - GET_VREG_WIDE d2, w2 // w2<- vCC - GET_VREG_WIDE d1, w1 // w1<- vBB - .if 0 - cbz d2, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - fadd d0, d1, d2 // d0<- op, w0-w4 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE d0, w4 // vAA<- d0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_double: /* 0xac */ -/* File: arm64/op_sub_double.S */ -/* File: arm64/binopWide.S */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = x1 op x2". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than x0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, rem-double - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - lsr w2, w0, #8 // w2<- CC - and w1, w0, #255 // w1<- BB - GET_VREG_WIDE d2, w2 // w2<- vCC - GET_VREG_WIDE d1, w1 // w1<- vBB - .if 0 - cbz d2, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - fsub d0, d1, d2 // d0<- op, w0-w4 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE d0, w4 // vAA<- d0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_double: /* 0xad */ -/* File: arm64/op_mul_double.S */ -/* File: arm64/binopWide.S */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = x1 op x2". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than x0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, rem-double - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - lsr w2, w0, #8 // w2<- CC - and w1, w0, #255 // w1<- BB - GET_VREG_WIDE d2, w2 // w2<- vCC - GET_VREG_WIDE d1, w1 // w1<- vBB - .if 0 - cbz d2, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - fmul d0, d1, d2 // d0<- op, w0-w4 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE d0, w4 // vAA<- d0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_div_double: /* 0xae */ -/* File: arm64/op_div_double.S */ -/* File: arm64/binopWide.S */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = x1 op x2". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than x0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, add-double, sub-double, mul-double, div-double, rem-double - */ - /* binop vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w4, wINST, #8 // w4<- AA - lsr w2, w0, #8 // w2<- CC - and w1, w0, #255 // w1<- BB - GET_VREG_WIDE d2, w2 // w2<- vCC - GET_VREG_WIDE d1, w1 // w1<- vBB - .if 0 - cbz d2, common_errDivideByZero // is second operand zero? - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - fdiv d0, d1, d2 // d0<- op, w0-w4 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE d0, w4 // vAA<- d0 - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_double: /* 0xaf */ -/* File: arm64/op_rem_double.S */ - /* rem vAA, vBB, vCC */ - FETCH w0, 1 // w0<- CCBB - lsr w2, w0, #8 // w2<- CC - and w1, w0, #255 // w1<- BB - GET_VREG_WIDE d1, w2 // d1<- vCC - GET_VREG_WIDE d0, w1 // d0<- vBB - bl fmod - lsr w4, wINST, #8 // w4<- AA - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE d0, w4 // vAA<- result - GOTO_OPCODE ip // jump to next instruction - /* 11-14 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_add_int_2addr: /* 0xb0 */ -/* File: arm64/op_add_int_2addr.S */ -/* File: arm64/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG w1, w3 // w1<- vB - GET_VREG w0, w9 // w0<- vA - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - // optional op; may set condition codes - add w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_int_2addr: /* 0xb1 */ -/* File: arm64/op_sub_int_2addr.S */ -/* File: arm64/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG w1, w3 // w1<- vB - GET_VREG w0, w9 // w0<- vA - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - // optional op; may set condition codes - sub w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int_2addr: /* 0xb2 */ -/* File: arm64/op_mul_int_2addr.S */ -/* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */ -/* File: arm64/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG w1, w3 // w1<- vB - GET_VREG w0, w9 // w0<- vA - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - // optional op; may set condition codes - mul w0, w1, w0 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_div_int_2addr: /* 0xb3 */ -/* File: arm64/op_div_int_2addr.S */ -/* File: arm64/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG w1, w3 // w1<- vB - GET_VREG w0, w9 // w0<- vA - .if 1 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - // optional op; may set condition codes - sdiv w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int_2addr: /* 0xb4 */ -/* File: arm64/op_rem_int_2addr.S */ -/* File: arm64/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG w1, w3 // w1<- vB - GET_VREG w0, w9 // w0<- vA - .if 1 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - sdiv w2, w0, w1 // optional op; may set condition codes - msub w0, w2, w1, w0 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_and_int_2addr: /* 0xb5 */ -/* File: arm64/op_and_int_2addr.S */ -/* File: arm64/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG w1, w3 // w1<- vB - GET_VREG w0, w9 // w0<- vA - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - // optional op; may set condition codes - and w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_or_int_2addr: /* 0xb6 */ -/* File: arm64/op_or_int_2addr.S */ -/* File: arm64/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG w1, w3 // w1<- vB - GET_VREG w0, w9 // w0<- vA - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - // optional op; may set condition codes - orr w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int_2addr: /* 0xb7 */ -/* File: arm64/op_xor_int_2addr.S */ -/* File: arm64/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG w1, w3 // w1<- vB - GET_VREG w0, w9 // w0<- vA - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - // optional op; may set condition codes - eor w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_shl_int_2addr: /* 0xb8 */ -/* File: arm64/op_shl_int_2addr.S */ -/* File: arm64/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG w1, w3 // w1<- vB - GET_VREG w0, w9 // w0<- vA - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - // optional op; may set condition codes - lsl w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_shr_int_2addr: /* 0xb9 */ -/* File: arm64/op_shr_int_2addr.S */ -/* File: arm64/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG w1, w3 // w1<- vB - GET_VREG w0, w9 // w0<- vA - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - // optional op; may set condition codes - asr w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_int_2addr: /* 0xba */ -/* File: arm64/op_ushr_int_2addr.S */ -/* File: arm64/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG w1, w3 // w1<- vB - GET_VREG w0, w9 // w0<- vA - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - // optional op; may set condition codes - lsr w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_add_long_2addr: /* 0xbb */ -/* File: arm64/op_add_long_2addr.S */ -/* File: arm64/binopWide2addr.S */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "x0 = x0 op x1". - * This must not be a function call, as we keep w2 live across it. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr - */ - /* binop/2addr vA, vB */ - lsr w1, wINST, #12 // w1<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG_WIDE x1, w1 // x1<- vB - GET_VREG_WIDE x0, w2 // x0<- vA - .if 0 - cbz x1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - - add x0, x0, x1 // result<- op - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w2 // vAA<- result - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_long_2addr: /* 0xbc */ -/* File: arm64/op_sub_long_2addr.S */ -/* File: arm64/binopWide2addr.S */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "x0 = x0 op x1". - * This must not be a function call, as we keep w2 live across it. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr - */ - /* binop/2addr vA, vB */ - lsr w1, wINST, #12 // w1<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG_WIDE x1, w1 // x1<- vB - GET_VREG_WIDE x0, w2 // x0<- vA - .if 0 - cbz x1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - - sub x0, x0, x1 // result<- op - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w2 // vAA<- result - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_long_2addr: /* 0xbd */ -/* File: arm64/op_mul_long_2addr.S */ -/* File: arm64/binopWide2addr.S */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "x0 = x0 op x1". - * This must not be a function call, as we keep w2 live across it. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr - */ - /* binop/2addr vA, vB */ - lsr w1, wINST, #12 // w1<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG_WIDE x1, w1 // x1<- vB - GET_VREG_WIDE x0, w2 // x0<- vA - .if 0 - cbz x1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - - mul x0, x0, x1 // result<- op - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w2 // vAA<- result - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_div_long_2addr: /* 0xbe */ -/* File: arm64/op_div_long_2addr.S */ -/* File: arm64/binopWide2addr.S */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "x0 = x0 op x1". - * This must not be a function call, as we keep w2 live across it. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr - */ - /* binop/2addr vA, vB */ - lsr w1, wINST, #12 // w1<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG_WIDE x1, w1 // x1<- vB - GET_VREG_WIDE x0, w2 // x0<- vA - .if 1 - cbz x1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - - sdiv x0, x0, x1 // result<- op - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w2 // vAA<- result - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_long_2addr: /* 0xbf */ -/* File: arm64/op_rem_long_2addr.S */ -/* File: arm64/binopWide2addr.S */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "x0 = x0 op x1". - * This must not be a function call, as we keep w2 live across it. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr - */ - /* binop/2addr vA, vB */ - lsr w1, wINST, #12 // w1<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG_WIDE x1, w1 // x1<- vB - GET_VREG_WIDE x0, w2 // x0<- vA - .if 1 - cbz x1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - sdiv x3, x0, x1 - msub x0, x3, x1, x0 // result<- op - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w2 // vAA<- result - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_and_long_2addr: /* 0xc0 */ -/* File: arm64/op_and_long_2addr.S */ -/* File: arm64/binopWide2addr.S */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "x0 = x0 op x1". - * This must not be a function call, as we keep w2 live across it. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr - */ - /* binop/2addr vA, vB */ - lsr w1, wINST, #12 // w1<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG_WIDE x1, w1 // x1<- vB - GET_VREG_WIDE x0, w2 // x0<- vA - .if 0 - cbz x1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - - and x0, x0, x1 // result<- op - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w2 // vAA<- result - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_or_long_2addr: /* 0xc1 */ -/* File: arm64/op_or_long_2addr.S */ -/* File: arm64/binopWide2addr.S */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "x0 = x0 op x1". - * This must not be a function call, as we keep w2 live across it. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr - */ - /* binop/2addr vA, vB */ - lsr w1, wINST, #12 // w1<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG_WIDE x1, w1 // x1<- vB - GET_VREG_WIDE x0, w2 // x0<- vA - .if 0 - cbz x1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - - orr x0, x0, x1 // result<- op - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w2 // vAA<- result - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_xor_long_2addr: /* 0xc2 */ -/* File: arm64/op_xor_long_2addr.S */ -/* File: arm64/binopWide2addr.S */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "x0 = x0 op x1". - * This must not be a function call, as we keep w2 live across it. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr - */ - /* binop/2addr vA, vB */ - lsr w1, wINST, #12 // w1<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG_WIDE x1, w1 // x1<- vB - GET_VREG_WIDE x0, w2 // x0<- vA - .if 0 - cbz x1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - - eor x0, x0, x1 // result<- op - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w2 // vAA<- result - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_shl_long_2addr: /* 0xc3 */ -/* File: arm64/op_shl_long_2addr.S */ -/* File: arm64/shiftWide2addr.S */ - /* - * Generic 64-bit shift operation. - */ - /* binop/2addr vA, vB */ - lsr w1, wINST, #12 // w1<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG w1, w1 // x1<- vB - GET_VREG_WIDE x0, w2 // x0<- vA - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - lsl x0, x0, x1 // Do the shift. Only low 6 bits of x1 are used. - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w2 // vAA<- result - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_shr_long_2addr: /* 0xc4 */ -/* File: arm64/op_shr_long_2addr.S */ -/* File: arm64/shiftWide2addr.S */ - /* - * Generic 64-bit shift operation. - */ - /* binop/2addr vA, vB */ - lsr w1, wINST, #12 // w1<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG w1, w1 // x1<- vB - GET_VREG_WIDE x0, w2 // x0<- vA - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - asr x0, x0, x1 // Do the shift. Only low 6 bits of x1 are used. - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w2 // vAA<- result - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_long_2addr: /* 0xc5 */ -/* File: arm64/op_ushr_long_2addr.S */ -/* File: arm64/shiftWide2addr.S */ - /* - * Generic 64-bit shift operation. - */ - /* binop/2addr vA, vB */ - lsr w1, wINST, #12 // w1<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG w1, w1 // x1<- vB - GET_VREG_WIDE x0, w2 // x0<- vA - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - lsr x0, x0, x1 // Do the shift. Only low 6 bits of x1 are used. - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE x0, w2 // vAA<- result - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_add_float_2addr: /* 0xc6 */ -/* File: arm64/op_add_float_2addr.S */ -/* File: arm64/fbinop2addr.S */ - /* - * Generic 32-bit floating point "/2addr" binary operation. Provide - * an "instr" line that specifies an instruction that performs - * "s2 = s0 op s1". - * - * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr - */ - /* binop/2addr vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG s1, w3 - GET_VREG s0, w9 - fadd s2, s0, s1 // s2<- op - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG s2, w9 - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_float_2addr: /* 0xc7 */ -/* File: arm64/op_sub_float_2addr.S */ -/* File: arm64/fbinop2addr.S */ - /* - * Generic 32-bit floating point "/2addr" binary operation. Provide - * an "instr" line that specifies an instruction that performs - * "s2 = s0 op s1". - * - * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr - */ - /* binop/2addr vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG s1, w3 - GET_VREG s0, w9 - fsub s2, s0, s1 // s2<- op - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG s2, w9 - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_float_2addr: /* 0xc8 */ -/* File: arm64/op_mul_float_2addr.S */ -/* File: arm64/fbinop2addr.S */ - /* - * Generic 32-bit floating point "/2addr" binary operation. Provide - * an "instr" line that specifies an instruction that performs - * "s2 = s0 op s1". - * - * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr - */ - /* binop/2addr vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG s1, w3 - GET_VREG s0, w9 - fmul s2, s0, s1 // s2<- op - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG s2, w9 - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_div_float_2addr: /* 0xc9 */ -/* File: arm64/op_div_float_2addr.S */ -/* File: arm64/fbinop2addr.S */ - /* - * Generic 32-bit floating point "/2addr" binary operation. Provide - * an "instr" line that specifies an instruction that performs - * "s2 = s0 op s1". - * - * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr - */ - /* binop/2addr vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG s1, w3 - GET_VREG s0, w9 - fdiv s2, s0, s1 // s2<- op - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG s2, w9 - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_float_2addr: /* 0xca */ -/* File: arm64/op_rem_float_2addr.S */ - /* rem vA, vB */ - lsr w3, wINST, #12 // w3<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG s1, w3 - GET_VREG s0, w9 - bl fmodf - ubfx w9, wINST, #8, #4 // w9<- A - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG s0, w9 - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_add_double_2addr: /* 0xcb */ -/* File: arm64/op_add_double_2addr.S */ -/* File: arm64/binopWide2addr.S */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "x0 = x0 op x1". - * This must not be a function call, as we keep w2 live across it. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr - */ - /* binop/2addr vA, vB */ - lsr w1, wINST, #12 // w1<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG_WIDE d1, w1 // x1<- vB - GET_VREG_WIDE d0, w2 // x0<- vA - .if 0 - cbz d1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - - fadd d0, d0, d1 // result<- op - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE d0, w2 // vAA<- result - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_double_2addr: /* 0xcc */ -/* File: arm64/op_sub_double_2addr.S */ -/* File: arm64/binopWide2addr.S */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "x0 = x0 op x1". - * This must not be a function call, as we keep w2 live across it. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr - */ - /* binop/2addr vA, vB */ - lsr w1, wINST, #12 // w1<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG_WIDE d1, w1 // x1<- vB - GET_VREG_WIDE d0, w2 // x0<- vA - .if 0 - cbz d1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - - fsub d0, d0, d1 // result<- op - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE d0, w2 // vAA<- result - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_double_2addr: /* 0xcd */ -/* File: arm64/op_mul_double_2addr.S */ -/* File: arm64/binopWide2addr.S */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "x0 = x0 op x1". - * This must not be a function call, as we keep w2 live across it. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr - */ - /* binop/2addr vA, vB */ - lsr w1, wINST, #12 // w1<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG_WIDE d1, w1 // x1<- vB - GET_VREG_WIDE d0, w2 // x0<- vA - .if 0 - cbz d1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - - fmul d0, d0, d1 // result<- op - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE d0, w2 // vAA<- result - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_div_double_2addr: /* 0xce */ -/* File: arm64/op_div_double_2addr.S */ -/* File: arm64/binopWide2addr.S */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "x0 = x0 op x1". - * This must not be a function call, as we keep w2 live across it. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr, add-double/2addr, - * sub-double/2addr, mul-double/2addr, div-double/2addr, rem-double/2addr - */ - /* binop/2addr vA, vB */ - lsr w1, wINST, #12 // w1<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG_WIDE d1, w1 // x1<- vB - GET_VREG_WIDE d0, w2 // x0<- vA - .if 0 - cbz d1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - - fdiv d0, d0, d1 // result<- op - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE d0, w2 // vAA<- result - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_double_2addr: /* 0xcf */ -/* File: arm64/op_rem_double_2addr.S */ - /* rem vA, vB */ - lsr w1, wINST, #12 // w1<- B - ubfx w2, wINST, #8, #4 // w2<- A - GET_VREG_WIDE d1, w1 // d1<- vB - GET_VREG_WIDE d0, w2 // d0<- vA - bl fmod - ubfx w2, wINST, #8, #4 // w2<- A (need to reload - killed across call) - FETCH_ADVANCE_INST 1 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG_WIDE d0, w2 // vAA<- result - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - -/* ------------------------------ */ - .balign 128 -.L_op_add_int_lit16: /* 0xd0 */ -/* File: arm64/op_add_int_lit16.S */ -/* File: arm64/binopLit16.S */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - FETCH_S w1, 1 // w1<- ssssCCCC (sign-extended) - lsr w2, wINST, #12 // w2<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG w0, w2 // w0<- vB - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - add w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_rsub_int: /* 0xd1 */ -/* File: arm64/op_rsub_int.S */ -/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ -/* File: arm64/binopLit16.S */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - FETCH_S w1, 1 // w1<- ssssCCCC (sign-extended) - lsr w2, wINST, #12 // w2<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG w0, w2 // w0<- vB - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - sub w0, w1, w0 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int_lit16: /* 0xd2 */ -/* File: arm64/op_mul_int_lit16.S */ -/* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */ -/* File: arm64/binopLit16.S */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - FETCH_S w1, 1 // w1<- ssssCCCC (sign-extended) - lsr w2, wINST, #12 // w2<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG w0, w2 // w0<- vB - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - mul w0, w1, w0 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_div_int_lit16: /* 0xd3 */ -/* File: arm64/op_div_int_lit16.S */ -/* File: arm64/binopLit16.S */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - FETCH_S w1, 1 // w1<- ssssCCCC (sign-extended) - lsr w2, wINST, #12 // w2<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG w0, w2 // w0<- vB - .if 1 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - sdiv w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int_lit16: /* 0xd4 */ -/* File: arm64/op_rem_int_lit16.S */ -/* File: arm64/binopLit16.S */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - FETCH_S w1, 1 // w1<- ssssCCCC (sign-extended) - lsr w2, wINST, #12 // w2<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG w0, w2 // w0<- vB - .if 1 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - sdiv w3, w0, w1 - msub w0, w3, w1, w0 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_and_int_lit16: /* 0xd5 */ -/* File: arm64/op_and_int_lit16.S */ -/* File: arm64/binopLit16.S */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - FETCH_S w1, 1 // w1<- ssssCCCC (sign-extended) - lsr w2, wINST, #12 // w2<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG w0, w2 // w0<- vB - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - and w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_or_int_lit16: /* 0xd6 */ -/* File: arm64/op_or_int_lit16.S */ -/* File: arm64/binopLit16.S */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - FETCH_S w1, 1 // w1<- ssssCCCC (sign-extended) - lsr w2, wINST, #12 // w2<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG w0, w2 // w0<- vB - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - orr w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int_lit16: /* 0xd7 */ -/* File: arm64/op_xor_int_lit16.S */ -/* File: arm64/binopLit16.S */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - FETCH_S w1, 1 // w1<- ssssCCCC (sign-extended) - lsr w2, wINST, #12 // w2<- B - ubfx w9, wINST, #8, #4 // w9<- A - GET_VREG w0, w2 // w0<- vB - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - eor w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-13 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_add_int_lit8: /* 0xd8 */ -/* File: arm64/op_add_int_lit8.S */ -/* File: arm64/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from w3 to w1 is not the default "asr w1, w3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC) - lsr w9, wINST, #8 // w9<- AA - and w2, w3, #255 // w2<- BB - GET_VREG w0, w2 // w0<- vBB - // optional; typically w1<- ssssssCC (sign extended) - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - // optional op; may set condition codes - add w0, w0, w3, asr #8 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-12 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_rsub_int_lit8: /* 0xd9 */ -/* File: arm64/op_rsub_int_lit8.S */ -/* File: arm64/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from w3 to w1 is not the default "asr w1, w3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC) - lsr w9, wINST, #8 // w9<- AA - and w2, w3, #255 // w2<- BB - GET_VREG w0, w2 // w0<- vBB - asr w1, w3, #8 // optional; typically w1<- ssssssCC (sign extended) - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - // optional op; may set condition codes - sub w0, w1, w0 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-12 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int_lit8: /* 0xda */ -/* File: arm64/op_mul_int_lit8.S */ -/* must be "mul w0, w1, w0" -- "w0, w0, w1" is illegal */ -/* File: arm64/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from w3 to w1 is not the default "asr w1, w3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC) - lsr w9, wINST, #8 // w9<- AA - and w2, w3, #255 // w2<- BB - GET_VREG w0, w2 // w0<- vBB - asr w1, w3, #8 // optional; typically w1<- ssssssCC (sign extended) - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - // optional op; may set condition codes - mul w0, w1, w0 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-12 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_div_int_lit8: /* 0xdb */ -/* File: arm64/op_div_int_lit8.S */ -/* File: arm64/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from w3 to w1 is not the default "asr w1, w3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC) - lsr w9, wINST, #8 // w9<- AA - and w2, w3, #255 // w2<- BB - GET_VREG w0, w2 // w0<- vBB - asr w1, w3, #8 // optional; typically w1<- ssssssCC (sign extended) - .if 1 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - // optional op; may set condition codes - sdiv w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-12 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int_lit8: /* 0xdc */ -/* File: arm64/op_rem_int_lit8.S */ -/* File: arm64/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from w3 to w1 is not the default "asr w1, w3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC) - lsr w9, wINST, #8 // w9<- AA - and w2, w3, #255 // w2<- BB - GET_VREG w0, w2 // w0<- vBB - asr w1, w3, #8 // optional; typically w1<- ssssssCC (sign extended) - .if 1 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - sdiv w3, w0, w1 // optional op; may set condition codes - msub w0, w3, w1, w0 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-12 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_and_int_lit8: /* 0xdd */ -/* File: arm64/op_and_int_lit8.S */ -/* File: arm64/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from w3 to w1 is not the default "asr w1, w3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC) - lsr w9, wINST, #8 // w9<- AA - and w2, w3, #255 // w2<- BB - GET_VREG w0, w2 // w0<- vBB - // optional; typically w1<- ssssssCC (sign extended) - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - // optional op; may set condition codes - and w0, w0, w3, asr #8 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-12 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_or_int_lit8: /* 0xde */ -/* File: arm64/op_or_int_lit8.S */ -/* File: arm64/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from w3 to w1 is not the default "asr w1, w3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC) - lsr w9, wINST, #8 // w9<- AA - and w2, w3, #255 // w2<- BB - GET_VREG w0, w2 // w0<- vBB - // optional; typically w1<- ssssssCC (sign extended) - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - // optional op; may set condition codes - orr w0, w0, w3, asr #8 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-12 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int_lit8: /* 0xdf */ -/* File: arm64/op_xor_int_lit8.S */ -/* File: arm64/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from w3 to w1 is not the default "asr w1, w3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC) - lsr w9, wINST, #8 // w9<- AA - and w2, w3, #255 // w2<- BB - GET_VREG w0, w2 // w0<- vBB - // optional; typically w1<- ssssssCC (sign extended) - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - // optional op; may set condition codes - eor w0, w0, w3, asr #8 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-12 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_shl_int_lit8: /* 0xe0 */ -/* File: arm64/op_shl_int_lit8.S */ -/* File: arm64/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from w3 to w1 is not the default "asr w1, w3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC) - lsr w9, wINST, #8 // w9<- AA - and w2, w3, #255 // w2<- BB - GET_VREG w0, w2 // w0<- vBB - ubfx w1, w3, #8, #5 // optional; typically w1<- ssssssCC (sign extended) - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - // optional op; may set condition codes - lsl w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-12 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_shr_int_lit8: /* 0xe1 */ -/* File: arm64/op_shr_int_lit8.S */ -/* File: arm64/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from w3 to w1 is not the default "asr w1, w3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC) - lsr w9, wINST, #8 // w9<- AA - and w2, w3, #255 // w2<- BB - GET_VREG w0, w2 // w0<- vBB - ubfx w1, w3, #8, #5 // optional; typically w1<- ssssssCC (sign extended) - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - // optional op; may set condition codes - asr w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-12 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_int_lit8: /* 0xe2 */ -/* File: arm64/op_ushr_int_lit8.S */ -/* File: arm64/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = w0 op w1". - * This could be an ARM instruction or a function call. (If the result - * comes back in a register other than w0, you can override "result".) - * - * You can override "extract" if the extraction of the literal value - * from w3 to w1 is not the default "asr w1, w3, #8". The extraction - * can be omitted completely if the shift is embedded in "instr". - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (w1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - FETCH_S w3, 1 // w3<- ssssCCBB (sign-extended for CC) - lsr w9, wINST, #8 // w9<- AA - and w2, w3, #255 // w2<- BB - GET_VREG w0, w2 // w0<- vBB - ubfx w1, w3, #8, #5 // optional; typically w1<- ssssssCC (sign extended) - .if 0 - cbz w1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - // optional op; may set condition codes - lsr w0, w0, w1 // w0<- op, w0-w3 changed - GET_INST_OPCODE ip // extract opcode from rINST - SET_VREG w0, w9 // vAA<- w0 - GOTO_OPCODE ip // jump to next instruction - /* 10-12 instructions */ - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_quick: /* 0xe3 */ -/* File: arm64/op_iget_quick.S */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset//CCCC */ - lsr w2, wINST, #12 // w2<- B - FETCH w1, 1 // w1<- field byte offset - GET_VREG w3, w2 // w3<- object we're operating on - ubfx w2, wINST, #8, #4 // w2<- A - cbz w3, common_errNullObject // object was null - ldr w0, [x3, x1] // w0<- obj.field - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - SET_VREG w0, w2 // fp[A]<- w0 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iget_wide_quick: /* 0xe4 */ -/* File: arm64/op_iget_wide_quick.S */ - /* iget-wide-quick vA, vB, offset//CCCC */ - lsr w2, wINST, #12 // w2<- B - FETCH w4, 1 // w4<- field byte offset - GET_VREG w3, w2 // w3<- object we're operating on - ubfx w2, wINST, #8, #4 // w2<- A - cbz w3, common_errNullObject // object was null - ldr x0, [x3, x4] // x0<- obj.field - FETCH_ADVANCE_INST 2 // advance rPC, load wINST - SET_VREG_WIDE x0, w2 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iget_object_quick: /* 0xe5 */ -/* File: arm64/op_iget_object_quick.S */ - /* For: iget-object-quick */ - /* op vA, vB, offset//CCCC */ - lsr w2, wINST, #12 // w2<- B - FETCH w1, 1 // w1<- field byte offset - EXPORT_PC - GET_VREG w0, w2 // w0<- object we're operating on - bl artIGetObjectFromMterp // (obj, offset) - ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET] - ubfx w2, wINST, #8, #4 // w2<- A - PREFETCH_INST 2 - cbnz w3, MterpPossibleException // bail out - SET_VREG_OBJECT w0, w2 // fp[A]<- w0 - ADVANCE 2 // advance rPC - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_quick: /* 0xe6 */ -/* File: arm64/op_iput_quick.S */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset//CCCC */ - lsr w2, wINST, #12 // w2<- B - FETCH w1, 1 // w1<- field byte offset - GET_VREG w3, w2 // w3<- fp[B], the object pointer - ubfx w2, wINST, #8, #4 // w2<- A - cbz w3, common_errNullObject // object was null - GET_VREG w0, w2 // w0<- fp[A] - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - str w0, [x3, x1] // obj.field<- w0 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_wide_quick: /* 0xe7 */ -/* File: arm64/op_iput_wide_quick.S */ - /* iput-wide-quick vA, vB, offset//CCCC */ - lsr w2, wINST, #12 // w2<- B - FETCH w3, 1 // w3<- field byte offset - GET_VREG w2, w2 // w2<- fp[B], the object pointer - ubfx w0, wINST, #8, #4 // w0<- A - cbz w2, common_errNullObject // object was null - GET_VREG_WIDE x0, w0 // x0<- fp[A] - FETCH_ADVANCE_INST 2 // advance rPC, load wINST - str x0, [x2, x3] // obj.field<- x0 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_object_quick: /* 0xe8 */ -/* File: arm64/op_iput_object_quick.S */ - EXPORT_PC - add x0, xFP, #OFF_FP_SHADOWFRAME - mov x1, xPC - mov w2, wINST - bl MterpIputObjectQuick - cbz w0, MterpException - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual_quick: /* 0xe9 */ -/* File: arm64/op_invoke_virtual_quick.S */ -/* File: arm64/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtualQuick - EXPORT_PC - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - mov x3, xINST - bl MterpInvokeVirtualQuick - cbz w0, MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cbnz w0, MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual_range_quick: /* 0xea */ -/* File: arm64/op_invoke_virtual_range_quick.S */ -/* File: arm64/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtualQuickRange - EXPORT_PC - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - mov x3, xINST - bl MterpInvokeVirtualQuickRange - cbz w0, MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cbnz w0, MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_boolean_quick: /* 0xeb */ -/* File: arm64/op_iput_boolean_quick.S */ -/* File: arm64/op_iput_quick.S */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset//CCCC */ - lsr w2, wINST, #12 // w2<- B - FETCH w1, 1 // w1<- field byte offset - GET_VREG w3, w2 // w3<- fp[B], the object pointer - ubfx w2, wINST, #8, #4 // w2<- A - cbz w3, common_errNullObject // object was null - GET_VREG w0, w2 // w0<- fp[A] - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - strb w0, [x3, x1] // obj.field<- w0 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_byte_quick: /* 0xec */ -/* File: arm64/op_iput_byte_quick.S */ -/* File: arm64/op_iput_quick.S */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset//CCCC */ - lsr w2, wINST, #12 // w2<- B - FETCH w1, 1 // w1<- field byte offset - GET_VREG w3, w2 // w3<- fp[B], the object pointer - ubfx w2, wINST, #8, #4 // w2<- A - cbz w3, common_errNullObject // object was null - GET_VREG w0, w2 // w0<- fp[A] - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - strb w0, [x3, x1] // obj.field<- w0 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_char_quick: /* 0xed */ -/* File: arm64/op_iput_char_quick.S */ -/* File: arm64/op_iput_quick.S */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset//CCCC */ - lsr w2, wINST, #12 // w2<- B - FETCH w1, 1 // w1<- field byte offset - GET_VREG w3, w2 // w3<- fp[B], the object pointer - ubfx w2, wINST, #8, #4 // w2<- A - cbz w3, common_errNullObject // object was null - GET_VREG w0, w2 // w0<- fp[A] - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - strh w0, [x3, x1] // obj.field<- w0 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_short_quick: /* 0xee */ -/* File: arm64/op_iput_short_quick.S */ -/* File: arm64/op_iput_quick.S */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset//CCCC */ - lsr w2, wINST, #12 // w2<- B - FETCH w1, 1 // w1<- field byte offset - GET_VREG w3, w2 // w3<- fp[B], the object pointer - ubfx w2, wINST, #8, #4 // w2<- A - cbz w3, common_errNullObject // object was null - GET_VREG w0, w2 // w0<- fp[A] - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - strh w0, [x3, x1] // obj.field<- w0 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_boolean_quick: /* 0xef */ -/* File: arm64/op_iget_boolean_quick.S */ -/* File: arm64/op_iget_quick.S */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset//CCCC */ - lsr w2, wINST, #12 // w2<- B - FETCH w1, 1 // w1<- field byte offset - GET_VREG w3, w2 // w3<- object we're operating on - ubfx w2, wINST, #8, #4 // w2<- A - cbz w3, common_errNullObject // object was null - ldrb w0, [x3, x1] // w0<- obj.field - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - SET_VREG w0, w2 // fp[A]<- w0 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_byte_quick: /* 0xf0 */ -/* File: arm64/op_iget_byte_quick.S */ -/* File: arm64/op_iget_quick.S */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset//CCCC */ - lsr w2, wINST, #12 // w2<- B - FETCH w1, 1 // w1<- field byte offset - GET_VREG w3, w2 // w3<- object we're operating on - ubfx w2, wINST, #8, #4 // w2<- A - cbz w3, common_errNullObject // object was null - ldrsb w0, [x3, x1] // w0<- obj.field - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - SET_VREG w0, w2 // fp[A]<- w0 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_char_quick: /* 0xf1 */ -/* File: arm64/op_iget_char_quick.S */ -/* File: arm64/op_iget_quick.S */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset//CCCC */ - lsr w2, wINST, #12 // w2<- B - FETCH w1, 1 // w1<- field byte offset - GET_VREG w3, w2 // w3<- object we're operating on - ubfx w2, wINST, #8, #4 // w2<- A - cbz w3, common_errNullObject // object was null - ldrh w0, [x3, x1] // w0<- obj.field - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - SET_VREG w0, w2 // fp[A]<- w0 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_short_quick: /* 0xf2 */ -/* File: arm64/op_iget_short_quick.S */ -/* File: arm64/op_iget_quick.S */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset//CCCC */ - lsr w2, wINST, #12 // w2<- B - FETCH w1, 1 // w1<- field byte offset - GET_VREG w3, w2 // w3<- object we're operating on - ubfx w2, wINST, #8, #4 // w2<- A - cbz w3, common_errNullObject // object was null - ldrsh w0, [x3, x1] // w0<- obj.field - FETCH_ADVANCE_INST 2 // advance rPC, load rINST - - SET_VREG w0, w2 // fp[A]<- w0 - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f3: /* 0xf3 */ -/* File: arm64/op_unused_f3.S */ -/* File: arm64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f4: /* 0xf4 */ -/* File: arm64/op_unused_f4.S */ -/* File: arm64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f5: /* 0xf5 */ -/* File: arm64/op_unused_f5.S */ -/* File: arm64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f6: /* 0xf6 */ -/* File: arm64/op_unused_f6.S */ -/* File: arm64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f7: /* 0xf7 */ -/* File: arm64/op_unused_f7.S */ -/* File: arm64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f8: /* 0xf8 */ -/* File: arm64/op_unused_f8.S */ -/* File: arm64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f9: /* 0xf9 */ -/* File: arm64/op_unused_f9.S */ -/* File: arm64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_polymorphic: /* 0xfa */ -/* File: arm64/op_invoke_polymorphic.S */ -/* File: arm64/invoke_polymorphic.S */ - /* - * invoke-polymorphic handler wrapper. - */ - /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ - .extern MterpInvokePolymorphic - EXPORT_PC - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - mov x3, xINST - bl MterpInvokePolymorphic - cbz w0, MterpException - FETCH_ADVANCE_INST 4 - bl MterpShouldSwitchInterpreters - cbnz w0, MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_polymorphic_range: /* 0xfb */ -/* File: arm64/op_invoke_polymorphic_range.S */ -/* File: arm64/invoke_polymorphic.S */ - /* - * invoke-polymorphic handler wrapper. - */ - /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ - .extern MterpInvokePolymorphicRange - EXPORT_PC - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - mov x3, xINST - bl MterpInvokePolymorphicRange - cbz w0, MterpException - FETCH_ADVANCE_INST 4 - bl MterpShouldSwitchInterpreters - cbnz w0, MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_custom: /* 0xfc */ -/* File: arm64/op_invoke_custom.S */ -/* File: arm64/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeCustom - EXPORT_PC - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - mov x3, xINST - bl MterpInvokeCustom - cbz w0, MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cbnz w0, MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_custom_range: /* 0xfd */ -/* File: arm64/op_invoke_custom_range.S */ -/* File: arm64/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeCustomRange - EXPORT_PC - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - mov x3, xINST - bl MterpInvokeCustomRange - cbz w0, MterpException - FETCH_ADVANCE_INST 3 - bl MterpShouldSwitchInterpreters - cbnz w0, MterpFallback - GET_INST_OPCODE ip - GOTO_OPCODE ip - - - -/* ------------------------------ */ - .balign 128 -.L_op_const_method_handle: /* 0xfe */ -/* File: arm64/op_const_method_handle.S */ -/* File: arm64/const.S */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstMethodHandle - EXPORT_PC - FETCH w0, 1 // w0<- BBBB - lsr w1, wINST, #8 // w1<- AA - add x2, xFP, #OFF_FP_SHADOWFRAME - mov x3, xSELF - bl MterpConstMethodHandle // (index, tgt_reg, shadow_frame, self) - PREFETCH_INST 2 // load rINST - cbnz w0, MterpPossibleException // let reference interpreter deal with it. - ADVANCE 2 // advance rPC - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_const_method_type: /* 0xff */ -/* File: arm64/op_const_method_type.S */ -/* File: arm64/const.S */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstMethodType - EXPORT_PC - FETCH w0, 1 // w0<- BBBB - lsr w1, wINST, #8 // w1<- AA - add x2, xFP, #OFF_FP_SHADOWFRAME - mov x3, xSELF - bl MterpConstMethodType // (index, tgt_reg, shadow_frame, self) - PREFETCH_INST 2 // load rINST - cbnz w0, MterpPossibleException // let reference interpreter deal with it. - ADVANCE 2 // advance rPC - GET_INST_OPCODE ip // extract opcode from rINST - GOTO_OPCODE ip // jump to next instruction - - - .balign 128 -/* File: arm64/instruction_end.S */ - - .type artMterpAsmInstructionEnd, #object - .hidden artMterpAsmInstructionEnd - .global artMterpAsmInstructionEnd -artMterpAsmInstructionEnd: - - -/* - * =========================================================================== - * Sister implementations - * =========================================================================== - */ -/* File: arm64/instruction_start_sister.S */ - - .type artMterpAsmSisterStart, #object - .hidden artMterpAsmSisterStart - .global artMterpAsmSisterStart - .text - .balign 4 -artMterpAsmSisterStart: - -/* File: arm64/instruction_end_sister.S */ - - .type artMterpAsmSisterEnd, #object - .hidden artMterpAsmSisterEnd - .global artMterpAsmSisterEnd -artMterpAsmSisterEnd: - -/* File: arm64/footer.S */ -/* - * =========================================================================== - * Common subroutines and data - * =========================================================================== - */ - - -/* - * We've detected a condition that will result in an exception, but the exception - * has not yet been thrown. Just bail out to the reference interpreter to deal with it. - * TUNING: for consistency, we may want to just go ahead and handle these here. - */ -common_errDivideByZero: - EXPORT_PC -#if MTERP_LOGGING - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - bl MterpLogDivideByZeroException -#endif - b MterpCommonFallback - -common_errArrayIndex: - EXPORT_PC -#if MTERP_LOGGING - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - bl MterpLogArrayIndexException -#endif - b MterpCommonFallback - -common_errNegativeArraySize: - EXPORT_PC -#if MTERP_LOGGING - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - bl MterpLogNegativeArraySizeException -#endif - b MterpCommonFallback - -common_errNoSuchMethod: - EXPORT_PC -#if MTERP_LOGGING - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - bl MterpLogNoSuchMethodException -#endif - b MterpCommonFallback - -common_errNullObject: - EXPORT_PC -#if MTERP_LOGGING - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - bl MterpLogNullObjectException -#endif - b MterpCommonFallback - -common_exceptionThrown: - EXPORT_PC -#if MTERP_LOGGING - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - bl MterpLogExceptionThrownException -#endif - b MterpCommonFallback - -MterpSuspendFallback: - EXPORT_PC -#if MTERP_LOGGING - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - ldr x2, [xSELF, #THREAD_FLAGS_OFFSET] - bl MterpLogSuspendFallback -#endif - b MterpCommonFallback - -/* - * If we're here, something is out of the ordinary. If there is a pending - * exception, handle it. Otherwise, roll back and retry with the reference - * interpreter. - */ -MterpPossibleException: - ldr x0, [xSELF, #THREAD_EXCEPTION_OFFSET] - cbz x0, MterpFallback // If not, fall back to reference interpreter. - /* intentional fallthrough - handle pending exception. */ -/* - * On return from a runtime helper routine, we've found a pending exception. - * Can we handle it here - or need to bail out to caller? - * - */ -MterpException: - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - bl MterpHandleException // (self, shadow_frame) - cbz w0, MterpExceptionReturn // no local catch, back to caller. - ldr x0, [xFP, #OFF_FP_DEX_INSTRUCTIONS] - ldr w1, [xFP, #OFF_FP_DEX_PC] - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] - add xPC, x0, x1, lsl #1 // generate new dex_pc_ptr - /* Do we need to switch interpreters? */ - bl MterpShouldSwitchInterpreters - cbnz w0, MterpFallback - /* resume execution at catch block */ - EXPORT_PC - FETCH_INST - GET_INST_OPCODE ip - GOTO_OPCODE ip - /* NOTE: no fallthrough */ -/* - * Common handling for branches with support for Jit profiling. - * On entry: - * wINST <= signed offset - * wPROFILE <= signed hotness countdown (expanded to 32 bits) - * condition bits <= set to establish sign of offset (use "NoFlags" entry if not) - * - * We have quite a few different cases for branch profiling, OSR detection and - * suspend check support here. - * - * Taken backward branches: - * If profiling active, do hotness countdown and report if we hit zero. - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * Is there a pending suspend request? If so, suspend. - * - * Taken forward branches and not-taken backward branches: - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * - * Our most common case is expected to be a taken backward branch with active jit profiling, - * but no full OSR check and no pending suspend request. - * Next most common case is not-taken branch with no full OSR check. - * - */ -MterpCommonTakenBranchNoFlags: - cmp wINST, #0 - b.gt .L_forward_branch // don't add forward branches to hotness - tbnz wPROFILE, #31, .L_no_count_backwards // go if negative - subs wPROFILE, wPROFILE, #1 // countdown - b.eq .L_add_batch // counted down to zero - report -.L_resume_backward_branch: - ldr lr, [xSELF, #THREAD_FLAGS_OFFSET] - add w2, wINST, wINST // w2<- byte offset - FETCH_ADVANCE_INST_RB w2 // update rPC, load wINST - REFRESH_IBASE - ands lr, lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - b.ne .L_suspend_request_pending - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - -.L_suspend_request_pending: - EXPORT_PC - mov x0, xSELF - bl MterpSuspendCheck // (self) - cbnz x0, MterpFallback - REFRESH_IBASE // might have changed during suspend - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - -.L_no_count_backwards: - cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? - b.ne .L_resume_backward_branch - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xINST - EXPORT_PC - bl MterpMaybeDoOnStackReplacement // (self, shadow_frame, offset) - cbnz x0, MterpOnStackReplacement - b .L_resume_backward_branch - -.L_forward_branch: - cmp wPROFILE, #JIT_CHECK_OSR // possible OSR re-entry? - b.eq .L_check_osr_forward -.L_resume_forward_branch: - add w2, wINST, wINST // w2<- byte offset - FETCH_ADVANCE_INST_RB w2 // update rPC, load wINST - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - -.L_check_osr_forward: - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xINST - EXPORT_PC - bl MterpMaybeDoOnStackReplacement // (self, shadow_frame, offset) - cbnz x0, MterpOnStackReplacement - b .L_resume_forward_branch - -.L_add_batch: - add x1, xFP, #OFF_FP_SHADOWFRAME - strh wPROFILE, [x1, #SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET] - ldr x0, [xFP, #OFF_FP_METHOD] - mov x2, xSELF - bl MterpAddHotnessBatch // (method, shadow_frame, self) - mov wPROFILE, w0 // restore new hotness countdown to wPROFILE - b .L_no_count_backwards - -/* - * Entered from the conditional branch handlers when OSR check request active on - * not-taken path. All Dalvik not-taken conditional branch offsets are 2. - */ -.L_check_not_taken_osr: - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, #2 - EXPORT_PC - bl MterpMaybeDoOnStackReplacement // (self, shadow_frame, offset) - cbnz x0, MterpOnStackReplacement - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - - -/* - * Check for suspend check request. Assumes wINST already loaded, xPC advanced and - * still needs to get the opcode and branch to it, and flags are in lr. - */ -MterpCheckSuspendAndContinue: - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh xIBASE - ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - b.ne check1 - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction -check1: - EXPORT_PC - mov x0, xSELF - bl MterpSuspendCheck // (self) - cbnz x0, MterpFallback // Something in the environment changed, switch interpreters - GET_INST_OPCODE ip // extract opcode from wINST - GOTO_OPCODE ip // jump to next instruction - -/* - * On-stack replacement has happened, and now we've returned from the compiled method. - */ -MterpOnStackReplacement: -#if MTERP_LOGGING - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - sxtw x2, wINST - bl MterpLogOSR -#endif - mov x0, #1 // Signal normal return - b MterpDone - -/* - * Bail out to reference interpreter. - */ -MterpFallback: - EXPORT_PC -#if MTERP_LOGGING - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - bl MterpLogFallback -#endif -MterpCommonFallback: - mov x0, #0 // signal retry with reference interpreter. - b MterpDone - -/* - * We pushed some registers on the stack in ExecuteMterpImpl, then saved - * SP and LR. Here we restore SP, restore the registers, and then restore - * LR to PC. - * - * On entry: - * uint32_t* xFP (should still be live, pointer to base of vregs) - */ -MterpExceptionReturn: - mov x0, #1 // signal return to caller. - b MterpDone -MterpReturn: - ldr x2, [xFP, #OFF_FP_RESULT_REGISTER] - str x0, [x2] - mov x0, #1 // signal return to caller. -MterpDone: -/* - * At this point, we expect wPROFILE to be non-zero. If negative, hotness is disabled or we're - * checking for OSR. If greater than zero, we might have unreported hotness to register - * (the difference between the ending wPROFILE and the cached hotness counter). wPROFILE - * should only reach zero immediately after a hotness decrement, and is then reset to either - * a negative special state or the new non-zero countdown value. - */ - cmp wPROFILE, #0 - bgt MterpProfileActive // if > 0, we may have some counts to report. - .cfi_remember_state - RESTORE_TWO_REGS fp, lr, 64 - RESTORE_TWO_REGS xPC, xFP, 48 - RESTORE_TWO_REGS xSELF, xINST, 32 - RESTORE_TWO_REGS xIBASE, xREFS, 16 - RESTORE_TWO_REGS_DECREASE_FRAME xPROFILE, x27, 80 - ret - .cfi_restore_state // Reset unwind info so following code unwinds. - .cfi_def_cfa_offset 80 // workaround for clang bug: 31975598 - -MterpProfileActive: - mov xINST, x0 // stash return value - /* Report cached hotness counts */ - ldr x0, [xFP, #OFF_FP_METHOD] - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xSELF - strh wPROFILE, [x1, #SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET] - bl MterpAddHotnessBatch // (method, shadow_frame, self) - mov x0, xINST // restore return value - RESTORE_TWO_REGS fp, lr, 64 - RESTORE_TWO_REGS xPC, xFP, 48 - RESTORE_TWO_REGS xSELF, xINST, 32 - RESTORE_TWO_REGS xIBASE, xREFS, 16 - RESTORE_TWO_REGS_DECREASE_FRAME xPROFILE, x27, 80 - ret - - -/* File: arm64/instruction_start_alt.S */ - - .type artMterpAsmAltInstructionStart, #object - .hidden artMterpAsmAltInstructionStart - .global artMterpAsmAltInstructionStart -artMterpAsmAltInstructionStart = .L_ALT_op_nop - .text - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_nop: /* 0x00 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (0 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move: /* 0x01 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (1 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_from16: /* 0x02 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (2 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_16: /* 0x03 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (3 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_wide: /* 0x04 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (4 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_wide_from16: /* 0x05 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (5 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_wide_16: /* 0x06 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (6 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_object: /* 0x07 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (7 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_object_from16: /* 0x08 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (8 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_object_16: /* 0x09 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (9 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_result: /* 0x0a */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (10 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_result_wide: /* 0x0b */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (11 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_result_object: /* 0x0c */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (12 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_exception: /* 0x0d */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (13 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_void: /* 0x0e */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (14 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return: /* 0x0f */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (15 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_wide: /* 0x10 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (16 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_object: /* 0x11 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (17 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_4: /* 0x12 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (18 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_16: /* 0x13 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (19 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const: /* 0x14 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (20 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_high16: /* 0x15 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (21 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide_16: /* 0x16 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (22 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide_32: /* 0x17 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (23 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide: /* 0x18 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (24 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide_high16: /* 0x19 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (25 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_string: /* 0x1a */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (26 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_string_jumbo: /* 0x1b */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (27 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_class: /* 0x1c */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (28 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_monitor_enter: /* 0x1d */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (29 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_monitor_exit: /* 0x1e */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (30 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_check_cast: /* 0x1f */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (31 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_instance_of: /* 0x20 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (32 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_array_length: /* 0x21 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (33 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_new_instance: /* 0x22 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (34 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_new_array: /* 0x23 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (35 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_filled_new_array: /* 0x24 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (36 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_filled_new_array_range: /* 0x25 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (37 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_fill_array_data: /* 0x26 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (38 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_throw: /* 0x27 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (39 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_goto: /* 0x28 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (40 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_goto_16: /* 0x29 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (41 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_goto_32: /* 0x2a */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (42 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_packed_switch: /* 0x2b */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (43 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sparse_switch: /* 0x2c */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (44 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpl_float: /* 0x2d */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (45 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpg_float: /* 0x2e */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (46 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpl_double: /* 0x2f */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (47 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpg_double: /* 0x30 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (48 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmp_long: /* 0x31 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (49 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_eq: /* 0x32 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (50 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_ne: /* 0x33 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (51 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_lt: /* 0x34 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (52 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_ge: /* 0x35 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (53 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_gt: /* 0x36 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (54 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_le: /* 0x37 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (55 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_eqz: /* 0x38 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (56 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_nez: /* 0x39 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (57 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_ltz: /* 0x3a */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (58 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_gez: /* 0x3b */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (59 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_gtz: /* 0x3c */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (60 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_lez: /* 0x3d */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (61 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_3e: /* 0x3e */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (62 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_3f: /* 0x3f */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (63 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_40: /* 0x40 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (64 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_41: /* 0x41 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (65 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_42: /* 0x42 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (66 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_43: /* 0x43 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (67 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget: /* 0x44 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (68 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_wide: /* 0x45 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (69 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_object: /* 0x46 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (70 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_boolean: /* 0x47 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (71 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_byte: /* 0x48 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (72 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_char: /* 0x49 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (73 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_short: /* 0x4a */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (74 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput: /* 0x4b */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (75 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_wide: /* 0x4c */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (76 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_object: /* 0x4d */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (77 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_boolean: /* 0x4e */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (78 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_byte: /* 0x4f */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (79 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_char: /* 0x50 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (80 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_short: /* 0x51 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (81 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget: /* 0x52 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (82 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_wide: /* 0x53 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (83 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_object: /* 0x54 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (84 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_boolean: /* 0x55 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (85 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_byte: /* 0x56 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (86 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_char: /* 0x57 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (87 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_short: /* 0x58 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (88 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput: /* 0x59 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (89 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_wide: /* 0x5a */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (90 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_object: /* 0x5b */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (91 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_boolean: /* 0x5c */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (92 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_byte: /* 0x5d */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (93 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_char: /* 0x5e */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (94 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_short: /* 0x5f */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (95 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget: /* 0x60 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (96 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_wide: /* 0x61 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (97 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_object: /* 0x62 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (98 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_boolean: /* 0x63 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (99 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_byte: /* 0x64 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (100 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_char: /* 0x65 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (101 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_short: /* 0x66 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (102 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput: /* 0x67 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (103 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_wide: /* 0x68 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (104 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_object: /* 0x69 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (105 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_boolean: /* 0x6a */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (106 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_byte: /* 0x6b */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (107 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_char: /* 0x6c */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (108 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_short: /* 0x6d */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (109 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual: /* 0x6e */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (110 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_super: /* 0x6f */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (111 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_direct: /* 0x70 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (112 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_static: /* 0x71 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (113 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_interface: /* 0x72 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (114 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_void_no_barrier: /* 0x73 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (115 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual_range: /* 0x74 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (116 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_super_range: /* 0x75 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (117 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_direct_range: /* 0x76 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (118 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_static_range: /* 0x77 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (119 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_interface_range: /* 0x78 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (120 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_79: /* 0x79 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (121 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_7a: /* 0x7a */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (122 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_int: /* 0x7b */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (123 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_not_int: /* 0x7c */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (124 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_long: /* 0x7d */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (125 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_not_long: /* 0x7e */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (126 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_float: /* 0x7f */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (127 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_double: /* 0x80 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (128 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_long: /* 0x81 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (129 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_float: /* 0x82 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (130 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_double: /* 0x83 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (131 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_long_to_int: /* 0x84 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (132 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_long_to_float: /* 0x85 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (133 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_long_to_double: /* 0x86 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (134 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_float_to_int: /* 0x87 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (135 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_float_to_long: /* 0x88 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (136 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_float_to_double: /* 0x89 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (137 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_double_to_int: /* 0x8a */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (138 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_double_to_long: /* 0x8b */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (139 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_double_to_float: /* 0x8c */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (140 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_byte: /* 0x8d */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (141 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_char: /* 0x8e */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (142 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_short: /* 0x8f */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (143 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int: /* 0x90 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (144 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_int: /* 0x91 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (145 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int: /* 0x92 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (146 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int: /* 0x93 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (147 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int: /* 0x94 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (148 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int: /* 0x95 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (149 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int: /* 0x96 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (150 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int: /* 0x97 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (151 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_int: /* 0x98 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (152 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_int: /* 0x99 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (153 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_int: /* 0x9a */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (154 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_long: /* 0x9b */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (155 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_long: /* 0x9c */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (156 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_long: /* 0x9d */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (157 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_long: /* 0x9e */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (158 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_long: /* 0x9f */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (159 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_long: /* 0xa0 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (160 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_long: /* 0xa1 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (161 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_long: /* 0xa2 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (162 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_long: /* 0xa3 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (163 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_long: /* 0xa4 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (164 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_long: /* 0xa5 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (165 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_float: /* 0xa6 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (166 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_float: /* 0xa7 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (167 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_float: /* 0xa8 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (168 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_float: /* 0xa9 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (169 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_float: /* 0xaa */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (170 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_double: /* 0xab */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (171 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_double: /* 0xac */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (172 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_double: /* 0xad */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (173 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_double: /* 0xae */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (174 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_double: /* 0xaf */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (175 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int_2addr: /* 0xb0 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (176 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_int_2addr: /* 0xb1 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (177 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int_2addr: /* 0xb2 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (178 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int_2addr: /* 0xb3 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (179 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int_2addr: /* 0xb4 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (180 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int_2addr: /* 0xb5 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (181 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int_2addr: /* 0xb6 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (182 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int_2addr: /* 0xb7 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (183 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_int_2addr: /* 0xb8 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (184 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_int_2addr: /* 0xb9 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (185 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_int_2addr: /* 0xba */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (186 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_long_2addr: /* 0xbb */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (187 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_long_2addr: /* 0xbc */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (188 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_long_2addr: /* 0xbd */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (189 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_long_2addr: /* 0xbe */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (190 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_long_2addr: /* 0xbf */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (191 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_long_2addr: /* 0xc0 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (192 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_long_2addr: /* 0xc1 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (193 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_long_2addr: /* 0xc2 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (194 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_long_2addr: /* 0xc3 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (195 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_long_2addr: /* 0xc4 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (196 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_long_2addr: /* 0xc5 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (197 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_float_2addr: /* 0xc6 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (198 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_float_2addr: /* 0xc7 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (199 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_float_2addr: /* 0xc8 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (200 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_float_2addr: /* 0xc9 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (201 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_float_2addr: /* 0xca */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (202 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_double_2addr: /* 0xcb */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (203 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_double_2addr: /* 0xcc */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (204 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_double_2addr: /* 0xcd */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (205 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_double_2addr: /* 0xce */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (206 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_double_2addr: /* 0xcf */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (207 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int_lit16: /* 0xd0 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (208 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rsub_int: /* 0xd1 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (209 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int_lit16: /* 0xd2 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (210 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int_lit16: /* 0xd3 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (211 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int_lit16: /* 0xd4 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (212 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int_lit16: /* 0xd5 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (213 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int_lit16: /* 0xd6 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (214 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int_lit16: /* 0xd7 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (215 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int_lit8: /* 0xd8 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (216 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rsub_int_lit8: /* 0xd9 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (217 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int_lit8: /* 0xda */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (218 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int_lit8: /* 0xdb */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (219 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int_lit8: /* 0xdc */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (220 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int_lit8: /* 0xdd */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (221 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int_lit8: /* 0xde */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (222 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int_lit8: /* 0xdf */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (223 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_int_lit8: /* 0xe0 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (224 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_int_lit8: /* 0xe1 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (225 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_int_lit8: /* 0xe2 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (226 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_quick: /* 0xe3 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (227 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_wide_quick: /* 0xe4 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (228 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_object_quick: /* 0xe5 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (229 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_quick: /* 0xe6 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (230 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_wide_quick: /* 0xe7 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (231 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_object_quick: /* 0xe8 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (232 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual_quick: /* 0xe9 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (233 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual_range_quick: /* 0xea */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (234 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_boolean_quick: /* 0xeb */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (235 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_byte_quick: /* 0xec */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (236 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_char_quick: /* 0xed */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (237 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_short_quick: /* 0xee */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (238 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_boolean_quick: /* 0xef */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (239 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_byte_quick: /* 0xf0 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (240 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_char_quick: /* 0xf1 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (241 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_short_quick: /* 0xf2 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (242 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f3: /* 0xf3 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (243 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f4: /* 0xf4 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (244 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f5: /* 0xf5 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (245 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f6: /* 0xf6 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (246 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f7: /* 0xf7 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (247 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f8: /* 0xf8 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (248 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f9: /* 0xf9 */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (249 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_polymorphic: /* 0xfa */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (250 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_polymorphic_range: /* 0xfb */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (251 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_custom: /* 0xfc */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (252 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_custom_range: /* 0xfd */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (253 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_method_handle: /* 0xfe */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (254 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_method_type: /* 0xff */ -/* File: arm64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - ldr xIBASE, [xSELF, #THREAD_CURRENT_IBASE_OFFSET] // refresh IBASE. - adr lr, artMterpAsmInstructionStart + (255 * 128) // Addr of primary handler. - mov x0, xSELF - add x1, xFP, #OFF_FP_SHADOWFRAME - mov x2, xPC - b MterpCheckBefore // (self, shadow_frame, dex_pc_ptr) Note: tail call. - - .balign 128 -/* File: arm64/instruction_end_alt.S */ - - .type artMterpAsmAltInstructionEnd, #object - .hidden artMterpAsmAltInstructionEnd - .global artMterpAsmAltInstructionEnd -artMterpAsmAltInstructionEnd: - -/* File: arm64/close_cfi.S */ -// Close out the cfi info. We're treating mterp as a single function. - -END ExecuteMterpImpl - - diff --git a/runtime/interpreter/mterp/out/mterp_mips.S b/runtime/interpreter/mterp/out/mterp_mips.S deleted file mode 100644 index 1f5bea0873d62bd8ca262825b82007341c51fee6..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/out/mterp_mips.S +++ /dev/null @@ -1,12389 +0,0 @@ -/* - * This file was generated automatically by gen-mterp.py for 'mips'. - * - * --> DO NOT EDIT <-- - */ - -/* File: mips/header.S */ -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - Art assembly interpreter notes: - - First validate assembly code by implementing ExecuteXXXImpl() style body (doesn't - handle invoke, allows higher-level code to create frame & shadow frame. - - Once that's working, support direct entry code & eliminate shadow frame (and - excess locals allocation. - - Some (hopefully) temporary ugliness. We'll treat rFP as pointing to the - base of the vreg array within the shadow frame. Access the other fields, - dex_pc_, method_ and number_of_vregs_ via negative offsets. For now, we'll continue - the shadow frame mechanism of double-storing object references - via rFP & - number_of_vregs_. - - */ - -#include "asm_support.h" -#include "interpreter/cfi_asm_support.h" - -#if (__mips==32) && (__mips_isa_rev>=2) -#define MIPS32REVGE2 /* mips32r2 and greater */ -#if (__mips==32) && (__mips_isa_rev>=5) -#define FPU64 /* 64 bit FPU */ -#if (__mips==32) && (__mips_isa_rev>=6) -#define MIPS32REVGE6 /* mips32r6 and greater */ -#endif -#endif -#endif - -/* MIPS definitions and declarations - - reg nick purpose - s0 rPC interpreted program counter, used for fetching instructions - s1 rFP interpreted frame pointer, used for accessing locals and args - s2 rSELF self (Thread) pointer - s3 rIBASE interpreted instruction base pointer, used for computed goto - s4 rINST first 16-bit code unit of current instruction - s5 rOBJ object pointer - s6 rREFS base of object references in shadow frame (ideally, we'll get rid of this later). - s7 rTEMP used as temp storage that can survive a function call - s8 rPROFILE branch profiling countdown - -*/ - -/* single-purpose registers, given names for clarity */ -#define rPC s0 -#define CFI_DEX 16 // DWARF register number of the register holding dex-pc (s0). -#define CFI_TMP 4 // DWARF register number of the first argument register (a0). -#define rFP s1 -#define rSELF s2 -#define rIBASE s3 -#define rINST s4 -#define rOBJ s5 -#define rREFS s6 -#define rTEMP s7 -#define rPROFILE s8 - -#define rARG0 a0 -#define rARG1 a1 -#define rARG2 a2 -#define rARG3 a3 -#define rRESULT0 v0 -#define rRESULT1 v1 - -/* GP register definitions */ -#define zero $0 /* always zero */ -#define AT $at /* assembler temp */ -#define v0 $2 /* return value */ -#define v1 $3 -#define a0 $4 /* argument registers */ -#define a1 $5 -#define a2 $6 -#define a3 $7 -#define t0 $8 /* temp registers (not saved across subroutine calls) */ -#define t1 $9 -#define t2 $10 -#define t3 $11 -#define t4 $12 -#define t5 $13 -#define t6 $14 -#define t7 $15 -#define ta0 $12 /* alias */ -#define ta1 $13 -#define ta2 $14 -#define ta3 $15 -#define s0 $16 /* saved across subroutine calls (callee saved) */ -#define s1 $17 -#define s2 $18 -#define s3 $19 -#define s4 $20 -#define s5 $21 -#define s6 $22 -#define s7 $23 -#define t8 $24 /* two more temp registers */ -#define t9 $25 -#define k0 $26 /* kernel temporary */ -#define k1 $27 -#define gp $28 /* global pointer */ -#define sp $29 /* stack pointer */ -#define s8 $30 /* one more callee saved */ -#define ra $31 /* return address */ - -/* FP register definitions */ -#define fv0 $f0 -#define fv0f $f1 -#define fv1 $f2 -#define fv1f $f3 -#define fa0 $f12 -#define fa0f $f13 -#define fa1 $f14 -#define fa1f $f15 -#define ft0 $f4 -#define ft0f $f5 -#define ft1 $f6 -#define ft1f $f7 -#define ft2 $f8 -#define ft2f $f9 -#define ft3 $f10 -#define ft3f $f11 -#define ft4 $f16 -#define ft4f $f17 -#define ft5 $f18 -#define ft5f $f19 -#define fs0 $f20 -#define fs0f $f21 -#define fs1 $f22 -#define fs1f $f23 -#define fs2 $f24 -#define fs2f $f25 -#define fs3 $f26 -#define fs3f $f27 -#define fs4 $f28 -#define fs4f $f29 -#define fs5 $f30 -#define fs5f $f31 - -#ifndef MIPS32REVGE6 -#define fcc0 $fcc0 -#define fcc1 $fcc1 -#endif - -#ifdef MIPS32REVGE2 -#define SEB(rd, rt) \ - seb rd, rt -#define SEH(rd, rt) \ - seh rd, rt -#define INSERT_HIGH_HALF(rd_lo, rt_hi) \ - ins rd_lo, rt_hi, 16, 16 -#else -#define SEB(rd, rt) \ - sll rd, rt, 24; \ - sra rd, rd, 24 -#define SEH(rd, rt) \ - sll rd, rt, 16; \ - sra rd, rd, 16 -/* Clobbers rt_hi on pre-R2. */ -#define INSERT_HIGH_HALF(rd_lo, rt_hi) \ - sll rt_hi, rt_hi, 16; \ - or rd_lo, rt_hi -#endif - -#ifdef FPU64 -#define MOVE_TO_FPU_HIGH(r, flo, fhi) \ - mthc1 r, flo -#else -#define MOVE_TO_FPU_HIGH(r, flo, fhi) \ - mtc1 r, fhi -#endif - -#ifdef MIPS32REVGE6 -#define JR(rt) \ - jic rt, 0 -#define LSA(rd, rs, rt, sa) \ - .if sa; \ - lsa rd, rs, rt, sa; \ - .else; \ - addu rd, rs, rt; \ - .endif -#else -#define JR(rt) \ - jalr zero, rt -#define LSA(rd, rs, rt, sa) \ - .if sa; \ - .set push; \ - .set noat; \ - sll AT, rs, sa; \ - addu rd, AT, rt; \ - .set pop; \ - .else; \ - addu rd, rs, rt; \ - .endif -#endif - -/* - * Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs. So, - * to access other shadow frame fields, we need to use a backwards offset. Define those here. - */ -#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) -#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) -#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) -#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) -#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) -#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) -#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) -#define OFF_FP_DEX_INSTRUCTIONS OFF_FP(SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET) -#define OFF_FP_SHADOWFRAME OFF_FP(0) - -#define MTERP_PROFILE_BRANCHES 1 -#define MTERP_LOGGING 0 - -/* - * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must - * be done *before* something throws. - * - * It's okay to do this more than once. - * - * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped - * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction - * offset into the code_items_[] array. For effiency, we will "export" the - * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC - * to convert to a dex pc when needed. - */ -#define EXPORT_PC() \ - sw rPC, OFF_FP_DEX_PC_PTR(rFP) - -#define EXPORT_DEX_PC(tmp) \ - lw tmp, OFF_FP_DEX_INSTRUCTIONS(rFP); \ - sw rPC, OFF_FP_DEX_PC_PTR(rFP); \ - subu tmp, rPC, tmp; \ - sra tmp, tmp, 1; \ - sw tmp, OFF_FP_DEX_PC(rFP) - -/* - * Fetch the next instruction from rPC into rINST. Does not advance rPC. - */ -#define FETCH_INST() lhu rINST, (rPC) - -/* - * Fetch the next instruction from the specified offset. Advances rPC - * to point to the next instruction. "_count" is in 16-bit code units. - * - * This must come AFTER anything that can throw an exception, or the - * exception catch may miss. (This also implies that it must come after - * EXPORT_PC().) - */ -#define FETCH_ADVANCE_INST(_count) \ - lhu rINST, ((_count)*2)(rPC); \ - addu rPC, rPC, ((_count) * 2) - -/* - * Similar to FETCH_ADVANCE_INST, but does not update rPC. Used to load - * rINST ahead of possible exception point. Be sure to manually advance rPC - * later. - */ -#define PREFETCH_INST(_count) lhu rINST, ((_count)*2)(rPC) - -/* Advance rPC by some number of code units. */ -#define ADVANCE(_count) addu rPC, rPC, ((_count) * 2) - -/* - * Fetch the next instruction from an offset specified by rd. Updates - * rPC to point to the next instruction. "rd" must specify the distance - * in bytes, *not* 16-bit code units, and may be a signed value. - */ -#define FETCH_ADVANCE_INST_RB(rd) \ - addu rPC, rPC, rd; \ - lhu rINST, (rPC) - -/* - * Fetch a half-word code unit from an offset past the current PC. The - * "_count" value is in 16-bit code units. Does not advance rPC. - * - * The "_S" variant works the same but treats the value as signed. - */ -#define FETCH(rd, _count) lhu rd, ((_count) * 2)(rPC) -#define FETCH_S(rd, _count) lh rd, ((_count) * 2)(rPC) - -/* - * Fetch one byte from an offset past the current PC. Pass in the same - * "_count" as you would for FETCH, and an additional 0/1 indicating which - * byte of the halfword you want (lo/hi). - */ -#define FETCH_B(rd, _count, _byte) lbu rd, ((_count) * 2 + _byte)(rPC) - -/* - * Put the instruction's opcode field into the specified register. - */ -#define GET_INST_OPCODE(rd) and rd, rINST, 0xFF - -/* - * Transform opcode into branch target address. - */ -#define GET_OPCODE_TARGET(rd) \ - sll rd, rd, 7; \ - addu rd, rIBASE, rd - -/* - * Begin executing the opcode in rd. - */ -#define GOTO_OPCODE(rd) \ - GET_OPCODE_TARGET(rd); \ - JR(rd) - -/* - * Get/set the 32-bit value from a Dalvik register. - */ -#define GET_VREG(rd, rix) LOAD_eas2(rd, rFP, rix) - -#define GET_VREG_F(rd, rix) \ - .set noat; \ - EAS2(AT, rFP, rix); \ - l.s rd, (AT); \ - .set at - -#ifdef MIPS32REVGE6 -#define SET_VREG(rd, rix) \ - lsa t8, rix, rFP, 2; \ - sw rd, 0(t8); \ - lsa t8, rix, rREFS, 2; \ - sw zero, 0(t8) -#else -#define SET_VREG(rd, rix) \ - .set noat; \ - sll AT, rix, 2; \ - addu t8, rFP, AT; \ - sw rd, 0(t8); \ - addu t8, rREFS, AT; \ - .set at; \ - sw zero, 0(t8) -#endif - -#ifdef MIPS32REVGE6 -#define SET_VREG_OBJECT(rd, rix) \ - lsa t8, rix, rFP, 2; \ - sw rd, 0(t8); \ - lsa t8, rix, rREFS, 2; \ - sw rd, 0(t8) -#else -#define SET_VREG_OBJECT(rd, rix) \ - .set noat; \ - sll AT, rix, 2; \ - addu t8, rFP, AT; \ - sw rd, 0(t8); \ - addu t8, rREFS, AT; \ - .set at; \ - sw rd, 0(t8) -#endif - -#ifdef MIPS32REVGE6 -#define SET_VREG64(rlo, rhi, rix) \ - lsa t8, rix, rFP, 2; \ - sw rlo, 0(t8); \ - sw rhi, 4(t8); \ - lsa t8, rix, rREFS, 2; \ - sw zero, 0(t8); \ - sw zero, 4(t8) -#else -#define SET_VREG64(rlo, rhi, rix) \ - .set noat; \ - sll AT, rix, 2; \ - addu t8, rFP, AT; \ - sw rlo, 0(t8); \ - sw rhi, 4(t8); \ - addu t8, rREFS, AT; \ - .set at; \ - sw zero, 0(t8); \ - sw zero, 4(t8) -#endif - -#ifdef MIPS32REVGE6 -#define SET_VREG_F(rd, rix) \ - lsa t8, rix, rFP, 2; \ - s.s rd, 0(t8); \ - lsa t8, rix, rREFS, 2; \ - sw zero, 0(t8) -#else -#define SET_VREG_F(rd, rix) \ - .set noat; \ - sll AT, rix, 2; \ - addu t8, rFP, AT; \ - s.s rd, 0(t8); \ - addu t8, rREFS, AT; \ - .set at; \ - sw zero, 0(t8) -#endif - -#ifdef MIPS32REVGE6 -#define SET_VREG64_F(rlo, rhi, rix) \ - lsa t8, rix, rFP, 2; \ - .set noat; \ - mfhc1 AT, rlo; \ - s.s rlo, 0(t8); \ - sw AT, 4(t8); \ - .set at; \ - lsa t8, rix, rREFS, 2; \ - sw zero, 0(t8); \ - sw zero, 4(t8) -#elif defined(FPU64) -#define SET_VREG64_F(rlo, rhi, rix) \ - .set noat; \ - sll AT, rix, 2; \ - addu t8, rREFS, AT; \ - sw zero, 0(t8); \ - sw zero, 4(t8); \ - addu t8, rFP, AT; \ - mfhc1 AT, rlo; \ - sw AT, 4(t8); \ - .set at; \ - s.s rlo, 0(t8) -#else -#define SET_VREG64_F(rlo, rhi, rix) \ - .set noat; \ - sll AT, rix, 2; \ - addu t8, rFP, AT; \ - s.s rlo, 0(t8); \ - s.s rhi, 4(t8); \ - addu t8, rREFS, AT; \ - .set at; \ - sw zero, 0(t8); \ - sw zero, 4(t8) -#endif - -/* Combination of the SET_VREG and GOTO_OPCODE functions to save 1 instruction */ -#ifdef MIPS32REVGE6 -#define SET_VREG_GOTO(rd, rix, dst) \ - .set noreorder; \ - GET_OPCODE_TARGET(dst); \ - lsa t8, rix, rFP, 2; \ - sw rd, 0(t8); \ - lsa t8, rix, rREFS, 2; \ - jalr zero, dst; \ - sw zero, 0(t8); \ - .set reorder -#else -#define SET_VREG_GOTO(rd, rix, dst) \ - .set noreorder; \ - GET_OPCODE_TARGET(dst); \ - .set noat; \ - sll AT, rix, 2; \ - addu t8, rFP, AT; \ - sw rd, 0(t8); \ - addu t8, rREFS, AT; \ - .set at; \ - jalr zero, dst; \ - sw zero, 0(t8); \ - .set reorder -#endif - -/* Combination of the SET_VREG_OBJECT and GOTO_OPCODE functions to save 1 instruction */ -#ifdef MIPS32REVGE6 -#define SET_VREG_OBJECT_GOTO(rd, rix, dst) \ - .set noreorder; \ - GET_OPCODE_TARGET(dst); \ - lsa t8, rix, rFP, 2; \ - sw rd, 0(t8); \ - lsa t8, rix, rREFS, 2; \ - jalr zero, dst; \ - sw rd, 0(t8); \ - .set reorder -#else -#define SET_VREG_OBJECT_GOTO(rd, rix, dst) \ - .set noreorder; \ - GET_OPCODE_TARGET(dst); \ - .set noat; \ - sll AT, rix, 2; \ - addu t8, rFP, AT; \ - sw rd, 0(t8); \ - addu t8, rREFS, AT; \ - .set at; \ - jalr zero, dst; \ - sw rd, 0(t8); \ - .set reorder -#endif - -/* Combination of the SET_VREG64 and GOTO_OPCODE functions to save 1 instruction */ -#ifdef MIPS32REVGE6 -#define SET_VREG64_GOTO(rlo, rhi, rix, dst) \ - .set noreorder; \ - GET_OPCODE_TARGET(dst); \ - lsa t8, rix, rFP, 2; \ - sw rlo, 0(t8); \ - sw rhi, 4(t8); \ - lsa t8, rix, rREFS, 2; \ - sw zero, 0(t8); \ - jalr zero, dst; \ - sw zero, 4(t8); \ - .set reorder -#else -#define SET_VREG64_GOTO(rlo, rhi, rix, dst) \ - .set noreorder; \ - GET_OPCODE_TARGET(dst); \ - .set noat; \ - sll AT, rix, 2; \ - addu t8, rFP, AT; \ - sw rlo, 0(t8); \ - sw rhi, 4(t8); \ - addu t8, rREFS, AT; \ - .set at; \ - sw zero, 0(t8); \ - jalr zero, dst; \ - sw zero, 4(t8); \ - .set reorder -#endif - -/* Combination of the SET_VREG_F and GOTO_OPCODE functions to save 1 instruction */ -#ifdef MIPS32REVGE6 -#define SET_VREG_F_GOTO(rd, rix, dst) \ - .set noreorder; \ - GET_OPCODE_TARGET(dst); \ - lsa t8, rix, rFP, 2; \ - s.s rd, 0(t8); \ - lsa t8, rix, rREFS, 2; \ - jalr zero, dst; \ - sw zero, 0(t8); \ - .set reorder -#else -#define SET_VREG_F_GOTO(rd, rix, dst) \ - .set noreorder; \ - GET_OPCODE_TARGET(dst); \ - .set noat; \ - sll AT, rix, 2; \ - addu t8, rFP, AT; \ - s.s rd, 0(t8); \ - addu t8, rREFS, AT; \ - .set at; \ - jalr zero, dst; \ - sw zero, 0(t8); \ - .set reorder -#endif - -/* Combination of the SET_VREG64_F and GOTO_OPCODE functions to save 1 instruction */ -#ifdef MIPS32REVGE6 -#define SET_VREG64_F_GOTO(rlo, rhi, rix, dst) \ - .set noreorder; \ - GET_OPCODE_TARGET(dst); \ - lsa t8, rix, rFP, 2; \ - .set noat; \ - mfhc1 AT, rlo; \ - s.s rlo, 0(t8); \ - sw AT, 4(t8); \ - .set at; \ - lsa t8, rix, rREFS, 2; \ - sw zero, 0(t8); \ - jalr zero, dst; \ - sw zero, 4(t8); \ - .set reorder -#elif defined(FPU64) -#define SET_VREG64_F_GOTO(rlo, rhi, rix, dst) \ - .set noreorder; \ - GET_OPCODE_TARGET(dst); \ - .set noat; \ - sll AT, rix, 2; \ - addu t8, rREFS, AT; \ - sw zero, 0(t8); \ - sw zero, 4(t8); \ - addu t8, rFP, AT; \ - mfhc1 AT, rlo; \ - sw AT, 4(t8); \ - .set at; \ - jalr zero, dst; \ - s.s rlo, 0(t8); \ - .set reorder -#else -#define SET_VREG64_F_GOTO(rlo, rhi, rix, dst) \ - .set noreorder; \ - GET_OPCODE_TARGET(dst); \ - .set noat; \ - sll AT, rix, 2; \ - addu t8, rFP, AT; \ - s.s rlo, 0(t8); \ - s.s rhi, 4(t8); \ - addu t8, rREFS, AT; \ - .set at; \ - sw zero, 0(t8); \ - jalr zero, dst; \ - sw zero, 4(t8); \ - .set reorder -#endif - -#define GET_OPA(rd) srl rd, rINST, 8 -#ifdef MIPS32REVGE2 -#define GET_OPA4(rd) ext rd, rINST, 8, 4 -#else -#define GET_OPA4(rd) GET_OPA(rd); and rd, 0xf -#endif -#define GET_OPB(rd) srl rd, rINST, 12 - -/* - * Form an Effective Address rd = rbase + roff<exception <- obj - b MterpException - -/* ------------------------------ */ - .balign 128 -.L_op_goto: /* 0x28 */ -/* File: mips/op_goto.S */ - /* - * Unconditional branch, 8-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto +AA */ - sll a0, rINST, 16 # a0 <- AAxx0000 - sra rINST, a0, 24 # rINST <- ssssssAA (sign-extended) - b MterpCommonTakenBranchNoFlags - -/* ------------------------------ */ - .balign 128 -.L_op_goto_16: /* 0x29 */ -/* File: mips/op_goto_16.S */ - /* - * Unconditional branch, 16-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto/16 +AAAA */ - FETCH_S(rINST, 1) # rINST <- ssssAAAA (sign-extended) - b MterpCommonTakenBranchNoFlags - -/* ------------------------------ */ - .balign 128 -.L_op_goto_32: /* 0x2a */ -/* File: mips/op_goto_32.S */ - /* - * Unconditional branch, 32-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - * - * Unlike most opcodes, this one is allowed to branch to itself, so - * our "backward branch" test must be "<=0" instead of "<0". - */ - /* goto/32 +AAAAAAAA */ - FETCH(rINST, 1) # rINST <- aaaa (lo) - FETCH(a1, 2) # a1 <- AAAA (hi) - INSERT_HIGH_HALF(rINST, a1) # rINST <- AAAAaaaa - b MterpCommonTakenBranchNoFlags - -/* ------------------------------ */ - .balign 128 -.L_op_packed_switch: /* 0x2b */ -/* File: mips/op_packed_switch.S */ - /* - * Handle a packed-switch or sparse-switch instruction. In both cases - * we decode it and hand it off to a helper function. - * - * We don't really expect backward branches in a switch statement, but - * they're perfectly legal, so we check for them here. - * - * for: packed-switch, sparse-switch - */ - /* op vAA, +BBBB */ - FETCH(a0, 1) # a0 <- bbbb (lo) - FETCH(a1, 2) # a1 <- BBBB (hi) - GET_OPA(a3) # a3 <- AA - INSERT_HIGH_HALF(a0, a1) # a0 <- BBBBbbbb - GET_VREG(a1, a3) # a1 <- vAA - EAS1(a0, rPC, a0) # a0 <- PC + BBBBbbbb*2 - JAL(MterpDoPackedSwitch) # a0 <- code-unit branch offset - move rINST, v0 - b MterpCommonTakenBranchNoFlags - -/* ------------------------------ */ - .balign 128 -.L_op_sparse_switch: /* 0x2c */ -/* File: mips/op_sparse_switch.S */ -/* File: mips/op_packed_switch.S */ - /* - * Handle a packed-switch or sparse-switch instruction. In both cases - * we decode it and hand it off to a helper function. - * - * We don't really expect backward branches in a switch statement, but - * they're perfectly legal, so we check for them here. - * - * for: packed-switch, sparse-switch - */ - /* op vAA, +BBBB */ - FETCH(a0, 1) # a0 <- bbbb (lo) - FETCH(a1, 2) # a1 <- BBBB (hi) - GET_OPA(a3) # a3 <- AA - INSERT_HIGH_HALF(a0, a1) # a0 <- BBBBbbbb - GET_VREG(a1, a3) # a1 <- vAA - EAS1(a0, rPC, a0) # a0 <- PC + BBBBbbbb*2 - JAL(MterpDoSparseSwitch) # a0 <- code-unit branch offset - move rINST, v0 - b MterpCommonTakenBranchNoFlags - - -/* ------------------------------ */ - .balign 128 -.L_op_cmpl_float: /* 0x2d */ -/* File: mips/op_cmpl_float.S */ - /* - * Compare two floating-point values. Puts 0(==), 1(>), or -1(<) - * into the destination register based on the comparison results. - * - * for: cmpl-float, cmpg-float - */ - /* op vAA, vBB, vCC */ - - FETCH(a0, 1) # a0 <- CCBB - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 - GET_VREG_F(ft0, a2) - GET_VREG_F(ft1, a3) -#ifdef MIPS32REVGE6 - cmp.eq.s ft2, ft0, ft1 - li rTEMP, 0 - bc1nez ft2, 1f # done if vBB == vCC (ordered) - .if 0 - cmp.lt.s ft2, ft0, ft1 - li rTEMP, -1 - bc1nez ft2, 1f # done if vBB < vCC (ordered) - li rTEMP, 1 # vBB > vCC or unordered - .else - cmp.lt.s ft2, ft1, ft0 - li rTEMP, 1 - bc1nez ft2, 1f # done if vBB > vCC (ordered) - li rTEMP, -1 # vBB < vCC or unordered - .endif -#else - c.eq.s fcc0, ft0, ft1 - li rTEMP, 0 - bc1t fcc0, 1f # done if vBB == vCC (ordered) - .if 0 - c.olt.s fcc0, ft0, ft1 - li rTEMP, -1 - bc1t fcc0, 1f # done if vBB < vCC (ordered) - li rTEMP, 1 # vBB > vCC or unordered - .else - c.olt.s fcc0, ft1, ft0 - li rTEMP, 1 - bc1t fcc0, 1f # done if vBB > vCC (ordered) - li rTEMP, -1 # vBB < vCC or unordered - .endif -#endif -1: - GET_OPA(rOBJ) - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(rTEMP, rOBJ, t0) # vAA <- rTEMP - -/* ------------------------------ */ - .balign 128 -.L_op_cmpg_float: /* 0x2e */ -/* File: mips/op_cmpg_float.S */ -/* File: mips/op_cmpl_float.S */ - /* - * Compare two floating-point values. Puts 0(==), 1(>), or -1(<) - * into the destination register based on the comparison results. - * - * for: cmpl-float, cmpg-float - */ - /* op vAA, vBB, vCC */ - - FETCH(a0, 1) # a0 <- CCBB - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 - GET_VREG_F(ft0, a2) - GET_VREG_F(ft1, a3) -#ifdef MIPS32REVGE6 - cmp.eq.s ft2, ft0, ft1 - li rTEMP, 0 - bc1nez ft2, 1f # done if vBB == vCC (ordered) - .if 1 - cmp.lt.s ft2, ft0, ft1 - li rTEMP, -1 - bc1nez ft2, 1f # done if vBB < vCC (ordered) - li rTEMP, 1 # vBB > vCC or unordered - .else - cmp.lt.s ft2, ft1, ft0 - li rTEMP, 1 - bc1nez ft2, 1f # done if vBB > vCC (ordered) - li rTEMP, -1 # vBB < vCC or unordered - .endif -#else - c.eq.s fcc0, ft0, ft1 - li rTEMP, 0 - bc1t fcc0, 1f # done if vBB == vCC (ordered) - .if 1 - c.olt.s fcc0, ft0, ft1 - li rTEMP, -1 - bc1t fcc0, 1f # done if vBB < vCC (ordered) - li rTEMP, 1 # vBB > vCC or unordered - .else - c.olt.s fcc0, ft1, ft0 - li rTEMP, 1 - bc1t fcc0, 1f # done if vBB > vCC (ordered) - li rTEMP, -1 # vBB < vCC or unordered - .endif -#endif -1: - GET_OPA(rOBJ) - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(rTEMP, rOBJ, t0) # vAA <- rTEMP - - -/* ------------------------------ */ - .balign 128 -.L_op_cmpl_double: /* 0x2f */ -/* File: mips/op_cmpl_double.S */ - /* - * Compare two floating-point values. Puts 0(==), 1(>), or -1(<) - * into the destination register based on the comparison results. - * - * For: cmpl-double, cmpg-double - */ - /* op vAA, vBB, vCC */ - - FETCH(a0, 1) # a0 <- CCBB - and rOBJ, a0, 255 # rOBJ <- BB - srl t0, a0, 8 # t0 <- CC - EAS2(rOBJ, rFP, rOBJ) # rOBJ <- &fp[BB] - EAS2(t0, rFP, t0) # t0 <- &fp[CC] - LOAD64_F(ft0, ft0f, rOBJ) - LOAD64_F(ft1, ft1f, t0) -#ifdef MIPS32REVGE6 - cmp.eq.d ft2, ft0, ft1 - li rTEMP, 0 - bc1nez ft2, 1f # done if vBB == vCC (ordered) - .if 0 - cmp.lt.d ft2, ft0, ft1 - li rTEMP, -1 - bc1nez ft2, 1f # done if vBB < vCC (ordered) - li rTEMP, 1 # vBB > vCC or unordered - .else - cmp.lt.d ft2, ft1, ft0 - li rTEMP, 1 - bc1nez ft2, 1f # done if vBB > vCC (ordered) - li rTEMP, -1 # vBB < vCC or unordered - .endif -#else - c.eq.d fcc0, ft0, ft1 - li rTEMP, 0 - bc1t fcc0, 1f # done if vBB == vCC (ordered) - .if 0 - c.olt.d fcc0, ft0, ft1 - li rTEMP, -1 - bc1t fcc0, 1f # done if vBB < vCC (ordered) - li rTEMP, 1 # vBB > vCC or unordered - .else - c.olt.d fcc0, ft1, ft0 - li rTEMP, 1 - bc1t fcc0, 1f # done if vBB > vCC (ordered) - li rTEMP, -1 # vBB < vCC or unordered - .endif -#endif -1: - GET_OPA(rOBJ) - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(rTEMP, rOBJ, t0) # vAA <- rTEMP - -/* ------------------------------ */ - .balign 128 -.L_op_cmpg_double: /* 0x30 */ -/* File: mips/op_cmpg_double.S */ -/* File: mips/op_cmpl_double.S */ - /* - * Compare two floating-point values. Puts 0(==), 1(>), or -1(<) - * into the destination register based on the comparison results. - * - * For: cmpl-double, cmpg-double - */ - /* op vAA, vBB, vCC */ - - FETCH(a0, 1) # a0 <- CCBB - and rOBJ, a0, 255 # rOBJ <- BB - srl t0, a0, 8 # t0 <- CC - EAS2(rOBJ, rFP, rOBJ) # rOBJ <- &fp[BB] - EAS2(t0, rFP, t0) # t0 <- &fp[CC] - LOAD64_F(ft0, ft0f, rOBJ) - LOAD64_F(ft1, ft1f, t0) -#ifdef MIPS32REVGE6 - cmp.eq.d ft2, ft0, ft1 - li rTEMP, 0 - bc1nez ft2, 1f # done if vBB == vCC (ordered) - .if 1 - cmp.lt.d ft2, ft0, ft1 - li rTEMP, -1 - bc1nez ft2, 1f # done if vBB < vCC (ordered) - li rTEMP, 1 # vBB > vCC or unordered - .else - cmp.lt.d ft2, ft1, ft0 - li rTEMP, 1 - bc1nez ft2, 1f # done if vBB > vCC (ordered) - li rTEMP, -1 # vBB < vCC or unordered - .endif -#else - c.eq.d fcc0, ft0, ft1 - li rTEMP, 0 - bc1t fcc0, 1f # done if vBB == vCC (ordered) - .if 1 - c.olt.d fcc0, ft0, ft1 - li rTEMP, -1 - bc1t fcc0, 1f # done if vBB < vCC (ordered) - li rTEMP, 1 # vBB > vCC or unordered - .else - c.olt.d fcc0, ft1, ft0 - li rTEMP, 1 - bc1t fcc0, 1f # done if vBB > vCC (ordered) - li rTEMP, -1 # vBB < vCC or unordered - .endif -#endif -1: - GET_OPA(rOBJ) - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(rTEMP, rOBJ, t0) # vAA <- rTEMP - - -/* ------------------------------ */ - .balign 128 -.L_op_cmp_long: /* 0x31 */ -/* File: mips/op_cmp_long.S */ - /* - * Compare two 64-bit values - * x = y return 0 - * x < y return -1 - * x > y return 1 - * - * I think I can improve on the ARM code by the following observation - * slt t0, x.hi, y.hi; # (x.hi < y.hi) ? 1:0 - * sgt t1, x.hi, y.hi; # (y.hi > x.hi) ? 1:0 - * subu v0, t0, t1 # v0= -1:1:0 for [ < > = ] - */ - /* cmp-long vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 # a3 <- CC - EAS2(a2, rFP, a2) # a2 <- &fp[BB] - EAS2(a3, rFP, a3) # a3 <- &fp[CC] - LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 - LOAD64(a2, a3, a3) # a2/a3 <- vCC/vCC+1 - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - slt t0, a1, a3 # compare hi - sgt t1, a1, a3 - subu v0, t1, t0 # v0 <- (-1, 1, 0) - bnez v0, .Lop_cmp_long_finish - # at this point x.hi==y.hi - sltu t0, a0, a2 # compare lo - sgtu t1, a0, a2 - subu v0, t1, t0 # v0 <- (-1, 1, 0) for [< > =] - -.Lop_cmp_long_finish: - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(v0, rOBJ, t0) # vAA <- v0 - -/* ------------------------------ */ - .balign 128 -.L_op_if_eq: /* 0x32 */ -/* File: mips/op_if_eq.S */ -/* File: mips/bincmp.S */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - GET_OPA4(a0) # a0 <- A+ - GET_OPB(a1) # a1 <- B - GET_VREG(a3, a1) # a3 <- vB - GET_VREG(a0, a0) # a0 <- vA - FETCH_S(rINST, 1) # rINST<- branch offset, in code units - beq a0, a3, MterpCommonTakenBranchNoFlags # compare (vA, vB) - li t0, JIT_CHECK_OSR - beq rPROFILE, t0, .L_check_not_taken_osr - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_ne: /* 0x33 */ -/* File: mips/op_if_ne.S */ -/* File: mips/bincmp.S */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - GET_OPA4(a0) # a0 <- A+ - GET_OPB(a1) # a1 <- B - GET_VREG(a3, a1) # a3 <- vB - GET_VREG(a0, a0) # a0 <- vA - FETCH_S(rINST, 1) # rINST<- branch offset, in code units - bne a0, a3, MterpCommonTakenBranchNoFlags # compare (vA, vB) - li t0, JIT_CHECK_OSR - beq rPROFILE, t0, .L_check_not_taken_osr - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_lt: /* 0x34 */ -/* File: mips/op_if_lt.S */ -/* File: mips/bincmp.S */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - GET_OPA4(a0) # a0 <- A+ - GET_OPB(a1) # a1 <- B - GET_VREG(a3, a1) # a3 <- vB - GET_VREG(a0, a0) # a0 <- vA - FETCH_S(rINST, 1) # rINST<- branch offset, in code units - blt a0, a3, MterpCommonTakenBranchNoFlags # compare (vA, vB) - li t0, JIT_CHECK_OSR - beq rPROFILE, t0, .L_check_not_taken_osr - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_ge: /* 0x35 */ -/* File: mips/op_if_ge.S */ -/* File: mips/bincmp.S */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - GET_OPA4(a0) # a0 <- A+ - GET_OPB(a1) # a1 <- B - GET_VREG(a3, a1) # a3 <- vB - GET_VREG(a0, a0) # a0 <- vA - FETCH_S(rINST, 1) # rINST<- branch offset, in code units - bge a0, a3, MterpCommonTakenBranchNoFlags # compare (vA, vB) - li t0, JIT_CHECK_OSR - beq rPROFILE, t0, .L_check_not_taken_osr - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_gt: /* 0x36 */ -/* File: mips/op_if_gt.S */ -/* File: mips/bincmp.S */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - GET_OPA4(a0) # a0 <- A+ - GET_OPB(a1) # a1 <- B - GET_VREG(a3, a1) # a3 <- vB - GET_VREG(a0, a0) # a0 <- vA - FETCH_S(rINST, 1) # rINST<- branch offset, in code units - bgt a0, a3, MterpCommonTakenBranchNoFlags # compare (vA, vB) - li t0, JIT_CHECK_OSR - beq rPROFILE, t0, .L_check_not_taken_osr - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_le: /* 0x37 */ -/* File: mips/op_if_le.S */ -/* File: mips/bincmp.S */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - GET_OPA4(a0) # a0 <- A+ - GET_OPB(a1) # a1 <- B - GET_VREG(a3, a1) # a3 <- vB - GET_VREG(a0, a0) # a0 <- vA - FETCH_S(rINST, 1) # rINST<- branch offset, in code units - ble a0, a3, MterpCommonTakenBranchNoFlags # compare (vA, vB) - li t0, JIT_CHECK_OSR - beq rPROFILE, t0, .L_check_not_taken_osr - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_eqz: /* 0x38 */ -/* File: mips/op_if_eqz.S */ -/* File: mips/zcmp.S */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - GET_OPA(a0) # a0 <- AA - GET_VREG(a0, a0) # a0 <- vAA - FETCH_S(rINST, 1) # rINST <- branch offset, in code units - beq a0, zero, MterpCommonTakenBranchNoFlags - li t0, JIT_CHECK_OSR # possible OSR re-entry? - beq rPROFILE, t0, .L_check_not_taken_osr - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_nez: /* 0x39 */ -/* File: mips/op_if_nez.S */ -/* File: mips/zcmp.S */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - GET_OPA(a0) # a0 <- AA - GET_VREG(a0, a0) # a0 <- vAA - FETCH_S(rINST, 1) # rINST <- branch offset, in code units - bne a0, zero, MterpCommonTakenBranchNoFlags - li t0, JIT_CHECK_OSR # possible OSR re-entry? - beq rPROFILE, t0, .L_check_not_taken_osr - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_ltz: /* 0x3a */ -/* File: mips/op_if_ltz.S */ -/* File: mips/zcmp.S */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - GET_OPA(a0) # a0 <- AA - GET_VREG(a0, a0) # a0 <- vAA - FETCH_S(rINST, 1) # rINST <- branch offset, in code units - blt a0, zero, MterpCommonTakenBranchNoFlags - li t0, JIT_CHECK_OSR # possible OSR re-entry? - beq rPROFILE, t0, .L_check_not_taken_osr - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_gez: /* 0x3b */ -/* File: mips/op_if_gez.S */ -/* File: mips/zcmp.S */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - GET_OPA(a0) # a0 <- AA - GET_VREG(a0, a0) # a0 <- vAA - FETCH_S(rINST, 1) # rINST <- branch offset, in code units - bge a0, zero, MterpCommonTakenBranchNoFlags - li t0, JIT_CHECK_OSR # possible OSR re-entry? - beq rPROFILE, t0, .L_check_not_taken_osr - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_gtz: /* 0x3c */ -/* File: mips/op_if_gtz.S */ -/* File: mips/zcmp.S */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - GET_OPA(a0) # a0 <- AA - GET_VREG(a0, a0) # a0 <- vAA - FETCH_S(rINST, 1) # rINST <- branch offset, in code units - bgt a0, zero, MterpCommonTakenBranchNoFlags - li t0, JIT_CHECK_OSR # possible OSR re-entry? - beq rPROFILE, t0, .L_check_not_taken_osr - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_lez: /* 0x3d */ -/* File: mips/op_if_lez.S */ -/* File: mips/zcmp.S */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform. - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - GET_OPA(a0) # a0 <- AA - GET_VREG(a0, a0) # a0 <- vAA - FETCH_S(rINST, 1) # rINST <- branch offset, in code units - ble a0, zero, MterpCommonTakenBranchNoFlags - li t0, JIT_CHECK_OSR # possible OSR re-entry? - beq rPROFILE, t0, .L_check_not_taken_osr - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_3e: /* 0x3e */ -/* File: mips/op_unused_3e.S */ -/* File: mips/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_3f: /* 0x3f */ -/* File: mips/op_unused_3f.S */ -/* File: mips/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_40: /* 0x40 */ -/* File: mips/op_unused_40.S */ -/* File: mips/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_41: /* 0x41 */ -/* File: mips/op_unused_41.S */ -/* File: mips/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_42: /* 0x42 */ -/* File: mips/op_unused_42.S */ -/* File: mips/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_43: /* 0x43 */ -/* File: mips/op_unused_43.S */ -/* File: mips/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_aget: /* 0x44 */ -/* File: mips/op_aget.S */ - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B(a2, 1, 0) # a2 <- BB - GET_OPA(rOBJ) # rOBJ <- AA - FETCH_B(a3, 1, 1) # a3 <- CC - GET_VREG(a0, a2) # a0 <- vBB (array object) - GET_VREG(a1, a3) # a1 <- vCC (requested index) - # null array object? - beqz a0, common_errNullObject # yes, bail - LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length - EASN(a0, a0, a1, 2) # a0 <- arrayObj + index*width - # a1 >= a3; compare unsigned index - bgeu a1, a3, common_errArrayIndex # index >= length, bail - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - lw a2, MIRROR_INT_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a2, rOBJ, t0) # vAA <- a2 - -/* ------------------------------ */ - .balign 128 -.L_op_aget_wide: /* 0x45 */ -/* File: mips/op_aget_wide.S */ - /* - * Array get, 64 bits. vAA <- vBB[vCC]. - * - * Arrays of long/double are 64-bit aligned. - */ - /* aget-wide vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 # a3 <- CC - GET_VREG(a0, a2) # a0 <- vBB (array object) - GET_VREG(a1, a3) # a1 <- vCC (requested index) - # null array object? - beqz a0, common_errNullObject # yes, bail - LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length - EAS3(a0, a0, a1) # a0 <- arrayObj + index*width - bgeu a1, a3, common_errArrayIndex # index >= length, bail - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - LOAD64_off(a2, a3, a0, MIRROR_WIDE_ARRAY_DATA_OFFSET) - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(a2, a3, rOBJ, t0) # vAA/vAA+1 <- a2/a3 - -/* ------------------------------ */ - .balign 128 -.L_op_aget_object: /* 0x46 */ -/* File: mips/op_aget_object.S */ - /* - * Array object get. vAA <- vBB[vCC]. - * - * for: aget-object - */ - /* op vAA, vBB, vCC */ - FETCH_B(a2, 1, 0) # a2 <- BB - GET_OPA(rOBJ) # rOBJ <- AA - FETCH_B(a3, 1, 1) # a3 <- CC - EXPORT_PC() - GET_VREG(a0, a2) # a0 <- vBB (array object) - GET_VREG(a1, a3) # a1 <- vCC (requested index) - JAL(artAGetObjectFromMterp) # v0 <- GetObj(array, index) - lw a1, THREAD_EXCEPTION_OFFSET(rSELF) - PREFETCH_INST(2) # load rINST - bnez a1, MterpException - ADVANCE(2) # advance rPC - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_OBJECT_GOTO(v0, rOBJ, t0) # vAA <- v0 - -/* ------------------------------ */ - .balign 128 -.L_op_aget_boolean: /* 0x47 */ -/* File: mips/op_aget_boolean.S */ -/* File: mips/op_aget.S */ - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B(a2, 1, 0) # a2 <- BB - GET_OPA(rOBJ) # rOBJ <- AA - FETCH_B(a3, 1, 1) # a3 <- CC - GET_VREG(a0, a2) # a0 <- vBB (array object) - GET_VREG(a1, a3) # a1 <- vCC (requested index) - # null array object? - beqz a0, common_errNullObject # yes, bail - LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length - EASN(a0, a0, a1, 0) # a0 <- arrayObj + index*width - # a1 >= a3; compare unsigned index - bgeu a1, a3, common_errArrayIndex # index >= length, bail - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - lbu a2, MIRROR_BOOLEAN_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a2, rOBJ, t0) # vAA <- a2 - - -/* ------------------------------ */ - .balign 128 -.L_op_aget_byte: /* 0x48 */ -/* File: mips/op_aget_byte.S */ -/* File: mips/op_aget.S */ - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B(a2, 1, 0) # a2 <- BB - GET_OPA(rOBJ) # rOBJ <- AA - FETCH_B(a3, 1, 1) # a3 <- CC - GET_VREG(a0, a2) # a0 <- vBB (array object) - GET_VREG(a1, a3) # a1 <- vCC (requested index) - # null array object? - beqz a0, common_errNullObject # yes, bail - LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length - EASN(a0, a0, a1, 0) # a0 <- arrayObj + index*width - # a1 >= a3; compare unsigned index - bgeu a1, a3, common_errArrayIndex # index >= length, bail - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - lb a2, MIRROR_BYTE_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a2, rOBJ, t0) # vAA <- a2 - - -/* ------------------------------ */ - .balign 128 -.L_op_aget_char: /* 0x49 */ -/* File: mips/op_aget_char.S */ -/* File: mips/op_aget.S */ - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B(a2, 1, 0) # a2 <- BB - GET_OPA(rOBJ) # rOBJ <- AA - FETCH_B(a3, 1, 1) # a3 <- CC - GET_VREG(a0, a2) # a0 <- vBB (array object) - GET_VREG(a1, a3) # a1 <- vCC (requested index) - # null array object? - beqz a0, common_errNullObject # yes, bail - LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length - EASN(a0, a0, a1, 1) # a0 <- arrayObj + index*width - # a1 >= a3; compare unsigned index - bgeu a1, a3, common_errArrayIndex # index >= length, bail - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - lhu a2, MIRROR_CHAR_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a2, rOBJ, t0) # vAA <- a2 - - -/* ------------------------------ */ - .balign 128 -.L_op_aget_short: /* 0x4a */ -/* File: mips/op_aget_short.S */ -/* File: mips/op_aget.S */ - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 - * instructions. We use a pair of FETCH_Bs instead. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B(a2, 1, 0) # a2 <- BB - GET_OPA(rOBJ) # rOBJ <- AA - FETCH_B(a3, 1, 1) # a3 <- CC - GET_VREG(a0, a2) # a0 <- vBB (array object) - GET_VREG(a1, a3) # a1 <- vCC (requested index) - # null array object? - beqz a0, common_errNullObject # yes, bail - LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length - EASN(a0, a0, a1, 1) # a0 <- arrayObj + index*width - # a1 >= a3; compare unsigned index - bgeu a1, a3, common_errArrayIndex # index >= length, bail - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - lh a2, MIRROR_SHORT_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a2, rOBJ, t0) # vAA <- a2 - - -/* ------------------------------ */ - .balign 128 -.L_op_aput: /* 0x4b */ -/* File: mips/op_aput.S */ - - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B(a2, 1, 0) # a2 <- BB - GET_OPA(rOBJ) # rOBJ <- AA - FETCH_B(a3, 1, 1) # a3 <- CC - GET_VREG(a0, a2) # a0 <- vBB (array object) - GET_VREG(a1, a3) # a1 <- vCC (requested index) - # null array object? - beqz a0, common_errNullObject # yes, bail - LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length - EASN(a0, a0, a1, 2) # a0 <- arrayObj + index*width - bgeu a1, a3, common_errArrayIndex # index >= length, bail - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_VREG(a2, rOBJ) # a2 <- vAA - GET_INST_OPCODE(t0) # extract opcode from rINST - GET_OPCODE_TARGET(t0) - sw a2, MIRROR_INT_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 - JR(t0) # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aput_wide: /* 0x4c */ -/* File: mips/op_aput_wide.S */ - /* - * Array put, 64 bits. vBB[vCC] <- vAA. - */ - /* aput-wide vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(t0) # t0 <- AA - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 # a3 <- CC - GET_VREG(a0, a2) # a0 <- vBB (array object) - GET_VREG(a1, a3) # a1 <- vCC (requested index) - # null array object? - beqz a0, common_errNullObject # yes, bail - LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length - EAS3(a0, a0, a1) # a0 <- arrayObj + index*width - EAS2(rOBJ, rFP, t0) # rOBJ <- &fp[AA] - # compare unsigned index, length - bgeu a1, a3, common_errArrayIndex # index >= length, bail - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - LOAD64(a2, a3, rOBJ) # a2/a3 <- vAA/vAA+1 - GET_INST_OPCODE(t0) # extract opcode from rINST - GET_OPCODE_TARGET(t0) - STORE64_off(a2, a3, a0, MIRROR_WIDE_ARRAY_DATA_OFFSET) # a2/a3 <- vBB[vCC] - JR(t0) # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aput_object: /* 0x4d */ -/* File: mips/op_aput_object.S */ - /* - * Store an object into an array. vBB[vCC] <- vAA. - * - */ - /* op vAA, vBB, vCC */ - EXPORT_PC() - addu a0, rFP, OFF_FP_SHADOWFRAME - move a1, rPC - move a2, rINST - JAL(MterpAputObject) - beqz v0, MterpPossibleException - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aput_boolean: /* 0x4e */ -/* File: mips/op_aput_boolean.S */ -/* File: mips/op_aput.S */ - - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B(a2, 1, 0) # a2 <- BB - GET_OPA(rOBJ) # rOBJ <- AA - FETCH_B(a3, 1, 1) # a3 <- CC - GET_VREG(a0, a2) # a0 <- vBB (array object) - GET_VREG(a1, a3) # a1 <- vCC (requested index) - # null array object? - beqz a0, common_errNullObject # yes, bail - LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length - EASN(a0, a0, a1, 0) # a0 <- arrayObj + index*width - bgeu a1, a3, common_errArrayIndex # index >= length, bail - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_VREG(a2, rOBJ) # a2 <- vAA - GET_INST_OPCODE(t0) # extract opcode from rINST - GET_OPCODE_TARGET(t0) - sb a2, MIRROR_BOOLEAN_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 - JR(t0) # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_aput_byte: /* 0x4f */ -/* File: mips/op_aput_byte.S */ -/* File: mips/op_aput.S */ - - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B(a2, 1, 0) # a2 <- BB - GET_OPA(rOBJ) # rOBJ <- AA - FETCH_B(a3, 1, 1) # a3 <- CC - GET_VREG(a0, a2) # a0 <- vBB (array object) - GET_VREG(a1, a3) # a1 <- vCC (requested index) - # null array object? - beqz a0, common_errNullObject # yes, bail - LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length - EASN(a0, a0, a1, 0) # a0 <- arrayObj + index*width - bgeu a1, a3, common_errArrayIndex # index >= length, bail - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_VREG(a2, rOBJ) # a2 <- vAA - GET_INST_OPCODE(t0) # extract opcode from rINST - GET_OPCODE_TARGET(t0) - sb a2, MIRROR_BYTE_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 - JR(t0) # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_aput_char: /* 0x50 */ -/* File: mips/op_aput_char.S */ -/* File: mips/op_aput.S */ - - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B(a2, 1, 0) # a2 <- BB - GET_OPA(rOBJ) # rOBJ <- AA - FETCH_B(a3, 1, 1) # a3 <- CC - GET_VREG(a0, a2) # a0 <- vBB (array object) - GET_VREG(a1, a3) # a1 <- vCC (requested index) - # null array object? - beqz a0, common_errNullObject # yes, bail - LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length - EASN(a0, a0, a1, 1) # a0 <- arrayObj + index*width - bgeu a1, a3, common_errArrayIndex # index >= length, bail - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_VREG(a2, rOBJ) # a2 <- vAA - GET_INST_OPCODE(t0) # extract opcode from rINST - GET_OPCODE_TARGET(t0) - sh a2, MIRROR_CHAR_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 - JR(t0) # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_aput_short: /* 0x51 */ -/* File: mips/op_aput_short.S */ -/* File: mips/op_aput.S */ - - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - FETCH_B(a2, 1, 0) # a2 <- BB - GET_OPA(rOBJ) # rOBJ <- AA - FETCH_B(a3, 1, 1) # a3 <- CC - GET_VREG(a0, a2) # a0 <- vBB (array object) - GET_VREG(a1, a3) # a1 <- vCC (requested index) - # null array object? - beqz a0, common_errNullObject # yes, bail - LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length - EASN(a0, a0, a1, 1) # a0 <- arrayObj + index*width - bgeu a1, a3, common_errArrayIndex # index >= length, bail - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_VREG(a2, rOBJ) # a2 <- vAA - GET_INST_OPCODE(t0) # extract opcode from rINST - GET_OPCODE_TARGET(t0) - sh a2, MIRROR_SHORT_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 - JR(t0) # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_iget: /* 0x52 */ -/* File: mips/op_iget.S */ -/* File: mips/field.S */ -TODO - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_wide: /* 0x53 */ -/* File: mips/op_iget_wide.S */ -/* File: mips/op_iget.S */ -/* File: mips/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_object: /* 0x54 */ -/* File: mips/op_iget_object.S */ -/* File: mips/op_iget.S */ -/* File: mips/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_boolean: /* 0x55 */ -/* File: mips/op_iget_boolean.S */ -/* File: mips/op_iget.S */ -/* File: mips/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_byte: /* 0x56 */ -/* File: mips/op_iget_byte.S */ -/* File: mips/op_iget.S */ -/* File: mips/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_char: /* 0x57 */ -/* File: mips/op_iget_char.S */ -/* File: mips/op_iget.S */ -/* File: mips/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_short: /* 0x58 */ -/* File: mips/op_iget_short.S */ -/* File: mips/op_iget.S */ -/* File: mips/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_iput: /* 0x59 */ -/* File: mips/op_iput.S */ -/* File: mips/field.S */ -TODO - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_wide: /* 0x5a */ -/* File: mips/op_iput_wide.S */ -/* File: mips/op_iput.S */ -/* File: mips/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_object: /* 0x5b */ -/* File: mips/op_iput_object.S */ -/* File: mips/op_iput.S */ -/* File: mips/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_boolean: /* 0x5c */ -/* File: mips/op_iput_boolean.S */ -/* File: mips/op_iput.S */ -/* File: mips/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_byte: /* 0x5d */ -/* File: mips/op_iput_byte.S */ -/* File: mips/op_iput.S */ -/* File: mips/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_char: /* 0x5e */ -/* File: mips/op_iput_char.S */ -/* File: mips/op_iput.S */ -/* File: mips/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_short: /* 0x5f */ -/* File: mips/op_iput_short.S */ -/* File: mips/op_iput.S */ -/* File: mips/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_sget: /* 0x60 */ -/* File: mips/op_sget.S */ -/* File: mips/field.S */ -TODO - - -/* ------------------------------ */ - .balign 128 -.L_op_sget_wide: /* 0x61 */ -/* File: mips/op_sget_wide.S */ -/* File: mips/op_sget.S */ -/* File: mips/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_sget_object: /* 0x62 */ -/* File: mips/op_sget_object.S */ -/* File: mips/op_sget.S */ -/* File: mips/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_sget_boolean: /* 0x63 */ -/* File: mips/op_sget_boolean.S */ -/* File: mips/op_sget.S */ -/* File: mips/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_sget_byte: /* 0x64 */ -/* File: mips/op_sget_byte.S */ -/* File: mips/op_sget.S */ -/* File: mips/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_sget_char: /* 0x65 */ -/* File: mips/op_sget_char.S */ -/* File: mips/op_sget.S */ -/* File: mips/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_sget_short: /* 0x66 */ -/* File: mips/op_sget_short.S */ -/* File: mips/op_sget.S */ -/* File: mips/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_sput: /* 0x67 */ -/* File: mips/op_sput.S */ -/* File: mips/field.S */ -TODO - - -/* ------------------------------ */ - .balign 128 -.L_op_sput_wide: /* 0x68 */ -/* File: mips/op_sput_wide.S */ -/* File: mips/op_sput.S */ -/* File: mips/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_sput_object: /* 0x69 */ -/* File: mips/op_sput_object.S */ -/* File: mips/op_sput.S */ -/* File: mips/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_sput_boolean: /* 0x6a */ -/* File: mips/op_sput_boolean.S */ -/* File: mips/op_sput.S */ -/* File: mips/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_sput_byte: /* 0x6b */ -/* File: mips/op_sput_byte.S */ -/* File: mips/op_sput.S */ -/* File: mips/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_sput_char: /* 0x6c */ -/* File: mips/op_sput_char.S */ -/* File: mips/op_sput.S */ -/* File: mips/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_sput_short: /* 0x6d */ -/* File: mips/op_sput_short.S */ -/* File: mips/op_sput.S */ -/* File: mips/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual: /* 0x6e */ -/* File: mips/op_invoke_virtual.S */ -/* File: mips/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtual - EXPORT_PC() - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - JAL(MterpInvokeVirtual) - beqz v0, MterpException - FETCH_ADVANCE_INST(3) - JAL(MterpShouldSwitchInterpreters) - bnez v0, MterpFallback - GET_INST_OPCODE(t0) - GOTO_OPCODE(t0) - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_super: /* 0x6f */ -/* File: mips/op_invoke_super.S */ -/* File: mips/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeSuper - EXPORT_PC() - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - JAL(MterpInvokeSuper) - beqz v0, MterpException - FETCH_ADVANCE_INST(3) - JAL(MterpShouldSwitchInterpreters) - bnez v0, MterpFallback - GET_INST_OPCODE(t0) - GOTO_OPCODE(t0) - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_direct: /* 0x70 */ -/* File: mips/op_invoke_direct.S */ -/* File: mips/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeDirect - EXPORT_PC() - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - JAL(MterpInvokeDirect) - beqz v0, MterpException - FETCH_ADVANCE_INST(3) - JAL(MterpShouldSwitchInterpreters) - bnez v0, MterpFallback - GET_INST_OPCODE(t0) - GOTO_OPCODE(t0) - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_static: /* 0x71 */ -/* File: mips/op_invoke_static.S */ -/* File: mips/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeStatic - EXPORT_PC() - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - JAL(MterpInvokeStatic) - beqz v0, MterpException - FETCH_ADVANCE_INST(3) - JAL(MterpShouldSwitchInterpreters) - bnez v0, MterpFallback - GET_INST_OPCODE(t0) - GOTO_OPCODE(t0) - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_interface: /* 0x72 */ -/* File: mips/op_invoke_interface.S */ -/* File: mips/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeInterface - EXPORT_PC() - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - JAL(MterpInvokeInterface) - beqz v0, MterpException - FETCH_ADVANCE_INST(3) - JAL(MterpShouldSwitchInterpreters) - bnez v0, MterpFallback - GET_INST_OPCODE(t0) - GOTO_OPCODE(t0) - - -/* ------------------------------ */ - .balign 128 -.L_op_return_void_no_barrier: /* 0x73 */ -/* File: mips/op_return_void_no_barrier.S */ - lw ra, THREAD_FLAGS_OFFSET(rSELF) - move a0, rSELF - and ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - beqz ra, 1f - JAL(MterpSuspendCheck) # (self) -1: - move v0, zero - move v1, zero - b MterpReturn - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual_range: /* 0x74 */ -/* File: mips/op_invoke_virtual_range.S */ -/* File: mips/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtualRange - EXPORT_PC() - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - JAL(MterpInvokeVirtualRange) - beqz v0, MterpException - FETCH_ADVANCE_INST(3) - JAL(MterpShouldSwitchInterpreters) - bnez v0, MterpFallback - GET_INST_OPCODE(t0) - GOTO_OPCODE(t0) - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_super_range: /* 0x75 */ -/* File: mips/op_invoke_super_range.S */ -/* File: mips/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeSuperRange - EXPORT_PC() - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - JAL(MterpInvokeSuperRange) - beqz v0, MterpException - FETCH_ADVANCE_INST(3) - JAL(MterpShouldSwitchInterpreters) - bnez v0, MterpFallback - GET_INST_OPCODE(t0) - GOTO_OPCODE(t0) - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_direct_range: /* 0x76 */ -/* File: mips/op_invoke_direct_range.S */ -/* File: mips/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeDirectRange - EXPORT_PC() - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - JAL(MterpInvokeDirectRange) - beqz v0, MterpException - FETCH_ADVANCE_INST(3) - JAL(MterpShouldSwitchInterpreters) - bnez v0, MterpFallback - GET_INST_OPCODE(t0) - GOTO_OPCODE(t0) - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_static_range: /* 0x77 */ -/* File: mips/op_invoke_static_range.S */ -/* File: mips/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeStaticRange - EXPORT_PC() - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - JAL(MterpInvokeStaticRange) - beqz v0, MterpException - FETCH_ADVANCE_INST(3) - JAL(MterpShouldSwitchInterpreters) - bnez v0, MterpFallback - GET_INST_OPCODE(t0) - GOTO_OPCODE(t0) - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_interface_range: /* 0x78 */ -/* File: mips/op_invoke_interface_range.S */ -/* File: mips/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeInterfaceRange - EXPORT_PC() - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - JAL(MterpInvokeInterfaceRange) - beqz v0, MterpException - FETCH_ADVANCE_INST(3) - JAL(MterpShouldSwitchInterpreters) - bnez v0, MterpFallback - GET_INST_OPCODE(t0) - GOTO_OPCODE(t0) - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_79: /* 0x79 */ -/* File: mips/op_unused_79.S */ -/* File: mips/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_7a: /* 0x7a */ -/* File: mips/op_unused_7a.S */ -/* File: mips/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_neg_int: /* 0x7b */ -/* File: mips/op_neg_int.S */ -/* File: mips/unop.S */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result0 = op a0". - * This could be a MIPS instruction or a function call. - * - * for: int-to-byte, int-to-char, int-to-short, - * neg-int, not-int, neg-float - */ - /* unop vA, vB */ - GET_OPB(a3) # a3 <- B - GET_OPA4(t0) # t0 <- A+ - GET_VREG(a0, a3) # a0 <- vB - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - # optional op - negu a0, a0 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t1) # extract opcode from rINST - SET_VREG_GOTO(a0, t0, t1) # vA <- result0 - - -/* ------------------------------ */ - .balign 128 -.L_op_not_int: /* 0x7c */ -/* File: mips/op_not_int.S */ -/* File: mips/unop.S */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result0 = op a0". - * This could be a MIPS instruction or a function call. - * - * for: int-to-byte, int-to-char, int-to-short, - * neg-int, not-int, neg-float - */ - /* unop vA, vB */ - GET_OPB(a3) # a3 <- B - GET_OPA4(t0) # t0 <- A+ - GET_VREG(a0, a3) # a0 <- vB - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - # optional op - not a0, a0 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t1) # extract opcode from rINST - SET_VREG_GOTO(a0, t0, t1) # vA <- result0 - - -/* ------------------------------ */ - .balign 128 -.L_op_neg_long: /* 0x7d */ -/* File: mips/op_neg_long.S */ -/* File: mips/unopWide.S */ - /* - * Generic 64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result0/result1 = op a0/a1". - * This could be MIPS instruction or a function call. - * - * For: neg-long, not-long, neg-double, - */ - /* unop vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - EAS2(a3, rFP, a3) # a3 <- &fp[B] - LOAD64(a0, a1, a3) # a0/a1 <- vA - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - negu v0, a0 # optional op - negu v1, a1; sltu a0, zero, v0; subu v1, v1, a0 # a0/a1 <- op, a2-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vA/vA+1 <- a0/a1 - - -/* ------------------------------ */ - .balign 128 -.L_op_not_long: /* 0x7e */ -/* File: mips/op_not_long.S */ -/* File: mips/unopWide.S */ - /* - * Generic 64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result0/result1 = op a0/a1". - * This could be MIPS instruction or a function call. - * - * For: neg-long, not-long, neg-double, - */ - /* unop vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - EAS2(a3, rFP, a3) # a3 <- &fp[B] - LOAD64(a0, a1, a3) # a0/a1 <- vA - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - not a0, a0 # optional op - not a1, a1 # a0/a1 <- op, a2-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vA/vA+1 <- a0/a1 - - -/* ------------------------------ */ - .balign 128 -.L_op_neg_float: /* 0x7f */ -/* File: mips/op_neg_float.S */ -/* File: mips/unop.S */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result0 = op a0". - * This could be a MIPS instruction or a function call. - * - * for: int-to-byte, int-to-char, int-to-short, - * neg-int, not-int, neg-float - */ - /* unop vA, vB */ - GET_OPB(a3) # a3 <- B - GET_OPA4(t0) # t0 <- A+ - GET_VREG(a0, a3) # a0 <- vB - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - # optional op - addu a0, a0, 0x80000000 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t1) # extract opcode from rINST - SET_VREG_GOTO(a0, t0, t1) # vA <- result0 - - -/* ------------------------------ */ - .balign 128 -.L_op_neg_double: /* 0x80 */ -/* File: mips/op_neg_double.S */ -/* File: mips/unopWide.S */ - /* - * Generic 64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result0/result1 = op a0/a1". - * This could be MIPS instruction or a function call. - * - * For: neg-long, not-long, neg-double, - */ - /* unop vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - EAS2(a3, rFP, a3) # a3 <- &fp[B] - LOAD64(a0, a1, a3) # a0/a1 <- vA - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - # optional op - addu a1, a1, 0x80000000 # a0/a1 <- op, a2-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vA/vA+1 <- a0/a1 - - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_long: /* 0x81 */ -/* File: mips/op_int_to_long.S */ -/* File: mips/unopWider.S */ - /* - * Generic 32bit-to-64bit unary operation. Provide an "instr" line - * that specifies an instruction that performs "result0/result1 = op a0". - * - * For: int-to-long - */ - /* unop vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a0, a3) # a0 <- vB - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - # optional op - sra a1, a0, 31 # result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vA/vA+1 <- a0/a1 - - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_float: /* 0x82 */ -/* File: mips/op_int_to_float.S */ -/* File: mips/funop.S */ - /* - * Generic 32-bit floating-point unary operation. Provide an "instr" - * line that specifies an instruction that performs "fv0 = op fa0". - * This could be a MIPS instruction or a function call. - * - * for: int-to-float - */ - /* unop vA, vB */ - GET_OPB(a3) # a3 <- B - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_VREG_F(fa0, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - cvt.s.w fv0, fa0 - GET_INST_OPCODE(t1) # extract opcode from rINST - SET_VREG_F_GOTO(fv0, rOBJ, t1) # vA <- fv0 - - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_double: /* 0x83 */ -/* File: mips/op_int_to_double.S */ -/* File: mips/funopWider.S */ - /* - * Generic 32bit-to-64bit floating-point unary operation. Provide an "instr" - * line that specifies an instruction that performs "fv0 = op fa0". - * - * For: int-to-double, float-to-double - */ - /* unop vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG_F(fa0, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - cvt.d.w fv0, fa0 - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vA/vA+1 <- fv0 - - -/* ------------------------------ */ - .balign 128 -.L_op_long_to_int: /* 0x84 */ -/* File: mips/op_long_to_int.S */ -/* we ignore the high word, making this equivalent to a 32-bit reg move */ -/* File: mips/op_move.S */ - /* for move, move-object, long-to-int */ - /* op vA, vB */ - GET_OPB(a1) # a1 <- B from 15:12 - GET_OPA4(a0) # a0 <- A from 11:8 - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - GET_VREG(a2, a1) # a2 <- fp[B] - GET_INST_OPCODE(t0) # t0 <- opcode from rINST - .if 0 - SET_VREG_OBJECT_GOTO(a2, a0, t0) # fp[A] <- a2 - .else - SET_VREG_GOTO(a2, a0, t0) # fp[A] <- a2 - .endif - - -/* ------------------------------ */ - .balign 128 -.L_op_long_to_float: /* 0x85 */ -/* File: mips/op_long_to_float.S */ - /* - * long-to-float - */ - /* unop vA, vB */ - GET_OPB(a3) # a3 <- B - GET_OPA4(rOBJ) # rOBJ <- A+ - EAS2(a3, rFP, a3) # a3 <- &fp[B] - -#ifdef MIPS32REVGE6 - LOAD64_F(fv0, fv0f, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - cvt.s.l fv0, fv0 -#else - LOAD64(rARG0, rARG1, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - JAL(__floatdisf) -#endif - - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_F_GOTO(fv0, rOBJ, t0) # vA <- fv0 - -/* ------------------------------ */ - .balign 128 -.L_op_long_to_double: /* 0x86 */ -/* File: mips/op_long_to_double.S */ - /* - * long-to-double - */ - /* unop vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - EAS2(a3, rFP, a3) # a3 <- &fp[B] - -#ifdef MIPS32REVGE6 - LOAD64_F(fv0, fv0f, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - cvt.d.l fv0, fv0 -#else - LOAD64(rARG0, rARG1, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - JAL(__floatdidf) # a0/a1 <- op, a2-a3 changed -#endif - - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vA/vA+1 <- result - -/* ------------------------------ */ - .balign 128 -.L_op_float_to_int: /* 0x87 */ -/* File: mips/op_float_to_int.S */ - /* - * float-to-int - * - * We have to clip values to int min/max per the specification. The - * expected common case is a "reasonable" value that converts directly - * to modest integer. The EABI convert function isn't doing this for us - * for pre-R6. - */ - /* unop vA, vB */ - GET_OPB(a3) # a3 <- B - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_VREG_F(fa0, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - -#ifndef MIPS32REVGE6 - li t0, INT_MIN_AS_FLOAT - mtc1 t0, fa1 - c.ole.s fcc0, fa1, fa0 -#endif - GET_INST_OPCODE(t1) # extract opcode from rINST -#ifndef MIPS32REVGE6 - bc1t fcc0, 1f # if INT_MIN <= vB, proceed to truncation - c.eq.s fcc0, fa0, fa0 - mtc1 zero, fa0 - movt.s fa0, fa1, fcc0 # fa0 = ordered(vB) ? INT_MIN_AS_FLOAT : 0 -1: -#endif - trunc.w.s fa0, fa0 - SET_VREG_F_GOTO(fa0, rOBJ, t1) # vA <- result - -/* ------------------------------ */ - .balign 128 -.L_op_float_to_long: /* 0x88 */ -/* File: mips/op_float_to_long.S */ - /* - * float-to-long - * - * We have to clip values to long min/max per the specification. The - * expected common case is a "reasonable" value that converts directly - * to modest integer. The EABI convert function isn't doing this for us - * for pre-R6. - */ - /* unop vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG_F(fa0, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - -#ifdef MIPS32REVGE6 - GET_INST_OPCODE(t1) # extract opcode from rINST - trunc.l.s fa0, fa0 - SET_VREG64_F_GOTO(fa0, fa0f, rOBJ, t1) # vA <- result -#else - c.eq.s fcc0, fa0, fa0 - li rRESULT0, 0 - li rRESULT1, 0 - bc1f fcc0, .Lop_float_to_long_get_opcode - - li t0, LONG_MIN_AS_FLOAT - mtc1 t0, fa1 - c.ole.s fcc0, fa0, fa1 - li rRESULT1, LONG_MIN_HIGH - bc1t fcc0, .Lop_float_to_long_get_opcode - - neg.s fa1, fa1 - c.ole.s fcc0, fa1, fa0 - nor rRESULT0, rRESULT0, zero - nor rRESULT1, rRESULT1, zero - bc1t fcc0, .Lop_float_to_long_get_opcode - - JAL(__fixsfdi) - GET_INST_OPCODE(t1) # extract opcode from rINST - b .Lop_float_to_long_set_vreg -#endif - -/* ------------------------------ */ - .balign 128 -.L_op_float_to_double: /* 0x89 */ -/* File: mips/op_float_to_double.S */ -/* File: mips/funopWider.S */ - /* - * Generic 32bit-to-64bit floating-point unary operation. Provide an "instr" - * line that specifies an instruction that performs "fv0 = op fa0". - * - * For: int-to-double, float-to-double - */ - /* unop vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG_F(fa0, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - cvt.d.s fv0, fa0 - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vA/vA+1 <- fv0 - - -/* ------------------------------ */ - .balign 128 -.L_op_double_to_int: /* 0x8a */ -/* File: mips/op_double_to_int.S */ - /* - * double-to-int - * - * We have to clip values to int min/max per the specification. The - * expected common case is a "reasonable" value that converts directly - * to modest integer. The EABI convert function isn't doing this for us - * for pre-R6. - */ - /* unop vA, vB */ - GET_OPB(a3) # a3 <- B - GET_OPA4(rOBJ) # rOBJ <- A+ - EAS2(a3, rFP, a3) # a3 <- &fp[B] - LOAD64_F(fa0, fa0f, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST -#ifndef MIPS32REVGE6 - li t0, INT_MIN_AS_DOUBLE_HIGH - mtc1 zero, fa1 - MOVE_TO_FPU_HIGH(t0, fa1, fa1f) - c.ole.d fcc0, fa1, fa0 -#endif - GET_INST_OPCODE(t1) # extract opcode from rINST -#ifndef MIPS32REVGE6 - bc1t fcc0, 1f # if INT_MIN <= vB, proceed to truncation - c.eq.d fcc0, fa0, fa0 - mtc1 zero, fa0 - MOVE_TO_FPU_HIGH(zero, fa0, fa0f) - movt.d fa0, fa1, fcc0 # fa0 = ordered(vB) ? INT_MIN_AS_DOUBLE : 0 -1: -#endif - trunc.w.d fa0, fa0 - SET_VREG_F_GOTO(fa0, rOBJ, t1) # vA <- result - -/* ------------------------------ */ - .balign 128 -.L_op_double_to_long: /* 0x8b */ -/* File: mips/op_double_to_long.S */ - /* - * double-to-long - * - * We have to clip values to long min/max per the specification. The - * expected common case is a "reasonable" value that converts directly - * to modest integer. The EABI convert function isn't doing this for us - * for pre-R6. - */ - /* unop vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - EAS2(a3, rFP, a3) # a3 <- &fp[B] - LOAD64_F(fa0, fa0f, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - -#ifdef MIPS32REVGE6 - GET_INST_OPCODE(t1) # extract opcode from rINST - trunc.l.d fa0, fa0 - SET_VREG64_F_GOTO(fa0, fa0f, rOBJ, t1) # vA <- result -#else - c.eq.d fcc0, fa0, fa0 - li rRESULT0, 0 - li rRESULT1, 0 - bc1f fcc0, .Lop_double_to_long_get_opcode - - li t0, LONG_MIN_AS_DOUBLE_HIGH - mtc1 zero, fa1 - MOVE_TO_FPU_HIGH(t0, fa1, fa1f) - c.ole.d fcc0, fa0, fa1 - li rRESULT1, LONG_MIN_HIGH - bc1t fcc0, .Lop_double_to_long_get_opcode - - neg.d fa1, fa1 - c.ole.d fcc0, fa1, fa0 - nor rRESULT0, rRESULT0, zero - nor rRESULT1, rRESULT1, zero - bc1t fcc0, .Lop_double_to_long_get_opcode - - JAL(__fixdfdi) - GET_INST_OPCODE(t1) # extract opcode from rINST - b .Lop_double_to_long_set_vreg -#endif - -/* ------------------------------ */ - .balign 128 -.L_op_double_to_float: /* 0x8c */ -/* File: mips/op_double_to_float.S */ -/* File: mips/unopNarrower.S */ - /* - * Generic 64bit-to-32bit floating-point unary operation. Provide an "instr" - * line that specifies an instruction that performs "fv0 = op fa0". - * - * For: double-to-float - */ - /* unop vA, vB */ - GET_OPB(a3) # a3 <- B - GET_OPA4(rOBJ) # rOBJ <- A+ - EAS2(a3, rFP, a3) # a3 <- &fp[B] - LOAD64_F(fa0, fa0f, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - cvt.s.d fv0, fa0 - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_F_GOTO(fv0, rOBJ, t0) # vA <- fv0 - - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_byte: /* 0x8d */ -/* File: mips/op_int_to_byte.S */ -/* File: mips/unop.S */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result0 = op a0". - * This could be a MIPS instruction or a function call. - * - * for: int-to-byte, int-to-char, int-to-short, - * neg-int, not-int, neg-float - */ - /* unop vA, vB */ - GET_OPB(a3) # a3 <- B - GET_OPA4(t0) # t0 <- A+ - GET_VREG(a0, a3) # a0 <- vB - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - # optional op - SEB(a0, a0) # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t1) # extract opcode from rINST - SET_VREG_GOTO(a0, t0, t1) # vA <- result0 - - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_char: /* 0x8e */ -/* File: mips/op_int_to_char.S */ -/* File: mips/unop.S */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result0 = op a0". - * This could be a MIPS instruction or a function call. - * - * for: int-to-byte, int-to-char, int-to-short, - * neg-int, not-int, neg-float - */ - /* unop vA, vB */ - GET_OPB(a3) # a3 <- B - GET_OPA4(t0) # t0 <- A+ - GET_VREG(a0, a3) # a0 <- vB - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - # optional op - and a0, 0xffff # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t1) # extract opcode from rINST - SET_VREG_GOTO(a0, t0, t1) # vA <- result0 - - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_short: /* 0x8f */ -/* File: mips/op_int_to_short.S */ -/* File: mips/unop.S */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result0 = op a0". - * This could be a MIPS instruction or a function call. - * - * for: int-to-byte, int-to-char, int-to-short, - * neg-int, not-int, neg-float - */ - /* unop vA, vB */ - GET_OPB(a3) # a3 <- B - GET_OPA4(t0) # t0 <- A+ - GET_VREG(a0, a3) # a0 <- vB - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - # optional op - SEH(a0, a0) # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t1) # extract opcode from rINST - SET_VREG_GOTO(a0, t0, t1) # vA <- result0 - - -/* ------------------------------ */ - .balign 128 -.L_op_add_int: /* 0x90 */ -/* File: mips/op_add_int.S */ -/* File: mips/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - srl a3, a0, 8 # a3 <- CC - and a2, a0, 255 # a2 <- BB - GET_VREG(a1, a3) # a1 <- vCC - GET_VREG(a0, a2) # a0 <- vBB - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - # optional op - addu a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_int: /* 0x91 */ -/* File: mips/op_sub_int.S */ -/* File: mips/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - srl a3, a0, 8 # a3 <- CC - and a2, a0, 255 # a2 <- BB - GET_VREG(a1, a3) # a1 <- vCC - GET_VREG(a0, a2) # a0 <- vBB - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - # optional op - subu a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int: /* 0x92 */ -/* File: mips/op_mul_int.S */ -/* File: mips/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - srl a3, a0, 8 # a3 <- CC - and a2, a0, 255 # a2 <- BB - GET_VREG(a1, a3) # a1 <- vCC - GET_VREG(a0, a2) # a0 <- vBB - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - # optional op - mul a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - - -/* ------------------------------ */ - .balign 128 -.L_op_div_int: /* 0x93 */ -/* File: mips/op_div_int.S */ -#ifdef MIPS32REVGE6 -/* File: mips/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - srl a3, a0, 8 # a3 <- CC - and a2, a0, 255 # a2 <- BB - GET_VREG(a1, a3) # a1 <- vCC - GET_VREG(a0, a2) # a0 <- vBB - .if 1 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - # optional op - div a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - -#else -/* File: mips/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - srl a3, a0, 8 # a3 <- CC - and a2, a0, 255 # a2 <- BB - GET_VREG(a1, a3) # a1 <- vCC - GET_VREG(a0, a2) # a0 <- vBB - .if 1 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - div zero, a0, a1 # optional op - mflo a0 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - -#endif - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int: /* 0x94 */ -/* File: mips/op_rem_int.S */ -#ifdef MIPS32REVGE6 -/* File: mips/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - srl a3, a0, 8 # a3 <- CC - and a2, a0, 255 # a2 <- BB - GET_VREG(a1, a3) # a1 <- vCC - GET_VREG(a0, a2) # a0 <- vBB - .if 1 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - # optional op - mod a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - -#else -/* File: mips/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - srl a3, a0, 8 # a3 <- CC - and a2, a0, 255 # a2 <- BB - GET_VREG(a1, a3) # a1 <- vCC - GET_VREG(a0, a2) # a0 <- vBB - .if 1 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - div zero, a0, a1 # optional op - mfhi a0 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - -#endif - -/* ------------------------------ */ - .balign 128 -.L_op_and_int: /* 0x95 */ -/* File: mips/op_and_int.S */ -/* File: mips/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - srl a3, a0, 8 # a3 <- CC - and a2, a0, 255 # a2 <- BB - GET_VREG(a1, a3) # a1 <- vCC - GET_VREG(a0, a2) # a0 <- vBB - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - # optional op - and a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - - -/* ------------------------------ */ - .balign 128 -.L_op_or_int: /* 0x96 */ -/* File: mips/op_or_int.S */ -/* File: mips/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - srl a3, a0, 8 # a3 <- CC - and a2, a0, 255 # a2 <- BB - GET_VREG(a1, a3) # a1 <- vCC - GET_VREG(a0, a2) # a0 <- vBB - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - # optional op - or a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int: /* 0x97 */ -/* File: mips/op_xor_int.S */ -/* File: mips/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - srl a3, a0, 8 # a3 <- CC - and a2, a0, 255 # a2 <- BB - GET_VREG(a1, a3) # a1 <- vCC - GET_VREG(a0, a2) # a0 <- vBB - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - # optional op - xor a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - - -/* ------------------------------ */ - .balign 128 -.L_op_shl_int: /* 0x98 */ -/* File: mips/op_shl_int.S */ -/* File: mips/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - srl a3, a0, 8 # a3 <- CC - and a2, a0, 255 # a2 <- BB - GET_VREG(a1, a3) # a1 <- vCC - GET_VREG(a0, a2) # a0 <- vBB - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - # optional op - sll a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - - -/* ------------------------------ */ - .balign 128 -.L_op_shr_int: /* 0x99 */ -/* File: mips/op_shr_int.S */ -/* File: mips/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - srl a3, a0, 8 # a3 <- CC - and a2, a0, 255 # a2 <- BB - GET_VREG(a1, a3) # a1 <- vCC - GET_VREG(a0, a2) # a0 <- vBB - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - # optional op - sra a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_int: /* 0x9a */ -/* File: mips/op_ushr_int.S */ -/* File: mips/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - srl a3, a0, 8 # a3 <- CC - and a2, a0, 255 # a2 <- BB - GET_VREG(a1, a3) # a1 <- vCC - GET_VREG(a0, a2) # a0 <- vBB - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - # optional op - srl a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - - -/* ------------------------------ */ - .balign 128 -.L_op_add_long: /* 0x9b */ -/* File: mips/op_add_long.S */ -/* - * The compiler generates the following sequence for - * [v1 v0] = [a1 a0] + [a3 a2]; - * addu v0,a2,a0 - * addu a1,a3,a1 - * sltu v1,v0,a2 - * addu v1,v1,a1 - */ -/* File: mips/binopWide.S */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0-a1 op a2-a3". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register pair other than a0-a1, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a2-a3). Useful for integer division and modulus. - * - * for: add-long, sub-long, div-long, rem-long, and-long, or-long, - * xor-long - * - * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 # a3 <- CC - EAS2(a2, rFP, a2) # a2 <- &fp[BB] - EAS2(t1, rFP, a3) # a3 <- &fp[CC] - LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 - LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 - .if 0 - or t0, a2, a3 # second arg (a2-a3) is zero? - beqz t0, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - addu v0, a2, a0 # optional op - addu a1, a3, a1; sltu v1, v0, a2; addu v1, v1, a1 # result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vAA/vAA+1 <- v0/v1 - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_long: /* 0x9c */ -/* File: mips/op_sub_long.S */ -/* - * For little endian the code sequence looks as follows: - * subu v0,a0,a2 - * subu v1,a1,a3 - * sltu a0,a0,v0 - * subu v1,v1,a0 - */ -/* File: mips/binopWide.S */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0-a1 op a2-a3". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register pair other than a0-a1, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a2-a3). Useful for integer division and modulus. - * - * for: add-long, sub-long, div-long, rem-long, and-long, or-long, - * xor-long - * - * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 # a3 <- CC - EAS2(a2, rFP, a2) # a2 <- &fp[BB] - EAS2(t1, rFP, a3) # a3 <- &fp[CC] - LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 - LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 - .if 0 - or t0, a2, a3 # second arg (a2-a3) is zero? - beqz t0, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - subu v0, a0, a2 # optional op - subu v1, a1, a3; sltu a0, a0, v0; subu v1, v1, a0 # result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vAA/vAA+1 <- v0/v1 - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_long: /* 0x9d */ -/* File: mips/op_mul_long.S */ - /* - * Signed 64-bit integer multiply. - * a1 a0 - * x a3 a2 - * ------------- - * a2a1 a2a0 - * a3a0 - * a3a1 (<= unused) - * --------------- - * v1 v0 - */ - /* mul-long vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - and t0, a0, 255 # a2 <- BB - srl t1, a0, 8 # a3 <- CC - EAS2(t0, rFP, t0) # t0 <- &fp[BB] - LOAD64(a0, a1, t0) # a0/a1 <- vBB/vBB+1 - - EAS2(t1, rFP, t1) # t0 <- &fp[CC] - LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 - - mul v1, a3, a0 # v1= a3a0 -#ifdef MIPS32REVGE6 - mulu v0, a2, a0 # v0= a2a0 - muhu t1, a2, a0 -#else - multu a2, a0 - mfhi t1 - mflo v0 # v0= a2a0 -#endif - mul t0, a2, a1 # t0= a2a1 - addu v1, v1, t1 # v1+= hi(a2a0) - addu v1, v1, t0 # v1= a3a0 + a2a1; - - GET_OPA(a0) # a0 <- AA - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - b .Lop_mul_long_finish - -/* ------------------------------ */ - .balign 128 -.L_op_div_long: /* 0x9e */ -/* File: mips/op_div_long.S */ -/* File: mips/binopWide.S */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0-a1 op a2-a3". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register pair other than a0-a1, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a2-a3). Useful for integer division and modulus. - * - * for: add-long, sub-long, div-long, rem-long, and-long, or-long, - * xor-long - * - * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 # a3 <- CC - EAS2(a2, rFP, a2) # a2 <- &fp[BB] - EAS2(t1, rFP, a3) # a3 <- &fp[CC] - LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 - LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 - .if 1 - or t0, a2, a3 # second arg (a2-a3) is zero? - beqz t0, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - # optional op - JAL(__divdi3) # result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vAA/vAA+1 <- v0/v1 - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_long: /* 0x9f */ -/* File: mips/op_rem_long.S */ -/* File: mips/binopWide.S */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0-a1 op a2-a3". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register pair other than a0-a1, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a2-a3). Useful for integer division and modulus. - * - * for: add-long, sub-long, div-long, rem-long, and-long, or-long, - * xor-long - * - * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 # a3 <- CC - EAS2(a2, rFP, a2) # a2 <- &fp[BB] - EAS2(t1, rFP, a3) # a3 <- &fp[CC] - LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 - LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 - .if 1 - or t0, a2, a3 # second arg (a2-a3) is zero? - beqz t0, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - # optional op - JAL(__moddi3) # result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vAA/vAA+1 <- v0/v1 - - -/* ------------------------------ */ - .balign 128 -.L_op_and_long: /* 0xa0 */ -/* File: mips/op_and_long.S */ -/* File: mips/binopWide.S */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0-a1 op a2-a3". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register pair other than a0-a1, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a2-a3). Useful for integer division and modulus. - * - * for: add-long, sub-long, div-long, rem-long, and-long, or-long, - * xor-long - * - * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 # a3 <- CC - EAS2(a2, rFP, a2) # a2 <- &fp[BB] - EAS2(t1, rFP, a3) # a3 <- &fp[CC] - LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 - LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 - .if 0 - or t0, a2, a3 # second arg (a2-a3) is zero? - beqz t0, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - and a0, a0, a2 # optional op - and a1, a1, a3 # result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vAA/vAA+1 <- a0/a1 - - -/* ------------------------------ */ - .balign 128 -.L_op_or_long: /* 0xa1 */ -/* File: mips/op_or_long.S */ -/* File: mips/binopWide.S */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0-a1 op a2-a3". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register pair other than a0-a1, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a2-a3). Useful for integer division and modulus. - * - * for: add-long, sub-long, div-long, rem-long, and-long, or-long, - * xor-long - * - * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 # a3 <- CC - EAS2(a2, rFP, a2) # a2 <- &fp[BB] - EAS2(t1, rFP, a3) # a3 <- &fp[CC] - LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 - LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 - .if 0 - or t0, a2, a3 # second arg (a2-a3) is zero? - beqz t0, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - or a0, a0, a2 # optional op - or a1, a1, a3 # result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vAA/vAA+1 <- a0/a1 - - -/* ------------------------------ */ - .balign 128 -.L_op_xor_long: /* 0xa2 */ -/* File: mips/op_xor_long.S */ -/* File: mips/binopWide.S */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0-a1 op a2-a3". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register pair other than a0-a1, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a2-a3). Useful for integer division and modulus. - * - * for: add-long, sub-long, div-long, rem-long, and-long, or-long, - * xor-long - * - * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 # a3 <- CC - EAS2(a2, rFP, a2) # a2 <- &fp[BB] - EAS2(t1, rFP, a3) # a3 <- &fp[CC] - LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 - LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 - .if 0 - or t0, a2, a3 # second arg (a2-a3) is zero? - beqz t0, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - xor a0, a0, a2 # optional op - xor a1, a1, a3 # result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vAA/vAA+1 <- a0/a1 - - -/* ------------------------------ */ - .balign 128 -.L_op_shl_long: /* 0xa3 */ -/* File: mips/op_shl_long.S */ - /* - * Long integer shift. This is different from the generic 32/64-bit - * binary operations because vAA/vBB are 64-bit but vCC (the shift - * distance) is 32-bit. Also, Dalvik requires us to mask off the low - * 6 bits of the shift distance. - */ - /* shl-long vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(t2) # t2 <- AA - and a3, a0, 255 # a3 <- BB - srl a0, a0, 8 # a0 <- CC - EAS2(a3, rFP, a3) # a3 <- &fp[BB] - GET_VREG(a2, a0) # a2 <- vCC - LOAD64(a0, a1, a3) # a0/a1 <- vBB/vBB+1 - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - - andi v1, a2, 0x20 # shift< shift & 0x20 - sll v0, a0, a2 # rlo<- alo << (shift&31) - bnez v1, .Lop_shl_long_finish - not v1, a2 # rhi<- 31-shift (shift is 5b) - srl a0, 1 - srl a0, v1 # alo<- alo >> (32-(shift&31)) - sll v1, a1, a2 # rhi<- ahi << (shift&31) - or v1, a0 # rhi<- rhi | alo - SET_VREG64_GOTO(v0, v1, t2, t0) # vAA/vAA+1 <- v0/v1 - -/* ------------------------------ */ - .balign 128 -.L_op_shr_long: /* 0xa4 */ -/* File: mips/op_shr_long.S */ - /* - * Long integer shift. This is different from the generic 32/64-bit - * binary operations because vAA/vBB are 64-bit but vCC (the shift - * distance) is 32-bit. Also, Dalvik requires us to mask off the low - * 6 bits of the shift distance. - */ - /* shr-long vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(t3) # t3 <- AA - and a3, a0, 255 # a3 <- BB - srl a0, a0, 8 # a0 <- CC - EAS2(a3, rFP, a3) # a3 <- &fp[BB] - GET_VREG(a2, a0) # a2 <- vCC - LOAD64(a0, a1, a3) # a0/a1 <- vBB/vBB+1 - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - - andi v0, a2, 0x20 # shift & 0x20 - sra v1, a1, a2 # rhi<- ahi >> (shift&31) - bnez v0, .Lop_shr_long_finish - srl v0, a0, a2 # rlo<- alo >> (shift&31) - not a0, a2 # alo<- 31-shift (shift is 5b) - sll a1, 1 - sll a1, a0 # ahi<- ahi << (32-(shift&31)) - or v0, a1 # rlo<- rlo | ahi - SET_VREG64_GOTO(v0, v1, t3, t0) # vAA/VAA+1 <- v0/v1 - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_long: /* 0xa5 */ -/* File: mips/op_ushr_long.S */ - /* - * Long integer shift. This is different from the generic 32/64-bit - * binary operations because vAA/vBB are 64-bit but vCC (the shift - * distance) is 32-bit. Also, Dalvik requires us to mask off the low - * 6 bits of the shift distance. - */ - /* ushr-long vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - and a3, a0, 255 # a3 <- BB - srl a0, a0, 8 # a0 <- CC - EAS2(a3, rFP, a3) # a3 <- &fp[BB] - GET_VREG(a2, a0) # a2 <- vCC - LOAD64(a0, a1, a3) # a0/a1 <- vBB/vBB+1 - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - - andi v0, a2, 0x20 # shift & 0x20 - srl v1, a1, a2 # rhi<- ahi >> (shift&31) - bnez v0, .Lop_ushr_long_finish - srl v0, a0, a2 # rlo<- alo >> (shift&31) - not a0, a2 # alo<- 31-n (shift is 5b) - sll a1, 1 - sll a1, a0 # ahi<- ahi << (32-(shift&31)) - or v0, a1 # rlo<- rlo | ahi - SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vAA/vAA+1 <- v0/v1 - -/* ------------------------------ */ - .balign 128 -.L_op_add_float: /* 0xa6 */ -/* File: mips/op_add_float.S */ -/* File: mips/fbinop.S */ - /* - * Generic 32-bit binary float operation. - * - * For: add-fp, sub-fp, mul-fp, div-fp, rem-fp - */ - - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - srl a3, a0, 8 # a3 <- CC - and a2, a0, 255 # a2 <- BB - GET_VREG_F(fa1, a3) # a1 <- vCC - GET_VREG_F(fa0, a2) # a0 <- vBB - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - add.s fv0, fa0, fa1 # f0 = result - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_F_GOTO(fv0, rOBJ, t0) # vAA <- fv0 - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_float: /* 0xa7 */ -/* File: mips/op_sub_float.S */ -/* File: mips/fbinop.S */ - /* - * Generic 32-bit binary float operation. - * - * For: add-fp, sub-fp, mul-fp, div-fp, rem-fp - */ - - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - srl a3, a0, 8 # a3 <- CC - and a2, a0, 255 # a2 <- BB - GET_VREG_F(fa1, a3) # a1 <- vCC - GET_VREG_F(fa0, a2) # a0 <- vBB - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - sub.s fv0, fa0, fa1 # f0 = result - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_F_GOTO(fv0, rOBJ, t0) # vAA <- fv0 - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_float: /* 0xa8 */ -/* File: mips/op_mul_float.S */ -/* File: mips/fbinop.S */ - /* - * Generic 32-bit binary float operation. - * - * For: add-fp, sub-fp, mul-fp, div-fp, rem-fp - */ - - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - srl a3, a0, 8 # a3 <- CC - and a2, a0, 255 # a2 <- BB - GET_VREG_F(fa1, a3) # a1 <- vCC - GET_VREG_F(fa0, a2) # a0 <- vBB - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - mul.s fv0, fa0, fa1 # f0 = result - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_F_GOTO(fv0, rOBJ, t0) # vAA <- fv0 - - -/* ------------------------------ */ - .balign 128 -.L_op_div_float: /* 0xa9 */ -/* File: mips/op_div_float.S */ -/* File: mips/fbinop.S */ - /* - * Generic 32-bit binary float operation. - * - * For: add-fp, sub-fp, mul-fp, div-fp, rem-fp - */ - - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - srl a3, a0, 8 # a3 <- CC - and a2, a0, 255 # a2 <- BB - GET_VREG_F(fa1, a3) # a1 <- vCC - GET_VREG_F(fa0, a2) # a0 <- vBB - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - div.s fv0, fa0, fa1 # f0 = result - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_F_GOTO(fv0, rOBJ, t0) # vAA <- fv0 - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_float: /* 0xaa */ -/* File: mips/op_rem_float.S */ -/* File: mips/fbinop.S */ - /* - * Generic 32-bit binary float operation. - * - * For: add-fp, sub-fp, mul-fp, div-fp, rem-fp - */ - - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - srl a3, a0, 8 # a3 <- CC - and a2, a0, 255 # a2 <- BB - GET_VREG_F(fa1, a3) # a1 <- vCC - GET_VREG_F(fa0, a2) # a0 <- vBB - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - JAL(fmodf) # f0 = result - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_F_GOTO(fv0, rOBJ, t0) # vAA <- fv0 - - -/* ------------------------------ */ - .balign 128 -.L_op_add_double: /* 0xab */ -/* File: mips/op_add_double.S */ -/* File: mips/fbinopWide.S */ - /* - * Generic 64-bit floating-point binary operation. Provide an "instr" - * line that specifies an instruction that performs "fv0 = fa0 op fa1". - * This could be an MIPS instruction or a function call. - * - * for: add-double, sub-double, mul-double, div-double, - * rem-double - * - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 # a3 <- CC - EAS2(a2, rFP, a2) # a2 <- &fp[BB] - EAS2(t1, rFP, a3) # a3 <- &fp[CC] - LOAD64_F(fa0, fa0f, a2) - LOAD64_F(fa1, fa1f, t1) - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - add.d fv0, fa0, fa1 - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vAA/vAA+1 <- fv0 - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_double: /* 0xac */ -/* File: mips/op_sub_double.S */ -/* File: mips/fbinopWide.S */ - /* - * Generic 64-bit floating-point binary operation. Provide an "instr" - * line that specifies an instruction that performs "fv0 = fa0 op fa1". - * This could be an MIPS instruction or a function call. - * - * for: add-double, sub-double, mul-double, div-double, - * rem-double - * - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 # a3 <- CC - EAS2(a2, rFP, a2) # a2 <- &fp[BB] - EAS2(t1, rFP, a3) # a3 <- &fp[CC] - LOAD64_F(fa0, fa0f, a2) - LOAD64_F(fa1, fa1f, t1) - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - sub.d fv0, fa0, fa1 - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vAA/vAA+1 <- fv0 - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_double: /* 0xad */ -/* File: mips/op_mul_double.S */ -/* File: mips/fbinopWide.S */ - /* - * Generic 64-bit floating-point binary operation. Provide an "instr" - * line that specifies an instruction that performs "fv0 = fa0 op fa1". - * This could be an MIPS instruction or a function call. - * - * for: add-double, sub-double, mul-double, div-double, - * rem-double - * - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 # a3 <- CC - EAS2(a2, rFP, a2) # a2 <- &fp[BB] - EAS2(t1, rFP, a3) # a3 <- &fp[CC] - LOAD64_F(fa0, fa0f, a2) - LOAD64_F(fa1, fa1f, t1) - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - mul.d fv0, fa0, fa1 - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vAA/vAA+1 <- fv0 - - -/* ------------------------------ */ - .balign 128 -.L_op_div_double: /* 0xae */ -/* File: mips/op_div_double.S */ -/* File: mips/fbinopWide.S */ - /* - * Generic 64-bit floating-point binary operation. Provide an "instr" - * line that specifies an instruction that performs "fv0 = fa0 op fa1". - * This could be an MIPS instruction or a function call. - * - * for: add-double, sub-double, mul-double, div-double, - * rem-double - * - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 # a3 <- CC - EAS2(a2, rFP, a2) # a2 <- &fp[BB] - EAS2(t1, rFP, a3) # a3 <- &fp[CC] - LOAD64_F(fa0, fa0f, a2) - LOAD64_F(fa1, fa1f, t1) - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - div.d fv0, fa0, fa1 - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vAA/vAA+1 <- fv0 - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_double: /* 0xaf */ -/* File: mips/op_rem_double.S */ -/* File: mips/fbinopWide.S */ - /* - * Generic 64-bit floating-point binary operation. Provide an "instr" - * line that specifies an instruction that performs "fv0 = fa0 op fa1". - * This could be an MIPS instruction or a function call. - * - * for: add-double, sub-double, mul-double, div-double, - * rem-double - * - */ - /* binop vAA, vBB, vCC */ - FETCH(a0, 1) # a0 <- CCBB - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a0, 255 # a2 <- BB - srl a3, a0, 8 # a3 <- CC - EAS2(a2, rFP, a2) # a2 <- &fp[BB] - EAS2(t1, rFP, a3) # a3 <- &fp[CC] - LOAD64_F(fa0, fa0f, a2) - LOAD64_F(fa1, fa1f, t1) - - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - JAL(fmod) - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vAA/vAA+1 <- fv0 - - -/* ------------------------------ */ - .balign 128 -.L_op_add_int_2addr: /* 0xb0 */ -/* File: mips/op_add_int_2addr.S */ -/* File: mips/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a0, rOBJ) # a0 <- vA - GET_VREG(a1, a3) # a1 <- vB - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - # optional op - addu a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_int_2addr: /* 0xb1 */ -/* File: mips/op_sub_int_2addr.S */ -/* File: mips/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a0, rOBJ) # a0 <- vA - GET_VREG(a1, a3) # a1 <- vB - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - # optional op - subu a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int_2addr: /* 0xb2 */ -/* File: mips/op_mul_int_2addr.S */ -/* File: mips/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a0, rOBJ) # a0 <- vA - GET_VREG(a1, a3) # a1 <- vB - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - # optional op - mul a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - - -/* ------------------------------ */ - .balign 128 -.L_op_div_int_2addr: /* 0xb3 */ -/* File: mips/op_div_int_2addr.S */ -#ifdef MIPS32REVGE6 -/* File: mips/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a0, rOBJ) # a0 <- vA - GET_VREG(a1, a3) # a1 <- vB - .if 1 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - # optional op - div a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - -#else -/* File: mips/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a0, rOBJ) # a0 <- vA - GET_VREG(a1, a3) # a1 <- vB - .if 1 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - div zero, a0, a1 # optional op - mflo a0 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - -#endif - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int_2addr: /* 0xb4 */ -/* File: mips/op_rem_int_2addr.S */ -#ifdef MIPS32REVGE6 -/* File: mips/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a0, rOBJ) # a0 <- vA - GET_VREG(a1, a3) # a1 <- vB - .if 1 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - # optional op - mod a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - -#else -/* File: mips/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a0, rOBJ) # a0 <- vA - GET_VREG(a1, a3) # a1 <- vB - .if 1 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - div zero, a0, a1 # optional op - mfhi a0 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - -#endif - -/* ------------------------------ */ - .balign 128 -.L_op_and_int_2addr: /* 0xb5 */ -/* File: mips/op_and_int_2addr.S */ -/* File: mips/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a0, rOBJ) # a0 <- vA - GET_VREG(a1, a3) # a1 <- vB - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - # optional op - and a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - - -/* ------------------------------ */ - .balign 128 -.L_op_or_int_2addr: /* 0xb6 */ -/* File: mips/op_or_int_2addr.S */ -/* File: mips/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a0, rOBJ) # a0 <- vA - GET_VREG(a1, a3) # a1 <- vB - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - # optional op - or a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int_2addr: /* 0xb7 */ -/* File: mips/op_xor_int_2addr.S */ -/* File: mips/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a0, rOBJ) # a0 <- vA - GET_VREG(a1, a3) # a1 <- vB - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - # optional op - xor a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - - -/* ------------------------------ */ - .balign 128 -.L_op_shl_int_2addr: /* 0xb8 */ -/* File: mips/op_shl_int_2addr.S */ -/* File: mips/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a0, rOBJ) # a0 <- vA - GET_VREG(a1, a3) # a1 <- vB - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - # optional op - sll a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - - -/* ------------------------------ */ - .balign 128 -.L_op_shr_int_2addr: /* 0xb9 */ -/* File: mips/op_shr_int_2addr.S */ -/* File: mips/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a0, rOBJ) # a0 <- vA - GET_VREG(a1, a3) # a1 <- vB - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - # optional op - sra a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_int_2addr: /* 0xba */ -/* File: mips/op_ushr_int_2addr.S */ -/* File: mips/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a0, rOBJ) # a0 <- vA - GET_VREG(a1, a3) # a1 <- vB - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - # optional op - srl a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - - -/* ------------------------------ */ - .balign 128 -.L_op_add_long_2addr: /* 0xbb */ -/* File: mips/op_add_long_2addr.S */ -/* - * See op_add_long.S for details - */ -/* File: mips/binopWide2addr.S */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0-a1 op a2-a3". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register pair other than a0-a1, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a2-a3). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a1) # a1 <- B - EAS2(a1, rFP, a1) # a1 <- &fp[B] - EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] - LOAD64(a2, a3, a1) # a2/a3 <- vB/vB+1 - LOAD64(a0, a1, t0) # a0/a1 <- vA/vA+1 - .if 0 - or t0, a2, a3 # second arg (a2-a3) is zero? - beqz t0, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - addu v0, a2, a0 # optional op - addu a1, a3, a1; sltu v1, v0, a2; addu v1, v1, a1 # result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vA/vA+1 <- v0/v1 - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_long_2addr: /* 0xbc */ -/* File: mips/op_sub_long_2addr.S */ -/* - * See op_sub_long.S for more details - */ -/* File: mips/binopWide2addr.S */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0-a1 op a2-a3". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register pair other than a0-a1, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a2-a3). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a1) # a1 <- B - EAS2(a1, rFP, a1) # a1 <- &fp[B] - EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] - LOAD64(a2, a3, a1) # a2/a3 <- vB/vB+1 - LOAD64(a0, a1, t0) # a0/a1 <- vA/vA+1 - .if 0 - or t0, a2, a3 # second arg (a2-a3) is zero? - beqz t0, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - subu v0, a0, a2 # optional op - subu v1, a1, a3; sltu a0, a0, v0; subu v1, v1, a0 # result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vA/vA+1 <- v0/v1 - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_long_2addr: /* 0xbd */ -/* File: mips/op_mul_long_2addr.S */ - /* - * See op_mul_long.S for more details - */ - /* mul-long/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - - EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] - LOAD64(a0, a1, t0) # vAA.low / high - - GET_OPB(t1) # t1 <- B - EAS2(t1, rFP, t1) # t1 <- &fp[B] - LOAD64(a2, a3, t1) # vBB.low / high - - mul v1, a3, a0 # v1= a3a0 -#ifdef MIPS32REVGE6 - mulu v0, a2, a0 # v0= a2a0 - muhu t1, a2, a0 -#else - multu a2, a0 - mfhi t1 - mflo v0 # v0= a2a0 - #endif - mul t2, a2, a1 # t2= a2a1 - addu v1, v1, t1 # v1= a3a0 + hi(a2a0) - addu v1, v1, t2 # v1= v1 + a2a1; - - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - GET_INST_OPCODE(t1) # extract opcode from rINST - SET_VREG64_GOTO(v0, v1, rOBJ, t1) # vA/vA+1 <- v0(low)/v1(high) - -/* ------------------------------ */ - .balign 128 -.L_op_div_long_2addr: /* 0xbe */ -/* File: mips/op_div_long_2addr.S */ -/* File: mips/binopWide2addr.S */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0-a1 op a2-a3". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register pair other than a0-a1, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a2-a3). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a1) # a1 <- B - EAS2(a1, rFP, a1) # a1 <- &fp[B] - EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] - LOAD64(a2, a3, a1) # a2/a3 <- vB/vB+1 - LOAD64(a0, a1, t0) # a0/a1 <- vA/vA+1 - .if 1 - or t0, a2, a3 # second arg (a2-a3) is zero? - beqz t0, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - # optional op - JAL(__divdi3) # result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vA/vA+1 <- v0/v1 - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_long_2addr: /* 0xbf */ -/* File: mips/op_rem_long_2addr.S */ -/* File: mips/binopWide2addr.S */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0-a1 op a2-a3". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register pair other than a0-a1, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a2-a3). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a1) # a1 <- B - EAS2(a1, rFP, a1) # a1 <- &fp[B] - EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] - LOAD64(a2, a3, a1) # a2/a3 <- vB/vB+1 - LOAD64(a0, a1, t0) # a0/a1 <- vA/vA+1 - .if 1 - or t0, a2, a3 # second arg (a2-a3) is zero? - beqz t0, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - # optional op - JAL(__moddi3) # result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vA/vA+1 <- v0/v1 - - -/* ------------------------------ */ - .balign 128 -.L_op_and_long_2addr: /* 0xc0 */ -/* File: mips/op_and_long_2addr.S */ -/* File: mips/binopWide2addr.S */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0-a1 op a2-a3". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register pair other than a0-a1, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a2-a3). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a1) # a1 <- B - EAS2(a1, rFP, a1) # a1 <- &fp[B] - EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] - LOAD64(a2, a3, a1) # a2/a3 <- vB/vB+1 - LOAD64(a0, a1, t0) # a0/a1 <- vA/vA+1 - .if 0 - or t0, a2, a3 # second arg (a2-a3) is zero? - beqz t0, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - and a0, a0, a2 # optional op - and a1, a1, a3 # result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vA/vA+1 <- a0/a1 - - -/* ------------------------------ */ - .balign 128 -.L_op_or_long_2addr: /* 0xc1 */ -/* File: mips/op_or_long_2addr.S */ -/* File: mips/binopWide2addr.S */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0-a1 op a2-a3". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register pair other than a0-a1, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a2-a3). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a1) # a1 <- B - EAS2(a1, rFP, a1) # a1 <- &fp[B] - EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] - LOAD64(a2, a3, a1) # a2/a3 <- vB/vB+1 - LOAD64(a0, a1, t0) # a0/a1 <- vA/vA+1 - .if 0 - or t0, a2, a3 # second arg (a2-a3) is zero? - beqz t0, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - or a0, a0, a2 # optional op - or a1, a1, a3 # result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vA/vA+1 <- a0/a1 - - -/* ------------------------------ */ - .balign 128 -.L_op_xor_long_2addr: /* 0xc2 */ -/* File: mips/op_xor_long_2addr.S */ -/* File: mips/binopWide2addr.S */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0-a1 op a2-a3". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register pair other than a0-a1, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a2-a3). Useful for integer division and modulus. - * - * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, - * and-long/2addr, or-long/2addr, xor-long/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a1) # a1 <- B - EAS2(a1, rFP, a1) # a1 <- &fp[B] - EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] - LOAD64(a2, a3, a1) # a2/a3 <- vB/vB+1 - LOAD64(a0, a1, t0) # a0/a1 <- vA/vA+1 - .if 0 - or t0, a2, a3 # second arg (a2-a3) is zero? - beqz t0, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - xor a0, a0, a2 # optional op - xor a1, a1, a3 # result <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vA/vA+1 <- a0/a1 - - -/* ------------------------------ */ - .balign 128 -.L_op_shl_long_2addr: /* 0xc3 */ -/* File: mips/op_shl_long_2addr.S */ - /* - * Long integer shift, 2addr version. vA is 64-bit value/result, vB is - * 32-bit shift distance. - */ - /* shl-long/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a2, a3) # a2 <- vB - EAS2(t2, rFP, rOBJ) # t2 <- &fp[A] - LOAD64(a0, a1, t2) # a0/a1 <- vA/vA+1 - - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - - andi v1, a2, 0x20 # shift< shift & 0x20 - sll v0, a0, a2 # rlo<- alo << (shift&31) - bnez v1, .Lop_shl_long_2addr_finish - not v1, a2 # rhi<- 31-shift (shift is 5b) - srl a0, 1 - srl a0, v1 # alo<- alo >> (32-(shift&31)) - sll v1, a1, a2 # rhi<- ahi << (shift&31) - or v1, a0 # rhi<- rhi | alo - SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vA/vA+1 <- v0/v1 - -/* ------------------------------ */ - .balign 128 -.L_op_shr_long_2addr: /* 0xc4 */ -/* File: mips/op_shr_long_2addr.S */ - /* - * Long integer shift, 2addr version. vA is 64-bit value/result, vB is - * 32-bit shift distance. - */ - /* shr-long/2addr vA, vB */ - GET_OPA4(t2) # t2 <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a2, a3) # a2 <- vB - EAS2(t0, rFP, t2) # t0 <- &fp[A] - LOAD64(a0, a1, t0) # a0/a1 <- vA/vA+1 - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - - andi v0, a2, 0x20 # shift & 0x20 - sra v1, a1, a2 # rhi<- ahi >> (shift&31) - bnez v0, .Lop_shr_long_2addr_finish - srl v0, a0, a2 # rlo<- alo >> (shift&31) - not a0, a2 # alo<- 31-shift (shift is 5b) - sll a1, 1 - sll a1, a0 # ahi<- ahi << (32-(shift&31)) - or v0, a1 # rlo<- rlo | ahi - SET_VREG64_GOTO(v0, v1, t2, t0) # vA/vA+1 <- v0/v1 - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_long_2addr: /* 0xc5 */ -/* File: mips/op_ushr_long_2addr.S */ - /* - * Long integer shift, 2addr version. vA is 64-bit value/result, vB is - * 32-bit shift distance. - */ - /* ushr-long/2addr vA, vB */ - GET_OPA4(t3) # t3 <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG(a2, a3) # a2 <- vB - EAS2(t0, rFP, t3) # t0 <- &fp[A] - LOAD64(a0, a1, t0) # a0/a1 <- vA/vA+1 - - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - - andi v0, a2, 0x20 # shift & 0x20 - srl v1, a1, a2 # rhi<- ahi >> (shift&31) - bnez v0, .Lop_ushr_long_2addr_finish - srl v0, a0, a2 # rlo<- alo >> (shift&31) - not a0, a2 # alo<- 31-n (shift is 5b) - sll a1, 1 - sll a1, a0 # ahi<- ahi << (32-(shift&31)) - or v0, a1 # rlo<- rlo | ahi - SET_VREG64_GOTO(v0, v1, t3, t0) # vA/vA+1 <- v0/v1 - -/* ------------------------------ */ - .balign 128 -.L_op_add_float_2addr: /* 0xc6 */ -/* File: mips/op_add_float_2addr.S */ -/* File: mips/fbinop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" - * that specifies an instruction that performs "fv0 = fa0 op fa1". - * This could be an MIPS instruction or a function call. - * - * For: add-float/2addr, sub-float/2addr, mul-float/2addr, - * div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG_F(fa0, rOBJ) - GET_VREG_F(fa1, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - add.s fv0, fa0, fa1 - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_F_GOTO(fv0, rOBJ, t0) # vA <- result - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_float_2addr: /* 0xc7 */ -/* File: mips/op_sub_float_2addr.S */ -/* File: mips/fbinop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" - * that specifies an instruction that performs "fv0 = fa0 op fa1". - * This could be an MIPS instruction or a function call. - * - * For: add-float/2addr, sub-float/2addr, mul-float/2addr, - * div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG_F(fa0, rOBJ) - GET_VREG_F(fa1, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - sub.s fv0, fa0, fa1 - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_F_GOTO(fv0, rOBJ, t0) # vA <- result - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_float_2addr: /* 0xc8 */ -/* File: mips/op_mul_float_2addr.S */ -/* File: mips/fbinop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" - * that specifies an instruction that performs "fv0 = fa0 op fa1". - * This could be an MIPS instruction or a function call. - * - * For: add-float/2addr, sub-float/2addr, mul-float/2addr, - * div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG_F(fa0, rOBJ) - GET_VREG_F(fa1, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - mul.s fv0, fa0, fa1 - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_F_GOTO(fv0, rOBJ, t0) # vA <- result - - -/* ------------------------------ */ - .balign 128 -.L_op_div_float_2addr: /* 0xc9 */ -/* File: mips/op_div_float_2addr.S */ -/* File: mips/fbinop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" - * that specifies an instruction that performs "fv0 = fa0 op fa1". - * This could be an MIPS instruction or a function call. - * - * For: add-float/2addr, sub-float/2addr, mul-float/2addr, - * div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG_F(fa0, rOBJ) - GET_VREG_F(fa1, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - div.s fv0, fa0, fa1 - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_F_GOTO(fv0, rOBJ, t0) # vA <- result - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_float_2addr: /* 0xca */ -/* File: mips/op_rem_float_2addr.S */ -/* File: mips/fbinop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" - * that specifies an instruction that performs "fv0 = fa0 op fa1". - * This could be an MIPS instruction or a function call. - * - * For: add-float/2addr, sub-float/2addr, mul-float/2addr, - * div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a3) # a3 <- B - GET_VREG_F(fa0, rOBJ) - GET_VREG_F(fa1, a3) - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - - JAL(fmodf) - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_F_GOTO(fv0, rOBJ, t0) # vA <- result - - -/* ------------------------------ */ - .balign 128 -.L_op_add_double_2addr: /* 0xcb */ -/* File: mips/op_add_double_2addr.S */ -/* File: mips/fbinopWide2addr.S */ - /* - * Generic 64-bit floating-point "/2addr" binary operation. - * Provide an "instr" line that specifies an instruction that - * performs "fv0 = fa0 op fa1". - * This could be an MIPS instruction or a function call. - * - * For: add-double/2addr, sub-double/2addr, mul-double/2addr, - * div-double/2addr, rem-double/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a1) # a1 <- B - EAS2(a1, rFP, a1) # a1 <- &fp[B] - EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] - LOAD64_F(fa0, fa0f, t0) - LOAD64_F(fa1, fa1f, a1) - - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - add.d fv0, fa0, fa1 - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vA/vA+1 <- fv0 - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_double_2addr: /* 0xcc */ -/* File: mips/op_sub_double_2addr.S */ -/* File: mips/fbinopWide2addr.S */ - /* - * Generic 64-bit floating-point "/2addr" binary operation. - * Provide an "instr" line that specifies an instruction that - * performs "fv0 = fa0 op fa1". - * This could be an MIPS instruction or a function call. - * - * For: add-double/2addr, sub-double/2addr, mul-double/2addr, - * div-double/2addr, rem-double/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a1) # a1 <- B - EAS2(a1, rFP, a1) # a1 <- &fp[B] - EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] - LOAD64_F(fa0, fa0f, t0) - LOAD64_F(fa1, fa1f, a1) - - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - sub.d fv0, fa0, fa1 - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vA/vA+1 <- fv0 - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_double_2addr: /* 0xcd */ -/* File: mips/op_mul_double_2addr.S */ -/* File: mips/fbinopWide2addr.S */ - /* - * Generic 64-bit floating-point "/2addr" binary operation. - * Provide an "instr" line that specifies an instruction that - * performs "fv0 = fa0 op fa1". - * This could be an MIPS instruction or a function call. - * - * For: add-double/2addr, sub-double/2addr, mul-double/2addr, - * div-double/2addr, rem-double/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a1) # a1 <- B - EAS2(a1, rFP, a1) # a1 <- &fp[B] - EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] - LOAD64_F(fa0, fa0f, t0) - LOAD64_F(fa1, fa1f, a1) - - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - mul.d fv0, fa0, fa1 - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vA/vA+1 <- fv0 - - -/* ------------------------------ */ - .balign 128 -.L_op_div_double_2addr: /* 0xce */ -/* File: mips/op_div_double_2addr.S */ -/* File: mips/fbinopWide2addr.S */ - /* - * Generic 64-bit floating-point "/2addr" binary operation. - * Provide an "instr" line that specifies an instruction that - * performs "fv0 = fa0 op fa1". - * This could be an MIPS instruction or a function call. - * - * For: add-double/2addr, sub-double/2addr, mul-double/2addr, - * div-double/2addr, rem-double/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a1) # a1 <- B - EAS2(a1, rFP, a1) # a1 <- &fp[B] - EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] - LOAD64_F(fa0, fa0f, t0) - LOAD64_F(fa1, fa1f, a1) - - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - div.d fv0, fa0, fa1 - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vA/vA+1 <- fv0 - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_double_2addr: /* 0xcf */ -/* File: mips/op_rem_double_2addr.S */ -/* File: mips/fbinopWide2addr.S */ - /* - * Generic 64-bit floating-point "/2addr" binary operation. - * Provide an "instr" line that specifies an instruction that - * performs "fv0 = fa0 op fa1". - * This could be an MIPS instruction or a function call. - * - * For: add-double/2addr, sub-double/2addr, mul-double/2addr, - * div-double/2addr, rem-double/2addr - */ - /* binop/2addr vA, vB */ - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_OPB(a1) # a1 <- B - EAS2(a1, rFP, a1) # a1 <- &fp[B] - EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] - LOAD64_F(fa0, fa0f, t0) - LOAD64_F(fa1, fa1f, a1) - - FETCH_ADVANCE_INST(1) # advance rPC, load rINST - JAL(fmod) - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vA/vA+1 <- fv0 - - -/* ------------------------------ */ - .balign 128 -.L_op_add_int_lit16: /* 0xd0 */ -/* File: mips/op_add_int_lit16.S */ -/* File: mips/binopLit16.S */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, +CCCC */ - FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) - GET_OPB(a2) # a2 <- B - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_VREG(a0, a2) # a0 <- vB - .if 0 - # cmp a1, 0; is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - # optional op - addu a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - - -/* ------------------------------ */ - .balign 128 -.L_op_rsub_int: /* 0xd1 */ -/* File: mips/op_rsub_int.S */ -/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ -/* File: mips/binopLit16.S */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, +CCCC */ - FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) - GET_OPB(a2) # a2 <- B - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_VREG(a0, a2) # a0 <- vB - .if 0 - # cmp a1, 0; is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - # optional op - subu a0, a1, a0 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int_lit16: /* 0xd2 */ -/* File: mips/op_mul_int_lit16.S */ -/* File: mips/binopLit16.S */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, +CCCC */ - FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) - GET_OPB(a2) # a2 <- B - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_VREG(a0, a2) # a0 <- vB - .if 0 - # cmp a1, 0; is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - # optional op - mul a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - - -/* ------------------------------ */ - .balign 128 -.L_op_div_int_lit16: /* 0xd3 */ -/* File: mips/op_div_int_lit16.S */ -#ifdef MIPS32REVGE6 -/* File: mips/binopLit16.S */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, +CCCC */ - FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) - GET_OPB(a2) # a2 <- B - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_VREG(a0, a2) # a0 <- vB - .if 1 - # cmp a1, 0; is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - # optional op - div a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - -#else -/* File: mips/binopLit16.S */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, +CCCC */ - FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) - GET_OPB(a2) # a2 <- B - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_VREG(a0, a2) # a0 <- vB - .if 1 - # cmp a1, 0; is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - div zero, a0, a1 # optional op - mflo a0 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - -#endif - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int_lit16: /* 0xd4 */ -/* File: mips/op_rem_int_lit16.S */ -#ifdef MIPS32REVGE6 -/* File: mips/binopLit16.S */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, +CCCC */ - FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) - GET_OPB(a2) # a2 <- B - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_VREG(a0, a2) # a0 <- vB - .if 1 - # cmp a1, 0; is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - # optional op - mod a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - -#else -/* File: mips/binopLit16.S */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, +CCCC */ - FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) - GET_OPB(a2) # a2 <- B - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_VREG(a0, a2) # a0 <- vB - .if 1 - # cmp a1, 0; is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - div zero, a0, a1 # optional op - mfhi a0 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - -#endif - -/* ------------------------------ */ - .balign 128 -.L_op_and_int_lit16: /* 0xd5 */ -/* File: mips/op_and_int_lit16.S */ -/* File: mips/binopLit16.S */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, +CCCC */ - FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) - GET_OPB(a2) # a2 <- B - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_VREG(a0, a2) # a0 <- vB - .if 0 - # cmp a1, 0; is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - # optional op - and a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - - -/* ------------------------------ */ - .balign 128 -.L_op_or_int_lit16: /* 0xd6 */ -/* File: mips/op_or_int_lit16.S */ -/* File: mips/binopLit16.S */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, +CCCC */ - FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) - GET_OPB(a2) # a2 <- B - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_VREG(a0, a2) # a0 <- vB - .if 0 - # cmp a1, 0; is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - # optional op - or a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int_lit16: /* 0xd7 */ -/* File: mips/op_xor_int_lit16.S */ -/* File: mips/binopLit16.S */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, +CCCC */ - FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) - GET_OPB(a2) # a2 <- B - GET_OPA4(rOBJ) # rOBJ <- A+ - GET_VREG(a0, a2) # a0 <- vB - .if 0 - # cmp a1, 0; is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - # optional op - xor a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 - - -/* ------------------------------ */ - .balign 128 -.L_op_add_int_lit8: /* 0xd8 */ -/* File: mips/op_add_int_lit8.S */ -/* File: mips/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, +CC */ - FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a3, 255 # a2 <- BB - GET_VREG(a0, a2) # a0 <- vBB - sra a1, a3, 8 # a1 <- ssssssCC (sign extended) - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - # optional op - addu a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - - -/* ------------------------------ */ - .balign 128 -.L_op_rsub_int_lit8: /* 0xd9 */ -/* File: mips/op_rsub_int_lit8.S */ -/* File: mips/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, +CC */ - FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a3, 255 # a2 <- BB - GET_VREG(a0, a2) # a0 <- vBB - sra a1, a3, 8 # a1 <- ssssssCC (sign extended) - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - # optional op - subu a0, a1, a0 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int_lit8: /* 0xda */ -/* File: mips/op_mul_int_lit8.S */ -/* File: mips/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, +CC */ - FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a3, 255 # a2 <- BB - GET_VREG(a0, a2) # a0 <- vBB - sra a1, a3, 8 # a1 <- ssssssCC (sign extended) - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - # optional op - mul a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - - -/* ------------------------------ */ - .balign 128 -.L_op_div_int_lit8: /* 0xdb */ -/* File: mips/op_div_int_lit8.S */ -#ifdef MIPS32REVGE6 -/* File: mips/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, +CC */ - FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a3, 255 # a2 <- BB - GET_VREG(a0, a2) # a0 <- vBB - sra a1, a3, 8 # a1 <- ssssssCC (sign extended) - .if 1 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - # optional op - div a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - -#else -/* File: mips/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, +CC */ - FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a3, 255 # a2 <- BB - GET_VREG(a0, a2) # a0 <- vBB - sra a1, a3, 8 # a1 <- ssssssCC (sign extended) - .if 1 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - div zero, a0, a1 # optional op - mflo a0 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - -#endif - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int_lit8: /* 0xdc */ -/* File: mips/op_rem_int_lit8.S */ -#ifdef MIPS32REVGE6 -/* File: mips/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, +CC */ - FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a3, 255 # a2 <- BB - GET_VREG(a0, a2) # a0 <- vBB - sra a1, a3, 8 # a1 <- ssssssCC (sign extended) - .if 1 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - # optional op - mod a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - -#else -/* File: mips/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, +CC */ - FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a3, 255 # a2 <- BB - GET_VREG(a0, a2) # a0 <- vBB - sra a1, a3, 8 # a1 <- ssssssCC (sign extended) - .if 1 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - div zero, a0, a1 # optional op - mfhi a0 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - -#endif - -/* ------------------------------ */ - .balign 128 -.L_op_and_int_lit8: /* 0xdd */ -/* File: mips/op_and_int_lit8.S */ -/* File: mips/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, +CC */ - FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a3, 255 # a2 <- BB - GET_VREG(a0, a2) # a0 <- vBB - sra a1, a3, 8 # a1 <- ssssssCC (sign extended) - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - # optional op - and a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - - -/* ------------------------------ */ - .balign 128 -.L_op_or_int_lit8: /* 0xde */ -/* File: mips/op_or_int_lit8.S */ -/* File: mips/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, +CC */ - FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a3, 255 # a2 <- BB - GET_VREG(a0, a2) # a0 <- vBB - sra a1, a3, 8 # a1 <- ssssssCC (sign extended) - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - # optional op - or a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int_lit8: /* 0xdf */ -/* File: mips/op_xor_int_lit8.S */ -/* File: mips/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, +CC */ - FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a3, 255 # a2 <- BB - GET_VREG(a0, a2) # a0 <- vBB - sra a1, a3, 8 # a1 <- ssssssCC (sign extended) - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - # optional op - xor a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - - -/* ------------------------------ */ - .balign 128 -.L_op_shl_int_lit8: /* 0xe0 */ -/* File: mips/op_shl_int_lit8.S */ -/* File: mips/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, +CC */ - FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a3, 255 # a2 <- BB - GET_VREG(a0, a2) # a0 <- vBB - sra a1, a3, 8 # a1 <- ssssssCC (sign extended) - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - # optional op - sll a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - - -/* ------------------------------ */ - .balign 128 -.L_op_shr_int_lit8: /* 0xe1 */ -/* File: mips/op_shr_int_lit8.S */ -/* File: mips/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, +CC */ - FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a3, 255 # a2 <- BB - GET_VREG(a0, a2) # a0 <- vBB - sra a1, a3, 8 # a1 <- ssssssCC (sign extended) - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - # optional op - sra a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_int_lit8: /* 0xe2 */ -/* File: mips/op_ushr_int_lit8.S */ -/* File: mips/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, +CC */ - FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) - GET_OPA(rOBJ) # rOBJ <- AA - and a2, a3, 255 # a2 <- BB - GET_VREG(a0, a2) # a0 <- vBB - sra a1, a3, 8 # a1 <- ssssssCC (sign extended) - .if 0 - # is second operand zero? - beqz a1, common_errDivideByZero - .endif - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - - # optional op - srl a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_quick: /* 0xe3 */ -/* File: mips/op_iget_quick.S */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset@CCCC */ - GET_OPB(a2) # a2 <- B - GET_VREG(a3, a2) # a3 <- object we're operating on - FETCH(a1, 1) # a1 <- field byte offset - GET_OPA4(a2) # a2 <- A(+) - # check object for null - beqz a3, common_errNullObject # object was null - addu t0, a3, a1 - lw a0, 0(t0) # a0 <- obj.field (8/16/32 bits) - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, a2, t0) # fp[A] <- a0 - -/* ------------------------------ */ - .balign 128 -.L_op_iget_wide_quick: /* 0xe4 */ -/* File: mips/op_iget_wide_quick.S */ - /* iget-wide-quick vA, vB, offset@CCCC */ - GET_OPB(a2) # a2 <- B - GET_VREG(a3, a2) # a3 <- object we're operating on - FETCH(a1, 1) # a1 <- field byte offset - GET_OPA4(a2) # a2 <- A(+) - # check object for null - beqz a3, common_errNullObject # object was null - addu t0, a3, a1 # t0 <- a3 + a1 - LOAD64(a0, a1, t0) # a0 <- obj.field (64 bits, aligned) - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(a0, a1, a2, t0) # fp[A] <- a0/a1 - -/* ------------------------------ */ - .balign 128 -.L_op_iget_object_quick: /* 0xe5 */ -/* File: mips/op_iget_object_quick.S */ - /* For: iget-object-quick */ - /* op vA, vB, offset@CCCC */ - GET_OPB(a2) # a2 <- B - FETCH(a1, 1) # a1 <- field byte offset - EXPORT_PC() - GET_VREG(a0, a2) # a0 <- object we're operating on - JAL(artIGetObjectFromMterp) # v0 <- GetObj(obj, offset) - lw a3, THREAD_EXCEPTION_OFFSET(rSELF) - GET_OPA4(a2) # a2<- A+ - PREFETCH_INST(2) # load rINST - bnez a3, MterpPossibleException # bail out - ADVANCE(2) # advance rPC - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_OBJECT_GOTO(v0, a2, t0) # fp[A] <- v0 - -/* ------------------------------ */ - .balign 128 -.L_op_iput_quick: /* 0xe6 */ -/* File: mips/op_iput_quick.S */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - GET_OPB(a2) # a2 <- B - GET_VREG(a3, a2) # a3 <- fp[B], the object pointer - FETCH(a1, 1) # a1 <- field byte offset - GET_OPA4(a2) # a2 <- A(+) - beqz a3, common_errNullObject # object was null - GET_VREG(a0, a2) # a0 <- fp[A] - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - addu t0, a3, a1 - GET_INST_OPCODE(t1) # extract opcode from rINST - GET_OPCODE_TARGET(t1) - sw a0, 0(t0) # obj.field (8/16/32 bits) <- a0 - JR(t1) # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_wide_quick: /* 0xe7 */ -/* File: mips/op_iput_wide_quick.S */ - /* iput-wide-quick vA, vB, offset@CCCC */ - GET_OPA4(a0) # a0 <- A(+) - GET_OPB(a1) # a1 <- B - GET_VREG(a2, a1) # a2 <- fp[B], the object pointer - # check object for null - beqz a2, common_errNullObject # object was null - EAS2(a3, rFP, a0) # a3 <- &fp[A] - LOAD64(a0, a1, a3) # a0/a1 <- fp[A] - FETCH(a3, 1) # a3 <- field byte offset - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - addu a2, a2, a3 # obj.field (64 bits, aligned) <- a0/a1 - GET_INST_OPCODE(t0) # extract opcode from rINST - GET_OPCODE_TARGET(t0) - STORE64(a0, a1, a2) # obj.field (64 bits, aligned) <- a0/a1 - JR(t0) # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_object_quick: /* 0xe8 */ -/* File: mips/op_iput_object_quick.S */ - /* For: iput-object-quick */ - /* op vA, vB, offset@CCCC */ - EXPORT_PC() - addu a0, rFP, OFF_FP_SHADOWFRAME - move a1, rPC - move a2, rINST - JAL(MterpIputObjectQuick) - beqz v0, MterpException - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual_quick: /* 0xe9 */ -/* File: mips/op_invoke_virtual_quick.S */ -/* File: mips/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtualQuick - EXPORT_PC() - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - JAL(MterpInvokeVirtualQuick) - beqz v0, MterpException - FETCH_ADVANCE_INST(3) - JAL(MterpShouldSwitchInterpreters) - bnez v0, MterpFallback - GET_INST_OPCODE(t0) - GOTO_OPCODE(t0) - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual_range_quick: /* 0xea */ -/* File: mips/op_invoke_virtual_range_quick.S */ -/* File: mips/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtualQuickRange - EXPORT_PC() - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - JAL(MterpInvokeVirtualQuickRange) - beqz v0, MterpException - FETCH_ADVANCE_INST(3) - JAL(MterpShouldSwitchInterpreters) - bnez v0, MterpFallback - GET_INST_OPCODE(t0) - GOTO_OPCODE(t0) - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_boolean_quick: /* 0xeb */ -/* File: mips/op_iput_boolean_quick.S */ -/* File: mips/op_iput_quick.S */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - GET_OPB(a2) # a2 <- B - GET_VREG(a3, a2) # a3 <- fp[B], the object pointer - FETCH(a1, 1) # a1 <- field byte offset - GET_OPA4(a2) # a2 <- A(+) - beqz a3, common_errNullObject # object was null - GET_VREG(a0, a2) # a0 <- fp[A] - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - addu t0, a3, a1 - GET_INST_OPCODE(t1) # extract opcode from rINST - GET_OPCODE_TARGET(t1) - sb a0, 0(t0) # obj.field (8/16/32 bits) <- a0 - JR(t1) # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_byte_quick: /* 0xec */ -/* File: mips/op_iput_byte_quick.S */ -/* File: mips/op_iput_quick.S */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - GET_OPB(a2) # a2 <- B - GET_VREG(a3, a2) # a3 <- fp[B], the object pointer - FETCH(a1, 1) # a1 <- field byte offset - GET_OPA4(a2) # a2 <- A(+) - beqz a3, common_errNullObject # object was null - GET_VREG(a0, a2) # a0 <- fp[A] - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - addu t0, a3, a1 - GET_INST_OPCODE(t1) # extract opcode from rINST - GET_OPCODE_TARGET(t1) - sb a0, 0(t0) # obj.field (8/16/32 bits) <- a0 - JR(t1) # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_char_quick: /* 0xed */ -/* File: mips/op_iput_char_quick.S */ -/* File: mips/op_iput_quick.S */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - GET_OPB(a2) # a2 <- B - GET_VREG(a3, a2) # a3 <- fp[B], the object pointer - FETCH(a1, 1) # a1 <- field byte offset - GET_OPA4(a2) # a2 <- A(+) - beqz a3, common_errNullObject # object was null - GET_VREG(a0, a2) # a0 <- fp[A] - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - addu t0, a3, a1 - GET_INST_OPCODE(t1) # extract opcode from rINST - GET_OPCODE_TARGET(t1) - sh a0, 0(t0) # obj.field (8/16/32 bits) <- a0 - JR(t1) # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_short_quick: /* 0xee */ -/* File: mips/op_iput_short_quick.S */ -/* File: mips/op_iput_quick.S */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - GET_OPB(a2) # a2 <- B - GET_VREG(a3, a2) # a3 <- fp[B], the object pointer - FETCH(a1, 1) # a1 <- field byte offset - GET_OPA4(a2) # a2 <- A(+) - beqz a3, common_errNullObject # object was null - GET_VREG(a0, a2) # a0 <- fp[A] - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - addu t0, a3, a1 - GET_INST_OPCODE(t1) # extract opcode from rINST - GET_OPCODE_TARGET(t1) - sh a0, 0(t0) # obj.field (8/16/32 bits) <- a0 - JR(t1) # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_boolean_quick: /* 0xef */ -/* File: mips/op_iget_boolean_quick.S */ -/* File: mips/op_iget_quick.S */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset@CCCC */ - GET_OPB(a2) # a2 <- B - GET_VREG(a3, a2) # a3 <- object we're operating on - FETCH(a1, 1) # a1 <- field byte offset - GET_OPA4(a2) # a2 <- A(+) - # check object for null - beqz a3, common_errNullObject # object was null - addu t0, a3, a1 - lbu a0, 0(t0) # a0 <- obj.field (8/16/32 bits) - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, a2, t0) # fp[A] <- a0 - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_byte_quick: /* 0xf0 */ -/* File: mips/op_iget_byte_quick.S */ -/* File: mips/op_iget_quick.S */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset@CCCC */ - GET_OPB(a2) # a2 <- B - GET_VREG(a3, a2) # a3 <- object we're operating on - FETCH(a1, 1) # a1 <- field byte offset - GET_OPA4(a2) # a2 <- A(+) - # check object for null - beqz a3, common_errNullObject # object was null - addu t0, a3, a1 - lb a0, 0(t0) # a0 <- obj.field (8/16/32 bits) - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, a2, t0) # fp[A] <- a0 - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_char_quick: /* 0xf1 */ -/* File: mips/op_iget_char_quick.S */ -/* File: mips/op_iget_quick.S */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset@CCCC */ - GET_OPB(a2) # a2 <- B - GET_VREG(a3, a2) # a3 <- object we're operating on - FETCH(a1, 1) # a1 <- field byte offset - GET_OPA4(a2) # a2 <- A(+) - # check object for null - beqz a3, common_errNullObject # object was null - addu t0, a3, a1 - lhu a0, 0(t0) # a0 <- obj.field (8/16/32 bits) - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, a2, t0) # fp[A] <- a0 - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_short_quick: /* 0xf2 */ -/* File: mips/op_iget_short_quick.S */ -/* File: mips/op_iget_quick.S */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset@CCCC */ - GET_OPB(a2) # a2 <- B - GET_VREG(a3, a2) # a3 <- object we're operating on - FETCH(a1, 1) # a1 <- field byte offset - GET_OPA4(a2) # a2 <- A(+) - # check object for null - beqz a3, common_errNullObject # object was null - addu t0, a3, a1 - lh a0, 0(t0) # a0 <- obj.field (8/16/32 bits) - FETCH_ADVANCE_INST(2) # advance rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG_GOTO(a0, a2, t0) # fp[A] <- a0 - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f3: /* 0xf3 */ -/* File: mips/op_unused_f3.S */ -/* File: mips/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f4: /* 0xf4 */ -/* File: mips/op_unused_f4.S */ -/* File: mips/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f5: /* 0xf5 */ -/* File: mips/op_unused_f5.S */ -/* File: mips/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f6: /* 0xf6 */ -/* File: mips/op_unused_f6.S */ -/* File: mips/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f7: /* 0xf7 */ -/* File: mips/op_unused_f7.S */ -/* File: mips/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f8: /* 0xf8 */ -/* File: mips/op_unused_f8.S */ -/* File: mips/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f9: /* 0xf9 */ -/* File: mips/op_unused_f9.S */ -/* File: mips/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_polymorphic: /* 0xfa */ -/* File: mips/op_invoke_polymorphic.S */ -/* File: mips/invoke_polymorphic.S */ - /* - * invoke-polymorphic handler wrapper. - */ - /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ - .extern MterpInvokePolymorphic - EXPORT_PC() - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - JAL(MterpInvokePolymorphic) - beqz v0, MterpException - FETCH_ADVANCE_INST(4) - JAL(MterpShouldSwitchInterpreters) - bnez v0, MterpFallback - GET_INST_OPCODE(t0) - GOTO_OPCODE(t0) - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_polymorphic_range: /* 0xfb */ -/* File: mips/op_invoke_polymorphic_range.S */ -/* File: mips/invoke_polymorphic.S */ - /* - * invoke-polymorphic handler wrapper. - */ - /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ - .extern MterpInvokePolymorphicRange - EXPORT_PC() - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - JAL(MterpInvokePolymorphicRange) - beqz v0, MterpException - FETCH_ADVANCE_INST(4) - JAL(MterpShouldSwitchInterpreters) - bnez v0, MterpFallback - GET_INST_OPCODE(t0) - GOTO_OPCODE(t0) - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_custom: /* 0xfc */ -/* File: mips/op_invoke_custom.S */ -/* File: mips/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeCustom - EXPORT_PC() - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - JAL(MterpInvokeCustom) - beqz v0, MterpException - FETCH_ADVANCE_INST(3) - JAL(MterpShouldSwitchInterpreters) - bnez v0, MterpFallback - GET_INST_OPCODE(t0) - GOTO_OPCODE(t0) - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_custom_range: /* 0xfd */ -/* File: mips/op_invoke_custom_range.S */ -/* File: mips/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeCustomRange - EXPORT_PC() - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - JAL(MterpInvokeCustomRange) - beqz v0, MterpException - FETCH_ADVANCE_INST(3) - JAL(MterpShouldSwitchInterpreters) - bnez v0, MterpFallback - GET_INST_OPCODE(t0) - GOTO_OPCODE(t0) - - -/* ------------------------------ */ - .balign 128 -.L_op_const_method_handle: /* 0xfe */ -/* File: mips/op_const_method_handle.S */ -/* File: mips/const.S */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstMethodHandle - EXPORT_PC() - FETCH(a0, 1) # a0 <- BBBB - GET_OPA(a1) # a1 <- AA - addu a2, rFP, OFF_FP_SHADOWFRAME # a2 <- shadow frame - move a3, rSELF - JAL(MterpConstMethodHandle) # v0 <- Mterp(index, tgt_reg, shadow_frame, self) - PREFETCH_INST(2) # load rINST - bnez v0, MterpPossibleException - ADVANCE(2) # advance rPC - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_const_method_type: /* 0xff */ -/* File: mips/op_const_method_type.S */ -/* File: mips/const.S */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstMethodType - EXPORT_PC() - FETCH(a0, 1) # a0 <- BBBB - GET_OPA(a1) # a1 <- AA - addu a2, rFP, OFF_FP_SHADOWFRAME # a2 <- shadow frame - move a3, rSELF - JAL(MterpConstMethodType) # v0 <- Mterp(index, tgt_reg, shadow_frame, self) - PREFETCH_INST(2) # load rINST - bnez v0, MterpPossibleException - ADVANCE(2) # advance rPC - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - - - .balign 128 -/* File: mips/instruction_end.S */ - - .global artMterpAsmInstructionEnd -artMterpAsmInstructionEnd: - - -/* - * =========================================================================== - * Sister implementations - * =========================================================================== - */ -/* File: mips/instruction_start_sister.S */ - - .global artMterpAsmSisterStart - .text - .balign 4 -artMterpAsmSisterStart: - - -/* continuation for op_float_to_long */ - -#ifndef MIPS32REVGE6 -.Lop_float_to_long_get_opcode: - GET_INST_OPCODE(t1) # extract opcode from rINST -.Lop_float_to_long_set_vreg: - SET_VREG64_GOTO(rRESULT0, rRESULT1, rOBJ, t1) # vA/vA+1 <- v0/v1 -#endif - -/* continuation for op_double_to_long */ - -#ifndef MIPS32REVGE6 -.Lop_double_to_long_get_opcode: - GET_INST_OPCODE(t1) # extract opcode from rINST -.Lop_double_to_long_set_vreg: - SET_VREG64_GOTO(rRESULT0, rRESULT1, rOBJ, t1) # vA/vA+1 <- v0/v1 -#endif - -/* continuation for op_mul_long */ - -.Lop_mul_long_finish: - GET_INST_OPCODE(t0) # extract opcode from rINST - SET_VREG64_GOTO(v0, v1, a0, t0) # vAA/vAA+1 <- v0(low)/v1(high) - -/* continuation for op_shl_long */ - -.Lop_shl_long_finish: - SET_VREG64_GOTO(zero, v0, t2, t0) # vAA/vAA+1 <- rlo/rhi - -/* continuation for op_shr_long */ - -.Lop_shr_long_finish: - sra a3, a1, 31 # a3<- sign(ah) - SET_VREG64_GOTO(v1, a3, t3, t0) # vAA/VAA+1 <- rlo/rhi - -/* continuation for op_ushr_long */ - -.Lop_ushr_long_finish: - SET_VREG64_GOTO(v1, zero, rOBJ, t0) # vAA/vAA+1 <- rlo/rhi - -/* continuation for op_shl_long_2addr */ - -.Lop_shl_long_2addr_finish: - SET_VREG64_GOTO(zero, v0, rOBJ, t0) # vA/vA+1 <- rlo/rhi - -/* continuation for op_shr_long_2addr */ - -.Lop_shr_long_2addr_finish: - sra a3, a1, 31 # a3<- sign(ah) - SET_VREG64_GOTO(v1, a3, t2, t0) # vA/vA+1 <- rlo/rhi - -/* continuation for op_ushr_long_2addr */ - -.Lop_ushr_long_2addr_finish: - SET_VREG64_GOTO(v1, zero, t3, t0) # vA/vA+1 <- rlo/rhi -/* File: mips/instruction_end_sister.S */ - - .global artMterpAsmSisterEnd -artMterpAsmSisterEnd: - -/* File: mips/instruction_start_alt.S */ - - .global artMterpAsmAltInstructionStart -artMterpAsmAltInstructionStart = .L_ALT_op_nop - .text - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_nop: /* 0x00 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (0 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move: /* 0x01 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (1 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_from16: /* 0x02 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (2 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_16: /* 0x03 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (3 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_wide: /* 0x04 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (4 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_wide_from16: /* 0x05 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (5 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_wide_16: /* 0x06 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (6 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_object: /* 0x07 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (7 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_object_from16: /* 0x08 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (8 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_object_16: /* 0x09 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (9 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_result: /* 0x0a */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (10 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_result_wide: /* 0x0b */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (11 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_result_object: /* 0x0c */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (12 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_exception: /* 0x0d */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (13 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_void: /* 0x0e */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (14 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return: /* 0x0f */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (15 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_wide: /* 0x10 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (16 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_object: /* 0x11 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (17 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_4: /* 0x12 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (18 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_16: /* 0x13 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (19 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const: /* 0x14 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (20 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_high16: /* 0x15 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (21 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide_16: /* 0x16 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (22 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide_32: /* 0x17 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (23 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide: /* 0x18 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (24 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide_high16: /* 0x19 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (25 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_string: /* 0x1a */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (26 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_string_jumbo: /* 0x1b */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (27 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_class: /* 0x1c */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (28 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_monitor_enter: /* 0x1d */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (29 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_monitor_exit: /* 0x1e */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (30 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_check_cast: /* 0x1f */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (31 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_instance_of: /* 0x20 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (32 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_array_length: /* 0x21 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (33 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_new_instance: /* 0x22 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (34 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_new_array: /* 0x23 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (35 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_filled_new_array: /* 0x24 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (36 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_filled_new_array_range: /* 0x25 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (37 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_fill_array_data: /* 0x26 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (38 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_throw: /* 0x27 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (39 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_goto: /* 0x28 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (40 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_goto_16: /* 0x29 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (41 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_goto_32: /* 0x2a */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (42 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_packed_switch: /* 0x2b */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (43 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sparse_switch: /* 0x2c */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (44 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpl_float: /* 0x2d */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (45 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpg_float: /* 0x2e */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (46 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpl_double: /* 0x2f */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (47 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpg_double: /* 0x30 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (48 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmp_long: /* 0x31 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (49 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_eq: /* 0x32 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (50 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_ne: /* 0x33 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (51 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_lt: /* 0x34 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (52 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_ge: /* 0x35 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (53 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_gt: /* 0x36 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (54 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_le: /* 0x37 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (55 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_eqz: /* 0x38 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (56 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_nez: /* 0x39 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (57 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_ltz: /* 0x3a */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (58 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_gez: /* 0x3b */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (59 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_gtz: /* 0x3c */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (60 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_lez: /* 0x3d */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (61 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_3e: /* 0x3e */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (62 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_3f: /* 0x3f */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (63 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_40: /* 0x40 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (64 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_41: /* 0x41 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (65 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_42: /* 0x42 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (66 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_43: /* 0x43 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (67 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget: /* 0x44 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (68 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_wide: /* 0x45 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (69 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_object: /* 0x46 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (70 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_boolean: /* 0x47 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (71 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_byte: /* 0x48 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (72 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_char: /* 0x49 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (73 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_short: /* 0x4a */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (74 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput: /* 0x4b */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (75 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_wide: /* 0x4c */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (76 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_object: /* 0x4d */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (77 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_boolean: /* 0x4e */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (78 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_byte: /* 0x4f */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (79 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_char: /* 0x50 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (80 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_short: /* 0x51 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (81 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget: /* 0x52 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (82 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_wide: /* 0x53 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (83 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_object: /* 0x54 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (84 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_boolean: /* 0x55 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (85 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_byte: /* 0x56 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (86 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_char: /* 0x57 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (87 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_short: /* 0x58 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (88 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput: /* 0x59 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (89 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_wide: /* 0x5a */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (90 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_object: /* 0x5b */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (91 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_boolean: /* 0x5c */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (92 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_byte: /* 0x5d */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (93 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_char: /* 0x5e */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (94 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_short: /* 0x5f */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (95 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget: /* 0x60 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (96 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_wide: /* 0x61 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (97 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_object: /* 0x62 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (98 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_boolean: /* 0x63 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (99 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_byte: /* 0x64 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (100 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_char: /* 0x65 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (101 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_short: /* 0x66 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (102 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput: /* 0x67 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (103 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_wide: /* 0x68 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (104 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_object: /* 0x69 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (105 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_boolean: /* 0x6a */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (106 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_byte: /* 0x6b */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (107 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_char: /* 0x6c */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (108 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_short: /* 0x6d */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (109 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual: /* 0x6e */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (110 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_super: /* 0x6f */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (111 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_direct: /* 0x70 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (112 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_static: /* 0x71 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (113 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_interface: /* 0x72 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (114 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_void_no_barrier: /* 0x73 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (115 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual_range: /* 0x74 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (116 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_super_range: /* 0x75 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (117 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_direct_range: /* 0x76 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (118 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_static_range: /* 0x77 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (119 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_interface_range: /* 0x78 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (120 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_79: /* 0x79 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (121 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_7a: /* 0x7a */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (122 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_int: /* 0x7b */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (123 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_not_int: /* 0x7c */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (124 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_long: /* 0x7d */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (125 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_not_long: /* 0x7e */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (126 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_float: /* 0x7f */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (127 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_double: /* 0x80 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (128 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_long: /* 0x81 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (129 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_float: /* 0x82 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (130 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_double: /* 0x83 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (131 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_long_to_int: /* 0x84 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (132 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_long_to_float: /* 0x85 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (133 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_long_to_double: /* 0x86 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (134 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_float_to_int: /* 0x87 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (135 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_float_to_long: /* 0x88 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (136 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_float_to_double: /* 0x89 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (137 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_double_to_int: /* 0x8a */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (138 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_double_to_long: /* 0x8b */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (139 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_double_to_float: /* 0x8c */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (140 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_byte: /* 0x8d */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (141 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_char: /* 0x8e */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (142 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_short: /* 0x8f */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (143 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int: /* 0x90 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (144 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_int: /* 0x91 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (145 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int: /* 0x92 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (146 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int: /* 0x93 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (147 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int: /* 0x94 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (148 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int: /* 0x95 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (149 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int: /* 0x96 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (150 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int: /* 0x97 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (151 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_int: /* 0x98 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (152 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_int: /* 0x99 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (153 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_int: /* 0x9a */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (154 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_long: /* 0x9b */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (155 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_long: /* 0x9c */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (156 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_long: /* 0x9d */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (157 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_long: /* 0x9e */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (158 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_long: /* 0x9f */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (159 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_long: /* 0xa0 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (160 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_long: /* 0xa1 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (161 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_long: /* 0xa2 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (162 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_long: /* 0xa3 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (163 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_long: /* 0xa4 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (164 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_long: /* 0xa5 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (165 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_float: /* 0xa6 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (166 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_float: /* 0xa7 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (167 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_float: /* 0xa8 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (168 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_float: /* 0xa9 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (169 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_float: /* 0xaa */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (170 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_double: /* 0xab */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (171 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_double: /* 0xac */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (172 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_double: /* 0xad */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (173 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_double: /* 0xae */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (174 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_double: /* 0xaf */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (175 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int_2addr: /* 0xb0 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (176 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_int_2addr: /* 0xb1 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (177 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int_2addr: /* 0xb2 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (178 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int_2addr: /* 0xb3 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (179 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int_2addr: /* 0xb4 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (180 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int_2addr: /* 0xb5 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (181 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int_2addr: /* 0xb6 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (182 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int_2addr: /* 0xb7 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (183 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_int_2addr: /* 0xb8 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (184 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_int_2addr: /* 0xb9 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (185 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_int_2addr: /* 0xba */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (186 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_long_2addr: /* 0xbb */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (187 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_long_2addr: /* 0xbc */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (188 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_long_2addr: /* 0xbd */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (189 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_long_2addr: /* 0xbe */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (190 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_long_2addr: /* 0xbf */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (191 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_long_2addr: /* 0xc0 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (192 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_long_2addr: /* 0xc1 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (193 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_long_2addr: /* 0xc2 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (194 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_long_2addr: /* 0xc3 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (195 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_long_2addr: /* 0xc4 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (196 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_long_2addr: /* 0xc5 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (197 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_float_2addr: /* 0xc6 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (198 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_float_2addr: /* 0xc7 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (199 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_float_2addr: /* 0xc8 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (200 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_float_2addr: /* 0xc9 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (201 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_float_2addr: /* 0xca */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (202 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_double_2addr: /* 0xcb */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (203 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_double_2addr: /* 0xcc */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (204 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_double_2addr: /* 0xcd */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (205 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_double_2addr: /* 0xce */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (206 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_double_2addr: /* 0xcf */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (207 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int_lit16: /* 0xd0 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (208 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rsub_int: /* 0xd1 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (209 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int_lit16: /* 0xd2 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (210 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int_lit16: /* 0xd3 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (211 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int_lit16: /* 0xd4 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (212 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int_lit16: /* 0xd5 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (213 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int_lit16: /* 0xd6 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (214 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int_lit16: /* 0xd7 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (215 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int_lit8: /* 0xd8 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (216 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rsub_int_lit8: /* 0xd9 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (217 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int_lit8: /* 0xda */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (218 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int_lit8: /* 0xdb */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (219 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int_lit8: /* 0xdc */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (220 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int_lit8: /* 0xdd */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (221 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int_lit8: /* 0xde */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (222 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int_lit8: /* 0xdf */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (223 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_int_lit8: /* 0xe0 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (224 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_int_lit8: /* 0xe1 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (225 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_int_lit8: /* 0xe2 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (226 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_quick: /* 0xe3 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (227 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_wide_quick: /* 0xe4 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (228 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_object_quick: /* 0xe5 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (229 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_quick: /* 0xe6 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (230 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_wide_quick: /* 0xe7 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (231 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_object_quick: /* 0xe8 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (232 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual_quick: /* 0xe9 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (233 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual_range_quick: /* 0xea */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (234 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_boolean_quick: /* 0xeb */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (235 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_byte_quick: /* 0xec */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (236 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_char_quick: /* 0xed */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (237 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_short_quick: /* 0xee */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (238 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_boolean_quick: /* 0xef */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (239 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_byte_quick: /* 0xf0 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (240 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_char_quick: /* 0xf1 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (241 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_short_quick: /* 0xf2 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (242 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f3: /* 0xf3 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (243 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f4: /* 0xf4 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (244 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f5: /* 0xf5 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (245 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f6: /* 0xf6 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (246 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f7: /* 0xf7 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (247 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f8: /* 0xf8 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (248 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f9: /* 0xf9 */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (249 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_polymorphic: /* 0xfa */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (250 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_polymorphic_range: /* 0xfb */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (251 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_custom: /* 0xfc */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (252 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_custom_range: /* 0xfd */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (253 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_method_handle: /* 0xfe */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (254 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_method_type: /* 0xff */ -/* File: mips/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - la ra, artMterpAsmInstructionStart + (255 * 128) # Addr of primary handler - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE - move a0, rSELF # arg0 - addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 - move a2, rPC - la t9, MterpCheckBefore - jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) - - .balign 128 -/* File: mips/instruction_end_alt.S */ - - .global artMterpAsmAltInstructionEnd -artMterpAsmAltInstructionEnd: - -/* File: mips/footer.S */ -/* - * =========================================================================== - * Common subroutines and data - * =========================================================================== - */ - - .text - .align 2 - -/* - * We've detected a condition that will result in an exception, but the exception - * has not yet been thrown. Just bail out to the reference interpreter to deal with it. - * TUNING: for consistency, we may want to just go ahead and handle these here. - */ -common_errDivideByZero: - EXPORT_PC() -#if MTERP_LOGGING - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - JAL(MterpLogDivideByZeroException) -#endif - b MterpCommonFallback - -common_errArrayIndex: - EXPORT_PC() -#if MTERP_LOGGING - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - JAL(MterpLogArrayIndexException) -#endif - b MterpCommonFallback - -common_errNegativeArraySize: - EXPORT_PC() -#if MTERP_LOGGING - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - JAL(MterpLogNegativeArraySizeException) -#endif - b MterpCommonFallback - -common_errNoSuchMethod: - EXPORT_PC() -#if MTERP_LOGGING - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - JAL(MterpLogNoSuchMethodException) -#endif - b MterpCommonFallback - -common_errNullObject: - EXPORT_PC() -#if MTERP_LOGGING - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - JAL(MterpLogNullObjectException) -#endif - b MterpCommonFallback - -common_exceptionThrown: - EXPORT_PC() -#if MTERP_LOGGING - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - JAL(MterpLogExceptionThrownException) -#endif - b MterpCommonFallback - -MterpSuspendFallback: - EXPORT_PC() -#if MTERP_LOGGING - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - lw a2, THREAD_FLAGS_OFFSET(rSELF) - JAL(MterpLogSuspendFallback) -#endif - b MterpCommonFallback - -/* - * If we're here, something is out of the ordinary. If there is a pending - * exception, handle it. Otherwise, roll back and retry with the reference - * interpreter. - */ -MterpPossibleException: - lw a0, THREAD_EXCEPTION_OFFSET(rSELF) - beqz a0, MterpFallback # If exception, fall back to reference interpreter. - /* intentional fallthrough - handle pending exception. */ -/* - * On return from a runtime helper routine, we've found a pending exception. - * Can we handle it here - or need to bail out to caller? - * - */ -MterpException: - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - JAL(MterpHandleException) # (self, shadow_frame) - beqz v0, MterpExceptionReturn # no local catch, back to caller. - lw a0, OFF_FP_DEX_INSTRUCTIONS(rFP) - lw a1, OFF_FP_DEX_PC(rFP) - lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) - EAS1(rPC, a0, a1) # generate new dex_pc_ptr - /* Do we need to switch interpreters? */ - JAL(MterpShouldSwitchInterpreters) - bnez v0, MterpFallback - /* resume execution at catch block */ - EXPORT_PC() - FETCH_INST() - GET_INST_OPCODE(t0) - GOTO_OPCODE(t0) - /* NOTE: no fallthrough */ - -/* - * Common handling for branches with support for Jit profiling. - * On entry: - * rINST <= signed offset - * rPROFILE <= signed hotness countdown (expanded to 32 bits) - * - * We have quite a few different cases for branch profiling, OSR detection and - * suspend check support here. - * - * Taken backward branches: - * If profiling active, do hotness countdown and report if we hit zero. - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * Is there a pending suspend request? If so, suspend. - * - * Taken forward branches and not-taken backward branches: - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * - * Our most common case is expected to be a taken backward branch with active jit profiling, - * but no full OSR check and no pending suspend request. - * Next most common case is not-taken branch with no full OSR check. - */ -MterpCommonTakenBranchNoFlags: - bgtz rINST, .L_forward_branch # don't add forward branches to hotness -/* - * We need to subtract 1 from positive values and we should not see 0 here, - * so we may use the result of the comparison with -1. - */ -#if JIT_CHECK_OSR != -1 -# error "JIT_CHECK_OSR must be -1." -#endif - li t0, JIT_CHECK_OSR - beq rPROFILE, t0, .L_osr_check - blt rPROFILE, t0, .L_resume_backward_branch - subu rPROFILE, 1 - beqz rPROFILE, .L_add_batch # counted down to zero - report -.L_resume_backward_branch: - lw ra, THREAD_FLAGS_OFFSET(rSELF) - REFRESH_IBASE() - addu a2, rINST, rINST # a2<- byte offset - FETCH_ADVANCE_INST_RB(a2) # update rPC, load rINST - and ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - bnez ra, .L_suspend_request_pending - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - -.L_suspend_request_pending: - EXPORT_PC() - move a0, rSELF - JAL(MterpSuspendCheck) # (self) - bnez v0, MterpFallback - REFRESH_IBASE() # might have changed during suspend - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - -.L_no_count_backwards: - li t0, JIT_CHECK_OSR # check for possible OSR re-entry - bne rPROFILE, t0, .L_resume_backward_branch -.L_osr_check: - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rINST - EXPORT_PC() - JAL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) - bnez v0, MterpOnStackReplacement - b .L_resume_backward_branch - -.L_forward_branch: - li t0, JIT_CHECK_OSR # check for possible OSR re-entry - beq rPROFILE, t0, .L_check_osr_forward -.L_resume_forward_branch: - add a2, rINST, rINST # a2<- byte offset - FETCH_ADVANCE_INST_RB(a2) # update rPC, load rINST - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - -.L_check_osr_forward: - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rINST - EXPORT_PC() - JAL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) - bnez v0, MterpOnStackReplacement - b .L_resume_forward_branch - -.L_add_batch: - addu a1, rFP, OFF_FP_SHADOWFRAME - sh rPROFILE, SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET(a1) - lw a0, OFF_FP_METHOD(rFP) - move a2, rSELF - JAL(MterpAddHotnessBatch) # (method, shadow_frame, self) - move rPROFILE, v0 # restore new hotness countdown to rPROFILE - b .L_no_count_backwards - -/* - * Entered from the conditional branch handlers when OSR check request active on - * not-taken path. All Dalvik not-taken conditional branch offsets are 2. - */ -.L_check_not_taken_osr: - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - li a2, 2 - EXPORT_PC() - JAL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) - bnez v0, MterpOnStackReplacement - FETCH_ADVANCE_INST(2) - GET_INST_OPCODE(t0) # extract opcode from rINST - GOTO_OPCODE(t0) # jump to next instruction - -/* - * On-stack replacement has happened, and now we've returned from the compiled method. - */ -MterpOnStackReplacement: -#if MTERP_LOGGING - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rINST - JAL(MterpLogOSR) -#endif - li v0, 1 # Signal normal return - b MterpDone - -/* - * Bail out to reference interpreter. - */ -MterpFallback: - EXPORT_PC() -#if MTERP_LOGGING - move a0, rSELF - addu a1, rFP, OFF_FP_SHADOWFRAME - JAL(MterpLogFallback) -#endif -MterpCommonFallback: - move v0, zero # signal retry with reference interpreter. - b MterpDone -/* - * We pushed some registers on the stack in ExecuteMterpImpl, then saved - * SP and LR. Here we restore SP, restore the registers, and then restore - * LR to PC. - * - * On entry: - * uint32_t* rFP (should still be live, pointer to base of vregs) - */ -MterpExceptionReturn: - li v0, 1 # signal return to caller. - b MterpDone -MterpReturn: - lw a2, OFF_FP_RESULT_REGISTER(rFP) - sw v0, 0(a2) - sw v1, 4(a2) - li v0, 1 # signal return to caller. -MterpDone: -/* - * At this point, we expect rPROFILE to be non-zero. If negative, hotness is disabled or we're - * checking for OSR. If greater than zero, we might have unreported hotness to register - * (the difference between the ending rPROFILE and the cached hotness counter). rPROFILE - * should only reach zero immediately after a hotness decrement, and is then reset to either - * a negative special state or the new non-zero countdown value. - */ - blez rPROFILE, .L_pop_and_return # if > 0, we may have some counts to report. - -MterpProfileActive: - move rINST, v0 # stash return value - /* Report cached hotness counts */ - lw a0, OFF_FP_METHOD(rFP) - addu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rSELF - sh rPROFILE, SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET(a1) - JAL(MterpAddHotnessBatch) # (method, shadow_frame, self) - move v0, rINST # restore return value - -.L_pop_and_return: -/* Restore from the stack and return. Frame size = STACK_SIZE */ - STACK_LOAD_FULL() - jalr zero, ra - - .cfi_endproc - .end ExecuteMterpImpl - diff --git a/runtime/interpreter/mterp/out/mterp_mips64.S b/runtime/interpreter/mterp/out/mterp_mips64.S deleted file mode 100644 index 40a8396f776b01e92d3bb3b88790e926c863f9d7..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/out/mterp_mips64.S +++ /dev/null @@ -1,11986 +0,0 @@ -/* - * This file was generated automatically by gen-mterp.py for 'mips64'. - * - * --> DO NOT EDIT <-- - */ - -/* File: mips64/header.S */ -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#define zero $0 /* always zero */ -#define AT $at /* assembler temp */ -#define v0 $2 /* return value */ -#define v1 $3 -#define a0 $4 /* argument registers */ -#define a1 $5 -#define a2 $6 -#define a3 $7 -#define a4 $8 /* expanded register arguments */ -#define a5 $9 -#define a6 $10 -#define a7 $11 -#define ta0 $8 /* alias */ -#define ta1 $9 -#define ta2 $10 -#define ta3 $11 -#define t0 $12 /* temp registers (not saved across subroutine calls) */ -#define t1 $13 -#define t2 $14 -#define t3 $15 - -#define s0 $16 /* saved across subroutine calls (callee saved) */ -#define s1 $17 -#define s2 $18 -#define s3 $19 -#define s4 $20 -#define s5 $21 -#define s6 $22 -#define s7 $23 -#define t8 $24 /* two more temp registers */ -#define t9 $25 -#define k0 $26 /* kernel temporary */ -#define k1 $27 -#define gp $28 /* global pointer */ -#define sp $29 /* stack pointer */ -#define s8 $30 /* one more callee saved */ -#define ra $31 /* return address */ - -#define f0 $f0 -#define f1 $f1 -#define f2 $f2 -#define f3 $f3 -#define f12 $f12 -#define f13 $f13 - -/* - * It looks like the GNU assembler currently does not support the blec and bgtc - * idioms, which should translate into bgec and bltc respectively with swapped - * left and right register operands. - * TODO: remove these macros when the assembler is fixed. - */ -.macro blec lreg, rreg, target - bgec \rreg, \lreg, \target -.endm -.macro bgtc lreg, rreg, target - bltc \rreg, \lreg, \target -.endm - -/* -Mterp and MIPS64 notes: - -The following registers have fixed assignments: - - reg nick purpose - s0 rPC interpreted program counter, used for fetching instructions - s1 rFP interpreted frame pointer, used for accessing locals and args - s2 rSELF self (Thread) pointer - s3 rINST first 16-bit code unit of current instruction - s4 rIBASE interpreted instruction base pointer, used for computed goto - s5 rREFS base of object references in shadow frame (ideally, we'll get rid of this later). - s6 rPROFILE jit profile hotness countdown -*/ - -/* During bringup, we'll use the shadow frame model instead of rFP */ -/* single-purpose registers, given names for clarity */ -#define rPC s0 -#define CFI_DEX 16 // DWARF register number of the register holding dex-pc (s0). -#define CFI_TMP 4 // DWARF register number of the first argument register (a0). -#define rFP s1 -#define rSELF s2 -#define rINST s3 -#define rIBASE s4 -#define rREFS s5 -#define rPROFILE s6 - -/* - * This is a #include, not a %include, because we want the C pre-processor - * to expand the macros into assembler assignment statements. - */ -#include "asm_support.h" -#include "interpreter/cfi_asm_support.h" - -/* - * Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs. So, - * to access other shadow frame fields, we need to use a backwards offset. Define those here. - */ -#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) -#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) -#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) -#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) -#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) -#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) -#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) -#define OFF_FP_DEX_INSTRUCTIONS OFF_FP(SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET) -#define OFF_FP_SHADOWFRAME OFF_FP(0) - -#define MTERP_PROFILE_BRANCHES 1 -#define MTERP_LOGGING 0 - -/* - * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must - * be done *before* something throws. - * - * It's okay to do this more than once. - * - * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped - * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction - * offset into the code_items_[] array. For effiency, we will "export" the - * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC - * to convert to a dex pc when needed. - */ -.macro EXPORT_PC - sd rPC, OFF_FP_DEX_PC_PTR(rFP) -.endm - -/* - * Refresh handler table. - */ -.macro REFRESH_IBASE - ld rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) -.endm - -/* - * Fetch the next instruction from rPC into rINST. Does not advance rPC. - */ -.macro FETCH_INST - lhu rINST, 0(rPC) -.endm - -/* Advance rPC by some number of code units. */ -.macro ADVANCE count - daddu rPC, rPC, (\count) * 2 -.endm - -/* - * Fetch the next instruction from an offset specified by _reg and advance xPC. - * xPC to point to the next instruction. "_reg" must specify the distance - * in bytes, *not* 16-bit code units, and may be a signed value. Must not set flags. - * - */ -.macro FETCH_ADVANCE_INST_RB reg - daddu rPC, rPC, \reg - FETCH_INST -.endm - -/* - * Fetch the next instruction from the specified offset. Advances rPC - * to point to the next instruction. - * - * This must come AFTER anything that can throw an exception, or the - * exception catch may miss. (This also implies that it must come after - * EXPORT_PC.) - */ -.macro FETCH_ADVANCE_INST count - ADVANCE \count - FETCH_INST -.endm - -/* - * Similar to FETCH_ADVANCE_INST, but does not update rPC. Used to load - * rINST ahead of possible exception point. Be sure to manually advance rPC - * later. - */ -.macro PREFETCH_INST count - lhu rINST, ((\count) * 2)(rPC) -.endm - -/* - * Put the instruction's opcode field into the specified register. - */ -.macro GET_INST_OPCODE reg - and \reg, rINST, 255 -.endm - -/* - * Begin executing the opcode in _reg. - */ -.macro GOTO_OPCODE reg - .set noat - sll AT, \reg, 7 - daddu AT, rIBASE, AT - jic AT, 0 - .set at -.endm - -/* - * Get/set the 32-bit value from a Dalvik register. - * Note, GET_VREG does sign extension to 64 bits while - * GET_VREG_U does zero extension to 64 bits. - * One is useful for arithmetic while the other is - * useful for storing the result value as 64-bit. - */ -.macro GET_VREG reg, vreg - .set noat - dlsa AT, \vreg, rFP, 2 - lw \reg, 0(AT) - .set at -.endm -.macro GET_VREG_U reg, vreg - .set noat - dlsa AT, \vreg, rFP, 2 - lwu \reg, 0(AT) - .set at -.endm -.macro GET_VREG_FLOAT reg, vreg - .set noat - dlsa AT, \vreg, rFP, 2 - lwc1 \reg, 0(AT) - .set at -.endm -.macro SET_VREG reg, vreg - .set noat - dlsa AT, \vreg, rFP, 2 - sw \reg, 0(AT) - dlsa AT, \vreg, rREFS, 2 - sw zero, 0(AT) - .set at -.endm -.macro SET_VREG_OBJECT reg, vreg - .set noat - dlsa AT, \vreg, rFP, 2 - sw \reg, 0(AT) - dlsa AT, \vreg, rREFS, 2 - sw \reg, 0(AT) - .set at -.endm -.macro SET_VREG_FLOAT reg, vreg - .set noat - dlsa AT, \vreg, rFP, 2 - swc1 \reg, 0(AT) - dlsa AT, \vreg, rREFS, 2 - sw zero, 0(AT) - .set at -.endm - -/* - * Get/set the 64-bit value from a Dalvik register. - * Avoid unaligned memory accesses. - * Note, SET_VREG_WIDE clobbers the register containing the value being stored. - * Note, SET_VREG_DOUBLE clobbers the register containing the Dalvik register number. - */ -.macro GET_VREG_WIDE reg, vreg - .set noat - dlsa AT, \vreg, rFP, 2 - lw \reg, 0(AT) - lw AT, 4(AT) - dinsu \reg, AT, 32, 32 - .set at -.endm -.macro GET_VREG_DOUBLE reg, vreg - .set noat - dlsa AT, \vreg, rFP, 2 - lwc1 \reg, 0(AT) - lw AT, 4(AT) - mthc1 AT, \reg - .set at -.endm -.macro SET_VREG_WIDE reg, vreg - .set noat - dlsa AT, \vreg, rFP, 2 - sw \reg, 0(AT) - drotr32 \reg, \reg, 0 - sw \reg, 4(AT) - dlsa AT, \vreg, rREFS, 2 - sw zero, 0(AT) - sw zero, 4(AT) - .set at -.endm -.macro SET_VREG_DOUBLE reg, vreg - .set noat - dlsa AT, \vreg, rREFS, 2 - sw zero, 0(AT) - sw zero, 4(AT) - dlsa AT, \vreg, rFP, 2 - swc1 \reg, 0(AT) - mfhc1 \vreg, \reg - sw \vreg, 4(AT) - .set at -.endm - -/* - * On-stack offsets for spilling/unspilling callee-saved registers - * and the frame size. - */ -#define STACK_OFFSET_RA 0 -#define STACK_OFFSET_GP 8 -#define STACK_OFFSET_S0 16 -#define STACK_OFFSET_S1 24 -#define STACK_OFFSET_S2 32 -#define STACK_OFFSET_S3 40 -#define STACK_OFFSET_S4 48 -#define STACK_OFFSET_S5 56 -#define STACK_OFFSET_S6 64 -#define STACK_SIZE 80 /* needs 16 byte alignment */ - -/* Constants for float/double_to_int/long conversions */ -#define INT_MIN 0x80000000 -#define INT_MIN_AS_FLOAT 0xCF000000 -#define INT_MIN_AS_DOUBLE 0xC1E0000000000000 -#define LONG_MIN 0x8000000000000000 -#define LONG_MIN_AS_FLOAT 0xDF000000 -#define LONG_MIN_AS_DOUBLE 0xC3E0000000000000 - -/* File: mips64/entry.S */ -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * Interpreter entry point. - */ - - .set reorder - - .text - .global ExecuteMterpImpl - .type ExecuteMterpImpl, %function - .balign 16 -/* - * On entry: - * a0 Thread* self - * a1 dex_instructions - * a2 ShadowFrame - * a3 JValue* result_register - * - */ -ExecuteMterpImpl: - .cfi_startproc - .cpsetup t9, t8, ExecuteMterpImpl - - .cfi_def_cfa sp, 0 - daddu sp, sp, -STACK_SIZE - .cfi_adjust_cfa_offset STACK_SIZE - - sd t8, STACK_OFFSET_GP(sp) - .cfi_rel_offset 28, STACK_OFFSET_GP - sd ra, STACK_OFFSET_RA(sp) - .cfi_rel_offset 31, STACK_OFFSET_RA - - sd s0, STACK_OFFSET_S0(sp) - .cfi_rel_offset 16, STACK_OFFSET_S0 - sd s1, STACK_OFFSET_S1(sp) - .cfi_rel_offset 17, STACK_OFFSET_S1 - sd s2, STACK_OFFSET_S2(sp) - .cfi_rel_offset 18, STACK_OFFSET_S2 - sd s3, STACK_OFFSET_S3(sp) - .cfi_rel_offset 19, STACK_OFFSET_S3 - sd s4, STACK_OFFSET_S4(sp) - .cfi_rel_offset 20, STACK_OFFSET_S4 - sd s5, STACK_OFFSET_S5(sp) - .cfi_rel_offset 21, STACK_OFFSET_S5 - sd s6, STACK_OFFSET_S6(sp) - .cfi_rel_offset 22, STACK_OFFSET_S6 - - /* Remember the return register */ - sd a3, SHADOWFRAME_RESULT_REGISTER_OFFSET(a2) - - /* Remember the dex instruction pointer */ - sd a1, SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET(a2) - - /* set up "named" registers */ - move rSELF, a0 - daddu rFP, a2, SHADOWFRAME_VREGS_OFFSET - lw v0, SHADOWFRAME_NUMBER_OF_VREGS_OFFSET(a2) - dlsa rREFS, v0, rFP, 2 - lw v0, SHADOWFRAME_DEX_PC_OFFSET(a2) - dlsa rPC, v0, a1, 1 - CFI_DEFINE_DEX_PC_WITH_OFFSET(CFI_TMP, CFI_DEX, 0) - EXPORT_PC - - /* Starting ibase */ - REFRESH_IBASE - - /* Set up for backwards branches & osr profiling */ - ld a0, OFF_FP_METHOD(rFP) - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rSELF - jal MterpSetUpHotnessCountdown - move rPROFILE, v0 # Starting hotness countdown to rPROFILE - - /* start executing the instruction at rPC */ - FETCH_INST - GET_INST_OPCODE v0 - GOTO_OPCODE v0 - - /* NOTE: no fallthrough */ - -/* File: mips64/instruction_start.S */ - - .global artMterpAsmInstructionStart -artMterpAsmInstructionStart = .L_op_nop - .text - -/* ------------------------------ */ - .balign 128 -.L_op_nop: /* 0x00 */ -/* File: mips64/op_nop.S */ - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move: /* 0x01 */ -/* File: mips64/op_move.S */ - /* for move, move-object, long-to-int */ - /* op vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_VREG a0, a3 # a0 <- vB - GET_INST_OPCODE v0 # extract opcode from rINST - .if 0 - SET_VREG_OBJECT a0, a2 # vA <- vB - .else - SET_VREG a0, a2 # vA <- vB - .endif - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_from16: /* 0x02 */ -/* File: mips64/op_move_from16.S */ - /* for: move/from16, move-object/from16 */ - /* op vAA, vBBBB */ - lhu a3, 2(rPC) # a3 <- BBBB - srl a2, rINST, 8 # a2 <- AA - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_VREG a0, a3 # a0 <- vBBBB - GET_INST_OPCODE v0 # extract opcode from rINST - .if 0 - SET_VREG_OBJECT a0, a2 # vAA <- vBBBB - .else - SET_VREG a0, a2 # vAA <- vBBBB - .endif - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_16: /* 0x03 */ -/* File: mips64/op_move_16.S */ - /* for: move/16, move-object/16 */ - /* op vAAAA, vBBBB */ - lhu a3, 4(rPC) # a3 <- BBBB - lhu a2, 2(rPC) # a2 <- AAAA - FETCH_ADVANCE_INST 3 # advance rPC, load rINST - GET_VREG a0, a3 # a0 <- vBBBB - GET_INST_OPCODE v0 # extract opcode from rINST - .if 0 - SET_VREG_OBJECT a0, a2 # vAAAA <- vBBBB - .else - SET_VREG a0, a2 # vAAAA <- vBBBB - .endif - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_wide: /* 0x04 */ -/* File: mips64/op_move_wide.S */ - /* move-wide vA, vB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - ext a3, rINST, 12, 4 # a3 <- B - ext a2, rINST, 8, 4 # a2 <- A - GET_VREG_WIDE a0, a3 # a0 <- vB - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vA <- vB - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_wide_from16: /* 0x05 */ -/* File: mips64/op_move_wide_from16.S */ - /* move-wide/from16 vAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - lhu a3, 2(rPC) # a3 <- BBBB - srl a2, rINST, 8 # a2 <- AA - GET_VREG_WIDE a0, a3 # a0 <- vBBBB - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vAA <- vBBBB - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_wide_16: /* 0x06 */ -/* File: mips64/op_move_wide_16.S */ - /* move-wide/16 vAAAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - lhu a3, 4(rPC) # a3 <- BBBB - lhu a2, 2(rPC) # a2 <- AAAA - GET_VREG_WIDE a0, a3 # a0 <- vBBBB - FETCH_ADVANCE_INST 3 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vAAAA <- vBBBB - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_object: /* 0x07 */ -/* File: mips64/op_move_object.S */ -/* File: mips64/op_move.S */ - /* for move, move-object, long-to-int */ - /* op vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_VREG a0, a3 # a0 <- vB - GET_INST_OPCODE v0 # extract opcode from rINST - .if 1 - SET_VREG_OBJECT a0, a2 # vA <- vB - .else - SET_VREG a0, a2 # vA <- vB - .endif - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_move_object_from16: /* 0x08 */ -/* File: mips64/op_move_object_from16.S */ -/* File: mips64/op_move_from16.S */ - /* for: move/from16, move-object/from16 */ - /* op vAA, vBBBB */ - lhu a3, 2(rPC) # a3 <- BBBB - srl a2, rINST, 8 # a2 <- AA - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_VREG a0, a3 # a0 <- vBBBB - GET_INST_OPCODE v0 # extract opcode from rINST - .if 1 - SET_VREG_OBJECT a0, a2 # vAA <- vBBBB - .else - SET_VREG a0, a2 # vAA <- vBBBB - .endif - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_move_object_16: /* 0x09 */ -/* File: mips64/op_move_object_16.S */ -/* File: mips64/op_move_16.S */ - /* for: move/16, move-object/16 */ - /* op vAAAA, vBBBB */ - lhu a3, 4(rPC) # a3 <- BBBB - lhu a2, 2(rPC) # a2 <- AAAA - FETCH_ADVANCE_INST 3 # advance rPC, load rINST - GET_VREG a0, a3 # a0 <- vBBBB - GET_INST_OPCODE v0 # extract opcode from rINST - .if 1 - SET_VREG_OBJECT a0, a2 # vAAAA <- vBBBB - .else - SET_VREG a0, a2 # vAAAA <- vBBBB - .endif - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_move_result: /* 0x0a */ -/* File: mips64/op_move_result.S */ - /* for: move-result, move-result-object */ - /* op vAA */ - srl a2, rINST, 8 # a2 <- AA - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - ld a0, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType - lw a0, 0(a0) # a0 <- result.i - GET_INST_OPCODE v0 # extract opcode from rINST - .if 0 - SET_VREG_OBJECT a0, a2 # vAA <- result - .else - SET_VREG a0, a2 # vAA <- result - .endif - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_result_wide: /* 0x0b */ -/* File: mips64/op_move_result_wide.S */ - /* for: move-result-wide */ - /* op vAA */ - srl a2, rINST, 8 # a2 <- AA - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - ld a0, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType - ld a0, 0(a0) # a0 <- result.j - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vAA <- result - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_move_result_object: /* 0x0c */ -/* File: mips64/op_move_result_object.S */ -/* File: mips64/op_move_result.S */ - /* for: move-result, move-result-object */ - /* op vAA */ - srl a2, rINST, 8 # a2 <- AA - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - ld a0, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType - lw a0, 0(a0) # a0 <- result.i - GET_INST_OPCODE v0 # extract opcode from rINST - .if 1 - SET_VREG_OBJECT a0, a2 # vAA <- result - .else - SET_VREG a0, a2 # vAA <- result - .endif - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_move_exception: /* 0x0d */ -/* File: mips64/op_move_exception.S */ - /* move-exception vAA */ - srl a2, rINST, 8 # a2 <- AA - ld a0, THREAD_EXCEPTION_OFFSET(rSELF) # load exception obj - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - SET_VREG_OBJECT a0, a2 # vAA <- exception obj - GET_INST_OPCODE v0 # extract opcode from rINST - sd zero, THREAD_EXCEPTION_OFFSET(rSELF) # clear exception - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_return_void: /* 0x0e */ -/* File: mips64/op_return_void.S */ - .extern MterpThreadFenceForConstructor - .extern MterpSuspendCheck - jal MterpThreadFenceForConstructor - lw ra, THREAD_FLAGS_OFFSET(rSELF) - move a0, rSELF - and ra, ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - beqzc ra, 1f - jal MterpSuspendCheck # (self) -1: - li a0, 0 - b MterpReturn - -/* ------------------------------ */ - .balign 128 -.L_op_return: /* 0x0f */ -/* File: mips64/op_return.S */ - /* - * Return a 32-bit value. - * - * for: return (sign-extend), return-object (zero-extend) - */ - /* op vAA */ - .extern MterpThreadFenceForConstructor - .extern MterpSuspendCheck - jal MterpThreadFenceForConstructor - lw ra, THREAD_FLAGS_OFFSET(rSELF) - move a0, rSELF - and ra, ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - beqzc ra, 1f - jal MterpSuspendCheck # (self) -1: - srl a2, rINST, 8 # a2 <- AA - GET_VREG a0, a2 # a0 <- vAA - b MterpReturn - -/* ------------------------------ */ - .balign 128 -.L_op_return_wide: /* 0x10 */ -/* File: mips64/op_return_wide.S */ - /* - * Return a 64-bit value. - */ - /* return-wide vAA */ - /* op vAA */ - .extern MterpThreadFenceForConstructor - .extern MterpSuspendCheck - jal MterpThreadFenceForConstructor - lw ra, THREAD_FLAGS_OFFSET(rSELF) - move a0, rSELF - and ra, ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - beqzc ra, 1f - jal MterpSuspendCheck # (self) -1: - srl a2, rINST, 8 # a2 <- AA - GET_VREG_WIDE a0, a2 # a0 <- vAA - b MterpReturn - -/* ------------------------------ */ - .balign 128 -.L_op_return_object: /* 0x11 */ -/* File: mips64/op_return_object.S */ -/* File: mips64/op_return.S */ - /* - * Return a 32-bit value. - * - * for: return (sign-extend), return-object (zero-extend) - */ - /* op vAA */ - .extern MterpThreadFenceForConstructor - .extern MterpSuspendCheck - jal MterpThreadFenceForConstructor - lw ra, THREAD_FLAGS_OFFSET(rSELF) - move a0, rSELF - and ra, ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - beqzc ra, 1f - jal MterpSuspendCheck # (self) -1: - srl a2, rINST, 8 # a2 <- AA - GET_VREG_U a0, a2 # a0 <- vAA - b MterpReturn - - -/* ------------------------------ */ - .balign 128 -.L_op_const_4: /* 0x12 */ -/* File: mips64/op_const_4.S */ - /* const/4 vA, #+B */ - ext a2, rINST, 8, 4 # a2 <- A - seh a0, rINST # sign extend B in rINST - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - sra a0, a0, 12 # shift B into its final position - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- +B - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_16: /* 0x13 */ -/* File: mips64/op_const_16.S */ - /* const/16 vAA, #+BBBB */ - srl a2, rINST, 8 # a2 <- AA - lh a0, 2(rPC) # a0 <- sign-extended BBBB - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vAA <- +BBBB - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const: /* 0x14 */ -/* File: mips64/op_const.S */ - /* const vAA, #+BBBBbbbb */ - srl a2, rINST, 8 # a2 <- AA - lh a0, 2(rPC) # a0 <- bbbb (low) - lh a1, 4(rPC) # a1 <- BBBB (high) - FETCH_ADVANCE_INST 3 # advance rPC, load rINST - ins a0, a1, 16, 16 # a0 = BBBBbbbb - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vAA <- +BBBBbbbb - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_high16: /* 0x15 */ -/* File: mips64/op_const_high16.S */ - /* const/high16 vAA, #+BBBB0000 */ - srl a2, rINST, 8 # a2 <- AA - lh a0, 2(rPC) # a0 <- BBBB - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - sll a0, a0, 16 # a0 <- BBBB0000 - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vAA <- +BBBB0000 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_wide_16: /* 0x16 */ -/* File: mips64/op_const_wide_16.S */ - /* const-wide/16 vAA, #+BBBB */ - srl a2, rINST, 8 # a2 <- AA - lh a0, 2(rPC) # a0 <- sign-extended BBBB - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vAA <- +BBBB - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_wide_32: /* 0x17 */ -/* File: mips64/op_const_wide_32.S */ - /* const-wide/32 vAA, #+BBBBbbbb */ - srl a2, rINST, 8 # a2 <- AA - lh a0, 2(rPC) # a0 <- bbbb (low) - lh a1, 4(rPC) # a1 <- BBBB (high) - FETCH_ADVANCE_INST 3 # advance rPC, load rINST - ins a0, a1, 16, 16 # a0 = BBBBbbbb - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vAA <- +BBBBbbbb - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_wide: /* 0x18 */ -/* File: mips64/op_const_wide.S */ - /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ - srl a4, rINST, 8 # a4 <- AA - lh a0, 2(rPC) # a0 <- bbbb (low) - lh a1, 4(rPC) # a1 <- BBBB (low middle) - lh a2, 6(rPC) # a2 <- hhhh (high middle) - lh a3, 8(rPC) # a3 <- HHHH (high) - FETCH_ADVANCE_INST 5 # advance rPC, load rINST - ins a0, a1, 16, 16 # a0 = BBBBbbbb - ins a2, a3, 16, 16 # a2 = HHHHhhhh - dinsu a0, a2, 32, 32 # a0 = HHHHhhhhBBBBbbbb - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a4 # vAA <- +HHHHhhhhBBBBbbbb - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_wide_high16: /* 0x19 */ -/* File: mips64/op_const_wide_high16.S */ - /* const-wide/high16 vAA, #+BBBB000000000000 */ - srl a2, rINST, 8 # a2 <- AA - lh a0, 2(rPC) # a0 <- BBBB - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - dsll32 a0, a0, 16 # a0 <- BBBB000000000000 - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vAA <- +BBBB000000000000 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_string: /* 0x1a */ -/* File: mips64/op_const_string.S */ -/* File: mips64/const.S */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstString - EXPORT_PC - lhu a0, 2(rPC) # a0 <- BBBB - srl a1, rINST, 8 # a1 <- AA - daddu a2, rFP, OFF_FP_SHADOWFRAME - move a3, rSELF - jal MterpConstString # (index, tgt_reg, shadow_frame, self) - PREFETCH_INST 2 # load rINST - bnez v0, MterpPossibleException # let reference interpreter deal with it. - ADVANCE 2 # advance rPC - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_const_string_jumbo: /* 0x1b */ -/* File: mips64/op_const_string_jumbo.S */ - /* const/string vAA, String//BBBBBBBB */ - .extern MterpConstString - EXPORT_PC - lh a0, 2(rPC) # a0 <- bbbb (low) - lh a4, 4(rPC) # a4 <- BBBB (high) - srl a1, rINST, 8 # a1 <- AA - ins a0, a4, 16, 16 # a0 <- BBBBbbbb - daddu a2, rFP, OFF_FP_SHADOWFRAME - move a3, rSELF - jal MterpConstString # (index, tgt_reg, shadow_frame, self) - PREFETCH_INST 3 # load rINST - bnez v0, MterpPossibleException # let reference interpreter deal with it. - ADVANCE 3 # advance rPC - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_const_class: /* 0x1c */ -/* File: mips64/op_const_class.S */ -/* File: mips64/const.S */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstClass - EXPORT_PC - lhu a0, 2(rPC) # a0 <- BBBB - srl a1, rINST, 8 # a1 <- AA - daddu a2, rFP, OFF_FP_SHADOWFRAME - move a3, rSELF - jal MterpConstClass # (index, tgt_reg, shadow_frame, self) - PREFETCH_INST 2 # load rINST - bnez v0, MterpPossibleException # let reference interpreter deal with it. - ADVANCE 2 # advance rPC - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_monitor_enter: /* 0x1d */ -/* File: mips64/op_monitor_enter.S */ - /* - * Synchronize on an object. - */ - /* monitor-enter vAA */ - .extern artLockObjectFromCode - EXPORT_PC - srl a2, rINST, 8 # a2 <- AA - GET_VREG_U a0, a2 # a0 <- vAA (object) - move a1, rSELF # a1 <- self - jal artLockObjectFromCode - bnezc v0, MterpException - FETCH_ADVANCE_INST 1 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_monitor_exit: /* 0x1e */ -/* File: mips64/op_monitor_exit.S */ - /* - * Unlock an object. - * - * Exceptions that occur when unlocking a monitor need to appear as - * if they happened at the following instruction. See the Dalvik - * instruction spec. - */ - /* monitor-exit vAA */ - .extern artUnlockObjectFromCode - EXPORT_PC - srl a2, rINST, 8 # a2 <- AA - GET_VREG_U a0, a2 # a0 <- vAA (object) - move a1, rSELF # a1 <- self - jal artUnlockObjectFromCode # v0 <- success for unlock(self, obj) - bnezc v0, MterpException - FETCH_ADVANCE_INST 1 # before throw: advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_check_cast: /* 0x1f */ -/* File: mips64/op_check_cast.S */ - /* - * Check to see if a cast from one class to another is allowed. - */ - /* check-cast vAA, class//BBBB */ - .extern MterpCheckCast - EXPORT_PC - lhu a0, 2(rPC) # a0 <- BBBB - srl a1, rINST, 8 # a1 <- AA - dlsa a1, a1, rFP, 2 # a1 <- &object - ld a2, OFF_FP_METHOD(rFP) # a2 <- method - move a3, rSELF # a3 <- self - jal MterpCheckCast # (index, &obj, method, self) - PREFETCH_INST 2 - bnez v0, MterpPossibleException - ADVANCE 2 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_instance_of: /* 0x20 */ -/* File: mips64/op_instance_of.S */ - /* - * Check to see if an object reference is an instance of a class. - * - * Most common situation is a non-null object, being compared against - * an already-resolved class. - */ - /* instance-of vA, vB, class//CCCC */ - .extern MterpInstanceOf - EXPORT_PC - lhu a0, 2(rPC) # a0 <- CCCC - srl a1, rINST, 12 # a1 <- B - dlsa a1, a1, rFP, 2 # a1 <- &object - ld a2, OFF_FP_METHOD(rFP) # a2 <- method - move a3, rSELF # a3 <- self - jal MterpInstanceOf # (index, &obj, method, self) - ld a1, THREAD_EXCEPTION_OFFSET(rSELF) - ext a2, rINST, 8, 4 # a2 <- A - PREFETCH_INST 2 - bnez a1, MterpException - ADVANCE 2 # advance rPC - SET_VREG v0, a2 # vA <- v0 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_array_length: /* 0x21 */ -/* File: mips64/op_array_length.S */ - /* - * Return the length of an array. - */ - srl a1, rINST, 12 # a1 <- B - GET_VREG_U a0, a1 # a0 <- vB (object ref) - ext a2, rINST, 8, 4 # a2 <- A - beqz a0, common_errNullObject # yup, fail - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- array length - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a3, a2 # vB <- length - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_new_instance: /* 0x22 */ -/* File: mips64/op_new_instance.S */ - /* - * Create a new instance of a class. - */ - /* new-instance vAA, class//BBBB */ - .extern MterpNewInstance - EXPORT_PC - daddu a0, rFP, OFF_FP_SHADOWFRAME - move a1, rSELF - move a2, rINST - jal MterpNewInstance # (shadow_frame, self, inst_data) - beqzc v0, MterpPossibleException - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_new_array: /* 0x23 */ -/* File: mips64/op_new_array.S */ - /* - * Allocate an array of objects, specified with the array class - * and a count. - * - * The verifier guarantees that this is an array class, so we don't - * check for it here. - */ - /* new-array vA, vB, class//CCCC */ - .extern MterpNewArray - EXPORT_PC - daddu a0, rFP, OFF_FP_SHADOWFRAME - move a1, rPC - move a2, rINST - move a3, rSELF - jal MterpNewArray - beqzc v0, MterpPossibleException - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_filled_new_array: /* 0x24 */ -/* File: mips64/op_filled_new_array.S */ - /* - * Create a new array with elements filled from registers. - * - * for: filled-new-array, filled-new-array/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class//CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, type//BBBB */ - .extern MterpFilledNewArray - EXPORT_PC - daddu a0, rFP, OFF_FP_SHADOWFRAME - move a1, rPC - move a2, rSELF - jal MterpFilledNewArray - beqzc v0, MterpPossibleException - FETCH_ADVANCE_INST 3 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_filled_new_array_range: /* 0x25 */ -/* File: mips64/op_filled_new_array_range.S */ -/* File: mips64/op_filled_new_array.S */ - /* - * Create a new array with elements filled from registers. - * - * for: filled-new-array, filled-new-array/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class//CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, type//BBBB */ - .extern MterpFilledNewArrayRange - EXPORT_PC - daddu a0, rFP, OFF_FP_SHADOWFRAME - move a1, rPC - move a2, rSELF - jal MterpFilledNewArrayRange - beqzc v0, MterpPossibleException - FETCH_ADVANCE_INST 3 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_fill_array_data: /* 0x26 */ -/* File: mips64/op_fill_array_data.S */ - /* fill-array-data vAA, +BBBBBBBB */ - .extern MterpFillArrayData - EXPORT_PC - lh a1, 2(rPC) # a1 <- bbbb (lo) - lh a0, 4(rPC) # a0 <- BBBB (hi) - srl a3, rINST, 8 # a3 <- AA - ins a1, a0, 16, 16 # a1 <- BBBBbbbb - GET_VREG_U a0, a3 # a0 <- vAA (array object) - dlsa a1, a1, rPC, 1 # a1 <- PC + BBBBbbbb*2 (array data off.) - jal MterpFillArrayData # (obj, payload) - beqzc v0, MterpPossibleException # exception? - FETCH_ADVANCE_INST 3 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_throw: /* 0x27 */ -/* File: mips64/op_throw.S */ - /* - * Throw an exception object in the current thread. - */ - /* throw vAA */ - EXPORT_PC - srl a2, rINST, 8 # a2 <- AA - GET_VREG_U a0, a2 # a0 <- vAA (exception object) - beqzc a0, common_errNullObject - sd a0, THREAD_EXCEPTION_OFFSET(rSELF) # thread->exception <- obj - b MterpException - -/* ------------------------------ */ - .balign 128 -.L_op_goto: /* 0x28 */ -/* File: mips64/op_goto.S */ - /* - * Unconditional branch, 8-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto +AA */ - srl rINST, rINST, 8 - seb rINST, rINST # rINST <- offset (sign-extended AA) - b MterpCommonTakenBranchNoFlags - -/* ------------------------------ */ - .balign 128 -.L_op_goto_16: /* 0x29 */ -/* File: mips64/op_goto_16.S */ - /* - * Unconditional branch, 16-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto/16 +AAAA */ - lh rINST, 2(rPC) # rINST <- offset (sign-extended AAAA) - b MterpCommonTakenBranchNoFlags - -/* ------------------------------ */ - .balign 128 -.L_op_goto_32: /* 0x2a */ -/* File: mips64/op_goto_32.S */ - /* - * Unconditional branch, 32-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - * - * Unlike most opcodes, this one is allowed to branch to itself, so - * our "backward branch" test must be "<=0" instead of "<0". - */ - /* goto/32 +AAAAAAAA */ - lh rINST, 2(rPC) # rINST <- aaaa (low) - lh a1, 4(rPC) # a1 <- AAAA (high) - ins rINST, a1, 16, 16 # rINST <- offset (sign-extended AAAAaaaa) - b MterpCommonTakenBranchNoFlags - -/* ------------------------------ */ - .balign 128 -.L_op_packed_switch: /* 0x2b */ -/* File: mips64/op_packed_switch.S */ - /* - * Handle a packed-switch or sparse-switch instruction. In both cases - * we decode it and hand it off to a helper function. - * - * We don't really expect backward branches in a switch statement, but - * they're perfectly legal, so we check for them here. - * - * for: packed-switch, sparse-switch - */ - /* op vAA, +BBBBBBBB */ - .extern MterpDoPackedSwitch - lh a0, 2(rPC) # a0 <- bbbb (lo) - lh a1, 4(rPC) # a1 <- BBBB (hi) - srl a3, rINST, 8 # a3 <- AA - ins a0, a1, 16, 16 # a0 <- BBBBbbbb - GET_VREG a1, a3 # a1 <- vAA - dlsa a0, a0, rPC, 1 # a0 <- PC + BBBBbbbb*2 - jal MterpDoPackedSwitch # v0 <- code-unit branch offset - move rINST, v0 - b MterpCommonTakenBranchNoFlags - -/* ------------------------------ */ - .balign 128 -.L_op_sparse_switch: /* 0x2c */ -/* File: mips64/op_sparse_switch.S */ -/* File: mips64/op_packed_switch.S */ - /* - * Handle a packed-switch or sparse-switch instruction. In both cases - * we decode it and hand it off to a helper function. - * - * We don't really expect backward branches in a switch statement, but - * they're perfectly legal, so we check for them here. - * - * for: packed-switch, sparse-switch - */ - /* op vAA, +BBBBBBBB */ - .extern MterpDoSparseSwitch - lh a0, 2(rPC) # a0 <- bbbb (lo) - lh a1, 4(rPC) # a1 <- BBBB (hi) - srl a3, rINST, 8 # a3 <- AA - ins a0, a1, 16, 16 # a0 <- BBBBbbbb - GET_VREG a1, a3 # a1 <- vAA - dlsa a0, a0, rPC, 1 # a0 <- PC + BBBBbbbb*2 - jal MterpDoSparseSwitch # v0 <- code-unit branch offset - move rINST, v0 - b MterpCommonTakenBranchNoFlags - - -/* ------------------------------ */ - .balign 128 -.L_op_cmpl_float: /* 0x2d */ -/* File: mips64/op_cmpl_float.S */ -/* File: mips64/fcmp.S */ - /* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * For: cmpl-float, cmpg-float - */ - /* op vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_FLOAT f0, a2 # f0 <- vBB - GET_VREG_FLOAT f1, a3 # f1 <- vCC - cmp.eq.s f2, f0, f1 - li a0, 0 - bc1nez f2, 1f # done if vBB == vCC (ordered) - .if 0 - cmp.lt.s f2, f0, f1 - li a0, -1 - bc1nez f2, 1f # done if vBB < vCC (ordered) - li a0, 1 # vBB > vCC or unordered - .else - cmp.lt.s f2, f1, f0 - li a0, 1 - bc1nez f2, 1f # done if vBB > vCC (ordered) - li a0, -1 # vBB < vCC or unordered - .endif -1: - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_cmpg_float: /* 0x2e */ -/* File: mips64/op_cmpg_float.S */ -/* File: mips64/fcmp.S */ - /* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * For: cmpl-float, cmpg-float - */ - /* op vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_FLOAT f0, a2 # f0 <- vBB - GET_VREG_FLOAT f1, a3 # f1 <- vCC - cmp.eq.s f2, f0, f1 - li a0, 0 - bc1nez f2, 1f # done if vBB == vCC (ordered) - .if 1 - cmp.lt.s f2, f0, f1 - li a0, -1 - bc1nez f2, 1f # done if vBB < vCC (ordered) - li a0, 1 # vBB > vCC or unordered - .else - cmp.lt.s f2, f1, f0 - li a0, 1 - bc1nez f2, 1f # done if vBB > vCC (ordered) - li a0, -1 # vBB < vCC or unordered - .endif -1: - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_cmpl_double: /* 0x2f */ -/* File: mips64/op_cmpl_double.S */ -/* File: mips64/fcmpWide.S */ - /* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * For: cmpl-double, cmpg-double - */ - /* op vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_DOUBLE f0, a2 # f0 <- vBB - GET_VREG_DOUBLE f1, a3 # f1 <- vCC - cmp.eq.d f2, f0, f1 - li a0, 0 - bc1nez f2, 1f # done if vBB == vCC (ordered) - .if 0 - cmp.lt.d f2, f0, f1 - li a0, -1 - bc1nez f2, 1f # done if vBB < vCC (ordered) - li a0, 1 # vBB > vCC or unordered - .else - cmp.lt.d f2, f1, f0 - li a0, 1 - bc1nez f2, 1f # done if vBB > vCC (ordered) - li a0, -1 # vBB < vCC or unordered - .endif -1: - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_cmpg_double: /* 0x30 */ -/* File: mips64/op_cmpg_double.S */ -/* File: mips64/fcmpWide.S */ - /* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * For: cmpl-double, cmpg-double - */ - /* op vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_DOUBLE f0, a2 # f0 <- vBB - GET_VREG_DOUBLE f1, a3 # f1 <- vCC - cmp.eq.d f2, f0, f1 - li a0, 0 - bc1nez f2, 1f # done if vBB == vCC (ordered) - .if 1 - cmp.lt.d f2, f0, f1 - li a0, -1 - bc1nez f2, 1f # done if vBB < vCC (ordered) - li a0, 1 # vBB > vCC or unordered - .else - cmp.lt.d f2, f1, f0 - li a0, 1 - bc1nez f2, 1f # done if vBB > vCC (ordered) - li a0, -1 # vBB < vCC or unordered - .endif -1: - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_cmp_long: /* 0x31 */ -/* File: mips64/op_cmp_long.S */ - /* cmp-long vAA, vBB, vCC */ - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - srl a4, rINST, 8 # a4 <- AA - GET_VREG_WIDE a0, a2 # a0 <- vBB - GET_VREG_WIDE a1, a3 # a1 <- vCC - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - slt a2, a0, a1 - slt a0, a1, a0 - subu a0, a0, a2 - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a4 # vAA <- result - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_if_eq: /* 0x32 */ -/* File: mips64/op_if_eq.S */ -/* File: mips64/bincmp.S */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform, e.g. for - * "if-le" you would use "le". - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - lh rINST, 2(rPC) # rINST <- offset (sign-extended CCCC) - GET_VREG a0, a2 # a0 <- vA - GET_VREG a1, a3 # a1 <- vB - beqc a0, a1, MterpCommonTakenBranchNoFlags - li v0, JIT_CHECK_OSR # possible OSR re-entry? - beqc rPROFILE, v0, .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_ne: /* 0x33 */ -/* File: mips64/op_if_ne.S */ -/* File: mips64/bincmp.S */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform, e.g. for - * "if-le" you would use "le". - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - lh rINST, 2(rPC) # rINST <- offset (sign-extended CCCC) - GET_VREG a0, a2 # a0 <- vA - GET_VREG a1, a3 # a1 <- vB - bnec a0, a1, MterpCommonTakenBranchNoFlags - li v0, JIT_CHECK_OSR # possible OSR re-entry? - beqc rPROFILE, v0, .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_lt: /* 0x34 */ -/* File: mips64/op_if_lt.S */ -/* File: mips64/bincmp.S */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform, e.g. for - * "if-le" you would use "le". - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - lh rINST, 2(rPC) # rINST <- offset (sign-extended CCCC) - GET_VREG a0, a2 # a0 <- vA - GET_VREG a1, a3 # a1 <- vB - bltc a0, a1, MterpCommonTakenBranchNoFlags - li v0, JIT_CHECK_OSR # possible OSR re-entry? - beqc rPROFILE, v0, .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_ge: /* 0x35 */ -/* File: mips64/op_if_ge.S */ -/* File: mips64/bincmp.S */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform, e.g. for - * "if-le" you would use "le". - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - lh rINST, 2(rPC) # rINST <- offset (sign-extended CCCC) - GET_VREG a0, a2 # a0 <- vA - GET_VREG a1, a3 # a1 <- vB - bgec a0, a1, MterpCommonTakenBranchNoFlags - li v0, JIT_CHECK_OSR # possible OSR re-entry? - beqc rPROFILE, v0, .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_gt: /* 0x36 */ -/* File: mips64/op_if_gt.S */ -/* File: mips64/bincmp.S */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform, e.g. for - * "if-le" you would use "le". - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - lh rINST, 2(rPC) # rINST <- offset (sign-extended CCCC) - GET_VREG a0, a2 # a0 <- vA - GET_VREG a1, a3 # a1 <- vB - bgtc a0, a1, MterpCommonTakenBranchNoFlags - li v0, JIT_CHECK_OSR # possible OSR re-entry? - beqc rPROFILE, v0, .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_le: /* 0x37 */ -/* File: mips64/op_if_le.S */ -/* File: mips64/bincmp.S */ - /* - * Generic two-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform, e.g. for - * "if-le" you would use "le". - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - lh rINST, 2(rPC) # rINST <- offset (sign-extended CCCC) - GET_VREG a0, a2 # a0 <- vA - GET_VREG a1, a3 # a1 <- vB - blec a0, a1, MterpCommonTakenBranchNoFlags - li v0, JIT_CHECK_OSR # possible OSR re-entry? - beqc rPROFILE, v0, .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_eqz: /* 0x38 */ -/* File: mips64/op_if_eqz.S */ -/* File: mips64/zcmp.S */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform, e.g. for - * "if-lez" you would use "le". - * - * For: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - srl a2, rINST, 8 # a2 <- AA - lh rINST, 2(rPC) # rINST <- offset (sign-extended BBBB) - GET_VREG a0, a2 # a0 <- vAA - beqzc a0, MterpCommonTakenBranchNoFlags - li v0, JIT_CHECK_OSR # possible OSR re-entry? - beqc rPROFILE, v0, .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_nez: /* 0x39 */ -/* File: mips64/op_if_nez.S */ -/* File: mips64/zcmp.S */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform, e.g. for - * "if-lez" you would use "le". - * - * For: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - srl a2, rINST, 8 # a2 <- AA - lh rINST, 2(rPC) # rINST <- offset (sign-extended BBBB) - GET_VREG a0, a2 # a0 <- vAA - bnezc a0, MterpCommonTakenBranchNoFlags - li v0, JIT_CHECK_OSR # possible OSR re-entry? - beqc rPROFILE, v0, .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_ltz: /* 0x3a */ -/* File: mips64/op_if_ltz.S */ -/* File: mips64/zcmp.S */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform, e.g. for - * "if-lez" you would use "le". - * - * For: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - srl a2, rINST, 8 # a2 <- AA - lh rINST, 2(rPC) # rINST <- offset (sign-extended BBBB) - GET_VREG a0, a2 # a0 <- vAA - bltzc a0, MterpCommonTakenBranchNoFlags - li v0, JIT_CHECK_OSR # possible OSR re-entry? - beqc rPROFILE, v0, .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_gez: /* 0x3b */ -/* File: mips64/op_if_gez.S */ -/* File: mips64/zcmp.S */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform, e.g. for - * "if-lez" you would use "le". - * - * For: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - srl a2, rINST, 8 # a2 <- AA - lh rINST, 2(rPC) # rINST <- offset (sign-extended BBBB) - GET_VREG a0, a2 # a0 <- vAA - bgezc a0, MterpCommonTakenBranchNoFlags - li v0, JIT_CHECK_OSR # possible OSR re-entry? - beqc rPROFILE, v0, .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_gtz: /* 0x3c */ -/* File: mips64/op_if_gtz.S */ -/* File: mips64/zcmp.S */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform, e.g. for - * "if-lez" you would use "le". - * - * For: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - srl a2, rINST, 8 # a2 <- AA - lh rINST, 2(rPC) # rINST <- offset (sign-extended BBBB) - GET_VREG a0, a2 # a0 <- vAA - bgtzc a0, MterpCommonTakenBranchNoFlags - li v0, JIT_CHECK_OSR # possible OSR re-entry? - beqc rPROFILE, v0, .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_if_lez: /* 0x3d */ -/* File: mips64/op_if_lez.S */ -/* File: mips64/zcmp.S */ - /* - * Generic one-operand compare-and-branch operation. Provide a "condition" - * fragment that specifies the comparison to perform, e.g. for - * "if-lez" you would use "le". - * - * For: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - srl a2, rINST, 8 # a2 <- AA - lh rINST, 2(rPC) # rINST <- offset (sign-extended BBBB) - GET_VREG a0, a2 # a0 <- vAA - blezc a0, MterpCommonTakenBranchNoFlags - li v0, JIT_CHECK_OSR # possible OSR re-entry? - beqc rPROFILE, v0, .L_check_not_taken_osr - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_3e: /* 0x3e */ -/* File: mips64/op_unused_3e.S */ -/* File: mips64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_3f: /* 0x3f */ -/* File: mips64/op_unused_3f.S */ -/* File: mips64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_40: /* 0x40 */ -/* File: mips64/op_unused_40.S */ -/* File: mips64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_41: /* 0x41 */ -/* File: mips64/op_unused_41.S */ -/* File: mips64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_42: /* 0x42 */ -/* File: mips64/op_unused_42.S */ -/* File: mips64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_43: /* 0x43 */ -/* File: mips64/op_unused_43.S */ -/* File: mips64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_aget: /* 0x44 */ -/* File: mips64/op_aget.S */ - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - srl a4, rINST, 8 # a4 <- AA - GET_VREG_U a0, a2 # a0 <- vBB (array object) - GET_VREG a1, a3 # a1 <- vCC (requested index) - beqz a0, common_errNullObject # bail if null array object - lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length - .if 2 - # [d]lsa does not support shift count of 0. - dlsa a0, a1, a0, 2 # a0 <- arrayObj + index*width - .else - daddu a0, a1, a0 # a0 <- arrayObj + index*width - .endif - bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - lw a2, MIRROR_INT_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a2, a4 # vAA <- a2 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aget_wide: /* 0x45 */ -/* File: mips64/op_aget_wide.S */ - /* - * Array get, 64 bits. vAA <- vBB[vCC]. - * - */ - /* aget-wide vAA, vBB, vCC */ - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - srl a4, rINST, 8 # a4 <- AA - GET_VREG_U a0, a2 # a0 <- vBB (array object) - GET_VREG a1, a3 # a1 <- vCC (requested index) - beqz a0, common_errNullObject # bail if null array object - lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length - dlsa a0, a1, a0, 3 # a0 <- arrayObj + index*width - bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - lw a2, MIRROR_WIDE_ARRAY_DATA_OFFSET(a0) - lw a3, (MIRROR_WIDE_ARRAY_DATA_OFFSET+4)(a0) - dinsu a2, a3, 32, 32 # a2 <- vBB[vCC] - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a2, a4 # vAA <- a2 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aget_object: /* 0x46 */ -/* File: mips64/op_aget_object.S */ - /* - * Array object get. vAA <- vBB[vCC]. - * - * for: aget-object - */ - /* op vAA, vBB, vCC */ - .extern artAGetObjectFromMterp - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - EXPORT_PC - GET_VREG_U a0, a2 # a0 <- vBB (array object) - GET_VREG a1, a3 # a1 <- vCC (requested index) - jal artAGetObjectFromMterp # (array, index) - ld a1, THREAD_EXCEPTION_OFFSET(rSELF) - srl a4, rINST, 8 # a4 <- AA - PREFETCH_INST 2 - bnez a1, MterpException - SET_VREG_OBJECT v0, a4 # vAA <- v0 - ADVANCE 2 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aget_boolean: /* 0x47 */ -/* File: mips64/op_aget_boolean.S */ -/* File: mips64/op_aget.S */ - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - srl a4, rINST, 8 # a4 <- AA - GET_VREG_U a0, a2 # a0 <- vBB (array object) - GET_VREG a1, a3 # a1 <- vCC (requested index) - beqz a0, common_errNullObject # bail if null array object - lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length - .if 0 - # [d]lsa does not support shift count of 0. - dlsa a0, a1, a0, 0 # a0 <- arrayObj + index*width - .else - daddu a0, a1, a0 # a0 <- arrayObj + index*width - .endif - bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - lbu a2, MIRROR_BOOLEAN_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a2, a4 # vAA <- a2 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_aget_byte: /* 0x48 */ -/* File: mips64/op_aget_byte.S */ -/* File: mips64/op_aget.S */ - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - srl a4, rINST, 8 # a4 <- AA - GET_VREG_U a0, a2 # a0 <- vBB (array object) - GET_VREG a1, a3 # a1 <- vCC (requested index) - beqz a0, common_errNullObject # bail if null array object - lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length - .if 0 - # [d]lsa does not support shift count of 0. - dlsa a0, a1, a0, 0 # a0 <- arrayObj + index*width - .else - daddu a0, a1, a0 # a0 <- arrayObj + index*width - .endif - bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - lb a2, MIRROR_BYTE_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a2, a4 # vAA <- a2 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_aget_char: /* 0x49 */ -/* File: mips64/op_aget_char.S */ -/* File: mips64/op_aget.S */ - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - srl a4, rINST, 8 # a4 <- AA - GET_VREG_U a0, a2 # a0 <- vBB (array object) - GET_VREG a1, a3 # a1 <- vCC (requested index) - beqz a0, common_errNullObject # bail if null array object - lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length - .if 1 - # [d]lsa does not support shift count of 0. - dlsa a0, a1, a0, 1 # a0 <- arrayObj + index*width - .else - daddu a0, a1, a0 # a0 <- arrayObj + index*width - .endif - bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - lhu a2, MIRROR_CHAR_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a2, a4 # vAA <- a2 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_aget_short: /* 0x4a */ -/* File: mips64/op_aget_short.S */ -/* File: mips64/op_aget.S */ - /* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - * NOTE: assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - srl a4, rINST, 8 # a4 <- AA - GET_VREG_U a0, a2 # a0 <- vBB (array object) - GET_VREG a1, a3 # a1 <- vCC (requested index) - beqz a0, common_errNullObject # bail if null array object - lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length - .if 1 - # [d]lsa does not support shift count of 0. - dlsa a0, a1, a0, 1 # a0 <- arrayObj + index*width - .else - daddu a0, a1, a0 # a0 <- arrayObj + index*width - .endif - bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - lh a2, MIRROR_SHORT_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a2, a4 # vAA <- a2 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_aput: /* 0x4b */ -/* File: mips64/op_aput.S */ - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - srl a4, rINST, 8 # a4 <- AA - GET_VREG_U a0, a2 # a0 <- vBB (array object) - GET_VREG a1, a3 # a1 <- vCC (requested index) - beqz a0, common_errNullObject # bail if null array object - lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length - .if 2 - # [d]lsa does not support shift count of 0. - dlsa a0, a1, a0, 2 # a0 <- arrayObj + index*width - .else - daddu a0, a1, a0 # a0 <- arrayObj + index*width - .endif - bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_VREG a2, a4 # a2 <- vAA - GET_INST_OPCODE v0 # extract opcode from rINST - sw a2, MIRROR_INT_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aput_wide: /* 0x4c */ -/* File: mips64/op_aput_wide.S */ - /* - * Array put, 64 bits. vBB[vCC] <- vAA. - * - */ - /* aput-wide vAA, vBB, vCC */ - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - srl a4, rINST, 8 # a4 <- AA - GET_VREG_U a0, a2 # a0 <- vBB (array object) - GET_VREG a1, a3 # a1 <- vCC (requested index) - beqz a0, common_errNullObject # bail if null array object - lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length - dlsa a0, a1, a0, 3 # a0 <- arrayObj + index*width - bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail - GET_VREG_WIDE a2, a4 # a2 <- vAA - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - sw a2, MIRROR_WIDE_ARRAY_DATA_OFFSET(a0) - dsrl32 a2, a2, 0 - sw a2, (MIRROR_WIDE_ARRAY_DATA_OFFSET+4)(a0) # vBB[vCC] <- a2 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aput_object: /* 0x4d */ -/* File: mips64/op_aput_object.S */ - /* - * Store an object into an array. vBB[vCC] <- vAA. - */ - /* op vAA, vBB, vCC */ - .extern MterpAputObject - EXPORT_PC - daddu a0, rFP, OFF_FP_SHADOWFRAME - move a1, rPC - move a2, rINST - jal MterpAputObject - beqzc v0, MterpPossibleException - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_aput_boolean: /* 0x4e */ -/* File: mips64/op_aput_boolean.S */ -/* File: mips64/op_aput.S */ - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - srl a4, rINST, 8 # a4 <- AA - GET_VREG_U a0, a2 # a0 <- vBB (array object) - GET_VREG a1, a3 # a1 <- vCC (requested index) - beqz a0, common_errNullObject # bail if null array object - lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length - .if 0 - # [d]lsa does not support shift count of 0. - dlsa a0, a1, a0, 0 # a0 <- arrayObj + index*width - .else - daddu a0, a1, a0 # a0 <- arrayObj + index*width - .endif - bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_VREG a2, a4 # a2 <- vAA - GET_INST_OPCODE v0 # extract opcode from rINST - sb a2, MIRROR_BOOLEAN_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_aput_byte: /* 0x4f */ -/* File: mips64/op_aput_byte.S */ -/* File: mips64/op_aput.S */ - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - srl a4, rINST, 8 # a4 <- AA - GET_VREG_U a0, a2 # a0 <- vBB (array object) - GET_VREG a1, a3 # a1 <- vCC (requested index) - beqz a0, common_errNullObject # bail if null array object - lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length - .if 0 - # [d]lsa does not support shift count of 0. - dlsa a0, a1, a0, 0 # a0 <- arrayObj + index*width - .else - daddu a0, a1, a0 # a0 <- arrayObj + index*width - .endif - bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_VREG a2, a4 # a2 <- vAA - GET_INST_OPCODE v0 # extract opcode from rINST - sb a2, MIRROR_BYTE_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_aput_char: /* 0x50 */ -/* File: mips64/op_aput_char.S */ -/* File: mips64/op_aput.S */ - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - srl a4, rINST, 8 # a4 <- AA - GET_VREG_U a0, a2 # a0 <- vBB (array object) - GET_VREG a1, a3 # a1 <- vCC (requested index) - beqz a0, common_errNullObject # bail if null array object - lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length - .if 1 - # [d]lsa does not support shift count of 0. - dlsa a0, a1, a0, 1 # a0 <- arrayObj + index*width - .else - daddu a0, a1, a0 # a0 <- arrayObj + index*width - .endif - bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_VREG a2, a4 # a2 <- vAA - GET_INST_OPCODE v0 # extract opcode from rINST - sh a2, MIRROR_CHAR_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_aput_short: /* 0x51 */ -/* File: mips64/op_aput_short.S */ -/* File: mips64/op_aput.S */ - /* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - * NOTE: this assumes data offset for arrays is the same for all non-wide types. - * If this changes, specialize. - */ - /* op vAA, vBB, vCC */ - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - srl a4, rINST, 8 # a4 <- AA - GET_VREG_U a0, a2 # a0 <- vBB (array object) - GET_VREG a1, a3 # a1 <- vCC (requested index) - beqz a0, common_errNullObject # bail if null array object - lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length - .if 1 - # [d]lsa does not support shift count of 0. - dlsa a0, a1, a0, 1 # a0 <- arrayObj + index*width - .else - daddu a0, a1, a0 # a0 <- arrayObj + index*width - .endif - bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_VREG a2, a4 # a2 <- vAA - GET_INST_OPCODE v0 # extract opcode from rINST - sh a2, MIRROR_SHORT_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_iget: /* 0x52 */ -/* File: mips64/op_iget.S */ -/* File: mips64/field.S */ -TODO - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_wide: /* 0x53 */ -/* File: mips64/op_iget_wide.S */ -/* File: mips64/op_iget.S */ -/* File: mips64/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_object: /* 0x54 */ -/* File: mips64/op_iget_object.S */ -/* File: mips64/op_iget.S */ -/* File: mips64/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_boolean: /* 0x55 */ -/* File: mips64/op_iget_boolean.S */ -/* File: mips64/op_iget.S */ -/* File: mips64/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_byte: /* 0x56 */ -/* File: mips64/op_iget_byte.S */ -/* File: mips64/op_iget.S */ -/* File: mips64/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_char: /* 0x57 */ -/* File: mips64/op_iget_char.S */ -/* File: mips64/op_iget.S */ -/* File: mips64/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_short: /* 0x58 */ -/* File: mips64/op_iget_short.S */ -/* File: mips64/op_iget.S */ -/* File: mips64/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_iput: /* 0x59 */ -/* File: mips64/op_iput.S */ -/* File: mips64/field.S */ -TODO - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_wide: /* 0x5a */ -/* File: mips64/op_iput_wide.S */ -/* File: mips64/op_iput.S */ -/* File: mips64/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_object: /* 0x5b */ -/* File: mips64/op_iput_object.S */ -/* File: mips64/op_iput.S */ -/* File: mips64/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_boolean: /* 0x5c */ -/* File: mips64/op_iput_boolean.S */ -/* File: mips64/op_iput.S */ -/* File: mips64/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_byte: /* 0x5d */ -/* File: mips64/op_iput_byte.S */ -/* File: mips64/op_iput.S */ -/* File: mips64/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_char: /* 0x5e */ -/* File: mips64/op_iput_char.S */ -/* File: mips64/op_iput.S */ -/* File: mips64/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_short: /* 0x5f */ -/* File: mips64/op_iput_short.S */ -/* File: mips64/op_iput.S */ -/* File: mips64/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_sget: /* 0x60 */ -/* File: mips64/op_sget.S */ -/* File: mips64/field.S */ -TODO - - -/* ------------------------------ */ - .balign 128 -.L_op_sget_wide: /* 0x61 */ -/* File: mips64/op_sget_wide.S */ -/* File: mips64/op_sget.S */ -/* File: mips64/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_sget_object: /* 0x62 */ -/* File: mips64/op_sget_object.S */ -/* File: mips64/op_sget.S */ -/* File: mips64/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_sget_boolean: /* 0x63 */ -/* File: mips64/op_sget_boolean.S */ -/* File: mips64/op_sget.S */ -/* File: mips64/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_sget_byte: /* 0x64 */ -/* File: mips64/op_sget_byte.S */ -/* File: mips64/op_sget.S */ -/* File: mips64/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_sget_char: /* 0x65 */ -/* File: mips64/op_sget_char.S */ -/* File: mips64/op_sget.S */ -/* File: mips64/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_sget_short: /* 0x66 */ -/* File: mips64/op_sget_short.S */ -/* File: mips64/op_sget.S */ -/* File: mips64/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_sput: /* 0x67 */ -/* File: mips64/op_sput.S */ -/* File: mips64/field.S */ -TODO - - -/* ------------------------------ */ - .balign 128 -.L_op_sput_wide: /* 0x68 */ -/* File: mips64/op_sput_wide.S */ -/* File: mips64/op_sput.S */ -/* File: mips64/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_sput_object: /* 0x69 */ -/* File: mips64/op_sput_object.S */ -/* File: mips64/op_sput.S */ -/* File: mips64/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_sput_boolean: /* 0x6a */ -/* File: mips64/op_sput_boolean.S */ -/* File: mips64/op_sput.S */ -/* File: mips64/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_sput_byte: /* 0x6b */ -/* File: mips64/op_sput_byte.S */ -/* File: mips64/op_sput.S */ -/* File: mips64/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_sput_char: /* 0x6c */ -/* File: mips64/op_sput_char.S */ -/* File: mips64/op_sput.S */ -/* File: mips64/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_sput_short: /* 0x6d */ -/* File: mips64/op_sput_short.S */ -/* File: mips64/op_sput.S */ -/* File: mips64/field.S */ -TODO - - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual: /* 0x6e */ -/* File: mips64/op_invoke_virtual.S */ -/* File: mips64/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtual - .extern MterpShouldSwitchInterpreters - EXPORT_PC - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - jal MterpInvokeVirtual - beqzc v0, MterpException - FETCH_ADVANCE_INST 3 - jal MterpShouldSwitchInterpreters - bnezc v0, MterpFallback - GET_INST_OPCODE v0 - GOTO_OPCODE v0 - - /* - * Handle a virtual method call. - * - * for: invoke-virtual, invoke-virtual/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_super: /* 0x6f */ -/* File: mips64/op_invoke_super.S */ -/* File: mips64/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeSuper - .extern MterpShouldSwitchInterpreters - EXPORT_PC - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - jal MterpInvokeSuper - beqzc v0, MterpException - FETCH_ADVANCE_INST 3 - jal MterpShouldSwitchInterpreters - bnezc v0, MterpFallback - GET_INST_OPCODE v0 - GOTO_OPCODE v0 - - /* - * Handle a "super" method call. - * - * for: invoke-super, invoke-super/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_direct: /* 0x70 */ -/* File: mips64/op_invoke_direct.S */ -/* File: mips64/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeDirect - .extern MterpShouldSwitchInterpreters - EXPORT_PC - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - jal MterpInvokeDirect - beqzc v0, MterpException - FETCH_ADVANCE_INST 3 - jal MterpShouldSwitchInterpreters - bnezc v0, MterpFallback - GET_INST_OPCODE v0 - GOTO_OPCODE v0 - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_static: /* 0x71 */ -/* File: mips64/op_invoke_static.S */ -/* File: mips64/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeStatic - .extern MterpShouldSwitchInterpreters - EXPORT_PC - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - jal MterpInvokeStatic - beqzc v0, MterpException - FETCH_ADVANCE_INST 3 - jal MterpShouldSwitchInterpreters - bnezc v0, MterpFallback - GET_INST_OPCODE v0 - GOTO_OPCODE v0 - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_interface: /* 0x72 */ -/* File: mips64/op_invoke_interface.S */ -/* File: mips64/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeInterface - .extern MterpShouldSwitchInterpreters - EXPORT_PC - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - jal MterpInvokeInterface - beqzc v0, MterpException - FETCH_ADVANCE_INST 3 - jal MterpShouldSwitchInterpreters - bnezc v0, MterpFallback - GET_INST_OPCODE v0 - GOTO_OPCODE v0 - - /* - * Handle an interface method call. - * - * for: invoke-interface, invoke-interface/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - -/* ------------------------------ */ - .balign 128 -.L_op_return_void_no_barrier: /* 0x73 */ -/* File: mips64/op_return_void_no_barrier.S */ - .extern MterpSuspendCheck - lw ra, THREAD_FLAGS_OFFSET(rSELF) - move a0, rSELF - and ra, ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - beqzc ra, 1f - jal MterpSuspendCheck # (self) -1: - li a0, 0 - b MterpReturn - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual_range: /* 0x74 */ -/* File: mips64/op_invoke_virtual_range.S */ -/* File: mips64/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtualRange - .extern MterpShouldSwitchInterpreters - EXPORT_PC - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - jal MterpInvokeVirtualRange - beqzc v0, MterpException - FETCH_ADVANCE_INST 3 - jal MterpShouldSwitchInterpreters - bnezc v0, MterpFallback - GET_INST_OPCODE v0 - GOTO_OPCODE v0 - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_super_range: /* 0x75 */ -/* File: mips64/op_invoke_super_range.S */ -/* File: mips64/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeSuperRange - .extern MterpShouldSwitchInterpreters - EXPORT_PC - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - jal MterpInvokeSuperRange - beqzc v0, MterpException - FETCH_ADVANCE_INST 3 - jal MterpShouldSwitchInterpreters - bnezc v0, MterpFallback - GET_INST_OPCODE v0 - GOTO_OPCODE v0 - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_direct_range: /* 0x76 */ -/* File: mips64/op_invoke_direct_range.S */ -/* File: mips64/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeDirectRange - .extern MterpShouldSwitchInterpreters - EXPORT_PC - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - jal MterpInvokeDirectRange - beqzc v0, MterpException - FETCH_ADVANCE_INST 3 - jal MterpShouldSwitchInterpreters - bnezc v0, MterpFallback - GET_INST_OPCODE v0 - GOTO_OPCODE v0 - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_static_range: /* 0x77 */ -/* File: mips64/op_invoke_static_range.S */ -/* File: mips64/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeStaticRange - .extern MterpShouldSwitchInterpreters - EXPORT_PC - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - jal MterpInvokeStaticRange - beqzc v0, MterpException - FETCH_ADVANCE_INST 3 - jal MterpShouldSwitchInterpreters - bnezc v0, MterpFallback - GET_INST_OPCODE v0 - GOTO_OPCODE v0 - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_interface_range: /* 0x78 */ -/* File: mips64/op_invoke_interface_range.S */ -/* File: mips64/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeInterfaceRange - .extern MterpShouldSwitchInterpreters - EXPORT_PC - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - jal MterpInvokeInterfaceRange - beqzc v0, MterpException - FETCH_ADVANCE_INST 3 - jal MterpShouldSwitchInterpreters - bnezc v0, MterpFallback - GET_INST_OPCODE v0 - GOTO_OPCODE v0 - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_79: /* 0x79 */ -/* File: mips64/op_unused_79.S */ -/* File: mips64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_7a: /* 0x7a */ -/* File: mips64/op_unused_7a.S */ -/* File: mips64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_neg_int: /* 0x7b */ -/* File: mips64/op_neg_int.S */ -/* File: mips64/unop.S */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "a0 = op a0". - * - * for: int-to-byte, int-to-char, int-to-short, - * not-int, neg-int - */ - /* unop vA, vB */ - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a3 # a0 <- vB - ext a2, rINST, 8, 4 # a2 <- A - # optional op - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - subu a0, zero, a0 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_not_int: /* 0x7c */ -/* File: mips64/op_not_int.S */ -/* File: mips64/unop.S */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "a0 = op a0". - * - * for: int-to-byte, int-to-char, int-to-short, - * not-int, neg-int - */ - /* unop vA, vB */ - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a3 # a0 <- vB - ext a2, rINST, 8, 4 # a2 <- A - # optional op - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - nor a0, zero, a0 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_neg_long: /* 0x7d */ -/* File: mips64/op_neg_long.S */ -/* File: mips64/unopWide.S */ - /* - * Generic 64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "a0 = op a0". - * - * For: not-long, neg-long - */ - /* unop vA, vB */ - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_WIDE a0, a3 # a0 <- vB - ext a2, rINST, 8, 4 # a2 <- A - # optional op - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - dsubu a0, zero, a0 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_not_long: /* 0x7e */ -/* File: mips64/op_not_long.S */ -/* File: mips64/unopWide.S */ - /* - * Generic 64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "a0 = op a0". - * - * For: not-long, neg-long - */ - /* unop vA, vB */ - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_WIDE a0, a3 # a0 <- vB - ext a2, rINST, 8, 4 # a2 <- A - # optional op - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - nor a0, zero, a0 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_neg_float: /* 0x7f */ -/* File: mips64/op_neg_float.S */ -/* File: mips64/fcvtHeader.S */ - /* - * Loads a specified register from vB. Used primarily for conversions - * from or to a floating-point type. - * - * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to - * store the result in vA and jump to the next instruction. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - */ - ext a1, rINST, 8, 4 # a1 <- A - srl a2, rINST, 12 # a2 <- B - GET_VREG_FLOAT f0, a2 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - - neg.s f0, f0 -/* File: mips64/fcvtFooter.S */ - /* - * Stores a specified register containing the result of conversion - * from or to a floating-point type and jumps to the next instruction. - * - * Expects a1 to contain the destination Dalvik register number. - * a1 is set up by fcvtHeader.S. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - * - * Note that this file can't be included after a break in other files - * and in those files its contents appear as a copy. - * See: float-to-int, float-to-long, double-to-int, double-to-long. - */ - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_FLOAT f0, a1 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_neg_double: /* 0x80 */ -/* File: mips64/op_neg_double.S */ -/* File: mips64/fcvtHeader.S */ - /* - * Loads a specified register from vB. Used primarily for conversions - * from or to a floating-point type. - * - * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to - * store the result in vA and jump to the next instruction. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - */ - ext a1, rINST, 8, 4 # a1 <- A - srl a2, rINST, 12 # a2 <- B - GET_VREG_DOUBLE f0, a2 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - - neg.d f0, f0 -/* File: mips64/fcvtFooter.S */ - /* - * Stores a specified register containing the result of conversion - * from or to a floating-point type and jumps to the next instruction. - * - * Expects a1 to contain the destination Dalvik register number. - * a1 is set up by fcvtHeader.S. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - * - * Note that this file can't be included after a break in other files - * and in those files its contents appear as a copy. - * See: float-to-int, float-to-long, double-to-int, double-to-long. - */ - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_DOUBLE f0, a1 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_long: /* 0x81 */ -/* File: mips64/op_int_to_long.S */ - /* int-to-long vA, vB */ - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a3 # a0 <- vB (sign-extended to 64 bits) - ext a2, rINST, 8, 4 # a2 <- A - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vA <- vB - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_float: /* 0x82 */ -/* File: mips64/op_int_to_float.S */ - /* - * Conversion from or to floating-point happens in a floating-point register. - * Therefore we load the input and store the output into or from a - * floating-point register irrespective of the type. - */ -/* File: mips64/fcvtHeader.S */ - /* - * Loads a specified register from vB. Used primarily for conversions - * from or to a floating-point type. - * - * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to - * store the result in vA and jump to the next instruction. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - */ - ext a1, rINST, 8, 4 # a1 <- A - srl a2, rINST, 12 # a2 <- B - GET_VREG_FLOAT f0, a2 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - - cvt.s.w f0, f0 -/* File: mips64/fcvtFooter.S */ - /* - * Stores a specified register containing the result of conversion - * from or to a floating-point type and jumps to the next instruction. - * - * Expects a1 to contain the destination Dalvik register number. - * a1 is set up by fcvtHeader.S. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - * - * Note that this file can't be included after a break in other files - * and in those files its contents appear as a copy. - * See: float-to-int, float-to-long, double-to-int, double-to-long. - */ - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_FLOAT f0, a1 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_double: /* 0x83 */ -/* File: mips64/op_int_to_double.S */ - /* - * Conversion from or to floating-point happens in a floating-point register. - * Therefore we load the input and store the output into or from a - * floating-point register irrespective of the type. - */ -/* File: mips64/fcvtHeader.S */ - /* - * Loads a specified register from vB. Used primarily for conversions - * from or to a floating-point type. - * - * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to - * store the result in vA and jump to the next instruction. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - */ - ext a1, rINST, 8, 4 # a1 <- A - srl a2, rINST, 12 # a2 <- B - GET_VREG_FLOAT f0, a2 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - - cvt.d.w f0, f0 -/* File: mips64/fcvtFooter.S */ - /* - * Stores a specified register containing the result of conversion - * from or to a floating-point type and jumps to the next instruction. - * - * Expects a1 to contain the destination Dalvik register number. - * a1 is set up by fcvtHeader.S. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - * - * Note that this file can't be included after a break in other files - * and in those files its contents appear as a copy. - * See: float-to-int, float-to-long, double-to-int, double-to-long. - */ - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_DOUBLE f0, a1 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_long_to_int: /* 0x84 */ -/* File: mips64/op_long_to_int.S */ -/* we ignore the high word, making this equivalent to a 32-bit reg move */ -/* File: mips64/op_move.S */ - /* for move, move-object, long-to-int */ - /* op vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_VREG a0, a3 # a0 <- vB - GET_INST_OPCODE v0 # extract opcode from rINST - .if 0 - SET_VREG_OBJECT a0, a2 # vA <- vB - .else - SET_VREG a0, a2 # vA <- vB - .endif - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_long_to_float: /* 0x85 */ -/* File: mips64/op_long_to_float.S */ - /* - * Conversion from or to floating-point happens in a floating-point register. - * Therefore we load the input and store the output into or from a - * floating-point register irrespective of the type. - */ -/* File: mips64/fcvtHeader.S */ - /* - * Loads a specified register from vB. Used primarily for conversions - * from or to a floating-point type. - * - * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to - * store the result in vA and jump to the next instruction. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - */ - ext a1, rINST, 8, 4 # a1 <- A - srl a2, rINST, 12 # a2 <- B - GET_VREG_DOUBLE f0, a2 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - - cvt.s.l f0, f0 -/* File: mips64/fcvtFooter.S */ - /* - * Stores a specified register containing the result of conversion - * from or to a floating-point type and jumps to the next instruction. - * - * Expects a1 to contain the destination Dalvik register number. - * a1 is set up by fcvtHeader.S. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - * - * Note that this file can't be included after a break in other files - * and in those files its contents appear as a copy. - * See: float-to-int, float-to-long, double-to-int, double-to-long. - */ - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_FLOAT f0, a1 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_long_to_double: /* 0x86 */ -/* File: mips64/op_long_to_double.S */ - /* - * Conversion from or to floating-point happens in a floating-point register. - * Therefore we load the input and store the output into or from a - * floating-point register irrespective of the type. - */ -/* File: mips64/fcvtHeader.S */ - /* - * Loads a specified register from vB. Used primarily for conversions - * from or to a floating-point type. - * - * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to - * store the result in vA and jump to the next instruction. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - */ - ext a1, rINST, 8, 4 # a1 <- A - srl a2, rINST, 12 # a2 <- B - GET_VREG_DOUBLE f0, a2 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - - cvt.d.l f0, f0 -/* File: mips64/fcvtFooter.S */ - /* - * Stores a specified register containing the result of conversion - * from or to a floating-point type and jumps to the next instruction. - * - * Expects a1 to contain the destination Dalvik register number. - * a1 is set up by fcvtHeader.S. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - * - * Note that this file can't be included after a break in other files - * and in those files its contents appear as a copy. - * See: float-to-int, float-to-long, double-to-int, double-to-long. - */ - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_DOUBLE f0, a1 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_float_to_int: /* 0x87 */ -/* File: mips64/op_float_to_int.S */ -/* File: mips64/fcvtHeader.S */ - /* - * Loads a specified register from vB. Used primarily for conversions - * from or to a floating-point type. - * - * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to - * store the result in vA and jump to the next instruction. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - */ - ext a1, rINST, 8, 4 # a1 <- A - srl a2, rINST, 12 # a2 <- B - GET_VREG_FLOAT f0, a2 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - - trunc.w.s f0, f0 -/* File: mips64/fcvtFooter.S */ - /* - * Stores a specified register containing the result of conversion - * from or to a floating-point type and jumps to the next instruction. - * - * Expects a1 to contain the destination Dalvik register number. - * a1 is set up by fcvtHeader.S. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - * - * Note that this file can't be included after a break in other files - * and in those files its contents appear as a copy. - * See: float-to-int, float-to-long, double-to-int, double-to-long. - */ - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_FLOAT f0, a1 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_float_to_long: /* 0x88 */ -/* File: mips64/op_float_to_long.S */ -/* File: mips64/fcvtHeader.S */ - /* - * Loads a specified register from vB. Used primarily for conversions - * from or to a floating-point type. - * - * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to - * store the result in vA and jump to the next instruction. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - */ - ext a1, rINST, 8, 4 # a1 <- A - srl a2, rINST, 12 # a2 <- B - GET_VREG_FLOAT f0, a2 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - - trunc.l.s f0, f0 -/* File: mips64/fcvtFooter.S */ - /* - * Stores a specified register containing the result of conversion - * from or to a floating-point type and jumps to the next instruction. - * - * Expects a1 to contain the destination Dalvik register number. - * a1 is set up by fcvtHeader.S. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - * - * Note that this file can't be included after a break in other files - * and in those files its contents appear as a copy. - * See: float-to-int, float-to-long, double-to-int, double-to-long. - */ - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_DOUBLE f0, a1 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_float_to_double: /* 0x89 */ -/* File: mips64/op_float_to_double.S */ - /* - * Conversion from or to floating-point happens in a floating-point register. - * Therefore we load the input and store the output into or from a - * floating-point register irrespective of the type. - */ -/* File: mips64/fcvtHeader.S */ - /* - * Loads a specified register from vB. Used primarily for conversions - * from or to a floating-point type. - * - * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to - * store the result in vA and jump to the next instruction. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - */ - ext a1, rINST, 8, 4 # a1 <- A - srl a2, rINST, 12 # a2 <- B - GET_VREG_FLOAT f0, a2 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - - cvt.d.s f0, f0 -/* File: mips64/fcvtFooter.S */ - /* - * Stores a specified register containing the result of conversion - * from or to a floating-point type and jumps to the next instruction. - * - * Expects a1 to contain the destination Dalvik register number. - * a1 is set up by fcvtHeader.S. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - * - * Note that this file can't be included after a break in other files - * and in those files its contents appear as a copy. - * See: float-to-int, float-to-long, double-to-int, double-to-long. - */ - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_DOUBLE f0, a1 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_double_to_int: /* 0x8a */ -/* File: mips64/op_double_to_int.S */ -/* File: mips64/fcvtHeader.S */ - /* - * Loads a specified register from vB. Used primarily for conversions - * from or to a floating-point type. - * - * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to - * store the result in vA and jump to the next instruction. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - */ - ext a1, rINST, 8, 4 # a1 <- A - srl a2, rINST, 12 # a2 <- B - GET_VREG_DOUBLE f0, a2 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - - trunc.w.d f0, f0 -/* File: mips64/fcvtFooter.S */ - /* - * Stores a specified register containing the result of conversion - * from or to a floating-point type and jumps to the next instruction. - * - * Expects a1 to contain the destination Dalvik register number. - * a1 is set up by fcvtHeader.S. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - * - * Note that this file can't be included after a break in other files - * and in those files its contents appear as a copy. - * See: float-to-int, float-to-long, double-to-int, double-to-long. - */ - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_FLOAT f0, a1 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_double_to_long: /* 0x8b */ -/* File: mips64/op_double_to_long.S */ -/* File: mips64/fcvtHeader.S */ - /* - * Loads a specified register from vB. Used primarily for conversions - * from or to a floating-point type. - * - * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to - * store the result in vA and jump to the next instruction. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - */ - ext a1, rINST, 8, 4 # a1 <- A - srl a2, rINST, 12 # a2 <- B - GET_VREG_DOUBLE f0, a2 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - - trunc.l.d f0, f0 -/* File: mips64/fcvtFooter.S */ - /* - * Stores a specified register containing the result of conversion - * from or to a floating-point type and jumps to the next instruction. - * - * Expects a1 to contain the destination Dalvik register number. - * a1 is set up by fcvtHeader.S. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - * - * Note that this file can't be included after a break in other files - * and in those files its contents appear as a copy. - * See: float-to-int, float-to-long, double-to-int, double-to-long. - */ - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_DOUBLE f0, a1 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_double_to_float: /* 0x8c */ -/* File: mips64/op_double_to_float.S */ - /* - * Conversion from or to floating-point happens in a floating-point register. - * Therefore we load the input and store the output into or from a - * floating-point register irrespective of the type. - */ -/* File: mips64/fcvtHeader.S */ - /* - * Loads a specified register from vB. Used primarily for conversions - * from or to a floating-point type. - * - * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to - * store the result in vA and jump to the next instruction. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - */ - ext a1, rINST, 8, 4 # a1 <- A - srl a2, rINST, 12 # a2 <- B - GET_VREG_DOUBLE f0, a2 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - - cvt.s.d f0, f0 -/* File: mips64/fcvtFooter.S */ - /* - * Stores a specified register containing the result of conversion - * from or to a floating-point type and jumps to the next instruction. - * - * Expects a1 to contain the destination Dalvik register number. - * a1 is set up by fcvtHeader.S. - * - * For: int-to-float, int-to-double, long-to-float, long-to-double, - * float-to-int, float-to-long, float-to-double, double-to-int, - * double-to-long, double-to-float, neg-float, neg-double. - * - * Note that this file can't be included after a break in other files - * and in those files its contents appear as a copy. - * See: float-to-int, float-to-long, double-to-int, double-to-long. - */ - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_FLOAT f0, a1 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_byte: /* 0x8d */ -/* File: mips64/op_int_to_byte.S */ -/* File: mips64/unop.S */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "a0 = op a0". - * - * for: int-to-byte, int-to-char, int-to-short, - * not-int, neg-int - */ - /* unop vA, vB */ - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a3 # a0 <- vB - ext a2, rINST, 8, 4 # a2 <- A - # optional op - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - seb a0, a0 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_char: /* 0x8e */ -/* File: mips64/op_int_to_char.S */ -/* File: mips64/unop.S */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "a0 = op a0". - * - * for: int-to-byte, int-to-char, int-to-short, - * not-int, neg-int - */ - /* unop vA, vB */ - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a3 # a0 <- vB - ext a2, rINST, 8, 4 # a2 <- A - # optional op - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - and a0, a0, 0xffff # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_short: /* 0x8f */ -/* File: mips64/op_int_to_short.S */ -/* File: mips64/unop.S */ - /* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "a0 = op a0". - * - * for: int-to-byte, int-to-char, int-to-short, - * not-int, neg-int - */ - /* unop vA, vB */ - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a3 # a0 <- vB - ext a2, rINST, 8, 4 # a2 <- A - # optional op - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - seh a0, a0 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_add_int: /* 0x90 */ -/* File: mips64/op_add_int.S */ -/* File: mips64/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG a0, a2 # a0 <- vBB - GET_VREG a1, a3 # a1 <- vCC - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - addu a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_int: /* 0x91 */ -/* File: mips64/op_sub_int.S */ -/* File: mips64/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG a0, a2 # a0 <- vBB - GET_VREG a1, a3 # a1 <- vCC - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - subu a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int: /* 0x92 */ -/* File: mips64/op_mul_int.S */ -/* File: mips64/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG a0, a2 # a0 <- vBB - GET_VREG a1, a3 # a1 <- vCC - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - mul a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_div_int: /* 0x93 */ -/* File: mips64/op_div_int.S */ -/* File: mips64/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG a0, a2 # a0 <- vBB - GET_VREG a1, a3 # a1 <- vCC - .if 1 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - div a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int: /* 0x94 */ -/* File: mips64/op_rem_int.S */ -/* File: mips64/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG a0, a2 # a0 <- vBB - GET_VREG a1, a3 # a1 <- vCC - .if 1 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - mod a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_and_int: /* 0x95 */ -/* File: mips64/op_and_int.S */ -/* File: mips64/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG a0, a2 # a0 <- vBB - GET_VREG a1, a3 # a1 <- vCC - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - and a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_or_int: /* 0x96 */ -/* File: mips64/op_or_int.S */ -/* File: mips64/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG a0, a2 # a0 <- vBB - GET_VREG a1, a3 # a1 <- vCC - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - or a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int: /* 0x97 */ -/* File: mips64/op_xor_int.S */ -/* File: mips64/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG a0, a2 # a0 <- vBB - GET_VREG a1, a3 # a1 <- vCC - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - xor a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_shl_int: /* 0x98 */ -/* File: mips64/op_shl_int.S */ -/* File: mips64/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG a0, a2 # a0 <- vBB - GET_VREG a1, a3 # a1 <- vCC - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - sll a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_shr_int: /* 0x99 */ -/* File: mips64/op_shr_int.S */ -/* File: mips64/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG a0, a2 # a0 <- vBB - GET_VREG a1, a3 # a1 <- vCC - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - sra a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_int: /* 0x9a */ -/* File: mips64/op_ushr_int.S */ -/* File: mips64/binop.S */ - /* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG a0, a2 # a0 <- vBB - GET_VREG a1, a3 # a1 <- vCC - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - srl a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_add_long: /* 0x9b */ -/* File: mips64/op_add_long.S */ -/* File: mips64/binopWide.S */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, shl-long, shr-long, ushr-long - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_WIDE a0, a2 # a0 <- vBB - GET_VREG_WIDE a1, a3 # a1 <- vCC - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - daddu a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_long: /* 0x9c */ -/* File: mips64/op_sub_long.S */ -/* File: mips64/binopWide.S */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, shl-long, shr-long, ushr-long - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_WIDE a0, a2 # a0 <- vBB - GET_VREG_WIDE a1, a3 # a1 <- vCC - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - dsubu a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_long: /* 0x9d */ -/* File: mips64/op_mul_long.S */ -/* File: mips64/binopWide.S */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, shl-long, shr-long, ushr-long - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_WIDE a0, a2 # a0 <- vBB - GET_VREG_WIDE a1, a3 # a1 <- vCC - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - dmul a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_div_long: /* 0x9e */ -/* File: mips64/op_div_long.S */ -/* File: mips64/binopWide.S */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, shl-long, shr-long, ushr-long - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_WIDE a0, a2 # a0 <- vBB - GET_VREG_WIDE a1, a3 # a1 <- vCC - .if 1 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - ddiv a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_long: /* 0x9f */ -/* File: mips64/op_rem_long.S */ -/* File: mips64/binopWide.S */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, shl-long, shr-long, ushr-long - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_WIDE a0, a2 # a0 <- vBB - GET_VREG_WIDE a1, a3 # a1 <- vCC - .if 1 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - dmod a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_and_long: /* 0xa0 */ -/* File: mips64/op_and_long.S */ -/* File: mips64/binopWide.S */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, shl-long, shr-long, ushr-long - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_WIDE a0, a2 # a0 <- vBB - GET_VREG_WIDE a1, a3 # a1 <- vCC - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - and a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_or_long: /* 0xa1 */ -/* File: mips64/op_or_long.S */ -/* File: mips64/binopWide.S */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, shl-long, shr-long, ushr-long - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_WIDE a0, a2 # a0 <- vBB - GET_VREG_WIDE a1, a3 # a1 <- vCC - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - or a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_xor_long: /* 0xa2 */ -/* File: mips64/op_xor_long.S */ -/* File: mips64/binopWide.S */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, shl-long, shr-long, ushr-long - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_WIDE a0, a2 # a0 <- vBB - GET_VREG_WIDE a1, a3 # a1 <- vCC - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - xor a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_shl_long: /* 0xa3 */ -/* File: mips64/op_shl_long.S */ -/* File: mips64/binopWide.S */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, shl-long, shr-long, ushr-long - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_WIDE a0, a2 # a0 <- vBB - GET_VREG_WIDE a1, a3 # a1 <- vCC - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - dsll a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_shr_long: /* 0xa4 */ -/* File: mips64/op_shr_long.S */ -/* File: mips64/binopWide.S */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, shl-long, shr-long, ushr-long - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_WIDE a0, a2 # a0 <- vBB - GET_VREG_WIDE a1, a3 # a1 <- vCC - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - dsra a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_long: /* 0xa5 */ -/* File: mips64/op_ushr_long.S */ -/* File: mips64/binopWide.S */ - /* - * Generic 64-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vCC (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, - * xor-long, shl-long, shr-long, ushr-long - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_WIDE a0, a2 # a0 <- vBB - GET_VREG_WIDE a1, a3 # a1 <- vCC - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - dsrl a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a4 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_add_float: /* 0xa6 */ -/* File: mips64/op_add_float.S */ -/* File: mips64/fbinop.S */ - /*: - * Generic 32-bit floating-point operation. - * - * For: add-float, sub-float, mul-float, div-float. - * form: f0, f0, f1 - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_FLOAT f0, a2 # f0 <- vBB - GET_VREG_FLOAT f1, a3 # f1 <- vCC - add.s f0, f0, f1 # f0 <- f0 op f1 - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_FLOAT f0, a4 # vAA <- f0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_float: /* 0xa7 */ -/* File: mips64/op_sub_float.S */ -/* File: mips64/fbinop.S */ - /*: - * Generic 32-bit floating-point operation. - * - * For: add-float, sub-float, mul-float, div-float. - * form: f0, f0, f1 - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_FLOAT f0, a2 # f0 <- vBB - GET_VREG_FLOAT f1, a3 # f1 <- vCC - sub.s f0, f0, f1 # f0 <- f0 op f1 - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_FLOAT f0, a4 # vAA <- f0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_float: /* 0xa8 */ -/* File: mips64/op_mul_float.S */ -/* File: mips64/fbinop.S */ - /*: - * Generic 32-bit floating-point operation. - * - * For: add-float, sub-float, mul-float, div-float. - * form: f0, f0, f1 - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_FLOAT f0, a2 # f0 <- vBB - GET_VREG_FLOAT f1, a3 # f1 <- vCC - mul.s f0, f0, f1 # f0 <- f0 op f1 - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_FLOAT f0, a4 # vAA <- f0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_div_float: /* 0xa9 */ -/* File: mips64/op_div_float.S */ -/* File: mips64/fbinop.S */ - /*: - * Generic 32-bit floating-point operation. - * - * For: add-float, sub-float, mul-float, div-float. - * form: f0, f0, f1 - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_FLOAT f0, a2 # f0 <- vBB - GET_VREG_FLOAT f1, a3 # f1 <- vCC - div.s f0, f0, f1 # f0 <- f0 op f1 - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_FLOAT f0, a4 # vAA <- f0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_float: /* 0xaa */ -/* File: mips64/op_rem_float.S */ - /* rem-float vAA, vBB, vCC */ - .extern fmodf - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_FLOAT f12, a2 # f12 <- vBB - GET_VREG_FLOAT f13, a3 # f13 <- vCC - jal fmodf # f0 <- f12 op f13 - srl a4, rINST, 8 # a4 <- AA - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_FLOAT f0, a4 # vAA <- f0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_add_double: /* 0xab */ -/* File: mips64/op_add_double.S */ -/* File: mips64/fbinopWide.S */ - /*: - * Generic 64-bit floating-point operation. - * - * For: add-double, sub-double, mul-double, div-double. - * form: f0, f0, f1 - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_DOUBLE f0, a2 # f0 <- vBB - GET_VREG_DOUBLE f1, a3 # f1 <- vCC - add.d f0, f0, f1 # f0 <- f0 op f1 - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_DOUBLE f0, a4 # vAA <- f0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_double: /* 0xac */ -/* File: mips64/op_sub_double.S */ -/* File: mips64/fbinopWide.S */ - /*: - * Generic 64-bit floating-point operation. - * - * For: add-double, sub-double, mul-double, div-double. - * form: f0, f0, f1 - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_DOUBLE f0, a2 # f0 <- vBB - GET_VREG_DOUBLE f1, a3 # f1 <- vCC - sub.d f0, f0, f1 # f0 <- f0 op f1 - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_DOUBLE f0, a4 # vAA <- f0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_double: /* 0xad */ -/* File: mips64/op_mul_double.S */ -/* File: mips64/fbinopWide.S */ - /*: - * Generic 64-bit floating-point operation. - * - * For: add-double, sub-double, mul-double, div-double. - * form: f0, f0, f1 - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_DOUBLE f0, a2 # f0 <- vBB - GET_VREG_DOUBLE f1, a3 # f1 <- vCC - mul.d f0, f0, f1 # f0 <- f0 op f1 - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_DOUBLE f0, a4 # vAA <- f0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_div_double: /* 0xae */ -/* File: mips64/op_div_double.S */ -/* File: mips64/fbinopWide.S */ - /*: - * Generic 64-bit floating-point operation. - * - * For: add-double, sub-double, mul-double, div-double. - * form: f0, f0, f1 - */ - /* binop vAA, vBB, vCC */ - srl a4, rINST, 8 # a4 <- AA - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_DOUBLE f0, a2 # f0 <- vBB - GET_VREG_DOUBLE f1, a3 # f1 <- vCC - div.d f0, f0, f1 # f0 <- f0 op f1 - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_DOUBLE f0, a4 # vAA <- f0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_double: /* 0xaf */ -/* File: mips64/op_rem_double.S */ - /* rem-double vAA, vBB, vCC */ - .extern fmod - lbu a2, 2(rPC) # a2 <- BB - lbu a3, 3(rPC) # a3 <- CC - GET_VREG_DOUBLE f12, a2 # f12 <- vBB - GET_VREG_DOUBLE f13, a3 # f13 <- vCC - jal fmod # f0 <- f12 op f13 - srl a4, rINST, 8 # a4 <- AA - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_DOUBLE f0, a4 # vAA <- f0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_add_int_2addr: /* 0xb0 */ -/* File: mips64/op_add_int_2addr.S */ -/* File: mips64/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a2 # a0 <- vA - GET_VREG a1, a3 # a1 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - addu a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_int_2addr: /* 0xb1 */ -/* File: mips64/op_sub_int_2addr.S */ -/* File: mips64/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a2 # a0 <- vA - GET_VREG a1, a3 # a1 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - subu a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int_2addr: /* 0xb2 */ -/* File: mips64/op_mul_int_2addr.S */ -/* File: mips64/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a2 # a0 <- vA - GET_VREG a1, a3 # a1 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - mul a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_div_int_2addr: /* 0xb3 */ -/* File: mips64/op_div_int_2addr.S */ -/* File: mips64/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a2 # a0 <- vA - GET_VREG a1, a3 # a1 <- vB - .if 1 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - div a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int_2addr: /* 0xb4 */ -/* File: mips64/op_rem_int_2addr.S */ -/* File: mips64/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a2 # a0 <- vA - GET_VREG a1, a3 # a1 <- vB - .if 1 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - mod a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_and_int_2addr: /* 0xb5 */ -/* File: mips64/op_and_int_2addr.S */ -/* File: mips64/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a2 # a0 <- vA - GET_VREG a1, a3 # a1 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - and a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_or_int_2addr: /* 0xb6 */ -/* File: mips64/op_or_int_2addr.S */ -/* File: mips64/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a2 # a0 <- vA - GET_VREG a1, a3 # a1 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - or a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int_2addr: /* 0xb7 */ -/* File: mips64/op_xor_int_2addr.S */ -/* File: mips64/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a2 # a0 <- vA - GET_VREG a1, a3 # a1 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - xor a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_shl_int_2addr: /* 0xb8 */ -/* File: mips64/op_shl_int_2addr.S */ -/* File: mips64/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a2 # a0 <- vA - GET_VREG a1, a3 # a1 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - sll a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_shr_int_2addr: /* 0xb9 */ -/* File: mips64/op_shr_int_2addr.S */ -/* File: mips64/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a2 # a0 <- vA - GET_VREG a1, a3 # a1 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - sra a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_int_2addr: /* 0xba */ -/* File: mips64/op_ushr_int_2addr.S */ -/* File: mips64/binop2addr.S */ - /* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (INT_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a2 # a0 <- vA - GET_VREG a1, a3 # a1 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - srl a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_add_long_2addr: /* 0xbb */ -/* File: mips64/op_add_long_2addr.S */ -/* File: mips64/binopWide2addr.S */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_WIDE a0, a2 # a0 <- vA - GET_VREG_WIDE a1, a3 # a1 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - daddu a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_long_2addr: /* 0xbc */ -/* File: mips64/op_sub_long_2addr.S */ -/* File: mips64/binopWide2addr.S */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_WIDE a0, a2 # a0 <- vA - GET_VREG_WIDE a1, a3 # a1 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - dsubu a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_long_2addr: /* 0xbd */ -/* File: mips64/op_mul_long_2addr.S */ -/* File: mips64/binopWide2addr.S */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_WIDE a0, a2 # a0 <- vA - GET_VREG_WIDE a1, a3 # a1 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - dmul a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_div_long_2addr: /* 0xbe */ -/* File: mips64/op_div_long_2addr.S */ -/* File: mips64/binopWide2addr.S */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_WIDE a0, a2 # a0 <- vA - GET_VREG_WIDE a1, a3 # a1 <- vB - .if 1 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - ddiv a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_long_2addr: /* 0xbf */ -/* File: mips64/op_rem_long_2addr.S */ -/* File: mips64/binopWide2addr.S */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_WIDE a0, a2 # a0 <- vA - GET_VREG_WIDE a1, a3 # a1 <- vB - .if 1 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - dmod a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_and_long_2addr: /* 0xc0 */ -/* File: mips64/op_and_long_2addr.S */ -/* File: mips64/binopWide2addr.S */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_WIDE a0, a2 # a0 <- vA - GET_VREG_WIDE a1, a3 # a1 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - and a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_or_long_2addr: /* 0xc1 */ -/* File: mips64/op_or_long_2addr.S */ -/* File: mips64/binopWide2addr.S */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_WIDE a0, a2 # a0 <- vA - GET_VREG_WIDE a1, a3 # a1 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - or a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_xor_long_2addr: /* 0xc2 */ -/* File: mips64/op_xor_long_2addr.S */ -/* File: mips64/binopWide2addr.S */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_WIDE a0, a2 # a0 <- vA - GET_VREG_WIDE a1, a3 # a1 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - xor a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_shl_long_2addr: /* 0xc3 */ -/* File: mips64/op_shl_long_2addr.S */ -/* File: mips64/binopWide2addr.S */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_WIDE a0, a2 # a0 <- vA - GET_VREG_WIDE a1, a3 # a1 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - dsll a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_shr_long_2addr: /* 0xc4 */ -/* File: mips64/op_shr_long_2addr.S */ -/* File: mips64/binopWide2addr.S */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_WIDE a0, a2 # a0 <- vA - GET_VREG_WIDE a1, a3 # a1 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - dsra a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_long_2addr: /* 0xc5 */ -/* File: mips64/op_ushr_long_2addr.S */ -/* File: mips64/binopWide2addr.S */ - /* - * Generic 64-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be a MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * vB (a1). Useful for integer division and modulus. Note that we - * *don't* check for (LONG_MIN / -1) here, because the CPU handles it - * correctly. - * - * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, - * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, - * shl-long/2addr, shr-long/2addr, ushr-long/2addr - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_WIDE a0, a2 # a0 <- vA - GET_VREG_WIDE a1, a3 # a1 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - # optional op - dsrl a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_WIDE a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_add_float_2addr: /* 0xc6 */ -/* File: mips64/op_add_float_2addr.S */ -/* File: mips64/fbinop2addr.S */ - /*: - * Generic 32-bit "/2addr" floating-point operation. - * - * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr. - * form: f0, f0, f1 - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_FLOAT f0, a2 # f0 <- vA - GET_VREG_FLOAT f1, a3 # f1 <- vB - add.s f0, f0, f1 # f0 <- f0 op f1 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_FLOAT f0, a2 # vA <- f0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_float_2addr: /* 0xc7 */ -/* File: mips64/op_sub_float_2addr.S */ -/* File: mips64/fbinop2addr.S */ - /*: - * Generic 32-bit "/2addr" floating-point operation. - * - * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr. - * form: f0, f0, f1 - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_FLOAT f0, a2 # f0 <- vA - GET_VREG_FLOAT f1, a3 # f1 <- vB - sub.s f0, f0, f1 # f0 <- f0 op f1 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_FLOAT f0, a2 # vA <- f0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_float_2addr: /* 0xc8 */ -/* File: mips64/op_mul_float_2addr.S */ -/* File: mips64/fbinop2addr.S */ - /*: - * Generic 32-bit "/2addr" floating-point operation. - * - * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr. - * form: f0, f0, f1 - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_FLOAT f0, a2 # f0 <- vA - GET_VREG_FLOAT f1, a3 # f1 <- vB - mul.s f0, f0, f1 # f0 <- f0 op f1 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_FLOAT f0, a2 # vA <- f0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_div_float_2addr: /* 0xc9 */ -/* File: mips64/op_div_float_2addr.S */ -/* File: mips64/fbinop2addr.S */ - /*: - * Generic 32-bit "/2addr" floating-point operation. - * - * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr. - * form: f0, f0, f1 - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_FLOAT f0, a2 # f0 <- vA - GET_VREG_FLOAT f1, a3 # f1 <- vB - div.s f0, f0, f1 # f0 <- f0 op f1 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_FLOAT f0, a2 # vA <- f0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_float_2addr: /* 0xca */ -/* File: mips64/op_rem_float_2addr.S */ - /* rem-float/2addr vA, vB */ - .extern fmodf - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_FLOAT f12, a2 # f12 <- vA - GET_VREG_FLOAT f13, a3 # f13 <- vB - jal fmodf # f0 <- f12 op f13 - ext a2, rINST, 8, 4 # a2 <- A - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_FLOAT f0, a2 # vA <- f0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_add_double_2addr: /* 0xcb */ -/* File: mips64/op_add_double_2addr.S */ -/* File: mips64/fbinopWide2addr.S */ - /*: - * Generic 64-bit "/2addr" floating-point operation. - * - * For: add-double/2addr, sub-double/2addr, mul-double/2addr, div-double/2addr. - * form: f0, f0, f1 - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_DOUBLE f0, a2 # f0 <- vA - GET_VREG_DOUBLE f1, a3 # f1 <- vB - add.d f0, f0, f1 # f0 <- f0 op f1 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_DOUBLE f0, a2 # vA <- f0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_double_2addr: /* 0xcc */ -/* File: mips64/op_sub_double_2addr.S */ -/* File: mips64/fbinopWide2addr.S */ - /*: - * Generic 64-bit "/2addr" floating-point operation. - * - * For: add-double/2addr, sub-double/2addr, mul-double/2addr, div-double/2addr. - * form: f0, f0, f1 - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_DOUBLE f0, a2 # f0 <- vA - GET_VREG_DOUBLE f1, a3 # f1 <- vB - sub.d f0, f0, f1 # f0 <- f0 op f1 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_DOUBLE f0, a2 # vA <- f0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_double_2addr: /* 0xcd */ -/* File: mips64/op_mul_double_2addr.S */ -/* File: mips64/fbinopWide2addr.S */ - /*: - * Generic 64-bit "/2addr" floating-point operation. - * - * For: add-double/2addr, sub-double/2addr, mul-double/2addr, div-double/2addr. - * form: f0, f0, f1 - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_DOUBLE f0, a2 # f0 <- vA - GET_VREG_DOUBLE f1, a3 # f1 <- vB - mul.d f0, f0, f1 # f0 <- f0 op f1 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_DOUBLE f0, a2 # vA <- f0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_div_double_2addr: /* 0xce */ -/* File: mips64/op_div_double_2addr.S */ -/* File: mips64/fbinopWide2addr.S */ - /*: - * Generic 64-bit "/2addr" floating-point operation. - * - * For: add-double/2addr, sub-double/2addr, mul-double/2addr, div-double/2addr. - * form: f0, f0, f1 - */ - /* binop/2addr vA, vB */ - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_DOUBLE f0, a2 # f0 <- vA - GET_VREG_DOUBLE f1, a3 # f1 <- vB - div.d f0, f0, f1 # f0 <- f0 op f1 - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_DOUBLE f0, a2 # vA <- f0 - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_double_2addr: /* 0xcf */ -/* File: mips64/op_rem_double_2addr.S */ - /* rem-double/2addr vA, vB */ - .extern fmod - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG_DOUBLE f12, a2 # f12 <- vA - GET_VREG_DOUBLE f13, a3 # f13 <- vB - jal fmod # f0 <- f12 op f13 - ext a2, rINST, 8, 4 # a2 <- A - FETCH_ADVANCE_INST 1 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG_DOUBLE f0, a2 # vA <- f0 - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_add_int_lit16: /* 0xd0 */ -/* File: mips64/op_add_int_lit16.S */ -/* File: mips64/binopLit16.S */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * CCCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - lh a1, 2(rPC) # a1 <- sign-extended CCCC - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a3 # a0 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - addu a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_rsub_int: /* 0xd1 */ -/* File: mips64/op_rsub_int.S */ -/* File: mips64/binopLit16.S */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * CCCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - lh a1, 2(rPC) # a1 <- sign-extended CCCC - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a3 # a0 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - subu a0, a1, a0 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int_lit16: /* 0xd2 */ -/* File: mips64/op_mul_int_lit16.S */ -/* File: mips64/binopLit16.S */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * CCCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - lh a1, 2(rPC) # a1 <- sign-extended CCCC - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a3 # a0 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - mul a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_div_int_lit16: /* 0xd3 */ -/* File: mips64/op_div_int_lit16.S */ -/* File: mips64/binopLit16.S */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * CCCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - lh a1, 2(rPC) # a1 <- sign-extended CCCC - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a3 # a0 <- vB - .if 1 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - div a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int_lit16: /* 0xd4 */ -/* File: mips64/op_rem_int_lit16.S */ -/* File: mips64/binopLit16.S */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * CCCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - lh a1, 2(rPC) # a1 <- sign-extended CCCC - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a3 # a0 <- vB - .if 1 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - mod a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_and_int_lit16: /* 0xd5 */ -/* File: mips64/op_and_int_lit16.S */ -/* File: mips64/binopLit16.S */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * CCCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - lh a1, 2(rPC) # a1 <- sign-extended CCCC - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a3 # a0 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - and a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_or_int_lit16: /* 0xd6 */ -/* File: mips64/op_or_int_lit16.S */ -/* File: mips64/binopLit16.S */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * CCCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - lh a1, 2(rPC) # a1 <- sign-extended CCCC - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a3 # a0 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - or a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int_lit16: /* 0xd7 */ -/* File: mips64/op_xor_int_lit16.S */ -/* File: mips64/binopLit16.S */ - /* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * CCCC (a1). Useful for integer division and modulus. - * - * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, - * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - lh a1, 2(rPC) # a1 <- sign-extended CCCC - ext a2, rINST, 8, 4 # a2 <- A - ext a3, rINST, 12, 4 # a3 <- B - GET_VREG a0, a3 # a0 <- vB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - xor a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_add_int_lit8: /* 0xd8 */ -/* File: mips64/op_add_int_lit8.S */ -/* File: mips64/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * CC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - lbu a3, 2(rPC) # a3 <- BB - lb a1, 3(rPC) # a1 <- sign-extended CC - srl a2, rINST, 8 # a2 <- AA - GET_VREG a0, a3 # a0 <- vBB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - addu a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_rsub_int_lit8: /* 0xd9 */ -/* File: mips64/op_rsub_int_lit8.S */ -/* File: mips64/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * CC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - lbu a3, 2(rPC) # a3 <- BB - lb a1, 3(rPC) # a1 <- sign-extended CC - srl a2, rINST, 8 # a2 <- AA - GET_VREG a0, a3 # a0 <- vBB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - subu a0, a1, a0 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int_lit8: /* 0xda */ -/* File: mips64/op_mul_int_lit8.S */ -/* File: mips64/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * CC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - lbu a3, 2(rPC) # a3 <- BB - lb a1, 3(rPC) # a1 <- sign-extended CC - srl a2, rINST, 8 # a2 <- AA - GET_VREG a0, a3 # a0 <- vBB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - mul a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_div_int_lit8: /* 0xdb */ -/* File: mips64/op_div_int_lit8.S */ -/* File: mips64/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * CC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - lbu a3, 2(rPC) # a3 <- BB - lb a1, 3(rPC) # a1 <- sign-extended CC - srl a2, rINST, 8 # a2 <- AA - GET_VREG a0, a3 # a0 <- vBB - .if 1 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - div a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int_lit8: /* 0xdc */ -/* File: mips64/op_rem_int_lit8.S */ -/* File: mips64/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * CC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - lbu a3, 2(rPC) # a3 <- BB - lb a1, 3(rPC) # a1 <- sign-extended CC - srl a2, rINST, 8 # a2 <- AA - GET_VREG a0, a3 # a0 <- vBB - .if 1 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - mod a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_and_int_lit8: /* 0xdd */ -/* File: mips64/op_and_int_lit8.S */ -/* File: mips64/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * CC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - lbu a3, 2(rPC) # a3 <- BB - lb a1, 3(rPC) # a1 <- sign-extended CC - srl a2, rINST, 8 # a2 <- AA - GET_VREG a0, a3 # a0 <- vBB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - and a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_or_int_lit8: /* 0xde */ -/* File: mips64/op_or_int_lit8.S */ -/* File: mips64/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * CC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - lbu a3, 2(rPC) # a3 <- BB - lb a1, 3(rPC) # a1 <- sign-extended CC - srl a2, rINST, 8 # a2 <- AA - GET_VREG a0, a3 # a0 <- vBB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - or a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int_lit8: /* 0xdf */ -/* File: mips64/op_xor_int_lit8.S */ -/* File: mips64/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * CC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - lbu a3, 2(rPC) # a3 <- BB - lb a1, 3(rPC) # a1 <- sign-extended CC - srl a2, rINST, 8 # a2 <- AA - GET_VREG a0, a3 # a0 <- vBB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - xor a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_shl_int_lit8: /* 0xe0 */ -/* File: mips64/op_shl_int_lit8.S */ -/* File: mips64/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * CC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - lbu a3, 2(rPC) # a3 <- BB - lb a1, 3(rPC) # a1 <- sign-extended CC - srl a2, rINST, 8 # a2 <- AA - GET_VREG a0, a3 # a0 <- vBB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - sll a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_shr_int_lit8: /* 0xe1 */ -/* File: mips64/op_shr_int_lit8.S */ -/* File: mips64/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * CC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - lbu a3, 2(rPC) # a3 <- BB - lb a1, 3(rPC) # a1 <- sign-extended CC - srl a2, rINST, 8 # a2 <- AA - GET_VREG a0, a3 # a0 <- vBB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - sra a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_int_lit8: /* 0xe2 */ -/* File: mips64/op_ushr_int_lit8.S */ -/* File: mips64/binopLit8.S */ - /* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = a0 op a1". - * This could be an MIPS instruction or a function call. (If the result - * comes back in a register other than a0, you can override "result".) - * - * If "chkzero" is set to 1, we perform a divide-by-zero check on - * CC (a1). Useful for integer division and modulus. - * - * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, - * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - lbu a3, 2(rPC) # a3 <- BB - lb a1, 3(rPC) # a1 <- sign-extended CC - srl a2, rINST, 8 # a2 <- AA - GET_VREG a0, a3 # a0 <- vBB - .if 0 - beqz a1, common_errDivideByZero # is second operand zero? - .endif - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - # optional op - srl a0, a0, a1 # a0 <- op, a0-a3 changed - GET_INST_OPCODE v0 # extract opcode from rINST - SET_VREG a0, a2 # vAA <- a0 - GOTO_OPCODE v0 # jump to next instruction - - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_quick: /* 0xe3 */ -/* File: mips64/op_iget_quick.S */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset//CCCC */ - srl a2, rINST, 12 # a2 <- B - lhu a1, 2(rPC) # a1 <- field byte offset - GET_VREG_U a3, a2 # a3 <- object we're operating on - ext a4, rINST, 8, 4 # a4 <- A - daddu a1, a1, a3 - beqz a3, common_errNullObject # object was null - lw a0, 0(a1) # a0 <- obj.field - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - SET_VREG a0, a4 # fp[A] <- a0 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iget_wide_quick: /* 0xe4 */ -/* File: mips64/op_iget_wide_quick.S */ - /* iget-wide-quick vA, vB, offset//CCCC */ - srl a2, rINST, 12 # a2 <- B - lhu a4, 2(rPC) # a4 <- field byte offset - GET_VREG_U a3, a2 # a3 <- object we're operating on - ext a2, rINST, 8, 4 # a2 <- A - beqz a3, common_errNullObject # object was null - daddu a4, a3, a4 # create direct pointer - lw a0, 0(a4) - lw a1, 4(a4) - dinsu a0, a1, 32, 32 - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - SET_VREG_WIDE a0, a2 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iget_object_quick: /* 0xe5 */ -/* File: mips64/op_iget_object_quick.S */ - /* For: iget-object-quick */ - /* op vA, vB, offset//CCCC */ - .extern artIGetObjectFromMterp - srl a2, rINST, 12 # a2 <- B - lhu a1, 2(rPC) # a1 <- field byte offset - EXPORT_PC - GET_VREG_U a0, a2 # a0 <- object we're operating on - jal artIGetObjectFromMterp # (obj, offset) - ld a3, THREAD_EXCEPTION_OFFSET(rSELF) - ext a2, rINST, 8, 4 # a2 <- A - PREFETCH_INST 2 - bnez a3, MterpPossibleException # bail out - SET_VREG_OBJECT v0, a2 # fp[A] <- v0 - ADVANCE 2 # advance rPC - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_quick: /* 0xe6 */ -/* File: mips64/op_iput_quick.S */ - /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */ - /* op vA, vB, offset//CCCC */ - srl a2, rINST, 12 # a2 <- B - lhu a1, 2(rPC) # a1 <- field byte offset - GET_VREG_U a3, a2 # a3 <- fp[B], the object pointer - ext a2, rINST, 8, 4 # a2 <- A - beqz a3, common_errNullObject # object was null - GET_VREG a0, a2 # a0 <- fp[A] - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - daddu a1, a1, a3 - sw a0, 0(a1) # obj.field <- a0 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_wide_quick: /* 0xe7 */ -/* File: mips64/op_iput_wide_quick.S */ - /* iput-wide-quick vA, vB, offset//CCCC */ - srl a2, rINST, 12 # a2 <- B - lhu a3, 2(rPC) # a3 <- field byte offset - GET_VREG_U a2, a2 # a2 <- fp[B], the object pointer - ext a0, rINST, 8, 4 # a0 <- A - beqz a2, common_errNullObject # object was null - GET_VREG_WIDE a0, a0 # a0 <- fp[A] - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - daddu a1, a2, a3 # create a direct pointer - sw a0, 0(a1) - dsrl32 a0, a0, 0 - sw a0, 4(a1) - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_iput_object_quick: /* 0xe8 */ -/* File: mips64/op_iput_object_quick.S */ - .extern MterpIputObjectQuick - EXPORT_PC - daddu a0, rFP, OFF_FP_SHADOWFRAME - move a1, rPC - move a2, rINST - jal MterpIputObjectQuick - beqzc v0, MterpException - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual_quick: /* 0xe9 */ -/* File: mips64/op_invoke_virtual_quick.S */ -/* File: mips64/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtualQuick - .extern MterpShouldSwitchInterpreters - EXPORT_PC - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - jal MterpInvokeVirtualQuick - beqzc v0, MterpException - FETCH_ADVANCE_INST 3 - jal MterpShouldSwitchInterpreters - bnezc v0, MterpFallback - GET_INST_OPCODE v0 - GOTO_OPCODE v0 - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual_range_quick: /* 0xea */ -/* File: mips64/op_invoke_virtual_range_quick.S */ -/* File: mips64/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtualQuickRange - .extern MterpShouldSwitchInterpreters - EXPORT_PC - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - jal MterpInvokeVirtualQuickRange - beqzc v0, MterpException - FETCH_ADVANCE_INST 3 - jal MterpShouldSwitchInterpreters - bnezc v0, MterpFallback - GET_INST_OPCODE v0 - GOTO_OPCODE v0 - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_boolean_quick: /* 0xeb */ -/* File: mips64/op_iput_boolean_quick.S */ -/* File: mips64/op_iput_quick.S */ - /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */ - /* op vA, vB, offset//CCCC */ - srl a2, rINST, 12 # a2 <- B - lhu a1, 2(rPC) # a1 <- field byte offset - GET_VREG_U a3, a2 # a3 <- fp[B], the object pointer - ext a2, rINST, 8, 4 # a2 <- A - beqz a3, common_errNullObject # object was null - GET_VREG a0, a2 # a0 <- fp[A] - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - daddu a1, a1, a3 - sb a0, 0(a1) # obj.field <- a0 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_byte_quick: /* 0xec */ -/* File: mips64/op_iput_byte_quick.S */ -/* File: mips64/op_iput_quick.S */ - /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */ - /* op vA, vB, offset//CCCC */ - srl a2, rINST, 12 # a2 <- B - lhu a1, 2(rPC) # a1 <- field byte offset - GET_VREG_U a3, a2 # a3 <- fp[B], the object pointer - ext a2, rINST, 8, 4 # a2 <- A - beqz a3, common_errNullObject # object was null - GET_VREG a0, a2 # a0 <- fp[A] - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - daddu a1, a1, a3 - sb a0, 0(a1) # obj.field <- a0 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_char_quick: /* 0xed */ -/* File: mips64/op_iput_char_quick.S */ -/* File: mips64/op_iput_quick.S */ - /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */ - /* op vA, vB, offset//CCCC */ - srl a2, rINST, 12 # a2 <- B - lhu a1, 2(rPC) # a1 <- field byte offset - GET_VREG_U a3, a2 # a3 <- fp[B], the object pointer - ext a2, rINST, 8, 4 # a2 <- A - beqz a3, common_errNullObject # object was null - GET_VREG a0, a2 # a0 <- fp[A] - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - daddu a1, a1, a3 - sh a0, 0(a1) # obj.field <- a0 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_short_quick: /* 0xee */ -/* File: mips64/op_iput_short_quick.S */ -/* File: mips64/op_iput_quick.S */ - /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */ - /* op vA, vB, offset//CCCC */ - srl a2, rINST, 12 # a2 <- B - lhu a1, 2(rPC) # a1 <- field byte offset - GET_VREG_U a3, a2 # a3 <- fp[B], the object pointer - ext a2, rINST, 8, 4 # a2 <- A - beqz a3, common_errNullObject # object was null - GET_VREG a0, a2 # a0 <- fp[A] - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - daddu a1, a1, a3 - sh a0, 0(a1) # obj.field <- a0 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_boolean_quick: /* 0xef */ -/* File: mips64/op_iget_boolean_quick.S */ -/* File: mips64/op_iget_quick.S */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset//CCCC */ - srl a2, rINST, 12 # a2 <- B - lhu a1, 2(rPC) # a1 <- field byte offset - GET_VREG_U a3, a2 # a3 <- object we're operating on - ext a4, rINST, 8, 4 # a4 <- A - daddu a1, a1, a3 - beqz a3, common_errNullObject # object was null - lbu a0, 0(a1) # a0 <- obj.field - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - SET_VREG a0, a4 # fp[A] <- a0 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_byte_quick: /* 0xf0 */ -/* File: mips64/op_iget_byte_quick.S */ -/* File: mips64/op_iget_quick.S */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset//CCCC */ - srl a2, rINST, 12 # a2 <- B - lhu a1, 2(rPC) # a1 <- field byte offset - GET_VREG_U a3, a2 # a3 <- object we're operating on - ext a4, rINST, 8, 4 # a4 <- A - daddu a1, a1, a3 - beqz a3, common_errNullObject # object was null - lb a0, 0(a1) # a0 <- obj.field - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - SET_VREG a0, a4 # fp[A] <- a0 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_char_quick: /* 0xf1 */ -/* File: mips64/op_iget_char_quick.S */ -/* File: mips64/op_iget_quick.S */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset//CCCC */ - srl a2, rINST, 12 # a2 <- B - lhu a1, 2(rPC) # a1 <- field byte offset - GET_VREG_U a3, a2 # a3 <- object we're operating on - ext a4, rINST, 8, 4 # a4 <- A - daddu a1, a1, a3 - beqz a3, common_errNullObject # object was null - lhu a0, 0(a1) # a0 <- obj.field - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - SET_VREG a0, a4 # fp[A] <- a0 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_short_quick: /* 0xf2 */ -/* File: mips64/op_iget_short_quick.S */ -/* File: mips64/op_iget_quick.S */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset//CCCC */ - srl a2, rINST, 12 # a2 <- B - lhu a1, 2(rPC) # a1 <- field byte offset - GET_VREG_U a3, a2 # a3 <- object we're operating on - ext a4, rINST, 8, 4 # a4 <- A - daddu a1, a1, a3 - beqz a3, common_errNullObject # object was null - lh a0, 0(a1) # a0 <- obj.field - FETCH_ADVANCE_INST 2 # advance rPC, load rINST - SET_VREG a0, a4 # fp[A] <- a0 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f3: /* 0xf3 */ -/* File: mips64/op_unused_f3.S */ -/* File: mips64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f4: /* 0xf4 */ -/* File: mips64/op_unused_f4.S */ -/* File: mips64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f5: /* 0xf5 */ -/* File: mips64/op_unused_f5.S */ -/* File: mips64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f6: /* 0xf6 */ -/* File: mips64/op_unused_f6.S */ -/* File: mips64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f7: /* 0xf7 */ -/* File: mips64/op_unused_f7.S */ -/* File: mips64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f8: /* 0xf8 */ -/* File: mips64/op_unused_f8.S */ -/* File: mips64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f9: /* 0xf9 */ -/* File: mips64/op_unused_f9.S */ -/* File: mips64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - b MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_polymorphic: /* 0xfa */ -/* File: mips64/op_invoke_polymorphic.S */ -/* File: mips64/invoke_polymorphic.S */ - /* - * invoke-polymorphic handler wrapper. - */ - /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ - .extern MterpInvokePolymorphic - .extern MterpShouldSwitchInterpreters - EXPORT_PC - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - jal MterpInvokePolymorphic - beqzc v0, MterpException - FETCH_ADVANCE_INST 4 - jal MterpShouldSwitchInterpreters - bnezc v0, MterpFallback - GET_INST_OPCODE v0 - GOTO_OPCODE v0 - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_polymorphic_range: /* 0xfb */ -/* File: mips64/op_invoke_polymorphic_range.S */ -/* File: mips64/invoke_polymorphic.S */ - /* - * invoke-polymorphic handler wrapper. - */ - /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ - .extern MterpInvokePolymorphicRange - .extern MterpShouldSwitchInterpreters - EXPORT_PC - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - jal MterpInvokePolymorphicRange - beqzc v0, MterpException - FETCH_ADVANCE_INST 4 - jal MterpShouldSwitchInterpreters - bnezc v0, MterpFallback - GET_INST_OPCODE v0 - GOTO_OPCODE v0 - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_custom: /* 0xfc */ -/* File: mips64/op_invoke_custom.S */ -/* File: mips64/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeCustom - .extern MterpShouldSwitchInterpreters - EXPORT_PC - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - jal MterpInvokeCustom - beqzc v0, MterpException - FETCH_ADVANCE_INST 3 - jal MterpShouldSwitchInterpreters - bnezc v0, MterpFallback - GET_INST_OPCODE v0 - GOTO_OPCODE v0 - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_custom_range: /* 0xfd */ -/* File: mips64/op_invoke_custom_range.S */ -/* File: mips64/invoke.S */ - /* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeCustomRange - .extern MterpShouldSwitchInterpreters - EXPORT_PC - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - move a3, rINST - jal MterpInvokeCustomRange - beqzc v0, MterpException - FETCH_ADVANCE_INST 3 - jal MterpShouldSwitchInterpreters - bnezc v0, MterpFallback - GET_INST_OPCODE v0 - GOTO_OPCODE v0 - - -/* ------------------------------ */ - .balign 128 -.L_op_const_method_handle: /* 0xfe */ -/* File: mips64/op_const_method_handle.S */ -/* File: mips64/const.S */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstMethodHandle - EXPORT_PC - lhu a0, 2(rPC) # a0 <- BBBB - srl a1, rINST, 8 # a1 <- AA - daddu a2, rFP, OFF_FP_SHADOWFRAME - move a3, rSELF - jal MterpConstMethodHandle # (index, tgt_reg, shadow_frame, self) - PREFETCH_INST 2 # load rINST - bnez v0, MterpPossibleException # let reference interpreter deal with it. - ADVANCE 2 # advance rPC - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - - -/* ------------------------------ */ - .balign 128 -.L_op_const_method_type: /* 0xff */ -/* File: mips64/op_const_method_type.S */ -/* File: mips64/const.S */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstMethodType - EXPORT_PC - lhu a0, 2(rPC) # a0 <- BBBB - srl a1, rINST, 8 # a1 <- AA - daddu a2, rFP, OFF_FP_SHADOWFRAME - move a3, rSELF - jal MterpConstMethodType # (index, tgt_reg, shadow_frame, self) - PREFETCH_INST 2 # load rINST - bnez v0, MterpPossibleException # let reference interpreter deal with it. - ADVANCE 2 # advance rPC - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - - - .balign 128 -/* File: mips64/instruction_end.S */ - - .global artMterpAsmInstructionEnd -artMterpAsmInstructionEnd: - - -/* - * =========================================================================== - * Sister implementations - * =========================================================================== - */ -/* File: mips64/instruction_start_sister.S */ - - .global artMterpAsmSisterStart - .text - .balign 4 -artMterpAsmSisterStart: - -/* File: mips64/instruction_end_sister.S */ - - .global artMterpAsmSisterEnd -artMterpAsmSisterEnd: - -/* File: mips64/instruction_start_alt.S */ - - .global artMterpAsmAltInstructionStart -artMterpAsmAltInstructionStart = .L_ALT_op_nop - .text - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_nop: /* 0x00 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (0 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move: /* 0x01 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (1 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_from16: /* 0x02 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (2 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_16: /* 0x03 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (3 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_wide: /* 0x04 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (4 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_wide_from16: /* 0x05 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (5 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_wide_16: /* 0x06 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (6 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_object: /* 0x07 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (7 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_object_from16: /* 0x08 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (8 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_object_16: /* 0x09 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (9 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_result: /* 0x0a */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (10 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_result_wide: /* 0x0b */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (11 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_result_object: /* 0x0c */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (12 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_exception: /* 0x0d */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (13 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_void: /* 0x0e */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (14 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return: /* 0x0f */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (15 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_wide: /* 0x10 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (16 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_object: /* 0x11 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (17 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_4: /* 0x12 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (18 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_16: /* 0x13 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (19 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const: /* 0x14 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (20 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_high16: /* 0x15 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (21 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide_16: /* 0x16 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (22 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide_32: /* 0x17 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (23 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide: /* 0x18 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (24 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide_high16: /* 0x19 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (25 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_string: /* 0x1a */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (26 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_string_jumbo: /* 0x1b */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (27 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_class: /* 0x1c */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (28 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_monitor_enter: /* 0x1d */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (29 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_monitor_exit: /* 0x1e */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (30 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_check_cast: /* 0x1f */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (31 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_instance_of: /* 0x20 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (32 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_array_length: /* 0x21 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (33 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_new_instance: /* 0x22 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (34 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_new_array: /* 0x23 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (35 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_filled_new_array: /* 0x24 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (36 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_filled_new_array_range: /* 0x25 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (37 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_fill_array_data: /* 0x26 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (38 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_throw: /* 0x27 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (39 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_goto: /* 0x28 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (40 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_goto_16: /* 0x29 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (41 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_goto_32: /* 0x2a */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (42 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_packed_switch: /* 0x2b */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (43 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sparse_switch: /* 0x2c */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (44 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpl_float: /* 0x2d */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (45 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpg_float: /* 0x2e */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (46 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpl_double: /* 0x2f */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (47 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpg_double: /* 0x30 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (48 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmp_long: /* 0x31 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (49 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_eq: /* 0x32 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (50 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_ne: /* 0x33 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (51 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_lt: /* 0x34 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (52 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_ge: /* 0x35 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (53 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_gt: /* 0x36 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (54 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_le: /* 0x37 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (55 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_eqz: /* 0x38 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (56 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_nez: /* 0x39 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (57 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_ltz: /* 0x3a */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (58 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_gez: /* 0x3b */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (59 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_gtz: /* 0x3c */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (60 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_lez: /* 0x3d */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (61 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_3e: /* 0x3e */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (62 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_3f: /* 0x3f */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (63 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_40: /* 0x40 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (64 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_41: /* 0x41 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (65 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_42: /* 0x42 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (66 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_43: /* 0x43 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (67 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget: /* 0x44 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (68 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_wide: /* 0x45 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (69 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_object: /* 0x46 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (70 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_boolean: /* 0x47 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (71 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_byte: /* 0x48 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (72 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_char: /* 0x49 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (73 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_short: /* 0x4a */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (74 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput: /* 0x4b */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (75 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_wide: /* 0x4c */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (76 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_object: /* 0x4d */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (77 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_boolean: /* 0x4e */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (78 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_byte: /* 0x4f */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (79 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_char: /* 0x50 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (80 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_short: /* 0x51 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (81 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget: /* 0x52 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (82 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_wide: /* 0x53 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (83 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_object: /* 0x54 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (84 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_boolean: /* 0x55 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (85 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_byte: /* 0x56 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (86 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_char: /* 0x57 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (87 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_short: /* 0x58 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (88 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput: /* 0x59 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (89 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_wide: /* 0x5a */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (90 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_object: /* 0x5b */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (91 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_boolean: /* 0x5c */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (92 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_byte: /* 0x5d */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (93 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_char: /* 0x5e */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (94 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_short: /* 0x5f */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (95 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget: /* 0x60 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (96 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_wide: /* 0x61 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (97 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_object: /* 0x62 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (98 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_boolean: /* 0x63 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (99 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_byte: /* 0x64 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (100 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_char: /* 0x65 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (101 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_short: /* 0x66 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (102 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput: /* 0x67 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (103 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_wide: /* 0x68 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (104 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_object: /* 0x69 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (105 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_boolean: /* 0x6a */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (106 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_byte: /* 0x6b */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (107 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_char: /* 0x6c */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (108 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_short: /* 0x6d */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (109 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual: /* 0x6e */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (110 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_super: /* 0x6f */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (111 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_direct: /* 0x70 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (112 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_static: /* 0x71 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (113 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_interface: /* 0x72 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (114 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_void_no_barrier: /* 0x73 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (115 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual_range: /* 0x74 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (116 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_super_range: /* 0x75 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (117 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_direct_range: /* 0x76 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (118 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_static_range: /* 0x77 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (119 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_interface_range: /* 0x78 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (120 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_79: /* 0x79 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (121 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_7a: /* 0x7a */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (122 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_int: /* 0x7b */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (123 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_not_int: /* 0x7c */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (124 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_long: /* 0x7d */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (125 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_not_long: /* 0x7e */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (126 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_float: /* 0x7f */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (127 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_double: /* 0x80 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (128 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_long: /* 0x81 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (129 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_float: /* 0x82 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (130 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_double: /* 0x83 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (131 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_long_to_int: /* 0x84 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (132 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_long_to_float: /* 0x85 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (133 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_long_to_double: /* 0x86 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (134 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_float_to_int: /* 0x87 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (135 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_float_to_long: /* 0x88 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (136 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_float_to_double: /* 0x89 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (137 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_double_to_int: /* 0x8a */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (138 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_double_to_long: /* 0x8b */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (139 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_double_to_float: /* 0x8c */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (140 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_byte: /* 0x8d */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (141 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_char: /* 0x8e */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (142 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_short: /* 0x8f */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (143 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int: /* 0x90 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (144 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_int: /* 0x91 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (145 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int: /* 0x92 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (146 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int: /* 0x93 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (147 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int: /* 0x94 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (148 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int: /* 0x95 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (149 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int: /* 0x96 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (150 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int: /* 0x97 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (151 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_int: /* 0x98 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (152 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_int: /* 0x99 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (153 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_int: /* 0x9a */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (154 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_long: /* 0x9b */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (155 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_long: /* 0x9c */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (156 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_long: /* 0x9d */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (157 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_long: /* 0x9e */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (158 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_long: /* 0x9f */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (159 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_long: /* 0xa0 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (160 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_long: /* 0xa1 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (161 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_long: /* 0xa2 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (162 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_long: /* 0xa3 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (163 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_long: /* 0xa4 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (164 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_long: /* 0xa5 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (165 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_float: /* 0xa6 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (166 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_float: /* 0xa7 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (167 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_float: /* 0xa8 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (168 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_float: /* 0xa9 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (169 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_float: /* 0xaa */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (170 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_double: /* 0xab */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (171 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_double: /* 0xac */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (172 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_double: /* 0xad */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (173 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_double: /* 0xae */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (174 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_double: /* 0xaf */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (175 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int_2addr: /* 0xb0 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (176 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_int_2addr: /* 0xb1 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (177 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int_2addr: /* 0xb2 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (178 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int_2addr: /* 0xb3 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (179 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int_2addr: /* 0xb4 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (180 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int_2addr: /* 0xb5 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (181 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int_2addr: /* 0xb6 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (182 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int_2addr: /* 0xb7 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (183 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_int_2addr: /* 0xb8 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (184 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_int_2addr: /* 0xb9 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (185 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_int_2addr: /* 0xba */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (186 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_long_2addr: /* 0xbb */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (187 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_long_2addr: /* 0xbc */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (188 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_long_2addr: /* 0xbd */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (189 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_long_2addr: /* 0xbe */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (190 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_long_2addr: /* 0xbf */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (191 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_long_2addr: /* 0xc0 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (192 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_long_2addr: /* 0xc1 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (193 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_long_2addr: /* 0xc2 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (194 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_long_2addr: /* 0xc3 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (195 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_long_2addr: /* 0xc4 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (196 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_long_2addr: /* 0xc5 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (197 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_float_2addr: /* 0xc6 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (198 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_float_2addr: /* 0xc7 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (199 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_float_2addr: /* 0xc8 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (200 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_float_2addr: /* 0xc9 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (201 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_float_2addr: /* 0xca */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (202 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_double_2addr: /* 0xcb */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (203 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_double_2addr: /* 0xcc */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (204 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_double_2addr: /* 0xcd */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (205 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_double_2addr: /* 0xce */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (206 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_double_2addr: /* 0xcf */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (207 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int_lit16: /* 0xd0 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (208 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rsub_int: /* 0xd1 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (209 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int_lit16: /* 0xd2 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (210 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int_lit16: /* 0xd3 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (211 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int_lit16: /* 0xd4 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (212 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int_lit16: /* 0xd5 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (213 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int_lit16: /* 0xd6 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (214 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int_lit16: /* 0xd7 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (215 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int_lit8: /* 0xd8 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (216 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rsub_int_lit8: /* 0xd9 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (217 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int_lit8: /* 0xda */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (218 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int_lit8: /* 0xdb */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (219 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int_lit8: /* 0xdc */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (220 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int_lit8: /* 0xdd */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (221 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int_lit8: /* 0xde */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (222 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int_lit8: /* 0xdf */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (223 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_int_lit8: /* 0xe0 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (224 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_int_lit8: /* 0xe1 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (225 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_int_lit8: /* 0xe2 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (226 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_quick: /* 0xe3 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (227 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_wide_quick: /* 0xe4 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (228 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_object_quick: /* 0xe5 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (229 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_quick: /* 0xe6 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (230 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_wide_quick: /* 0xe7 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (231 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_object_quick: /* 0xe8 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (232 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual_quick: /* 0xe9 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (233 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual_range_quick: /* 0xea */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (234 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_boolean_quick: /* 0xeb */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (235 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_byte_quick: /* 0xec */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (236 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_char_quick: /* 0xed */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (237 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_short_quick: /* 0xee */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (238 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_boolean_quick: /* 0xef */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (239 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_byte_quick: /* 0xf0 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (240 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_char_quick: /* 0xf1 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (241 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_short_quick: /* 0xf2 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (242 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f3: /* 0xf3 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (243 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f4: /* 0xf4 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (244 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f5: /* 0xf5 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (245 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f6: /* 0xf6 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (246 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f7: /* 0xf7 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (247 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f8: /* 0xf8 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (248 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f9: /* 0xf9 */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (249 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_polymorphic: /* 0xfa */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (250 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_polymorphic_range: /* 0xfb */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (251 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_custom: /* 0xfc */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (252 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_custom_range: /* 0xfd */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (253 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_method_handle: /* 0xfe */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (254 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_method_type: /* 0xff */ -/* File: mips64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Note that the call to MterpCheckBefore is done as a tail call. - */ - .extern MterpCheckBefore - REFRESH_IBASE - dla ra, artMterpAsmInstructionStart - dla t9, MterpCheckBefore - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rPC - daddu ra, ra, (255 * 128) # Addr of primary handler. - jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. - - .balign 128 -/* File: mips64/instruction_end_alt.S */ - - .global artMterpAsmAltInstructionEnd -artMterpAsmAltInstructionEnd: - -/* File: mips64/footer.S */ -/* - * We've detected a condition that will result in an exception, but the exception - * has not yet been thrown. Just bail out to the reference interpreter to deal with it. - * TUNING: for consistency, we may want to just go ahead and handle these here. - */ - - .extern MterpLogDivideByZeroException -common_errDivideByZero: - EXPORT_PC -#if MTERP_LOGGING - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - jal MterpLogDivideByZeroException -#endif - b MterpCommonFallback - - .extern MterpLogArrayIndexException -common_errArrayIndex: - EXPORT_PC -#if MTERP_LOGGING - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - jal MterpLogArrayIndexException -#endif - b MterpCommonFallback - - .extern MterpLogNullObjectException -common_errNullObject: - EXPORT_PC -#if MTERP_LOGGING - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - jal MterpLogNullObjectException -#endif - b MterpCommonFallback - -/* - * If we're here, something is out of the ordinary. If there is a pending - * exception, handle it. Otherwise, roll back and retry with the reference - * interpreter. - */ -MterpPossibleException: - ld a0, THREAD_EXCEPTION_OFFSET(rSELF) - beqzc a0, MterpFallback # If not, fall back to reference interpreter. - /* intentional fallthrough - handle pending exception. */ -/* - * On return from a runtime helper routine, we've found a pending exception. - * Can we handle it here - or need to bail out to caller? - * - */ - .extern MterpHandleException - .extern MterpShouldSwitchInterpreters -MterpException: - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - jal MterpHandleException # (self, shadow_frame) - beqzc v0, MterpExceptionReturn # no local catch, back to caller. - ld a0, OFF_FP_DEX_INSTRUCTIONS(rFP) - lwu a1, OFF_FP_DEX_PC(rFP) - REFRESH_IBASE - dlsa rPC, a1, a0, 1 # generate new dex_pc_ptr - /* Do we need to switch interpreters? */ - jal MterpShouldSwitchInterpreters - bnezc v0, MterpFallback - /* resume execution at catch block */ - EXPORT_PC - FETCH_INST - GET_INST_OPCODE v0 - GOTO_OPCODE v0 - /* NOTE: no fallthrough */ - -/* - * Common handling for branches with support for Jit profiling. - * On entry: - * rINST <= signed offset - * rPROFILE <= signed hotness countdown (expanded to 64 bits) - * - * We have quite a few different cases for branch profiling, OSR detection and - * suspend check support here. - * - * Taken backward branches: - * If profiling active, do hotness countdown and report if we hit zero. - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * Is there a pending suspend request? If so, suspend. - * - * Taken forward branches and not-taken backward branches: - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * - * Our most common case is expected to be a taken backward branch with active jit profiling, - * but no full OSR check and no pending suspend request. - * Next most common case is not-taken branch with no full OSR check. - * - */ -MterpCommonTakenBranchNoFlags: - bgtzc rINST, .L_forward_branch # don't add forward branches to hotness -/* - * We need to subtract 1 from positive values and we should not see 0 here, - * so we may use the result of the comparison with -1. - */ - li v0, JIT_CHECK_OSR - beqc rPROFILE, v0, .L_osr_check - bltc rPROFILE, v0, .L_resume_backward_branch - dsubu rPROFILE, 1 - beqzc rPROFILE, .L_add_batch # counted down to zero - report -.L_resume_backward_branch: - lw ra, THREAD_FLAGS_OFFSET(rSELF) - REFRESH_IBASE - daddu a2, rINST, rINST # a2<- byte offset - FETCH_ADVANCE_INST_RB a2 # update rPC, load rINST - and ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST - bnezc ra, .L_suspend_request_pending - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -.L_suspend_request_pending: - EXPORT_PC - move a0, rSELF - jal MterpSuspendCheck # (self) - bnezc v0, MterpFallback - REFRESH_IBASE # might have changed during suspend - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -.L_no_count_backwards: - li v0, JIT_CHECK_OSR # check for possible OSR re-entry - bnec rPROFILE, v0, .L_resume_backward_branch -.L_osr_check: - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rINST - EXPORT_PC - jal MterpMaybeDoOnStackReplacement # (self, shadow_frame, offset) - bnezc v0, MterpOnStackReplacement - b .L_resume_backward_branch - -.L_forward_branch: - li v0, JIT_CHECK_OSR # check for possible OSR re-entry - beqc rPROFILE, v0, .L_check_osr_forward -.L_resume_forward_branch: - daddu a2, rINST, rINST # a2<- byte offset - FETCH_ADVANCE_INST_RB a2 # update rPC, load rINST - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -.L_check_osr_forward: - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rINST - EXPORT_PC - jal MterpMaybeDoOnStackReplacement # (self, shadow_frame, offset) - bnezc v0, MterpOnStackReplacement - b .L_resume_forward_branch - -.L_add_batch: - daddu a1, rFP, OFF_FP_SHADOWFRAME - sh rPROFILE, SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET(a1) - ld a0, OFF_FP_METHOD(rFP) - move a2, rSELF - jal MterpAddHotnessBatch # (method, shadow_frame, self) - move rPROFILE, v0 # restore new hotness countdown to rPROFILE - b .L_no_count_backwards - -/* - * Entered from the conditional branch handlers when OSR check request active on - * not-taken path. All Dalvik not-taken conditional branch offsets are 2. - */ -.L_check_not_taken_osr: - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - li a2, 2 - EXPORT_PC - jal MterpMaybeDoOnStackReplacement # (self, shadow_frame, offset) - bnezc v0, MterpOnStackReplacement - FETCH_ADVANCE_INST 2 - GET_INST_OPCODE v0 # extract opcode from rINST - GOTO_OPCODE v0 # jump to next instruction - -/* - * On-stack replacement has happened, and now we've returned from the compiled method. - */ -MterpOnStackReplacement: -#if MTERP_LOGGING - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rINST # rINST contains offset - jal MterpLogOSR -#endif - li v0, 1 # Signal normal return - b MterpDone - -/* - * Bail out to reference interpreter. - */ - .extern MterpLogFallback -MterpFallback: - EXPORT_PC -#if MTERP_LOGGING - move a0, rSELF - daddu a1, rFP, OFF_FP_SHADOWFRAME - jal MterpLogFallback -#endif -MterpCommonFallback: - li v0, 0 # signal retry with reference interpreter. - b MterpDone - -/* - * We pushed some registers on the stack in ExecuteMterpImpl, then saved - * SP and RA. Here we restore SP, restore the registers, and then restore - * RA to PC. - * - * On entry: - * uint32_t* rFP (should still be live, pointer to base of vregs) - */ -MterpExceptionReturn: - li v0, 1 # signal return to caller. - b MterpDone -/* - * Returned value is expected in a0 and if it's not 64-bit, the 32 most - * significant bits of a0 must be zero-extended or sign-extended - * depending on the return type. - */ -MterpReturn: - ld a2, OFF_FP_RESULT_REGISTER(rFP) - sd a0, 0(a2) - li v0, 1 # signal return to caller. -MterpDone: -/* - * At this point, we expect rPROFILE to be non-zero. If negative, hotness is disabled or we're - * checking for OSR. If greater than zero, we might have unreported hotness to register - * (the difference between the ending rPROFILE and the cached hotness counter). rPROFILE - * should only reach zero immediately after a hotness decrement, and is then reset to either - * a negative special state or the new non-zero countdown value. - */ - blez rPROFILE, .L_pop_and_return # if > 0, we may have some counts to report. - -MterpProfileActive: - move rINST, v0 # stash return value - /* Report cached hotness counts */ - ld a0, OFF_FP_METHOD(rFP) - daddu a1, rFP, OFF_FP_SHADOWFRAME - move a2, rSELF - sh rPROFILE, SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET(a1) - jal MterpAddHotnessBatch # (method, shadow_frame, self) - move v0, rINST # restore return value - -.L_pop_and_return: - ld s6, STACK_OFFSET_S6(sp) - .cfi_restore 22 - ld s5, STACK_OFFSET_S5(sp) - .cfi_restore 21 - ld s4, STACK_OFFSET_S4(sp) - .cfi_restore 20 - ld s3, STACK_OFFSET_S3(sp) - .cfi_restore 19 - ld s2, STACK_OFFSET_S2(sp) - .cfi_restore 18 - ld s1, STACK_OFFSET_S1(sp) - .cfi_restore 17 - ld s0, STACK_OFFSET_S0(sp) - .cfi_restore 16 - - ld ra, STACK_OFFSET_RA(sp) - .cfi_restore 31 - - ld t8, STACK_OFFSET_GP(sp) - .cpreturn - .cfi_restore 28 - - .set noreorder - jr ra - daddu sp, sp, STACK_SIZE - .cfi_adjust_cfa_offset -STACK_SIZE - - .cfi_endproc - .set reorder - .size ExecuteMterpImpl, .-ExecuteMterpImpl - diff --git a/runtime/interpreter/mterp/out/mterp_x86.S b/runtime/interpreter/mterp/out/mterp_x86.S deleted file mode 100644 index 32811ff370c6660fe1fda6e92eab5aced9a2d30c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/out/mterp_x86.S +++ /dev/null @@ -1,12855 +0,0 @@ -/* - * This file was generated automatically by gen-mterp.py for 'x86'. - * - * --> DO NOT EDIT <-- - */ - -/* File: x86/header.S */ -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - Art assembly interpreter notes: - - First validate assembly code by implementing ExecuteXXXImpl() style body (doesn't - handle invoke, allows higher-level code to create frame & shadow frame. - - Once that's working, support direct entry code & eliminate shadow frame (and - excess locals allocation. - - Some (hopefully) temporary ugliness. We'll treat rFP as pointing to the - base of the vreg array within the shadow frame. Access the other fields, - dex_pc_, method_ and number_of_vregs_ via negative offsets. For now, we'll continue - the shadow frame mechanism of double-storing object references - via rFP & - number_of_vregs_. - - */ - -/* -x86 ABI general notes: - -Caller save set: - eax, edx, ecx, st(0)-st(7) -Callee save set: - ebx, esi, edi, ebp -Return regs: - 32-bit in eax - 64-bit in edx:eax (low-order 32 in eax) - fp on top of fp stack st(0) - -Parameters passed on stack, pushed right-to-left. On entry to target, first -parm is at 4(%esp). Traditional entry code is: - -functEntry: - push %ebp # save old frame pointer - mov %ebp,%esp # establish new frame pointer - sub FrameSize,%esp # Allocate storage for spill, locals & outs - -Once past the prologue, arguments are referenced at ((argno + 2)*4)(%ebp) - -Stack must be 16-byte aligned to support SSE in native code. - -If we're not doing variable stack allocation (alloca), the frame pointer can be -eliminated and all arg references adjusted to be esp relative. -*/ - -/* -Mterp and x86 notes: - -Some key interpreter variables will be assigned to registers. - - nick reg purpose - rPC esi interpreted program counter, used for fetching instructions - rFP edi interpreted frame pointer, used for accessing locals and args - rINSTw bx first 16-bit code of current instruction - rINSTbl bl opcode portion of instruction word - rINSTbh bh high byte of inst word, usually contains src/tgt reg names - rIBASE edx base of instruction handler table - rREFS ebp base of object references in shadow frame. - -Notes: - o High order 16 bits of ebx must be zero on entry to handler - o rPC, rFP, rINSTw/rINSTbl valid on handler entry and exit - o eax and ecx are scratch, rINSTw/ebx sometimes scratch - -Macros are provided for common operations. Each macro MUST emit only -one instruction to make instruction-counting easier. They MUST NOT alter -unspecified registers or condition codes. -*/ - -/* - * This is a #include, not a %include, because we want the C pre-processor - * to expand the macros into assembler assignment statements. - */ -#include "asm_support.h" -#include "interpreter/cfi_asm_support.h" - -/* - * Handle mac compiler specific - */ -#if defined(__APPLE__) - #define MACRO_LITERAL(value) $(value) - #define FUNCTION_TYPE(name) - #define OBJECT_TYPE(name) - #define SIZE(start,end) - // Mac OS' symbols have an _ prefix. - #define SYMBOL(name) _ ## name - #define ASM_HIDDEN .private_extern -#else - #define MACRO_LITERAL(value) $value - #define FUNCTION_TYPE(name) .type name, @function - #define OBJECT_TYPE(name) .type name, @object - #define SIZE(start,end) .size start, .-end - #define SYMBOL(name) name - #define ASM_HIDDEN .hidden -#endif - -.macro PUSH _reg - pushl \_reg - .cfi_adjust_cfa_offset 4 - .cfi_rel_offset \_reg, 0 -.endm - -.macro POP _reg - popl \_reg - .cfi_adjust_cfa_offset -4 - .cfi_restore \_reg -.endm - -/* - * Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs. So, - * to access other shadow frame fields, we need to use a backwards offset. Define those here. - */ -#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) -#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) -#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) -#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) -#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) -#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) -#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) -#define OFF_FP_DEX_INSTRUCTIONS OFF_FP(SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET) -#define OFF_FP_COUNTDOWN_OFFSET OFF_FP(SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET) -#define OFF_FP_SHADOWFRAME OFF_FP(0) - -/* Frame size must be 16-byte aligned. - * Remember about 4 bytes for return address + 4 * 4 for spills - */ -#define FRAME_SIZE 28 - -/* Frame diagram while executing ExecuteMterpImpl, high to low addresses */ -#define IN_ARG3 (FRAME_SIZE + 16 + 16) -#define IN_ARG2 (FRAME_SIZE + 16 + 12) -#define IN_ARG1 (FRAME_SIZE + 16 + 8) -#define IN_ARG0 (FRAME_SIZE + 16 + 4) -/* Spill offsets relative to %esp */ -#define LOCAL0 (FRAME_SIZE - 4) -#define LOCAL1 (FRAME_SIZE - 8) -#define LOCAL2 (FRAME_SIZE - 12) -/* Out Arg offsets, relative to %esp */ -#define OUT_ARG3 ( 12) -#define OUT_ARG2 ( 8) -#define OUT_ARG1 ( 4) -#define OUT_ARG0 ( 0) /* <- ExecuteMterpImpl esp + 0 */ - -/* During bringup, we'll use the shadow frame model instead of rFP */ -/* single-purpose registers, given names for clarity */ -#define rSELF IN_ARG0(%esp) -#define rPC %esi -#define CFI_DEX 6 // DWARF register number of the register holding dex-pc (esi). -#define CFI_TMP 0 // DWARF register number of the first argument register (eax). -#define rFP %edi -#define rINST %ebx -#define rINSTw %bx -#define rINSTbh %bh -#define rINSTbl %bl -#define rIBASE %edx -#define rREFS %ebp -#define rPROFILE OFF_FP_COUNTDOWN_OFFSET(rFP) - -#define MTERP_LOGGING 0 - -/* - * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must - * be done *before* something throws. - * - * It's okay to do this more than once. - * - * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped - * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction - * offset into the code_items_[] array. For effiency, we will "export" the - * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC - * to convert to a dex pc when needed. - */ -.macro EXPORT_PC - movl rPC, OFF_FP_DEX_PC_PTR(rFP) -.endm - -/* - * Refresh handler table. - */ -.macro REFRESH_IBASE - movl rSELF, rIBASE - movl THREAD_CURRENT_IBASE_OFFSET(rIBASE), rIBASE -.endm - -/* - * Refresh handler table. - * IBase handles uses the caller save register so we must restore it after each call. - * Also it is used as a result of some 64-bit operations (like imul) and we should - * restore it in such cases also. - * - * TODO: Consider spilling the IBase instead of restoring it from Thread structure. - */ -.macro RESTORE_IBASE - movl rSELF, rIBASE - movl THREAD_CURRENT_IBASE_OFFSET(rIBASE), rIBASE -.endm - -/* - * If rSELF is already loaded then we can use it from known reg. - */ -.macro RESTORE_IBASE_FROM_SELF _reg - movl THREAD_CURRENT_IBASE_OFFSET(\_reg), rIBASE -.endm - -/* - * Refresh rINST. - * At enter to handler rINST does not contain the opcode number. - * However some utilities require the full value, so this macro - * restores the opcode number. - */ -.macro REFRESH_INST _opnum - movb rINSTbl, rINSTbh - movb MACRO_LITERAL(\_opnum), rINSTbl -.endm - -/* - * Fetch the next instruction from rPC into rINSTw. Does not advance rPC. - */ -.macro FETCH_INST - movzwl (rPC), rINST -.endm - -/* - * Remove opcode from rINST, compute the address of handler and jump to it. - */ -.macro GOTO_NEXT - movzx rINSTbl,%eax - movzbl rINSTbh,rINST - shll MACRO_LITERAL(7), %eax - addl rIBASE, %eax - jmp *%eax -.endm - -/* - * Advance rPC by instruction count. - */ -.macro ADVANCE_PC _count - leal 2*\_count(rPC), rPC -.endm - -/* - * Advance rPC by instruction count, fetch instruction and jump to handler. - */ -.macro ADVANCE_PC_FETCH_AND_GOTO_NEXT _count - ADVANCE_PC \_count - FETCH_INST - GOTO_NEXT -.endm - -/* - * Get/set the 32-bit value from a Dalvik register. - */ -#define VREG_ADDRESS(_vreg) (rFP,_vreg,4) -#define VREG_HIGH_ADDRESS(_vreg) 4(rFP,_vreg,4) -#define VREG_REF_ADDRESS(_vreg) (rREFS,_vreg,4) -#define VREG_REF_HIGH_ADDRESS(_vreg) 4(rREFS,_vreg,4) - -.macro GET_VREG _reg _vreg - movl (rFP,\_vreg,4), \_reg -.endm - -/* Read wide value to xmm. */ -.macro GET_WIDE_FP_VREG _reg _vreg - movq (rFP,\_vreg,4), \_reg -.endm - -.macro SET_VREG _reg _vreg - movl \_reg, (rFP,\_vreg,4) - movl MACRO_LITERAL(0), (rREFS,\_vreg,4) -.endm - -/* Write wide value from xmm. xmm is clobbered. */ -.macro SET_WIDE_FP_VREG _reg _vreg - movq \_reg, (rFP,\_vreg,4) - pxor \_reg, \_reg - movq \_reg, (rREFS,\_vreg,4) -.endm - -.macro SET_VREG_OBJECT _reg _vreg - movl \_reg, (rFP,\_vreg,4) - movl \_reg, (rREFS,\_vreg,4) -.endm - -.macro GET_VREG_HIGH _reg _vreg - movl 4(rFP,\_vreg,4), \_reg -.endm - -.macro SET_VREG_HIGH _reg _vreg - movl \_reg, 4(rFP,\_vreg,4) - movl MACRO_LITERAL(0), 4(rREFS,\_vreg,4) -.endm - -.macro CLEAR_REF _vreg - movl MACRO_LITERAL(0), (rREFS,\_vreg,4) -.endm - -.macro CLEAR_WIDE_REF _vreg - movl MACRO_LITERAL(0), (rREFS,\_vreg,4) - movl MACRO_LITERAL(0), 4(rREFS,\_vreg,4) -.endm - -/* File: x86/entry.S */ -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -/* - * Interpreter entry point. - */ - - .text - ASM_HIDDEN SYMBOL(ExecuteMterpImpl) - .global SYMBOL(ExecuteMterpImpl) - FUNCTION_TYPE(ExecuteMterpImpl) - -/* - * On entry: - * 0 Thread* self - * 1 insns_ - * 2 ShadowFrame - * 3 JValue* result_register - * - */ - -SYMBOL(ExecuteMterpImpl): - .cfi_startproc - .cfi_def_cfa esp, 4 - - /* Spill callee save regs */ - PUSH %ebp - PUSH %edi - PUSH %esi - PUSH %ebx - - /* Allocate frame */ - subl $FRAME_SIZE, %esp - .cfi_adjust_cfa_offset FRAME_SIZE - - /* Load ShadowFrame pointer */ - movl IN_ARG2(%esp), %edx - - /* Remember the return register */ - movl IN_ARG3(%esp), %eax - movl %eax, SHADOWFRAME_RESULT_REGISTER_OFFSET(%edx) - - /* Remember the code_item */ - movl IN_ARG1(%esp), %ecx - movl %ecx, SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET(%edx) - - /* set up "named" registers */ - movl SHADOWFRAME_NUMBER_OF_VREGS_OFFSET(%edx), %eax - leal SHADOWFRAME_VREGS_OFFSET(%edx), rFP - leal (rFP, %eax, 4), rREFS - movl SHADOWFRAME_DEX_PC_OFFSET(%edx), %eax - lea (%ecx, %eax, 2), rPC - CFI_DEFINE_DEX_PC_WITH_OFFSET(CFI_TMP, CFI_DEX, 0) - EXPORT_PC - - /* Set up for backwards branches & osr profiling */ - movl OFF_FP_METHOD(rFP), %eax - movl %eax, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - movl rSELF, %eax - movl %eax, OUT_ARG2(%esp) - call SYMBOL(MterpSetUpHotnessCountdown) - - /* Starting ibase */ - REFRESH_IBASE - - /* start executing the instruction at rPC */ - FETCH_INST - GOTO_NEXT - /* NOTE: no fallthrough */ - -/* File: x86/instruction_start.S */ - - OBJECT_TYPE(artMterpAsmInstructionStart) - ASM_HIDDEN SYMBOL(artMterpAsmInstructionStart) - .global SYMBOL(artMterpAsmInstructionStart) -SYMBOL(artMterpAsmInstructionStart) = .L_op_nop - .text - -/* ------------------------------ */ - .balign 128 -.L_op_nop: /* 0x00 */ -/* File: x86/op_nop.S */ - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_move: /* 0x01 */ -/* File: x86/op_move.S */ - /* for move, move-object, long-to-int */ - /* op vA, vB */ - movzbl rINSTbl, %eax # eax <- BA - andb $0xf, %al # eax <- A - shrl $4, rINST # rINST <- B - GET_VREG rINST, rINST - .if 0 - SET_VREG_OBJECT rINST, %eax # fp[A] <- fp[B] - .else - SET_VREG rINST, %eax # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_move_from16: /* 0x02 */ -/* File: x86/op_move_from16.S */ - /* for: move/from16, move-object/from16 */ - /* op vAA, vBBBB */ - movzx rINSTbl, %eax # eax <- AA - movw 2(rPC), rINSTw # rINSTw <- BBBB - GET_VREG rINST, rINST # rINST <- fp[BBBB] - .if 0 - SET_VREG_OBJECT rINST, %eax # fp[A] <- fp[B] - .else - SET_VREG rINST, %eax # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_move_16: /* 0x03 */ -/* File: x86/op_move_16.S */ - /* for: move/16, move-object/16 */ - /* op vAAAA, vBBBB */ - movzwl 4(rPC), %ecx # ecx <- BBBB - movzwl 2(rPC), %eax # eax <- AAAA - GET_VREG rINST, %ecx - .if 0 - SET_VREG_OBJECT rINST, %eax # fp[A] <- fp[B] - .else - SET_VREG rINST, %eax # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 - -/* ------------------------------ */ - .balign 128 -.L_op_move_wide: /* 0x04 */ -/* File: x86/op_move_wide.S */ - /* move-wide vA, vB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - GET_WIDE_FP_VREG %xmm0, rINST # xmm0 <- v[B] - SET_WIDE_FP_VREG %xmm0, %ecx # v[A] <- xmm0 - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_move_wide_from16: /* 0x05 */ -/* File: x86/op_move_wide_from16.S */ - /* move-wide/from16 vAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - movzwl 2(rPC), %ecx # ecx <- BBBB - movzbl rINSTbl, %eax # eax <- AAAA - GET_WIDE_FP_VREG %xmm0, %ecx # xmm0 <- v[B] - SET_WIDE_FP_VREG %xmm0, %eax # v[A] <- xmm0 - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_move_wide_16: /* 0x06 */ -/* File: x86/op_move_wide_16.S */ - /* move-wide/16 vAAAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - movzwl 4(rPC), %ecx # ecx<- BBBB - movzwl 2(rPC), %eax # eax<- AAAA - GET_WIDE_FP_VREG %xmm0, %ecx # xmm0 <- v[B] - SET_WIDE_FP_VREG %xmm0, %eax # v[A] <- xmm0 - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 - -/* ------------------------------ */ - .balign 128 -.L_op_move_object: /* 0x07 */ -/* File: x86/op_move_object.S */ -/* File: x86/op_move.S */ - /* for move, move-object, long-to-int */ - /* op vA, vB */ - movzbl rINSTbl, %eax # eax <- BA - andb $0xf, %al # eax <- A - shrl $4, rINST # rINST <- B - GET_VREG rINST, rINST - .if 1 - SET_VREG_OBJECT rINST, %eax # fp[A] <- fp[B] - .else - SET_VREG rINST, %eax # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_move_object_from16: /* 0x08 */ -/* File: x86/op_move_object_from16.S */ -/* File: x86/op_move_from16.S */ - /* for: move/from16, move-object/from16 */ - /* op vAA, vBBBB */ - movzx rINSTbl, %eax # eax <- AA - movw 2(rPC), rINSTw # rINSTw <- BBBB - GET_VREG rINST, rINST # rINST <- fp[BBBB] - .if 1 - SET_VREG_OBJECT rINST, %eax # fp[A] <- fp[B] - .else - SET_VREG rINST, %eax # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_move_object_16: /* 0x09 */ -/* File: x86/op_move_object_16.S */ -/* File: x86/op_move_16.S */ - /* for: move/16, move-object/16 */ - /* op vAAAA, vBBBB */ - movzwl 4(rPC), %ecx # ecx <- BBBB - movzwl 2(rPC), %eax # eax <- AAAA - GET_VREG rINST, %ecx - .if 1 - SET_VREG_OBJECT rINST, %eax # fp[A] <- fp[B] - .else - SET_VREG rINST, %eax # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 - - -/* ------------------------------ */ - .balign 128 -.L_op_move_result: /* 0x0a */ -/* File: x86/op_move_result.S */ - /* for: move-result, move-result-object */ - /* op vAA */ - movl OFF_FP_RESULT_REGISTER(rFP), %eax # get pointer to result JType. - movl (%eax), %eax # r0 <- result.i. - .if 0 - SET_VREG_OBJECT %eax, rINST # fp[A] <- fp[B] - .else - SET_VREG %eax, rINST # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_move_result_wide: /* 0x0b */ -/* File: x86/op_move_result_wide.S */ - /* move-result-wide vAA */ - movl OFF_FP_RESULT_REGISTER(rFP), %eax # get pointer to result JType. - movl 4(%eax), %ecx # Get high - movl (%eax), %eax # Get low - SET_VREG %eax, rINST # v[AA+0] <- eax - SET_VREG_HIGH %ecx, rINST # v[AA+1] <- ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_move_result_object: /* 0x0c */ -/* File: x86/op_move_result_object.S */ -/* File: x86/op_move_result.S */ - /* for: move-result, move-result-object */ - /* op vAA */ - movl OFF_FP_RESULT_REGISTER(rFP), %eax # get pointer to result JType. - movl (%eax), %eax # r0 <- result.i. - .if 1 - SET_VREG_OBJECT %eax, rINST # fp[A] <- fp[B] - .else - SET_VREG %eax, rINST # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_move_exception: /* 0x0d */ -/* File: x86/op_move_exception.S */ - /* move-exception vAA */ - movl rSELF, %ecx - movl THREAD_EXCEPTION_OFFSET(%ecx), %eax - SET_VREG_OBJECT %eax, rINST # fp[AA] <- exception object - movl $0, THREAD_EXCEPTION_OFFSET(%ecx) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_return_void: /* 0x0e */ -/* File: x86/op_return_void.S */ - .extern MterpThreadFenceForConstructor - call SYMBOL(MterpThreadFenceForConstructor) - movl rSELF, %eax - testl $(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(%eax) - jz 1f - movl %eax, OUT_ARG0(%esp) - call SYMBOL(MterpSuspendCheck) -1: - xorl %eax, %eax - xorl %ecx, %ecx - jmp MterpReturn - -/* ------------------------------ */ - .balign 128 -.L_op_return: /* 0x0f */ -/* File: x86/op_return.S */ -/* - * Return a 32-bit value. - * - * for: return, return-object - */ - /* op vAA */ - .extern MterpThreadFenceForConstructor - call SYMBOL(MterpThreadFenceForConstructor) - movl rSELF, %eax - testl $(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(%eax) - jz 1f - movl %eax, OUT_ARG0(%esp) - call SYMBOL(MterpSuspendCheck) -1: - GET_VREG %eax, rINST # eax <- vAA - xorl %ecx, %ecx - jmp MterpReturn - -/* ------------------------------ */ - .balign 128 -.L_op_return_wide: /* 0x10 */ -/* File: x86/op_return_wide.S */ -/* - * Return a 64-bit value. - */ - /* return-wide vAA */ - .extern MterpThreadFenceForConstructor - call SYMBOL(MterpThreadFenceForConstructor) - movl rSELF, %eax - testl $(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(%eax) - jz 1f - movl %eax, OUT_ARG0(%esp) - call SYMBOL(MterpSuspendCheck) -1: - GET_VREG %eax, rINST # eax <- v[AA+0] - GET_VREG_HIGH %ecx, rINST # ecx <- v[AA+1] - jmp MterpReturn - -/* ------------------------------ */ - .balign 128 -.L_op_return_object: /* 0x11 */ -/* File: x86/op_return_object.S */ -/* File: x86/op_return.S */ -/* - * Return a 32-bit value. - * - * for: return, return-object - */ - /* op vAA */ - .extern MterpThreadFenceForConstructor - call SYMBOL(MterpThreadFenceForConstructor) - movl rSELF, %eax - testl $(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(%eax) - jz 1f - movl %eax, OUT_ARG0(%esp) - call SYMBOL(MterpSuspendCheck) -1: - GET_VREG %eax, rINST # eax <- vAA - xorl %ecx, %ecx - jmp MterpReturn - - -/* ------------------------------ */ - .balign 128 -.L_op_const_4: /* 0x12 */ -/* File: x86/op_const_4.S */ - /* const/4 vA, #+B */ - movsx rINSTbl, %eax # eax <-ssssssBx - movl $0xf, rINST - andl %eax, rINST # rINST <- A - sarl $4, %eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_const_16: /* 0x13 */ -/* File: x86/op_const_16.S */ - /* const/16 vAA, #+BBBB */ - movswl 2(rPC), %ecx # ecx <- ssssBBBB - SET_VREG %ecx, rINST # vAA <- ssssBBBB - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_const: /* 0x14 */ -/* File: x86/op_const.S */ - /* const vAA, #+BBBBbbbb */ - movl 2(rPC), %eax # grab all 32 bits at once - SET_VREG %eax, rINST # vAA<- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 - -/* ------------------------------ */ - .balign 128 -.L_op_const_high16: /* 0x15 */ -/* File: x86/op_const_high16.S */ - /* const/high16 vAA, #+BBBB0000 */ - movzwl 2(rPC), %eax # eax <- 0000BBBB - sall $16, %eax # eax <- BBBB0000 - SET_VREG %eax, rINST # vAA <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_const_wide_16: /* 0x16 */ -/* File: x86/op_const_wide_16.S */ - /* const-wide/16 vAA, #+BBBB */ - movswl 2(rPC), %eax # eax <- ssssBBBB - movl rIBASE, %ecx # preserve rIBASE (cltd trashes it) - cltd # rIBASE:eax <- ssssssssssssBBBB - SET_VREG_HIGH rIBASE, rINST # store msw - SET_VREG %eax, rINST # store lsw - movl %ecx, rIBASE # restore rIBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_const_wide_32: /* 0x17 */ -/* File: x86/op_const_wide_32.S */ - /* const-wide/32 vAA, #+BBBBbbbb */ - movl 2(rPC), %eax # eax <- BBBBbbbb - movl rIBASE, %ecx # preserve rIBASE (cltd trashes it) - cltd # rIBASE:eax <- ssssssssssssBBBB - SET_VREG_HIGH rIBASE, rINST # store msw - SET_VREG %eax, rINST # store lsw - movl %ecx, rIBASE # restore rIBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 - -/* ------------------------------ */ - .balign 128 -.L_op_const_wide: /* 0x18 */ -/* File: x86/op_const_wide.S */ - /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ - movl 2(rPC), %eax # eax <- lsw - movzbl rINSTbl, %ecx # ecx <- AA - movl 6(rPC), rINST # rINST <- msw - SET_VREG %eax, %ecx - SET_VREG_HIGH rINST, %ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 5 - -/* ------------------------------ */ - .balign 128 -.L_op_const_wide_high16: /* 0x19 */ -/* File: x86/op_const_wide_high16.S */ - /* const-wide/high16 vAA, #+BBBB000000000000 */ - movzwl 2(rPC), %eax # eax <- 0000BBBB - sall $16, %eax # eax <- BBBB0000 - SET_VREG_HIGH %eax, rINST # v[AA+1] <- eax - xorl %eax, %eax - SET_VREG %eax, rINST # v[AA+0] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_const_string: /* 0x1a */ -/* File: x86/op_const_string.S */ -/* File: x86/const.S */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstString - EXPORT_PC - movzwl 2(rPC), %eax # eax <- BBBB - movl %eax, OUT_ARG0(%esp) - movl rINST, OUT_ARG1(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) - call SYMBOL(MterpConstString) # (index, tgt_reg, shadow_frame, self) - RESTORE_IBASE - testb %al, %al - jnz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_const_string_jumbo: /* 0x1b */ -/* File: x86/op_const_string_jumbo.S */ - /* const/string vAA, String@BBBBBBBB */ - EXPORT_PC - movl 2(rPC), %eax # eax <- BBBB - movl %eax, OUT_ARG0(%esp) - movl rINST, OUT_ARG1(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) - call SYMBOL(MterpConstString) # (index, tgt_reg, shadow_frame, self) - RESTORE_IBASE - testb %al, %al - jnz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 - -/* ------------------------------ */ - .balign 128 -.L_op_const_class: /* 0x1c */ -/* File: x86/op_const_class.S */ -/* File: x86/const.S */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstClass - EXPORT_PC - movzwl 2(rPC), %eax # eax <- BBBB - movl %eax, OUT_ARG0(%esp) - movl rINST, OUT_ARG1(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) - call SYMBOL(MterpConstClass) # (index, tgt_reg, shadow_frame, self) - RESTORE_IBASE - testb %al, %al - jnz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_monitor_enter: /* 0x1d */ -/* File: x86/op_monitor_enter.S */ -/* - * Synchronize on an object. - */ - /* monitor-enter vAA */ - EXPORT_PC - GET_VREG %ecx, rINST - movl %ecx, OUT_ARG0(%esp) - movl rSELF, %eax - movl %eax, OUT_ARG1(%esp) - call SYMBOL(artLockObjectFromCode) # (object, self) - RESTORE_IBASE - testb %al, %al - jnz MterpException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_monitor_exit: /* 0x1e */ -/* File: x86/op_monitor_exit.S */ -/* - * Unlock an object. - * - * Exceptions that occur when unlocking a monitor need to appear as - * if they happened at the following instruction. See the Dalvik - * instruction spec. - */ - /* monitor-exit vAA */ - EXPORT_PC - GET_VREG %ecx, rINST - movl %ecx, OUT_ARG0(%esp) - movl rSELF, %eax - movl %eax, OUT_ARG1(%esp) - call SYMBOL(artUnlockObjectFromCode) # (object, self) - RESTORE_IBASE - testb %al, %al - jnz MterpException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_check_cast: /* 0x1f */ -/* File: x86/op_check_cast.S */ -/* - * Check to see if a cast from one class to another is allowed. - */ - /* check-cast vAA, class@BBBB */ - EXPORT_PC - movzwl 2(rPC), %eax # eax <- BBBB - movl %eax, OUT_ARG0(%esp) - leal VREG_ADDRESS(rINST), %ecx - movl %ecx, OUT_ARG1(%esp) - movl OFF_FP_METHOD(rFP),%eax - movl %eax, OUT_ARG2(%esp) - movl rSELF, %ecx - movl %ecx, OUT_ARG3(%esp) - call SYMBOL(MterpCheckCast) # (index, &obj, method, self) - RESTORE_IBASE - testb %al, %al - jnz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_instance_of: /* 0x20 */ -/* File: x86/op_instance_of.S */ -/* - * Check to see if an object reference is an instance of a class. - * - * Most common situation is a non-null object, being compared against - * an already-resolved class. - */ - /* instance-of vA, vB, class@CCCC */ - EXPORT_PC - movzwl 2(rPC), %eax # eax <- BBBB - movl %eax, OUT_ARG0(%esp) - movl rINST, %eax # eax <- BA - sarl $4, %eax # eax <- B - leal VREG_ADDRESS(%eax), %ecx # Get object address - movl %ecx, OUT_ARG1(%esp) - movl OFF_FP_METHOD(rFP),%eax - movl %eax, OUT_ARG2(%esp) - movl rSELF, %ecx - movl %ecx, OUT_ARG3(%esp) - call SYMBOL(MterpInstanceOf) # (index, &obj, method, self) - movl rSELF, %ecx - RESTORE_IBASE_FROM_SELF %ecx - cmpl $0, THREAD_EXCEPTION_OFFSET(%ecx) - jnz MterpException - andb $0xf, rINSTbl # rINSTbl <- A - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_array_length: /* 0x21 */ -/* File: x86/op_array_length.S */ -/* - * Return the length of an array. - */ - mov rINST, %eax # eax <- BA - sarl $4, rINST # rINST <- B - GET_VREG %ecx, rINST # ecx <- vB (object ref) - testl %ecx, %ecx # is null? - je common_errNullObject - andb $0xf, %al # eax <- A - movl MIRROR_ARRAY_LENGTH_OFFSET(%ecx), rINST - SET_VREG rINST, %eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_new_instance: /* 0x22 */ -/* File: x86/op_new_instance.S */ -/* - * Create a new instance of a class. - */ - /* new-instance vAA, class@BBBB */ - EXPORT_PC - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG0(%esp) - movl rSELF, %ecx - movl %ecx, OUT_ARG1(%esp) - REFRESH_INST 34 - movl rINST, OUT_ARG2(%esp) - call SYMBOL(MterpNewInstance) - RESTORE_IBASE - testb %al, %al # 0 means an exception is thrown - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_new_array: /* 0x23 */ -/* File: x86/op_new_array.S */ -/* - * Allocate an array of objects, specified with the array class - * and a count. - * - * The verifier guarantees that this is an array class, so we don't - * check for it here. - */ - /* new-array vA, vB, class@CCCC */ - EXPORT_PC - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG0(%esp) - movl rPC, OUT_ARG1(%esp) - REFRESH_INST 35 - movl rINST, OUT_ARG2(%esp) - movl rSELF, %ecx - movl %ecx, OUT_ARG3(%esp) - call SYMBOL(MterpNewArray) - RESTORE_IBASE - testb %al, %al # 0 means an exception is thrown - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_filled_new_array: /* 0x24 */ -/* File: x86/op_filled_new_array.S */ -/* - * Create a new array with elements filled from registers. - * - * for: filled-new-array, filled-new-array/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ - .extern MterpFilledNewArray - EXPORT_PC - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG0(%esp) - movl rPC, OUT_ARG1(%esp) - movl rSELF, %ecx - movl %ecx, OUT_ARG2(%esp) - call SYMBOL(MterpFilledNewArray) - REFRESH_IBASE - testb %al, %al # 0 means an exception is thrown - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 - -/* ------------------------------ */ - .balign 128 -.L_op_filled_new_array_range: /* 0x25 */ -/* File: x86/op_filled_new_array_range.S */ -/* File: x86/op_filled_new_array.S */ -/* - * Create a new array with elements filled from registers. - * - * for: filled-new-array, filled-new-array/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ - .extern MterpFilledNewArrayRange - EXPORT_PC - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG0(%esp) - movl rPC, OUT_ARG1(%esp) - movl rSELF, %ecx - movl %ecx, OUT_ARG2(%esp) - call SYMBOL(MterpFilledNewArrayRange) - REFRESH_IBASE - testb %al, %al # 0 means an exception is thrown - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 - - -/* ------------------------------ */ - .balign 128 -.L_op_fill_array_data: /* 0x26 */ -/* File: x86/op_fill_array_data.S */ - /* fill-array-data vAA, +BBBBBBBB */ - EXPORT_PC - movl 2(rPC), %ecx # ecx <- BBBBbbbb - leal (rPC,%ecx,2), %ecx # ecx <- PC + BBBBbbbb*2 - GET_VREG %eax, rINST # eax <- vAA (array object) - movl %eax, OUT_ARG0(%esp) - movl %ecx, OUT_ARG1(%esp) - call SYMBOL(MterpFillArrayData) # (obj, payload) - REFRESH_IBASE - testb %al, %al # 0 means an exception is thrown - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 - -/* ------------------------------ */ - .balign 128 -.L_op_throw: /* 0x27 */ -/* File: x86/op_throw.S */ -/* - * Throw an exception object in the current thread. - */ - /* throw vAA */ - EXPORT_PC - GET_VREG %eax, rINST # eax<- vAA (exception object) - testl %eax, %eax - jz common_errNullObject - movl rSELF,%ecx - movl %eax, THREAD_EXCEPTION_OFFSET(%ecx) - jmp MterpException - -/* ------------------------------ */ - .balign 128 -.L_op_goto: /* 0x28 */ -/* File: x86/op_goto.S */ -/* - * Unconditional branch, 8-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto +AA */ - movsbl rINSTbl, rINST # rINST <- ssssssAA - testl rINST, rINST - jmp MterpCommonTakenBranch - -/* ------------------------------ */ - .balign 128 -.L_op_goto_16: /* 0x29 */ -/* File: x86/op_goto_16.S */ -/* - * Unconditional branch, 16-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto/16 +AAAA */ - movswl 2(rPC), rINST # rINST <- ssssAAAA - testl rINST, rINST - jmp MterpCommonTakenBranch - -/* ------------------------------ */ - .balign 128 -.L_op_goto_32: /* 0x2a */ -/* File: x86/op_goto_32.S */ -/* - * Unconditional branch, 32-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - * - * Unlike most opcodes, this one is allowed to branch to itself, so - * our "backward branch" test must be "<=0" instead of "<0". Because - * we need the V bit set, we'll use an adds to convert from Dalvik - * offset to byte offset. - */ - /* goto/32 +AAAAAAAA */ - movl 2(rPC), rINST # rINST <- AAAAAAAA - testl rINST, rINST - jmp MterpCommonTakenBranch - -/* ------------------------------ */ - .balign 128 -.L_op_packed_switch: /* 0x2b */ -/* File: x86/op_packed_switch.S */ -/* - * Handle a packed-switch or sparse-switch instruction. In both cases - * we decode it and hand it off to a helper function. - * - * We don't really expect backward branches in a switch statement, but - * they're perfectly legal, so we check for them here. - * - * for: packed-switch, sparse-switch - */ - /* op vAA, +BBBB */ - movl 2(rPC), %ecx # ecx <- BBBBbbbb - GET_VREG %eax, rINST # eax <- vAA - leal (rPC,%ecx,2), %ecx # ecx <- PC + BBBBbbbb*2 - movl %eax, OUT_ARG1(%esp) # ARG1 <- vAA - movl %ecx, OUT_ARG0(%esp) # ARG0 <- switchData - call SYMBOL(MterpDoPackedSwitch) - REFRESH_IBASE - testl %eax, %eax - movl %eax, rINST - jmp MterpCommonTakenBranch - -/* ------------------------------ */ - .balign 128 -.L_op_sparse_switch: /* 0x2c */ -/* File: x86/op_sparse_switch.S */ -/* File: x86/op_packed_switch.S */ -/* - * Handle a packed-switch or sparse-switch instruction. In both cases - * we decode it and hand it off to a helper function. - * - * We don't really expect backward branches in a switch statement, but - * they're perfectly legal, so we check for them here. - * - * for: packed-switch, sparse-switch - */ - /* op vAA, +BBBB */ - movl 2(rPC), %ecx # ecx <- BBBBbbbb - GET_VREG %eax, rINST # eax <- vAA - leal (rPC,%ecx,2), %ecx # ecx <- PC + BBBBbbbb*2 - movl %eax, OUT_ARG1(%esp) # ARG1 <- vAA - movl %ecx, OUT_ARG0(%esp) # ARG0 <- switchData - call SYMBOL(MterpDoSparseSwitch) - REFRESH_IBASE - testl %eax, %eax - movl %eax, rINST - jmp MterpCommonTakenBranch - - -/* ------------------------------ */ - .balign 128 -.L_op_cmpl_float: /* 0x2d */ -/* File: x86/op_cmpl_float.S */ -/* File: x86/fpcmp.S */ -/* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * int compare(x, y) { - * if (x == y) { - * return 0; - * } else if (x < y) { - * return -1; - * } else if (x > y) { - * return 1; - * } else { - * return nanval ? 1 : -1; - * } - * } - */ - /* op vAA, vBB, vCC */ - movzbl 3(rPC), %ecx # ecx<- CC - movzbl 2(rPC), %eax # eax<- BB - movss VREG_ADDRESS(%eax), %xmm0 - xor %eax, %eax - ucomiss VREG_ADDRESS(%ecx), %xmm0 - jp .Lop_cmpl_float_nan_is_neg - je .Lop_cmpl_float_finish - jb .Lop_cmpl_float_less -.Lop_cmpl_float_nan_is_pos: - incl %eax - jmp .Lop_cmpl_float_finish -.Lop_cmpl_float_nan_is_neg: -.Lop_cmpl_float_less: - decl %eax -.Lop_cmpl_float_finish: - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_cmpg_float: /* 0x2e */ -/* File: x86/op_cmpg_float.S */ -/* File: x86/fpcmp.S */ -/* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * int compare(x, y) { - * if (x == y) { - * return 0; - * } else if (x < y) { - * return -1; - * } else if (x > y) { - * return 1; - * } else { - * return nanval ? 1 : -1; - * } - * } - */ - /* op vAA, vBB, vCC */ - movzbl 3(rPC), %ecx # ecx<- CC - movzbl 2(rPC), %eax # eax<- BB - movss VREG_ADDRESS(%eax), %xmm0 - xor %eax, %eax - ucomiss VREG_ADDRESS(%ecx), %xmm0 - jp .Lop_cmpg_float_nan_is_pos - je .Lop_cmpg_float_finish - jb .Lop_cmpg_float_less -.Lop_cmpg_float_nan_is_pos: - incl %eax - jmp .Lop_cmpg_float_finish -.Lop_cmpg_float_nan_is_neg: -.Lop_cmpg_float_less: - decl %eax -.Lop_cmpg_float_finish: - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_cmpl_double: /* 0x2f */ -/* File: x86/op_cmpl_double.S */ -/* File: x86/fpcmp.S */ -/* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * int compare(x, y) { - * if (x == y) { - * return 0; - * } else if (x < y) { - * return -1; - * } else if (x > y) { - * return 1; - * } else { - * return nanval ? 1 : -1; - * } - * } - */ - /* op vAA, vBB, vCC */ - movzbl 3(rPC), %ecx # ecx<- CC - movzbl 2(rPC), %eax # eax<- BB - movsd VREG_ADDRESS(%eax), %xmm0 - xor %eax, %eax - ucomisd VREG_ADDRESS(%ecx), %xmm0 - jp .Lop_cmpl_double_nan_is_neg - je .Lop_cmpl_double_finish - jb .Lop_cmpl_double_less -.Lop_cmpl_double_nan_is_pos: - incl %eax - jmp .Lop_cmpl_double_finish -.Lop_cmpl_double_nan_is_neg: -.Lop_cmpl_double_less: - decl %eax -.Lop_cmpl_double_finish: - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_cmpg_double: /* 0x30 */ -/* File: x86/op_cmpg_double.S */ -/* File: x86/fpcmp.S */ -/* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * int compare(x, y) { - * if (x == y) { - * return 0; - * } else if (x < y) { - * return -1; - * } else if (x > y) { - * return 1; - * } else { - * return nanval ? 1 : -1; - * } - * } - */ - /* op vAA, vBB, vCC */ - movzbl 3(rPC), %ecx # ecx<- CC - movzbl 2(rPC), %eax # eax<- BB - movsd VREG_ADDRESS(%eax), %xmm0 - xor %eax, %eax - ucomisd VREG_ADDRESS(%ecx), %xmm0 - jp .Lop_cmpg_double_nan_is_pos - je .Lop_cmpg_double_finish - jb .Lop_cmpg_double_less -.Lop_cmpg_double_nan_is_pos: - incl %eax - jmp .Lop_cmpg_double_finish -.Lop_cmpg_double_nan_is_neg: -.Lop_cmpg_double_less: - decl %eax -.Lop_cmpg_double_finish: - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_cmp_long: /* 0x31 */ -/* File: x86/op_cmp_long.S */ -/* - * Compare two 64-bit values. Puts 0, 1, or -1 into the destination - * register based on the results of the comparison. - */ - /* cmp-long vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG_HIGH %eax, %eax # eax <- v[BB+1], BB is clobbered - cmpl VREG_HIGH_ADDRESS(%ecx), %eax - jl .Lop_cmp_long_smaller - jg .Lop_cmp_long_bigger - movzbl 2(rPC), %eax # eax <- BB, restore BB - GET_VREG %eax, %eax # eax <- v[BB] - sub VREG_ADDRESS(%ecx), %eax - ja .Lop_cmp_long_bigger - jb .Lop_cmp_long_smaller -.Lop_cmp_long_finish: - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -.Lop_cmp_long_bigger: - movl $1, %eax - jmp .Lop_cmp_long_finish - -.Lop_cmp_long_smaller: - movl $-1, %eax - jmp .Lop_cmp_long_finish - -/* ------------------------------ */ - .balign 128 -.L_op_if_eq: /* 0x32 */ -/* File: x86/op_if_eq.S */ -/* File: x86/bincmp.S */ -/* - * Generic two-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - movzx rINSTbl, %ecx # ecx <- A+ - andb $0xf, %cl # ecx <- A - GET_VREG %eax, %ecx # eax <- vA - sarl $4, rINST # rINST <- B - cmpl VREG_ADDRESS(rINST), %eax # compare (vA, vB) - jne 1f - movswl 2(rPC), rINST # Get signed branch offset - testl rINST, rINST - jmp MterpCommonTakenBranch -1: - cmpw $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_if_ne: /* 0x33 */ -/* File: x86/op_if_ne.S */ -/* File: x86/bincmp.S */ -/* - * Generic two-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - movzx rINSTbl, %ecx # ecx <- A+ - andb $0xf, %cl # ecx <- A - GET_VREG %eax, %ecx # eax <- vA - sarl $4, rINST # rINST <- B - cmpl VREG_ADDRESS(rINST), %eax # compare (vA, vB) - je 1f - movswl 2(rPC), rINST # Get signed branch offset - testl rINST, rINST - jmp MterpCommonTakenBranch -1: - cmpw $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_if_lt: /* 0x34 */ -/* File: x86/op_if_lt.S */ -/* File: x86/bincmp.S */ -/* - * Generic two-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - movzx rINSTbl, %ecx # ecx <- A+ - andb $0xf, %cl # ecx <- A - GET_VREG %eax, %ecx # eax <- vA - sarl $4, rINST # rINST <- B - cmpl VREG_ADDRESS(rINST), %eax # compare (vA, vB) - jge 1f - movswl 2(rPC), rINST # Get signed branch offset - testl rINST, rINST - jmp MterpCommonTakenBranch -1: - cmpw $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_if_ge: /* 0x35 */ -/* File: x86/op_if_ge.S */ -/* File: x86/bincmp.S */ -/* - * Generic two-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - movzx rINSTbl, %ecx # ecx <- A+ - andb $0xf, %cl # ecx <- A - GET_VREG %eax, %ecx # eax <- vA - sarl $4, rINST # rINST <- B - cmpl VREG_ADDRESS(rINST), %eax # compare (vA, vB) - jl 1f - movswl 2(rPC), rINST # Get signed branch offset - testl rINST, rINST - jmp MterpCommonTakenBranch -1: - cmpw $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_if_gt: /* 0x36 */ -/* File: x86/op_if_gt.S */ -/* File: x86/bincmp.S */ -/* - * Generic two-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - movzx rINSTbl, %ecx # ecx <- A+ - andb $0xf, %cl # ecx <- A - GET_VREG %eax, %ecx # eax <- vA - sarl $4, rINST # rINST <- B - cmpl VREG_ADDRESS(rINST), %eax # compare (vA, vB) - jle 1f - movswl 2(rPC), rINST # Get signed branch offset - testl rINST, rINST - jmp MterpCommonTakenBranch -1: - cmpw $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_if_le: /* 0x37 */ -/* File: x86/op_if_le.S */ -/* File: x86/bincmp.S */ -/* - * Generic two-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - movzx rINSTbl, %ecx # ecx <- A+ - andb $0xf, %cl # ecx <- A - GET_VREG %eax, %ecx # eax <- vA - sarl $4, rINST # rINST <- B - cmpl VREG_ADDRESS(rINST), %eax # compare (vA, vB) - jg 1f - movswl 2(rPC), rINST # Get signed branch offset - testl rINST, rINST - jmp MterpCommonTakenBranch -1: - cmpw $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_if_eqz: /* 0x38 */ -/* File: x86/op_if_eqz.S */ -/* File: x86/zcmp.S */ -/* - * Generic one-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - cmpl $0, VREG_ADDRESS(rINST) # compare (vA, 0) - jne 1f - movswl 2(rPC), rINST # fetch signed displacement - testl rINST, rINST - jmp MterpCommonTakenBranch -1: - cmpw $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_if_nez: /* 0x39 */ -/* File: x86/op_if_nez.S */ -/* File: x86/zcmp.S */ -/* - * Generic one-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - cmpl $0, VREG_ADDRESS(rINST) # compare (vA, 0) - je 1f - movswl 2(rPC), rINST # fetch signed displacement - testl rINST, rINST - jmp MterpCommonTakenBranch -1: - cmpw $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_if_ltz: /* 0x3a */ -/* File: x86/op_if_ltz.S */ -/* File: x86/zcmp.S */ -/* - * Generic one-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - cmpl $0, VREG_ADDRESS(rINST) # compare (vA, 0) - jge 1f - movswl 2(rPC), rINST # fetch signed displacement - testl rINST, rINST - jmp MterpCommonTakenBranch -1: - cmpw $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_if_gez: /* 0x3b */ -/* File: x86/op_if_gez.S */ -/* File: x86/zcmp.S */ -/* - * Generic one-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - cmpl $0, VREG_ADDRESS(rINST) # compare (vA, 0) - jl 1f - movswl 2(rPC), rINST # fetch signed displacement - testl rINST, rINST - jmp MterpCommonTakenBranch -1: - cmpw $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_if_gtz: /* 0x3c */ -/* File: x86/op_if_gtz.S */ -/* File: x86/zcmp.S */ -/* - * Generic one-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - cmpl $0, VREG_ADDRESS(rINST) # compare (vA, 0) - jle 1f - movswl 2(rPC), rINST # fetch signed displacement - testl rINST, rINST - jmp MterpCommonTakenBranch -1: - cmpw $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_if_lez: /* 0x3d */ -/* File: x86/op_if_lez.S */ -/* File: x86/zcmp.S */ -/* - * Generic one-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - cmpl $0, VREG_ADDRESS(rINST) # compare (vA, 0) - jg 1f - movswl 2(rPC), rINST # fetch signed displacement - testl rINST, rINST - jmp MterpCommonTakenBranch -1: - cmpw $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_3e: /* 0x3e */ -/* File: x86/op_unused_3e.S */ -/* File: x86/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_3f: /* 0x3f */ -/* File: x86/op_unused_3f.S */ -/* File: x86/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_40: /* 0x40 */ -/* File: x86/op_unused_40.S */ -/* File: x86/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_41: /* 0x41 */ -/* File: x86/op_unused_41.S */ -/* File: x86/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_42: /* 0x42 */ -/* File: x86/op_unused_42.S */ -/* File: x86/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_43: /* 0x43 */ -/* File: x86/op_unused_43.S */ -/* File: x86/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_aget: /* 0x44 */ -/* File: x86/op_aget.S */ -/* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - */ - /* op vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB (array object) - GET_VREG %ecx, %ecx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - movl MIRROR_INT_ARRAY_DATA_OFFSET(%eax,%ecx,4), %eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_aget_wide: /* 0x45 */ -/* File: x86/op_aget_wide.S */ -/* - * Array get, 64 bits. vAA <- vBB[vCC]. - */ - /* aget-wide vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB (array object) - GET_VREG %ecx, %ecx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - leal MIRROR_WIDE_ARRAY_DATA_OFFSET(%eax,%ecx,8), %eax - movq (%eax), %xmm0 # xmm0 <- vBB[vCC] - SET_WIDE_FP_VREG %xmm0, rINST # vAA <- xmm0 - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_aget_object: /* 0x46 */ -/* File: x86/op_aget_object.S */ -/* - * Array object get. vAA <- vBB[vCC]. - * - * for: aget-object - */ - /* op vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB (array object) - GET_VREG %ecx, %ecx # ecs <- vCC (requested index) - EXPORT_PC - movl %eax, OUT_ARG0(%esp) - movl %ecx, OUT_ARG1(%esp) - call SYMBOL(artAGetObjectFromMterp) # (array, index) - movl rSELF, %ecx - RESTORE_IBASE_FROM_SELF %ecx - cmpl $0, THREAD_EXCEPTION_OFFSET(%ecx) - jnz MterpException - SET_VREG_OBJECT %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_aget_boolean: /* 0x47 */ -/* File: x86/op_aget_boolean.S */ -/* File: x86/op_aget.S */ -/* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - */ - /* op vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB (array object) - GET_VREG %ecx, %ecx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - movzbl MIRROR_BOOLEAN_ARRAY_DATA_OFFSET(%eax,%ecx,1), %eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_aget_byte: /* 0x48 */ -/* File: x86/op_aget_byte.S */ -/* File: x86/op_aget.S */ -/* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - */ - /* op vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB (array object) - GET_VREG %ecx, %ecx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - movsbl MIRROR_BYTE_ARRAY_DATA_OFFSET(%eax,%ecx,1), %eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_aget_char: /* 0x49 */ -/* File: x86/op_aget_char.S */ -/* File: x86/op_aget.S */ -/* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - */ - /* op vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB (array object) - GET_VREG %ecx, %ecx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - movzwl MIRROR_CHAR_ARRAY_DATA_OFFSET(%eax,%ecx,2), %eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_aget_short: /* 0x4a */ -/* File: x86/op_aget_short.S */ -/* File: x86/op_aget.S */ -/* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - */ - /* op vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB (array object) - GET_VREG %ecx, %ecx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - movswl MIRROR_SHORT_ARRAY_DATA_OFFSET(%eax,%ecx,2), %eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_aput: /* 0x4b */ -/* File: x86/op_aput.S */ -/* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - */ - /* op vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB (array object) - GET_VREG %ecx, %ecx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - leal MIRROR_INT_ARRAY_DATA_OFFSET(%eax,%ecx,4), %eax - GET_VREG rINST, rINST - movl rINST, (%eax) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_aput_wide: /* 0x4c */ -/* File: x86/op_aput_wide.S */ -/* - * Array put, 64 bits. vBB[vCC] <- vAA. - * - */ - /* aput-wide vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB (array object) - GET_VREG %ecx, %ecx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - leal MIRROR_WIDE_ARRAY_DATA_OFFSET(%eax,%ecx,8), %eax - GET_WIDE_FP_VREG %xmm0, rINST # xmm0 <- vAA - movq %xmm0, (%eax) # vBB[vCC] <- xmm0 - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_aput_object: /* 0x4d */ -/* File: x86/op_aput_object.S */ -/* - * Store an object into an array. vBB[vCC] <- vAA. - */ - /* op vAA, vBB, vCC */ - EXPORT_PC - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG0(%esp) - movl rPC, OUT_ARG1(%esp) - REFRESH_INST 77 - movl rINST, OUT_ARG2(%esp) - call SYMBOL(MterpAputObject) # (array, index) - RESTORE_IBASE - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_aput_boolean: /* 0x4e */ -/* File: x86/op_aput_boolean.S */ -/* File: x86/op_aput.S */ -/* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - */ - /* op vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB (array object) - GET_VREG %ecx, %ecx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - leal MIRROR_BOOLEAN_ARRAY_DATA_OFFSET(%eax,%ecx,1), %eax - GET_VREG rINST, rINST - movb rINSTbl, (%eax) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_aput_byte: /* 0x4f */ -/* File: x86/op_aput_byte.S */ -/* File: x86/op_aput.S */ -/* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - */ - /* op vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB (array object) - GET_VREG %ecx, %ecx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - leal MIRROR_BYTE_ARRAY_DATA_OFFSET(%eax,%ecx,1), %eax - GET_VREG rINST, rINST - movb rINSTbl, (%eax) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_aput_char: /* 0x50 */ -/* File: x86/op_aput_char.S */ -/* File: x86/op_aput.S */ -/* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - */ - /* op vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB (array object) - GET_VREG %ecx, %ecx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - leal MIRROR_CHAR_ARRAY_DATA_OFFSET(%eax,%ecx,2), %eax - GET_VREG rINST, rINST - movw rINSTw, (%eax) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_aput_short: /* 0x51 */ -/* File: x86/op_aput_short.S */ -/* File: x86/op_aput.S */ -/* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - */ - /* op vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB (array object) - GET_VREG %ecx, %ecx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - leal MIRROR_SHORT_ARRAY_DATA_OFFSET(%eax,%ecx,2), %eax - GET_VREG rINST, rINST - movw rINSTw, (%eax) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_iget: /* 0x52 */ -/* File: x86/op_iget.S */ -/* File: x86/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetU32 - REFRESH_INST 82 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpIGetU32) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_wide: /* 0x53 */ -/* File: x86/op_iget_wide.S */ -/* File: x86/op_iget.S */ -/* File: x86/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetU64 - REFRESH_INST 83 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpIGetU64) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_object: /* 0x54 */ -/* File: x86/op_iget_object.S */ -/* File: x86/op_iget.S */ -/* File: x86/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetObj - REFRESH_INST 84 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpIGetObj) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_boolean: /* 0x55 */ -/* File: x86/op_iget_boolean.S */ -/* File: x86/op_iget.S */ -/* File: x86/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetU8 - REFRESH_INST 85 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpIGetU8) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_byte: /* 0x56 */ -/* File: x86/op_iget_byte.S */ -/* File: x86/op_iget.S */ -/* File: x86/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetI8 - REFRESH_INST 86 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpIGetI8) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_char: /* 0x57 */ -/* File: x86/op_iget_char.S */ -/* File: x86/op_iget.S */ -/* File: x86/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetU16 - REFRESH_INST 87 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpIGetU16) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_short: /* 0x58 */ -/* File: x86/op_iget_short.S */ -/* File: x86/op_iget.S */ -/* File: x86/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetI16 - REFRESH_INST 88 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpIGetI16) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_iput: /* 0x59 */ -/* File: x86/op_iput.S */ -/* File: x86/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutU32 - REFRESH_INST 89 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpIPutU32) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_wide: /* 0x5a */ -/* File: x86/op_iput_wide.S */ -/* File: x86/op_iput.S */ -/* File: x86/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutU64 - REFRESH_INST 90 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpIPutU64) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_object: /* 0x5b */ -/* File: x86/op_iput_object.S */ -/* File: x86/op_iput.S */ -/* File: x86/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutObj - REFRESH_INST 91 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpIPutObj) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_boolean: /* 0x5c */ -/* File: x86/op_iput_boolean.S */ -/* File: x86/op_iput.S */ -/* File: x86/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutU8 - REFRESH_INST 92 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpIPutU8) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_byte: /* 0x5d */ -/* File: x86/op_iput_byte.S */ -/* File: x86/op_iput.S */ -/* File: x86/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutI8 - REFRESH_INST 93 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpIPutI8) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_char: /* 0x5e */ -/* File: x86/op_iput_char.S */ -/* File: x86/op_iput.S */ -/* File: x86/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutU16 - REFRESH_INST 94 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpIPutU16) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_short: /* 0x5f */ -/* File: x86/op_iput_short.S */ -/* File: x86/op_iput.S */ -/* File: x86/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutI16 - REFRESH_INST 95 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpIPutI16) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_sget: /* 0x60 */ -/* File: x86/op_sget.S */ -/* File: x86/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetU32 - REFRESH_INST 96 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpSGetU32) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_sget_wide: /* 0x61 */ -/* File: x86/op_sget_wide.S */ -/* File: x86/op_sget.S */ -/* File: x86/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetU64 - REFRESH_INST 97 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpSGetU64) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_sget_object: /* 0x62 */ -/* File: x86/op_sget_object.S */ -/* File: x86/op_sget.S */ -/* File: x86/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetObj - REFRESH_INST 98 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpSGetObj) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_sget_boolean: /* 0x63 */ -/* File: x86/op_sget_boolean.S */ -/* File: x86/op_sget.S */ -/* File: x86/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetU8 - REFRESH_INST 99 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpSGetU8) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_sget_byte: /* 0x64 */ -/* File: x86/op_sget_byte.S */ -/* File: x86/op_sget.S */ -/* File: x86/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetI8 - REFRESH_INST 100 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpSGetI8) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_sget_char: /* 0x65 */ -/* File: x86/op_sget_char.S */ -/* File: x86/op_sget.S */ -/* File: x86/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetU16 - REFRESH_INST 101 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpSGetU16) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_sget_short: /* 0x66 */ -/* File: x86/op_sget_short.S */ -/* File: x86/op_sget.S */ -/* File: x86/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetI16 - REFRESH_INST 102 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpSGetI16) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_sput: /* 0x67 */ -/* File: x86/op_sput.S */ -/* File: x86/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutU32 - REFRESH_INST 103 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpSPutU32) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_sput_wide: /* 0x68 */ -/* File: x86/op_sput_wide.S */ -/* File: x86/op_sput.S */ -/* File: x86/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutU64 - REFRESH_INST 104 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpSPutU64) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_sput_object: /* 0x69 */ -/* File: x86/op_sput_object.S */ -/* File: x86/op_sput.S */ -/* File: x86/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutObj - REFRESH_INST 105 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpSPutObj) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_sput_boolean: /* 0x6a */ -/* File: x86/op_sput_boolean.S */ -/* File: x86/op_sput.S */ -/* File: x86/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutU8 - REFRESH_INST 106 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpSPutU8) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_sput_byte: /* 0x6b */ -/* File: x86/op_sput_byte.S */ -/* File: x86/op_sput.S */ -/* File: x86/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutI8 - REFRESH_INST 107 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpSPutI8) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_sput_char: /* 0x6c */ -/* File: x86/op_sput_char.S */ -/* File: x86/op_sput.S */ -/* File: x86/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutU16 - REFRESH_INST 108 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpSPutU16) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_sput_short: /* 0x6d */ -/* File: x86/op_sput_short.S */ -/* File: x86/op_sput.S */ -/* File: x86/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutI16 - REFRESH_INST 109 # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL(MterpSPutI16) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual: /* 0x6e */ -/* File: x86/op_invoke_virtual.S */ -/* File: x86/invoke.S */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtual - EXPORT_PC - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - REFRESH_INST 110 - movl rINST, OUT_ARG3(%esp) - call SYMBOL(MterpInvokeVirtual) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - RESTORE_IBASE - FETCH_INST - GOTO_NEXT - -/* - * Handle a virtual method call. - * - * for: invoke-virtual, invoke-virtual/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_super: /* 0x6f */ -/* File: x86/op_invoke_super.S */ -/* File: x86/invoke.S */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeSuper - EXPORT_PC - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - REFRESH_INST 111 - movl rINST, OUT_ARG3(%esp) - call SYMBOL(MterpInvokeSuper) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - RESTORE_IBASE - FETCH_INST - GOTO_NEXT - -/* - * Handle a "super" method call. - * - * for: invoke-super, invoke-super/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_direct: /* 0x70 */ -/* File: x86/op_invoke_direct.S */ -/* File: x86/invoke.S */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeDirect - EXPORT_PC - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - REFRESH_INST 112 - movl rINST, OUT_ARG3(%esp) - call SYMBOL(MterpInvokeDirect) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - RESTORE_IBASE - FETCH_INST - GOTO_NEXT - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_static: /* 0x71 */ -/* File: x86/op_invoke_static.S */ -/* File: x86/invoke.S */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeStatic - EXPORT_PC - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - REFRESH_INST 113 - movl rINST, OUT_ARG3(%esp) - call SYMBOL(MterpInvokeStatic) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - RESTORE_IBASE - FETCH_INST - GOTO_NEXT - - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_interface: /* 0x72 */ -/* File: x86/op_invoke_interface.S */ -/* File: x86/invoke.S */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeInterface - EXPORT_PC - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - REFRESH_INST 114 - movl rINST, OUT_ARG3(%esp) - call SYMBOL(MterpInvokeInterface) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - RESTORE_IBASE - FETCH_INST - GOTO_NEXT - -/* - * Handle an interface method call. - * - * for: invoke-interface, invoke-interface/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - -/* ------------------------------ */ - .balign 128 -.L_op_return_void_no_barrier: /* 0x73 */ -/* File: x86/op_return_void_no_barrier.S */ - movl rSELF, %eax - testl $(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(%eax) - jz 1f - movl %eax, OUT_ARG0(%esp) - call SYMBOL(MterpSuspendCheck) -1: - xorl %eax, %eax - xorl %ecx, %ecx - jmp MterpReturn - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual_range: /* 0x74 */ -/* File: x86/op_invoke_virtual_range.S */ -/* File: x86/invoke.S */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtualRange - EXPORT_PC - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - REFRESH_INST 116 - movl rINST, OUT_ARG3(%esp) - call SYMBOL(MterpInvokeVirtualRange) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - RESTORE_IBASE - FETCH_INST - GOTO_NEXT - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_super_range: /* 0x75 */ -/* File: x86/op_invoke_super_range.S */ -/* File: x86/invoke.S */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeSuperRange - EXPORT_PC - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - REFRESH_INST 117 - movl rINST, OUT_ARG3(%esp) - call SYMBOL(MterpInvokeSuperRange) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - RESTORE_IBASE - FETCH_INST - GOTO_NEXT - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_direct_range: /* 0x76 */ -/* File: x86/op_invoke_direct_range.S */ -/* File: x86/invoke.S */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeDirectRange - EXPORT_PC - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - REFRESH_INST 118 - movl rINST, OUT_ARG3(%esp) - call SYMBOL(MterpInvokeDirectRange) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - RESTORE_IBASE - FETCH_INST - GOTO_NEXT - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_static_range: /* 0x77 */ -/* File: x86/op_invoke_static_range.S */ -/* File: x86/invoke.S */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeStaticRange - EXPORT_PC - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - REFRESH_INST 119 - movl rINST, OUT_ARG3(%esp) - call SYMBOL(MterpInvokeStaticRange) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - RESTORE_IBASE - FETCH_INST - GOTO_NEXT - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_interface_range: /* 0x78 */ -/* File: x86/op_invoke_interface_range.S */ -/* File: x86/invoke.S */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeInterfaceRange - EXPORT_PC - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - REFRESH_INST 120 - movl rINST, OUT_ARG3(%esp) - call SYMBOL(MterpInvokeInterfaceRange) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - RESTORE_IBASE - FETCH_INST - GOTO_NEXT - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_79: /* 0x79 */ -/* File: x86/op_unused_79.S */ -/* File: x86/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_7a: /* 0x7a */ -/* File: x86/op_unused_7a.S */ -/* File: x86/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_neg_int: /* 0x7b */ -/* File: x86/op_neg_int.S */ -/* File: x86/unop.S */ -/* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op eax". - */ - /* unop vA, vB */ - movzbl rINSTbl,%ecx # ecx <- A+ - sarl $4,rINST # rINST <- B - GET_VREG %eax, rINST # eax <- vB - andb $0xf,%cl # ecx <- A - negl %eax - SET_VREG %eax, %ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_not_int: /* 0x7c */ -/* File: x86/op_not_int.S */ -/* File: x86/unop.S */ -/* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op eax". - */ - /* unop vA, vB */ - movzbl rINSTbl,%ecx # ecx <- A+ - sarl $4,rINST # rINST <- B - GET_VREG %eax, rINST # eax <- vB - andb $0xf,%cl # ecx <- A - notl %eax - SET_VREG %eax, %ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_neg_long: /* 0x7d */ -/* File: x86/op_neg_long.S */ - /* unop vA, vB */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $4, %ecx # ecx <- B - andb $0xf, rINSTbl # rINST <- A - GET_VREG %eax, %ecx # eax <- v[B+0] - GET_VREG_HIGH %ecx, %ecx # ecx <- v[B+1] - negl %eax - adcl $0, %ecx - negl %ecx - SET_VREG %eax, rINST # v[A+0] <- eax - SET_VREG_HIGH %ecx, rINST # v[A+1] <- ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_not_long: /* 0x7e */ -/* File: x86/op_not_long.S */ - /* unop vA, vB */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $4, %ecx # ecx <- B - andb $0xf, rINSTbl # rINST <- A - GET_VREG %eax, %ecx # eax <- v[B+0] - GET_VREG_HIGH %ecx, %ecx # ecx <- v[B+1] - notl %eax - notl %ecx - SET_VREG %eax, rINST # v[A+0] <- eax - SET_VREG_HIGH %ecx, rINST # v[A+1] <- ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_neg_float: /* 0x7f */ -/* File: x86/op_neg_float.S */ -/* File: x86/fpcvt.S */ -/* - * Generic 32-bit FP conversion operation. - */ - /* unop vA, vB */ - movzbl rINSTbl, %ecx # ecx <- A+ - sarl $4, rINST # rINST <- B - flds VREG_ADDRESS(rINST) # %st0 <- vB - andb $0xf, %cl # ecx <- A - fchs - fstps VREG_ADDRESS(%ecx) # vA <- %st0 - .if 0 - CLEAR_WIDE_REF %ecx - .else - CLEAR_REF %ecx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_neg_double: /* 0x80 */ -/* File: x86/op_neg_double.S */ -/* File: x86/fpcvt.S */ -/* - * Generic 32-bit FP conversion operation. - */ - /* unop vA, vB */ - movzbl rINSTbl, %ecx # ecx <- A+ - sarl $4, rINST # rINST <- B - fldl VREG_ADDRESS(rINST) # %st0 <- vB - andb $0xf, %cl # ecx <- A - fchs - fstpl VREG_ADDRESS(%ecx) # vA <- %st0 - .if 1 - CLEAR_WIDE_REF %ecx - .else - CLEAR_REF %ecx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_long: /* 0x81 */ -/* File: x86/op_int_to_long.S */ - /* int to long vA, vB */ - movzbl rINSTbl, %eax # eax <- +A - sarl $4, %eax # eax <- B - GET_VREG %eax, %eax # eax <- vB - andb $0xf, rINSTbl # rINST <- A - movl rIBASE, %ecx # cltd trashes rIBASE/edx - cltd # rINST:eax<- sssssssBBBBBBBB - SET_VREG_HIGH rIBASE, rINST # v[A+1] <- rIBASE - SET_VREG %eax, rINST # v[A+0] <- %eax - movl %ecx, rIBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_float: /* 0x82 */ -/* File: x86/op_int_to_float.S */ -/* File: x86/fpcvt.S */ -/* - * Generic 32-bit FP conversion operation. - */ - /* unop vA, vB */ - movzbl rINSTbl, %ecx # ecx <- A+ - sarl $4, rINST # rINST <- B - fildl VREG_ADDRESS(rINST) # %st0 <- vB - andb $0xf, %cl # ecx <- A - - fstps VREG_ADDRESS(%ecx) # vA <- %st0 - .if 0 - CLEAR_WIDE_REF %ecx - .else - CLEAR_REF %ecx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_double: /* 0x83 */ -/* File: x86/op_int_to_double.S */ -/* File: x86/fpcvt.S */ -/* - * Generic 32-bit FP conversion operation. - */ - /* unop vA, vB */ - movzbl rINSTbl, %ecx # ecx <- A+ - sarl $4, rINST # rINST <- B - fildl VREG_ADDRESS(rINST) # %st0 <- vB - andb $0xf, %cl # ecx <- A - - fstpl VREG_ADDRESS(%ecx) # vA <- %st0 - .if 1 - CLEAR_WIDE_REF %ecx - .else - CLEAR_REF %ecx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_long_to_int: /* 0x84 */ -/* File: x86/op_long_to_int.S */ -/* we ignore the high word, making this equivalent to a 32-bit reg move */ -/* File: x86/op_move.S */ - /* for move, move-object, long-to-int */ - /* op vA, vB */ - movzbl rINSTbl, %eax # eax <- BA - andb $0xf, %al # eax <- A - shrl $4, rINST # rINST <- B - GET_VREG rINST, rINST - .if 0 - SET_VREG_OBJECT rINST, %eax # fp[A] <- fp[B] - .else - SET_VREG rINST, %eax # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_long_to_float: /* 0x85 */ -/* File: x86/op_long_to_float.S */ -/* File: x86/fpcvt.S */ -/* - * Generic 32-bit FP conversion operation. - */ - /* unop vA, vB */ - movzbl rINSTbl, %ecx # ecx <- A+ - sarl $4, rINST # rINST <- B - fildll VREG_ADDRESS(rINST) # %st0 <- vB - andb $0xf, %cl # ecx <- A - - fstps VREG_ADDRESS(%ecx) # vA <- %st0 - .if 0 - CLEAR_WIDE_REF %ecx - .else - CLEAR_REF %ecx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_long_to_double: /* 0x86 */ -/* File: x86/op_long_to_double.S */ -/* File: x86/fpcvt.S */ -/* - * Generic 32-bit FP conversion operation. - */ - /* unop vA, vB */ - movzbl rINSTbl, %ecx # ecx <- A+ - sarl $4, rINST # rINST <- B - fildll VREG_ADDRESS(rINST) # %st0 <- vB - andb $0xf, %cl # ecx <- A - - fstpl VREG_ADDRESS(%ecx) # vA <- %st0 - .if 1 - CLEAR_WIDE_REF %ecx - .else - CLEAR_REF %ecx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_float_to_int: /* 0x87 */ -/* File: x86/op_float_to_int.S */ -/* File: x86/cvtfp_int.S */ -/* On fp to int conversions, Java requires that - * if the result > maxint, it should be clamped to maxint. If it is less - * than minint, it should be clamped to minint. If it is a nan, the result - * should be zero. Further, the rounding mode is to truncate. This model - * differs from what is delivered normally via the x86 fpu, so we have - * to play some games. - */ - /* float/double to int/long vA, vB */ - movzbl rINSTbl, %ecx # ecx <- A+ - sarl $4, rINST # rINST <- B - .if 0 - fldl VREG_ADDRESS(rINST) # %st0 <- vB - .else - flds VREG_ADDRESS(rINST) # %st0 <- vB - .endif - ftst - fnstcw LOCAL0(%esp) # remember original rounding mode - movzwl LOCAL0(%esp), %eax - movb $0xc, %ah - movw %ax, LOCAL0+2(%esp) - fldcw LOCAL0+2(%esp) # set "to zero" rounding mode - andb $0xf, %cl # ecx <- A - .if 0 - fistpll VREG_ADDRESS(%ecx) # convert and store - .else - fistpl VREG_ADDRESS(%ecx) # convert and store - .endif - fldcw LOCAL0(%esp) # restore previous rounding mode - .if 0 - movl $0x80000000, %eax - xorl VREG_HIGH_ADDRESS(%ecx), %eax - orl VREG_ADDRESS(%ecx), %eax - .else - cmpl $0x80000000, VREG_ADDRESS(%ecx) - .endif - je .Lop_float_to_int_special_case # fix up result - -.Lop_float_to_int_finish: - xor %eax, %eax - mov %eax, VREG_REF_ADDRESS(%ecx) - .if 0 - mov %eax, VREG_REF_HIGH_ADDRESS(%ecx) - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -.Lop_float_to_int_special_case: - fnstsw %ax - sahf - jp .Lop_float_to_int_isNaN - adcl $-1, VREG_ADDRESS(%ecx) - .if 0 - adcl $-1, VREG_HIGH_ADDRESS(%ecx) - .endif - jmp .Lop_float_to_int_finish -.Lop_float_to_int_isNaN: - movl $0, VREG_ADDRESS(%ecx) - .if 0 - movl $0, VREG_HIGH_ADDRESS(%ecx) - .endif - jmp .Lop_float_to_int_finish - - -/* ------------------------------ */ - .balign 128 -.L_op_float_to_long: /* 0x88 */ -/* File: x86/op_float_to_long.S */ -/* File: x86/cvtfp_int.S */ -/* On fp to int conversions, Java requires that - * if the result > maxint, it should be clamped to maxint. If it is less - * than minint, it should be clamped to minint. If it is a nan, the result - * should be zero. Further, the rounding mode is to truncate. This model - * differs from what is delivered normally via the x86 fpu, so we have - * to play some games. - */ - /* float/double to int/long vA, vB */ - movzbl rINSTbl, %ecx # ecx <- A+ - sarl $4, rINST # rINST <- B - .if 0 - fldl VREG_ADDRESS(rINST) # %st0 <- vB - .else - flds VREG_ADDRESS(rINST) # %st0 <- vB - .endif - ftst - fnstcw LOCAL0(%esp) # remember original rounding mode - movzwl LOCAL0(%esp), %eax - movb $0xc, %ah - movw %ax, LOCAL0+2(%esp) - fldcw LOCAL0+2(%esp) # set "to zero" rounding mode - andb $0xf, %cl # ecx <- A - .if 1 - fistpll VREG_ADDRESS(%ecx) # convert and store - .else - fistpl VREG_ADDRESS(%ecx) # convert and store - .endif - fldcw LOCAL0(%esp) # restore previous rounding mode - .if 1 - movl $0x80000000, %eax - xorl VREG_HIGH_ADDRESS(%ecx), %eax - orl VREG_ADDRESS(%ecx), %eax - .else - cmpl $0x80000000, VREG_ADDRESS(%ecx) - .endif - je .Lop_float_to_long_special_case # fix up result - -.Lop_float_to_long_finish: - xor %eax, %eax - mov %eax, VREG_REF_ADDRESS(%ecx) - .if 1 - mov %eax, VREG_REF_HIGH_ADDRESS(%ecx) - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -.Lop_float_to_long_special_case: - fnstsw %ax - sahf - jp .Lop_float_to_long_isNaN - adcl $-1, VREG_ADDRESS(%ecx) - .if 1 - adcl $-1, VREG_HIGH_ADDRESS(%ecx) - .endif - jmp .Lop_float_to_long_finish -.Lop_float_to_long_isNaN: - movl $0, VREG_ADDRESS(%ecx) - .if 1 - movl $0, VREG_HIGH_ADDRESS(%ecx) - .endif - jmp .Lop_float_to_long_finish - - -/* ------------------------------ */ - .balign 128 -.L_op_float_to_double: /* 0x89 */ -/* File: x86/op_float_to_double.S */ -/* File: x86/fpcvt.S */ -/* - * Generic 32-bit FP conversion operation. - */ - /* unop vA, vB */ - movzbl rINSTbl, %ecx # ecx <- A+ - sarl $4, rINST # rINST <- B - flds VREG_ADDRESS(rINST) # %st0 <- vB - andb $0xf, %cl # ecx <- A - - fstpl VREG_ADDRESS(%ecx) # vA <- %st0 - .if 1 - CLEAR_WIDE_REF %ecx - .else - CLEAR_REF %ecx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_double_to_int: /* 0x8a */ -/* File: x86/op_double_to_int.S */ -/* File: x86/cvtfp_int.S */ -/* On fp to int conversions, Java requires that - * if the result > maxint, it should be clamped to maxint. If it is less - * than minint, it should be clamped to minint. If it is a nan, the result - * should be zero. Further, the rounding mode is to truncate. This model - * differs from what is delivered normally via the x86 fpu, so we have - * to play some games. - */ - /* float/double to int/long vA, vB */ - movzbl rINSTbl, %ecx # ecx <- A+ - sarl $4, rINST # rINST <- B - .if 1 - fldl VREG_ADDRESS(rINST) # %st0 <- vB - .else - flds VREG_ADDRESS(rINST) # %st0 <- vB - .endif - ftst - fnstcw LOCAL0(%esp) # remember original rounding mode - movzwl LOCAL0(%esp), %eax - movb $0xc, %ah - movw %ax, LOCAL0+2(%esp) - fldcw LOCAL0+2(%esp) # set "to zero" rounding mode - andb $0xf, %cl # ecx <- A - .if 0 - fistpll VREG_ADDRESS(%ecx) # convert and store - .else - fistpl VREG_ADDRESS(%ecx) # convert and store - .endif - fldcw LOCAL0(%esp) # restore previous rounding mode - .if 0 - movl $0x80000000, %eax - xorl VREG_HIGH_ADDRESS(%ecx), %eax - orl VREG_ADDRESS(%ecx), %eax - .else - cmpl $0x80000000, VREG_ADDRESS(%ecx) - .endif - je .Lop_double_to_int_special_case # fix up result - -.Lop_double_to_int_finish: - xor %eax, %eax - mov %eax, VREG_REF_ADDRESS(%ecx) - .if 0 - mov %eax, VREG_REF_HIGH_ADDRESS(%ecx) - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -.Lop_double_to_int_special_case: - fnstsw %ax - sahf - jp .Lop_double_to_int_isNaN - adcl $-1, VREG_ADDRESS(%ecx) - .if 0 - adcl $-1, VREG_HIGH_ADDRESS(%ecx) - .endif - jmp .Lop_double_to_int_finish -.Lop_double_to_int_isNaN: - movl $0, VREG_ADDRESS(%ecx) - .if 0 - movl $0, VREG_HIGH_ADDRESS(%ecx) - .endif - jmp .Lop_double_to_int_finish - - -/* ------------------------------ */ - .balign 128 -.L_op_double_to_long: /* 0x8b */ -/* File: x86/op_double_to_long.S */ -/* File: x86/cvtfp_int.S */ -/* On fp to int conversions, Java requires that - * if the result > maxint, it should be clamped to maxint. If it is less - * than minint, it should be clamped to minint. If it is a nan, the result - * should be zero. Further, the rounding mode is to truncate. This model - * differs from what is delivered normally via the x86 fpu, so we have - * to play some games. - */ - /* float/double to int/long vA, vB */ - movzbl rINSTbl, %ecx # ecx <- A+ - sarl $4, rINST # rINST <- B - .if 1 - fldl VREG_ADDRESS(rINST) # %st0 <- vB - .else - flds VREG_ADDRESS(rINST) # %st0 <- vB - .endif - ftst - fnstcw LOCAL0(%esp) # remember original rounding mode - movzwl LOCAL0(%esp), %eax - movb $0xc, %ah - movw %ax, LOCAL0+2(%esp) - fldcw LOCAL0+2(%esp) # set "to zero" rounding mode - andb $0xf, %cl # ecx <- A - .if 1 - fistpll VREG_ADDRESS(%ecx) # convert and store - .else - fistpl VREG_ADDRESS(%ecx) # convert and store - .endif - fldcw LOCAL0(%esp) # restore previous rounding mode - .if 1 - movl $0x80000000, %eax - xorl VREG_HIGH_ADDRESS(%ecx), %eax - orl VREG_ADDRESS(%ecx), %eax - .else - cmpl $0x80000000, VREG_ADDRESS(%ecx) - .endif - je .Lop_double_to_long_special_case # fix up result - -.Lop_double_to_long_finish: - xor %eax, %eax - mov %eax, VREG_REF_ADDRESS(%ecx) - .if 1 - mov %eax, VREG_REF_HIGH_ADDRESS(%ecx) - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -.Lop_double_to_long_special_case: - fnstsw %ax - sahf - jp .Lop_double_to_long_isNaN - adcl $-1, VREG_ADDRESS(%ecx) - .if 1 - adcl $-1, VREG_HIGH_ADDRESS(%ecx) - .endif - jmp .Lop_double_to_long_finish -.Lop_double_to_long_isNaN: - movl $0, VREG_ADDRESS(%ecx) - .if 1 - movl $0, VREG_HIGH_ADDRESS(%ecx) - .endif - jmp .Lop_double_to_long_finish - - -/* ------------------------------ */ - .balign 128 -.L_op_double_to_float: /* 0x8c */ -/* File: x86/op_double_to_float.S */ -/* File: x86/fpcvt.S */ -/* - * Generic 32-bit FP conversion operation. - */ - /* unop vA, vB */ - movzbl rINSTbl, %ecx # ecx <- A+ - sarl $4, rINST # rINST <- B - fldl VREG_ADDRESS(rINST) # %st0 <- vB - andb $0xf, %cl # ecx <- A - - fstps VREG_ADDRESS(%ecx) # vA <- %st0 - .if 0 - CLEAR_WIDE_REF %ecx - .else - CLEAR_REF %ecx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_byte: /* 0x8d */ -/* File: x86/op_int_to_byte.S */ -/* File: x86/unop.S */ -/* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op eax". - */ - /* unop vA, vB */ - movzbl rINSTbl,%ecx # ecx <- A+ - sarl $4,rINST # rINST <- B - GET_VREG %eax, rINST # eax <- vB - andb $0xf,%cl # ecx <- A - movsbl %al, %eax - SET_VREG %eax, %ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_char: /* 0x8e */ -/* File: x86/op_int_to_char.S */ -/* File: x86/unop.S */ -/* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op eax". - */ - /* unop vA, vB */ - movzbl rINSTbl,%ecx # ecx <- A+ - sarl $4,rINST # rINST <- B - GET_VREG %eax, rINST # eax <- vB - andb $0xf,%cl # ecx <- A - movzwl %ax,%eax - SET_VREG %eax, %ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_short: /* 0x8f */ -/* File: x86/op_int_to_short.S */ -/* File: x86/unop.S */ -/* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op eax". - */ - /* unop vA, vB */ - movzbl rINSTbl,%ecx # ecx <- A+ - sarl $4,rINST # rINST <- B - GET_VREG %eax, rINST # eax <- vB - andb $0xf,%cl # ecx <- A - movswl %ax, %eax - SET_VREG %eax, %ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_add_int: /* 0x90 */ -/* File: x86/op_add_int.S */ -/* File: x86/binop.S */ -/* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = eax op (rFP,%ecx,4)". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int, sub-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB - addl (rFP,%ecx,4), %eax # ex: addl (rFP,%ecx,4),%eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_int: /* 0x91 */ -/* File: x86/op_sub_int.S */ -/* File: x86/binop.S */ -/* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = eax op (rFP,%ecx,4)". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int, sub-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB - subl (rFP,%ecx,4), %eax # ex: addl (rFP,%ecx,4),%eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int: /* 0x92 */ -/* File: x86/op_mul_int.S */ - /* - * 32-bit binary multiplication. - */ - /* mul vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB - mov rIBASE, LOCAL0(%esp) - imull (rFP,%ecx,4), %eax # trashes rIBASE/edx - mov LOCAL0(%esp), rIBASE - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_div_int: /* 0x93 */ -/* File: x86/op_div_int.S */ -/* File: x86/bindiv.S */ -/* - * 32-bit binary div/rem operation. Handles special case of op0=minint and - * op1=-1. - */ - /* div/rem vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB - GET_VREG %ecx, %ecx # ecx <- vCC - mov rIBASE, LOCAL0(%esp) - testl %ecx, %ecx - je common_errDivideByZero - movl %eax, %edx - orl %ecx, %edx - testl $0xFFFFFF00, %edx # If both arguments are less - # than 8-bit and +ve - jz .Lop_div_int_8 # Do 8-bit divide - testl $0xFFFF0000, %edx # If both arguments are less - # than 16-bit and +ve - jz .Lop_div_int_16 # Do 16-bit divide - cmpl $-1, %ecx - jne .Lop_div_int_32 - cmpl $0x80000000, %eax - jne .Lop_div_int_32 - movl $0x80000000, %eax - jmp .Lop_div_int_finish -.Lop_div_int_32: - cltd - idivl %ecx - jmp .Lop_div_int_finish -.Lop_div_int_8: - div %cl # 8-bit divide otherwise. - # Remainder in %ah, quotient in %al - .if 0 - movl %eax, %edx - shr $8, %edx - .else - andl $0x000000FF, %eax - .endif - jmp .Lop_div_int_finish -.Lop_div_int_16: - xorl %edx, %edx # Clear %edx before divide - div %cx -.Lop_div_int_finish: - SET_VREG %eax, rINST - mov LOCAL0(%esp), rIBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int: /* 0x94 */ -/* File: x86/op_rem_int.S */ -/* File: x86/bindiv.S */ -/* - * 32-bit binary div/rem operation. Handles special case of op0=minint and - * op1=-1. - */ - /* div/rem vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB - GET_VREG %ecx, %ecx # ecx <- vCC - mov rIBASE, LOCAL0(%esp) - testl %ecx, %ecx - je common_errDivideByZero - movl %eax, %edx - orl %ecx, %edx - testl $0xFFFFFF00, %edx # If both arguments are less - # than 8-bit and +ve - jz .Lop_rem_int_8 # Do 8-bit divide - testl $0xFFFF0000, %edx # If both arguments are less - # than 16-bit and +ve - jz .Lop_rem_int_16 # Do 16-bit divide - cmpl $-1, %ecx - jne .Lop_rem_int_32 - cmpl $0x80000000, %eax - jne .Lop_rem_int_32 - movl $0, rIBASE - jmp .Lop_rem_int_finish -.Lop_rem_int_32: - cltd - idivl %ecx - jmp .Lop_rem_int_finish -.Lop_rem_int_8: - div %cl # 8-bit divide otherwise. - # Remainder in %ah, quotient in %al - .if 1 - movl %eax, %edx - shr $8, %edx - .else - andl $0x000000FF, %eax - .endif - jmp .Lop_rem_int_finish -.Lop_rem_int_16: - xorl %edx, %edx # Clear %edx before divide - div %cx -.Lop_rem_int_finish: - SET_VREG rIBASE, rINST - mov LOCAL0(%esp), rIBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_and_int: /* 0x95 */ -/* File: x86/op_and_int.S */ -/* File: x86/binop.S */ -/* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = eax op (rFP,%ecx,4)". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int, sub-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB - andl (rFP,%ecx,4), %eax # ex: addl (rFP,%ecx,4),%eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_or_int: /* 0x96 */ -/* File: x86/op_or_int.S */ -/* File: x86/binop.S */ -/* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = eax op (rFP,%ecx,4)". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int, sub-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB - orl (rFP,%ecx,4), %eax # ex: addl (rFP,%ecx,4),%eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int: /* 0x97 */ -/* File: x86/op_xor_int.S */ -/* File: x86/binop.S */ -/* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = eax op (rFP,%ecx,4)". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int, sub-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB - xorl (rFP,%ecx,4), %eax # ex: addl (rFP,%ecx,4),%eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_shl_int: /* 0x98 */ -/* File: x86/op_shl_int.S */ -/* File: x86/binop1.S */ -/* - * Generic 32-bit binary operation in which both operands loaded to - * registers (op0 in eax, op1 in ecx). - */ - /* binop vAA, vBB, vCC */ - movzbl 2(rPC),%eax # eax <- BB - movzbl 3(rPC),%ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB - GET_VREG %ecx, %ecx # eax <- vBB - sall %cl, %eax # ex: addl %ecx,%eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_shr_int: /* 0x99 */ -/* File: x86/op_shr_int.S */ -/* File: x86/binop1.S */ -/* - * Generic 32-bit binary operation in which both operands loaded to - * registers (op0 in eax, op1 in ecx). - */ - /* binop vAA, vBB, vCC */ - movzbl 2(rPC),%eax # eax <- BB - movzbl 3(rPC),%ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB - GET_VREG %ecx, %ecx # eax <- vBB - sarl %cl, %eax # ex: addl %ecx,%eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_int: /* 0x9a */ -/* File: x86/op_ushr_int.S */ -/* File: x86/binop1.S */ -/* - * Generic 32-bit binary operation in which both operands loaded to - * registers (op0 in eax, op1 in ecx). - */ - /* binop vAA, vBB, vCC */ - movzbl 2(rPC),%eax # eax <- BB - movzbl 3(rPC),%ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB - GET_VREG %ecx, %ecx # eax <- vBB - shrl %cl, %eax # ex: addl %ecx,%eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_add_long: /* 0x9b */ -/* File: x86/op_add_long.S */ -/* File: x86/binopWide.S */ -/* - * Generic 64-bit binary operation. - */ - /* binop vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - movl rIBASE, LOCAL0(%esp) # save rIBASE - GET_VREG rIBASE, %eax # rIBASE <- v[BB+0] - GET_VREG_HIGH %eax, %eax # eax <- v[BB+1] - addl (rFP,%ecx,4), rIBASE # ex: addl (rFP,%ecx,4),rIBASE - adcl 4(rFP,%ecx,4), %eax # ex: adcl 4(rFP,%ecx,4),%eax - SET_VREG rIBASE, rINST # v[AA+0] <- rIBASE - movl LOCAL0(%esp), rIBASE # restore rIBASE - SET_VREG_HIGH %eax, rINST # v[AA+1] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_long: /* 0x9c */ -/* File: x86/op_sub_long.S */ -/* File: x86/binopWide.S */ -/* - * Generic 64-bit binary operation. - */ - /* binop vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - movl rIBASE, LOCAL0(%esp) # save rIBASE - GET_VREG rIBASE, %eax # rIBASE <- v[BB+0] - GET_VREG_HIGH %eax, %eax # eax <- v[BB+1] - subl (rFP,%ecx,4), rIBASE # ex: addl (rFP,%ecx,4),rIBASE - sbbl 4(rFP,%ecx,4), %eax # ex: adcl 4(rFP,%ecx,4),%eax - SET_VREG rIBASE, rINST # v[AA+0] <- rIBASE - movl LOCAL0(%esp), rIBASE # restore rIBASE - SET_VREG_HIGH %eax, rINST # v[AA+1] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_long: /* 0x9d */ -/* File: x86/op_mul_long.S */ -/* - * Signed 64-bit integer multiply. - * - * We could definately use more free registers for - * this code. We spill rINSTw (ebx), - * giving us eax, ebc, ecx and edx as computational - * temps. On top of that, we'll spill edi (rFP) - * for use as the vB pointer and esi (rPC) for use - * as the vC pointer. Yuck. - * - */ - /* mul-long vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- B - movzbl 3(rPC), %ecx # ecx <- C - mov rPC, LOCAL0(%esp) # save Interpreter PC - mov rFP, LOCAL1(%esp) # save FP - mov rIBASE, LOCAL2(%esp) # save rIBASE - leal (rFP,%eax,4), %esi # esi <- &v[B] - leal (rFP,%ecx,4), rFP # rFP <- &v[C] - movl 4(%esi), %ecx # ecx <- Bmsw - imull (rFP), %ecx # ecx <- (Bmsw*Clsw) - movl 4(rFP), %eax # eax <- Cmsw - imull (%esi), %eax # eax <- (Cmsw*Blsw) - addl %eax, %ecx # ecx <- (Bmsw*Clsw)+(Cmsw*Blsw) - movl (rFP), %eax # eax <- Clsw - mull (%esi) # eax <- (Clsw*Alsw) - mov LOCAL0(%esp), rPC # restore Interpreter PC - mov LOCAL1(%esp), rFP # restore FP - leal (%ecx,rIBASE), rIBASE # full result now in rIBASE:%eax - SET_VREG_HIGH rIBASE, rINST # v[B+1] <- rIBASE - mov LOCAL2(%esp), rIBASE # restore IBASE - SET_VREG %eax, rINST # v[B] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_div_long: /* 0x9e */ -/* File: x86/op_div_long.S */ -/* art_quick_* methods has quick abi, - * so use eax, ecx, edx, ebx for args - */ - /* div vAA, vBB, vCC */ - .extern art_quick_ldiv - mov rIBASE, LOCAL0(%esp) # save rIBASE/%edx - mov rINST, LOCAL1(%esp) # save rINST/%ebx - movzbl 3(rPC), %eax # eax <- CC - GET_VREG %ecx, %eax - GET_VREG_HIGH %ebx, %eax - movl %ecx, %edx - orl %ebx, %ecx - jz common_errDivideByZero - movzbl 2(rPC), %eax # eax <- BB - GET_VREG_HIGH %ecx, %eax - GET_VREG %eax, %eax - call SYMBOL(art_quick_ldiv) - mov LOCAL1(%esp), rINST # restore rINST/%ebx - SET_VREG_HIGH rIBASE, rINST - SET_VREG %eax, rINST - mov LOCAL0(%esp), rIBASE # restore rIBASE/%edx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_rem_long: /* 0x9f */ -/* File: x86/op_rem_long.S */ -/* File: x86/op_div_long.S */ -/* art_quick_* methods has quick abi, - * so use eax, ecx, edx, ebx for args - */ - /* div vAA, vBB, vCC */ - .extern art_quick_lmod - mov rIBASE, LOCAL0(%esp) # save rIBASE/%edx - mov rINST, LOCAL1(%esp) # save rINST/%ebx - movzbl 3(rPC), %eax # eax <- CC - GET_VREG %ecx, %eax - GET_VREG_HIGH %ebx, %eax - movl %ecx, %edx - orl %ebx, %ecx - jz common_errDivideByZero - movzbl 2(rPC), %eax # eax <- BB - GET_VREG_HIGH %ecx, %eax - GET_VREG %eax, %eax - call SYMBOL(art_quick_lmod) - mov LOCAL1(%esp), rINST # restore rINST/%ebx - SET_VREG_HIGH rIBASE, rINST - SET_VREG %eax, rINST - mov LOCAL0(%esp), rIBASE # restore rIBASE/%edx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_and_long: /* 0xa0 */ -/* File: x86/op_and_long.S */ -/* File: x86/binopWide.S */ -/* - * Generic 64-bit binary operation. - */ - /* binop vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - movl rIBASE, LOCAL0(%esp) # save rIBASE - GET_VREG rIBASE, %eax # rIBASE <- v[BB+0] - GET_VREG_HIGH %eax, %eax # eax <- v[BB+1] - andl (rFP,%ecx,4), rIBASE # ex: addl (rFP,%ecx,4),rIBASE - andl 4(rFP,%ecx,4), %eax # ex: adcl 4(rFP,%ecx,4),%eax - SET_VREG rIBASE, rINST # v[AA+0] <- rIBASE - movl LOCAL0(%esp), rIBASE # restore rIBASE - SET_VREG_HIGH %eax, rINST # v[AA+1] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_or_long: /* 0xa1 */ -/* File: x86/op_or_long.S */ -/* File: x86/binopWide.S */ -/* - * Generic 64-bit binary operation. - */ - /* binop vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - movl rIBASE, LOCAL0(%esp) # save rIBASE - GET_VREG rIBASE, %eax # rIBASE <- v[BB+0] - GET_VREG_HIGH %eax, %eax # eax <- v[BB+1] - orl (rFP,%ecx,4), rIBASE # ex: addl (rFP,%ecx,4),rIBASE - orl 4(rFP,%ecx,4), %eax # ex: adcl 4(rFP,%ecx,4),%eax - SET_VREG rIBASE, rINST # v[AA+0] <- rIBASE - movl LOCAL0(%esp), rIBASE # restore rIBASE - SET_VREG_HIGH %eax, rINST # v[AA+1] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_xor_long: /* 0xa2 */ -/* File: x86/op_xor_long.S */ -/* File: x86/binopWide.S */ -/* - * Generic 64-bit binary operation. - */ - /* binop vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - movl rIBASE, LOCAL0(%esp) # save rIBASE - GET_VREG rIBASE, %eax # rIBASE <- v[BB+0] - GET_VREG_HIGH %eax, %eax # eax <- v[BB+1] - xorl (rFP,%ecx,4), rIBASE # ex: addl (rFP,%ecx,4),rIBASE - xorl 4(rFP,%ecx,4), %eax # ex: adcl 4(rFP,%ecx,4),%eax - SET_VREG rIBASE, rINST # v[AA+0] <- rIBASE - movl LOCAL0(%esp), rIBASE # restore rIBASE - SET_VREG_HIGH %eax, rINST # v[AA+1] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_shl_long: /* 0xa3 */ -/* File: x86/op_shl_long.S */ -/* - * Long integer shift. This is different from the generic 32/64-bit - * binary operations because vAA/vBB are 64-bit but vCC (the shift - * distance) is 32-bit. Also, Dalvik requires us to mask off the low - * 6 bits of the shift distance. x86 shifts automatically mask off - * the low 5 bits of %cl, so have to handle the 64 > shiftcount > 31 - * case specially. - */ - /* shl-long vAA, vBB, vCC */ - /* ecx gets shift count */ - /* Need to spill rINST */ - /* rINSTw gets AA */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - movl rIBASE, LOCAL0(%esp) - GET_VREG_HIGH rIBASE, %eax # ecx <- v[BB+1] - GET_VREG %ecx, %ecx # ecx <- vCC - GET_VREG %eax, %eax # eax <- v[BB+0] - shldl %eax,rIBASE - sall %cl, %eax - testb $32, %cl - je 2f - movl %eax, rIBASE - xorl %eax, %eax -2: - SET_VREG_HIGH rIBASE, rINST # v[AA+1] <- rIBASE - movl LOCAL0(%esp), rIBASE - SET_VREG %eax, rINST # v[AA+0] <- %eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_shr_long: /* 0xa4 */ -/* File: x86/op_shr_long.S */ -/* - * Long integer shift. This is different from the generic 32/64-bit - * binary operations because vAA/vBB are 64-bit but vCC (the shift - * distance) is 32-bit. Also, Dalvik requires us to mask off the low - * 6 bits of the shift distance. x86 shifts automatically mask off - * the low 5 bits of %cl, so have to handle the 64 > shiftcount > 31 - * case specially. - */ - /* shr-long vAA, vBB, vCC */ - /* ecx gets shift count */ - /* Need to spill rIBASE */ - /* rINSTw gets AA */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - movl rIBASE, LOCAL0(%esp) - GET_VREG_HIGH rIBASE, %eax # rIBASE<- v[BB+1] - GET_VREG %ecx, %ecx # ecx <- vCC - GET_VREG %eax, %eax # eax <- v[BB+0] - shrdl rIBASE, %eax - sarl %cl, rIBASE - testb $32, %cl - je 2f - movl rIBASE, %eax - sarl $31, rIBASE -2: - SET_VREG_HIGH rIBASE, rINST # v[AA+1] <- rIBASE - movl LOCAL0(%esp), rIBASE - SET_VREG %eax, rINST # v[AA+0] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_long: /* 0xa5 */ -/* File: x86/op_ushr_long.S */ -/* - * Long integer shift. This is different from the generic 32/64-bit - * binary operations because vAA/vBB are 64-bit but vCC (the shift - * distance) is 32-bit. Also, Dalvik requires us to mask off the low - * 6 bits of the shift distance. x86 shifts automatically mask off - * the low 5 bits of %cl, so have to handle the 64 > shiftcount > 31 - * case specially. - */ - /* shr-long vAA, vBB, vCC */ - /* ecx gets shift count */ - /* Need to spill rIBASE */ - /* rINSTw gets AA */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - movl rIBASE, LOCAL0(%esp) - GET_VREG_HIGH rIBASE, %eax # rIBASE <- v[BB+1] - GET_VREG %ecx, %ecx # ecx <- vCC - GET_VREG %eax, %eax # eax <- v[BB+0] - shrdl rIBASE, %eax - shrl %cl, rIBASE - testb $32, %cl - je 2f - movl rIBASE, %eax - xorl rIBASE, rIBASE -2: - SET_VREG_HIGH rIBASE, rINST # v[AA+1] <- rIBASE - movl LOCAL0(%esp), rIBASE - SET_VREG %eax, rINST # v[BB+0] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_add_float: /* 0xa6 */ -/* File: x86/op_add_float.S */ -/* File: x86/sseBinop.S */ - movzbl 2(rPC), %ecx # ecx <- BB - movzbl 3(rPC), %eax # eax <- CC - movss VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src - addss VREG_ADDRESS(%eax), %xmm0 - movss %xmm0, VREG_ADDRESS(rINST) # vAA <- %xmm0 - pxor %xmm0, %xmm0 - movss %xmm0, VREG_REF_ADDRESS(rINST) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_float: /* 0xa7 */ -/* File: x86/op_sub_float.S */ -/* File: x86/sseBinop.S */ - movzbl 2(rPC), %ecx # ecx <- BB - movzbl 3(rPC), %eax # eax <- CC - movss VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src - subss VREG_ADDRESS(%eax), %xmm0 - movss %xmm0, VREG_ADDRESS(rINST) # vAA <- %xmm0 - pxor %xmm0, %xmm0 - movss %xmm0, VREG_REF_ADDRESS(rINST) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_float: /* 0xa8 */ -/* File: x86/op_mul_float.S */ -/* File: x86/sseBinop.S */ - movzbl 2(rPC), %ecx # ecx <- BB - movzbl 3(rPC), %eax # eax <- CC - movss VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src - mulss VREG_ADDRESS(%eax), %xmm0 - movss %xmm0, VREG_ADDRESS(rINST) # vAA <- %xmm0 - pxor %xmm0, %xmm0 - movss %xmm0, VREG_REF_ADDRESS(rINST) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_div_float: /* 0xa9 */ -/* File: x86/op_div_float.S */ -/* File: x86/sseBinop.S */ - movzbl 2(rPC), %ecx # ecx <- BB - movzbl 3(rPC), %eax # eax <- CC - movss VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src - divss VREG_ADDRESS(%eax), %xmm0 - movss %xmm0, VREG_ADDRESS(rINST) # vAA <- %xmm0 - pxor %xmm0, %xmm0 - movss %xmm0, VREG_REF_ADDRESS(rINST) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_float: /* 0xaa */ -/* File: x86/op_rem_float.S */ - /* rem_float vAA, vBB, vCC */ - movzbl 3(rPC), %ecx # ecx <- BB - movzbl 2(rPC), %eax # eax <- CC - flds VREG_ADDRESS(%ecx) # vBB to fp stack - flds VREG_ADDRESS(%eax) # vCC to fp stack -1: - fprem - fstsw %ax - sahf - jp 1b - fstp %st(1) - fstps VREG_ADDRESS(rINST) # %st to vAA - CLEAR_REF rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_add_double: /* 0xab */ -/* File: x86/op_add_double.S */ -/* File: x86/sseBinop.S */ - movzbl 2(rPC), %ecx # ecx <- BB - movzbl 3(rPC), %eax # eax <- CC - movsd VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src - addsd VREG_ADDRESS(%eax), %xmm0 - movsd %xmm0, VREG_ADDRESS(rINST) # vAA <- %xmm0 - pxor %xmm0, %xmm0 - movsd %xmm0, VREG_REF_ADDRESS(rINST) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_double: /* 0xac */ -/* File: x86/op_sub_double.S */ -/* File: x86/sseBinop.S */ - movzbl 2(rPC), %ecx # ecx <- BB - movzbl 3(rPC), %eax # eax <- CC - movsd VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src - subsd VREG_ADDRESS(%eax), %xmm0 - movsd %xmm0, VREG_ADDRESS(rINST) # vAA <- %xmm0 - pxor %xmm0, %xmm0 - movsd %xmm0, VREG_REF_ADDRESS(rINST) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_double: /* 0xad */ -/* File: x86/op_mul_double.S */ -/* File: x86/sseBinop.S */ - movzbl 2(rPC), %ecx # ecx <- BB - movzbl 3(rPC), %eax # eax <- CC - movsd VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src - mulsd VREG_ADDRESS(%eax), %xmm0 - movsd %xmm0, VREG_ADDRESS(rINST) # vAA <- %xmm0 - pxor %xmm0, %xmm0 - movsd %xmm0, VREG_REF_ADDRESS(rINST) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_div_double: /* 0xae */ -/* File: x86/op_div_double.S */ -/* File: x86/sseBinop.S */ - movzbl 2(rPC), %ecx # ecx <- BB - movzbl 3(rPC), %eax # eax <- CC - movsd VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src - divsd VREG_ADDRESS(%eax), %xmm0 - movsd %xmm0, VREG_ADDRESS(rINST) # vAA <- %xmm0 - pxor %xmm0, %xmm0 - movsd %xmm0, VREG_REF_ADDRESS(rINST) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_double: /* 0xaf */ -/* File: x86/op_rem_double.S */ - /* rem_double vAA, vBB, vCC */ - movzbl 3(rPC), %ecx # ecx <- BB - movzbl 2(rPC), %eax # eax <- CC - fldl VREG_ADDRESS(%ecx) # %st1 <- fp[vBB] - fldl VREG_ADDRESS(%eax) # %st0 <- fp[vCC] -1: - fprem - fstsw %ax - sahf - jp 1b - fstp %st(1) - fstpl VREG_ADDRESS(rINST) # fp[vAA] <- %st - CLEAR_WIDE_REF rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_add_int_2addr: /* 0xb0 */ -/* File: x86/op_add_int_2addr.S */ -/* File: x86/binop2addr.S */ -/* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an instruction or a function call. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - movzx rINSTbl, %ecx # ecx <- A+ - sarl $4, rINST # rINST <- B - GET_VREG %eax, rINST # eax <- vB - andb $0xf, %cl # ecx <- A - addl %eax, (rFP,%ecx,4) # for ex: addl %eax,(rFP,%ecx,4) - CLEAR_REF %ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_int_2addr: /* 0xb1 */ -/* File: x86/op_sub_int_2addr.S */ -/* File: x86/binop2addr.S */ -/* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an instruction or a function call. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - movzx rINSTbl, %ecx # ecx <- A+ - sarl $4, rINST # rINST <- B - GET_VREG %eax, rINST # eax <- vB - andb $0xf, %cl # ecx <- A - subl %eax, (rFP,%ecx,4) # for ex: addl %eax,(rFP,%ecx,4) - CLEAR_REF %ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int_2addr: /* 0xb2 */ -/* File: x86/op_mul_int_2addr.S */ - /* mul vA, vB */ - movzx rINSTbl, %ecx # ecx <- A+ - sarl $4, rINST # rINST <- B - GET_VREG %eax, rINST # eax <- vB - andb $0xf, %cl # ecx <- A - movl rIBASE, rINST - imull (rFP,%ecx,4), %eax # trashes rIBASE/edx - movl rINST, rIBASE - SET_VREG %eax, %ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_div_int_2addr: /* 0xb3 */ -/* File: x86/op_div_int_2addr.S */ -/* File: x86/bindiv2addr.S */ -/* - * 32-bit binary div/rem operation. Handles special case of op0=minint and - * op1=-1. - */ - /* div/rem/2addr vA, vB */ - movzx rINSTbl, %ecx # eax <- BA - mov rIBASE, LOCAL0(%esp) - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # eax <- vBB - andb $0xf, rINSTbl # rINST <- A - GET_VREG %eax, rINST # eax <- vBB - testl %ecx, %ecx - je common_errDivideByZero - cmpl $-1, %ecx - jne .Lop_div_int_2addr_continue_div2addr - cmpl $0x80000000, %eax - jne .Lop_div_int_2addr_continue_div2addr - movl $0x80000000, %eax - SET_VREG %eax, rINST - mov LOCAL0(%esp), rIBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -.Lop_div_int_2addr_continue_div2addr: - cltd - idivl %ecx - SET_VREG %eax, rINST - mov LOCAL0(%esp), rIBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int_2addr: /* 0xb4 */ -/* File: x86/op_rem_int_2addr.S */ -/* File: x86/bindiv2addr.S */ -/* - * 32-bit binary div/rem operation. Handles special case of op0=minint and - * op1=-1. - */ - /* div/rem/2addr vA, vB */ - movzx rINSTbl, %ecx # eax <- BA - mov rIBASE, LOCAL0(%esp) - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # eax <- vBB - andb $0xf, rINSTbl # rINST <- A - GET_VREG %eax, rINST # eax <- vBB - testl %ecx, %ecx - je common_errDivideByZero - cmpl $-1, %ecx - jne .Lop_rem_int_2addr_continue_div2addr - cmpl $0x80000000, %eax - jne .Lop_rem_int_2addr_continue_div2addr - movl $0, rIBASE - SET_VREG rIBASE, rINST - mov LOCAL0(%esp), rIBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -.Lop_rem_int_2addr_continue_div2addr: - cltd - idivl %ecx - SET_VREG rIBASE, rINST - mov LOCAL0(%esp), rIBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_and_int_2addr: /* 0xb5 */ -/* File: x86/op_and_int_2addr.S */ -/* File: x86/binop2addr.S */ -/* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an instruction or a function call. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - movzx rINSTbl, %ecx # ecx <- A+ - sarl $4, rINST # rINST <- B - GET_VREG %eax, rINST # eax <- vB - andb $0xf, %cl # ecx <- A - andl %eax, (rFP,%ecx,4) # for ex: addl %eax,(rFP,%ecx,4) - CLEAR_REF %ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_or_int_2addr: /* 0xb6 */ -/* File: x86/op_or_int_2addr.S */ -/* File: x86/binop2addr.S */ -/* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an instruction or a function call. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - movzx rINSTbl, %ecx # ecx <- A+ - sarl $4, rINST # rINST <- B - GET_VREG %eax, rINST # eax <- vB - andb $0xf, %cl # ecx <- A - orl %eax, (rFP,%ecx,4) # for ex: addl %eax,(rFP,%ecx,4) - CLEAR_REF %ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int_2addr: /* 0xb7 */ -/* File: x86/op_xor_int_2addr.S */ -/* File: x86/binop2addr.S */ -/* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an instruction or a function call. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - movzx rINSTbl, %ecx # ecx <- A+ - sarl $4, rINST # rINST <- B - GET_VREG %eax, rINST # eax <- vB - andb $0xf, %cl # ecx <- A - xorl %eax, (rFP,%ecx,4) # for ex: addl %eax,(rFP,%ecx,4) - CLEAR_REF %ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_shl_int_2addr: /* 0xb8 */ -/* File: x86/op_shl_int_2addr.S */ -/* File: x86/shop2addr.S */ -/* - * Generic 32-bit "shift/2addr" operation. - */ - /* shift/2addr vA, vB */ - movzx rINSTbl, %ecx # eax <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # eax <- vBB - andb $0xf, rINSTbl # rINST <- A - GET_VREG %eax, rINST # eax <- vAA - sall %cl, %eax # ex: sarl %cl, %eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_shr_int_2addr: /* 0xb9 */ -/* File: x86/op_shr_int_2addr.S */ -/* File: x86/shop2addr.S */ -/* - * Generic 32-bit "shift/2addr" operation. - */ - /* shift/2addr vA, vB */ - movzx rINSTbl, %ecx # eax <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # eax <- vBB - andb $0xf, rINSTbl # rINST <- A - GET_VREG %eax, rINST # eax <- vAA - sarl %cl, %eax # ex: sarl %cl, %eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_int_2addr: /* 0xba */ -/* File: x86/op_ushr_int_2addr.S */ -/* File: x86/shop2addr.S */ -/* - * Generic 32-bit "shift/2addr" operation. - */ - /* shift/2addr vA, vB */ - movzx rINSTbl, %ecx # eax <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # eax <- vBB - andb $0xf, rINSTbl # rINST <- A - GET_VREG %eax, rINST # eax <- vAA - shrl %cl, %eax # ex: sarl %cl, %eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_add_long_2addr: /* 0xbb */ -/* File: x86/op_add_long_2addr.S */ -/* File: x86/binopWide2addr.S */ -/* - * Generic 64-bit binary operation. - */ - /* binop/2addr vA, vB */ - movzbl rINSTbl, %ecx # ecx<- BA - sarl $4, %ecx # ecx<- B - GET_VREG %eax, %ecx # eax<- v[B+0] - GET_VREG_HIGH %ecx, %ecx # eax<- v[B+1] - andb $0xF, rINSTbl # rINST<- A - addl %eax, (rFP,rINST,4) # ex: addl %eax,(rFP,rINST,4) - adcl %ecx, 4(rFP,rINST,4) # ex: adcl %ecx,4(rFP,rINST,4) - CLEAR_WIDE_REF rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_long_2addr: /* 0xbc */ -/* File: x86/op_sub_long_2addr.S */ -/* File: x86/binopWide2addr.S */ -/* - * Generic 64-bit binary operation. - */ - /* binop/2addr vA, vB */ - movzbl rINSTbl, %ecx # ecx<- BA - sarl $4, %ecx # ecx<- B - GET_VREG %eax, %ecx # eax<- v[B+0] - GET_VREG_HIGH %ecx, %ecx # eax<- v[B+1] - andb $0xF, rINSTbl # rINST<- A - subl %eax, (rFP,rINST,4) # ex: addl %eax,(rFP,rINST,4) - sbbl %ecx, 4(rFP,rINST,4) # ex: adcl %ecx,4(rFP,rINST,4) - CLEAR_WIDE_REF rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_long_2addr: /* 0xbd */ -/* File: x86/op_mul_long_2addr.S */ -/* - * Signed 64-bit integer multiply, 2-addr version - * - * We could definately use more free registers for - * this code. We must spill %edx (rIBASE) because it - * is used by imul. We'll also spill rINST (ebx), - * giving us eax, ebc, ecx and rIBASE as computational - * temps. On top of that, we'll spill %esi (edi) - * for use as the vA pointer and rFP (esi) for use - * as the vB pointer. Yuck. - */ - /* mul-long/2addr vA, vB */ - movzbl rINSTbl, %eax # eax <- BA - andb $0xf, %al # eax <- A - CLEAR_WIDE_REF %eax # clear refs in advance - sarl $4, rINST # rINST <- B - mov rPC, LOCAL0(%esp) # save Interpreter PC - mov rFP, LOCAL1(%esp) # save FP - mov rIBASE, LOCAL2(%esp) # save rIBASE - leal (rFP,%eax,4), %esi # esi <- &v[A] - leal (rFP,rINST,4), rFP # rFP <- &v[B] - movl 4(%esi), %ecx # ecx <- Amsw - imull (rFP), %ecx # ecx <- (Amsw*Blsw) - movl 4(rFP), %eax # eax <- Bmsw - imull (%esi), %eax # eax <- (Bmsw*Alsw) - addl %eax, %ecx # ecx <- (Amsw*Blsw)+(Bmsw*Alsw) - movl (rFP), %eax # eax <- Blsw - mull (%esi) # eax <- (Blsw*Alsw) - leal (%ecx,rIBASE), rIBASE # full result now in %edx:%eax - movl rIBASE, 4(%esi) # v[A+1] <- rIBASE - movl %eax, (%esi) # v[A] <- %eax - mov LOCAL0(%esp), rPC # restore Interpreter PC - mov LOCAL2(%esp), rIBASE # restore IBASE - mov LOCAL1(%esp), rFP # restore FP - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_div_long_2addr: /* 0xbe */ -/* File: x86/op_div_long_2addr.S */ -/* art_quick_* methods has quick abi, - * so use eax, ecx, edx, ebx for args - */ - /* div/2addr vA, vB */ - .extern art_quick_ldiv - mov rIBASE, LOCAL0(%esp) # save rIBASE/%edx - movzbl rINSTbl, %eax - shrl $4, %eax # eax <- B - andb $0xf, rINSTbl # rINST <- A - mov rINST, LOCAL1(%esp) # save rINST/%ebx - movl %ebx, %ecx - GET_VREG %edx, %eax - GET_VREG_HIGH %ebx, %eax - movl %edx, %eax - orl %ebx, %eax - jz common_errDivideByZero - GET_VREG %eax, %ecx - GET_VREG_HIGH %ecx, %ecx - call SYMBOL(art_quick_ldiv) - mov LOCAL1(%esp), rINST # restore rINST/%ebx - SET_VREG_HIGH rIBASE, rINST - SET_VREG %eax, rINST - mov LOCAL0(%esp), rIBASE # restore rIBASE/%edx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_rem_long_2addr: /* 0xbf */ -/* File: x86/op_rem_long_2addr.S */ -/* File: x86/op_div_long_2addr.S */ -/* art_quick_* methods has quick abi, - * so use eax, ecx, edx, ebx for args - */ - /* div/2addr vA, vB */ - .extern art_quick_lmod - mov rIBASE, LOCAL0(%esp) # save rIBASE/%edx - movzbl rINSTbl, %eax - shrl $4, %eax # eax <- B - andb $0xf, rINSTbl # rINST <- A - mov rINST, LOCAL1(%esp) # save rINST/%ebx - movl %ebx, %ecx - GET_VREG %edx, %eax - GET_VREG_HIGH %ebx, %eax - movl %edx, %eax - orl %ebx, %eax - jz common_errDivideByZero - GET_VREG %eax, %ecx - GET_VREG_HIGH %ecx, %ecx - call SYMBOL(art_quick_lmod) - mov LOCAL1(%esp), rINST # restore rINST/%ebx - SET_VREG_HIGH rIBASE, rINST - SET_VREG %eax, rINST - mov LOCAL0(%esp), rIBASE # restore rIBASE/%edx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_and_long_2addr: /* 0xc0 */ -/* File: x86/op_and_long_2addr.S */ -/* File: x86/binopWide2addr.S */ -/* - * Generic 64-bit binary operation. - */ - /* binop/2addr vA, vB */ - movzbl rINSTbl, %ecx # ecx<- BA - sarl $4, %ecx # ecx<- B - GET_VREG %eax, %ecx # eax<- v[B+0] - GET_VREG_HIGH %ecx, %ecx # eax<- v[B+1] - andb $0xF, rINSTbl # rINST<- A - andl %eax, (rFP,rINST,4) # ex: addl %eax,(rFP,rINST,4) - andl %ecx, 4(rFP,rINST,4) # ex: adcl %ecx,4(rFP,rINST,4) - CLEAR_WIDE_REF rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_or_long_2addr: /* 0xc1 */ -/* File: x86/op_or_long_2addr.S */ -/* File: x86/binopWide2addr.S */ -/* - * Generic 64-bit binary operation. - */ - /* binop/2addr vA, vB */ - movzbl rINSTbl, %ecx # ecx<- BA - sarl $4, %ecx # ecx<- B - GET_VREG %eax, %ecx # eax<- v[B+0] - GET_VREG_HIGH %ecx, %ecx # eax<- v[B+1] - andb $0xF, rINSTbl # rINST<- A - orl %eax, (rFP,rINST,4) # ex: addl %eax,(rFP,rINST,4) - orl %ecx, 4(rFP,rINST,4) # ex: adcl %ecx,4(rFP,rINST,4) - CLEAR_WIDE_REF rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_xor_long_2addr: /* 0xc2 */ -/* File: x86/op_xor_long_2addr.S */ -/* File: x86/binopWide2addr.S */ -/* - * Generic 64-bit binary operation. - */ - /* binop/2addr vA, vB */ - movzbl rINSTbl, %ecx # ecx<- BA - sarl $4, %ecx # ecx<- B - GET_VREG %eax, %ecx # eax<- v[B+0] - GET_VREG_HIGH %ecx, %ecx # eax<- v[B+1] - andb $0xF, rINSTbl # rINST<- A - xorl %eax, (rFP,rINST,4) # ex: addl %eax,(rFP,rINST,4) - xorl %ecx, 4(rFP,rINST,4) # ex: adcl %ecx,4(rFP,rINST,4) - CLEAR_WIDE_REF rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_shl_long_2addr: /* 0xc3 */ -/* File: x86/op_shl_long_2addr.S */ -/* - * Long integer shift, 2addr version. vA is 64-bit value/result, vB is - * 32-bit shift distance. - */ - /* shl-long/2addr vA, vB */ - /* ecx gets shift count */ - /* Need to spill rIBASE */ - /* rINSTw gets AA */ - movzbl rINSTbl, %ecx # ecx <- BA - andb $0xf, rINSTbl # rINST <- A - GET_VREG %eax, rINST # eax <- v[AA+0] - sarl $4, %ecx # ecx <- B - movl rIBASE, LOCAL0(%esp) - GET_VREG_HIGH rIBASE, rINST # rIBASE <- v[AA+1] - GET_VREG %ecx, %ecx # ecx <- vBB - shldl %eax, rIBASE - sall %cl, %eax - testb $32, %cl - je 2f - movl %eax, rIBASE - xorl %eax, %eax -2: - SET_VREG_HIGH rIBASE, rINST # v[AA+1] <- rIBASE - movl LOCAL0(%esp), rIBASE - SET_VREG %eax, rINST # v[AA+0] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_shr_long_2addr: /* 0xc4 */ -/* File: x86/op_shr_long_2addr.S */ -/* - * Long integer shift, 2addr version. vA is 64-bit value/result, vB is - * 32-bit shift distance. - */ - /* shl-long/2addr vA, vB */ - /* ecx gets shift count */ - /* Need to spill rIBASE */ - /* rINSTw gets AA */ - movzbl rINSTbl, %ecx # ecx <- BA - andb $0xf, rINSTbl # rINST <- A - GET_VREG %eax, rINST # eax <- v[AA+0] - sarl $4, %ecx # ecx <- B - movl rIBASE, LOCAL0(%esp) - GET_VREG_HIGH rIBASE, rINST # rIBASE <- v[AA+1] - GET_VREG %ecx, %ecx # ecx <- vBB - shrdl rIBASE, %eax - sarl %cl, rIBASE - testb $32, %cl - je 2f - movl rIBASE, %eax - sarl $31, rIBASE -2: - SET_VREG_HIGH rIBASE, rINST # v[AA+1] <- rIBASE - movl LOCAL0(%esp), rIBASE - SET_VREG %eax, rINST # v[AA+0] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_long_2addr: /* 0xc5 */ -/* File: x86/op_ushr_long_2addr.S */ -/* - * Long integer shift, 2addr version. vA is 64-bit value/result, vB is - * 32-bit shift distance. - */ - /* shl-long/2addr vA, vB */ - /* ecx gets shift count */ - /* Need to spill rIBASE */ - /* rINSTw gets AA */ - movzbl rINSTbl, %ecx # ecx <- BA - andb $0xf, rINSTbl # rINST <- A - GET_VREG %eax, rINST # eax <- v[AA+0] - sarl $4, %ecx # ecx <- B - movl rIBASE, LOCAL0(%esp) - GET_VREG_HIGH rIBASE, rINST # rIBASE <- v[AA+1] - GET_VREG %ecx, %ecx # ecx <- vBB - shrdl rIBASE, %eax - shrl %cl, rIBASE - testb $32, %cl - je 2f - movl rIBASE, %eax - xorl rIBASE, rIBASE -2: - SET_VREG_HIGH rIBASE, rINST # v[AA+1] <- rIBASE - movl LOCAL0(%esp), rIBASE - SET_VREG %eax, rINST # v[AA+0] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_add_float_2addr: /* 0xc6 */ -/* File: x86/op_add_float_2addr.S */ -/* File: x86/sseBinop2Addr.S */ - movzx rINSTbl, %ecx # ecx <- A+ - andl $0xf, %ecx # ecx <- A - movss VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src - sarl $4, rINST # rINST<- B - addss VREG_ADDRESS(rINST), %xmm0 - movss %xmm0, VREG_ADDRESS(%ecx) # vAA<- %xmm0 - pxor %xmm0, %xmm0 - movss %xmm0, VREG_REF_ADDRESS(rINST) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_float_2addr: /* 0xc7 */ -/* File: x86/op_sub_float_2addr.S */ -/* File: x86/sseBinop2Addr.S */ - movzx rINSTbl, %ecx # ecx <- A+ - andl $0xf, %ecx # ecx <- A - movss VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src - sarl $4, rINST # rINST<- B - subss VREG_ADDRESS(rINST), %xmm0 - movss %xmm0, VREG_ADDRESS(%ecx) # vAA<- %xmm0 - pxor %xmm0, %xmm0 - movss %xmm0, VREG_REF_ADDRESS(rINST) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_float_2addr: /* 0xc8 */ -/* File: x86/op_mul_float_2addr.S */ -/* File: x86/sseBinop2Addr.S */ - movzx rINSTbl, %ecx # ecx <- A+ - andl $0xf, %ecx # ecx <- A - movss VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src - sarl $4, rINST # rINST<- B - mulss VREG_ADDRESS(rINST), %xmm0 - movss %xmm0, VREG_ADDRESS(%ecx) # vAA<- %xmm0 - pxor %xmm0, %xmm0 - movss %xmm0, VREG_REF_ADDRESS(rINST) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_div_float_2addr: /* 0xc9 */ -/* File: x86/op_div_float_2addr.S */ -/* File: x86/sseBinop2Addr.S */ - movzx rINSTbl, %ecx # ecx <- A+ - andl $0xf, %ecx # ecx <- A - movss VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src - sarl $4, rINST # rINST<- B - divss VREG_ADDRESS(rINST), %xmm0 - movss %xmm0, VREG_ADDRESS(%ecx) # vAA<- %xmm0 - pxor %xmm0, %xmm0 - movss %xmm0, VREG_REF_ADDRESS(rINST) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_float_2addr: /* 0xca */ -/* File: x86/op_rem_float_2addr.S */ - /* rem_float/2addr vA, vB */ - movzx rINSTbl, %ecx # ecx <- A+ - sarl $4, rINST # rINST <- B - flds VREG_ADDRESS(rINST) # vB to fp stack - andb $0xf, %cl # ecx <- A - flds VREG_ADDRESS(%ecx) # vA to fp stack -1: - fprem - fstsw %ax - sahf - jp 1b - fstp %st(1) - fstps VREG_ADDRESS(%ecx) # %st to vA - CLEAR_REF %ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_add_double_2addr: /* 0xcb */ -/* File: x86/op_add_double_2addr.S */ -/* File: x86/sseBinop2Addr.S */ - movzx rINSTbl, %ecx # ecx <- A+ - andl $0xf, %ecx # ecx <- A - movsd VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src - sarl $4, rINST # rINST<- B - addsd VREG_ADDRESS(rINST), %xmm0 - movsd %xmm0, VREG_ADDRESS(%ecx) # vAA<- %xmm0 - pxor %xmm0, %xmm0 - movsd %xmm0, VREG_REF_ADDRESS(rINST) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_double_2addr: /* 0xcc */ -/* File: x86/op_sub_double_2addr.S */ -/* File: x86/sseBinop2Addr.S */ - movzx rINSTbl, %ecx # ecx <- A+ - andl $0xf, %ecx # ecx <- A - movsd VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src - sarl $4, rINST # rINST<- B - subsd VREG_ADDRESS(rINST), %xmm0 - movsd %xmm0, VREG_ADDRESS(%ecx) # vAA<- %xmm0 - pxor %xmm0, %xmm0 - movsd %xmm0, VREG_REF_ADDRESS(rINST) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_double_2addr: /* 0xcd */ -/* File: x86/op_mul_double_2addr.S */ -/* File: x86/sseBinop2Addr.S */ - movzx rINSTbl, %ecx # ecx <- A+ - andl $0xf, %ecx # ecx <- A - movsd VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src - sarl $4, rINST # rINST<- B - mulsd VREG_ADDRESS(rINST), %xmm0 - movsd %xmm0, VREG_ADDRESS(%ecx) # vAA<- %xmm0 - pxor %xmm0, %xmm0 - movsd %xmm0, VREG_REF_ADDRESS(rINST) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_div_double_2addr: /* 0xce */ -/* File: x86/op_div_double_2addr.S */ -/* File: x86/sseBinop2Addr.S */ - movzx rINSTbl, %ecx # ecx <- A+ - andl $0xf, %ecx # ecx <- A - movsd VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src - sarl $4, rINST # rINST<- B - divsd VREG_ADDRESS(rINST), %xmm0 - movsd %xmm0, VREG_ADDRESS(%ecx) # vAA<- %xmm0 - pxor %xmm0, %xmm0 - movsd %xmm0, VREG_REF_ADDRESS(rINST) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_double_2addr: /* 0xcf */ -/* File: x86/op_rem_double_2addr.S */ - /* rem_double/2addr vA, vB */ - movzx rINSTbl, %ecx # ecx <- A+ - sarl $4, rINST # rINST <- B - fldl VREG_ADDRESS(rINST) # vB to fp stack - andb $0xf, %cl # ecx <- A - fldl VREG_ADDRESS(%ecx) # vA to fp stack -1: - fprem - fstsw %ax - sahf - jp 1b - fstp %st(1) - fstpl VREG_ADDRESS(%ecx) # %st to vA - CLEAR_WIDE_REF %ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_add_int_lit16: /* 0xd0 */ -/* File: x86/op_add_int_lit16.S */ -/* File: x86/binopLit16.S */ -/* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int/lit16, rsub-int, - * and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - movzbl rINSTbl, %eax # eax <- 000000BA - sarl $4, %eax # eax <- B - GET_VREG %eax, %eax # eax <- vB - movswl 2(rPC), %ecx # ecx <- ssssCCCC - andb $0xf, rINSTbl # rINST <- A - addl %ecx, %eax # for example: addl %ecx, %eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_rsub_int: /* 0xd1 */ -/* File: x86/op_rsub_int.S */ -/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ -/* File: x86/binopLit16.S */ -/* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int/lit16, rsub-int, - * and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - movzbl rINSTbl, %eax # eax <- 000000BA - sarl $4, %eax # eax <- B - GET_VREG %eax, %eax # eax <- vB - movswl 2(rPC), %ecx # ecx <- ssssCCCC - andb $0xf, rINSTbl # rINST <- A - subl %eax, %ecx # for example: addl %ecx, %eax - SET_VREG %ecx, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int_lit16: /* 0xd2 */ -/* File: x86/op_mul_int_lit16.S */ - /* mul/lit16 vA, vB, #+CCCC */ - /* Need A in rINST, ssssCCCC in ecx, vB in eax */ - movzbl rINSTbl, %eax # eax <- 000000BA - sarl $4, %eax # eax <- B - GET_VREG %eax, %eax # eax <- vB - movl rIBASE, %ecx - movswl 2(rPC), rIBASE # rIBASE <- ssssCCCC - andb $0xf, rINSTbl # rINST <- A - imull rIBASE, %eax # trashes rIBASE/edx - movl %ecx, rIBASE - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_div_int_lit16: /* 0xd3 */ -/* File: x86/op_div_int_lit16.S */ -/* File: x86/bindivLit16.S */ -/* - * 32-bit binary div/rem operation. Handles special case of op0=minint and - * op1=-1. - */ - /* div/rem/lit16 vA, vB, #+CCCC */ - /* Need A in rINST, ssssCCCC in ecx, vB in eax */ - movzbl rINSTbl, %eax # eax <- 000000BA - sarl $4, %eax # eax <- B - GET_VREG %eax, %eax # eax <- vB - movswl 2(rPC), %ecx # ecx <- ssssCCCC - andb $0xf, rINSTbl # rINST <- A - testl %ecx, %ecx - je common_errDivideByZero - cmpl $-1, %ecx - jne .Lop_div_int_lit16_continue_div - cmpl $0x80000000, %eax - jne .Lop_div_int_lit16_continue_div - movl $0x80000000, %eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -.Lop_div_int_lit16_continue_div: - mov rIBASE, LOCAL0(%esp) - cltd - idivl %ecx - SET_VREG %eax, rINST - mov LOCAL0(%esp), rIBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int_lit16: /* 0xd4 */ -/* File: x86/op_rem_int_lit16.S */ -/* File: x86/bindivLit16.S */ -/* - * 32-bit binary div/rem operation. Handles special case of op0=minint and - * op1=-1. - */ - /* div/rem/lit16 vA, vB, #+CCCC */ - /* Need A in rINST, ssssCCCC in ecx, vB in eax */ - movzbl rINSTbl, %eax # eax <- 000000BA - sarl $4, %eax # eax <- B - GET_VREG %eax, %eax # eax <- vB - movswl 2(rPC), %ecx # ecx <- ssssCCCC - andb $0xf, rINSTbl # rINST <- A - testl %ecx, %ecx - je common_errDivideByZero - cmpl $-1, %ecx - jne .Lop_rem_int_lit16_continue_div - cmpl $0x80000000, %eax - jne .Lop_rem_int_lit16_continue_div - movl $0, %eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -.Lop_rem_int_lit16_continue_div: - mov rIBASE, LOCAL0(%esp) - cltd - idivl %ecx - SET_VREG rIBASE, rINST - mov LOCAL0(%esp), rIBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_and_int_lit16: /* 0xd5 */ -/* File: x86/op_and_int_lit16.S */ -/* File: x86/binopLit16.S */ -/* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int/lit16, rsub-int, - * and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - movzbl rINSTbl, %eax # eax <- 000000BA - sarl $4, %eax # eax <- B - GET_VREG %eax, %eax # eax <- vB - movswl 2(rPC), %ecx # ecx <- ssssCCCC - andb $0xf, rINSTbl # rINST <- A - andl %ecx, %eax # for example: addl %ecx, %eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_or_int_lit16: /* 0xd6 */ -/* File: x86/op_or_int_lit16.S */ -/* File: x86/binopLit16.S */ -/* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int/lit16, rsub-int, - * and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - movzbl rINSTbl, %eax # eax <- 000000BA - sarl $4, %eax # eax <- B - GET_VREG %eax, %eax # eax <- vB - movswl 2(rPC), %ecx # ecx <- ssssCCCC - andb $0xf, rINSTbl # rINST <- A - orl %ecx, %eax # for example: addl %ecx, %eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int_lit16: /* 0xd7 */ -/* File: x86/op_xor_int_lit16.S */ -/* File: x86/binopLit16.S */ -/* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int/lit16, rsub-int, - * and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - movzbl rINSTbl, %eax # eax <- 000000BA - sarl $4, %eax # eax <- B - GET_VREG %eax, %eax # eax <- vB - movswl 2(rPC), %ecx # ecx <- ssssCCCC - andb $0xf, rINSTbl # rINST <- A - xorl %ecx, %eax # for example: addl %ecx, %eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_add_int_lit8: /* 0xd8 */ -/* File: x86/op_add_int_lit8.S */ -/* File: x86/binopLit8.S */ -/* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * For: add-int/lit8, rsub-int/lit8 - * and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - movzbl 2(rPC), %eax # eax <- BB - movsbl 3(rPC), %ecx # ecx <- ssssssCC - GET_VREG %eax, %eax # eax <- rBB - addl %ecx, %eax # ex: addl %ecx,%eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_rsub_int_lit8: /* 0xd9 */ -/* File: x86/op_rsub_int_lit8.S */ -/* File: x86/binopLit8.S */ -/* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * For: add-int/lit8, rsub-int/lit8 - * and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - movzbl 2(rPC), %eax # eax <- BB - movsbl 3(rPC), %ecx # ecx <- ssssssCC - GET_VREG %eax, %eax # eax <- rBB - subl %eax, %ecx # ex: addl %ecx,%eax - SET_VREG %ecx, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int_lit8: /* 0xda */ -/* File: x86/op_mul_int_lit8.S */ - /* mul/lit8 vAA, vBB, #+CC */ - movzbl 2(rPC), %eax # eax <- BB - movl rIBASE, %ecx - GET_VREG %eax, %eax # eax <- rBB - movsbl 3(rPC), rIBASE # rIBASE <- ssssssCC - imull rIBASE, %eax # trashes rIBASE/edx - movl %ecx, rIBASE - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_div_int_lit8: /* 0xdb */ -/* File: x86/op_div_int_lit8.S */ -/* File: x86/bindivLit8.S */ -/* - * 32-bit div/rem "lit8" binary operation. Handles special case of - * op0=minint & op1=-1 - */ - /* div/rem/lit8 vAA, vBB, #+CC */ - movzbl 2(rPC), %eax # eax <- BB - movsbl 3(rPC), %ecx # ecx <- ssssssCC - GET_VREG %eax, %eax # eax <- rBB - testl %ecx, %ecx - je common_errDivideByZero - cmpl $0x80000000, %eax - jne .Lop_div_int_lit8_continue_div - cmpl $-1, %ecx - jne .Lop_div_int_lit8_continue_div - movl $0x80000000, %eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -.Lop_div_int_lit8_continue_div: - mov rIBASE, LOCAL0(%esp) - cltd - idivl %ecx - SET_VREG %eax, rINST - mov LOCAL0(%esp), rIBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int_lit8: /* 0xdc */ -/* File: x86/op_rem_int_lit8.S */ -/* File: x86/bindivLit8.S */ -/* - * 32-bit div/rem "lit8" binary operation. Handles special case of - * op0=minint & op1=-1 - */ - /* div/rem/lit8 vAA, vBB, #+CC */ - movzbl 2(rPC), %eax # eax <- BB - movsbl 3(rPC), %ecx # ecx <- ssssssCC - GET_VREG %eax, %eax # eax <- rBB - testl %ecx, %ecx - je common_errDivideByZero - cmpl $0x80000000, %eax - jne .Lop_rem_int_lit8_continue_div - cmpl $-1, %ecx - jne .Lop_rem_int_lit8_continue_div - movl $0, %eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -.Lop_rem_int_lit8_continue_div: - mov rIBASE, LOCAL0(%esp) - cltd - idivl %ecx - SET_VREG rIBASE, rINST - mov LOCAL0(%esp), rIBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_and_int_lit8: /* 0xdd */ -/* File: x86/op_and_int_lit8.S */ -/* File: x86/binopLit8.S */ -/* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * For: add-int/lit8, rsub-int/lit8 - * and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - movzbl 2(rPC), %eax # eax <- BB - movsbl 3(rPC), %ecx # ecx <- ssssssCC - GET_VREG %eax, %eax # eax <- rBB - andl %ecx, %eax # ex: addl %ecx,%eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_or_int_lit8: /* 0xde */ -/* File: x86/op_or_int_lit8.S */ -/* File: x86/binopLit8.S */ -/* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * For: add-int/lit8, rsub-int/lit8 - * and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - movzbl 2(rPC), %eax # eax <- BB - movsbl 3(rPC), %ecx # ecx <- ssssssCC - GET_VREG %eax, %eax # eax <- rBB - orl %ecx, %eax # ex: addl %ecx,%eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int_lit8: /* 0xdf */ -/* File: x86/op_xor_int_lit8.S */ -/* File: x86/binopLit8.S */ -/* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * For: add-int/lit8, rsub-int/lit8 - * and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - movzbl 2(rPC), %eax # eax <- BB - movsbl 3(rPC), %ecx # ecx <- ssssssCC - GET_VREG %eax, %eax # eax <- rBB - xorl %ecx, %eax # ex: addl %ecx,%eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_shl_int_lit8: /* 0xe0 */ -/* File: x86/op_shl_int_lit8.S */ -/* File: x86/binopLit8.S */ -/* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * For: add-int/lit8, rsub-int/lit8 - * and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - movzbl 2(rPC), %eax # eax <- BB - movsbl 3(rPC), %ecx # ecx <- ssssssCC - GET_VREG %eax, %eax # eax <- rBB - sall %cl, %eax # ex: addl %ecx,%eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_shr_int_lit8: /* 0xe1 */ -/* File: x86/op_shr_int_lit8.S */ -/* File: x86/binopLit8.S */ -/* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * For: add-int/lit8, rsub-int/lit8 - * and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - movzbl 2(rPC), %eax # eax <- BB - movsbl 3(rPC), %ecx # ecx <- ssssssCC - GET_VREG %eax, %eax # eax <- rBB - sarl %cl, %eax # ex: addl %ecx,%eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_int_lit8: /* 0xe2 */ -/* File: x86/op_ushr_int_lit8.S */ -/* File: x86/binopLit8.S */ -/* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * For: add-int/lit8, rsub-int/lit8 - * and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - movzbl 2(rPC), %eax # eax <- BB - movsbl 3(rPC), %ecx # ecx <- ssssssCC - GET_VREG %eax, %eax # eax <- rBB - shrl %cl, %eax # ex: addl %ecx,%eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_quick: /* 0xe3 */ -/* File: x86/op_iget_quick.S */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset@CCCC */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # vB (object we're operating on) - movzwl 2(rPC), %eax # eax <- field byte offset - testl %ecx, %ecx # is object null? - je common_errNullObject - movl (%ecx,%eax,1), %eax - andb $0xf,rINSTbl # rINST <- A - SET_VREG %eax, rINST # fp[A] <- value - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iget_wide_quick: /* 0xe4 */ -/* File: x86/op_iget_wide_quick.S */ - /* iget-wide-quick vA, vB, offset@CCCC */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # vB (object we're operating on) - movzwl 2(rPC), %eax # eax <- field byte offset - testl %ecx, %ecx # is object null? - je common_errNullObject - movq (%ecx,%eax,1), %xmm0 - andb $0xf, rINSTbl # rINST <- A - SET_WIDE_FP_VREG %xmm0, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iget_object_quick: /* 0xe5 */ -/* File: x86/op_iget_object_quick.S */ - /* For: iget-object-quick */ - /* op vA, vB, offset@CCCC */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # vB (object we're operating on) - movzwl 2(rPC), %eax # eax <- field byte offset - movl %ecx, OUT_ARG0(%esp) - movl %eax, OUT_ARG1(%esp) - EXPORT_PC - call SYMBOL(artIGetObjectFromMterp) # (obj, offset) - movl rSELF, %ecx - RESTORE_IBASE_FROM_SELF %ecx - cmpl $0, THREAD_EXCEPTION_OFFSET(%ecx) - jnz MterpException # bail out - andb $0xf,rINSTbl # rINST <- A - SET_VREG_OBJECT %eax, rINST # fp[A] <- value - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iput_quick: /* 0xe6 */ -/* File: x86/op_iput_quick.S */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # vB (object we're operating on) - testl %ecx, %ecx # is object null? - je common_errNullObject - andb $0xf, rINSTbl # rINST <- A - GET_VREG rINST, rINST # rINST <- v[A] - movzwl 2(rPC), %eax # eax <- field byte offset - movl rINST, (%ecx,%eax,1) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iput_wide_quick: /* 0xe7 */ -/* File: x86/op_iput_wide_quick.S */ - /* iput-wide-quick vA, vB, offset@CCCC */ - movzbl rINSTbl, %ecx # ecx<- BA - sarl $4, %ecx # ecx<- B - GET_VREG %ecx, %ecx # vB (object we're operating on) - testl %ecx, %ecx # is object null? - je common_errNullObject - movzwl 2(rPC), %eax # eax<- field byte offset - leal (%ecx,%eax,1), %ecx # ecx<- Address of 64-bit target - andb $0xf, rINSTbl # rINST<- A - GET_WIDE_FP_VREG %xmm0, rINST # xmm0<- fp[A]/fp[A+1] - movq %xmm0, (%ecx) # obj.field<- r0/r1 - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iput_object_quick: /* 0xe8 */ -/* File: x86/op_iput_object_quick.S */ - EXPORT_PC - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG0(%esp) - movl rPC, OUT_ARG1(%esp) - REFRESH_INST 232 - movl rINST, OUT_ARG2(%esp) - call SYMBOL(MterpIputObjectQuick) - testb %al, %al - jz MterpException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual_quick: /* 0xe9 */ -/* File: x86/op_invoke_virtual_quick.S */ -/* File: x86/invoke.S */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtualQuick - EXPORT_PC - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - REFRESH_INST 233 - movl rINST, OUT_ARG3(%esp) - call SYMBOL(MterpInvokeVirtualQuick) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - RESTORE_IBASE - FETCH_INST - GOTO_NEXT - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual_range_quick: /* 0xea */ -/* File: x86/op_invoke_virtual_range_quick.S */ -/* File: x86/invoke.S */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtualQuickRange - EXPORT_PC - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - REFRESH_INST 234 - movl rINST, OUT_ARG3(%esp) - call SYMBOL(MterpInvokeVirtualQuickRange) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - RESTORE_IBASE - FETCH_INST - GOTO_NEXT - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_boolean_quick: /* 0xeb */ -/* File: x86/op_iput_boolean_quick.S */ -/* File: x86/op_iput_quick.S */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # vB (object we're operating on) - testl %ecx, %ecx # is object null? - je common_errNullObject - andb $0xf, rINSTbl # rINST <- A - GET_VREG rINST, rINST # rINST <- v[A] - movzwl 2(rPC), %eax # eax <- field byte offset - movb rINSTbl, (%ecx,%eax,1) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_byte_quick: /* 0xec */ -/* File: x86/op_iput_byte_quick.S */ -/* File: x86/op_iput_quick.S */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # vB (object we're operating on) - testl %ecx, %ecx # is object null? - je common_errNullObject - andb $0xf, rINSTbl # rINST <- A - GET_VREG rINST, rINST # rINST <- v[A] - movzwl 2(rPC), %eax # eax <- field byte offset - movb rINSTbl, (%ecx,%eax,1) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_char_quick: /* 0xed */ -/* File: x86/op_iput_char_quick.S */ -/* File: x86/op_iput_quick.S */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # vB (object we're operating on) - testl %ecx, %ecx # is object null? - je common_errNullObject - andb $0xf, rINSTbl # rINST <- A - GET_VREG rINST, rINST # rINST <- v[A] - movzwl 2(rPC), %eax # eax <- field byte offset - movw rINSTw, (%ecx,%eax,1) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_short_quick: /* 0xee */ -/* File: x86/op_iput_short_quick.S */ -/* File: x86/op_iput_quick.S */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # vB (object we're operating on) - testl %ecx, %ecx # is object null? - je common_errNullObject - andb $0xf, rINSTbl # rINST <- A - GET_VREG rINST, rINST # rINST <- v[A] - movzwl 2(rPC), %eax # eax <- field byte offset - movw rINSTw, (%ecx,%eax,1) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_boolean_quick: /* 0xef */ -/* File: x86/op_iget_boolean_quick.S */ -/* File: x86/op_iget_quick.S */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset@CCCC */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # vB (object we're operating on) - movzwl 2(rPC), %eax # eax <- field byte offset - testl %ecx, %ecx # is object null? - je common_errNullObject - movsbl (%ecx,%eax,1), %eax - andb $0xf,rINSTbl # rINST <- A - SET_VREG %eax, rINST # fp[A] <- value - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_byte_quick: /* 0xf0 */ -/* File: x86/op_iget_byte_quick.S */ -/* File: x86/op_iget_quick.S */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset@CCCC */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # vB (object we're operating on) - movzwl 2(rPC), %eax # eax <- field byte offset - testl %ecx, %ecx # is object null? - je common_errNullObject - movsbl (%ecx,%eax,1), %eax - andb $0xf,rINSTbl # rINST <- A - SET_VREG %eax, rINST # fp[A] <- value - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_char_quick: /* 0xf1 */ -/* File: x86/op_iget_char_quick.S */ -/* File: x86/op_iget_quick.S */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset@CCCC */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # vB (object we're operating on) - movzwl 2(rPC), %eax # eax <- field byte offset - testl %ecx, %ecx # is object null? - je common_errNullObject - movzwl (%ecx,%eax,1), %eax - andb $0xf,rINSTbl # rINST <- A - SET_VREG %eax, rINST # fp[A] <- value - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_short_quick: /* 0xf2 */ -/* File: x86/op_iget_short_quick.S */ -/* File: x86/op_iget_quick.S */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset@CCCC */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # vB (object we're operating on) - movzwl 2(rPC), %eax # eax <- field byte offset - testl %ecx, %ecx # is object null? - je common_errNullObject - movswl (%ecx,%eax,1), %eax - andb $0xf,rINSTbl # rINST <- A - SET_VREG %eax, rINST # fp[A] <- value - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f3: /* 0xf3 */ -/* File: x86/op_unused_f3.S */ -/* File: x86/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f4: /* 0xf4 */ -/* File: x86/op_unused_f4.S */ -/* File: x86/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f5: /* 0xf5 */ -/* File: x86/op_unused_f5.S */ -/* File: x86/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f6: /* 0xf6 */ -/* File: x86/op_unused_f6.S */ -/* File: x86/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f7: /* 0xf7 */ -/* File: x86/op_unused_f7.S */ -/* File: x86/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f8: /* 0xf8 */ -/* File: x86/op_unused_f8.S */ -/* File: x86/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f9: /* 0xf9 */ -/* File: x86/op_unused_f9.S */ -/* File: x86/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_polymorphic: /* 0xfa */ -/* File: x86/op_invoke_polymorphic.S */ -/* File: x86/invoke_polymorphic.S */ - /* - * invoke-polymorphic handler wrapper. - */ - /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ - .extern MterpInvokePolymorphic - EXPORT_PC - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - REFRESH_INST 250 - movl rINST, OUT_ARG3(%esp) - call SYMBOL(MterpInvokePolymorphic) - testb %al, %al - jz MterpException - ADVANCE_PC 4 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - RESTORE_IBASE - FETCH_INST - GOTO_NEXT - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_polymorphic_range: /* 0xfb */ -/* File: x86/op_invoke_polymorphic_range.S */ -/* File: x86/invoke_polymorphic.S */ - /* - * invoke-polymorphic handler wrapper. - */ - /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ - .extern MterpInvokePolymorphicRange - EXPORT_PC - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - REFRESH_INST 251 - movl rINST, OUT_ARG3(%esp) - call SYMBOL(MterpInvokePolymorphicRange) - testb %al, %al - jz MterpException - ADVANCE_PC 4 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - RESTORE_IBASE - FETCH_INST - GOTO_NEXT - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_custom: /* 0xfc */ -/* File: x86/op_invoke_custom.S */ -/* File: x86/invoke.S */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeCustom - EXPORT_PC - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - REFRESH_INST 252 - movl rINST, OUT_ARG3(%esp) - call SYMBOL(MterpInvokeCustom) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - RESTORE_IBASE - FETCH_INST - GOTO_NEXT - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_custom_range: /* 0xfd */ -/* File: x86/op_invoke_custom_range.S */ -/* File: x86/invoke.S */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeCustomRange - EXPORT_PC - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - REFRESH_INST 253 - movl rINST, OUT_ARG3(%esp) - call SYMBOL(MterpInvokeCustomRange) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - RESTORE_IBASE - FETCH_INST - GOTO_NEXT - - -/* ------------------------------ */ - .balign 128 -.L_op_const_method_handle: /* 0xfe */ -/* File: x86/op_const_method_handle.S */ -/* File: x86/const.S */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstMethodHandle - EXPORT_PC - movzwl 2(rPC), %eax # eax <- BBBB - movl %eax, OUT_ARG0(%esp) - movl rINST, OUT_ARG1(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) - call SYMBOL(MterpConstMethodHandle) # (index, tgt_reg, shadow_frame, self) - RESTORE_IBASE - testb %al, %al - jnz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_const_method_type: /* 0xff */ -/* File: x86/op_const_method_type.S */ -/* File: x86/const.S */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstMethodType - EXPORT_PC - movzwl 2(rPC), %eax # eax <- BBBB - movl %eax, OUT_ARG0(%esp) - movl rINST, OUT_ARG1(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) - call SYMBOL(MterpConstMethodType) # (index, tgt_reg, shadow_frame, self) - RESTORE_IBASE - testb %al, %al - jnz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - .balign 128 -/* File: x86/instruction_end.S */ - - OBJECT_TYPE(artMterpAsmInstructionEnd) - ASM_HIDDEN SYMBOL(artMterpAsmInstructionEnd) - .global SYMBOL(artMterpAsmInstructionEnd) -SYMBOL(artMterpAsmInstructionEnd): - - -/* - * =========================================================================== - * Sister implementations - * =========================================================================== - */ -/* File: x86/instruction_start_sister.S */ - - OBJECT_TYPE(artMterpAsmSisterStart) - ASM_HIDDEN SYMBOL(artMterpAsmSisterStart) - .global SYMBOL(artMterpAsmSisterStart) - .text - .balign 4 -SYMBOL(artMterpAsmSisterStart): - -/* File: x86/instruction_end_sister.S */ - - OBJECT_TYPE(artMterpAsmSisterEnd) - ASM_HIDDEN SYMBOL(artMterpAsmSisterEnd) - .global SYMBOL(artMterpAsmSisterEnd) -SYMBOL(artMterpAsmSisterEnd): - -/* File: x86/instruction_start_alt.S */ - - OBJECT_TYPE(artMterpAsmAltInstructionStart) - ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionStart) - .global SYMBOL(artMterpAsmAltInstructionStart) - .text -SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_nop: /* 0x00 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(0*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move: /* 0x01 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(1*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_from16: /* 0x02 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(2*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_16: /* 0x03 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(3*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_wide: /* 0x04 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(4*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_wide_from16: /* 0x05 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(5*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_wide_16: /* 0x06 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(6*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_object: /* 0x07 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(7*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_object_from16: /* 0x08 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(8*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_object_16: /* 0x09 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(9*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_result: /* 0x0a */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(10*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_result_wide: /* 0x0b */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(11*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_result_object: /* 0x0c */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(12*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_exception: /* 0x0d */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(13*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_void: /* 0x0e */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(14*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return: /* 0x0f */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(15*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_wide: /* 0x10 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(16*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_object: /* 0x11 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(17*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_4: /* 0x12 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(18*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_16: /* 0x13 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(19*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const: /* 0x14 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(20*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_high16: /* 0x15 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(21*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide_16: /* 0x16 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(22*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide_32: /* 0x17 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(23*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide: /* 0x18 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(24*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide_high16: /* 0x19 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(25*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_string: /* 0x1a */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(26*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_string_jumbo: /* 0x1b */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(27*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_class: /* 0x1c */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(28*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_monitor_enter: /* 0x1d */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(29*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_monitor_exit: /* 0x1e */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(30*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_check_cast: /* 0x1f */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(31*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_instance_of: /* 0x20 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(32*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_array_length: /* 0x21 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(33*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_new_instance: /* 0x22 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(34*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_new_array: /* 0x23 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(35*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_filled_new_array: /* 0x24 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(36*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_filled_new_array_range: /* 0x25 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(37*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_fill_array_data: /* 0x26 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(38*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_throw: /* 0x27 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(39*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_goto: /* 0x28 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(40*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_goto_16: /* 0x29 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(41*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_goto_32: /* 0x2a */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(42*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_packed_switch: /* 0x2b */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(43*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sparse_switch: /* 0x2c */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(44*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpl_float: /* 0x2d */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(45*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpg_float: /* 0x2e */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(46*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpl_double: /* 0x2f */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(47*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpg_double: /* 0x30 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(48*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmp_long: /* 0x31 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(49*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_eq: /* 0x32 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(50*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_ne: /* 0x33 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(51*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_lt: /* 0x34 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(52*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_ge: /* 0x35 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(53*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_gt: /* 0x36 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(54*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_le: /* 0x37 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(55*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_eqz: /* 0x38 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(56*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_nez: /* 0x39 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(57*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_ltz: /* 0x3a */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(58*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_gez: /* 0x3b */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(59*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_gtz: /* 0x3c */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(60*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_lez: /* 0x3d */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(61*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_3e: /* 0x3e */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(62*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_3f: /* 0x3f */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(63*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_40: /* 0x40 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(64*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_41: /* 0x41 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(65*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_42: /* 0x42 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(66*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_43: /* 0x43 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(67*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget: /* 0x44 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(68*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_wide: /* 0x45 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(69*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_object: /* 0x46 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(70*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_boolean: /* 0x47 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(71*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_byte: /* 0x48 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(72*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_char: /* 0x49 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(73*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_short: /* 0x4a */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(74*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput: /* 0x4b */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(75*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_wide: /* 0x4c */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(76*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_object: /* 0x4d */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(77*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_boolean: /* 0x4e */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(78*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_byte: /* 0x4f */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(79*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_char: /* 0x50 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(80*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_short: /* 0x51 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(81*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget: /* 0x52 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(82*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_wide: /* 0x53 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(83*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_object: /* 0x54 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(84*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_boolean: /* 0x55 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(85*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_byte: /* 0x56 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(86*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_char: /* 0x57 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(87*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_short: /* 0x58 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(88*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput: /* 0x59 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(89*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_wide: /* 0x5a */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(90*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_object: /* 0x5b */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(91*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_boolean: /* 0x5c */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(92*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_byte: /* 0x5d */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(93*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_char: /* 0x5e */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(94*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_short: /* 0x5f */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(95*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget: /* 0x60 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(96*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_wide: /* 0x61 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(97*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_object: /* 0x62 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(98*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_boolean: /* 0x63 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(99*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_byte: /* 0x64 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(100*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_char: /* 0x65 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(101*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_short: /* 0x66 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(102*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput: /* 0x67 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(103*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_wide: /* 0x68 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(104*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_object: /* 0x69 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(105*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_boolean: /* 0x6a */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(106*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_byte: /* 0x6b */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(107*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_char: /* 0x6c */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(108*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_short: /* 0x6d */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(109*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual: /* 0x6e */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(110*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_super: /* 0x6f */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(111*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_direct: /* 0x70 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(112*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_static: /* 0x71 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(113*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_interface: /* 0x72 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(114*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_void_no_barrier: /* 0x73 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(115*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual_range: /* 0x74 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(116*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_super_range: /* 0x75 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(117*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_direct_range: /* 0x76 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(118*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_static_range: /* 0x77 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(119*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_interface_range: /* 0x78 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(120*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_79: /* 0x79 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(121*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_7a: /* 0x7a */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(122*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_int: /* 0x7b */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(123*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_not_int: /* 0x7c */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(124*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_long: /* 0x7d */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(125*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_not_long: /* 0x7e */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(126*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_float: /* 0x7f */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(127*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_double: /* 0x80 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(128*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_long: /* 0x81 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(129*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_float: /* 0x82 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(130*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_double: /* 0x83 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(131*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_long_to_int: /* 0x84 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(132*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_long_to_float: /* 0x85 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(133*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_long_to_double: /* 0x86 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(134*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_float_to_int: /* 0x87 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(135*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_float_to_long: /* 0x88 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(136*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_float_to_double: /* 0x89 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(137*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_double_to_int: /* 0x8a */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(138*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_double_to_long: /* 0x8b */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(139*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_double_to_float: /* 0x8c */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(140*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_byte: /* 0x8d */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(141*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_char: /* 0x8e */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(142*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_short: /* 0x8f */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(143*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int: /* 0x90 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(144*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_int: /* 0x91 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(145*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int: /* 0x92 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(146*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int: /* 0x93 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(147*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int: /* 0x94 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(148*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int: /* 0x95 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(149*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int: /* 0x96 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(150*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int: /* 0x97 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(151*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_int: /* 0x98 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(152*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_int: /* 0x99 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(153*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_int: /* 0x9a */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(154*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_long: /* 0x9b */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(155*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_long: /* 0x9c */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(156*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_long: /* 0x9d */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(157*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_long: /* 0x9e */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(158*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_long: /* 0x9f */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(159*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_long: /* 0xa0 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(160*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_long: /* 0xa1 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(161*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_long: /* 0xa2 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(162*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_long: /* 0xa3 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(163*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_long: /* 0xa4 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(164*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_long: /* 0xa5 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(165*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_float: /* 0xa6 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(166*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_float: /* 0xa7 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(167*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_float: /* 0xa8 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(168*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_float: /* 0xa9 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(169*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_float: /* 0xaa */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(170*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_double: /* 0xab */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(171*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_double: /* 0xac */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(172*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_double: /* 0xad */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(173*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_double: /* 0xae */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(174*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_double: /* 0xaf */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(175*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int_2addr: /* 0xb0 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(176*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_int_2addr: /* 0xb1 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(177*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int_2addr: /* 0xb2 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(178*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int_2addr: /* 0xb3 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(179*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int_2addr: /* 0xb4 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(180*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int_2addr: /* 0xb5 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(181*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int_2addr: /* 0xb6 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(182*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int_2addr: /* 0xb7 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(183*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_int_2addr: /* 0xb8 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(184*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_int_2addr: /* 0xb9 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(185*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_int_2addr: /* 0xba */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(186*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_long_2addr: /* 0xbb */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(187*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_long_2addr: /* 0xbc */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(188*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_long_2addr: /* 0xbd */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(189*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_long_2addr: /* 0xbe */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(190*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_long_2addr: /* 0xbf */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(191*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_long_2addr: /* 0xc0 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(192*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_long_2addr: /* 0xc1 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(193*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_long_2addr: /* 0xc2 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(194*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_long_2addr: /* 0xc3 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(195*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_long_2addr: /* 0xc4 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(196*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_long_2addr: /* 0xc5 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(197*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_float_2addr: /* 0xc6 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(198*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_float_2addr: /* 0xc7 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(199*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_float_2addr: /* 0xc8 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(200*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_float_2addr: /* 0xc9 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(201*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_float_2addr: /* 0xca */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(202*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_double_2addr: /* 0xcb */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(203*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_double_2addr: /* 0xcc */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(204*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_double_2addr: /* 0xcd */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(205*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_double_2addr: /* 0xce */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(206*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_double_2addr: /* 0xcf */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(207*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int_lit16: /* 0xd0 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(208*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rsub_int: /* 0xd1 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(209*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int_lit16: /* 0xd2 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(210*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int_lit16: /* 0xd3 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(211*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int_lit16: /* 0xd4 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(212*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int_lit16: /* 0xd5 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(213*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int_lit16: /* 0xd6 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(214*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int_lit16: /* 0xd7 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(215*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int_lit8: /* 0xd8 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(216*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rsub_int_lit8: /* 0xd9 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(217*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int_lit8: /* 0xda */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(218*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int_lit8: /* 0xdb */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(219*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int_lit8: /* 0xdc */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(220*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int_lit8: /* 0xdd */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(221*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int_lit8: /* 0xde */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(222*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int_lit8: /* 0xdf */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(223*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_int_lit8: /* 0xe0 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(224*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_int_lit8: /* 0xe1 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(225*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_int_lit8: /* 0xe2 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(226*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_quick: /* 0xe3 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(227*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_wide_quick: /* 0xe4 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(228*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_object_quick: /* 0xe5 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(229*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_quick: /* 0xe6 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(230*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_wide_quick: /* 0xe7 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(231*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_object_quick: /* 0xe8 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(232*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual_quick: /* 0xe9 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(233*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual_range_quick: /* 0xea */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(234*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_boolean_quick: /* 0xeb */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(235*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_byte_quick: /* 0xec */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(236*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_char_quick: /* 0xed */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(237*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_short_quick: /* 0xee */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(238*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_boolean_quick: /* 0xef */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(239*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_byte_quick: /* 0xf0 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(240*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_char_quick: /* 0xf1 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(241*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_short_quick: /* 0xf2 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(242*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f3: /* 0xf3 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(243*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f4: /* 0xf4 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(244*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f5: /* 0xf5 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(245*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f6: /* 0xf6 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(246*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f7: /* 0xf7 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(247*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f8: /* 0xf8 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(248*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f9: /* 0xf9 */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(249*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_polymorphic: /* 0xfa */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(250*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_polymorphic_range: /* 0xfb */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(251*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_custom: /* 0xfc */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(252*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_custom_range: /* 0xfd */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(253*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_method_handle: /* 0xfe */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(254*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_method_type: /* 0xff */ -/* File: x86/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(255*128) - - .balign 128 -/* File: x86/instruction_end_alt.S */ - - OBJECT_TYPE(artMterpAsmAltInstructionEnd) - ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionEnd) - .global SYMBOL(artMterpAsmAltInstructionEnd) -SYMBOL(artMterpAsmAltInstructionEnd): - -/* File: x86/footer.S */ -/* - * =========================================================================== - * Common subroutines and data - * =========================================================================== - */ - - .text - .align 2 - -/* - * We've detected a condition that will result in an exception, but the exception - * has not yet been thrown. Just bail out to the reference interpreter to deal with it. - * TUNING: for consistency, we may want to just go ahead and handle these here. - */ -common_errDivideByZero: - EXPORT_PC -#if MTERP_LOGGING - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - lea OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - call SYMBOL(MterpLogDivideByZeroException) -#endif - jmp MterpCommonFallback - -common_errArrayIndex: - EXPORT_PC -#if MTERP_LOGGING - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - lea OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - call SYMBOL(MterpLogArrayIndexException) -#endif - jmp MterpCommonFallback - -common_errNegativeArraySize: - EXPORT_PC -#if MTERP_LOGGING - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - lea OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - call SYMBOL(MterpLogNegativeArraySizeException) -#endif - jmp MterpCommonFallback - -common_errNoSuchMethod: - EXPORT_PC -#if MTERP_LOGGING - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - lea OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - call SYMBOL(MterpLogNoSuchMethodException) -#endif - jmp MterpCommonFallback - -common_errNullObject: - EXPORT_PC -#if MTERP_LOGGING - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - lea OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - call SYMBOL(MterpLogNullObjectException) -#endif - jmp MterpCommonFallback - -common_exceptionThrown: - EXPORT_PC -#if MTERP_LOGGING - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - lea OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG0(%esp) - call SYMBOL(MterpLogExceptionThrownException) -#endif - jmp MterpCommonFallback - -MterpSuspendFallback: - EXPORT_PC -#if MTERP_LOGGING - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - lea OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG0(%esp) - movl THREAD_FLAGS_OFFSET(%eax), %eax - movl %eax, OUT_ARG2(%esp) - call SYMBOL(MterpLogSuspendFallback) -#endif - jmp MterpCommonFallback - -/* - * If we're here, something is out of the ordinary. If there is a pending - * exception, handle it. Otherwise, roll back and retry with the reference - * interpreter. - */ -MterpPossibleException: - movl rSELF, %eax - testl $-1, THREAD_EXCEPTION_OFFSET(%eax) - jz MterpFallback - /* intentional fallthrough - handle pending exception. */ - -/* - * On return from a runtime helper routine, we've found a pending exception. - * Can we handle it here - or need to bail out to caller? - * - */ -MterpException: - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - lea OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - call SYMBOL(MterpHandleException) - testb %al, %al - jz MterpExceptionReturn - movl OFF_FP_DEX_INSTRUCTIONS(rFP), %eax - movl OFF_FP_DEX_PC(rFP), %ecx - lea (%eax, %ecx, 2), rPC - movl rPC, OFF_FP_DEX_PC_PTR(rFP) - /* Do we need to switch interpreters? */ - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - /* resume execution at catch block */ - REFRESH_IBASE - FETCH_INST - GOTO_NEXT - /* NOTE: no fallthrough */ - -/* - * Common handling for branches with support for Jit profiling. - * On entry: - * rINST <= signed offset - * condition bits <= set to establish sign of offset (use "NoFlags" entry if not) - * - * We have quite a few different cases for branch profiling, OSR detection and - * suspend check support here. - * - * Taken backward branches: - * If profiling active, do hotness countdown and report if we hit zero. - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * Is there a pending suspend request? If so, suspend. - * - * Taken forward branches and not-taken backward branches: - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * - * Our most common case is expected to be a taken backward branch with active jit profiling, - * but no full OSR check and no pending suspend request. - * Next most common case is not-taken branch with no full OSR check. - * - */ -MterpCommonTakenBranch: - jg .L_forward_branch # don't add forward branches to hotness -/* - * We need to subtract 1 from positive values and we should not see 0 here, - * so we may use the result of the comparison with -1. - */ -#if JIT_CHECK_OSR != -1 -# error "JIT_CHECK_OSR must be -1." -#endif - cmpw $JIT_CHECK_OSR, rPROFILE - je .L_osr_check - decw rPROFILE - je .L_add_batch # counted down to zero - report -.L_resume_backward_branch: - movl rSELF, %eax - testl $(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(%eax) - leal (rPC, rINST, 2), rPC - FETCH_INST - jnz .L_suspend_request_pending - REFRESH_IBASE - GOTO_NEXT - -.L_suspend_request_pending: - EXPORT_PC - movl %eax, OUT_ARG0(%esp) # rSELF in eax - call SYMBOL(MterpSuspendCheck) # (self) - testb %al, %al - jnz MterpFallback - REFRESH_IBASE # might have changed during suspend - GOTO_NEXT - -.L_no_count_backwards: - cmpw $JIT_CHECK_OSR, rPROFILE # possible OSR re-entry? - jne .L_resume_backward_branch -.L_osr_check: - EXPORT_PC - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - movl rINST, OUT_ARG2(%esp) - call SYMBOL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) - testb %al, %al - jz .L_resume_backward_branch - jmp MterpOnStackReplacement - -.L_forward_branch: - cmpw $JIT_CHECK_OSR, rPROFILE # possible OSR re-entry? - je .L_check_osr_forward -.L_resume_forward_branch: - leal (rPC, rINST, 2), rPC - FETCH_INST - GOTO_NEXT - -.L_check_osr_forward: - EXPORT_PC - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - movl rINST, OUT_ARG2(%esp) - call SYMBOL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) - testb %al, %al - REFRESH_IBASE - jz .L_resume_forward_branch - jmp MterpOnStackReplacement - -.L_add_batch: - movl OFF_FP_METHOD(rFP), %eax - movl %eax, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - movl rSELF, %eax - movl %eax, OUT_ARG2(%esp) - call SYMBOL(MterpAddHotnessBatch) # (method, shadow_frame, self) - jmp .L_no_count_backwards - -/* - * Entered from the conditional branch handlers when OSR check request active on - * not-taken path. All Dalvik not-taken conditional branch offsets are 2. - */ -.L_check_not_taken_osr: - EXPORT_PC - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - movl $2, OUT_ARG2(%esp) - call SYMBOL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) - testb %al, %al - REFRESH_IBASE - jnz MterpOnStackReplacement - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* - * On-stack replacement has happened, and now we've returned from the compiled method. - */ -MterpOnStackReplacement: -#if MTERP_LOGGING - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - lea OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - movl rINST, OUT_ARG2(%esp) - call SYMBOL(MterpLogOSR) -#endif - movl $1, %eax - jmp MterpDone - -/* - * Bail out to reference interpreter. - */ -MterpFallback: - EXPORT_PC -#if MTERP_LOGGING - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - lea OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - call SYMBOL(MterpLogFallback) -#endif -MterpCommonFallback: - xor %eax, %eax - jmp MterpDone - -/* - * On entry: - * uint32_t* rFP (should still be live, pointer to base of vregs) - */ -MterpExceptionReturn: - movl $1, %eax - jmp MterpDone -MterpReturn: - movl OFF_FP_RESULT_REGISTER(rFP), %edx - movl %eax, (%edx) - movl %ecx, 4(%edx) - mov $1, %eax -MterpDone: -/* - * At this point, we expect rPROFILE to be non-zero. If negative, hotness is disabled or we're - * checking for OSR. If greater than zero, we might have unreported hotness to register - * (the difference between the ending rPROFILE and the cached hotness counter). rPROFILE - * should only reach zero immediately after a hotness decrement, and is then reset to either - * a negative special state or the new non-zero countdown value. - */ - cmpw $0, rPROFILE - jle MRestoreFrame # if > 0, we may have some counts to report. - - movl %eax, rINST # stash return value - /* Report cached hotness counts */ - movl OFF_FP_METHOD(rFP), %eax - movl %eax, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - movl rSELF, %eax - movl %eax, OUT_ARG2(%esp) - call SYMBOL(MterpAddHotnessBatch) # (method, shadow_frame, self) - movl rINST, %eax # restore return value - - /* pop up frame */ -MRestoreFrame: - addl $FRAME_SIZE, %esp - .cfi_adjust_cfa_offset -FRAME_SIZE - - /* Restore callee save register */ - POP %ebx - POP %esi - POP %edi - POP %ebp - ret - .cfi_endproc - SIZE(ExecuteMterpImpl,ExecuteMterpImpl) - diff --git a/runtime/interpreter/mterp/out/mterp_x86_64.S b/runtime/interpreter/mterp/out/mterp_x86_64.S deleted file mode 100644 index 6d8bb4c7c45e39b713ffadb5cb4c42f8c67bddb0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/out/mterp_x86_64.S +++ /dev/null @@ -1,12040 +0,0 @@ -/* - * This file was generated automatically by gen-mterp.py for 'x86_64'. - * - * --> DO NOT EDIT <-- - */ - -/* File: x86_64/header.S */ -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - Art assembly interpreter notes: - - First validate assembly code by implementing ExecuteXXXImpl() style body (doesn't - handle invoke, allows higher-level code to create frame & shadow frame. - - Once that's working, support direct entry code & eliminate shadow frame (and - excess locals allocation. - - Some (hopefully) temporary ugliness. We'll treat rFP as pointing to the - base of the vreg array within the shadow frame. Access the other fields, - dex_pc_, method_ and number_of_vregs_ via negative offsets. For now, we'll continue - the shadow frame mechanism of double-storing object references - via rFP & - number_of_vregs_. - - */ - -/* -x86_64 ABI general notes: - -Caller save set: - rax, rdx, rcx, rsi, rdi, r8-r11, st(0)-st(7) -Callee save set: - rbx, rbp, r12-r15 -Return regs: - 32-bit in eax - 64-bit in rax - fp on xmm0 - -First 8 fp parameters came in xmm0-xmm7. -First 6 non-fp parameters came in rdi, rsi, rdx, rcx, r8, r9. -Other parameters passed on stack, pushed right-to-left. On entry to target, first -param is at 8(%esp). Traditional entry code is: - -Stack must be 16-byte aligned to support SSE in native code. - -If we're not doing variable stack allocation (alloca), the frame pointer can be -eliminated and all arg references adjusted to be esp relative. -*/ - -/* -Mterp and x86_64 notes: - -Some key interpreter variables will be assigned to registers. - - nick reg purpose - rPROFILE rbp countdown register for jit profiling - rPC r12 interpreted program counter, used for fetching instructions - rFP r13 interpreted frame pointer, used for accessing locals and args - rINSTw bx first 16-bit code of current instruction - rINSTbl bl opcode portion of instruction word - rINSTbh bh high byte of inst word, usually contains src/tgt reg names - rIBASE r14 base of instruction handler table - rREFS r15 base of object references in shadow frame. - -Notes: - o High order 16 bits of ebx must be zero on entry to handler - o rPC, rFP, rINSTw/rINSTbl valid on handler entry and exit - o eax and ecx are scratch, rINSTw/ebx sometimes scratch - -Macros are provided for common operations. Each macro MUST emit only -one instruction to make instruction-counting easier. They MUST NOT alter -unspecified registers or condition codes. -*/ - -/* - * This is a #include, not a %include, because we want the C pre-processor - * to expand the macros into assembler assignment statements. - */ -#include "asm_support.h" -#include "interpreter/cfi_asm_support.h" - -/* - * Handle mac compiler specific - */ -#if defined(__APPLE__) - #define MACRO_LITERAL(value) $(value) - #define FUNCTION_TYPE(name) - #define OBJECT_TYPE(name) - #define SIZE(start,end) - // Mac OS' symbols have an _ prefix. - #define SYMBOL(name) _ ## name - #define ASM_HIDDEN .private_extern -#else - #define MACRO_LITERAL(value) $value - #define FUNCTION_TYPE(name) .type name, @function - #define OBJECT_TYPE(name) .type name, @object - #define SIZE(start,end) .size start, .-end - #define SYMBOL(name) name - #define ASM_HIDDEN .hidden -#endif - -.macro PUSH _reg - pushq \_reg - .cfi_adjust_cfa_offset 8 - .cfi_rel_offset \_reg, 0 -.endm - -.macro POP _reg - popq \_reg - .cfi_adjust_cfa_offset -8 - .cfi_restore \_reg -.endm - -/* - * Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs. So, - * to access other shadow frame fields, we need to use a backwards offset. Define those here. - */ -#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) -#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) -#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) -#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) -#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) -#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) -#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) -#define OFF_FP_DEX_INSTRUCTIONS OFF_FP(SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET) -#define OFF_FP_COUNTDOWN_OFFSET OFF_FP(SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET) -#define OFF_FP_SHADOWFRAME (-SHADOWFRAME_VREGS_OFFSET) - -/* Frame size must be 16-byte aligned. - * Remember about 8 bytes for return address + 6 * 8 for spills. - */ -#define FRAME_SIZE 8 - -/* Frame diagram while executing ExecuteMterpImpl, high to low addresses */ -#define IN_ARG3 %rcx -#define IN_ARG2 %rdx -#define IN_ARG1 %rsi -#define IN_ARG0 %rdi -/* Spill offsets relative to %esp */ -#define SELF_SPILL (FRAME_SIZE - 8) -/* Out Args */ -#define OUT_ARG3 %rcx -#define OUT_ARG2 %rdx -#define OUT_ARG1 %rsi -#define OUT_ARG0 %rdi -#define OUT_32_ARG3 %ecx -#define OUT_32_ARG2 %edx -#define OUT_32_ARG1 %esi -#define OUT_32_ARG0 %edi -#define OUT_FP_ARG1 %xmm1 -#define OUT_FP_ARG0 %xmm0 - -/* During bringup, we'll use the shadow frame model instead of rFP */ -/* single-purpose registers, given names for clarity */ -#define rSELF SELF_SPILL(%rsp) -#define rPC %r12 -#define CFI_DEX 12 // DWARF register number of the register holding dex-pc (rPC). -#define CFI_TMP 5 // DWARF register number of the first argument register (rdi). -#define rFP %r13 -#define rINST %ebx -#define rINSTq %rbx -#define rINSTw %bx -#define rINSTbh %bh -#define rINSTbl %bl -#define rIBASE %r14 -#define rREFS %r15 -#define rPROFILE %ebp - -#define MTERP_LOGGING 0 - -/* - * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must - * be done *before* something throws. - * - * It's okay to do this more than once. - * - * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped - * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction - * offset into the code_items_[] array. For effiency, we will "export" the - * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC - * to convert to a dex pc when needed. - */ -.macro EXPORT_PC - movq rPC, OFF_FP_DEX_PC_PTR(rFP) -.endm - -/* - * Refresh handler table. - * IBase handles uses the caller save register so we must restore it after each call. - * Also it is used as a result of some 64-bit operations (like imul) and we should - * restore it in such cases also. - * - */ -.macro REFRESH_IBASE_REG self_reg - movq THREAD_CURRENT_IBASE_OFFSET(\self_reg), rIBASE -.endm -.macro REFRESH_IBASE - movq rSELF, rIBASE - REFRESH_IBASE_REG rIBASE -.endm - -/* - * Refresh rINST. - * At enter to handler rINST does not contain the opcode number. - * However some utilities require the full value, so this macro - * restores the opcode number. - */ -.macro REFRESH_INST _opnum - movb rINSTbl, rINSTbh - movb $\_opnum, rINSTbl -.endm - -/* - * Fetch the next instruction from rPC into rINSTw. Does not advance rPC. - */ -.macro FETCH_INST - movzwq (rPC), rINSTq -.endm - -/* - * Remove opcode from rINST, compute the address of handler and jump to it. - */ -.macro GOTO_NEXT - movzx rINSTbl,%eax - movzbl rINSTbh,rINST - shll MACRO_LITERAL(7), %eax - addq rIBASE, %rax - jmp *%rax -.endm - -/* - * Advance rPC by instruction count. - */ -.macro ADVANCE_PC _count - leaq 2*\_count(rPC), rPC -.endm - -/* - * Advance rPC by instruction count, fetch instruction and jump to handler. - */ -.macro ADVANCE_PC_FETCH_AND_GOTO_NEXT _count - ADVANCE_PC \_count - FETCH_INST - GOTO_NEXT -.endm - -/* - * Get/set the 32-bit value from a Dalvik register. - */ -#define VREG_ADDRESS(_vreg) (rFP,_vreg,4) -#define VREG_REF_ADDRESS(_vreg) (rREFS,_vreg,4) - -.macro GET_VREG _reg _vreg - movl (rFP,\_vreg,4), \_reg -.endm - -/* Read wide value. */ -.macro GET_WIDE_VREG _reg _vreg - movq (rFP,\_vreg,4), \_reg -.endm - -.macro SET_VREG _reg _vreg - movl \_reg, (rFP,\_vreg,4) - movl MACRO_LITERAL(0), (rREFS,\_vreg,4) -.endm - -/* Write wide value. reg is clobbered. */ -.macro SET_WIDE_VREG _reg _vreg - movq \_reg, (rFP,\_vreg,4) - xorq \_reg, \_reg - movq \_reg, (rREFS,\_vreg,4) -.endm - -.macro SET_VREG_OBJECT _reg _vreg - movl \_reg, (rFP,\_vreg,4) - movl \_reg, (rREFS,\_vreg,4) -.endm - -.macro GET_VREG_HIGH _reg _vreg - movl 4(rFP,\_vreg,4), \_reg -.endm - -.macro SET_VREG_HIGH _reg _vreg - movl \_reg, 4(rFP,\_vreg,4) - movl MACRO_LITERAL(0), 4(rREFS,\_vreg,4) -.endm - -.macro CLEAR_REF _vreg - movl MACRO_LITERAL(0), (rREFS,\_vreg,4) -.endm - -.macro CLEAR_WIDE_REF _vreg - movl MACRO_LITERAL(0), (rREFS,\_vreg,4) - movl MACRO_LITERAL(0), 4(rREFS,\_vreg,4) -.endm - -/* File: x86_64/entry.S */ -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -/* - * Interpreter entry point. - */ - - .text - ASM_HIDDEN SYMBOL(ExecuteMterpImpl) - .global SYMBOL(ExecuteMterpImpl) - FUNCTION_TYPE(ExecuteMterpImpl) - -/* - * On entry: - * 0 Thread* self - * 1 insns_ - * 2 ShadowFrame - * 3 JValue* result_register - * - */ - -SYMBOL(ExecuteMterpImpl): - .cfi_startproc - .cfi_def_cfa rsp, 8 - - /* Spill callee save regs */ - PUSH %rbx - PUSH %rbp - PUSH %r12 - PUSH %r13 - PUSH %r14 - PUSH %r15 - - /* Allocate frame */ - subq $FRAME_SIZE, %rsp - .cfi_adjust_cfa_offset FRAME_SIZE - - /* Remember the return register */ - movq IN_ARG3, SHADOWFRAME_RESULT_REGISTER_OFFSET(IN_ARG2) - - /* Remember the code_item */ - movq IN_ARG1, SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET(IN_ARG2) - - /* set up "named" registers */ - movl SHADOWFRAME_NUMBER_OF_VREGS_OFFSET(IN_ARG2), %eax - leaq SHADOWFRAME_VREGS_OFFSET(IN_ARG2), rFP - leaq (rFP, %rax, 4), rREFS - movl SHADOWFRAME_DEX_PC_OFFSET(IN_ARG2), %eax - leaq (IN_ARG1, %rax, 2), rPC - CFI_DEFINE_DEX_PC_WITH_OFFSET(CFI_TMP, CFI_DEX, 0) - EXPORT_PC - - /* Starting ibase */ - movq IN_ARG0, rSELF - REFRESH_IBASE_REG IN_ARG0 - - /* Set up for backwards branches & osr profiling */ - movq IN_ARG0, OUT_ARG2 /* Set up OUT_ARG2 before clobbering IN_ARG0 */ - movq OFF_FP_METHOD(rFP), OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - call SYMBOL(MterpSetUpHotnessCountdown) - movswl %ax, rPROFILE - - /* start executing the instruction at rPC */ - FETCH_INST - GOTO_NEXT - /* NOTE: no fallthrough */ - -/* File: x86_64/instruction_start.S */ - - OBJECT_TYPE(artMterpAsmInstructionStart) - ASM_HIDDEN SYMBOL(artMterpAsmInstructionStart) - .global SYMBOL(artMterpAsmInstructionStart) -SYMBOL(artMterpAsmInstructionStart) = .L_op_nop - .text - -/* ------------------------------ */ - .balign 128 -.L_op_nop: /* 0x00 */ -/* File: x86_64/op_nop.S */ - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_move: /* 0x01 */ -/* File: x86_64/op_move.S */ - /* for move, move-object, long-to-int */ - /* op vA, vB */ - movl rINST, %eax # eax <- BA - andb $0xf, %al # eax <- A - shrl $4, rINST # rINST <- B - GET_VREG %edx, rINSTq - .if 0 - SET_VREG_OBJECT %edx, %rax # fp[A] <- fp[B] - .else - SET_VREG %edx, %rax # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_move_from16: /* 0x02 */ -/* File: x86_64/op_move_from16.S */ - /* for: move/from16, move-object/from16 */ - /* op vAA, vBBBB */ - movzwq 2(rPC), %rax # eax <- BBBB - GET_VREG %edx, %rax # edx <- fp[BBBB] - .if 0 - SET_VREG_OBJECT %edx, rINSTq # fp[A] <- fp[B] - .else - SET_VREG %edx, rINSTq # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_move_16: /* 0x03 */ -/* File: x86_64/op_move_16.S */ - /* for: move/16, move-object/16 */ - /* op vAAAA, vBBBB */ - movzwq 4(rPC), %rcx # ecx <- BBBB - movzwq 2(rPC), %rax # eax <- AAAA - GET_VREG %edx, %rcx - .if 0 - SET_VREG_OBJECT %edx, %rax # fp[A] <- fp[B] - .else - SET_VREG %edx, %rax # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 - -/* ------------------------------ */ - .balign 128 -.L_op_move_wide: /* 0x04 */ -/* File: x86_64/op_move_wide.S */ - /* move-wide vA, vB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - movl rINST, %ecx # ecx <- BA - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - GET_WIDE_VREG %rdx, rINSTq # rdx <- v[B] - SET_WIDE_VREG %rdx, %rcx # v[A] <- rdx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_move_wide_from16: /* 0x05 */ -/* File: x86_64/op_move_wide_from16.S */ - /* move-wide/from16 vAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - movzwl 2(rPC), %ecx # ecx <- BBBB - GET_WIDE_VREG %rdx, %rcx # rdx <- v[B] - SET_WIDE_VREG %rdx, rINSTq # v[A] <- rdx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_move_wide_16: /* 0x06 */ -/* File: x86_64/op_move_wide_16.S */ - /* move-wide/16 vAAAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - movzwq 4(rPC), %rcx # ecx<- BBBB - movzwq 2(rPC), %rax # eax<- AAAA - GET_WIDE_VREG %rdx, %rcx # rdx <- v[B] - SET_WIDE_VREG %rdx, %rax # v[A] <- rdx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 - -/* ------------------------------ */ - .balign 128 -.L_op_move_object: /* 0x07 */ -/* File: x86_64/op_move_object.S */ -/* File: x86_64/op_move.S */ - /* for move, move-object, long-to-int */ - /* op vA, vB */ - movl rINST, %eax # eax <- BA - andb $0xf, %al # eax <- A - shrl $4, rINST # rINST <- B - GET_VREG %edx, rINSTq - .if 1 - SET_VREG_OBJECT %edx, %rax # fp[A] <- fp[B] - .else - SET_VREG %edx, %rax # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_move_object_from16: /* 0x08 */ -/* File: x86_64/op_move_object_from16.S */ -/* File: x86_64/op_move_from16.S */ - /* for: move/from16, move-object/from16 */ - /* op vAA, vBBBB */ - movzwq 2(rPC), %rax # eax <- BBBB - GET_VREG %edx, %rax # edx <- fp[BBBB] - .if 1 - SET_VREG_OBJECT %edx, rINSTq # fp[A] <- fp[B] - .else - SET_VREG %edx, rINSTq # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_move_object_16: /* 0x09 */ -/* File: x86_64/op_move_object_16.S */ -/* File: x86_64/op_move_16.S */ - /* for: move/16, move-object/16 */ - /* op vAAAA, vBBBB */ - movzwq 4(rPC), %rcx # ecx <- BBBB - movzwq 2(rPC), %rax # eax <- AAAA - GET_VREG %edx, %rcx - .if 1 - SET_VREG_OBJECT %edx, %rax # fp[A] <- fp[B] - .else - SET_VREG %edx, %rax # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 - - -/* ------------------------------ */ - .balign 128 -.L_op_move_result: /* 0x0a */ -/* File: x86_64/op_move_result.S */ - /* for: move-result, move-result-object */ - /* op vAA */ - movq OFF_FP_RESULT_REGISTER(rFP), %rax # get pointer to result JType. - movl (%rax), %eax # r0 <- result.i. - .if 0 - SET_VREG_OBJECT %eax, rINSTq # fp[A] <- fp[B] - .else - SET_VREG %eax, rINSTq # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_move_result_wide: /* 0x0b */ -/* File: x86_64/op_move_result_wide.S */ - /* move-result-wide vAA */ - movq OFF_FP_RESULT_REGISTER(rFP), %rax # get pointer to result JType. - movq (%rax), %rdx # Get wide - SET_WIDE_VREG %rdx, rINSTq # v[AA] <- rdx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_move_result_object: /* 0x0c */ -/* File: x86_64/op_move_result_object.S */ -/* File: x86_64/op_move_result.S */ - /* for: move-result, move-result-object */ - /* op vAA */ - movq OFF_FP_RESULT_REGISTER(rFP), %rax # get pointer to result JType. - movl (%rax), %eax # r0 <- result.i. - .if 1 - SET_VREG_OBJECT %eax, rINSTq # fp[A] <- fp[B] - .else - SET_VREG %eax, rINSTq # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_move_exception: /* 0x0d */ -/* File: x86_64/op_move_exception.S */ - /* move-exception vAA */ - movq rSELF, %rcx - movl THREAD_EXCEPTION_OFFSET(%rcx), %eax - SET_VREG_OBJECT %eax, rINSTq # fp[AA] <- exception object - movl $0, THREAD_EXCEPTION_OFFSET(%rcx) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_return_void: /* 0x0e */ -/* File: x86_64/op_return_void.S */ - .extern MterpThreadFenceForConstructor - call SYMBOL(MterpThreadFenceForConstructor) - movq rSELF, OUT_ARG0 - testl $(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(OUT_ARG0) - jz 1f - call SYMBOL(MterpSuspendCheck) -1: - xorq %rax, %rax - jmp MterpReturn - -/* ------------------------------ */ - .balign 128 -.L_op_return: /* 0x0f */ -/* File: x86_64/op_return.S */ -/* - * Return a 32-bit value. - * - * for: return, return-object - */ - /* op vAA */ - .extern MterpThreadFenceForConstructor - call SYMBOL(MterpThreadFenceForConstructor) - movq rSELF, OUT_ARG0 - testl $(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(OUT_ARG0) - jz 1f - call SYMBOL(MterpSuspendCheck) -1: - GET_VREG %eax, rINSTq # eax <- vAA - jmp MterpReturn - -/* ------------------------------ */ - .balign 128 -.L_op_return_wide: /* 0x10 */ -/* File: x86_64/op_return_wide.S */ -/* - * Return a 64-bit value. - */ - /* return-wide vAA */ - .extern MterpThreadFenceForConstructor - call SYMBOL(MterpThreadFenceForConstructor) - movq rSELF, OUT_ARG0 - testl $(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(OUT_ARG0) - jz 1f - call SYMBOL(MterpSuspendCheck) -1: - GET_WIDE_VREG %rax, rINSTq # eax <- v[AA] - jmp MterpReturn - -/* ------------------------------ */ - .balign 128 -.L_op_return_object: /* 0x11 */ -/* File: x86_64/op_return_object.S */ -/* File: x86_64/op_return.S */ -/* - * Return a 32-bit value. - * - * for: return, return-object - */ - /* op vAA */ - .extern MterpThreadFenceForConstructor - call SYMBOL(MterpThreadFenceForConstructor) - movq rSELF, OUT_ARG0 - testl $(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(OUT_ARG0) - jz 1f - call SYMBOL(MterpSuspendCheck) -1: - GET_VREG %eax, rINSTq # eax <- vAA - jmp MterpReturn - - -/* ------------------------------ */ - .balign 128 -.L_op_const_4: /* 0x12 */ -/* File: x86_64/op_const_4.S */ - /* const/4 vA, #+B */ - movsbl rINSTbl, %eax # eax <-ssssssBx - movl $0xf, rINST - andl %eax, rINST # rINST <- A - sarl $4, %eax - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_const_16: /* 0x13 */ -/* File: x86_64/op_const_16.S */ - /* const/16 vAA, #+BBBB */ - movswl 2(rPC), %ecx # ecx <- ssssBBBB - SET_VREG %ecx, rINSTq # vAA <- ssssBBBB - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_const: /* 0x14 */ -/* File: x86_64/op_const.S */ - /* const vAA, #+BBBBbbbb */ - movl 2(rPC), %eax # grab all 32 bits at once - SET_VREG %eax, rINSTq # vAA<- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 - -/* ------------------------------ */ - .balign 128 -.L_op_const_high16: /* 0x15 */ -/* File: x86_64/op_const_high16.S */ - /* const/high16 vAA, #+BBBB0000 */ - movzwl 2(rPC), %eax # eax <- 0000BBBB - sall $16, %eax # eax <- BBBB0000 - SET_VREG %eax, rINSTq # vAA <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_const_wide_16: /* 0x16 */ -/* File: x86_64/op_const_wide_16.S */ - /* const-wide/16 vAA, #+BBBB */ - movswq 2(rPC), %rax # rax <- ssssBBBB - SET_WIDE_VREG %rax, rINSTq # store - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_const_wide_32: /* 0x17 */ -/* File: x86_64/op_const_wide_32.S */ - /* const-wide/32 vAA, #+BBBBbbbb */ - movslq 2(rPC), %rax # eax <- ssssssssBBBBbbbb - SET_WIDE_VREG %rax, rINSTq # store - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 - -/* ------------------------------ */ - .balign 128 -.L_op_const_wide: /* 0x18 */ -/* File: x86_64/op_const_wide.S */ - /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ - movq 2(rPC), %rax # rax <- HHHHhhhhBBBBbbbb - SET_WIDE_VREG %rax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 5 - -/* ------------------------------ */ - .balign 128 -.L_op_const_wide_high16: /* 0x19 */ -/* File: x86_64/op_const_wide_high16.S */ - /* const-wide/high16 vAA, #+BBBB000000000000 */ - movzwq 2(rPC), %rax # eax <- 0000BBBB - salq $48, %rax # eax <- BBBB0000 - SET_WIDE_VREG %rax, rINSTq # v[AA+0] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_const_string: /* 0x1a */ -/* File: x86_64/op_const_string.S */ -/* File: x86_64/const.S */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstString - EXPORT_PC - movzwq 2(rPC), OUT_ARG0 # eax <- OUT_ARG0 - movq rINSTq, OUT_ARG1 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 - movq rSELF, OUT_ARG3 - call SYMBOL(MterpConstString) # (index, tgt_reg, shadow_frame, self) - testb %al, %al - jnz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_const_string_jumbo: /* 0x1b */ -/* File: x86_64/op_const_string_jumbo.S */ - /* const/string vAA, String@BBBBBBBB */ - EXPORT_PC - movl 2(rPC), OUT_32_ARG0 # OUT_32_ARG0 <- BBBB - movq rINSTq, OUT_ARG1 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 - movq rSELF, OUT_ARG3 - call SYMBOL(MterpConstString) # (index, tgt_reg, shadow_frame, self) - testb %al, %al - jnz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 - -/* ------------------------------ */ - .balign 128 -.L_op_const_class: /* 0x1c */ -/* File: x86_64/op_const_class.S */ -/* File: x86_64/const.S */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstClass - EXPORT_PC - movzwq 2(rPC), OUT_ARG0 # eax <- OUT_ARG0 - movq rINSTq, OUT_ARG1 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 - movq rSELF, OUT_ARG3 - call SYMBOL(MterpConstClass) # (index, tgt_reg, shadow_frame, self) - testb %al, %al - jnz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_monitor_enter: /* 0x1d */ -/* File: x86_64/op_monitor_enter.S */ -/* - * Synchronize on an object. - */ - /* monitor-enter vAA */ - EXPORT_PC - GET_VREG OUT_32_ARG0, rINSTq - movq rSELF, OUT_ARG1 - call SYMBOL(artLockObjectFromCode) # (object, self) - testq %rax, %rax - jnz MterpException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_monitor_exit: /* 0x1e */ -/* File: x86_64/op_monitor_exit.S */ -/* - * Unlock an object. - * - * Exceptions that occur when unlocking a monitor need to appear as - * if they happened at the following instruction. See the Dalvik - * instruction spec. - */ - /* monitor-exit vAA */ - EXPORT_PC - GET_VREG OUT_32_ARG0, rINSTq - movq rSELF, OUT_ARG1 - call SYMBOL(artUnlockObjectFromCode) # (object, self) - testq %rax, %rax - jnz MterpException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_check_cast: /* 0x1f */ -/* File: x86_64/op_check_cast.S */ -/* - * Check to see if a cast from one class to another is allowed. - */ - /* check-cast vAA, class@BBBB */ - EXPORT_PC - movzwq 2(rPC), OUT_ARG0 # OUT_ARG0 <- BBBB - leaq VREG_ADDRESS(rINSTq), OUT_ARG1 - movq OFF_FP_METHOD(rFP), OUT_ARG2 - movq rSELF, OUT_ARG3 - call SYMBOL(MterpCheckCast) # (index, &obj, method, self) - testb %al, %al - jnz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_instance_of: /* 0x20 */ -/* File: x86_64/op_instance_of.S */ -/* - * Check to see if an object reference is an instance of a class. - * - * Most common situation is a non-null object, being compared against - * an already-resolved class. - */ - /* instance-of vA, vB, class@CCCC */ - EXPORT_PC - movzwl 2(rPC), OUT_32_ARG0 # OUT_32_ARG0 <- CCCC - movl rINST, %eax # eax <- BA - sarl $4, %eax # eax <- B - leaq VREG_ADDRESS(%rax), OUT_ARG1 # Get object address - movq OFF_FP_METHOD(rFP), OUT_ARG2 - movq rSELF, OUT_ARG3 - call SYMBOL(MterpInstanceOf) # (index, &obj, method, self) - movsbl %al, %eax - movq rSELF, %rcx - cmpq $0, THREAD_EXCEPTION_OFFSET(%rcx) - jnz MterpException - andb $0xf, rINSTbl # rINSTbl <- A - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_array_length: /* 0x21 */ -/* File: x86_64/op_array_length.S */ -/* - * Return the length of an array. - */ - movl rINST, %eax # eax <- BA - sarl $4, rINST # rINST <- B - GET_VREG %ecx, rINSTq # ecx <- vB (object ref) - testl %ecx, %ecx # is null? - je common_errNullObject - andb $0xf, %al # eax <- A - movl MIRROR_ARRAY_LENGTH_OFFSET(%rcx), rINST - SET_VREG rINST, %rax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_new_instance: /* 0x22 */ -/* File: x86_64/op_new_instance.S */ -/* - * Create a new instance of a class. - */ - /* new-instance vAA, class@BBBB */ - EXPORT_PC - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG0 - movq rSELF, OUT_ARG1 - REFRESH_INST 34 - movq rINSTq, OUT_ARG2 - call SYMBOL(MterpNewInstance) - testb %al, %al # 0 means an exception is thrown - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_new_array: /* 0x23 */ -/* File: x86_64/op_new_array.S */ -/* - * Allocate an array of objects, specified with the array class - * and a count. - * - * The verifier guarantees that this is an array class, so we don't - * check for it here. - */ - /* new-array vA, vB, class@CCCC */ - EXPORT_PC - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG0 - movq rPC, OUT_ARG1 - REFRESH_INST 35 - movq rINSTq, OUT_ARG2 - movq rSELF, OUT_ARG3 - call SYMBOL(MterpNewArray) - testb %al, %al # 0 means an exception is thrown - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_filled_new_array: /* 0x24 */ -/* File: x86_64/op_filled_new_array.S */ -/* - * Create a new array with elements filled from registers. - * - * for: filled-new-array, filled-new-array/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ - .extern MterpFilledNewArray - EXPORT_PC - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG0 - movq rPC, OUT_ARG1 - movq rSELF, OUT_ARG2 - call SYMBOL(MterpFilledNewArray) - testb %al, %al # 0 means an exception is thrown - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 - -/* ------------------------------ */ - .balign 128 -.L_op_filled_new_array_range: /* 0x25 */ -/* File: x86_64/op_filled_new_array_range.S */ -/* File: x86_64/op_filled_new_array.S */ -/* - * Create a new array with elements filled from registers. - * - * for: filled-new-array, filled-new-array/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ - .extern MterpFilledNewArrayRange - EXPORT_PC - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG0 - movq rPC, OUT_ARG1 - movq rSELF, OUT_ARG2 - call SYMBOL(MterpFilledNewArrayRange) - testb %al, %al # 0 means an exception is thrown - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 - - -/* ------------------------------ */ - .balign 128 -.L_op_fill_array_data: /* 0x26 */ -/* File: x86_64/op_fill_array_data.S */ - /* fill-array-data vAA, +BBBBBBBB */ - EXPORT_PC - movslq 2(rPC), %rcx # rcx <- ssssssssBBBBbbbb - leaq (rPC,%rcx,2), OUT_ARG1 # OUT_ARG1 <- PC + ssssssssBBBBbbbb*2 - GET_VREG OUT_32_ARG0, rINSTq # OUT_ARG0 <- vAA (array object) - call SYMBOL(MterpFillArrayData) # (obj, payload) - testb %al, %al # 0 means an exception is thrown - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 - -/* ------------------------------ */ - .balign 128 -.L_op_throw: /* 0x27 */ -/* File: x86_64/op_throw.S */ -/* - * Throw an exception object in the current thread. - */ - /* throw vAA */ - EXPORT_PC - GET_VREG %eax, rINSTq # eax<- vAA (exception object) - testb %al, %al - jz common_errNullObject - movq rSELF, %rcx - movq %rax, THREAD_EXCEPTION_OFFSET(%rcx) - jmp MterpException - -/* ------------------------------ */ - .balign 128 -.L_op_goto: /* 0x28 */ -/* File: x86_64/op_goto.S */ -/* - * Unconditional branch, 8-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto +AA */ - movsbq rINSTbl, rINSTq # rINSTq <- ssssssAA - testq rINSTq, rINSTq - jmp MterpCommonTakenBranch - -/* ------------------------------ */ - .balign 128 -.L_op_goto_16: /* 0x29 */ -/* File: x86_64/op_goto_16.S */ -/* - * Unconditional branch, 16-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto/16 +AAAA */ - movswq 2(rPC), rINSTq # rINSTq <- ssssAAAA - testq rINSTq, rINSTq - jmp MterpCommonTakenBranch - -/* ------------------------------ */ - .balign 128 -.L_op_goto_32: /* 0x2a */ -/* File: x86_64/op_goto_32.S */ -/* - * Unconditional branch, 32-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - * - * Because we need the SF bit set, we'll use an adds - * to convert from Dalvik offset to byte offset. - */ - /* goto/32 +AAAAAAAA */ - movslq 2(rPC), rINSTq # rINSTq <- AAAAAAAA - testq rINSTq, rINSTq - jmp MterpCommonTakenBranch - -/* ------------------------------ */ - .balign 128 -.L_op_packed_switch: /* 0x2b */ -/* File: x86_64/op_packed_switch.S */ -/* - * Handle a packed-switch or sparse-switch instruction. In both cases - * we decode it and hand it off to a helper function. - * - * We don't really expect backward branches in a switch statement, but - * they're perfectly legal, so we check for them here. - * - * for: packed-switch, sparse-switch - */ - /* op vAA, +BBBB */ - movslq 2(rPC), OUT_ARG0 # rcx <- ssssssssBBBBbbbb - leaq (rPC,OUT_ARG0,2), OUT_ARG0 # rcx <- PC + ssssssssBBBBbbbb*2 - GET_VREG OUT_32_ARG1, rINSTq # eax <- vAA - call SYMBOL(MterpDoPackedSwitch) - testl %eax, %eax - movslq %eax, rINSTq - jmp MterpCommonTakenBranch - -/* ------------------------------ */ - .balign 128 -.L_op_sparse_switch: /* 0x2c */ -/* File: x86_64/op_sparse_switch.S */ -/* File: x86_64/op_packed_switch.S */ -/* - * Handle a packed-switch or sparse-switch instruction. In both cases - * we decode it and hand it off to a helper function. - * - * We don't really expect backward branches in a switch statement, but - * they're perfectly legal, so we check for them here. - * - * for: packed-switch, sparse-switch - */ - /* op vAA, +BBBB */ - movslq 2(rPC), OUT_ARG0 # rcx <- ssssssssBBBBbbbb - leaq (rPC,OUT_ARG0,2), OUT_ARG0 # rcx <- PC + ssssssssBBBBbbbb*2 - GET_VREG OUT_32_ARG1, rINSTq # eax <- vAA - call SYMBOL(MterpDoSparseSwitch) - testl %eax, %eax - movslq %eax, rINSTq - jmp MterpCommonTakenBranch - - -/* ------------------------------ */ - .balign 128 -.L_op_cmpl_float: /* 0x2d */ -/* File: x86_64/op_cmpl_float.S */ -/* File: x86_64/fpcmp.S */ -/* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * int compare(x, y) { - * if (x == y) { - * return 0; - * } else if (x < y) { - * return -1; - * } else if (x > y) { - * return 1; - * } else { - * return nanval ? 1 : -1; - * } - * } - */ - /* op vAA, vBB, vCC */ - movzbq 3(rPC), %rcx # ecx<- CC - movzbq 2(rPC), %rax # eax<- BB - movss VREG_ADDRESS(%rax), %xmm0 - xor %eax, %eax - ucomiss VREG_ADDRESS(%rcx), %xmm0 - jp .Lop_cmpl_float_nan_is_neg - je .Lop_cmpl_float_finish - jb .Lop_cmpl_float_less -.Lop_cmpl_float_nan_is_pos: - addb $1, %al - jmp .Lop_cmpl_float_finish -.Lop_cmpl_float_nan_is_neg: -.Lop_cmpl_float_less: - movl $-1, %eax -.Lop_cmpl_float_finish: - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_cmpg_float: /* 0x2e */ -/* File: x86_64/op_cmpg_float.S */ -/* File: x86_64/fpcmp.S */ -/* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * int compare(x, y) { - * if (x == y) { - * return 0; - * } else if (x < y) { - * return -1; - * } else if (x > y) { - * return 1; - * } else { - * return nanval ? 1 : -1; - * } - * } - */ - /* op vAA, vBB, vCC */ - movzbq 3(rPC), %rcx # ecx<- CC - movzbq 2(rPC), %rax # eax<- BB - movss VREG_ADDRESS(%rax), %xmm0 - xor %eax, %eax - ucomiss VREG_ADDRESS(%rcx), %xmm0 - jp .Lop_cmpg_float_nan_is_pos - je .Lop_cmpg_float_finish - jb .Lop_cmpg_float_less -.Lop_cmpg_float_nan_is_pos: - addb $1, %al - jmp .Lop_cmpg_float_finish -.Lop_cmpg_float_nan_is_neg: -.Lop_cmpg_float_less: - movl $-1, %eax -.Lop_cmpg_float_finish: - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_cmpl_double: /* 0x2f */ -/* File: x86_64/op_cmpl_double.S */ -/* File: x86_64/fpcmp.S */ -/* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * int compare(x, y) { - * if (x == y) { - * return 0; - * } else if (x < y) { - * return -1; - * } else if (x > y) { - * return 1; - * } else { - * return nanval ? 1 : -1; - * } - * } - */ - /* op vAA, vBB, vCC */ - movzbq 3(rPC), %rcx # ecx<- CC - movzbq 2(rPC), %rax # eax<- BB - movsd VREG_ADDRESS(%rax), %xmm0 - xor %eax, %eax - ucomisd VREG_ADDRESS(%rcx), %xmm0 - jp .Lop_cmpl_double_nan_is_neg - je .Lop_cmpl_double_finish - jb .Lop_cmpl_double_less -.Lop_cmpl_double_nan_is_pos: - addb $1, %al - jmp .Lop_cmpl_double_finish -.Lop_cmpl_double_nan_is_neg: -.Lop_cmpl_double_less: - movl $-1, %eax -.Lop_cmpl_double_finish: - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_cmpg_double: /* 0x30 */ -/* File: x86_64/op_cmpg_double.S */ -/* File: x86_64/fpcmp.S */ -/* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * int compare(x, y) { - * if (x == y) { - * return 0; - * } else if (x < y) { - * return -1; - * } else if (x > y) { - * return 1; - * } else { - * return nanval ? 1 : -1; - * } - * } - */ - /* op vAA, vBB, vCC */ - movzbq 3(rPC), %rcx # ecx<- CC - movzbq 2(rPC), %rax # eax<- BB - movsd VREG_ADDRESS(%rax), %xmm0 - xor %eax, %eax - ucomisd VREG_ADDRESS(%rcx), %xmm0 - jp .Lop_cmpg_double_nan_is_pos - je .Lop_cmpg_double_finish - jb .Lop_cmpg_double_less -.Lop_cmpg_double_nan_is_pos: - addb $1, %al - jmp .Lop_cmpg_double_finish -.Lop_cmpg_double_nan_is_neg: -.Lop_cmpg_double_less: - movl $-1, %eax -.Lop_cmpg_double_finish: - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_cmp_long: /* 0x31 */ -/* File: x86_64/op_cmp_long.S */ -/* - * Compare two 64-bit values. Puts 0, 1, or -1 into the destination - * register based on the results of the comparison. - */ - /* cmp-long vAA, vBB, vCC */ - movzbq 2(rPC), %rdx # edx <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_WIDE_VREG %rdx, %rdx # rdx <- v[BB] - xorl %eax, %eax - xorl %edi, %edi - addb $1, %al - movl $-1, %esi - cmpq VREG_ADDRESS(%rcx), %rdx - cmovl %esi, %edi - cmovg %eax, %edi - SET_VREG %edi, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_if_eq: /* 0x32 */ -/* File: x86_64/op_if_eq.S */ -/* File: x86_64/bincmp.S */ -/* - * Generic two-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # rcx <- A - GET_VREG %eax, %rcx # eax <- vA - cmpl VREG_ADDRESS(rINSTq), %eax # compare (vA, vB) - jne 1f - movswq 2(rPC), rINSTq # Get signed branch offset - testq rINSTq, rINSTq - jmp MterpCommonTakenBranch -1: - cmpl $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_if_ne: /* 0x33 */ -/* File: x86_64/op_if_ne.S */ -/* File: x86_64/bincmp.S */ -/* - * Generic two-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # rcx <- A - GET_VREG %eax, %rcx # eax <- vA - cmpl VREG_ADDRESS(rINSTq), %eax # compare (vA, vB) - je 1f - movswq 2(rPC), rINSTq # Get signed branch offset - testq rINSTq, rINSTq - jmp MterpCommonTakenBranch -1: - cmpl $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_if_lt: /* 0x34 */ -/* File: x86_64/op_if_lt.S */ -/* File: x86_64/bincmp.S */ -/* - * Generic two-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # rcx <- A - GET_VREG %eax, %rcx # eax <- vA - cmpl VREG_ADDRESS(rINSTq), %eax # compare (vA, vB) - jge 1f - movswq 2(rPC), rINSTq # Get signed branch offset - testq rINSTq, rINSTq - jmp MterpCommonTakenBranch -1: - cmpl $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_if_ge: /* 0x35 */ -/* File: x86_64/op_if_ge.S */ -/* File: x86_64/bincmp.S */ -/* - * Generic two-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # rcx <- A - GET_VREG %eax, %rcx # eax <- vA - cmpl VREG_ADDRESS(rINSTq), %eax # compare (vA, vB) - jl 1f - movswq 2(rPC), rINSTq # Get signed branch offset - testq rINSTq, rINSTq - jmp MterpCommonTakenBranch -1: - cmpl $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_if_gt: /* 0x36 */ -/* File: x86_64/op_if_gt.S */ -/* File: x86_64/bincmp.S */ -/* - * Generic two-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # rcx <- A - GET_VREG %eax, %rcx # eax <- vA - cmpl VREG_ADDRESS(rINSTq), %eax # compare (vA, vB) - jle 1f - movswq 2(rPC), rINSTq # Get signed branch offset - testq rINSTq, rINSTq - jmp MterpCommonTakenBranch -1: - cmpl $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_if_le: /* 0x37 */ -/* File: x86_64/op_if_le.S */ -/* File: x86_64/bincmp.S */ -/* - * Generic two-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # rcx <- A - GET_VREG %eax, %rcx # eax <- vA - cmpl VREG_ADDRESS(rINSTq), %eax # compare (vA, vB) - jg 1f - movswq 2(rPC), rINSTq # Get signed branch offset - testq rINSTq, rINSTq - jmp MterpCommonTakenBranch -1: - cmpl $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_if_eqz: /* 0x38 */ -/* File: x86_64/op_if_eqz.S */ -/* File: x86_64/zcmp.S */ -/* - * Generic one-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - cmpl $0, VREG_ADDRESS(rINSTq) # compare (vA, 0) - jne 1f - movswq 2(rPC), rINSTq # fetch signed displacement - testq rINSTq, rINSTq - jmp MterpCommonTakenBranch -1: - cmpl $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_if_nez: /* 0x39 */ -/* File: x86_64/op_if_nez.S */ -/* File: x86_64/zcmp.S */ -/* - * Generic one-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - cmpl $0, VREG_ADDRESS(rINSTq) # compare (vA, 0) - je 1f - movswq 2(rPC), rINSTq # fetch signed displacement - testq rINSTq, rINSTq - jmp MterpCommonTakenBranch -1: - cmpl $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_if_ltz: /* 0x3a */ -/* File: x86_64/op_if_ltz.S */ -/* File: x86_64/zcmp.S */ -/* - * Generic one-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - cmpl $0, VREG_ADDRESS(rINSTq) # compare (vA, 0) - jge 1f - movswq 2(rPC), rINSTq # fetch signed displacement - testq rINSTq, rINSTq - jmp MterpCommonTakenBranch -1: - cmpl $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_if_gez: /* 0x3b */ -/* File: x86_64/op_if_gez.S */ -/* File: x86_64/zcmp.S */ -/* - * Generic one-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - cmpl $0, VREG_ADDRESS(rINSTq) # compare (vA, 0) - jl 1f - movswq 2(rPC), rINSTq # fetch signed displacement - testq rINSTq, rINSTq - jmp MterpCommonTakenBranch -1: - cmpl $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_if_gtz: /* 0x3c */ -/* File: x86_64/op_if_gtz.S */ -/* File: x86_64/zcmp.S */ -/* - * Generic one-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - cmpl $0, VREG_ADDRESS(rINSTq) # compare (vA, 0) - jle 1f - movswq 2(rPC), rINSTq # fetch signed displacement - testq rINSTq, rINSTq - jmp MterpCommonTakenBranch -1: - cmpl $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_if_lez: /* 0x3d */ -/* File: x86_64/op_if_lez.S */ -/* File: x86_64/zcmp.S */ -/* - * Generic one-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - cmpl $0, VREG_ADDRESS(rINSTq) # compare (vA, 0) - jg 1f - movswq 2(rPC), rINSTq # fetch signed displacement - testq rINSTq, rINSTq - jmp MterpCommonTakenBranch -1: - cmpl $JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_3e: /* 0x3e */ -/* File: x86_64/op_unused_3e.S */ -/* File: x86_64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_3f: /* 0x3f */ -/* File: x86_64/op_unused_3f.S */ -/* File: x86_64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_40: /* 0x40 */ -/* File: x86_64/op_unused_40.S */ -/* File: x86_64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_41: /* 0x41 */ -/* File: x86_64/op_unused_41.S */ -/* File: x86_64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_42: /* 0x42 */ -/* File: x86_64/op_unused_42.S */ -/* File: x86_64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_43: /* 0x43 */ -/* File: x86_64/op_unused_43.S */ -/* File: x86_64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_aget: /* 0x44 */ -/* File: x86_64/op_aget.S */ -/* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short, aget-wide - * - */ - /* op vAA, vBB, vCC */ - movzbq 2(rPC), %rax # eax <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_VREG %eax, %rax # eax <- vBB (array object) - GET_VREG %ecx, %rcx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - .if 0 - movq MIRROR_INT_ARRAY_DATA_OFFSET(%rax,%rcx,8), %rax - SET_WIDE_VREG %rax, rINSTq - .else - movl MIRROR_INT_ARRAY_DATA_OFFSET(%rax,%rcx,4), %eax - SET_VREG %eax, rINSTq - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_aget_wide: /* 0x45 */ -/* File: x86_64/op_aget_wide.S */ -/* File: x86_64/op_aget.S */ -/* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short, aget-wide - * - */ - /* op vAA, vBB, vCC */ - movzbq 2(rPC), %rax # eax <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_VREG %eax, %rax # eax <- vBB (array object) - GET_VREG %ecx, %rcx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - .if 1 - movq MIRROR_WIDE_ARRAY_DATA_OFFSET(%rax,%rcx,8), %rax - SET_WIDE_VREG %rax, rINSTq - .else - movq MIRROR_WIDE_ARRAY_DATA_OFFSET(%rax,%rcx,8), %eax - SET_VREG %eax, rINSTq - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_aget_object: /* 0x46 */ -/* File: x86_64/op_aget_object.S */ -/* - * Array object get. vAA <- vBB[vCC]. - * - * for: aget-object - */ - /* op vAA, vBB, vCC */ - movzbq 2(rPC), %rax # rax <- BB - movzbq 3(rPC), %rcx # rcx <- CC - GET_VREG OUT_32_ARG0, %rax # eax <- vBB (array object) - GET_VREG OUT_32_ARG1, %rcx # ecx <- vCC (requested index) - EXPORT_PC - call SYMBOL(artAGetObjectFromMterp) # (array, index) - movq rSELF, %rcx - cmpq $0, THREAD_EXCEPTION_OFFSET(%rcx) - jnz MterpException - SET_VREG_OBJECT %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_aget_boolean: /* 0x47 */ -/* File: x86_64/op_aget_boolean.S */ -/* File: x86_64/op_aget.S */ -/* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short, aget-wide - * - */ - /* op vAA, vBB, vCC */ - movzbq 2(rPC), %rax # eax <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_VREG %eax, %rax # eax <- vBB (array object) - GET_VREG %ecx, %rcx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - .if 0 - movq MIRROR_BOOLEAN_ARRAY_DATA_OFFSET(%rax,%rcx,8), %rax - SET_WIDE_VREG %rax, rINSTq - .else - movzbl MIRROR_BOOLEAN_ARRAY_DATA_OFFSET(%rax,%rcx,1), %eax - SET_VREG %eax, rINSTq - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_aget_byte: /* 0x48 */ -/* File: x86_64/op_aget_byte.S */ -/* File: x86_64/op_aget.S */ -/* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short, aget-wide - * - */ - /* op vAA, vBB, vCC */ - movzbq 2(rPC), %rax # eax <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_VREG %eax, %rax # eax <- vBB (array object) - GET_VREG %ecx, %rcx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - .if 0 - movq MIRROR_BYTE_ARRAY_DATA_OFFSET(%rax,%rcx,8), %rax - SET_WIDE_VREG %rax, rINSTq - .else - movsbl MIRROR_BYTE_ARRAY_DATA_OFFSET(%rax,%rcx,1), %eax - SET_VREG %eax, rINSTq - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_aget_char: /* 0x49 */ -/* File: x86_64/op_aget_char.S */ -/* File: x86_64/op_aget.S */ -/* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short, aget-wide - * - */ - /* op vAA, vBB, vCC */ - movzbq 2(rPC), %rax # eax <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_VREG %eax, %rax # eax <- vBB (array object) - GET_VREG %ecx, %rcx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - .if 0 - movq MIRROR_CHAR_ARRAY_DATA_OFFSET(%rax,%rcx,8), %rax - SET_WIDE_VREG %rax, rINSTq - .else - movzwl MIRROR_CHAR_ARRAY_DATA_OFFSET(%rax,%rcx,2), %eax - SET_VREG %eax, rINSTq - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_aget_short: /* 0x4a */ -/* File: x86_64/op_aget_short.S */ -/* File: x86_64/op_aget.S */ -/* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short, aget-wide - * - */ - /* op vAA, vBB, vCC */ - movzbq 2(rPC), %rax # eax <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_VREG %eax, %rax # eax <- vBB (array object) - GET_VREG %ecx, %rcx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - .if 0 - movq MIRROR_SHORT_ARRAY_DATA_OFFSET(%rax,%rcx,8), %rax - SET_WIDE_VREG %rax, rINSTq - .else - movswl MIRROR_SHORT_ARRAY_DATA_OFFSET(%rax,%rcx,2), %eax - SET_VREG %eax, rINSTq - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_aput: /* 0x4b */ -/* File: x86_64/op_aput.S */ -/* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short, aput-wide - * - */ - /* op vAA, vBB, vCC */ - movzbq 2(rPC), %rax # rax <- BB - movzbq 3(rPC), %rcx # rcx <- CC - GET_VREG %eax, %rax # eax <- vBB (array object) - GET_VREG %ecx, %rcx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - .if 0 - GET_WIDE_VREG rINSTq, rINSTq - .else - GET_VREG rINST, rINSTq - .endif - movl rINST, MIRROR_INT_ARRAY_DATA_OFFSET(%rax,%rcx,4) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_aput_wide: /* 0x4c */ -/* File: x86_64/op_aput_wide.S */ -/* File: x86_64/op_aput.S */ -/* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short, aput-wide - * - */ - /* op vAA, vBB, vCC */ - movzbq 2(rPC), %rax # rax <- BB - movzbq 3(rPC), %rcx # rcx <- CC - GET_VREG %eax, %rax # eax <- vBB (array object) - GET_VREG %ecx, %rcx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - .if 1 - GET_WIDE_VREG rINSTq, rINSTq - .else - GET_VREG rINST, rINSTq - .endif - movq rINSTq, MIRROR_WIDE_ARRAY_DATA_OFFSET(%rax,%rcx,8) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_aput_object: /* 0x4d */ -/* File: x86_64/op_aput_object.S */ -/* - * Store an object into an array. vBB[vCC] <- vAA. - */ - /* op vAA, vBB, vCC */ - EXPORT_PC - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG0 - movq rPC, OUT_ARG1 - REFRESH_INST 77 - movq rINSTq, OUT_ARG2 - call SYMBOL(MterpAputObject) # (array, index) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_aput_boolean: /* 0x4e */ -/* File: x86_64/op_aput_boolean.S */ -/* File: x86_64/op_aput.S */ -/* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short, aput-wide - * - */ - /* op vAA, vBB, vCC */ - movzbq 2(rPC), %rax # rax <- BB - movzbq 3(rPC), %rcx # rcx <- CC - GET_VREG %eax, %rax # eax <- vBB (array object) - GET_VREG %ecx, %rcx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - .if 0 - GET_WIDE_VREG rINSTq, rINSTq - .else - GET_VREG rINST, rINSTq - .endif - movb rINSTbl, MIRROR_BOOLEAN_ARRAY_DATA_OFFSET(%rax,%rcx,1) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_aput_byte: /* 0x4f */ -/* File: x86_64/op_aput_byte.S */ -/* File: x86_64/op_aput.S */ -/* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short, aput-wide - * - */ - /* op vAA, vBB, vCC */ - movzbq 2(rPC), %rax # rax <- BB - movzbq 3(rPC), %rcx # rcx <- CC - GET_VREG %eax, %rax # eax <- vBB (array object) - GET_VREG %ecx, %rcx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - .if 0 - GET_WIDE_VREG rINSTq, rINSTq - .else - GET_VREG rINST, rINSTq - .endif - movb rINSTbl, MIRROR_BYTE_ARRAY_DATA_OFFSET(%rax,%rcx,1) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_aput_char: /* 0x50 */ -/* File: x86_64/op_aput_char.S */ -/* File: x86_64/op_aput.S */ -/* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short, aput-wide - * - */ - /* op vAA, vBB, vCC */ - movzbq 2(rPC), %rax # rax <- BB - movzbq 3(rPC), %rcx # rcx <- CC - GET_VREG %eax, %rax # eax <- vBB (array object) - GET_VREG %ecx, %rcx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - .if 0 - GET_WIDE_VREG rINSTq, rINSTq - .else - GET_VREG rINST, rINSTq - .endif - movw rINSTw, MIRROR_CHAR_ARRAY_DATA_OFFSET(%rax,%rcx,2) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_aput_short: /* 0x51 */ -/* File: x86_64/op_aput_short.S */ -/* File: x86_64/op_aput.S */ -/* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short, aput-wide - * - */ - /* op vAA, vBB, vCC */ - movzbq 2(rPC), %rax # rax <- BB - movzbq 3(rPC), %rcx # rcx <- CC - GET_VREG %eax, %rax # eax <- vBB (array object) - GET_VREG %ecx, %rcx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - .if 0 - GET_WIDE_VREG rINSTq, rINSTq - .else - GET_VREG rINST, rINSTq - .endif - movw rINSTw, MIRROR_SHORT_ARRAY_DATA_OFFSET(%rax,%rcx,2) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_iget: /* 0x52 */ -/* File: x86_64/op_iget.S */ -/* File: x86_64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetU32 - REFRESH_INST 82 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpIGetU32) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_wide: /* 0x53 */ -/* File: x86_64/op_iget_wide.S */ -/* File: x86_64/op_iget.S */ -/* File: x86_64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetU64 - REFRESH_INST 83 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpIGetU64) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_object: /* 0x54 */ -/* File: x86_64/op_iget_object.S */ -/* File: x86_64/op_iget.S */ -/* File: x86_64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetObj - REFRESH_INST 84 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpIGetObj) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_boolean: /* 0x55 */ -/* File: x86_64/op_iget_boolean.S */ -/* File: x86_64/op_iget.S */ -/* File: x86_64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetU8 - REFRESH_INST 85 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpIGetU8) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_byte: /* 0x56 */ -/* File: x86_64/op_iget_byte.S */ -/* File: x86_64/op_iget.S */ -/* File: x86_64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetI8 - REFRESH_INST 86 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpIGetI8) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_char: /* 0x57 */ -/* File: x86_64/op_iget_char.S */ -/* File: x86_64/op_iget.S */ -/* File: x86_64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetU16 - REFRESH_INST 87 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpIGetU16) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_short: /* 0x58 */ -/* File: x86_64/op_iget_short.S */ -/* File: x86_64/op_iget.S */ -/* File: x86_64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIGetI16 - REFRESH_INST 88 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpIGetI16) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_iput: /* 0x59 */ -/* File: x86_64/op_iput.S */ -/* File: x86_64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutU32 - REFRESH_INST 89 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpIPutU32) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_wide: /* 0x5a */ -/* File: x86_64/op_iput_wide.S */ -/* File: x86_64/op_iput.S */ -/* File: x86_64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutU64 - REFRESH_INST 90 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpIPutU64) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_object: /* 0x5b */ -/* File: x86_64/op_iput_object.S */ -/* File: x86_64/op_iput.S */ -/* File: x86_64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutObj - REFRESH_INST 91 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpIPutObj) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_boolean: /* 0x5c */ -/* File: x86_64/op_iput_boolean.S */ -/* File: x86_64/op_iput.S */ -/* File: x86_64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutU8 - REFRESH_INST 92 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpIPutU8) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_byte: /* 0x5d */ -/* File: x86_64/op_iput_byte.S */ -/* File: x86_64/op_iput.S */ -/* File: x86_64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutI8 - REFRESH_INST 93 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpIPutI8) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_char: /* 0x5e */ -/* File: x86_64/op_iput_char.S */ -/* File: x86_64/op_iput.S */ -/* File: x86_64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutU16 - REFRESH_INST 94 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpIPutU16) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_short: /* 0x5f */ -/* File: x86_64/op_iput_short.S */ -/* File: x86_64/op_iput.S */ -/* File: x86_64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpIPutI16 - REFRESH_INST 95 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpIPutI16) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_sget: /* 0x60 */ -/* File: x86_64/op_sget.S */ -/* File: x86_64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetU32 - REFRESH_INST 96 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpSGetU32) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_sget_wide: /* 0x61 */ -/* File: x86_64/op_sget_wide.S */ -/* File: x86_64/op_sget.S */ -/* File: x86_64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetU64 - REFRESH_INST 97 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpSGetU64) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_sget_object: /* 0x62 */ -/* File: x86_64/op_sget_object.S */ -/* File: x86_64/op_sget.S */ -/* File: x86_64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetObj - REFRESH_INST 98 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpSGetObj) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_sget_boolean: /* 0x63 */ -/* File: x86_64/op_sget_boolean.S */ -/* File: x86_64/op_sget.S */ -/* File: x86_64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetU8 - REFRESH_INST 99 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpSGetU8) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_sget_byte: /* 0x64 */ -/* File: x86_64/op_sget_byte.S */ -/* File: x86_64/op_sget.S */ -/* File: x86_64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetI8 - REFRESH_INST 100 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpSGetI8) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_sget_char: /* 0x65 */ -/* File: x86_64/op_sget_char.S */ -/* File: x86_64/op_sget.S */ -/* File: x86_64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetU16 - REFRESH_INST 101 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpSGetU16) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_sget_short: /* 0x66 */ -/* File: x86_64/op_sget_short.S */ -/* File: x86_64/op_sget.S */ -/* File: x86_64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSGetI16 - REFRESH_INST 102 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpSGetI16) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_sput: /* 0x67 */ -/* File: x86_64/op_sput.S */ -/* File: x86_64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutU32 - REFRESH_INST 103 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpSPutU32) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_sput_wide: /* 0x68 */ -/* File: x86_64/op_sput_wide.S */ -/* File: x86_64/op_sput.S */ -/* File: x86_64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutU64 - REFRESH_INST 104 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpSPutU64) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_sput_object: /* 0x69 */ -/* File: x86_64/op_sput_object.S */ -/* File: x86_64/op_sput.S */ -/* File: x86_64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutObj - REFRESH_INST 105 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpSPutObj) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_sput_boolean: /* 0x6a */ -/* File: x86_64/op_sput_boolean.S */ -/* File: x86_64/op_sput.S */ -/* File: x86_64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutU8 - REFRESH_INST 106 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpSPutU8) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_sput_byte: /* 0x6b */ -/* File: x86_64/op_sput_byte.S */ -/* File: x86_64/op_sput.S */ -/* File: x86_64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutI8 - REFRESH_INST 107 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpSPutI8) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_sput_char: /* 0x6c */ -/* File: x86_64/op_sput_char.S */ -/* File: x86_64/op_sput.S */ -/* File: x86_64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutU16 - REFRESH_INST 108 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpSPutU16) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_sput_short: /* 0x6d */ -/* File: x86_64/op_sput_short.S */ -/* File: x86_64/op_sput.S */ -/* File: x86_64/field.S */ - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern MterpSPutI16 - REFRESH_INST 109 # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL(MterpSPutI16) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual: /* 0x6e */ -/* File: x86_64/op_invoke_virtual.S */ -/* File: x86_64/invoke.S */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtual - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - REFRESH_INST 110 - movl rINST, OUT_32_ARG3 - call SYMBOL(MterpInvokeVirtual) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - FETCH_INST - GOTO_NEXT - -/* - * Handle a virtual method call. - * - * for: invoke-virtual, invoke-virtual/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_super: /* 0x6f */ -/* File: x86_64/op_invoke_super.S */ -/* File: x86_64/invoke.S */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeSuper - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - REFRESH_INST 111 - movl rINST, OUT_32_ARG3 - call SYMBOL(MterpInvokeSuper) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - FETCH_INST - GOTO_NEXT - -/* - * Handle a "super" method call. - * - * for: invoke-super, invoke-super/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_direct: /* 0x70 */ -/* File: x86_64/op_invoke_direct.S */ -/* File: x86_64/invoke.S */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeDirect - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - REFRESH_INST 112 - movl rINST, OUT_32_ARG3 - call SYMBOL(MterpInvokeDirect) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - FETCH_INST - GOTO_NEXT - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_static: /* 0x71 */ -/* File: x86_64/op_invoke_static.S */ -/* File: x86_64/invoke.S */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeStatic - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - REFRESH_INST 113 - movl rINST, OUT_32_ARG3 - call SYMBOL(MterpInvokeStatic) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - FETCH_INST - GOTO_NEXT - - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_interface: /* 0x72 */ -/* File: x86_64/op_invoke_interface.S */ -/* File: x86_64/invoke.S */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeInterface - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - REFRESH_INST 114 - movl rINST, OUT_32_ARG3 - call SYMBOL(MterpInvokeInterface) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - FETCH_INST - GOTO_NEXT - -/* - * Handle an interface method call. - * - * for: invoke-interface, invoke-interface/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - -/* ------------------------------ */ - .balign 128 -.L_op_return_void_no_barrier: /* 0x73 */ -/* File: x86_64/op_return_void_no_barrier.S */ - movq rSELF, OUT_ARG0 - testl $(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(OUT_ARG0) - jz 1f - call SYMBOL(MterpSuspendCheck) -1: - xorq %rax, %rax - jmp MterpReturn - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual_range: /* 0x74 */ -/* File: x86_64/op_invoke_virtual_range.S */ -/* File: x86_64/invoke.S */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtualRange - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - REFRESH_INST 116 - movl rINST, OUT_32_ARG3 - call SYMBOL(MterpInvokeVirtualRange) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - FETCH_INST - GOTO_NEXT - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_super_range: /* 0x75 */ -/* File: x86_64/op_invoke_super_range.S */ -/* File: x86_64/invoke.S */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeSuperRange - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - REFRESH_INST 117 - movl rINST, OUT_32_ARG3 - call SYMBOL(MterpInvokeSuperRange) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - FETCH_INST - GOTO_NEXT - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_direct_range: /* 0x76 */ -/* File: x86_64/op_invoke_direct_range.S */ -/* File: x86_64/invoke.S */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeDirectRange - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - REFRESH_INST 118 - movl rINST, OUT_32_ARG3 - call SYMBOL(MterpInvokeDirectRange) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - FETCH_INST - GOTO_NEXT - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_static_range: /* 0x77 */ -/* File: x86_64/op_invoke_static_range.S */ -/* File: x86_64/invoke.S */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeStaticRange - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - REFRESH_INST 119 - movl rINST, OUT_32_ARG3 - call SYMBOL(MterpInvokeStaticRange) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - FETCH_INST - GOTO_NEXT - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_interface_range: /* 0x78 */ -/* File: x86_64/op_invoke_interface_range.S */ -/* File: x86_64/invoke.S */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeInterfaceRange - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - REFRESH_INST 120 - movl rINST, OUT_32_ARG3 - call SYMBOL(MterpInvokeInterfaceRange) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - FETCH_INST - GOTO_NEXT - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_79: /* 0x79 */ -/* File: x86_64/op_unused_79.S */ -/* File: x86_64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_7a: /* 0x7a */ -/* File: x86_64/op_unused_7a.S */ -/* File: x86_64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_neg_int: /* 0x7b */ -/* File: x86_64/op_neg_int.S */ -/* File: x86_64/unop.S */ -/* - * Generic 32/64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op eax". - */ - /* unop vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4,rINST # rINST <- B - .if 0 - GET_WIDE_VREG %rax, rINSTq # rax <- vB - .else - GET_VREG %eax, rINSTq # eax <- vB - .endif - andb $0xf,%cl # ecx <- A - - negl %eax - .if 0 - SET_WIDE_VREG %rax, %rcx - .else - SET_VREG %eax, %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_not_int: /* 0x7c */ -/* File: x86_64/op_not_int.S */ -/* File: x86_64/unop.S */ -/* - * Generic 32/64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op eax". - */ - /* unop vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4,rINST # rINST <- B - .if 0 - GET_WIDE_VREG %rax, rINSTq # rax <- vB - .else - GET_VREG %eax, rINSTq # eax <- vB - .endif - andb $0xf,%cl # ecx <- A - - notl %eax - .if 0 - SET_WIDE_VREG %rax, %rcx - .else - SET_VREG %eax, %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_neg_long: /* 0x7d */ -/* File: x86_64/op_neg_long.S */ -/* File: x86_64/unop.S */ -/* - * Generic 32/64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op eax". - */ - /* unop vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4,rINST # rINST <- B - .if 1 - GET_WIDE_VREG %rax, rINSTq # rax <- vB - .else - GET_VREG %eax, rINSTq # eax <- vB - .endif - andb $0xf,%cl # ecx <- A - - negq %rax - .if 1 - SET_WIDE_VREG %rax, %rcx - .else - SET_VREG %eax, %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_not_long: /* 0x7e */ -/* File: x86_64/op_not_long.S */ -/* File: x86_64/unop.S */ -/* - * Generic 32/64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op eax". - */ - /* unop vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4,rINST # rINST <- B - .if 1 - GET_WIDE_VREG %rax, rINSTq # rax <- vB - .else - GET_VREG %eax, rINSTq # eax <- vB - .endif - andb $0xf,%cl # ecx <- A - - notq %rax - .if 1 - SET_WIDE_VREG %rax, %rcx - .else - SET_VREG %eax, %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_neg_float: /* 0x7f */ -/* File: x86_64/op_neg_float.S */ -/* File: x86_64/unop.S */ -/* - * Generic 32/64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op eax". - */ - /* unop vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4,rINST # rINST <- B - .if 0 - GET_WIDE_VREG %rax, rINSTq # rax <- vB - .else - GET_VREG %eax, rINSTq # eax <- vB - .endif - andb $0xf,%cl # ecx <- A - - xorl $0x80000000, %eax - .if 0 - SET_WIDE_VREG %rax, %rcx - .else - SET_VREG %eax, %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_neg_double: /* 0x80 */ -/* File: x86_64/op_neg_double.S */ -/* File: x86_64/unop.S */ -/* - * Generic 32/64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op eax". - */ - /* unop vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4,rINST # rINST <- B - .if 1 - GET_WIDE_VREG %rax, rINSTq # rax <- vB - .else - GET_VREG %eax, rINSTq # eax <- vB - .endif - andb $0xf,%cl # ecx <- A - movq $0x8000000000000000, %rsi - xorq %rsi, %rax - .if 1 - SET_WIDE_VREG %rax, %rcx - .else - SET_VREG %eax, %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_long: /* 0x81 */ -/* File: x86_64/op_int_to_long.S */ - /* int to long vA, vB */ - movzbq rINSTbl, %rax # rax <- +A - sarl $4, %eax # eax <- B - andb $0xf, rINSTbl # rINST <- A - movslq VREG_ADDRESS(%rax), %rax - SET_WIDE_VREG %rax, rINSTq # v[A] <- %rax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_float: /* 0x82 */ -/* File: x86_64/op_int_to_float.S */ -/* File: x86_64/fpcvt.S */ -/* - * Generic 32-bit FP conversion operation. - */ - /* unop vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - cvtsi2ssl VREG_ADDRESS(rINSTq), %xmm0 - .if 0 - movsd %xmm0, VREG_ADDRESS(%rcx) - CLEAR_WIDE_REF %rcx - .else - movss %xmm0, VREG_ADDRESS(%rcx) - CLEAR_REF %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_double: /* 0x83 */ -/* File: x86_64/op_int_to_double.S */ -/* File: x86_64/fpcvt.S */ -/* - * Generic 32-bit FP conversion operation. - */ - /* unop vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - cvtsi2sdl VREG_ADDRESS(rINSTq), %xmm0 - .if 1 - movsd %xmm0, VREG_ADDRESS(%rcx) - CLEAR_WIDE_REF %rcx - .else - movss %xmm0, VREG_ADDRESS(%rcx) - CLEAR_REF %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_long_to_int: /* 0x84 */ -/* File: x86_64/op_long_to_int.S */ -/* we ignore the high word, making this equivalent to a 32-bit reg move */ -/* File: x86_64/op_move.S */ - /* for move, move-object, long-to-int */ - /* op vA, vB */ - movl rINST, %eax # eax <- BA - andb $0xf, %al # eax <- A - shrl $4, rINST # rINST <- B - GET_VREG %edx, rINSTq - .if 0 - SET_VREG_OBJECT %edx, %rax # fp[A] <- fp[B] - .else - SET_VREG %edx, %rax # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_long_to_float: /* 0x85 */ -/* File: x86_64/op_long_to_float.S */ -/* File: x86_64/fpcvt.S */ -/* - * Generic 32-bit FP conversion operation. - */ - /* unop vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - cvtsi2ssq VREG_ADDRESS(rINSTq), %xmm0 - .if 0 - movsd %xmm0, VREG_ADDRESS(%rcx) - CLEAR_WIDE_REF %rcx - .else - movss %xmm0, VREG_ADDRESS(%rcx) - CLEAR_REF %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_long_to_double: /* 0x86 */ -/* File: x86_64/op_long_to_double.S */ -/* File: x86_64/fpcvt.S */ -/* - * Generic 32-bit FP conversion operation. - */ - /* unop vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - cvtsi2sdq VREG_ADDRESS(rINSTq), %xmm0 - .if 1 - movsd %xmm0, VREG_ADDRESS(%rcx) - CLEAR_WIDE_REF %rcx - .else - movss %xmm0, VREG_ADDRESS(%rcx) - CLEAR_REF %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_float_to_int: /* 0x87 */ -/* File: x86_64/op_float_to_int.S */ -/* File: x86_64/cvtfp_int.S */ -/* On fp to int conversions, Java requires that - * if the result > maxint, it should be clamped to maxint. If it is less - * than minint, it should be clamped to minint. If it is a nan, the result - * should be zero. Further, the rounding mode is to truncate. - */ - /* float/double to int/long vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - movss VREG_ADDRESS(rINSTq), %xmm0 - movl $0x7fffffff, %eax - cvtsi2ssl %eax, %xmm1 - comiss %xmm1, %xmm0 - jae 1f - jp 2f - cvttss2sil %xmm0, %eax - jmp 1f -2: - xorl %eax, %eax -1: - .if 0 - SET_WIDE_VREG %eax, %rcx - .else - SET_VREG %eax, %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_float_to_long: /* 0x88 */ -/* File: x86_64/op_float_to_long.S */ -/* File: x86_64/cvtfp_int.S */ -/* On fp to int conversions, Java requires that - * if the result > maxint, it should be clamped to maxint. If it is less - * than minint, it should be clamped to minint. If it is a nan, the result - * should be zero. Further, the rounding mode is to truncate. - */ - /* float/double to int/long vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - movss VREG_ADDRESS(rINSTq), %xmm0 - movq $0x7fffffffffffffff, %rax - cvtsi2ssq %rax, %xmm1 - comiss %xmm1, %xmm0 - jae 1f - jp 2f - cvttss2siq %xmm0, %rax - jmp 1f -2: - xorq %rax, %rax -1: - .if 1 - SET_WIDE_VREG %rax, %rcx - .else - SET_VREG %rax, %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_float_to_double: /* 0x89 */ -/* File: x86_64/op_float_to_double.S */ -/* File: x86_64/fpcvt.S */ -/* - * Generic 32-bit FP conversion operation. - */ - /* unop vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - cvtss2sd VREG_ADDRESS(rINSTq), %xmm0 - .if 1 - movsd %xmm0, VREG_ADDRESS(%rcx) - CLEAR_WIDE_REF %rcx - .else - movss %xmm0, VREG_ADDRESS(%rcx) - CLEAR_REF %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_double_to_int: /* 0x8a */ -/* File: x86_64/op_double_to_int.S */ -/* File: x86_64/cvtfp_int.S */ -/* On fp to int conversions, Java requires that - * if the result > maxint, it should be clamped to maxint. If it is less - * than minint, it should be clamped to minint. If it is a nan, the result - * should be zero. Further, the rounding mode is to truncate. - */ - /* float/double to int/long vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - movsd VREG_ADDRESS(rINSTq), %xmm0 - movl $0x7fffffff, %eax - cvtsi2sdl %eax, %xmm1 - comisd %xmm1, %xmm0 - jae 1f - jp 2f - cvttsd2sil %xmm0, %eax - jmp 1f -2: - xorl %eax, %eax -1: - .if 0 - SET_WIDE_VREG %eax, %rcx - .else - SET_VREG %eax, %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_double_to_long: /* 0x8b */ -/* File: x86_64/op_double_to_long.S */ -/* File: x86_64/cvtfp_int.S */ -/* On fp to int conversions, Java requires that - * if the result > maxint, it should be clamped to maxint. If it is less - * than minint, it should be clamped to minint. If it is a nan, the result - * should be zero. Further, the rounding mode is to truncate. - */ - /* float/double to int/long vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - movsd VREG_ADDRESS(rINSTq), %xmm0 - movq $0x7fffffffffffffff, %rax - cvtsi2sdq %rax, %xmm1 - comisd %xmm1, %xmm0 - jae 1f - jp 2f - cvttsd2siq %xmm0, %rax - jmp 1f -2: - xorq %rax, %rax -1: - .if 1 - SET_WIDE_VREG %rax, %rcx - .else - SET_VREG %rax, %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_double_to_float: /* 0x8c */ -/* File: x86_64/op_double_to_float.S */ -/* File: x86_64/fpcvt.S */ -/* - * Generic 32-bit FP conversion operation. - */ - /* unop vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - cvtsd2ss VREG_ADDRESS(rINSTq), %xmm0 - .if 0 - movsd %xmm0, VREG_ADDRESS(%rcx) - CLEAR_WIDE_REF %rcx - .else - movss %xmm0, VREG_ADDRESS(%rcx) - CLEAR_REF %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_byte: /* 0x8d */ -/* File: x86_64/op_int_to_byte.S */ -/* File: x86_64/unop.S */ -/* - * Generic 32/64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op eax". - */ - /* unop vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4,rINST # rINST <- B - .if 0 - GET_WIDE_VREG %rax, rINSTq # rax <- vB - .else - GET_VREG %eax, rINSTq # eax <- vB - .endif - andb $0xf,%cl # ecx <- A - -movsbl %al, %eax - .if 0 - SET_WIDE_VREG %rax, %rcx - .else - SET_VREG %eax, %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_char: /* 0x8e */ -/* File: x86_64/op_int_to_char.S */ -/* File: x86_64/unop.S */ -/* - * Generic 32/64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op eax". - */ - /* unop vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4,rINST # rINST <- B - .if 0 - GET_WIDE_VREG %rax, rINSTq # rax <- vB - .else - GET_VREG %eax, rINSTq # eax <- vB - .endif - andb $0xf,%cl # ecx <- A - -movzwl %ax,%eax - .if 0 - SET_WIDE_VREG %rax, %rcx - .else - SET_VREG %eax, %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_int_to_short: /* 0x8f */ -/* File: x86_64/op_int_to_short.S */ -/* File: x86_64/unop.S */ -/* - * Generic 32/64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op eax". - */ - /* unop vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4,rINST # rINST <- B - .if 0 - GET_WIDE_VREG %rax, rINSTq # rax <- vB - .else - GET_VREG %eax, rINSTq # eax <- vB - .endif - andb $0xf,%cl # ecx <- A - -movswl %ax, %eax - .if 0 - SET_WIDE_VREG %rax, %rcx - .else - SET_VREG %eax, %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_add_int: /* 0x90 */ -/* File: x86_64/op_add_int.S */ -/* File: x86_64/binop.S */ -/* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = eax op (rFP,%ecx,4)". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int, sub-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - movzbq 2(rPC), %rax # rax <- BB - movzbq 3(rPC), %rcx # rcx <- CC - GET_VREG %eax, %rax # eax <- vBB - addl (rFP,%rcx,4), %eax # ex: addl (rFP,%rcx,4),%eax - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_int: /* 0x91 */ -/* File: x86_64/op_sub_int.S */ -/* File: x86_64/binop.S */ -/* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = eax op (rFP,%ecx,4)". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int, sub-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - movzbq 2(rPC), %rax # rax <- BB - movzbq 3(rPC), %rcx # rcx <- CC - GET_VREG %eax, %rax # eax <- vBB - subl (rFP,%rcx,4), %eax # ex: addl (rFP,%rcx,4),%eax - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int: /* 0x92 */ -/* File: x86_64/op_mul_int.S */ -/* File: x86_64/binop.S */ -/* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = eax op (rFP,%ecx,4)". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int, sub-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - movzbq 2(rPC), %rax # rax <- BB - movzbq 3(rPC), %rcx # rcx <- CC - GET_VREG %eax, %rax # eax <- vBB - imull (rFP,%rcx,4), %eax # ex: addl (rFP,%rcx,4),%eax - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_div_int: /* 0x93 */ -/* File: x86_64/op_div_int.S */ -/* File: x86_64/bindiv.S */ -/* - * 32-bit binary div/rem operation. Handles special case of op1=-1. - */ - /* div/rem vAA, vBB, vCC */ - movzbq 2(rPC), %rax # rax <- BB - movzbq 3(rPC), %rcx # rcx <- CC - .if 0 - GET_WIDE_VREG %rax, %rax # eax <- vBB - GET_WIDE_VREG %ecx, %rcx # ecx <- vCC - .else - GET_VREG %eax, %rax # eax <- vBB - GET_VREG %ecx, %rcx # ecx <- vCC - .endif - testl %ecx, %ecx - jz common_errDivideByZero - cmpl $-1, %ecx - je 2f - cdq # rdx:rax <- sign-extended of rax - idivl %ecx -1: - .if 0 - SET_WIDE_VREG %eax, rINSTq # eax <- vBB - .else - SET_VREG %eax, rINSTq # eax <- vBB - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 -2: - .if 0 - xorl %eax, %eax - .else - negl %eax - .endif - jmp 1b - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int: /* 0x94 */ -/* File: x86_64/op_rem_int.S */ -/* File: x86_64/bindiv.S */ -/* - * 32-bit binary div/rem operation. Handles special case of op1=-1. - */ - /* div/rem vAA, vBB, vCC */ - movzbq 2(rPC), %rax # rax <- BB - movzbq 3(rPC), %rcx # rcx <- CC - .if 0 - GET_WIDE_VREG %rax, %rax # eax <- vBB - GET_WIDE_VREG %ecx, %rcx # ecx <- vCC - .else - GET_VREG %eax, %rax # eax <- vBB - GET_VREG %ecx, %rcx # ecx <- vCC - .endif - testl %ecx, %ecx - jz common_errDivideByZero - cmpl $-1, %ecx - je 2f - cdq # rdx:rax <- sign-extended of rax - idivl %ecx -1: - .if 0 - SET_WIDE_VREG %edx, rINSTq # eax <- vBB - .else - SET_VREG %edx, rINSTq # eax <- vBB - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 -2: - .if 1 - xorl %edx, %edx - .else - negl %edx - .endif - jmp 1b - - -/* ------------------------------ */ - .balign 128 -.L_op_and_int: /* 0x95 */ -/* File: x86_64/op_and_int.S */ -/* File: x86_64/binop.S */ -/* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = eax op (rFP,%ecx,4)". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int, sub-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - movzbq 2(rPC), %rax # rax <- BB - movzbq 3(rPC), %rcx # rcx <- CC - GET_VREG %eax, %rax # eax <- vBB - andl (rFP,%rcx,4), %eax # ex: addl (rFP,%rcx,4),%eax - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_or_int: /* 0x96 */ -/* File: x86_64/op_or_int.S */ -/* File: x86_64/binop.S */ -/* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = eax op (rFP,%ecx,4)". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int, sub-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - movzbq 2(rPC), %rax # rax <- BB - movzbq 3(rPC), %rcx # rcx <- CC - GET_VREG %eax, %rax # eax <- vBB - orl (rFP,%rcx,4), %eax # ex: addl (rFP,%rcx,4),%eax - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int: /* 0x97 */ -/* File: x86_64/op_xor_int.S */ -/* File: x86_64/binop.S */ -/* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = eax op (rFP,%ecx,4)". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int, sub-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - movzbq 2(rPC), %rax # rax <- BB - movzbq 3(rPC), %rcx # rcx <- CC - GET_VREG %eax, %rax # eax <- vBB - xorl (rFP,%rcx,4), %eax # ex: addl (rFP,%rcx,4),%eax - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_shl_int: /* 0x98 */ -/* File: x86_64/op_shl_int.S */ -/* File: x86_64/binop1.S */ -/* - * Generic 32-bit binary operation in which both operands loaded to - * registers (op0 in eax, op1 in ecx). - */ - /* binop vAA, vBB, vCC */ - movzbq 2(rPC), %rax # eax <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_VREG %ecx, %rcx # eax <- vCC - .if 0 - GET_WIDE_VREG %rax, %rax # rax <- vBB - sall %cl, %eax # ex: addl %ecx,%eax - SET_WIDE_VREG %rax, rINSTq - .else - GET_VREG %eax, %rax # eax <- vBB - sall %cl, %eax # ex: addl %ecx,%eax - SET_VREG %eax, rINSTq - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_shr_int: /* 0x99 */ -/* File: x86_64/op_shr_int.S */ -/* File: x86_64/binop1.S */ -/* - * Generic 32-bit binary operation in which both operands loaded to - * registers (op0 in eax, op1 in ecx). - */ - /* binop vAA, vBB, vCC */ - movzbq 2(rPC), %rax # eax <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_VREG %ecx, %rcx # eax <- vCC - .if 0 - GET_WIDE_VREG %rax, %rax # rax <- vBB - sarl %cl, %eax # ex: addl %ecx,%eax - SET_WIDE_VREG %rax, rINSTq - .else - GET_VREG %eax, %rax # eax <- vBB - sarl %cl, %eax # ex: addl %ecx,%eax - SET_VREG %eax, rINSTq - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_int: /* 0x9a */ -/* File: x86_64/op_ushr_int.S */ -/* File: x86_64/binop1.S */ -/* - * Generic 32-bit binary operation in which both operands loaded to - * registers (op0 in eax, op1 in ecx). - */ - /* binop vAA, vBB, vCC */ - movzbq 2(rPC), %rax # eax <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_VREG %ecx, %rcx # eax <- vCC - .if 0 - GET_WIDE_VREG %rax, %rax # rax <- vBB - shrl %cl, %eax # ex: addl %ecx,%eax - SET_WIDE_VREG %rax, rINSTq - .else - GET_VREG %eax, %rax # eax <- vBB - shrl %cl, %eax # ex: addl %ecx,%eax - SET_VREG %eax, rINSTq - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_add_long: /* 0x9b */ -/* File: x86_64/op_add_long.S */ -/* File: x86_64/binopWide.S */ -/* - * Generic 64-bit binary operation. - */ - /* binop vAA, vBB, vCC */ - movzbq 2(rPC), %rax # eax <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_WIDE_VREG %rax, %rax # rax <- v[BB] - addq (rFP,%rcx,4), %rax # ex: addq (rFP,%rcx,4),%rax - SET_WIDE_VREG %rax, rINSTq # v[AA] <- rax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_long: /* 0x9c */ -/* File: x86_64/op_sub_long.S */ -/* File: x86_64/binopWide.S */ -/* - * Generic 64-bit binary operation. - */ - /* binop vAA, vBB, vCC */ - movzbq 2(rPC), %rax # eax <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_WIDE_VREG %rax, %rax # rax <- v[BB] - subq (rFP,%rcx,4), %rax # ex: addq (rFP,%rcx,4),%rax - SET_WIDE_VREG %rax, rINSTq # v[AA] <- rax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_long: /* 0x9d */ -/* File: x86_64/op_mul_long.S */ -/* File: x86_64/binopWide.S */ -/* - * Generic 64-bit binary operation. - */ - /* binop vAA, vBB, vCC */ - movzbq 2(rPC), %rax # eax <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_WIDE_VREG %rax, %rax # rax <- v[BB] - imulq (rFP,%rcx,4), %rax # ex: addq (rFP,%rcx,4),%rax - SET_WIDE_VREG %rax, rINSTq # v[AA] <- rax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_div_long: /* 0x9e */ -/* File: x86_64/op_div_long.S */ -/* File: x86_64/bindiv.S */ -/* - * 32-bit binary div/rem operation. Handles special case of op1=-1. - */ - /* div/rem vAA, vBB, vCC */ - movzbq 2(rPC), %rax # rax <- BB - movzbq 3(rPC), %rcx # rcx <- CC - .if 1 - GET_WIDE_VREG %rax, %rax # eax <- vBB - GET_WIDE_VREG %rcx, %rcx # ecx <- vCC - .else - GET_VREG %eax, %rax # eax <- vBB - GET_VREG %rcx, %rcx # ecx <- vCC - .endif - testq %rcx, %rcx - jz common_errDivideByZero - cmpq $-1, %rcx - je 2f - cqo # rdx:rax <- sign-extended of rax - idivq %rcx -1: - .if 1 - SET_WIDE_VREG %rax, rINSTq # eax <- vBB - .else - SET_VREG %rax, rINSTq # eax <- vBB - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 -2: - .if 0 - xorq %rax, %rax - .else - negq %rax - .endif - jmp 1b - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_long: /* 0x9f */ -/* File: x86_64/op_rem_long.S */ -/* File: x86_64/bindiv.S */ -/* - * 32-bit binary div/rem operation. Handles special case of op1=-1. - */ - /* div/rem vAA, vBB, vCC */ - movzbq 2(rPC), %rax # rax <- BB - movzbq 3(rPC), %rcx # rcx <- CC - .if 1 - GET_WIDE_VREG %rax, %rax # eax <- vBB - GET_WIDE_VREG %rcx, %rcx # ecx <- vCC - .else - GET_VREG %eax, %rax # eax <- vBB - GET_VREG %rcx, %rcx # ecx <- vCC - .endif - testq %rcx, %rcx - jz common_errDivideByZero - cmpq $-1, %rcx - je 2f - cqo # rdx:rax <- sign-extended of rax - idivq %rcx -1: - .if 1 - SET_WIDE_VREG %rdx, rINSTq # eax <- vBB - .else - SET_VREG %rdx, rINSTq # eax <- vBB - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 -2: - .if 1 - xorq %rdx, %rdx - .else - negq %rdx - .endif - jmp 1b - - -/* ------------------------------ */ - .balign 128 -.L_op_and_long: /* 0xa0 */ -/* File: x86_64/op_and_long.S */ -/* File: x86_64/binopWide.S */ -/* - * Generic 64-bit binary operation. - */ - /* binop vAA, vBB, vCC */ - movzbq 2(rPC), %rax # eax <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_WIDE_VREG %rax, %rax # rax <- v[BB] - andq (rFP,%rcx,4), %rax # ex: addq (rFP,%rcx,4),%rax - SET_WIDE_VREG %rax, rINSTq # v[AA] <- rax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_or_long: /* 0xa1 */ -/* File: x86_64/op_or_long.S */ -/* File: x86_64/binopWide.S */ -/* - * Generic 64-bit binary operation. - */ - /* binop vAA, vBB, vCC */ - movzbq 2(rPC), %rax # eax <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_WIDE_VREG %rax, %rax # rax <- v[BB] - orq (rFP,%rcx,4), %rax # ex: addq (rFP,%rcx,4),%rax - SET_WIDE_VREG %rax, rINSTq # v[AA] <- rax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_xor_long: /* 0xa2 */ -/* File: x86_64/op_xor_long.S */ -/* File: x86_64/binopWide.S */ -/* - * Generic 64-bit binary operation. - */ - /* binop vAA, vBB, vCC */ - movzbq 2(rPC), %rax # eax <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_WIDE_VREG %rax, %rax # rax <- v[BB] - xorq (rFP,%rcx,4), %rax # ex: addq (rFP,%rcx,4),%rax - SET_WIDE_VREG %rax, rINSTq # v[AA] <- rax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_shl_long: /* 0xa3 */ -/* File: x86_64/op_shl_long.S */ -/* File: x86_64/binop1.S */ -/* - * Generic 32-bit binary operation in which both operands loaded to - * registers (op0 in eax, op1 in ecx). - */ - /* binop vAA, vBB, vCC */ - movzbq 2(rPC), %rax # eax <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_VREG %ecx, %rcx # eax <- vCC - .if 1 - GET_WIDE_VREG %rax, %rax # rax <- vBB - salq %cl, %rax # ex: addl %ecx,%eax - SET_WIDE_VREG %rax, rINSTq - .else - GET_VREG %eax, %rax # eax <- vBB - salq %cl, %rax # ex: addl %ecx,%eax - SET_VREG %eax, rINSTq - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_shr_long: /* 0xa4 */ -/* File: x86_64/op_shr_long.S */ -/* File: x86_64/binop1.S */ -/* - * Generic 32-bit binary operation in which both operands loaded to - * registers (op0 in eax, op1 in ecx). - */ - /* binop vAA, vBB, vCC */ - movzbq 2(rPC), %rax # eax <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_VREG %ecx, %rcx # eax <- vCC - .if 1 - GET_WIDE_VREG %rax, %rax # rax <- vBB - sarq %cl, %rax # ex: addl %ecx,%eax - SET_WIDE_VREG %rax, rINSTq - .else - GET_VREG %eax, %rax # eax <- vBB - sarq %cl, %rax # ex: addl %ecx,%eax - SET_VREG %eax, rINSTq - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_long: /* 0xa5 */ -/* File: x86_64/op_ushr_long.S */ -/* File: x86_64/binop1.S */ -/* - * Generic 32-bit binary operation in which both operands loaded to - * registers (op0 in eax, op1 in ecx). - */ - /* binop vAA, vBB, vCC */ - movzbq 2(rPC), %rax # eax <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_VREG %ecx, %rcx # eax <- vCC - .if 1 - GET_WIDE_VREG %rax, %rax # rax <- vBB - shrq %cl, %rax # ex: addl %ecx,%eax - SET_WIDE_VREG %rax, rINSTq - .else - GET_VREG %eax, %rax # eax <- vBB - shrq %cl, %rax # ex: addl %ecx,%eax - SET_VREG %eax, rINSTq - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_add_float: /* 0xa6 */ -/* File: x86_64/op_add_float.S */ -/* File: x86_64/sseBinop.S */ - movzbq 2(rPC), %rcx # ecx <- BB - movzbq 3(rPC), %rax # eax <- CC - movss VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src - addss VREG_ADDRESS(%rax), %xmm0 - movss %xmm0, VREG_ADDRESS(rINSTq) # vAA <- %xmm0 - pxor %xmm0, %xmm0 - movss %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_float: /* 0xa7 */ -/* File: x86_64/op_sub_float.S */ -/* File: x86_64/sseBinop.S */ - movzbq 2(rPC), %rcx # ecx <- BB - movzbq 3(rPC), %rax # eax <- CC - movss VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src - subss VREG_ADDRESS(%rax), %xmm0 - movss %xmm0, VREG_ADDRESS(rINSTq) # vAA <- %xmm0 - pxor %xmm0, %xmm0 - movss %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_float: /* 0xa8 */ -/* File: x86_64/op_mul_float.S */ -/* File: x86_64/sseBinop.S */ - movzbq 2(rPC), %rcx # ecx <- BB - movzbq 3(rPC), %rax # eax <- CC - movss VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src - mulss VREG_ADDRESS(%rax), %xmm0 - movss %xmm0, VREG_ADDRESS(rINSTq) # vAA <- %xmm0 - pxor %xmm0, %xmm0 - movss %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_div_float: /* 0xa9 */ -/* File: x86_64/op_div_float.S */ -/* File: x86_64/sseBinop.S */ - movzbq 2(rPC), %rcx # ecx <- BB - movzbq 3(rPC), %rax # eax <- CC - movss VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src - divss VREG_ADDRESS(%rax), %xmm0 - movss %xmm0, VREG_ADDRESS(rINSTq) # vAA <- %xmm0 - pxor %xmm0, %xmm0 - movss %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_float: /* 0xaa */ -/* File: x86_64/op_rem_float.S */ - /* rem_float vAA, vBB, vCC */ - movzbq 3(rPC), %rcx # ecx <- BB - movzbq 2(rPC), %rax # eax <- CC - flds VREG_ADDRESS(%rcx) # vBB to fp stack - flds VREG_ADDRESS(%rax) # vCC to fp stack -1: - fprem - fstsw %ax - sahf - jp 1b - fstp %st(1) - fstps VREG_ADDRESS(rINSTq) # %st to vAA - CLEAR_REF rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_add_double: /* 0xab */ -/* File: x86_64/op_add_double.S */ -/* File: x86_64/sseBinop.S */ - movzbq 2(rPC), %rcx # ecx <- BB - movzbq 3(rPC), %rax # eax <- CC - movsd VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src - addsd VREG_ADDRESS(%rax), %xmm0 - movsd %xmm0, VREG_ADDRESS(rINSTq) # vAA <- %xmm0 - pxor %xmm0, %xmm0 - movsd %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_double: /* 0xac */ -/* File: x86_64/op_sub_double.S */ -/* File: x86_64/sseBinop.S */ - movzbq 2(rPC), %rcx # ecx <- BB - movzbq 3(rPC), %rax # eax <- CC - movsd VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src - subsd VREG_ADDRESS(%rax), %xmm0 - movsd %xmm0, VREG_ADDRESS(rINSTq) # vAA <- %xmm0 - pxor %xmm0, %xmm0 - movsd %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_double: /* 0xad */ -/* File: x86_64/op_mul_double.S */ -/* File: x86_64/sseBinop.S */ - movzbq 2(rPC), %rcx # ecx <- BB - movzbq 3(rPC), %rax # eax <- CC - movsd VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src - mulsd VREG_ADDRESS(%rax), %xmm0 - movsd %xmm0, VREG_ADDRESS(rINSTq) # vAA <- %xmm0 - pxor %xmm0, %xmm0 - movsd %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_div_double: /* 0xae */ -/* File: x86_64/op_div_double.S */ -/* File: x86_64/sseBinop.S */ - movzbq 2(rPC), %rcx # ecx <- BB - movzbq 3(rPC), %rax # eax <- CC - movsd VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src - divsd VREG_ADDRESS(%rax), %xmm0 - movsd %xmm0, VREG_ADDRESS(rINSTq) # vAA <- %xmm0 - pxor %xmm0, %xmm0 - movsd %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_double: /* 0xaf */ -/* File: x86_64/op_rem_double.S */ - /* rem_double vAA, vBB, vCC */ - movzbq 3(rPC), %rcx # ecx <- BB - movzbq 2(rPC), %rax # eax <- CC - fldl VREG_ADDRESS(%rcx) # %st1 <- fp[vBB] - fldl VREG_ADDRESS(%rax) # %st0 <- fp[vCC] -1: - fprem - fstsw %ax - sahf - jp 1b - fstp %st(1) - fstpl VREG_ADDRESS(rINSTq) # fp[vAA] <- %st - CLEAR_WIDE_REF rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_add_int_2addr: /* 0xb0 */ -/* File: x86_64/op_add_int_2addr.S */ -/* File: x86_64/binop2addr.S */ -/* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an instruction or a function call. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - GET_VREG %eax, rINSTq # eax <- vB - addl %eax, (rFP,%rcx,4) # for ex: addl %eax,(rFP,%ecx,4) - CLEAR_REF %rcx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_int_2addr: /* 0xb1 */ -/* File: x86_64/op_sub_int_2addr.S */ -/* File: x86_64/binop2addr.S */ -/* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an instruction or a function call. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - GET_VREG %eax, rINSTq # eax <- vB - subl %eax, (rFP,%rcx,4) # for ex: addl %eax,(rFP,%ecx,4) - CLEAR_REF %rcx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int_2addr: /* 0xb2 */ -/* File: x86_64/op_mul_int_2addr.S */ - /* mul vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - GET_VREG %eax, %rcx # eax <- vA - imull (rFP,rINSTq,4), %eax - SET_VREG %eax, %rcx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_div_int_2addr: /* 0xb3 */ -/* File: x86_64/op_div_int_2addr.S */ -/* File: x86_64/bindiv2addr.S */ -/* - * 32-bit binary div/rem operation. Handles special case of op1=-1. - */ - /* div/rem/2addr vA, vB */ - movl rINST, %ecx # rcx <- BA - sarl $4, %ecx # rcx <- B - andb $0xf, rINSTbl # rINST <- A - .if 0 - GET_WIDE_VREG %rax, rINSTq # eax <- vA - GET_WIDE_VREG %ecx, %rcx # ecx <- vB - .else - GET_VREG %eax, rINSTq # eax <- vA - GET_VREG %ecx, %rcx # ecx <- vB - .endif - testl %ecx, %ecx - jz common_errDivideByZero - cmpl $-1, %ecx - je 2f - cdq # rdx:rax <- sign-extended of rax - idivl %ecx -1: - .if 0 - SET_WIDE_VREG %eax, rINSTq # vA <- result - .else - SET_VREG %eax, rINSTq # vA <- result - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 -2: - .if 0 - xorl %eax, %eax - .else - negl %eax - .endif - jmp 1b - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int_2addr: /* 0xb4 */ -/* File: x86_64/op_rem_int_2addr.S */ -/* File: x86_64/bindiv2addr.S */ -/* - * 32-bit binary div/rem operation. Handles special case of op1=-1. - */ - /* div/rem/2addr vA, vB */ - movl rINST, %ecx # rcx <- BA - sarl $4, %ecx # rcx <- B - andb $0xf, rINSTbl # rINST <- A - .if 0 - GET_WIDE_VREG %rax, rINSTq # eax <- vA - GET_WIDE_VREG %ecx, %rcx # ecx <- vB - .else - GET_VREG %eax, rINSTq # eax <- vA - GET_VREG %ecx, %rcx # ecx <- vB - .endif - testl %ecx, %ecx - jz common_errDivideByZero - cmpl $-1, %ecx - je 2f - cdq # rdx:rax <- sign-extended of rax - idivl %ecx -1: - .if 0 - SET_WIDE_VREG %edx, rINSTq # vA <- result - .else - SET_VREG %edx, rINSTq # vA <- result - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 -2: - .if 1 - xorl %edx, %edx - .else - negl %edx - .endif - jmp 1b - - -/* ------------------------------ */ - .balign 128 -.L_op_and_int_2addr: /* 0xb5 */ -/* File: x86_64/op_and_int_2addr.S */ -/* File: x86_64/binop2addr.S */ -/* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an instruction or a function call. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - GET_VREG %eax, rINSTq # eax <- vB - andl %eax, (rFP,%rcx,4) # for ex: addl %eax,(rFP,%ecx,4) - CLEAR_REF %rcx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_or_int_2addr: /* 0xb6 */ -/* File: x86_64/op_or_int_2addr.S */ -/* File: x86_64/binop2addr.S */ -/* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an instruction or a function call. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - GET_VREG %eax, rINSTq # eax <- vB - orl %eax, (rFP,%rcx,4) # for ex: addl %eax,(rFP,%ecx,4) - CLEAR_REF %rcx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int_2addr: /* 0xb7 */ -/* File: x86_64/op_xor_int_2addr.S */ -/* File: x86_64/binop2addr.S */ -/* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an instruction or a function call. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - GET_VREG %eax, rINSTq # eax <- vB - xorl %eax, (rFP,%rcx,4) # for ex: addl %eax,(rFP,%ecx,4) - CLEAR_REF %rcx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_shl_int_2addr: /* 0xb8 */ -/* File: x86_64/op_shl_int_2addr.S */ -/* File: x86_64/shop2addr.S */ -/* - * Generic 32-bit "shift/2addr" operation. - */ - /* shift/2addr vA, vB */ - movl rINST, %ecx # ecx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %rcx # ecx <- vBB - andb $0xf, rINSTbl # rINST <- A - .if 0 - GET_WIDE_VREG %rax, rINSTq # rax <- vAA - sall %cl, %eax # ex: sarl %cl, %eax - SET_WIDE_VREG %rax, rINSTq - .else - GET_VREG %eax, rINSTq # eax <- vAA - sall %cl, %eax # ex: sarl %cl, %eax - SET_VREG %eax, rINSTq - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_shr_int_2addr: /* 0xb9 */ -/* File: x86_64/op_shr_int_2addr.S */ -/* File: x86_64/shop2addr.S */ -/* - * Generic 32-bit "shift/2addr" operation. - */ - /* shift/2addr vA, vB */ - movl rINST, %ecx # ecx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %rcx # ecx <- vBB - andb $0xf, rINSTbl # rINST <- A - .if 0 - GET_WIDE_VREG %rax, rINSTq # rax <- vAA - sarl %cl, %eax # ex: sarl %cl, %eax - SET_WIDE_VREG %rax, rINSTq - .else - GET_VREG %eax, rINSTq # eax <- vAA - sarl %cl, %eax # ex: sarl %cl, %eax - SET_VREG %eax, rINSTq - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_int_2addr: /* 0xba */ -/* File: x86_64/op_ushr_int_2addr.S */ -/* File: x86_64/shop2addr.S */ -/* - * Generic 32-bit "shift/2addr" operation. - */ - /* shift/2addr vA, vB */ - movl rINST, %ecx # ecx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %rcx # ecx <- vBB - andb $0xf, rINSTbl # rINST <- A - .if 0 - GET_WIDE_VREG %rax, rINSTq # rax <- vAA - shrl %cl, %eax # ex: sarl %cl, %eax - SET_WIDE_VREG %rax, rINSTq - .else - GET_VREG %eax, rINSTq # eax <- vAA - shrl %cl, %eax # ex: sarl %cl, %eax - SET_VREG %eax, rINSTq - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_add_long_2addr: /* 0xbb */ -/* File: x86_64/op_add_long_2addr.S */ -/* File: x86_64/binopWide2addr.S */ -/* - * Generic 64-bit binary operation. - */ - /* binop/2addr vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - GET_WIDE_VREG %rax, rINSTq # rax <- vB - addq %rax, (rFP,%rcx,4) # for ex: addq %rax,(rFP,%rcx,4) - CLEAR_WIDE_REF %rcx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_long_2addr: /* 0xbc */ -/* File: x86_64/op_sub_long_2addr.S */ -/* File: x86_64/binopWide2addr.S */ -/* - * Generic 64-bit binary operation. - */ - /* binop/2addr vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - GET_WIDE_VREG %rax, rINSTq # rax <- vB - subq %rax, (rFP,%rcx,4) # for ex: addq %rax,(rFP,%rcx,4) - CLEAR_WIDE_REF %rcx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_long_2addr: /* 0xbd */ -/* File: x86_64/op_mul_long_2addr.S */ - /* mul vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - GET_WIDE_VREG %rax, %rcx # rax <- vA - imulq (rFP,rINSTq,4), %rax - SET_WIDE_VREG %rax, %rcx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_div_long_2addr: /* 0xbe */ -/* File: x86_64/op_div_long_2addr.S */ -/* File: x86_64/bindiv2addr.S */ -/* - * 32-bit binary div/rem operation. Handles special case of op1=-1. - */ - /* div/rem/2addr vA, vB */ - movl rINST, %ecx # rcx <- BA - sarl $4, %ecx # rcx <- B - andb $0xf, rINSTbl # rINST <- A - .if 1 - GET_WIDE_VREG %rax, rINSTq # eax <- vA - GET_WIDE_VREG %rcx, %rcx # ecx <- vB - .else - GET_VREG %eax, rINSTq # eax <- vA - GET_VREG %rcx, %rcx # ecx <- vB - .endif - testq %rcx, %rcx - jz common_errDivideByZero - cmpq $-1, %rcx - je 2f - cqo # rdx:rax <- sign-extended of rax - idivq %rcx -1: - .if 1 - SET_WIDE_VREG %rax, rINSTq # vA <- result - .else - SET_VREG %rax, rINSTq # vA <- result - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 -2: - .if 0 - xorq %rax, %rax - .else - negq %rax - .endif - jmp 1b - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_long_2addr: /* 0xbf */ -/* File: x86_64/op_rem_long_2addr.S */ -/* File: x86_64/bindiv2addr.S */ -/* - * 32-bit binary div/rem operation. Handles special case of op1=-1. - */ - /* div/rem/2addr vA, vB */ - movl rINST, %ecx # rcx <- BA - sarl $4, %ecx # rcx <- B - andb $0xf, rINSTbl # rINST <- A - .if 1 - GET_WIDE_VREG %rax, rINSTq # eax <- vA - GET_WIDE_VREG %rcx, %rcx # ecx <- vB - .else - GET_VREG %eax, rINSTq # eax <- vA - GET_VREG %rcx, %rcx # ecx <- vB - .endif - testq %rcx, %rcx - jz common_errDivideByZero - cmpq $-1, %rcx - je 2f - cqo # rdx:rax <- sign-extended of rax - idivq %rcx -1: - .if 1 - SET_WIDE_VREG %rdx, rINSTq # vA <- result - .else - SET_VREG %rdx, rINSTq # vA <- result - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 -2: - .if 1 - xorq %rdx, %rdx - .else - negq %rdx - .endif - jmp 1b - - -/* ------------------------------ */ - .balign 128 -.L_op_and_long_2addr: /* 0xc0 */ -/* File: x86_64/op_and_long_2addr.S */ -/* File: x86_64/binopWide2addr.S */ -/* - * Generic 64-bit binary operation. - */ - /* binop/2addr vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - GET_WIDE_VREG %rax, rINSTq # rax <- vB - andq %rax, (rFP,%rcx,4) # for ex: addq %rax,(rFP,%rcx,4) - CLEAR_WIDE_REF %rcx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_or_long_2addr: /* 0xc1 */ -/* File: x86_64/op_or_long_2addr.S */ -/* File: x86_64/binopWide2addr.S */ -/* - * Generic 64-bit binary operation. - */ - /* binop/2addr vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - GET_WIDE_VREG %rax, rINSTq # rax <- vB - orq %rax, (rFP,%rcx,4) # for ex: addq %rax,(rFP,%rcx,4) - CLEAR_WIDE_REF %rcx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_xor_long_2addr: /* 0xc2 */ -/* File: x86_64/op_xor_long_2addr.S */ -/* File: x86_64/binopWide2addr.S */ -/* - * Generic 64-bit binary operation. - */ - /* binop/2addr vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $4, rINST # rINST <- B - andb $0xf, %cl # ecx <- A - GET_WIDE_VREG %rax, rINSTq # rax <- vB - xorq %rax, (rFP,%rcx,4) # for ex: addq %rax,(rFP,%rcx,4) - CLEAR_WIDE_REF %rcx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_shl_long_2addr: /* 0xc3 */ -/* File: x86_64/op_shl_long_2addr.S */ -/* File: x86_64/shop2addr.S */ -/* - * Generic 32-bit "shift/2addr" operation. - */ - /* shift/2addr vA, vB */ - movl rINST, %ecx # ecx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %rcx # ecx <- vBB - andb $0xf, rINSTbl # rINST <- A - .if 1 - GET_WIDE_VREG %rax, rINSTq # rax <- vAA - salq %cl, %rax # ex: sarl %cl, %eax - SET_WIDE_VREG %rax, rINSTq - .else - GET_VREG %eax, rINSTq # eax <- vAA - salq %cl, %rax # ex: sarl %cl, %eax - SET_VREG %eax, rINSTq - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_shr_long_2addr: /* 0xc4 */ -/* File: x86_64/op_shr_long_2addr.S */ -/* File: x86_64/shop2addr.S */ -/* - * Generic 32-bit "shift/2addr" operation. - */ - /* shift/2addr vA, vB */ - movl rINST, %ecx # ecx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %rcx # ecx <- vBB - andb $0xf, rINSTbl # rINST <- A - .if 1 - GET_WIDE_VREG %rax, rINSTq # rax <- vAA - sarq %cl, %rax # ex: sarl %cl, %eax - SET_WIDE_VREG %rax, rINSTq - .else - GET_VREG %eax, rINSTq # eax <- vAA - sarq %cl, %rax # ex: sarl %cl, %eax - SET_VREG %eax, rINSTq - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_long_2addr: /* 0xc5 */ -/* File: x86_64/op_ushr_long_2addr.S */ -/* File: x86_64/shop2addr.S */ -/* - * Generic 32-bit "shift/2addr" operation. - */ - /* shift/2addr vA, vB */ - movl rINST, %ecx # ecx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %rcx # ecx <- vBB - andb $0xf, rINSTbl # rINST <- A - .if 1 - GET_WIDE_VREG %rax, rINSTq # rax <- vAA - shrq %cl, %rax # ex: sarl %cl, %eax - SET_WIDE_VREG %rax, rINSTq - .else - GET_VREG %eax, rINSTq # eax <- vAA - shrq %cl, %rax # ex: sarl %cl, %eax - SET_VREG %eax, rINSTq - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_add_float_2addr: /* 0xc6 */ -/* File: x86_64/op_add_float_2addr.S */ -/* File: x86_64/sseBinop2Addr.S */ - movl rINST, %ecx # ecx <- A+ - andl $0xf, %ecx # ecx <- A - movss VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src - sarl $4, rINST # rINST<- B - addss VREG_ADDRESS(rINSTq), %xmm0 - movss %xmm0, VREG_ADDRESS(%rcx) # vAA<- %xmm0 - pxor %xmm0, %xmm0 - movss %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_float_2addr: /* 0xc7 */ -/* File: x86_64/op_sub_float_2addr.S */ -/* File: x86_64/sseBinop2Addr.S */ - movl rINST, %ecx # ecx <- A+ - andl $0xf, %ecx # ecx <- A - movss VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src - sarl $4, rINST # rINST<- B - subss VREG_ADDRESS(rINSTq), %xmm0 - movss %xmm0, VREG_ADDRESS(%rcx) # vAA<- %xmm0 - pxor %xmm0, %xmm0 - movss %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_float_2addr: /* 0xc8 */ -/* File: x86_64/op_mul_float_2addr.S */ -/* File: x86_64/sseBinop2Addr.S */ - movl rINST, %ecx # ecx <- A+ - andl $0xf, %ecx # ecx <- A - movss VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src - sarl $4, rINST # rINST<- B - mulss VREG_ADDRESS(rINSTq), %xmm0 - movss %xmm0, VREG_ADDRESS(%rcx) # vAA<- %xmm0 - pxor %xmm0, %xmm0 - movss %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_div_float_2addr: /* 0xc9 */ -/* File: x86_64/op_div_float_2addr.S */ -/* File: x86_64/sseBinop2Addr.S */ - movl rINST, %ecx # ecx <- A+ - andl $0xf, %ecx # ecx <- A - movss VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src - sarl $4, rINST # rINST<- B - divss VREG_ADDRESS(rINSTq), %xmm0 - movss %xmm0, VREG_ADDRESS(%rcx) # vAA<- %xmm0 - pxor %xmm0, %xmm0 - movss %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_float_2addr: /* 0xca */ -/* File: x86_64/op_rem_float_2addr.S */ - /* rem_float/2addr vA, vB */ - movzbq rINSTbl, %rcx # ecx <- A+ - sarl $4, rINST # rINST <- B - flds VREG_ADDRESS(rINSTq) # vB to fp stack - andb $0xf, %cl # ecx <- A - flds VREG_ADDRESS(%rcx) # vA to fp stack -1: - fprem - fstsw %ax - sahf - jp 1b - fstp %st(1) - fstps VREG_ADDRESS(%rcx) # %st to vA - CLEAR_REF %rcx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_add_double_2addr: /* 0xcb */ -/* File: x86_64/op_add_double_2addr.S */ -/* File: x86_64/sseBinop2Addr.S */ - movl rINST, %ecx # ecx <- A+ - andl $0xf, %ecx # ecx <- A - movsd VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src - sarl $4, rINST # rINST<- B - addsd VREG_ADDRESS(rINSTq), %xmm0 - movsd %xmm0, VREG_ADDRESS(%rcx) # vAA<- %xmm0 - pxor %xmm0, %xmm0 - movsd %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_sub_double_2addr: /* 0xcc */ -/* File: x86_64/op_sub_double_2addr.S */ -/* File: x86_64/sseBinop2Addr.S */ - movl rINST, %ecx # ecx <- A+ - andl $0xf, %ecx # ecx <- A - movsd VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src - sarl $4, rINST # rINST<- B - subsd VREG_ADDRESS(rINSTq), %xmm0 - movsd %xmm0, VREG_ADDRESS(%rcx) # vAA<- %xmm0 - pxor %xmm0, %xmm0 - movsd %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_double_2addr: /* 0xcd */ -/* File: x86_64/op_mul_double_2addr.S */ -/* File: x86_64/sseBinop2Addr.S */ - movl rINST, %ecx # ecx <- A+ - andl $0xf, %ecx # ecx <- A - movsd VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src - sarl $4, rINST # rINST<- B - mulsd VREG_ADDRESS(rINSTq), %xmm0 - movsd %xmm0, VREG_ADDRESS(%rcx) # vAA<- %xmm0 - pxor %xmm0, %xmm0 - movsd %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_div_double_2addr: /* 0xce */ -/* File: x86_64/op_div_double_2addr.S */ -/* File: x86_64/sseBinop2Addr.S */ - movl rINST, %ecx # ecx <- A+ - andl $0xf, %ecx # ecx <- A - movsd VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src - sarl $4, rINST # rINST<- B - divsd VREG_ADDRESS(rINSTq), %xmm0 - movsd %xmm0, VREG_ADDRESS(%rcx) # vAA<- %xmm0 - pxor %xmm0, %xmm0 - movsd %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_double_2addr: /* 0xcf */ -/* File: x86_64/op_rem_double_2addr.S */ - /* rem_double/2addr vA, vB */ - movzbq rINSTbl, %rcx # ecx <- A+ - sarl $4, rINST # rINST <- B - fldl VREG_ADDRESS(rINSTq) # vB to fp stack - andb $0xf, %cl # ecx <- A - fldl VREG_ADDRESS(%rcx) # vA to fp stack -1: - fprem - fstsw %ax - sahf - jp 1b - fstp %st(1) - fstpl VREG_ADDRESS(%rcx) # %st to vA - CLEAR_WIDE_REF %rcx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -/* ------------------------------ */ - .balign 128 -.L_op_add_int_lit16: /* 0xd0 */ -/* File: x86_64/op_add_int_lit16.S */ -/* File: x86_64/binopLit16.S */ -/* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int/lit16, rsub-int, - * and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - movl rINST, %eax # rax <- 000000BA - sarl $4, %eax # eax <- B - GET_VREG %eax, %rax # eax <- vB - andb $0xf, rINSTbl # rINST <- A - movswl 2(rPC), %ecx # ecx <- ssssCCCC - addl %ecx, %eax # for example: addl %ecx, %eax - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_rsub_int: /* 0xd1 */ -/* File: x86_64/op_rsub_int.S */ -/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ -/* File: x86_64/binopLit16.S */ -/* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int/lit16, rsub-int, - * and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - movl rINST, %eax # rax <- 000000BA - sarl $4, %eax # eax <- B - GET_VREG %eax, %rax # eax <- vB - andb $0xf, rINSTbl # rINST <- A - movswl 2(rPC), %ecx # ecx <- ssssCCCC - subl %eax, %ecx # for example: addl %ecx, %eax - SET_VREG %ecx, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int_lit16: /* 0xd2 */ -/* File: x86_64/op_mul_int_lit16.S */ -/* File: x86_64/binopLit16.S */ -/* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int/lit16, rsub-int, - * and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - movl rINST, %eax # rax <- 000000BA - sarl $4, %eax # eax <- B - GET_VREG %eax, %rax # eax <- vB - andb $0xf, rINSTbl # rINST <- A - movswl 2(rPC), %ecx # ecx <- ssssCCCC - imull %ecx, %eax # for example: addl %ecx, %eax - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_div_int_lit16: /* 0xd3 */ -/* File: x86_64/op_div_int_lit16.S */ -/* File: x86_64/bindivLit16.S */ -/* - * 32-bit binary div/rem operation. Handles special case of op1=-1. - */ - /* div/rem/lit16 vA, vB, #+CCCC */ - /* Need A in rINST, ssssCCCC in ecx, vB in eax */ - movl rINST, %eax # rax <- 000000BA - sarl $4, %eax # eax <- B - GET_VREG %eax, %rax # eax <- vB - movswl 2(rPC), %ecx # ecx <- ssssCCCC - andb $0xf, rINSTbl # rINST <- A - testl %ecx, %ecx - jz common_errDivideByZero - cmpl $-1, %ecx - je 2f - cdq # rax <- sign-extended of eax - idivl %ecx -1: - SET_VREG %eax, rINSTq # vA <- result - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 -2: - .if 0 - xorl %eax, %eax - .else - negl %eax - .endif - jmp 1b - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int_lit16: /* 0xd4 */ -/* File: x86_64/op_rem_int_lit16.S */ -/* File: x86_64/bindivLit16.S */ -/* - * 32-bit binary div/rem operation. Handles special case of op1=-1. - */ - /* div/rem/lit16 vA, vB, #+CCCC */ - /* Need A in rINST, ssssCCCC in ecx, vB in eax */ - movl rINST, %eax # rax <- 000000BA - sarl $4, %eax # eax <- B - GET_VREG %eax, %rax # eax <- vB - movswl 2(rPC), %ecx # ecx <- ssssCCCC - andb $0xf, rINSTbl # rINST <- A - testl %ecx, %ecx - jz common_errDivideByZero - cmpl $-1, %ecx - je 2f - cdq # rax <- sign-extended of eax - idivl %ecx -1: - SET_VREG %edx, rINSTq # vA <- result - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 -2: - .if 1 - xorl %edx, %edx - .else - negl %edx - .endif - jmp 1b - - -/* ------------------------------ */ - .balign 128 -.L_op_and_int_lit16: /* 0xd5 */ -/* File: x86_64/op_and_int_lit16.S */ -/* File: x86_64/binopLit16.S */ -/* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int/lit16, rsub-int, - * and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - movl rINST, %eax # rax <- 000000BA - sarl $4, %eax # eax <- B - GET_VREG %eax, %rax # eax <- vB - andb $0xf, rINSTbl # rINST <- A - movswl 2(rPC), %ecx # ecx <- ssssCCCC - andl %ecx, %eax # for example: addl %ecx, %eax - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_or_int_lit16: /* 0xd6 */ -/* File: x86_64/op_or_int_lit16.S */ -/* File: x86_64/binopLit16.S */ -/* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int/lit16, rsub-int, - * and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - movl rINST, %eax # rax <- 000000BA - sarl $4, %eax # eax <- B - GET_VREG %eax, %rax # eax <- vB - andb $0xf, rINSTbl # rINST <- A - movswl 2(rPC), %ecx # ecx <- ssssCCCC - orl %ecx, %eax # for example: addl %ecx, %eax - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int_lit16: /* 0xd7 */ -/* File: x86_64/op_xor_int_lit16.S */ -/* File: x86_64/binopLit16.S */ -/* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int/lit16, rsub-int, - * and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - movl rINST, %eax # rax <- 000000BA - sarl $4, %eax # eax <- B - GET_VREG %eax, %rax # eax <- vB - andb $0xf, rINSTbl # rINST <- A - movswl 2(rPC), %ecx # ecx <- ssssCCCC - xorl %ecx, %eax # for example: addl %ecx, %eax - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_add_int_lit8: /* 0xd8 */ -/* File: x86_64/op_add_int_lit8.S */ -/* File: x86_64/binopLit8.S */ -/* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * For: add-int/lit8, rsub-int/lit8 - * and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - movzbq 2(rPC), %rax # rax <- BB - movsbl 3(rPC), %ecx # rcx <- ssssssCC - GET_VREG %eax, %rax # eax <- rBB - addl %ecx, %eax # ex: addl %ecx,%eax - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_rsub_int_lit8: /* 0xd9 */ -/* File: x86_64/op_rsub_int_lit8.S */ -/* File: x86_64/binopLit8.S */ -/* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * For: add-int/lit8, rsub-int/lit8 - * and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - movzbq 2(rPC), %rax # rax <- BB - movsbl 3(rPC), %ecx # rcx <- ssssssCC - GET_VREG %eax, %rax # eax <- rBB - subl %eax, %ecx # ex: addl %ecx,%eax - SET_VREG %ecx, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_mul_int_lit8: /* 0xda */ -/* File: x86_64/op_mul_int_lit8.S */ -/* File: x86_64/binopLit8.S */ -/* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * For: add-int/lit8, rsub-int/lit8 - * and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - movzbq 2(rPC), %rax # rax <- BB - movsbl 3(rPC), %ecx # rcx <- ssssssCC - GET_VREG %eax, %rax # eax <- rBB - imull %ecx, %eax # ex: addl %ecx,%eax - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_div_int_lit8: /* 0xdb */ -/* File: x86_64/op_div_int_lit8.S */ -/* File: x86_64/bindivLit8.S */ -/* - * 32-bit div/rem "lit8" binary operation. Handles special case of - * op0=minint & op1=-1 - */ - /* div/rem/lit8 vAA, vBB, #+CC */ - movzbq 2(rPC), %rax # eax <- BB - movsbl 3(rPC), %ecx # ecx <- ssssssCC - GET_VREG %eax, %rax # eax <- rBB - testl %ecx, %ecx - je common_errDivideByZero - cmpl $-1, %ecx - je 2f - cdq # rax <- sign-extended of eax - idivl %ecx -1: - SET_VREG %eax, rINSTq # vA <- result - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 -2: - .if 0 - xorl %eax, %eax - .else - negl %eax - .endif - jmp 1b - - -/* ------------------------------ */ - .balign 128 -.L_op_rem_int_lit8: /* 0xdc */ -/* File: x86_64/op_rem_int_lit8.S */ -/* File: x86_64/bindivLit8.S */ -/* - * 32-bit div/rem "lit8" binary operation. Handles special case of - * op0=minint & op1=-1 - */ - /* div/rem/lit8 vAA, vBB, #+CC */ - movzbq 2(rPC), %rax # eax <- BB - movsbl 3(rPC), %ecx # ecx <- ssssssCC - GET_VREG %eax, %rax # eax <- rBB - testl %ecx, %ecx - je common_errDivideByZero - cmpl $-1, %ecx - je 2f - cdq # rax <- sign-extended of eax - idivl %ecx -1: - SET_VREG %edx, rINSTq # vA <- result - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 -2: - .if 1 - xorl %edx, %edx - .else - negl %edx - .endif - jmp 1b - - -/* ------------------------------ */ - .balign 128 -.L_op_and_int_lit8: /* 0xdd */ -/* File: x86_64/op_and_int_lit8.S */ -/* File: x86_64/binopLit8.S */ -/* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * For: add-int/lit8, rsub-int/lit8 - * and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - movzbq 2(rPC), %rax # rax <- BB - movsbl 3(rPC), %ecx # rcx <- ssssssCC - GET_VREG %eax, %rax # eax <- rBB - andl %ecx, %eax # ex: addl %ecx,%eax - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_or_int_lit8: /* 0xde */ -/* File: x86_64/op_or_int_lit8.S */ -/* File: x86_64/binopLit8.S */ -/* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * For: add-int/lit8, rsub-int/lit8 - * and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - movzbq 2(rPC), %rax # rax <- BB - movsbl 3(rPC), %ecx # rcx <- ssssssCC - GET_VREG %eax, %rax # eax <- rBB - orl %ecx, %eax # ex: addl %ecx,%eax - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_xor_int_lit8: /* 0xdf */ -/* File: x86_64/op_xor_int_lit8.S */ -/* File: x86_64/binopLit8.S */ -/* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * For: add-int/lit8, rsub-int/lit8 - * and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - movzbq 2(rPC), %rax # rax <- BB - movsbl 3(rPC), %ecx # rcx <- ssssssCC - GET_VREG %eax, %rax # eax <- rBB - xorl %ecx, %eax # ex: addl %ecx,%eax - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_shl_int_lit8: /* 0xe0 */ -/* File: x86_64/op_shl_int_lit8.S */ -/* File: x86_64/binopLit8.S */ -/* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * For: add-int/lit8, rsub-int/lit8 - * and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - movzbq 2(rPC), %rax # rax <- BB - movsbl 3(rPC), %ecx # rcx <- ssssssCC - GET_VREG %eax, %rax # eax <- rBB - sall %cl, %eax # ex: addl %ecx,%eax - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_shr_int_lit8: /* 0xe1 */ -/* File: x86_64/op_shr_int_lit8.S */ -/* File: x86_64/binopLit8.S */ -/* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * For: add-int/lit8, rsub-int/lit8 - * and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - movzbq 2(rPC), %rax # rax <- BB - movsbl 3(rPC), %ecx # rcx <- ssssssCC - GET_VREG %eax, %rax # eax <- rBB - sarl %cl, %eax # ex: addl %ecx,%eax - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_ushr_int_lit8: /* 0xe2 */ -/* File: x86_64/op_ushr_int_lit8.S */ -/* File: x86_64/binopLit8.S */ -/* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * For: add-int/lit8, rsub-int/lit8 - * and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - movzbq 2(rPC), %rax # rax <- BB - movsbl 3(rPC), %ecx # rcx <- ssssssCC - GET_VREG %eax, %rax # eax <- rBB - shrl %cl, %eax # ex: addl %ecx,%eax - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_quick: /* 0xe3 */ -/* File: x86_64/op_iget_quick.S */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick, iget-wide-quick */ - /* op vA, vB, offset@CCCC */ - movl rINST, %ecx # rcx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %rcx # vB (object we're operating on) - movzwq 2(rPC), %rax # eax <- field byte offset - testl %ecx, %ecx # is object null? - je common_errNullObject - andb $0xf,rINSTbl # rINST <- A - .if 0 - movq (%rcx,%rax,1), %rax - SET_WIDE_VREG %rax, rINSTq # fp[A] <- value - .else - movl (%rcx,%rax,1), %eax - SET_VREG %eax, rINSTq # fp[A] <- value - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iget_wide_quick: /* 0xe4 */ -/* File: x86_64/op_iget_wide_quick.S */ -/* File: x86_64/op_iget_quick.S */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick, iget-wide-quick */ - /* op vA, vB, offset@CCCC */ - movl rINST, %ecx # rcx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %rcx # vB (object we're operating on) - movzwq 2(rPC), %rax # eax <- field byte offset - testl %ecx, %ecx # is object null? - je common_errNullObject - andb $0xf,rINSTbl # rINST <- A - .if 1 - movq (%rcx,%rax,1), %rax - SET_WIDE_VREG %rax, rINSTq # fp[A] <- value - .else - movswl (%rcx,%rax,1), %eax - SET_VREG %eax, rINSTq # fp[A] <- value - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_object_quick: /* 0xe5 */ -/* File: x86_64/op_iget_object_quick.S */ - /* For: iget-object-quick */ - /* op vA, vB, offset@CCCC */ - .extern artIGetObjectFromMterp - movzbq rINSTbl, %rcx # rcx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG OUT_32_ARG0, %rcx # vB (object we're operating on) - movzwl 2(rPC), OUT_32_ARG1 # eax <- field byte offset - EXPORT_PC - callq SYMBOL(artIGetObjectFromMterp) # (obj, offset) - movq rSELF, %rcx - cmpq $0, THREAD_EXCEPTION_OFFSET(%rcx) - jnz MterpException # bail out - andb $0xf, rINSTbl # rINST <- A - SET_VREG_OBJECT %eax, rINSTq # fp[A] <- value - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iput_quick: /* 0xe6 */ -/* File: x86_64/op_iput_quick.S */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - movzbq rINSTbl, %rcx # rcx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %rcx # vB (object we're operating on) - testl %ecx, %ecx # is object null? - je common_errNullObject - andb $0xf, rINSTbl # rINST <- A - GET_VREG rINST, rINSTq # rINST <- v[A] - movzwq 2(rPC), %rax # rax <- field byte offset - movl rINST, (%rcx,%rax,1) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iput_wide_quick: /* 0xe7 */ -/* File: x86_64/op_iput_wide_quick.S */ - /* iput-wide-quick vA, vB, offset@CCCC */ - movzbq rINSTbl, %rcx # rcx<- BA - sarl $4, %ecx # ecx<- B - GET_VREG %ecx, %rcx # vB (object we're operating on) - testl %ecx, %ecx # is object null? - je common_errNullObject - movzwq 2(rPC), %rax # rax<- field byte offset - leaq (%rcx,%rax,1), %rcx # ecx<- Address of 64-bit target - andb $0xf, rINSTbl # rINST<- A - GET_WIDE_VREG %rax, rINSTq # rax<- fp[A]/fp[A+1] - movq %rax, (%rcx) # obj.field<- r0/r1 - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_iput_object_quick: /* 0xe8 */ -/* File: x86_64/op_iput_object_quick.S */ - EXPORT_PC - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG0 - movq rPC, OUT_ARG1 - REFRESH_INST 232 - movl rINST, OUT_32_ARG2 - call SYMBOL(MterpIputObjectQuick) - testb %al, %al - jz MterpException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual_quick: /* 0xe9 */ -/* File: x86_64/op_invoke_virtual_quick.S */ -/* File: x86_64/invoke.S */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtualQuick - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - REFRESH_INST 233 - movl rINST, OUT_32_ARG3 - call SYMBOL(MterpInvokeVirtualQuick) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - FETCH_INST - GOTO_NEXT - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_virtual_range_quick: /* 0xea */ -/* File: x86_64/op_invoke_virtual_range_quick.S */ -/* File: x86_64/invoke.S */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeVirtualQuickRange - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - REFRESH_INST 234 - movl rINST, OUT_32_ARG3 - call SYMBOL(MterpInvokeVirtualQuickRange) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - FETCH_INST - GOTO_NEXT - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_boolean_quick: /* 0xeb */ -/* File: x86_64/op_iput_boolean_quick.S */ -/* File: x86_64/op_iput_quick.S */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - movzbq rINSTbl, %rcx # rcx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %rcx # vB (object we're operating on) - testl %ecx, %ecx # is object null? - je common_errNullObject - andb $0xf, rINSTbl # rINST <- A - GET_VREG rINST, rINSTq # rINST <- v[A] - movzwq 2(rPC), %rax # rax <- field byte offset - movb rINSTbl, (%rcx,%rax,1) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_byte_quick: /* 0xec */ -/* File: x86_64/op_iput_byte_quick.S */ -/* File: x86_64/op_iput_quick.S */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - movzbq rINSTbl, %rcx # rcx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %rcx # vB (object we're operating on) - testl %ecx, %ecx # is object null? - je common_errNullObject - andb $0xf, rINSTbl # rINST <- A - GET_VREG rINST, rINSTq # rINST <- v[A] - movzwq 2(rPC), %rax # rax <- field byte offset - movb rINSTbl, (%rcx,%rax,1) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_char_quick: /* 0xed */ -/* File: x86_64/op_iput_char_quick.S */ -/* File: x86_64/op_iput_quick.S */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - movzbq rINSTbl, %rcx # rcx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %rcx # vB (object we're operating on) - testl %ecx, %ecx # is object null? - je common_errNullObject - andb $0xf, rINSTbl # rINST <- A - GET_VREG rINST, rINSTq # rINST <- v[A] - movzwq 2(rPC), %rax # rax <- field byte offset - movw rINSTw, (%rcx,%rax,1) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_iput_short_quick: /* 0xee */ -/* File: x86_64/op_iput_short_quick.S */ -/* File: x86_64/op_iput_quick.S */ - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - movzbq rINSTbl, %rcx # rcx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %rcx # vB (object we're operating on) - testl %ecx, %ecx # is object null? - je common_errNullObject - andb $0xf, rINSTbl # rINST <- A - GET_VREG rINST, rINSTq # rINST <- v[A] - movzwq 2(rPC), %rax # rax <- field byte offset - movw rINSTw, (%rcx,%rax,1) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_boolean_quick: /* 0xef */ -/* File: x86_64/op_iget_boolean_quick.S */ -/* File: x86_64/op_iget_quick.S */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick, iget-wide-quick */ - /* op vA, vB, offset@CCCC */ - movl rINST, %ecx # rcx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %rcx # vB (object we're operating on) - movzwq 2(rPC), %rax # eax <- field byte offset - testl %ecx, %ecx # is object null? - je common_errNullObject - andb $0xf,rINSTbl # rINST <- A - .if 0 - movq (%rcx,%rax,1), %rax - SET_WIDE_VREG %rax, rINSTq # fp[A] <- value - .else - movsbl (%rcx,%rax,1), %eax - SET_VREG %eax, rINSTq # fp[A] <- value - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_byte_quick: /* 0xf0 */ -/* File: x86_64/op_iget_byte_quick.S */ -/* File: x86_64/op_iget_quick.S */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick, iget-wide-quick */ - /* op vA, vB, offset@CCCC */ - movl rINST, %ecx # rcx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %rcx # vB (object we're operating on) - movzwq 2(rPC), %rax # eax <- field byte offset - testl %ecx, %ecx # is object null? - je common_errNullObject - andb $0xf,rINSTbl # rINST <- A - .if 0 - movq (%rcx,%rax,1), %rax - SET_WIDE_VREG %rax, rINSTq # fp[A] <- value - .else - movsbl (%rcx,%rax,1), %eax - SET_VREG %eax, rINSTq # fp[A] <- value - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_char_quick: /* 0xf1 */ -/* File: x86_64/op_iget_char_quick.S */ -/* File: x86_64/op_iget_quick.S */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick, iget-wide-quick */ - /* op vA, vB, offset@CCCC */ - movl rINST, %ecx # rcx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %rcx # vB (object we're operating on) - movzwq 2(rPC), %rax # eax <- field byte offset - testl %ecx, %ecx # is object null? - je common_errNullObject - andb $0xf,rINSTbl # rINST <- A - .if 0 - movq (%rcx,%rax,1), %rax - SET_WIDE_VREG %rax, rINSTq # fp[A] <- value - .else - movzwl (%rcx,%rax,1), %eax - SET_VREG %eax, rINSTq # fp[A] <- value - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_iget_short_quick: /* 0xf2 */ -/* File: x86_64/op_iget_short_quick.S */ -/* File: x86_64/op_iget_quick.S */ - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick, iget-wide-quick */ - /* op vA, vB, offset@CCCC */ - movl rINST, %ecx # rcx <- BA - sarl $4, %ecx # ecx <- B - GET_VREG %ecx, %rcx # vB (object we're operating on) - movzwq 2(rPC), %rax # eax <- field byte offset - testl %ecx, %ecx # is object null? - je common_errNullObject - andb $0xf,rINSTbl # rINST <- A - .if 0 - movq (%rcx,%rax,1), %rax - SET_WIDE_VREG %rax, rINSTq # fp[A] <- value - .else - movswl (%rcx,%rax,1), %eax - SET_VREG %eax, rINSTq # fp[A] <- value - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f3: /* 0xf3 */ -/* File: x86_64/op_unused_f3.S */ -/* File: x86_64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f4: /* 0xf4 */ -/* File: x86_64/op_unused_f4.S */ -/* File: x86_64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f5: /* 0xf5 */ -/* File: x86_64/op_unused_f5.S */ -/* File: x86_64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f6: /* 0xf6 */ -/* File: x86_64/op_unused_f6.S */ -/* File: x86_64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f7: /* 0xf7 */ -/* File: x86_64/op_unused_f7.S */ -/* File: x86_64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f8: /* 0xf8 */ -/* File: x86_64/op_unused_f8.S */ -/* File: x86_64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_unused_f9: /* 0xf9 */ -/* File: x86_64/op_unused_f9.S */ -/* File: x86_64/unused.S */ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_polymorphic: /* 0xfa */ -/* File: x86_64/op_invoke_polymorphic.S */ -/* File: x86_64/invoke_polymorphic.S */ - /* - * invoke-polymorphic handler wrapper. - */ - /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ - .extern MterpInvokePolymorphic - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - REFRESH_INST 250 - movl rINST, OUT_32_ARG3 - call SYMBOL(MterpInvokePolymorphic) - testb %al, %al - jz MterpException - ADVANCE_PC 4 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - FETCH_INST - GOTO_NEXT - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_polymorphic_range: /* 0xfb */ -/* File: x86_64/op_invoke_polymorphic_range.S */ -/* File: x86_64/invoke_polymorphic.S */ - /* - * invoke-polymorphic handler wrapper. - */ - /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ - .extern MterpInvokePolymorphicRange - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - REFRESH_INST 251 - movl rINST, OUT_32_ARG3 - call SYMBOL(MterpInvokePolymorphicRange) - testb %al, %al - jz MterpException - ADVANCE_PC 4 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - FETCH_INST - GOTO_NEXT - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_custom: /* 0xfc */ -/* File: x86_64/op_invoke_custom.S */ -/* File: x86_64/invoke.S */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeCustom - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - REFRESH_INST 252 - movl rINST, OUT_32_ARG3 - call SYMBOL(MterpInvokeCustom) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - FETCH_INST - GOTO_NEXT - - -/* ------------------------------ */ - .balign 128 -.L_op_invoke_custom_range: /* 0xfd */ -/* File: x86_64/op_invoke_custom_range.S */ -/* File: x86_64/invoke.S */ -/* - * Generic invoke handler wrapper. - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ - .extern MterpInvokeCustomRange - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - REFRESH_INST 253 - movl rINST, OUT_32_ARG3 - call SYMBOL(MterpInvokeCustomRange) - testb %al, %al - jz MterpException - ADVANCE_PC 3 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - FETCH_INST - GOTO_NEXT - - -/* ------------------------------ */ - .balign 128 -.L_op_const_method_handle: /* 0xfe */ -/* File: x86_64/op_const_method_handle.S */ -/* File: x86_64/const.S */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstMethodHandle - EXPORT_PC - movzwq 2(rPC), OUT_ARG0 # eax <- OUT_ARG0 - movq rINSTq, OUT_ARG1 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 - movq rSELF, OUT_ARG3 - call SYMBOL(MterpConstMethodHandle) # (index, tgt_reg, shadow_frame, self) - testb %al, %al - jnz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - -/* ------------------------------ */ - .balign 128 -.L_op_const_method_type: /* 0xff */ -/* File: x86_64/op_const_method_type.S */ -/* File: x86_64/const.S */ - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern MterpConstMethodType - EXPORT_PC - movzwq 2(rPC), OUT_ARG0 # eax <- OUT_ARG0 - movq rINSTq, OUT_ARG1 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 - movq rSELF, OUT_ARG3 - call SYMBOL(MterpConstMethodType) # (index, tgt_reg, shadow_frame, self) - testb %al, %al - jnz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - - - .balign 128 -/* File: x86_64/instruction_end.S */ - - OBJECT_TYPE(artMterpAsmInstructionEnd) - ASM_HIDDEN SYMBOL(artMterpAsmInstructionEnd) - .global SYMBOL(artMterpAsmInstructionEnd) -SYMBOL(artMterpAsmInstructionEnd): - - -/* - * =========================================================================== - * Sister implementations - * =========================================================================== - */ -/* File: x86_64/instruction_start_sister.S */ - - OBJECT_TYPE(artMterpAsmSisterStart) - ASM_HIDDEN SYMBOL(artMterpAsmSisterStart) - .global SYMBOL(artMterpAsmSisterStart) - .text - .balign 4 -SYMBOL(artMterpAsmSisterStart): - -/* File: x86_64/instruction_end_sister.S */ - - OBJECT_TYPE(artMterpAsmSisterEnd) - ASM_HIDDEN SYMBOL(artMterpAsmSisterEnd) - .global SYMBOL(artMterpAsmSisterEnd) -SYMBOL(artMterpAsmSisterEnd): - -/* File: x86_64/instruction_start_alt.S */ - - OBJECT_TYPE(artMterpAsmAltInstructionStart) - ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionStart) - .global SYMBOL(artMterpAsmAltInstructionStart) - .text -SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_nop: /* 0x00 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(0*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move: /* 0x01 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(1*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_from16: /* 0x02 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(2*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_16: /* 0x03 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(3*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_wide: /* 0x04 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(4*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_wide_from16: /* 0x05 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(5*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_wide_16: /* 0x06 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(6*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_object: /* 0x07 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(7*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_object_from16: /* 0x08 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(8*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_object_16: /* 0x09 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(9*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_result: /* 0x0a */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(10*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_result_wide: /* 0x0b */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(11*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_result_object: /* 0x0c */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(12*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_move_exception: /* 0x0d */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(13*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_void: /* 0x0e */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(14*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return: /* 0x0f */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(15*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_wide: /* 0x10 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(16*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_object: /* 0x11 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(17*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_4: /* 0x12 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(18*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_16: /* 0x13 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(19*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const: /* 0x14 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(20*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_high16: /* 0x15 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(21*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide_16: /* 0x16 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(22*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide_32: /* 0x17 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(23*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide: /* 0x18 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(24*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_wide_high16: /* 0x19 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(25*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_string: /* 0x1a */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(26*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_string_jumbo: /* 0x1b */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(27*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_class: /* 0x1c */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(28*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_monitor_enter: /* 0x1d */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(29*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_monitor_exit: /* 0x1e */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(30*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_check_cast: /* 0x1f */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(31*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_instance_of: /* 0x20 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(32*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_array_length: /* 0x21 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(33*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_new_instance: /* 0x22 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(34*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_new_array: /* 0x23 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(35*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_filled_new_array: /* 0x24 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(36*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_filled_new_array_range: /* 0x25 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(37*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_fill_array_data: /* 0x26 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(38*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_throw: /* 0x27 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(39*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_goto: /* 0x28 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(40*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_goto_16: /* 0x29 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(41*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_goto_32: /* 0x2a */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(42*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_packed_switch: /* 0x2b */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(43*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sparse_switch: /* 0x2c */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(44*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpl_float: /* 0x2d */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(45*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpg_float: /* 0x2e */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(46*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpl_double: /* 0x2f */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(47*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmpg_double: /* 0x30 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(48*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_cmp_long: /* 0x31 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(49*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_eq: /* 0x32 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(50*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_ne: /* 0x33 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(51*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_lt: /* 0x34 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(52*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_ge: /* 0x35 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(53*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_gt: /* 0x36 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(54*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_le: /* 0x37 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(55*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_eqz: /* 0x38 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(56*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_nez: /* 0x39 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(57*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_ltz: /* 0x3a */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(58*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_gez: /* 0x3b */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(59*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_gtz: /* 0x3c */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(60*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_if_lez: /* 0x3d */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(61*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_3e: /* 0x3e */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(62*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_3f: /* 0x3f */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(63*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_40: /* 0x40 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(64*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_41: /* 0x41 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(65*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_42: /* 0x42 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(66*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_43: /* 0x43 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(67*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget: /* 0x44 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(68*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_wide: /* 0x45 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(69*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_object: /* 0x46 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(70*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_boolean: /* 0x47 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(71*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_byte: /* 0x48 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(72*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_char: /* 0x49 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(73*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aget_short: /* 0x4a */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(74*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput: /* 0x4b */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(75*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_wide: /* 0x4c */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(76*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_object: /* 0x4d */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(77*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_boolean: /* 0x4e */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(78*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_byte: /* 0x4f */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(79*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_char: /* 0x50 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(80*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_aput_short: /* 0x51 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(81*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget: /* 0x52 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(82*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_wide: /* 0x53 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(83*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_object: /* 0x54 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(84*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_boolean: /* 0x55 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(85*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_byte: /* 0x56 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(86*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_char: /* 0x57 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(87*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_short: /* 0x58 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(88*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput: /* 0x59 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(89*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_wide: /* 0x5a */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(90*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_object: /* 0x5b */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(91*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_boolean: /* 0x5c */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(92*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_byte: /* 0x5d */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(93*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_char: /* 0x5e */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(94*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_short: /* 0x5f */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(95*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget: /* 0x60 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(96*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_wide: /* 0x61 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(97*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_object: /* 0x62 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(98*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_boolean: /* 0x63 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(99*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_byte: /* 0x64 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(100*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_char: /* 0x65 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(101*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sget_short: /* 0x66 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(102*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput: /* 0x67 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(103*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_wide: /* 0x68 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(104*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_object: /* 0x69 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(105*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_boolean: /* 0x6a */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(106*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_byte: /* 0x6b */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(107*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_char: /* 0x6c */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(108*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sput_short: /* 0x6d */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(109*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual: /* 0x6e */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(110*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_super: /* 0x6f */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(111*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_direct: /* 0x70 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(112*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_static: /* 0x71 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(113*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_interface: /* 0x72 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(114*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_return_void_no_barrier: /* 0x73 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(115*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual_range: /* 0x74 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(116*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_super_range: /* 0x75 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(117*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_direct_range: /* 0x76 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(118*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_static_range: /* 0x77 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(119*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_interface_range: /* 0x78 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(120*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_79: /* 0x79 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(121*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_7a: /* 0x7a */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(122*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_int: /* 0x7b */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(123*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_not_int: /* 0x7c */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(124*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_long: /* 0x7d */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(125*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_not_long: /* 0x7e */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(126*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_float: /* 0x7f */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(127*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_neg_double: /* 0x80 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(128*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_long: /* 0x81 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(129*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_float: /* 0x82 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(130*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_double: /* 0x83 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(131*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_long_to_int: /* 0x84 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(132*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_long_to_float: /* 0x85 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(133*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_long_to_double: /* 0x86 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(134*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_float_to_int: /* 0x87 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(135*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_float_to_long: /* 0x88 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(136*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_float_to_double: /* 0x89 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(137*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_double_to_int: /* 0x8a */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(138*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_double_to_long: /* 0x8b */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(139*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_double_to_float: /* 0x8c */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(140*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_byte: /* 0x8d */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(141*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_char: /* 0x8e */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(142*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_int_to_short: /* 0x8f */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(143*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int: /* 0x90 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(144*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_int: /* 0x91 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(145*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int: /* 0x92 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(146*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int: /* 0x93 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(147*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int: /* 0x94 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(148*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int: /* 0x95 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(149*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int: /* 0x96 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(150*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int: /* 0x97 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(151*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_int: /* 0x98 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(152*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_int: /* 0x99 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(153*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_int: /* 0x9a */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(154*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_long: /* 0x9b */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(155*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_long: /* 0x9c */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(156*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_long: /* 0x9d */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(157*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_long: /* 0x9e */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(158*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_long: /* 0x9f */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(159*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_long: /* 0xa0 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(160*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_long: /* 0xa1 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(161*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_long: /* 0xa2 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(162*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_long: /* 0xa3 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(163*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_long: /* 0xa4 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(164*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_long: /* 0xa5 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(165*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_float: /* 0xa6 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(166*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_float: /* 0xa7 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(167*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_float: /* 0xa8 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(168*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_float: /* 0xa9 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(169*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_float: /* 0xaa */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(170*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_double: /* 0xab */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(171*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_double: /* 0xac */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(172*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_double: /* 0xad */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(173*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_double: /* 0xae */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(174*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_double: /* 0xaf */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(175*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int_2addr: /* 0xb0 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(176*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_int_2addr: /* 0xb1 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(177*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int_2addr: /* 0xb2 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(178*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int_2addr: /* 0xb3 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(179*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int_2addr: /* 0xb4 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(180*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int_2addr: /* 0xb5 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(181*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int_2addr: /* 0xb6 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(182*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int_2addr: /* 0xb7 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(183*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_int_2addr: /* 0xb8 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(184*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_int_2addr: /* 0xb9 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(185*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_int_2addr: /* 0xba */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(186*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_long_2addr: /* 0xbb */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(187*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_long_2addr: /* 0xbc */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(188*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_long_2addr: /* 0xbd */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(189*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_long_2addr: /* 0xbe */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(190*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_long_2addr: /* 0xbf */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(191*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_long_2addr: /* 0xc0 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(192*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_long_2addr: /* 0xc1 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(193*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_long_2addr: /* 0xc2 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(194*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_long_2addr: /* 0xc3 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(195*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_long_2addr: /* 0xc4 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(196*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_long_2addr: /* 0xc5 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(197*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_float_2addr: /* 0xc6 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(198*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_float_2addr: /* 0xc7 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(199*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_float_2addr: /* 0xc8 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(200*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_float_2addr: /* 0xc9 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(201*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_float_2addr: /* 0xca */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(202*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_double_2addr: /* 0xcb */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(203*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_sub_double_2addr: /* 0xcc */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(204*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_double_2addr: /* 0xcd */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(205*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_double_2addr: /* 0xce */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(206*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_double_2addr: /* 0xcf */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(207*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int_lit16: /* 0xd0 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(208*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rsub_int: /* 0xd1 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(209*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int_lit16: /* 0xd2 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(210*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int_lit16: /* 0xd3 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(211*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int_lit16: /* 0xd4 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(212*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int_lit16: /* 0xd5 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(213*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int_lit16: /* 0xd6 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(214*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int_lit16: /* 0xd7 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(215*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_add_int_lit8: /* 0xd8 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(216*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rsub_int_lit8: /* 0xd9 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(217*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_mul_int_lit8: /* 0xda */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(218*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_div_int_lit8: /* 0xdb */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(219*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_rem_int_lit8: /* 0xdc */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(220*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_and_int_lit8: /* 0xdd */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(221*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_or_int_lit8: /* 0xde */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(222*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_xor_int_lit8: /* 0xdf */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(223*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shl_int_lit8: /* 0xe0 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(224*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_shr_int_lit8: /* 0xe1 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(225*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_ushr_int_lit8: /* 0xe2 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(226*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_quick: /* 0xe3 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(227*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_wide_quick: /* 0xe4 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(228*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_object_quick: /* 0xe5 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(229*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_quick: /* 0xe6 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(230*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_wide_quick: /* 0xe7 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(231*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_object_quick: /* 0xe8 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(232*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual_quick: /* 0xe9 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(233*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_virtual_range_quick: /* 0xea */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(234*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_boolean_quick: /* 0xeb */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(235*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_byte_quick: /* 0xec */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(236*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_char_quick: /* 0xed */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(237*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iput_short_quick: /* 0xee */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(238*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_boolean_quick: /* 0xef */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(239*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_byte_quick: /* 0xf0 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(240*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_char_quick: /* 0xf1 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(241*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_iget_short_quick: /* 0xf2 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(242*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f3: /* 0xf3 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(243*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f4: /* 0xf4 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(244*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f5: /* 0xf5 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(245*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f6: /* 0xf6 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(246*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f7: /* 0xf7 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(247*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f8: /* 0xf8 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(248*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_unused_f9: /* 0xf9 */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(249*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_polymorphic: /* 0xfa */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(250*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_polymorphic_range: /* 0xfb */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(251*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_custom: /* 0xfc */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(252*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_invoke_custom_range: /* 0xfd */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(253*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_method_handle: /* 0xfe */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(254*128) - -/* ------------------------------ */ - .balign 128 -.L_ALT_op_const_method_type: /* 0xff */ -/* File: x86_64/alt_stub.S */ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(255*128) - - .balign 128 -/* File: x86_64/instruction_end_alt.S */ - - OBJECT_TYPE(artMterpAsmAltInstructionEnd) - ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionEnd) - .global SYMBOL(artMterpAsmAltInstructionEnd) -SYMBOL(artMterpAsmAltInstructionEnd): - -/* File: x86_64/footer.S */ -/* - * =========================================================================== - * Common subroutines and data - * =========================================================================== - */ - - .text - .align 2 - -/* - * We've detected a condition that will result in an exception, but the exception - * has not yet been thrown. Just bail out to the reference interpreter to deal with it. - * TUNING: for consistency, we may want to just go ahead and handle these here. - */ -common_errDivideByZero: - EXPORT_PC -#if MTERP_LOGGING - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - call SYMBOL(MterpLogDivideByZeroException) -#endif - jmp MterpCommonFallback - -common_errArrayIndex: - EXPORT_PC -#if MTERP_LOGGING - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - call SYMBOL(MterpLogArrayIndexException) -#endif - jmp MterpCommonFallback - -common_errNegativeArraySize: - EXPORT_PC -#if MTERP_LOGGING - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - call SYMBOL(MterpLogNegativeArraySizeException) -#endif - jmp MterpCommonFallback - -common_errNoSuchMethod: - EXPORT_PC -#if MTERP_LOGGING - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - call SYMBOL(MterpLogNoSuchMethodException) -#endif - jmp MterpCommonFallback - -common_errNullObject: - EXPORT_PC -#if MTERP_LOGGING - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - call SYMBOL(MterpLogNullObjectException) -#endif - jmp MterpCommonFallback - -common_exceptionThrown: - EXPORT_PC -#if MTERP_LOGGING - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - call SYMBOL(MterpLogExceptionThrownException) -#endif - jmp MterpCommonFallback - -MterpSuspendFallback: - EXPORT_PC -#if MTERP_LOGGING - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movl THREAD_FLAGS_OFFSET(OUT_ARG0), OUT_32_ARG2 - call SYMBOL(MterpLogSuspendFallback) -#endif - jmp MterpCommonFallback - -/* - * If we're here, something is out of the ordinary. If there is a pending - * exception, handle it. Otherwise, roll back and retry with the reference - * interpreter. - */ -MterpPossibleException: - movq rSELF, %rcx - cmpq $0, THREAD_EXCEPTION_OFFSET(%rcx) - jz MterpFallback - /* intentional fallthrough - handle pending exception. */ - -/* - * On return from a runtime helper routine, we've found a pending exception. - * Can we handle it here - or need to bail out to caller? - * - */ -MterpException: - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - call SYMBOL(MterpHandleException) - testb %al, %al - jz MterpExceptionReturn - movq OFF_FP_DEX_INSTRUCTIONS(rFP), %rax - mov OFF_FP_DEX_PC(rFP), %ecx - leaq (%rax, %rcx, 2), rPC - movq rPC, OFF_FP_DEX_PC_PTR(rFP) - /* Do we need to switch interpreters? */ - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - /* resume execution at catch block */ - REFRESH_IBASE - FETCH_INST - GOTO_NEXT - /* NOTE: no fallthrough */ - -/* - * Common handling for branches with support for Jit profiling. - * On entry: - * rINST <= signed offset - * rPROFILE <= signed hotness countdown (expanded to 32 bits) - * condition bits <= set to establish sign of offset (use "NoFlags" entry if not) - * - * We have quite a few different cases for branch profiling, OSR detection and - * suspend check support here. - * - * Taken backward branches: - * If profiling active, do hotness countdown and report if we hit zero. - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * Is there a pending suspend request? If so, suspend. - * - * Taken forward branches and not-taken backward branches: - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * - * Our most common case is expected to be a taken backward branch with active jit profiling, - * but no full OSR check and no pending suspend request. - * Next most common case is not-taken branch with no full OSR check. - * - */ -MterpCommonTakenBranch: - jg .L_forward_branch # don't add forward branches to hotness -/* - * We need to subtract 1 from positive values and we should not see 0 here, - * so we may use the result of the comparison with -1. - */ -#if JIT_CHECK_OSR != -1 -# error "JIT_CHECK_OSR must be -1." -#endif - cmpl $JIT_CHECK_OSR, rPROFILE - je .L_osr_check - decl rPROFILE - je .L_add_batch # counted down to zero - report -.L_resume_backward_branch: - movq rSELF, %rax - testl $(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(%rax) - REFRESH_IBASE_REG %rax - leaq (rPC, rINSTq, 2), rPC - FETCH_INST - jnz .L_suspend_request_pending - GOTO_NEXT - -.L_suspend_request_pending: - EXPORT_PC - movq rSELF, OUT_ARG0 - call SYMBOL(MterpSuspendCheck) # (self) - testb %al, %al - jnz MterpFallback - REFRESH_IBASE # might have changed during suspend - GOTO_NEXT - -.L_no_count_backwards: - cmpl $JIT_CHECK_OSR, rPROFILE # possible OSR re-entry? - jne .L_resume_backward_branch -.L_osr_check: - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rINSTq, OUT_ARG2 - call SYMBOL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) - testb %al, %al - jz .L_resume_backward_branch - jmp MterpOnStackReplacement - -.L_forward_branch: - cmpl $JIT_CHECK_OSR, rPROFILE # possible OSR re-entry? - je .L_check_osr_forward -.L_resume_forward_branch: - leaq (rPC, rINSTq, 2), rPC - FETCH_INST - GOTO_NEXT - -.L_check_osr_forward: - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rINSTq, OUT_ARG2 - call SYMBOL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) - testb %al, %al - jz .L_resume_forward_branch - jmp MterpOnStackReplacement - -.L_add_batch: - movl rPROFILE, %eax - movq OFF_FP_METHOD(rFP), OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movw %ax, OFF_FP_COUNTDOWN_OFFSET(rFP) - movq rSELF, OUT_ARG2 - call SYMBOL(MterpAddHotnessBatch) # (method, shadow_frame, self) - movswl %ax, rPROFILE - jmp .L_no_count_backwards - -/* - * Entered from the conditional branch handlers when OSR check request active on - * not-taken path. All Dalvik not-taken conditional branch offsets are 2. - */ -.L_check_not_taken_osr: - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movl $2, OUT_32_ARG2 - call SYMBOL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) - testb %al, %al - jnz MterpOnStackReplacement - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* - * On-stack replacement has happened, and now we've returned from the compiled method. - */ -MterpOnStackReplacement: -#if MTERP_LOGGING - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movl rINST, OUT_32_ARG2 - call SYMBOL(MterpLogOSR) -#endif - movl $1, %eax - jmp MterpDone - -/* - * Bail out to reference interpreter. - */ -MterpFallback: - EXPORT_PC -#if MTERP_LOGGING - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - call SYMBOL(MterpLogFallback) -#endif -MterpCommonFallback: - xorl %eax, %eax - jmp MterpDone - -/* - * On entry: - * uint32_t* rFP (should still be live, pointer to base of vregs) - */ -MterpExceptionReturn: - movl $1, %eax - jmp MterpDone -MterpReturn: - movq OFF_FP_RESULT_REGISTER(rFP), %rdx - movq %rax, (%rdx) - movl $1, %eax -MterpDone: -/* - * At this point, we expect rPROFILE to be non-zero. If negative, hotness is disabled or we're - * checking for OSR. If greater than zero, we might have unreported hotness to register - * (the difference between the ending rPROFILE and the cached hotness counter). rPROFILE - * should only reach zero immediately after a hotness decrement, and is then reset to either - * a negative special state or the new non-zero countdown value. - */ - testl rPROFILE, rPROFILE - jle MRestoreFrame # if > 0, we may have some counts to report. - - movl %eax, rINST # stash return value - /* Report cached hotness counts */ - movl rPROFILE, %eax - movq OFF_FP_METHOD(rFP), OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movw %ax, OFF_FP_COUNTDOWN_OFFSET(rFP) - movq rSELF, OUT_ARG2 - call SYMBOL(MterpAddHotnessBatch) # (method, shadow_frame, self) - movl rINST, %eax # restore return value - - /* pop up frame */ -MRestoreFrame: - addq $FRAME_SIZE, %rsp - .cfi_adjust_cfa_offset -FRAME_SIZE - - /* Restore callee save register */ - POP %r15 - POP %r14 - POP %r13 - POP %r12 - POP %rbp - POP %rbx - ret - .cfi_endproc - SIZE(ExecuteMterpImpl,ExecuteMterpImpl) - diff --git a/runtime/interpreter/mterp/rebuild.sh b/runtime/interpreter/mterp/rebuild.sh deleted file mode 100755 index ca3dcd9a136a27844fcba607cc3f27c11b1e08c3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/rebuild.sh +++ /dev/null @@ -1,23 +0,0 @@ -#!/bin/sh -# -# Copyright (C) 2016 The Android Open Source Project -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -# -# Rebuild for all known targets. Necessary until the stuff in "out" gets -# generated as part of the build. -# -set -e - -for arch in arm x86 mips arm64 x86_64 mips64; do TARGET_ARCH_EXT=$arch make -f Makefile_mterp; done diff --git a/runtime/interpreter/mterp/x86/alt_stub.S b/runtime/interpreter/mterp/x86/alt_stub.S deleted file mode 100644 index a5b39b80e9f44e56a5fe69904f1593d28f385d56..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/alt_stub.S +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - REFRESH_IBASE - jmp .L_op_nop+(${opnum}*${handler_size_bytes}) diff --git a/runtime/interpreter/mterp/x86/arithmetic.S b/runtime/interpreter/mterp/x86/arithmetic.S new file mode 100644 index 0000000000000000000000000000000000000000..a9fa0fc68f26fb777f6c4715c2c76ec36010f4c0 --- /dev/null +++ b/runtime/interpreter/mterp/x86/arithmetic.S @@ -0,0 +1,936 @@ +%def bindiv(result="", special="", rem=""): +/* + * 32-bit binary div/rem operation. Handles special case of op0=minint and + * op1=-1. + */ + /* div/rem vAA, vBB, vCC */ + movzbl 2(rPC), %eax # eax <- BB + movzbl 3(rPC), %ecx # ecx <- CC + GET_VREG %eax, %eax # eax <- vBB + GET_VREG %ecx, %ecx # ecx <- vCC + mov rIBASE, LOCAL0(%esp) + testl %ecx, %ecx + je common_errDivideByZero + movl %eax, %edx + orl %ecx, %edx + testl $$0xFFFFFF00, %edx # If both arguments are less + # than 8-bit and +ve + jz .L${opcode}_8 # Do 8-bit divide + testl $$0xFFFF0000, %edx # If both arguments are less + # than 16-bit and +ve + jz .L${opcode}_16 # Do 16-bit divide + cmpl $$-1, %ecx + jne .L${opcode}_32 + cmpl $$0x80000000, %eax + jne .L${opcode}_32 + movl $special, $result + jmp .L${opcode}_finish +.L${opcode}_32: + cltd + idivl %ecx + jmp .L${opcode}_finish +.L${opcode}_8: + div %cl # 8-bit divide otherwise. + # Remainder in %ah, quotient in %al + .if $rem + movl %eax, %edx + shr $$8, %edx + .else + andl $$0x000000FF, %eax + .endif + jmp .L${opcode}_finish +.L${opcode}_16: + xorl %edx, %edx # Clear %edx before divide + div %cx +.L${opcode}_finish: + SET_VREG $result, rINST + mov LOCAL0(%esp), rIBASE + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def bindiv2addr(result="", special=""): +/* + * 32-bit binary div/rem operation. Handles special case of op0=minint and + * op1=-1. + */ + /* div/rem/2addr vA, vB */ + movzx rINSTbl, %ecx # eax <- BA + mov rIBASE, LOCAL0(%esp) + sarl $$4, %ecx # ecx <- B + GET_VREG %ecx, %ecx # eax <- vBB + andb $$0xf, rINSTbl # rINST <- A + GET_VREG %eax, rINST # eax <- vBB + testl %ecx, %ecx + je common_errDivideByZero + cmpl $$-1, %ecx + jne .L${opcode}_continue_div2addr + cmpl $$0x80000000, %eax + jne .L${opcode}_continue_div2addr + movl $special, $result + SET_VREG $result, rINST + mov LOCAL0(%esp), rIBASE + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +.L${opcode}_continue_div2addr: + cltd + idivl %ecx + SET_VREG $result, rINST + mov LOCAL0(%esp), rIBASE + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def bindivLit16(result="", special=""): +/* + * 32-bit binary div/rem operation. Handles special case of op0=minint and + * op1=-1. + */ + /* div/rem/lit16 vA, vB, #+CCCC */ + /* Need A in rINST, ssssCCCC in ecx, vB in eax */ + movzbl rINSTbl, %eax # eax <- 000000BA + sarl $$4, %eax # eax <- B + GET_VREG %eax, %eax # eax <- vB + movswl 2(rPC), %ecx # ecx <- ssssCCCC + andb $$0xf, rINSTbl # rINST <- A + testl %ecx, %ecx + je common_errDivideByZero + cmpl $$-1, %ecx + jne .L${opcode}_continue_div + cmpl $$0x80000000, %eax + jne .L${opcode}_continue_div + movl $special, %eax + SET_VREG %eax, rINST + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +.L${opcode}_continue_div: + mov rIBASE, LOCAL0(%esp) + cltd + idivl %ecx + SET_VREG $result, rINST + mov LOCAL0(%esp), rIBASE + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def bindivLit8(result="", special=""): +/* + * 32-bit div/rem "lit8" binary operation. Handles special case of + * op0=minint & op1=-1 + */ + /* div/rem/lit8 vAA, vBB, #+CC */ + movzbl 2(rPC), %eax # eax <- BB + movsbl 3(rPC), %ecx # ecx <- ssssssCC + GET_VREG %eax, %eax # eax <- rBB + testl %ecx, %ecx + je common_errDivideByZero + cmpl $$0x80000000, %eax + jne .L${opcode}_continue_div + cmpl $$-1, %ecx + jne .L${opcode}_continue_div + movl $special, %eax + SET_VREG %eax, rINST + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +.L${opcode}_continue_div: + mov rIBASE, LOCAL0(%esp) + cltd + idivl %ecx + SET_VREG $result, rINST + mov LOCAL0(%esp), rIBASE + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def binop(result="%eax", instr=""): +/* + * Generic 32-bit binary operation. Provide an "instr" line that + * specifies an instruction that performs "result = eax op (rFP,%ecx,4)". + * This could be an x86 instruction or a function call. (If the result + * comes back in a register other than eax, you can override "result".) + * + * For: add-int, sub-int, and-int, or-int, + * xor-int, shl-int, shr-int, ushr-int + */ + /* binop vAA, vBB, vCC */ + movzbl 2(rPC), %eax # eax <- BB + movzbl 3(rPC), %ecx # ecx <- CC + GET_VREG %eax, %eax # eax <- vBB + $instr # ex: addl (rFP,%ecx,4),%eax + SET_VREG $result, rINST + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def binop1(result="%eax", tmp="%ecx", instr=""): +/* + * Generic 32-bit binary operation in which both operands loaded to + * registers (op0 in eax, op1 in ecx). + */ + /* binop vAA, vBB, vCC */ + movzbl 2(rPC),%eax # eax <- BB + movzbl 3(rPC),%ecx # ecx <- CC + GET_VREG %eax, %eax # eax <- vBB + GET_VREG %ecx, %ecx # eax <- vBB + $instr # ex: addl %ecx,%eax + SET_VREG $result, rINST + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def binop2addr(result="%eax", instr=""): +/* + * Generic 32-bit "/2addr" binary operation. Provide an "instr" line + * that specifies an instruction that performs "result = r0 op r1". + * This could be an instruction or a function call. + * + * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, + * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, + * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, + * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr + */ + /* binop/2addr vA, vB */ + movzx rINSTbl, %ecx # ecx <- A+ + sarl $$4, rINST # rINST <- B + GET_VREG %eax, rINST # eax <- vB + andb $$0xf, %cl # ecx <- A + $instr # for ex: addl %eax,(rFP,%ecx,4) + CLEAR_REF %ecx + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def binopLit16(result="%eax", instr=""): +/* + * Generic 32-bit "lit16" binary operation. Provide an "instr" line + * that specifies an instruction that performs "result = eax op ecx". + * This could be an x86 instruction or a function call. (If the result + * comes back in a register other than eax, you can override "result".) + * + * For: add-int/lit16, rsub-int, + * and-int/lit16, or-int/lit16, xor-int/lit16 + */ + /* binop/lit16 vA, vB, #+CCCC */ + movzbl rINSTbl, %eax # eax <- 000000BA + sarl $$4, %eax # eax <- B + GET_VREG %eax, %eax # eax <- vB + movswl 2(rPC), %ecx # ecx <- ssssCCCC + andb $$0xf, rINSTbl # rINST <- A + $instr # for example: addl %ecx, %eax + SET_VREG $result, rINST + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def binopLit8(result="%eax", instr=""): +/* + * Generic 32-bit "lit8" binary operation. Provide an "instr" line + * that specifies an instruction that performs "result = eax op ecx". + * This could be an x86 instruction or a function call. (If the result + * comes back in a register other than r0, you can override "result".) + * + * For: add-int/lit8, rsub-int/lit8 + * and-int/lit8, or-int/lit8, xor-int/lit8, + * shl-int/lit8, shr-int/lit8, ushr-int/lit8 + */ + /* binop/lit8 vAA, vBB, #+CC */ + movzbl 2(rPC), %eax # eax <- BB + movsbl 3(rPC), %ecx # ecx <- ssssssCC + GET_VREG %eax, %eax # eax <- rBB + $instr # ex: addl %ecx,%eax + SET_VREG $result, rINST + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def binopWide(instr1="", instr2=""): +/* + * Generic 64-bit binary operation. + */ + /* binop vAA, vBB, vCC */ + movzbl 2(rPC), %eax # eax <- BB + movzbl 3(rPC), %ecx # ecx <- CC + movl rIBASE, LOCAL0(%esp) # save rIBASE + GET_VREG rIBASE, %eax # rIBASE <- v[BB+0] + GET_VREG_HIGH %eax, %eax # eax <- v[BB+1] + $instr1 # ex: addl (rFP,%ecx,4),rIBASE + $instr2 # ex: adcl 4(rFP,%ecx,4),%eax + SET_VREG rIBASE, rINST # v[AA+0] <- rIBASE + movl LOCAL0(%esp), rIBASE # restore rIBASE + SET_VREG_HIGH %eax, rINST # v[AA+1] <- eax + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def binopWide2addr(instr1="", instr2=""): +/* + * Generic 64-bit binary operation. + */ + /* binop/2addr vA, vB */ + movzbl rINSTbl, %ecx # ecx<- BA + sarl $$4, %ecx # ecx<- B + GET_VREG %eax, %ecx # eax<- v[B+0] + GET_VREG_HIGH %ecx, %ecx # eax<- v[B+1] + andb $$0xF, rINSTbl # rINST<- A + $instr1 # ex: addl %eax,(rFP,rINST,4) + $instr2 # ex: adcl %ecx,4(rFP,rINST,4) + CLEAR_WIDE_REF rINST + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def cvtfp_int(srcdouble="1", tgtlong="1"): +/* On fp to int conversions, Java requires that + * if the result > maxint, it should be clamped to maxint. If it is less + * than minint, it should be clamped to minint. If it is a nan, the result + * should be zero. Further, the rounding mode is to truncate. This model + * differs from what is delivered normally via the x86 fpu, so we have + * to play some games. + */ + /* float/double to int/long vA, vB */ + movzbl rINSTbl, %ecx # ecx <- A+ + sarl $$4, rINST # rINST <- B + .if $srcdouble + fldl VREG_ADDRESS(rINST) # %st0 <- vB + .else + flds VREG_ADDRESS(rINST) # %st0 <- vB + .endif + ftst + fnstcw LOCAL0(%esp) # remember original rounding mode + movzwl LOCAL0(%esp), %eax + movb $$0xc, %ah + movw %ax, LOCAL0+2(%esp) + fldcw LOCAL0+2(%esp) # set "to zero" rounding mode + andb $$0xf, %cl # ecx <- A + .if $tgtlong + fistpll VREG_ADDRESS(%ecx) # convert and store + .else + fistpl VREG_ADDRESS(%ecx) # convert and store + .endif + fldcw LOCAL0(%esp) # restore previous rounding mode + .if $tgtlong + movl $$0x80000000, %eax + xorl VREG_HIGH_ADDRESS(%ecx), %eax + orl VREG_ADDRESS(%ecx), %eax + .else + cmpl $$0x80000000, VREG_ADDRESS(%ecx) + .endif + je .L${opcode}_special_case # fix up result + +.L${opcode}_finish: + xor %eax, %eax + mov %eax, VREG_REF_ADDRESS(%ecx) + .if $tgtlong + mov %eax, VREG_REF_HIGH_ADDRESS(%ecx) + .endif + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +.L${opcode}_special_case: + fnstsw %ax + sahf + jp .L${opcode}_isNaN + adcl $$-1, VREG_ADDRESS(%ecx) + .if $tgtlong + adcl $$-1, VREG_HIGH_ADDRESS(%ecx) + .endif + jmp .L${opcode}_finish +.L${opcode}_isNaN: + movl $$0, VREG_ADDRESS(%ecx) + .if $tgtlong + movl $$0, VREG_HIGH_ADDRESS(%ecx) + .endif + jmp .L${opcode}_finish + +%def shop2addr(result="%eax", instr=""): +/* + * Generic 32-bit "shift/2addr" operation. + */ + /* shift/2addr vA, vB */ + movzx rINSTbl, %ecx # eax <- BA + sarl $$4, %ecx # ecx <- B + GET_VREG %ecx, %ecx # eax <- vBB + andb $$0xf, rINSTbl # rINST <- A + GET_VREG %eax, rINST # eax <- vAA + $instr # ex: sarl %cl, %eax + SET_VREG $result, rINST + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def unop(instr=""): +/* + * Generic 32-bit unary operation. Provide an "instr" line that + * specifies an instruction that performs "result = op eax". + */ + /* unop vA, vB */ + movzbl rINSTbl,%ecx # ecx <- A+ + sarl $$4,rINST # rINST <- B + GET_VREG %eax, rINST # eax <- vB + andb $$0xf,%cl # ecx <- A + $instr + SET_VREG %eax, %ecx + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_add_int(): +% binop(instr="addl (rFP,%ecx,4), %eax") + +%def op_add_int_2addr(): +% binop2addr(instr="addl %eax, (rFP,%ecx,4)") + +%def op_add_int_lit16(): +% binopLit16(instr="addl %ecx, %eax") + +%def op_add_int_lit8(): +% binopLit8(instr="addl %ecx, %eax") + +%def op_add_long(): +% binopWide(instr1="addl (rFP,%ecx,4), rIBASE", instr2="adcl 4(rFP,%ecx,4), %eax") + +%def op_add_long_2addr(): +% binopWide2addr(instr1="addl %eax, (rFP,rINST,4)", instr2="adcl %ecx, 4(rFP,rINST,4)") + +%def op_and_int(): +% binop(instr="andl (rFP,%ecx,4), %eax") + +%def op_and_int_2addr(): +% binop2addr(instr="andl %eax, (rFP,%ecx,4)") + +%def op_and_int_lit16(): +% binopLit16(instr="andl %ecx, %eax") + +%def op_and_int_lit8(): +% binopLit8(instr="andl %ecx, %eax") + +%def op_and_long(): +% binopWide(instr1="andl (rFP,%ecx,4), rIBASE", instr2="andl 4(rFP,%ecx,4), %eax") + +%def op_and_long_2addr(): +% binopWide2addr(instr1="andl %eax, (rFP,rINST,4)", instr2="andl %ecx, 4(rFP,rINST,4)") + +%def op_cmp_long(): +/* + * Compare two 64-bit values. Puts 0, 1, or -1 into the destination + * register based on the results of the comparison. + */ + /* cmp-long vAA, vBB, vCC */ + movzbl 2(rPC), %eax # eax <- BB + movzbl 3(rPC), %ecx # ecx <- CC + GET_VREG_HIGH %eax, %eax # eax <- v[BB+1], BB is clobbered + cmpl VREG_HIGH_ADDRESS(%ecx), %eax + jl .L${opcode}_smaller + jg .L${opcode}_bigger + movzbl 2(rPC), %eax # eax <- BB, restore BB + GET_VREG %eax, %eax # eax <- v[BB] + sub VREG_ADDRESS(%ecx), %eax + ja .L${opcode}_bigger + jb .L${opcode}_smaller +.L${opcode}_finish: + SET_VREG %eax, rINST + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +.L${opcode}_bigger: + movl $$1, %eax + jmp .L${opcode}_finish + +.L${opcode}_smaller: + movl $$-1, %eax + jmp .L${opcode}_finish + +%def op_div_int(): +% bindiv(result="%eax", special="$0x80000000", rem="0") + +%def op_div_int_2addr(): +% bindiv2addr(result="%eax", special="$0x80000000") + +%def op_div_int_lit16(): +% bindivLit16(result="%eax", special="$0x80000000") + +%def op_div_int_lit8(): +% bindivLit8(result="%eax", special="$0x80000000") + +%def op_div_long(routine="art_quick_ldiv"): +/* art_quick_* methods has quick abi, + * so use eax, ecx, edx, ebx for args + */ + /* div vAA, vBB, vCC */ + .extern $routine + mov rIBASE, LOCAL0(%esp) # save rIBASE/%edx + mov rINST, LOCAL1(%esp) # save rINST/%ebx + movzbl 3(rPC), %eax # eax <- CC + GET_VREG %ecx, %eax + GET_VREG_HIGH %ebx, %eax + movl %ecx, %edx + orl %ebx, %ecx + jz common_errDivideByZero + movzbl 2(rPC), %eax # eax <- BB + GET_VREG_HIGH %ecx, %eax + GET_VREG %eax, %eax + call SYMBOL($routine) + mov LOCAL1(%esp), rINST # restore rINST/%ebx + SET_VREG_HIGH rIBASE, rINST + SET_VREG %eax, rINST + mov LOCAL0(%esp), rIBASE # restore rIBASE/%edx + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_div_long_2addr(routine="art_quick_ldiv"): +/* art_quick_* methods has quick abi, + * so use eax, ecx, edx, ebx for args + */ + /* div/2addr vA, vB */ + .extern $routine + mov rIBASE, LOCAL0(%esp) # save rIBASE/%edx + movzbl rINSTbl, %eax + shrl $$4, %eax # eax <- B + andb $$0xf, rINSTbl # rINST <- A + mov rINST, LOCAL1(%esp) # save rINST/%ebx + movl %ebx, %ecx + GET_VREG %edx, %eax + GET_VREG_HIGH %ebx, %eax + movl %edx, %eax + orl %ebx, %eax + jz common_errDivideByZero + GET_VREG %eax, %ecx + GET_VREG_HIGH %ecx, %ecx + call SYMBOL($routine) + mov LOCAL1(%esp), rINST # restore rINST/%ebx + SET_VREG_HIGH rIBASE, rINST + SET_VREG %eax, rINST + mov LOCAL0(%esp), rIBASE # restore rIBASE/%edx + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_int_to_byte(): +% unop(instr="movsbl %al, %eax") + +%def op_int_to_char(): +% unop(instr="movzwl %ax,%eax") + +%def op_int_to_long(): + /* int to long vA, vB */ + movzbl rINSTbl, %eax # eax <- +A + sarl $$4, %eax # eax <- B + GET_VREG %eax, %eax # eax <- vB + andb $$0xf, rINSTbl # rINST <- A + movl rIBASE, %ecx # cltd trashes rIBASE/edx + cltd # rINST:eax<- sssssssBBBBBBBB + SET_VREG_HIGH rIBASE, rINST # v[A+1] <- rIBASE + SET_VREG %eax, rINST # v[A+0] <- %eax + movl %ecx, rIBASE + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + + +%def op_int_to_short(): +% unop(instr="movswl %ax, %eax") + +%def op_long_to_int(): +/* we ignore the high word, making this equivalent to a 32-bit reg move */ +% op_move() + +%def op_mul_int(): + /* + * 32-bit binary multiplication. + */ + /* mul vAA, vBB, vCC */ + movzbl 2(rPC), %eax # eax <- BB + movzbl 3(rPC), %ecx # ecx <- CC + GET_VREG %eax, %eax # eax <- vBB + mov rIBASE, LOCAL0(%esp) + imull (rFP,%ecx,4), %eax # trashes rIBASE/edx + mov LOCAL0(%esp), rIBASE + SET_VREG %eax, rINST + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_mul_int_2addr(): + /* mul vA, vB */ + movzx rINSTbl, %ecx # ecx <- A+ + sarl $$4, rINST # rINST <- B + GET_VREG %eax, rINST # eax <- vB + andb $$0xf, %cl # ecx <- A + movl rIBASE, rINST + imull (rFP,%ecx,4), %eax # trashes rIBASE/edx + movl rINST, rIBASE + SET_VREG %eax, %ecx + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_mul_int_lit16(): + /* mul/lit16 vA, vB, #+CCCC */ + /* Need A in rINST, ssssCCCC in ecx, vB in eax */ + movzbl rINSTbl, %eax # eax <- 000000BA + sarl $$4, %eax # eax <- B + GET_VREG %eax, %eax # eax <- vB + movl rIBASE, %ecx + movswl 2(rPC), rIBASE # rIBASE <- ssssCCCC + andb $$0xf, rINSTbl # rINST <- A + imull rIBASE, %eax # trashes rIBASE/edx + movl %ecx, rIBASE + SET_VREG %eax, rINST + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_mul_int_lit8(): + /* mul/lit8 vAA, vBB, #+CC */ + movzbl 2(rPC), %eax # eax <- BB + movl rIBASE, %ecx + GET_VREG %eax, %eax # eax <- rBB + movsbl 3(rPC), rIBASE # rIBASE <- ssssssCC + imull rIBASE, %eax # trashes rIBASE/edx + movl %ecx, rIBASE + SET_VREG %eax, rINST + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_mul_long(): +/* + * Signed 64-bit integer multiply. + * + * We could definately use more free registers for + * this code. We spill rINSTw (ebx), + * giving us eax, ebc, ecx and edx as computational + * temps. On top of that, we'll spill edi (rFP) + * for use as the vB pointer and esi (rPC) for use + * as the vC pointer. Yuck. + * + */ + /* mul-long vAA, vBB, vCC */ + movzbl 2(rPC), %eax # eax <- B + movzbl 3(rPC), %ecx # ecx <- C + mov rPC, LOCAL0(%esp) # save Interpreter PC + mov rFP, LOCAL1(%esp) # save FP + mov rIBASE, LOCAL2(%esp) # save rIBASE + leal (rFP,%eax,4), %esi # esi <- &v[B] + leal (rFP,%ecx,4), rFP # rFP <- &v[C] + movl 4(%esi), %ecx # ecx <- Bmsw + imull (rFP), %ecx # ecx <- (Bmsw*Clsw) + movl 4(rFP), %eax # eax <- Cmsw + imull (%esi), %eax # eax <- (Cmsw*Blsw) + addl %eax, %ecx # ecx <- (Bmsw*Clsw)+(Cmsw*Blsw) + movl (rFP), %eax # eax <- Clsw + mull (%esi) # eax <- (Clsw*Alsw) + mov LOCAL0(%esp), rPC # restore Interpreter PC + mov LOCAL1(%esp), rFP # restore FP + leal (%ecx,rIBASE), rIBASE # full result now in rIBASE:%eax + SET_VREG_HIGH rIBASE, rINST # v[B+1] <- rIBASE + mov LOCAL2(%esp), rIBASE # restore IBASE + SET_VREG %eax, rINST # v[B] <- eax + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_mul_long_2addr(): +/* + * Signed 64-bit integer multiply, 2-addr version + * + * We could definately use more free registers for + * this code. We must spill %edx (rIBASE) because it + * is used by imul. We'll also spill rINST (ebx), + * giving us eax, ebc, ecx and rIBASE as computational + * temps. On top of that, we'll spill %esi (edi) + * for use as the vA pointer and rFP (esi) for use + * as the vB pointer. Yuck. + */ + /* mul-long/2addr vA, vB */ + movzbl rINSTbl, %eax # eax <- BA + andb $$0xf, %al # eax <- A + CLEAR_WIDE_REF %eax # clear refs in advance + sarl $$4, rINST # rINST <- B + mov rPC, LOCAL0(%esp) # save Interpreter PC + mov rFP, LOCAL1(%esp) # save FP + mov rIBASE, LOCAL2(%esp) # save rIBASE + leal (rFP,%eax,4), %esi # esi <- &v[A] + leal (rFP,rINST,4), rFP # rFP <- &v[B] + movl 4(%esi), %ecx # ecx <- Amsw + imull (rFP), %ecx # ecx <- (Amsw*Blsw) + movl 4(rFP), %eax # eax <- Bmsw + imull (%esi), %eax # eax <- (Bmsw*Alsw) + addl %eax, %ecx # ecx <- (Amsw*Blsw)+(Bmsw*Alsw) + movl (rFP), %eax # eax <- Blsw + mull (%esi) # eax <- (Blsw*Alsw) + leal (%ecx,rIBASE), rIBASE # full result now in %edx:%eax + movl rIBASE, 4(%esi) # v[A+1] <- rIBASE + movl %eax, (%esi) # v[A] <- %eax + mov LOCAL0(%esp), rPC # restore Interpreter PC + mov LOCAL2(%esp), rIBASE # restore IBASE + mov LOCAL1(%esp), rFP # restore FP + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_neg_int(): +% unop(instr="negl %eax") + +%def op_neg_long(): + /* unop vA, vB */ + movzbl rINSTbl, %ecx # ecx <- BA + sarl $$4, %ecx # ecx <- B + andb $$0xf, rINSTbl # rINST <- A + GET_VREG %eax, %ecx # eax <- v[B+0] + GET_VREG_HIGH %ecx, %ecx # ecx <- v[B+1] + negl %eax + adcl $$0, %ecx + negl %ecx + SET_VREG %eax, rINST # v[A+0] <- eax + SET_VREG_HIGH %ecx, rINST # v[A+1] <- ecx + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + + +%def op_not_int(): +% unop(instr="notl %eax") + +%def op_not_long(): + /* unop vA, vB */ + movzbl rINSTbl, %ecx # ecx <- BA + sarl $$4, %ecx # ecx <- B + andb $$0xf, rINSTbl # rINST <- A + GET_VREG %eax, %ecx # eax <- v[B+0] + GET_VREG_HIGH %ecx, %ecx # ecx <- v[B+1] + notl %eax + notl %ecx + SET_VREG %eax, rINST # v[A+0] <- eax + SET_VREG_HIGH %ecx, rINST # v[A+1] <- ecx + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_or_int(): +% binop(instr="orl (rFP,%ecx,4), %eax") + +%def op_or_int_2addr(): +% binop2addr(instr="orl %eax, (rFP,%ecx,4)") + +%def op_or_int_lit16(): +% binopLit16(instr="orl %ecx, %eax") + +%def op_or_int_lit8(): +% binopLit8(instr="orl %ecx, %eax") + +%def op_or_long(): +% binopWide(instr1="orl (rFP,%ecx,4), rIBASE", instr2="orl 4(rFP,%ecx,4), %eax") + +%def op_or_long_2addr(): +% binopWide2addr(instr1="orl %eax, (rFP,rINST,4)", instr2="orl %ecx, 4(rFP,rINST,4)") + +%def op_rem_int(): +% bindiv(result="rIBASE", special="$0", rem="1") + +%def op_rem_int_2addr(): +% bindiv2addr(result="rIBASE", special="$0") + +%def op_rem_int_lit16(): +% bindivLit16(result="rIBASE", special="$0") + +%def op_rem_int_lit8(): +% bindivLit8(result="rIBASE", special="$0") + +%def op_rem_long(): +% op_div_long(routine="art_quick_lmod") + +%def op_rem_long_2addr(): +% op_div_long_2addr(routine="art_quick_lmod") + +%def op_rsub_int(): +/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ +% binopLit16(instr="subl %eax, %ecx", result="%ecx") + +%def op_rsub_int_lit8(): +% binopLit8(instr="subl %eax, %ecx", result="%ecx") + +%def op_shl_int(): +% binop1(instr="sall %cl, %eax") + +%def op_shl_int_2addr(): +% shop2addr(instr="sall %cl, %eax") + +%def op_shl_int_lit8(): +% binopLit8(instr="sall %cl, %eax") + +%def op_shl_long(): +/* + * Long integer shift. This is different from the generic 32/64-bit + * binary operations because vAA/vBB are 64-bit but vCC (the shift + * distance) is 32-bit. Also, Dalvik requires us to mask off the low + * 6 bits of the shift distance. x86 shifts automatically mask off + * the low 5 bits of %cl, so have to handle the 64 > shiftcount > 31 + * case specially. + */ + /* shl-long vAA, vBB, vCC */ + /* ecx gets shift count */ + /* Need to spill rINST */ + /* rINSTw gets AA */ + movzbl 2(rPC), %eax # eax <- BB + movzbl 3(rPC), %ecx # ecx <- CC + movl rIBASE, LOCAL0(%esp) + GET_VREG_HIGH rIBASE, %eax # ecx <- v[BB+1] + GET_VREG %ecx, %ecx # ecx <- vCC + GET_VREG %eax, %eax # eax <- v[BB+0] + shldl %eax,rIBASE + sall %cl, %eax + testb $$32, %cl + je 2f + movl %eax, rIBASE + xorl %eax, %eax +2: + SET_VREG_HIGH rIBASE, rINST # v[AA+1] <- rIBASE + movl LOCAL0(%esp), rIBASE + SET_VREG %eax, rINST # v[AA+0] <- %eax + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_shl_long_2addr(): +/* + * Long integer shift, 2addr version. vA is 64-bit value/result, vB is + * 32-bit shift distance. + */ + /* shl-long/2addr vA, vB */ + /* ecx gets shift count */ + /* Need to spill rIBASE */ + /* rINSTw gets AA */ + movzbl rINSTbl, %ecx # ecx <- BA + andb $$0xf, rINSTbl # rINST <- A + GET_VREG %eax, rINST # eax <- v[AA+0] + sarl $$4, %ecx # ecx <- B + movl rIBASE, LOCAL0(%esp) + GET_VREG_HIGH rIBASE, rINST # rIBASE <- v[AA+1] + GET_VREG %ecx, %ecx # ecx <- vBB + shldl %eax, rIBASE + sall %cl, %eax + testb $$32, %cl + je 2f + movl %eax, rIBASE + xorl %eax, %eax +2: + SET_VREG_HIGH rIBASE, rINST # v[AA+1] <- rIBASE + movl LOCAL0(%esp), rIBASE + SET_VREG %eax, rINST # v[AA+0] <- eax + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_shr_int(): +% binop1(instr="sarl %cl, %eax") + +%def op_shr_int_2addr(): +% shop2addr(instr="sarl %cl, %eax") + +%def op_shr_int_lit8(): +% binopLit8(instr="sarl %cl, %eax") + +%def op_shr_long(): +/* + * Long integer shift. This is different from the generic 32/64-bit + * binary operations because vAA/vBB are 64-bit but vCC (the shift + * distance) is 32-bit. Also, Dalvik requires us to mask off the low + * 6 bits of the shift distance. x86 shifts automatically mask off + * the low 5 bits of %cl, so have to handle the 64 > shiftcount > 31 + * case specially. + */ + /* shr-long vAA, vBB, vCC */ + /* ecx gets shift count */ + /* Need to spill rIBASE */ + /* rINSTw gets AA */ + movzbl 2(rPC), %eax # eax <- BB + movzbl 3(rPC), %ecx # ecx <- CC + movl rIBASE, LOCAL0(%esp) + GET_VREG_HIGH rIBASE, %eax # rIBASE<- v[BB+1] + GET_VREG %ecx, %ecx # ecx <- vCC + GET_VREG %eax, %eax # eax <- v[BB+0] + shrdl rIBASE, %eax + sarl %cl, rIBASE + testb $$32, %cl + je 2f + movl rIBASE, %eax + sarl $$31, rIBASE +2: + SET_VREG_HIGH rIBASE, rINST # v[AA+1] <- rIBASE + movl LOCAL0(%esp), rIBASE + SET_VREG %eax, rINST # v[AA+0] <- eax + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_shr_long_2addr(): +/* + * Long integer shift, 2addr version. vA is 64-bit value/result, vB is + * 32-bit shift distance. + */ + /* shl-long/2addr vA, vB */ + /* ecx gets shift count */ + /* Need to spill rIBASE */ + /* rINSTw gets AA */ + movzbl rINSTbl, %ecx # ecx <- BA + andb $$0xf, rINSTbl # rINST <- A + GET_VREG %eax, rINST # eax <- v[AA+0] + sarl $$4, %ecx # ecx <- B + movl rIBASE, LOCAL0(%esp) + GET_VREG_HIGH rIBASE, rINST # rIBASE <- v[AA+1] + GET_VREG %ecx, %ecx # ecx <- vBB + shrdl rIBASE, %eax + sarl %cl, rIBASE + testb $$32, %cl + je 2f + movl rIBASE, %eax + sarl $$31, rIBASE +2: + SET_VREG_HIGH rIBASE, rINST # v[AA+1] <- rIBASE + movl LOCAL0(%esp), rIBASE + SET_VREG %eax, rINST # v[AA+0] <- eax + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_sub_int(): +% binop(instr="subl (rFP,%ecx,4), %eax") + +%def op_sub_int_2addr(): +% binop2addr(instr="subl %eax, (rFP,%ecx,4)") + +%def op_sub_long(): +% binopWide(instr1="subl (rFP,%ecx,4), rIBASE", instr2="sbbl 4(rFP,%ecx,4), %eax") + +%def op_sub_long_2addr(): +% binopWide2addr(instr1="subl %eax, (rFP,rINST,4)", instr2="sbbl %ecx, 4(rFP,rINST,4)") + +%def op_ushr_int(): +% binop1(instr="shrl %cl, %eax") + +%def op_ushr_int_2addr(): +% shop2addr(instr="shrl %cl, %eax") + +%def op_ushr_int_lit8(): +% binopLit8(instr="shrl %cl, %eax") + +%def op_ushr_long(): +/* + * Long integer shift. This is different from the generic 32/64-bit + * binary operations because vAA/vBB are 64-bit but vCC (the shift + * distance) is 32-bit. Also, Dalvik requires us to mask off the low + * 6 bits of the shift distance. x86 shifts automatically mask off + * the low 5 bits of %cl, so have to handle the 64 > shiftcount > 31 + * case specially. + */ + /* shr-long vAA, vBB, vCC */ + /* ecx gets shift count */ + /* Need to spill rIBASE */ + /* rINSTw gets AA */ + movzbl 2(rPC), %eax # eax <- BB + movzbl 3(rPC), %ecx # ecx <- CC + movl rIBASE, LOCAL0(%esp) + GET_VREG_HIGH rIBASE, %eax # rIBASE <- v[BB+1] + GET_VREG %ecx, %ecx # ecx <- vCC + GET_VREG %eax, %eax # eax <- v[BB+0] + shrdl rIBASE, %eax + shrl %cl, rIBASE + testb $$32, %cl + je 2f + movl rIBASE, %eax + xorl rIBASE, rIBASE +2: + SET_VREG_HIGH rIBASE, rINST # v[AA+1] <- rIBASE + movl LOCAL0(%esp), rIBASE + SET_VREG %eax, rINST # v[BB+0] <- eax + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_ushr_long_2addr(): +/* + * Long integer shift, 2addr version. vA is 64-bit value/result, vB is + * 32-bit shift distance. + */ + /* shl-long/2addr vA, vB */ + /* ecx gets shift count */ + /* Need to spill rIBASE */ + /* rINSTw gets AA */ + movzbl rINSTbl, %ecx # ecx <- BA + andb $$0xf, rINSTbl # rINST <- A + GET_VREG %eax, rINST # eax <- v[AA+0] + sarl $$4, %ecx # ecx <- B + movl rIBASE, LOCAL0(%esp) + GET_VREG_HIGH rIBASE, rINST # rIBASE <- v[AA+1] + GET_VREG %ecx, %ecx # ecx <- vBB + shrdl rIBASE, %eax + shrl %cl, rIBASE + testb $$32, %cl + je 2f + movl rIBASE, %eax + xorl rIBASE, rIBASE +2: + SET_VREG_HIGH rIBASE, rINST # v[AA+1] <- rIBASE + movl LOCAL0(%esp), rIBASE + SET_VREG %eax, rINST # v[AA+0] <- eax + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_xor_int(): +% binop(instr="xorl (rFP,%ecx,4), %eax") + +%def op_xor_int_2addr(): +% binop2addr(instr="xorl %eax, (rFP,%ecx,4)") + +%def op_xor_int_lit16(): +% binopLit16(instr="xorl %ecx, %eax") + +%def op_xor_int_lit8(): +% binopLit8(instr="xorl %ecx, %eax") + +%def op_xor_long(): +% binopWide(instr1="xorl (rFP,%ecx,4), rIBASE", instr2="xorl 4(rFP,%ecx,4), %eax") + +%def op_xor_long_2addr(): +% binopWide2addr(instr1="xorl %eax, (rFP,rINST,4)", instr2="xorl %ecx, 4(rFP,rINST,4)") diff --git a/runtime/interpreter/mterp/x86/array.S b/runtime/interpreter/mterp/x86/array.S new file mode 100644 index 0000000000000000000000000000000000000000..de846a472835ce3a5691522b23bf16e838441b6a --- /dev/null +++ b/runtime/interpreter/mterp/x86/array.S @@ -0,0 +1,215 @@ +%def op_aget(load="movl", shift="4", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"): +/* + * Array get, 32 bits or less. vAA <- vBB[vCC]. + * + * for: aget, aget-boolean, aget-byte, aget-char, aget-short + * + */ + /* op vAA, vBB, vCC */ + movzbl 2(rPC), %eax # eax <- BB + movzbl 3(rPC), %ecx # ecx <- CC + GET_VREG %eax, %eax # eax <- vBB (array object) + GET_VREG %ecx, %ecx # ecx <- vCC (requested index) + testl %eax, %eax # null array object? + je common_errNullObject # bail if so + cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx + jae common_errArrayIndex # index >= length, bail. + $load $data_offset(%eax,%ecx,$shift), %eax + SET_VREG %eax, rINST + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_aget_boolean(): +% op_aget(load="movzbl", shift="1", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") + +%def op_aget_byte(): +% op_aget(load="movsbl", shift="1", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") + +%def op_aget_char(): +% op_aget(load="movzwl", shift="2", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") + +%def op_aget_object(): +/* + * Array object get. vAA <- vBB[vCC]. + * + * for: aget-object + */ + /* op vAA, vBB, vCC */ + movzbl 2(rPC), %eax # eax <- BB + movzbl 3(rPC), %ecx # ecx <- CC + GET_VREG %eax, %eax # eax <- vBB (array object) + GET_VREG %ecx, %ecx # ecs <- vCC (requested index) + EXPORT_PC + movl %eax, OUT_ARG0(%esp) + movl %ecx, OUT_ARG1(%esp) + call SYMBOL(artAGetObjectFromMterp) # (array, index) + movl rSELF, %ecx + RESTORE_IBASE_FROM_SELF %ecx + cmpl $$0, THREAD_EXCEPTION_OFFSET(%ecx) + jnz MterpException + SET_VREG_OBJECT %eax, rINST + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_aget_short(): +% op_aget(load="movswl", shift="2", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") + +%def op_aget_wide(): +/* + * Array get, 64 bits. vAA <- vBB[vCC]. + */ + /* aget-wide vAA, vBB, vCC */ + movzbl 2(rPC), %eax # eax <- BB + movzbl 3(rPC), %ecx # ecx <- CC + GET_VREG %eax, %eax # eax <- vBB (array object) + GET_VREG %ecx, %ecx # ecx <- vCC (requested index) + testl %eax, %eax # null array object? + je common_errNullObject # bail if so + cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx + jae common_errArrayIndex # index >= length, bail. + leal MIRROR_WIDE_ARRAY_DATA_OFFSET(%eax,%ecx,8), %eax + movq (%eax), %xmm0 # xmm0 <- vBB[vCC] + SET_WIDE_FP_VREG %xmm0, rINST # vAA <- xmm0 + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_aput(reg="rINST", store="movl", shift="4", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"): +/* + * Array put, 32 bits or less. vBB[vCC] <- vAA. + * + * for: aput, aput-boolean, aput-byte, aput-char, aput-short + * + */ + /* op vAA, vBB, vCC */ + movzbl 2(rPC), %eax # eax <- BB + movzbl 3(rPC), %ecx # ecx <- CC + GET_VREG %eax, %eax # eax <- vBB (array object) + GET_VREG %ecx, %ecx # ecx <- vCC (requested index) + testl %eax, %eax # null array object? + je common_errNullObject # bail if so + cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx + jae common_errArrayIndex # index >= length, bail. + leal $data_offset(%eax,%ecx,$shift), %eax + GET_VREG rINST, rINST + $store $reg, (%eax) + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_aput_boolean(): +% op_aput(reg="rINSTbl", store="movb", shift="1", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") + +%def op_aput_byte(): +% op_aput(reg="rINSTbl", store="movb", shift="1", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") + +%def op_aput_char(): +% op_aput(reg="rINSTw", store="movw", shift="2", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") + +%def op_aput_object(): +/* + * Store an object into an array. vBB[vCC] <- vAA. + */ + /* op vAA, vBB, vCC */ + EXPORT_PC + leal OFF_FP_SHADOWFRAME(rFP), %eax + movl %eax, OUT_ARG0(%esp) + movl rPC, OUT_ARG1(%esp) + REFRESH_INST ${opnum} + movl rINST, OUT_ARG2(%esp) + call SYMBOL(MterpAputObject) # (array, index) + RESTORE_IBASE + testb %al, %al + jz MterpPossibleException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_aput_short(): +% op_aput(reg="rINSTw", store="movw", shift="2", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") + +%def op_aput_wide(): +/* + * Array put, 64 bits. vBB[vCC] <- vAA. + * + */ + /* aput-wide vAA, vBB, vCC */ + movzbl 2(rPC), %eax # eax <- BB + movzbl 3(rPC), %ecx # ecx <- CC + GET_VREG %eax, %eax # eax <- vBB (array object) + GET_VREG %ecx, %ecx # ecx <- vCC (requested index) + testl %eax, %eax # null array object? + je common_errNullObject # bail if so + cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx + jae common_errArrayIndex # index >= length, bail. + leal MIRROR_WIDE_ARRAY_DATA_OFFSET(%eax,%ecx,8), %eax + GET_WIDE_FP_VREG %xmm0, rINST # xmm0 <- vAA + movq %xmm0, (%eax) # vBB[vCC] <- xmm0 + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_array_length(): +/* + * Return the length of an array. + */ + mov rINST, %eax # eax <- BA + sarl $$4, rINST # rINST <- B + GET_VREG %ecx, rINST # ecx <- vB (object ref) + testl %ecx, %ecx # is null? + je common_errNullObject + andb $$0xf, %al # eax <- A + movl MIRROR_ARRAY_LENGTH_OFFSET(%ecx), rINST + SET_VREG rINST, %eax + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_fill_array_data(): + /* fill-array-data vAA, +BBBBBBBB */ + EXPORT_PC + movl 2(rPC), %ecx # ecx <- BBBBbbbb + leal (rPC,%ecx,2), %ecx # ecx <- PC + BBBBbbbb*2 + GET_VREG %eax, rINST # eax <- vAA (array object) + movl %eax, OUT_ARG0(%esp) + movl %ecx, OUT_ARG1(%esp) + call SYMBOL(MterpFillArrayData) # (obj, payload) + REFRESH_IBASE + testb %al, %al # 0 means an exception is thrown + jz MterpPossibleException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 + +%def op_filled_new_array(helper="MterpFilledNewArray"): +/* + * Create a new array with elements filled from registers. + * + * for: filled-new-array, filled-new-array/range + */ + /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ + /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ + .extern $helper + EXPORT_PC + leal OFF_FP_SHADOWFRAME(rFP), %eax + movl %eax, OUT_ARG0(%esp) + movl rPC, OUT_ARG1(%esp) + movl rSELF, %ecx + movl %ecx, OUT_ARG2(%esp) + call SYMBOL($helper) + REFRESH_IBASE + testb %al, %al # 0 means an exception is thrown + jz MterpPossibleException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 + +%def op_filled_new_array_range(): +% op_filled_new_array(helper="MterpFilledNewArrayRange") + +%def op_new_array(): +/* + * Allocate an array of objects, specified with the array class + * and a count. + * + * The verifier guarantees that this is an array class, so we don't + * check for it here. + */ + /* new-array vA, vB, class@CCCC */ + EXPORT_PC + leal OFF_FP_SHADOWFRAME(rFP), %eax + movl %eax, OUT_ARG0(%esp) + movl rPC, OUT_ARG1(%esp) + REFRESH_INST ${opnum} + movl rINST, OUT_ARG2(%esp) + movl rSELF, %ecx + movl %ecx, OUT_ARG3(%esp) + call SYMBOL(MterpNewArray) + RESTORE_IBASE + testb %al, %al # 0 means an exception is thrown + jz MterpPossibleException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/bincmp.S b/runtime/interpreter/mterp/x86/bincmp.S deleted file mode 100644 index ee32278d5b2001e5a43d90f9bc1526cdeef420f3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/bincmp.S +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Generic two-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - movzx rINSTbl, %ecx # ecx <- A+ - andb $$0xf, %cl # ecx <- A - GET_VREG %eax, %ecx # eax <- vA - sarl $$4, rINST # rINST <- B - cmpl VREG_ADDRESS(rINST), %eax # compare (vA, vB) - j${revcmp} 1f - movswl 2(rPC), rINST # Get signed branch offset - testl rINST, rINST - jmp MterpCommonTakenBranch -1: - cmpw $$JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/bindiv.S b/runtime/interpreter/mterp/x86/bindiv.S deleted file mode 100644 index e87ba45546b811a1da21fbeb3276e97a9c01e365..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/bindiv.S +++ /dev/null @@ -1,48 +0,0 @@ -%default {"result":"","special":"","rem":""} -/* - * 32-bit binary div/rem operation. Handles special case of op0=minint and - * op1=-1. - */ - /* div/rem vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB - GET_VREG %ecx, %ecx # ecx <- vCC - mov rIBASE, LOCAL0(%esp) - testl %ecx, %ecx - je common_errDivideByZero - movl %eax, %edx - orl %ecx, %edx - testl $$0xFFFFFF00, %edx # If both arguments are less - # than 8-bit and +ve - jz .L${opcode}_8 # Do 8-bit divide - testl $$0xFFFF0000, %edx # If both arguments are less - # than 16-bit and +ve - jz .L${opcode}_16 # Do 16-bit divide - cmpl $$-1, %ecx - jne .L${opcode}_32 - cmpl $$0x80000000, %eax - jne .L${opcode}_32 - movl $special, $result - jmp .L${opcode}_finish -.L${opcode}_32: - cltd - idivl %ecx - jmp .L${opcode}_finish -.L${opcode}_8: - div %cl # 8-bit divide otherwise. - # Remainder in %ah, quotient in %al - .if $rem - movl %eax, %edx - shr $$8, %edx - .else - andl $$0x000000FF, %eax - .endif - jmp .L${opcode}_finish -.L${opcode}_16: - xorl %edx, %edx # Clear %edx before divide - div %cx -.L${opcode}_finish: - SET_VREG $result, rINST - mov LOCAL0(%esp), rIBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/bindiv2addr.S b/runtime/interpreter/mterp/x86/bindiv2addr.S deleted file mode 100644 index e620996c9fba732ca10bea62e37ccc8cfab86b1d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/bindiv2addr.S +++ /dev/null @@ -1,29 +0,0 @@ -%default {"result":"","special":""} -/* - * 32-bit binary div/rem operation. Handles special case of op0=minint and - * op1=-1. - */ - /* div/rem/2addr vA, vB */ - movzx rINSTbl, %ecx # eax <- BA - mov rIBASE, LOCAL0(%esp) - sarl $$4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # eax <- vBB - andb $$0xf, rINSTbl # rINST <- A - GET_VREG %eax, rINST # eax <- vBB - testl %ecx, %ecx - je common_errDivideByZero - cmpl $$-1, %ecx - jne .L${opcode}_continue_div2addr - cmpl $$0x80000000, %eax - jne .L${opcode}_continue_div2addr - movl $special, $result - SET_VREG $result, rINST - mov LOCAL0(%esp), rIBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -.L${opcode}_continue_div2addr: - cltd - idivl %ecx - SET_VREG $result, rINST - mov LOCAL0(%esp), rIBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/bindivLit16.S b/runtime/interpreter/mterp/x86/bindivLit16.S deleted file mode 100644 index be094aee496e172908f4c3f0387722d01766eb50..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/bindivLit16.S +++ /dev/null @@ -1,29 +0,0 @@ -%default {"result":"","special":""} -/* - * 32-bit binary div/rem operation. Handles special case of op0=minint and - * op1=-1. - */ - /* div/rem/lit16 vA, vB, #+CCCC */ - /* Need A in rINST, ssssCCCC in ecx, vB in eax */ - movzbl rINSTbl, %eax # eax <- 000000BA - sarl $$4, %eax # eax <- B - GET_VREG %eax, %eax # eax <- vB - movswl 2(rPC), %ecx # ecx <- ssssCCCC - andb $$0xf, rINSTbl # rINST <- A - testl %ecx, %ecx - je common_errDivideByZero - cmpl $$-1, %ecx - jne .L${opcode}_continue_div - cmpl $$0x80000000, %eax - jne .L${opcode}_continue_div - movl $special, %eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -.L${opcode}_continue_div: - mov rIBASE, LOCAL0(%esp) - cltd - idivl %ecx - SET_VREG $result, rINST - mov LOCAL0(%esp), rIBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/bindivLit8.S b/runtime/interpreter/mterp/x86/bindivLit8.S deleted file mode 100644 index fddb54574d91afa8b86c27c9f357d01656cd90a6..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/bindivLit8.S +++ /dev/null @@ -1,26 +0,0 @@ -%default {"result":"","special":""} -/* - * 32-bit div/rem "lit8" binary operation. Handles special case of - * op0=minint & op1=-1 - */ - /* div/rem/lit8 vAA, vBB, #+CC */ - movzbl 2(rPC), %eax # eax <- BB - movsbl 3(rPC), %ecx # ecx <- ssssssCC - GET_VREG %eax, %eax # eax <- rBB - testl %ecx, %ecx - je common_errDivideByZero - cmpl $$0x80000000, %eax - jne .L${opcode}_continue_div - cmpl $$-1, %ecx - jne .L${opcode}_continue_div - movl $special, %eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -.L${opcode}_continue_div: - mov rIBASE, LOCAL0(%esp) - cltd - idivl %ecx - SET_VREG $result, rINST - mov LOCAL0(%esp), rIBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/binop.S b/runtime/interpreter/mterp/x86/binop.S deleted file mode 100644 index d8952352129bf5f59d5b7a3e0fe1b23c94f599cb..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/binop.S +++ /dev/null @@ -1,17 +0,0 @@ -%default {"result":"%eax"} -/* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = eax op (rFP,%ecx,4)". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int, sub-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB - $instr # ex: addl (rFP,%ecx,4),%eax - SET_VREG $result, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/binop1.S b/runtime/interpreter/mterp/x86/binop1.S deleted file mode 100644 index 5049bb325e009605cbb12a0e1bd7cc45ad377c5f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/binop1.S +++ /dev/null @@ -1,13 +0,0 @@ -%default {"result":"%eax","tmp":"%ecx"} -/* - * Generic 32-bit binary operation in which both operands loaded to - * registers (op0 in eax, op1 in ecx). - */ - /* binop vAA, vBB, vCC */ - movzbl 2(rPC),%eax # eax <- BB - movzbl 3(rPC),%ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB - GET_VREG %ecx, %ecx # eax <- vBB - $instr # ex: addl %ecx,%eax - SET_VREG $result, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/binop2addr.S b/runtime/interpreter/mterp/x86/binop2addr.S deleted file mode 100644 index f126234a40ceefd115a6ec2e11d7f6fe5cd04fad..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/binop2addr.S +++ /dev/null @@ -1,19 +0,0 @@ -%default {"result":"%eax"} -/* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an instruction or a function call. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - movzx rINSTbl, %ecx # ecx <- A+ - sarl $$4, rINST # rINST <- B - GET_VREG %eax, rINST # eax <- vB - andb $$0xf, %cl # ecx <- A - $instr # for ex: addl %eax,(rFP,%ecx,4) - CLEAR_REF %ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/binopLit16.S b/runtime/interpreter/mterp/x86/binopLit16.S deleted file mode 100644 index 2fd59de9361cf90f4f409b84ab52404611744dbd..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/binopLit16.S +++ /dev/null @@ -1,19 +0,0 @@ -%default {"result":"%eax"} -/* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int/lit16, rsub-int, - * and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - movzbl rINSTbl, %eax # eax <- 000000BA - sarl $$4, %eax # eax <- B - GET_VREG %eax, %eax # eax <- vB - movswl 2(rPC), %ecx # ecx <- ssssCCCC - andb $$0xf, rINSTbl # rINST <- A - $instr # for example: addl %ecx, %eax - SET_VREG $result, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/binopLit8.S b/runtime/interpreter/mterp/x86/binopLit8.S deleted file mode 100644 index 67cead27d5bcbcbfcff2cc4b9f8d1dcbb884e324..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/binopLit8.S +++ /dev/null @@ -1,18 +0,0 @@ -%default {"result":"%eax"} -/* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * For: add-int/lit8, rsub-int/lit8 - * and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - movzbl 2(rPC), %eax # eax <- BB - movsbl 3(rPC), %ecx # ecx <- ssssssCC - GET_VREG %eax, %eax # eax <- rBB - $instr # ex: addl %ecx,%eax - SET_VREG $result, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/binopWide.S b/runtime/interpreter/mterp/x86/binopWide.S deleted file mode 100644 index da1293d5b94be087f370f61277d5a4a4af9d7ce7..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/binopWide.S +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Generic 64-bit binary operation. - */ - /* binop vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - movl rIBASE, LOCAL0(%esp) # save rIBASE - GET_VREG rIBASE, %eax # rIBASE <- v[BB+0] - GET_VREG_HIGH %eax, %eax # eax <- v[BB+1] - $instr1 # ex: addl (rFP,%ecx,4),rIBASE - $instr2 # ex: adcl 4(rFP,%ecx,4),%eax - SET_VREG rIBASE, rINST # v[AA+0] <- rIBASE - movl LOCAL0(%esp), rIBASE # restore rIBASE - SET_VREG_HIGH %eax, rINST # v[AA+1] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/binopWide2addr.S b/runtime/interpreter/mterp/x86/binopWide2addr.S deleted file mode 100644 index da816f468bd0761dd77096b2ed417c8602dac0db..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/binopWide2addr.S +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Generic 64-bit binary operation. - */ - /* binop/2addr vA, vB */ - movzbl rINSTbl, %ecx # ecx<- BA - sarl $$4, %ecx # ecx<- B - GET_VREG %eax, %ecx # eax<- v[B+0] - GET_VREG_HIGH %ecx, %ecx # eax<- v[B+1] - andb $$0xF, rINSTbl # rINST<- A - $instr1 # ex: addl %eax,(rFP,rINST,4) - $instr2 # ex: adcl %ecx,4(rFP,rINST,4) - CLEAR_WIDE_REF rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/const.S b/runtime/interpreter/mterp/x86/const.S deleted file mode 100644 index f0cac1a19b3f3625ebdecf696244dbe75ba6a873..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/const.S +++ /dev/null @@ -1,19 +0,0 @@ -%default { "helper":"UndefinedConstHandler" } - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern $helper - EXPORT_PC - movzwl 2(rPC), %eax # eax <- BBBB - movl %eax, OUT_ARG0(%esp) - movl rINST, OUT_ARG1(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) - call SYMBOL($helper) # (index, tgt_reg, shadow_frame, self) - RESTORE_IBASE - testb %al, %al - jnz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/control_flow.S b/runtime/interpreter/mterp/x86/control_flow.S new file mode 100644 index 0000000000000000000000000000000000000000..74b4fad34f813dd64847d8897b18cc3b2a287edf --- /dev/null +++ b/runtime/interpreter/mterp/x86/control_flow.S @@ -0,0 +1,219 @@ +%def bincmp(revcmp=""): +/* + * Generic two-operand compare-and-branch operation. Provide a "revcmp" + * fragment that specifies the *reverse* comparison to perform, e.g. + * for "if-le" you would use "gt". + * + * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le + */ + /* if-cmp vA, vB, +CCCC */ + movzx rINSTbl, %ecx # ecx <- A+ + andb $$0xf, %cl # ecx <- A + GET_VREG %eax, %ecx # eax <- vA + sarl $$4, rINST # rINST <- B + cmpl VREG_ADDRESS(rINST), %eax # compare (vA, vB) + j${revcmp} 1f + movswl 2(rPC), rINST # Get signed branch offset + testl rINST, rINST + jmp MterpCommonTakenBranch +1: + cmpw $$JIT_CHECK_OSR, rPROFILE + je .L_check_not_taken_osr + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def zcmp(revcmp=""): +/* + * Generic one-operand compare-and-branch operation. Provide a "revcmp" + * fragment that specifies the *reverse* comparison to perform, e.g. + * for "if-le" you would use "gt". + * + * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez + */ + /* if-cmp vAA, +BBBB */ + cmpl $$0, VREG_ADDRESS(rINST) # compare (vA, 0) + j${revcmp} 1f + movswl 2(rPC), rINST # fetch signed displacement + testl rINST, rINST + jmp MterpCommonTakenBranch +1: + cmpw $$JIT_CHECK_OSR, rPROFILE + je .L_check_not_taken_osr + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_goto(): +/* + * Unconditional branch, 8-bit offset. + * + * The branch distance is a signed code-unit offset, which we need to + * double to get a byte offset. + */ + /* goto +AA */ + movsbl rINSTbl, rINST # rINST <- ssssssAA + testl rINST, rINST + jmp MterpCommonTakenBranch + +%def op_goto_16(): +/* + * Unconditional branch, 16-bit offset. + * + * The branch distance is a signed code-unit offset, which we need to + * double to get a byte offset. + */ + /* goto/16 +AAAA */ + movswl 2(rPC), rINST # rINST <- ssssAAAA + testl rINST, rINST + jmp MterpCommonTakenBranch + +%def op_goto_32(): +/* + * Unconditional branch, 32-bit offset. + * + * The branch distance is a signed code-unit offset, which we need to + * double to get a byte offset. + * + * Unlike most opcodes, this one is allowed to branch to itself, so + * our "backward branch" test must be "<=0" instead of "<0". Because + * we need the V bit set, we'll use an adds to convert from Dalvik + * offset to byte offset. + */ + /* goto/32 +AAAAAAAA */ + movl 2(rPC), rINST # rINST <- AAAAAAAA + testl rINST, rINST + jmp MterpCommonTakenBranch + +%def op_if_eq(): +% bincmp(revcmp="ne") + +%def op_if_eqz(): +% zcmp(revcmp="ne") + +%def op_if_ge(): +% bincmp(revcmp="l") + +%def op_if_gez(): +% zcmp(revcmp="l") + +%def op_if_gt(): +% bincmp(revcmp="le") + +%def op_if_gtz(): +% zcmp(revcmp="le") + +%def op_if_le(): +% bincmp(revcmp="g") + +%def op_if_lez(): +% zcmp(revcmp="g") + +%def op_if_lt(): +% bincmp(revcmp="ge") + +%def op_if_ltz(): +% zcmp(revcmp="ge") + +%def op_if_ne(): +% bincmp(revcmp="e") + +%def op_if_nez(): +% zcmp(revcmp="e") + +%def op_packed_switch(func="MterpDoPackedSwitch"): +/* + * Handle a packed-switch or sparse-switch instruction. In both cases + * we decode it and hand it off to a helper function. + * + * We don't really expect backward branches in a switch statement, but + * they're perfectly legal, so we check for them here. + * + * for: packed-switch, sparse-switch + */ + /* op vAA, +BBBB */ + movl 2(rPC), %ecx # ecx <- BBBBbbbb + GET_VREG %eax, rINST # eax <- vAA + leal (rPC,%ecx,2), %ecx # ecx <- PC + BBBBbbbb*2 + movl %eax, OUT_ARG1(%esp) # ARG1 <- vAA + movl %ecx, OUT_ARG0(%esp) # ARG0 <- switchData + call SYMBOL($func) + REFRESH_IBASE + testl %eax, %eax + movl %eax, rINST + jmp MterpCommonTakenBranch + +%def op_return(): +/* + * Return a 32-bit value. + * + * for: return, return-object + */ + /* op vAA */ + .extern MterpThreadFenceForConstructor + call SYMBOL(MterpThreadFenceForConstructor) + movl rSELF, %eax + testl $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(%eax) + jz 1f + movl %eax, OUT_ARG0(%esp) + call SYMBOL(MterpSuspendCheck) +1: + GET_VREG %eax, rINST # eax <- vAA + xorl %ecx, %ecx + jmp MterpReturn + +%def op_return_object(): +% op_return() + +%def op_return_void(): + .extern MterpThreadFenceForConstructor + call SYMBOL(MterpThreadFenceForConstructor) + movl rSELF, %eax + testl $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(%eax) + jz 1f + movl %eax, OUT_ARG0(%esp) + call SYMBOL(MterpSuspendCheck) +1: + xorl %eax, %eax + xorl %ecx, %ecx + jmp MterpReturn + +%def op_return_void_no_barrier(): + movl rSELF, %eax + testl $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(%eax) + jz 1f + movl %eax, OUT_ARG0(%esp) + call SYMBOL(MterpSuspendCheck) +1: + xorl %eax, %eax + xorl %ecx, %ecx + jmp MterpReturn + +%def op_return_wide(): +/* + * Return a 64-bit value. + */ + /* return-wide vAA */ + .extern MterpThreadFenceForConstructor + call SYMBOL(MterpThreadFenceForConstructor) + movl rSELF, %eax + testl $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(%eax) + jz 1f + movl %eax, OUT_ARG0(%esp) + call SYMBOL(MterpSuspendCheck) +1: + GET_VREG %eax, rINST # eax <- v[AA+0] + GET_VREG_HIGH %ecx, rINST # ecx <- v[AA+1] + jmp MterpReturn + +%def op_sparse_switch(): +% op_packed_switch(func="MterpDoSparseSwitch") + +%def op_throw(): +/* + * Throw an exception object in the current thread. + */ + /* throw vAA */ + EXPORT_PC + GET_VREG %eax, rINST # eax<- vAA (exception object) + testl %eax, %eax + jz common_errNullObject + movl rSELF,%ecx + movl %eax, THREAD_EXCEPTION_OFFSET(%ecx) + jmp MterpException diff --git a/runtime/interpreter/mterp/x86/cvtfp_int.S b/runtime/interpreter/mterp/x86/cvtfp_int.S deleted file mode 100644 index a8bad639d60491df4a8c4390dc63156802d22bc4..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/cvtfp_int.S +++ /dev/null @@ -1,61 +0,0 @@ -%default {"srcdouble":"1","tgtlong":"1"} -/* On fp to int conversions, Java requires that - * if the result > maxint, it should be clamped to maxint. If it is less - * than minint, it should be clamped to minint. If it is a nan, the result - * should be zero. Further, the rounding mode is to truncate. This model - * differs from what is delivered normally via the x86 fpu, so we have - * to play some games. - */ - /* float/double to int/long vA, vB */ - movzbl rINSTbl, %ecx # ecx <- A+ - sarl $$4, rINST # rINST <- B - .if $srcdouble - fldl VREG_ADDRESS(rINST) # %st0 <- vB - .else - flds VREG_ADDRESS(rINST) # %st0 <- vB - .endif - ftst - fnstcw LOCAL0(%esp) # remember original rounding mode - movzwl LOCAL0(%esp), %eax - movb $$0xc, %ah - movw %ax, LOCAL0+2(%esp) - fldcw LOCAL0+2(%esp) # set "to zero" rounding mode - andb $$0xf, %cl # ecx <- A - .if $tgtlong - fistpll VREG_ADDRESS(%ecx) # convert and store - .else - fistpl VREG_ADDRESS(%ecx) # convert and store - .endif - fldcw LOCAL0(%esp) # restore previous rounding mode - .if $tgtlong - movl $$0x80000000, %eax - xorl VREG_HIGH_ADDRESS(%ecx), %eax - orl VREG_ADDRESS(%ecx), %eax - .else - cmpl $$0x80000000, VREG_ADDRESS(%ecx) - .endif - je .L${opcode}_special_case # fix up result - -.L${opcode}_finish: - xor %eax, %eax - mov %eax, VREG_REF_ADDRESS(%ecx) - .if $tgtlong - mov %eax, VREG_REF_HIGH_ADDRESS(%ecx) - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - -.L${opcode}_special_case: - fnstsw %ax - sahf - jp .L${opcode}_isNaN - adcl $$-1, VREG_ADDRESS(%ecx) - .if $tgtlong - adcl $$-1, VREG_HIGH_ADDRESS(%ecx) - .endif - jmp .L${opcode}_finish -.L${opcode}_isNaN: - movl $$0, VREG_ADDRESS(%ecx) - .if $tgtlong - movl $$0, VREG_HIGH_ADDRESS(%ecx) - .endif - jmp .L${opcode}_finish diff --git a/runtime/interpreter/mterp/x86/entry.S b/runtime/interpreter/mterp/x86/entry.S deleted file mode 100644 index 939dc61d952c0efb0d6627071e1b87cb9bcb3000..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/entry.S +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -/* - * Interpreter entry point. - */ - - .text - ASM_HIDDEN SYMBOL(ExecuteMterpImpl) - .global SYMBOL(ExecuteMterpImpl) - FUNCTION_TYPE(ExecuteMterpImpl) - -/* - * On entry: - * 0 Thread* self - * 1 insns_ - * 2 ShadowFrame - * 3 JValue* result_register - * - */ - -SYMBOL(ExecuteMterpImpl): - .cfi_startproc - .cfi_def_cfa esp, 4 - - /* Spill callee save regs */ - PUSH %ebp - PUSH %edi - PUSH %esi - PUSH %ebx - - /* Allocate frame */ - subl $$FRAME_SIZE, %esp - .cfi_adjust_cfa_offset FRAME_SIZE - - /* Load ShadowFrame pointer */ - movl IN_ARG2(%esp), %edx - - /* Remember the return register */ - movl IN_ARG3(%esp), %eax - movl %eax, SHADOWFRAME_RESULT_REGISTER_OFFSET(%edx) - - /* Remember the code_item */ - movl IN_ARG1(%esp), %ecx - movl %ecx, SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET(%edx) - - /* set up "named" registers */ - movl SHADOWFRAME_NUMBER_OF_VREGS_OFFSET(%edx), %eax - leal SHADOWFRAME_VREGS_OFFSET(%edx), rFP - leal (rFP, %eax, 4), rREFS - movl SHADOWFRAME_DEX_PC_OFFSET(%edx), %eax - lea (%ecx, %eax, 2), rPC - CFI_DEFINE_DEX_PC_WITH_OFFSET(CFI_TMP, CFI_DEX, 0) - EXPORT_PC - - /* Set up for backwards branches & osr profiling */ - movl OFF_FP_METHOD(rFP), %eax - movl %eax, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - movl rSELF, %eax - movl %eax, OUT_ARG2(%esp) - call SYMBOL(MterpSetUpHotnessCountdown) - - /* Starting ibase */ - REFRESH_IBASE - - /* start executing the instruction at rPC */ - FETCH_INST - GOTO_NEXT - /* NOTE: no fallthrough */ diff --git a/runtime/interpreter/mterp/x86/fallback.S b/runtime/interpreter/mterp/x86/fallback.S deleted file mode 100644 index 8d61166f63d57a950db9bb1e3bceef3edb6a8374..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/fallback.S +++ /dev/null @@ -1,3 +0,0 @@ -/* Transfer stub to alternate interpreter */ - jmp MterpFallback - diff --git a/runtime/interpreter/mterp/x86/field.S b/runtime/interpreter/mterp/x86/field.S deleted file mode 100644 index 8432c744ea6944b388b3935757c876b864a0178c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/field.S +++ /dev/null @@ -1,17 +0,0 @@ -%default { } - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern $helper - REFRESH_INST ${opnum} # fix rINST to include opcode - movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst - movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) # arg3: Thread* self - call SYMBOL($helper) - testb %al, %al - jz MterpPossibleException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/floating_point.S b/runtime/interpreter/mterp/x86/floating_point.S new file mode 100644 index 0000000000000000000000000000000000000000..3de1fc8f19e7b78e5bdaf0b223273ba368e96123 --- /dev/null +++ b/runtime/interpreter/mterp/x86/floating_point.S @@ -0,0 +1,236 @@ +%def fpcmp(suff="d", nanval="pos"): +/* + * Compare two floating-point values. Puts 0, 1, or -1 into the + * destination register based on the results of the comparison. + * + * int compare(x, y) { + * if (x == y) { + * return 0; + * } else if (x < y) { + * return -1; + * } else if (x > y) { + * return 1; + * } else { + * return nanval ? 1 : -1; + * } + * } + */ + /* op vAA, vBB, vCC */ + movzbl 3(rPC), %ecx # ecx<- CC + movzbl 2(rPC), %eax # eax<- BB + movs${suff} VREG_ADDRESS(%eax), %xmm0 + xor %eax, %eax + ucomis${suff} VREG_ADDRESS(%ecx), %xmm0 + jp .L${opcode}_nan_is_${nanval} + je .L${opcode}_finish + jb .L${opcode}_less +.L${opcode}_nan_is_pos: + incl %eax + jmp .L${opcode}_finish +.L${opcode}_nan_is_neg: +.L${opcode}_less: + decl %eax +.L${opcode}_finish: + SET_VREG %eax, rINST + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def fpcvt(instr="", load="", store="", wide="0"): +/* + * Generic 32-bit FP conversion operation. + */ + /* unop vA, vB */ + movzbl rINSTbl, %ecx # ecx <- A+ + sarl $$4, rINST # rINST <- B + $load VREG_ADDRESS(rINST) # %st0 <- vB + andb $$0xf, %cl # ecx <- A + $instr + $store VREG_ADDRESS(%ecx) # vA <- %st0 + .if $wide + CLEAR_WIDE_REF %ecx + .else + CLEAR_REF %ecx + .endif + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def sseBinop(instr="", suff=""): + movzbl 2(rPC), %ecx # ecx <- BB + movzbl 3(rPC), %eax # eax <- CC + movs${suff} VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src + ${instr}${suff} VREG_ADDRESS(%eax), %xmm0 + movs${suff} %xmm0, VREG_ADDRESS(rINST) # vAA <- %xmm0 + pxor %xmm0, %xmm0 + movs${suff} %xmm0, VREG_REF_ADDRESS(rINST) # clear ref + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def sseBinop2Addr(instr="", suff=""): + movzx rINSTbl, %ecx # ecx <- A+ + andl $$0xf, %ecx # ecx <- A + movs${suff} VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src + sarl $$4, rINST # rINST<- B + ${instr}${suff} VREG_ADDRESS(rINST), %xmm0 + movs${suff} %xmm0, VREG_ADDRESS(%ecx) # vAA<- %xmm0 + pxor %xmm0, %xmm0 + movs${suff} %xmm0, VREG_REF_ADDRESS(rINST) # clear ref + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_add_double(): +% sseBinop(instr="adds", suff="d") + +%def op_add_double_2addr(): +% sseBinop2Addr(instr="adds", suff="d") + +%def op_add_float(): +% sseBinop(instr="adds", suff="s") + +%def op_add_float_2addr(): +% sseBinop2Addr(instr="adds", suff="s") + +%def op_cmpg_double(): +% fpcmp(suff="d", nanval="pos") + +%def op_cmpg_float(): +% fpcmp(suff="s", nanval="pos") + +%def op_cmpl_double(): +% fpcmp(suff="d", nanval="neg") + +%def op_cmpl_float(): +% fpcmp(suff="s", nanval="neg") + +%def op_div_double(): +% sseBinop(instr="divs", suff="d") + +%def op_div_double_2addr(): +% sseBinop2Addr(instr="divs", suff="d") + +%def op_div_float(): +% sseBinop(instr="divs", suff="s") + +%def op_div_float_2addr(): +% sseBinop2Addr(instr="divs", suff="s") + +%def op_double_to_float(): +% fpcvt(load="fldl", store="fstps") + +%def op_double_to_int(): +% cvtfp_int(srcdouble="1", tgtlong="0") + +%def op_double_to_long(): +% cvtfp_int(srcdouble="1", tgtlong="1") + +%def op_float_to_double(): +% fpcvt(load="flds", store="fstpl", wide="1") + +%def op_float_to_int(): +% cvtfp_int(srcdouble="0", tgtlong="0") + +%def op_float_to_long(): +% cvtfp_int(srcdouble="0", tgtlong="1") + +%def op_int_to_double(): +% fpcvt(load="fildl", store="fstpl", wide="1") + +%def op_int_to_float(): +% fpcvt(load="fildl", store="fstps") + +%def op_long_to_double(): +% fpcvt(load="fildll", store="fstpl", wide="1") + +%def op_long_to_float(): +% fpcvt(load="fildll", store="fstps") + +%def op_mul_double(): +% sseBinop(instr="muls", suff="d") + +%def op_mul_double_2addr(): +% sseBinop2Addr(instr="muls", suff="d") + +%def op_mul_float(): +% sseBinop(instr="muls", suff="s") + +%def op_mul_float_2addr(): +% sseBinop2Addr(instr="muls", suff="s") + +%def op_neg_double(): +% fpcvt(instr="fchs", load="fldl", store="fstpl", wide="1") + +%def op_neg_float(): +% fpcvt(instr="fchs", load="flds", store="fstps") + +%def op_rem_double(): + /* rem_double vAA, vBB, vCC */ + movzbl 3(rPC), %ecx # ecx <- BB + movzbl 2(rPC), %eax # eax <- CC + fldl VREG_ADDRESS(%ecx) # %st1 <- fp[vBB] + fldl VREG_ADDRESS(%eax) # %st0 <- fp[vCC] +1: + fprem + fstsw %ax + sahf + jp 1b + fstp %st(1) + fstpl VREG_ADDRESS(rINST) # fp[vAA] <- %st + CLEAR_WIDE_REF rINST + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_rem_double_2addr(): + /* rem_double/2addr vA, vB */ + movzx rINSTbl, %ecx # ecx <- A+ + sarl $$4, rINST # rINST <- B + fldl VREG_ADDRESS(rINST) # vB to fp stack + andb $$0xf, %cl # ecx <- A + fldl VREG_ADDRESS(%ecx) # vA to fp stack +1: + fprem + fstsw %ax + sahf + jp 1b + fstp %st(1) + fstpl VREG_ADDRESS(%ecx) # %st to vA + CLEAR_WIDE_REF %ecx + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_rem_float(): + /* rem_float vAA, vBB, vCC */ + movzbl 3(rPC), %ecx # ecx <- BB + movzbl 2(rPC), %eax # eax <- CC + flds VREG_ADDRESS(%ecx) # vBB to fp stack + flds VREG_ADDRESS(%eax) # vCC to fp stack +1: + fprem + fstsw %ax + sahf + jp 1b + fstp %st(1) + fstps VREG_ADDRESS(rINST) # %st to vAA + CLEAR_REF rINST + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_rem_float_2addr(): + /* rem_float/2addr vA, vB */ + movzx rINSTbl, %ecx # ecx <- A+ + sarl $$4, rINST # rINST <- B + flds VREG_ADDRESS(rINST) # vB to fp stack + andb $$0xf, %cl # ecx <- A + flds VREG_ADDRESS(%ecx) # vA to fp stack +1: + fprem + fstsw %ax + sahf + jp 1b + fstp %st(1) + fstps VREG_ADDRESS(%ecx) # %st to vA + CLEAR_REF %ecx + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_sub_double(): +% sseBinop(instr="subs", suff="d") + +%def op_sub_double_2addr(): +% sseBinop2Addr(instr="subs", suff="d") + +%def op_sub_float(): +% sseBinop(instr="subs", suff="s") + +%def op_sub_float_2addr(): +% sseBinop2Addr(instr="subs", suff="s") diff --git a/runtime/interpreter/mterp/x86/footer.S b/runtime/interpreter/mterp/x86/footer.S deleted file mode 100644 index 0b08cf98a379972929ebceb6225ccf123a1bcc55..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/footer.S +++ /dev/null @@ -1,325 +0,0 @@ -/* - * =========================================================================== - * Common subroutines and data - * =========================================================================== - */ - - .text - .align 2 - -/* - * We've detected a condition that will result in an exception, but the exception - * has not yet been thrown. Just bail out to the reference interpreter to deal with it. - * TUNING: for consistency, we may want to just go ahead and handle these here. - */ -common_errDivideByZero: - EXPORT_PC -#if MTERP_LOGGING - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - lea OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - call SYMBOL(MterpLogDivideByZeroException) -#endif - jmp MterpCommonFallback - -common_errArrayIndex: - EXPORT_PC -#if MTERP_LOGGING - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - lea OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - call SYMBOL(MterpLogArrayIndexException) -#endif - jmp MterpCommonFallback - -common_errNegativeArraySize: - EXPORT_PC -#if MTERP_LOGGING - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - lea OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - call SYMBOL(MterpLogNegativeArraySizeException) -#endif - jmp MterpCommonFallback - -common_errNoSuchMethod: - EXPORT_PC -#if MTERP_LOGGING - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - lea OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - call SYMBOL(MterpLogNoSuchMethodException) -#endif - jmp MterpCommonFallback - -common_errNullObject: - EXPORT_PC -#if MTERP_LOGGING - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - lea OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - call SYMBOL(MterpLogNullObjectException) -#endif - jmp MterpCommonFallback - -common_exceptionThrown: - EXPORT_PC -#if MTERP_LOGGING - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - lea OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG0(%esp) - call SYMBOL(MterpLogExceptionThrownException) -#endif - jmp MterpCommonFallback - -MterpSuspendFallback: - EXPORT_PC -#if MTERP_LOGGING - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - lea OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG0(%esp) - movl THREAD_FLAGS_OFFSET(%eax), %eax - movl %eax, OUT_ARG2(%esp) - call SYMBOL(MterpLogSuspendFallback) -#endif - jmp MterpCommonFallback - -/* - * If we're here, something is out of the ordinary. If there is a pending - * exception, handle it. Otherwise, roll back and retry with the reference - * interpreter. - */ -MterpPossibleException: - movl rSELF, %eax - testl $$-1, THREAD_EXCEPTION_OFFSET(%eax) - jz MterpFallback - /* intentional fallthrough - handle pending exception. */ - -/* - * On return from a runtime helper routine, we've found a pending exception. - * Can we handle it here - or need to bail out to caller? - * - */ -MterpException: - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - lea OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - call SYMBOL(MterpHandleException) - testb %al, %al - jz MterpExceptionReturn - movl OFF_FP_DEX_INSTRUCTIONS(rFP), %eax - movl OFF_FP_DEX_PC(rFP), %ecx - lea (%eax, %ecx, 2), rPC - movl rPC, OFF_FP_DEX_PC_PTR(rFP) - /* Do we need to switch interpreters? */ - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - /* resume execution at catch block */ - REFRESH_IBASE - FETCH_INST - GOTO_NEXT - /* NOTE: no fallthrough */ - -/* - * Common handling for branches with support for Jit profiling. - * On entry: - * rINST <= signed offset - * condition bits <= set to establish sign of offset (use "NoFlags" entry if not) - * - * We have quite a few different cases for branch profiling, OSR detection and - * suspend check support here. - * - * Taken backward branches: - * If profiling active, do hotness countdown and report if we hit zero. - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * Is there a pending suspend request? If so, suspend. - * - * Taken forward branches and not-taken backward branches: - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * - * Our most common case is expected to be a taken backward branch with active jit profiling, - * but no full OSR check and no pending suspend request. - * Next most common case is not-taken branch with no full OSR check. - * - */ -MterpCommonTakenBranch: - jg .L_forward_branch # don't add forward branches to hotness -/* - * We need to subtract 1 from positive values and we should not see 0 here, - * so we may use the result of the comparison with -1. - */ -#if JIT_CHECK_OSR != -1 -# error "JIT_CHECK_OSR must be -1." -#endif - cmpw $$JIT_CHECK_OSR, rPROFILE - je .L_osr_check - decw rPROFILE - je .L_add_batch # counted down to zero - report -.L_resume_backward_branch: - movl rSELF, %eax - testl $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(%eax) - leal (rPC, rINST, 2), rPC - FETCH_INST - jnz .L_suspend_request_pending - REFRESH_IBASE - GOTO_NEXT - -.L_suspend_request_pending: - EXPORT_PC - movl %eax, OUT_ARG0(%esp) # rSELF in eax - call SYMBOL(MterpSuspendCheck) # (self) - testb %al, %al - jnz MterpFallback - REFRESH_IBASE # might have changed during suspend - GOTO_NEXT - -.L_no_count_backwards: - cmpw $$JIT_CHECK_OSR, rPROFILE # possible OSR re-entry? - jne .L_resume_backward_branch -.L_osr_check: - EXPORT_PC - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - movl rINST, OUT_ARG2(%esp) - call SYMBOL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) - testb %al, %al - jz .L_resume_backward_branch - jmp MterpOnStackReplacement - -.L_forward_branch: - cmpw $$JIT_CHECK_OSR, rPROFILE # possible OSR re-entry? - je .L_check_osr_forward -.L_resume_forward_branch: - leal (rPC, rINST, 2), rPC - FETCH_INST - GOTO_NEXT - -.L_check_osr_forward: - EXPORT_PC - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - movl rINST, OUT_ARG2(%esp) - call SYMBOL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) - testb %al, %al - REFRESH_IBASE - jz .L_resume_forward_branch - jmp MterpOnStackReplacement - -.L_add_batch: - movl OFF_FP_METHOD(rFP), %eax - movl %eax, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - movl rSELF, %eax - movl %eax, OUT_ARG2(%esp) - call SYMBOL(MterpAddHotnessBatch) # (method, shadow_frame, self) - jmp .L_no_count_backwards - -/* - * Entered from the conditional branch handlers when OSR check request active on - * not-taken path. All Dalvik not-taken conditional branch offsets are 2. - */ -.L_check_not_taken_osr: - EXPORT_PC - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - movl $$2, OUT_ARG2(%esp) - call SYMBOL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) - testb %al, %al - REFRESH_IBASE - jnz MterpOnStackReplacement - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* - * On-stack replacement has happened, and now we've returned from the compiled method. - */ -MterpOnStackReplacement: -#if MTERP_LOGGING - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - lea OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - movl rINST, OUT_ARG2(%esp) - call SYMBOL(MterpLogOSR) -#endif - movl $$1, %eax - jmp MterpDone - -/* - * Bail out to reference interpreter. - */ -MterpFallback: - EXPORT_PC -#if MTERP_LOGGING - movl rSELF, %eax - movl %eax, OUT_ARG0(%esp) - lea OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - call SYMBOL(MterpLogFallback) -#endif -MterpCommonFallback: - xor %eax, %eax - jmp MterpDone - -/* - * On entry: - * uint32_t* rFP (should still be live, pointer to base of vregs) - */ -MterpExceptionReturn: - movl $$1, %eax - jmp MterpDone -MterpReturn: - movl OFF_FP_RESULT_REGISTER(rFP), %edx - movl %eax, (%edx) - movl %ecx, 4(%edx) - mov $$1, %eax -MterpDone: -/* - * At this point, we expect rPROFILE to be non-zero. If negative, hotness is disabled or we're - * checking for OSR. If greater than zero, we might have unreported hotness to register - * (the difference between the ending rPROFILE and the cached hotness counter). rPROFILE - * should only reach zero immediately after a hotness decrement, and is then reset to either - * a negative special state or the new non-zero countdown value. - */ - cmpw $$0, rPROFILE - jle MRestoreFrame # if > 0, we may have some counts to report. - - movl %eax, rINST # stash return value - /* Report cached hotness counts */ - movl OFF_FP_METHOD(rFP), %eax - movl %eax, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %ecx - movl %ecx, OUT_ARG1(%esp) - movl rSELF, %eax - movl %eax, OUT_ARG2(%esp) - call SYMBOL(MterpAddHotnessBatch) # (method, shadow_frame, self) - movl rINST, %eax # restore return value - - /* pop up frame */ -MRestoreFrame: - addl $$FRAME_SIZE, %esp - .cfi_adjust_cfa_offset -FRAME_SIZE - - /* Restore callee save register */ - POP %ebx - POP %esi - POP %edi - POP %ebp - ret - .cfi_endproc - SIZE(ExecuteMterpImpl,ExecuteMterpImpl) diff --git a/runtime/interpreter/mterp/x86/fpcmp.S b/runtime/interpreter/mterp/x86/fpcmp.S deleted file mode 100644 index 5f9eef9d097c641cbcb6dc33344f712e2bc05bf1..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/fpcmp.S +++ /dev/null @@ -1,35 +0,0 @@ -%default {"suff":"d","nanval":"pos"} -/* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * int compare(x, y) { - * if (x == y) { - * return 0; - * } else if (x < y) { - * return -1; - * } else if (x > y) { - * return 1; - * } else { - * return nanval ? 1 : -1; - * } - * } - */ - /* op vAA, vBB, vCC */ - movzbl 3(rPC), %ecx # ecx<- CC - movzbl 2(rPC), %eax # eax<- BB - movs${suff} VREG_ADDRESS(%eax), %xmm0 - xor %eax, %eax - ucomis${suff} VREG_ADDRESS(%ecx), %xmm0 - jp .L${opcode}_nan_is_${nanval} - je .L${opcode}_finish - jb .L${opcode}_less -.L${opcode}_nan_is_pos: - incl %eax - jmp .L${opcode}_finish -.L${opcode}_nan_is_neg: -.L${opcode}_less: - decl %eax -.L${opcode}_finish: - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/fpcvt.S b/runtime/interpreter/mterp/x86/fpcvt.S deleted file mode 100644 index 780828518fbc0660d025542febdff7834bee5445..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/fpcvt.S +++ /dev/null @@ -1,17 +0,0 @@ -%default {"instr":"","load":"","store":"","wide":"0"} -/* - * Generic 32-bit FP conversion operation. - */ - /* unop vA, vB */ - movzbl rINSTbl, %ecx # ecx <- A+ - sarl $$4, rINST # rINST <- B - $load VREG_ADDRESS(rINST) # %st0 <- vB - andb $$0xf, %cl # ecx <- A - $instr - $store VREG_ADDRESS(%ecx) # vA <- %st0 - .if $wide - CLEAR_WIDE_REF %ecx - .else - CLEAR_REF %ecx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/header.S b/runtime/interpreter/mterp/x86/header.S deleted file mode 100644 index a79db27abf1b0d21efeb8fc7eb3768c093413873..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/header.S +++ /dev/null @@ -1,316 +0,0 @@ -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - Art assembly interpreter notes: - - First validate assembly code by implementing ExecuteXXXImpl() style body (doesn't - handle invoke, allows higher-level code to create frame & shadow frame. - - Once that's working, support direct entry code & eliminate shadow frame (and - excess locals allocation. - - Some (hopefully) temporary ugliness. We'll treat rFP as pointing to the - base of the vreg array within the shadow frame. Access the other fields, - dex_pc_, method_ and number_of_vregs_ via negative offsets. For now, we'll continue - the shadow frame mechanism of double-storing object references - via rFP & - number_of_vregs_. - - */ - -/* -x86 ABI general notes: - -Caller save set: - eax, edx, ecx, st(0)-st(7) -Callee save set: - ebx, esi, edi, ebp -Return regs: - 32-bit in eax - 64-bit in edx:eax (low-order 32 in eax) - fp on top of fp stack st(0) - -Parameters passed on stack, pushed right-to-left. On entry to target, first -parm is at 4(%esp). Traditional entry code is: - -functEntry: - push %ebp # save old frame pointer - mov %ebp,%esp # establish new frame pointer - sub FrameSize,%esp # Allocate storage for spill, locals & outs - -Once past the prologue, arguments are referenced at ((argno + 2)*4)(%ebp) - -Stack must be 16-byte aligned to support SSE in native code. - -If we're not doing variable stack allocation (alloca), the frame pointer can be -eliminated and all arg references adjusted to be esp relative. -*/ - -/* -Mterp and x86 notes: - -Some key interpreter variables will be assigned to registers. - - nick reg purpose - rPC esi interpreted program counter, used for fetching instructions - rFP edi interpreted frame pointer, used for accessing locals and args - rINSTw bx first 16-bit code of current instruction - rINSTbl bl opcode portion of instruction word - rINSTbh bh high byte of inst word, usually contains src/tgt reg names - rIBASE edx base of instruction handler table - rREFS ebp base of object references in shadow frame. - -Notes: - o High order 16 bits of ebx must be zero on entry to handler - o rPC, rFP, rINSTw/rINSTbl valid on handler entry and exit - o eax and ecx are scratch, rINSTw/ebx sometimes scratch - -Macros are provided for common operations. Each macro MUST emit only -one instruction to make instruction-counting easier. They MUST NOT alter -unspecified registers or condition codes. -*/ - -/* - * This is a #include, not a %include, because we want the C pre-processor - * to expand the macros into assembler assignment statements. - */ -#include "asm_support.h" -#include "interpreter/cfi_asm_support.h" - -/* - * Handle mac compiler specific - */ -#if defined(__APPLE__) - #define MACRO_LITERAL(value) $$(value) - #define FUNCTION_TYPE(name) - #define OBJECT_TYPE(name) - #define SIZE(start,end) - // Mac OS' symbols have an _ prefix. - #define SYMBOL(name) _ ## name - #define ASM_HIDDEN .private_extern -#else - #define MACRO_LITERAL(value) $$value - #define FUNCTION_TYPE(name) .type name, @function - #define OBJECT_TYPE(name) .type name, @object - #define SIZE(start,end) .size start, .-end - #define SYMBOL(name) name - #define ASM_HIDDEN .hidden -#endif - -.macro PUSH _reg - pushl \_reg - .cfi_adjust_cfa_offset 4 - .cfi_rel_offset \_reg, 0 -.endm - -.macro POP _reg - popl \_reg - .cfi_adjust_cfa_offset -4 - .cfi_restore \_reg -.endm - -/* - * Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs. So, - * to access other shadow frame fields, we need to use a backwards offset. Define those here. - */ -#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) -#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) -#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) -#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) -#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) -#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) -#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) -#define OFF_FP_DEX_INSTRUCTIONS OFF_FP(SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET) -#define OFF_FP_COUNTDOWN_OFFSET OFF_FP(SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET) -#define OFF_FP_SHADOWFRAME OFF_FP(0) - -/* Frame size must be 16-byte aligned. - * Remember about 4 bytes for return address + 4 * 4 for spills - */ -#define FRAME_SIZE 28 - -/* Frame diagram while executing ExecuteMterpImpl, high to low addresses */ -#define IN_ARG3 (FRAME_SIZE + 16 + 16) -#define IN_ARG2 (FRAME_SIZE + 16 + 12) -#define IN_ARG1 (FRAME_SIZE + 16 + 8) -#define IN_ARG0 (FRAME_SIZE + 16 + 4) -/* Spill offsets relative to %esp */ -#define LOCAL0 (FRAME_SIZE - 4) -#define LOCAL1 (FRAME_SIZE - 8) -#define LOCAL2 (FRAME_SIZE - 12) -/* Out Arg offsets, relative to %esp */ -#define OUT_ARG3 ( 12) -#define OUT_ARG2 ( 8) -#define OUT_ARG1 ( 4) -#define OUT_ARG0 ( 0) /* <- ExecuteMterpImpl esp + 0 */ - -/* During bringup, we'll use the shadow frame model instead of rFP */ -/* single-purpose registers, given names for clarity */ -#define rSELF IN_ARG0(%esp) -#define rPC %esi -#define CFI_DEX 6 // DWARF register number of the register holding dex-pc (esi). -#define CFI_TMP 0 // DWARF register number of the first argument register (eax). -#define rFP %edi -#define rINST %ebx -#define rINSTw %bx -#define rINSTbh %bh -#define rINSTbl %bl -#define rIBASE %edx -#define rREFS %ebp -#define rPROFILE OFF_FP_COUNTDOWN_OFFSET(rFP) - -#define MTERP_LOGGING 0 - -/* - * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must - * be done *before* something throws. - * - * It's okay to do this more than once. - * - * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped - * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction - * offset into the code_items_[] array. For effiency, we will "export" the - * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC - * to convert to a dex pc when needed. - */ -.macro EXPORT_PC - movl rPC, OFF_FP_DEX_PC_PTR(rFP) -.endm - -/* - * Refresh handler table. - */ -.macro REFRESH_IBASE - movl rSELF, rIBASE - movl THREAD_CURRENT_IBASE_OFFSET(rIBASE), rIBASE -.endm - -/* - * Refresh handler table. - * IBase handles uses the caller save register so we must restore it after each call. - * Also it is used as a result of some 64-bit operations (like imul) and we should - * restore it in such cases also. - * - * TODO: Consider spilling the IBase instead of restoring it from Thread structure. - */ -.macro RESTORE_IBASE - movl rSELF, rIBASE - movl THREAD_CURRENT_IBASE_OFFSET(rIBASE), rIBASE -.endm - -/* - * If rSELF is already loaded then we can use it from known reg. - */ -.macro RESTORE_IBASE_FROM_SELF _reg - movl THREAD_CURRENT_IBASE_OFFSET(\_reg), rIBASE -.endm - -/* - * Refresh rINST. - * At enter to handler rINST does not contain the opcode number. - * However some utilities require the full value, so this macro - * restores the opcode number. - */ -.macro REFRESH_INST _opnum - movb rINSTbl, rINSTbh - movb MACRO_LITERAL(\_opnum), rINSTbl -.endm - -/* - * Fetch the next instruction from rPC into rINSTw. Does not advance rPC. - */ -.macro FETCH_INST - movzwl (rPC), rINST -.endm - -/* - * Remove opcode from rINST, compute the address of handler and jump to it. - */ -.macro GOTO_NEXT - movzx rINSTbl,%eax - movzbl rINSTbh,rINST - shll MACRO_LITERAL(${handler_size_bits}), %eax - addl rIBASE, %eax - jmp *%eax -.endm - -/* - * Advance rPC by instruction count. - */ -.macro ADVANCE_PC _count - leal 2*\_count(rPC), rPC -.endm - -/* - * Advance rPC by instruction count, fetch instruction and jump to handler. - */ -.macro ADVANCE_PC_FETCH_AND_GOTO_NEXT _count - ADVANCE_PC \_count - FETCH_INST - GOTO_NEXT -.endm - -/* - * Get/set the 32-bit value from a Dalvik register. - */ -#define VREG_ADDRESS(_vreg) (rFP,_vreg,4) -#define VREG_HIGH_ADDRESS(_vreg) 4(rFP,_vreg,4) -#define VREG_REF_ADDRESS(_vreg) (rREFS,_vreg,4) -#define VREG_REF_HIGH_ADDRESS(_vreg) 4(rREFS,_vreg,4) - -.macro GET_VREG _reg _vreg - movl (rFP,\_vreg,4), \_reg -.endm - -/* Read wide value to xmm. */ -.macro GET_WIDE_FP_VREG _reg _vreg - movq (rFP,\_vreg,4), \_reg -.endm - -.macro SET_VREG _reg _vreg - movl \_reg, (rFP,\_vreg,4) - movl MACRO_LITERAL(0), (rREFS,\_vreg,4) -.endm - -/* Write wide value from xmm. xmm is clobbered. */ -.macro SET_WIDE_FP_VREG _reg _vreg - movq \_reg, (rFP,\_vreg,4) - pxor \_reg, \_reg - movq \_reg, (rREFS,\_vreg,4) -.endm - -.macro SET_VREG_OBJECT _reg _vreg - movl \_reg, (rFP,\_vreg,4) - movl \_reg, (rREFS,\_vreg,4) -.endm - -.macro GET_VREG_HIGH _reg _vreg - movl 4(rFP,\_vreg,4), \_reg -.endm - -.macro SET_VREG_HIGH _reg _vreg - movl \_reg, 4(rFP,\_vreg,4) - movl MACRO_LITERAL(0), 4(rREFS,\_vreg,4) -.endm - -.macro CLEAR_REF _vreg - movl MACRO_LITERAL(0), (rREFS,\_vreg,4) -.endm - -.macro CLEAR_WIDE_REF _vreg - movl MACRO_LITERAL(0), (rREFS,\_vreg,4) - movl MACRO_LITERAL(0), 4(rREFS,\_vreg,4) -.endm diff --git a/runtime/interpreter/mterp/x86/instruction_end.S b/runtime/interpreter/mterp/x86/instruction_end.S deleted file mode 100644 index 94587f83b7ece94acc81c162b24242ca73dbf6a8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/instruction_end.S +++ /dev/null @@ -1,5 +0,0 @@ - - OBJECT_TYPE(artMterpAsmInstructionEnd) - ASM_HIDDEN SYMBOL(artMterpAsmInstructionEnd) - .global SYMBOL(artMterpAsmInstructionEnd) -SYMBOL(artMterpAsmInstructionEnd): diff --git a/runtime/interpreter/mterp/x86/instruction_end_alt.S b/runtime/interpreter/mterp/x86/instruction_end_alt.S deleted file mode 100644 index 7757bce9a7eba09c81d13bb34be3356a1c0813d8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/instruction_end_alt.S +++ /dev/null @@ -1,5 +0,0 @@ - - OBJECT_TYPE(artMterpAsmAltInstructionEnd) - ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionEnd) - .global SYMBOL(artMterpAsmAltInstructionEnd) -SYMBOL(artMterpAsmAltInstructionEnd): diff --git a/runtime/interpreter/mterp/x86/instruction_end_sister.S b/runtime/interpreter/mterp/x86/instruction_end_sister.S deleted file mode 100644 index 8eb79accdf82bd257721ba37a04ed9319d23c36b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/instruction_end_sister.S +++ /dev/null @@ -1,5 +0,0 @@ - - OBJECT_TYPE(artMterpAsmSisterEnd) - ASM_HIDDEN SYMBOL(artMterpAsmSisterEnd) - .global SYMBOL(artMterpAsmSisterEnd) -SYMBOL(artMterpAsmSisterEnd): diff --git a/runtime/interpreter/mterp/x86/instruction_start.S b/runtime/interpreter/mterp/x86/instruction_start.S deleted file mode 100644 index 5d29a8199373e2abfc49b32baf183107a96b3c1d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/instruction_start.S +++ /dev/null @@ -1,6 +0,0 @@ - - OBJECT_TYPE(artMterpAsmInstructionStart) - ASM_HIDDEN SYMBOL(artMterpAsmInstructionStart) - .global SYMBOL(artMterpAsmInstructionStart) -SYMBOL(artMterpAsmInstructionStart) = .L_op_nop - .text diff --git a/runtime/interpreter/mterp/x86/instruction_start_alt.S b/runtime/interpreter/mterp/x86/instruction_start_alt.S deleted file mode 100644 index 8dcf5bfaf95be22f84f4e8670a19a56d7b9a2d46..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/instruction_start_alt.S +++ /dev/null @@ -1,6 +0,0 @@ - - OBJECT_TYPE(artMterpAsmAltInstructionStart) - ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionStart) - .global SYMBOL(artMterpAsmAltInstructionStart) - .text -SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop diff --git a/runtime/interpreter/mterp/x86/instruction_start_sister.S b/runtime/interpreter/mterp/x86/instruction_start_sister.S deleted file mode 100644 index 796e98b09a4ca70adac9aa64992c0928fce7229e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/instruction_start_sister.S +++ /dev/null @@ -1,7 +0,0 @@ - - OBJECT_TYPE(artMterpAsmSisterStart) - ASM_HIDDEN SYMBOL(artMterpAsmSisterStart) - .global SYMBOL(artMterpAsmSisterStart) - .text - .balign 4 -SYMBOL(artMterpAsmSisterStart): diff --git a/runtime/interpreter/mterp/x86/invoke.S b/runtime/interpreter/mterp/x86/invoke.S index c23053becb94cbb05aaf4b303481664afb50e2ee..587c4cfd63a653f6aea1fc8ebd41aea3533ca7b7 100644 --- a/runtime/interpreter/mterp/x86/invoke.S +++ b/runtime/interpreter/mterp/x86/invoke.S @@ -1,4 +1,4 @@ -%default { "helper":"UndefinedInvokeHandler" } +%def invoke(helper="UndefinedInvokeHandler"): /* * Generic invoke handler wrapper. */ @@ -23,3 +23,99 @@ RESTORE_IBASE FETCH_INST GOTO_NEXT + +%def invoke_polymorphic(helper="UndefinedInvokeHandler"): + /* + * invoke-polymorphic handler wrapper. + */ + /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ + /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ + .extern $helper + EXPORT_PC + movl rSELF, %ecx + movl %ecx, OUT_ARG0(%esp) + leal OFF_FP_SHADOWFRAME(rFP), %eax + movl %eax, OUT_ARG1(%esp) + movl rPC, OUT_ARG2(%esp) + REFRESH_INST ${opnum} + movl rINST, OUT_ARG3(%esp) + call SYMBOL($helper) + testb %al, %al + jz MterpException + ADVANCE_PC 4 + call SYMBOL(MterpShouldSwitchInterpreters) + testb %al, %al + jnz MterpFallback + RESTORE_IBASE + FETCH_INST + GOTO_NEXT + +%def op_invoke_custom(): +% invoke(helper="MterpInvokeCustom") + +%def op_invoke_custom_range(): +% invoke(helper="MterpInvokeCustomRange") + +%def op_invoke_direct(): +% invoke(helper="MterpInvokeDirect") + +%def op_invoke_direct_range(): +% invoke(helper="MterpInvokeDirectRange") + +%def op_invoke_interface(): +% invoke(helper="MterpInvokeInterface") +/* + * Handle an interface method call. + * + * for: invoke-interface, invoke-interface/range + */ + /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ + /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ + +%def op_invoke_interface_range(): +% invoke(helper="MterpInvokeInterfaceRange") + +%def op_invoke_polymorphic(): +% invoke_polymorphic(helper="MterpInvokePolymorphic") + +%def op_invoke_polymorphic_range(): +% invoke_polymorphic(helper="MterpInvokePolymorphicRange") + +%def op_invoke_static(): +% invoke(helper="MterpInvokeStatic") + + +%def op_invoke_static_range(): +% invoke(helper="MterpInvokeStaticRange") + +%def op_invoke_super(): +% invoke(helper="MterpInvokeSuper") +/* + * Handle a "super" method call. + * + * for: invoke-super, invoke-super/range + */ + /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ + /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ + +%def op_invoke_super_range(): +% invoke(helper="MterpInvokeSuperRange") + +%def op_invoke_virtual(): +% invoke(helper="MterpInvokeVirtual") +/* + * Handle a virtual method call. + * + * for: invoke-virtual, invoke-virtual/range + */ + /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ + /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ + +%def op_invoke_virtual_quick(): +% invoke(helper="MterpInvokeVirtualQuick") + +%def op_invoke_virtual_range(): +% invoke(helper="MterpInvokeVirtualRange") + +%def op_invoke_virtual_range_quick(): +% invoke(helper="MterpInvokeVirtualQuickRange") diff --git a/runtime/interpreter/mterp/x86/invoke_polymorphic.S b/runtime/interpreter/mterp/x86/invoke_polymorphic.S deleted file mode 100644 index 5690b22028e61a03a366e4693e6222153a5183b3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/invoke_polymorphic.S +++ /dev/null @@ -1,25 +0,0 @@ -%default { "helper":"UndefinedInvokeHandler" } - /* - * invoke-polymorphic handler wrapper. - */ - /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ - .extern $helper - EXPORT_PC - movl rSELF, %ecx - movl %ecx, OUT_ARG0(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG1(%esp) - movl rPC, OUT_ARG2(%esp) - REFRESH_INST ${opnum} - movl rINST, OUT_ARG3(%esp) - call SYMBOL($helper) - testb %al, %al - jz MterpException - ADVANCE_PC 4 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - RESTORE_IBASE - FETCH_INST - GOTO_NEXT diff --git a/runtime/interpreter/mterp/x86/main.S b/runtime/interpreter/mterp/x86/main.S new file mode 100644 index 0000000000000000000000000000000000000000..ac0bb20fcb912009ace5ff71aa835de0fad046f4 --- /dev/null +++ b/runtime/interpreter/mterp/x86/main.S @@ -0,0 +1,789 @@ +%def header(): +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + Art assembly interpreter notes: + + First validate assembly code by implementing ExecuteXXXImpl() style body (doesn't + handle invoke, allows higher-level code to create frame & shadow frame. + + Once that's working, support direct entry code & eliminate shadow frame (and + excess locals allocation. + + Some (hopefully) temporary ugliness. We'll treat rFP as pointing to the + base of the vreg array within the shadow frame. Access the other fields, + dex_pc_, method_ and number_of_vregs_ via negative offsets. For now, we'll continue + the shadow frame mechanism of double-storing object references - via rFP & + number_of_vregs_. + + */ + +/* +x86 ABI general notes: + +Caller save set: + eax, edx, ecx, st(0)-st(7) +Callee save set: + ebx, esi, edi, ebp +Return regs: + 32-bit in eax + 64-bit in edx:eax (low-order 32 in eax) + fp on top of fp stack st(0) + +Parameters passed on stack, pushed right-to-left. On entry to target, first +parm is at 4(%esp). Traditional entry code is: + +functEntry: + push %ebp # save old frame pointer + mov %ebp,%esp # establish new frame pointer + sub FrameSize,%esp # Allocate storage for spill, locals & outs + +Once past the prologue, arguments are referenced at ((argno + 2)*4)(%ebp) + +Stack must be 16-byte aligned to support SSE in native code. + +If we're not doing variable stack allocation (alloca), the frame pointer can be +eliminated and all arg references adjusted to be esp relative. +*/ + +/* +Mterp and x86 notes: + +Some key interpreter variables will be assigned to registers. + + nick reg purpose + rPC esi interpreted program counter, used for fetching instructions + rFP edi interpreted frame pointer, used for accessing locals and args + rINSTw bx first 16-bit code of current instruction + rINSTbl bl opcode portion of instruction word + rINSTbh bh high byte of inst word, usually contains src/tgt reg names + rIBASE edx base of instruction handler table + rREFS ebp base of object references in shadow frame. + +Notes: + o High order 16 bits of ebx must be zero on entry to handler + o rPC, rFP, rINSTw/rINSTbl valid on handler entry and exit + o eax and ecx are scratch, rINSTw/ebx sometimes scratch + +Macros are provided for common operations. Each macro MUST emit only +one instruction to make instruction-counting easier. They MUST NOT alter +unspecified registers or condition codes. +*/ + +/* + * This is a #include, not a %include, because we want the C pre-processor + * to expand the macros into assembler assignment statements. + */ +#include "asm_support.h" +#include "interpreter/cfi_asm_support.h" + +/* + * Handle mac compiler specific + */ +#if defined(__APPLE__) + #define MACRO_LITERAL(value) $$(value) + #define FUNCTION_TYPE(name) + #define OBJECT_TYPE(name) + #define SIZE(start,end) + // Mac OS' symbols have an _ prefix. + #define SYMBOL(name) _ ## name + #define ASM_HIDDEN .private_extern +#else + #define MACRO_LITERAL(value) $$value + #define FUNCTION_TYPE(name) .type name, @function + #define OBJECT_TYPE(name) .type name, @object + #define SIZE(start,end) .size start, .-end + #define SYMBOL(name) name + #define ASM_HIDDEN .hidden +#endif + +.macro PUSH _reg + pushl \_reg + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset \_reg, 0 +.endm + +.macro POP _reg + popl \_reg + .cfi_adjust_cfa_offset -4 + .cfi_restore \_reg +.endm + +/* + * Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs. So, + * to access other shadow frame fields, we need to use a backwards offset. Define those here. + */ +#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) +#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) +#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) +#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) +#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) +#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) +#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) +#define OFF_FP_DEX_INSTRUCTIONS OFF_FP(SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET) +#define OFF_FP_COUNTDOWN_OFFSET OFF_FP(SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET) +#define OFF_FP_SHADOWFRAME OFF_FP(0) + +/* Frame size must be 16-byte aligned. + * Remember about 4 bytes for return address + 4 * 4 for spills + */ +#define FRAME_SIZE 28 + +/* Frame diagram while executing ExecuteMterpImpl, high to low addresses */ +#define IN_ARG3 (FRAME_SIZE + 16 + 16) +#define IN_ARG2 (FRAME_SIZE + 16 + 12) +#define IN_ARG1 (FRAME_SIZE + 16 + 8) +#define IN_ARG0 (FRAME_SIZE + 16 + 4) +/* Spill offsets relative to %esp */ +#define LOCAL0 (FRAME_SIZE - 4) +#define LOCAL1 (FRAME_SIZE - 8) +#define LOCAL2 (FRAME_SIZE - 12) +/* Out Arg offsets, relative to %esp */ +#define OUT_ARG3 ( 12) +#define OUT_ARG2 ( 8) +#define OUT_ARG1 ( 4) +#define OUT_ARG0 ( 0) /* <- ExecuteMterpImpl esp + 0 */ + +/* During bringup, we'll use the shadow frame model instead of rFP */ +/* single-purpose registers, given names for clarity */ +#define rSELF IN_ARG0(%esp) +#define rPC %esi +#define CFI_DEX 6 // DWARF register number of the register holding dex-pc (esi). +#define CFI_TMP 0 // DWARF register number of the first argument register (eax). +#define rFP %edi +#define rINST %ebx +#define rINSTw %bx +#define rINSTbh %bh +#define rINSTbl %bl +#define rIBASE %edx +#define rREFS %ebp +#define rPROFILE OFF_FP_COUNTDOWN_OFFSET(rFP) + +#define MTERP_LOGGING 0 + +/* + * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must + * be done *before* something throws. + * + * It's okay to do this more than once. + * + * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped + * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction + * offset into the code_items_[] array. For effiency, we will "export" the + * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC + * to convert to a dex pc when needed. + */ +.macro EXPORT_PC + movl rPC, OFF_FP_DEX_PC_PTR(rFP) +.endm + +/* + * Refresh handler table. + */ +.macro REFRESH_IBASE + movl rSELF, rIBASE + movl THREAD_CURRENT_IBASE_OFFSET(rIBASE), rIBASE +.endm + +/* + * Refresh handler table. + * IBase handles uses the caller save register so we must restore it after each call. + * Also it is used as a result of some 64-bit operations (like imul) and we should + * restore it in such cases also. + * + * TODO: Consider spilling the IBase instead of restoring it from Thread structure. + */ +.macro RESTORE_IBASE + movl rSELF, rIBASE + movl THREAD_CURRENT_IBASE_OFFSET(rIBASE), rIBASE +.endm + +/* + * If rSELF is already loaded then we can use it from known reg. + */ +.macro RESTORE_IBASE_FROM_SELF _reg + movl THREAD_CURRENT_IBASE_OFFSET(\_reg), rIBASE +.endm + +/* + * Refresh rINST. + * At enter to handler rINST does not contain the opcode number. + * However some utilities require the full value, so this macro + * restores the opcode number. + */ +.macro REFRESH_INST _opnum + movb rINSTbl, rINSTbh + movb MACRO_LITERAL(\_opnum), rINSTbl +.endm + +/* + * Fetch the next instruction from rPC into rINSTw. Does not advance rPC. + */ +.macro FETCH_INST + movzwl (rPC), rINST +.endm + +/* + * Remove opcode from rINST, compute the address of handler and jump to it. + */ +.macro GOTO_NEXT + movzx rINSTbl,%eax + movzbl rINSTbh,rINST + shll MACRO_LITERAL(${handler_size_bits}), %eax + addl rIBASE, %eax + jmp *%eax +.endm + +/* + * Advance rPC by instruction count. + */ +.macro ADVANCE_PC _count + leal 2*\_count(rPC), rPC +.endm + +/* + * Advance rPC by instruction count, fetch instruction and jump to handler. + */ +.macro ADVANCE_PC_FETCH_AND_GOTO_NEXT _count + ADVANCE_PC \_count + FETCH_INST + GOTO_NEXT +.endm + +/* + * Get/set the 32-bit value from a Dalvik register. + */ +#define VREG_ADDRESS(_vreg) (rFP,_vreg,4) +#define VREG_HIGH_ADDRESS(_vreg) 4(rFP,_vreg,4) +#define VREG_REF_ADDRESS(_vreg) (rREFS,_vreg,4) +#define VREG_REF_HIGH_ADDRESS(_vreg) 4(rREFS,_vreg,4) + +.macro GET_VREG _reg _vreg + movl (rFP,\_vreg,4), \_reg +.endm + +/* Read wide value to xmm. */ +.macro GET_WIDE_FP_VREG _reg _vreg + movq (rFP,\_vreg,4), \_reg +.endm + +.macro SET_VREG _reg _vreg + movl \_reg, (rFP,\_vreg,4) + movl MACRO_LITERAL(0), (rREFS,\_vreg,4) +.endm + +/* Write wide value from xmm. xmm is clobbered. */ +.macro SET_WIDE_FP_VREG _reg _vreg + movq \_reg, (rFP,\_vreg,4) + pxor \_reg, \_reg + movq \_reg, (rREFS,\_vreg,4) +.endm + +.macro SET_VREG_OBJECT _reg _vreg + movl \_reg, (rFP,\_vreg,4) + movl \_reg, (rREFS,\_vreg,4) +.endm + +.macro GET_VREG_HIGH _reg _vreg + movl 4(rFP,\_vreg,4), \_reg +.endm + +.macro SET_VREG_HIGH _reg _vreg + movl \_reg, 4(rFP,\_vreg,4) + movl MACRO_LITERAL(0), 4(rREFS,\_vreg,4) +.endm + +.macro CLEAR_REF _vreg + movl MACRO_LITERAL(0), (rREFS,\_vreg,4) +.endm + +.macro CLEAR_WIDE_REF _vreg + movl MACRO_LITERAL(0), (rREFS,\_vreg,4) + movl MACRO_LITERAL(0), 4(rREFS,\_vreg,4) +.endm + +%def entry(): +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* + * Interpreter entry point. + */ + + .text + ASM_HIDDEN SYMBOL(ExecuteMterpImpl) + .global SYMBOL(ExecuteMterpImpl) + FUNCTION_TYPE(ExecuteMterpImpl) + +/* + * On entry: + * 0 Thread* self + * 1 insns_ + * 2 ShadowFrame + * 3 JValue* result_register + * + */ + +SYMBOL(ExecuteMterpImpl): + .cfi_startproc + .cfi_def_cfa esp, 4 + + /* Spill callee save regs */ + PUSH %ebp + PUSH %edi + PUSH %esi + PUSH %ebx + + /* Allocate frame */ + subl $$FRAME_SIZE, %esp + .cfi_adjust_cfa_offset FRAME_SIZE + + /* Load ShadowFrame pointer */ + movl IN_ARG2(%esp), %edx + + /* Remember the return register */ + movl IN_ARG3(%esp), %eax + movl %eax, SHADOWFRAME_RESULT_REGISTER_OFFSET(%edx) + + /* Remember the code_item */ + movl IN_ARG1(%esp), %ecx + movl %ecx, SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET(%edx) + + /* set up "named" registers */ + movl SHADOWFRAME_NUMBER_OF_VREGS_OFFSET(%edx), %eax + leal SHADOWFRAME_VREGS_OFFSET(%edx), rFP + leal (rFP, %eax, 4), rREFS + movl SHADOWFRAME_DEX_PC_OFFSET(%edx), %eax + lea (%ecx, %eax, 2), rPC + CFI_DEFINE_DEX_PC_WITH_OFFSET(CFI_TMP, CFI_DEX, 0) + EXPORT_PC + + /* Set up for backwards branches & osr profiling */ + movl OFF_FP_METHOD(rFP), %eax + movl %eax, OUT_ARG0(%esp) + leal OFF_FP_SHADOWFRAME(rFP), %ecx + movl %ecx, OUT_ARG1(%esp) + movl rSELF, %eax + movl %eax, OUT_ARG2(%esp) + call SYMBOL(MterpSetUpHotnessCountdown) + + /* Starting ibase */ + REFRESH_IBASE + + /* start executing the instruction at rPC */ + FETCH_INST + GOTO_NEXT + /* NOTE: no fallthrough */ + +%def alt_stub(): +/* + * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle + * any interesting requests and then jump to the real instruction + * handler. Unlike the Arm handler, we can't do this as a tail call + * because rIBASE is caller save and we need to reload it. + * + * Note that unlike in the Arm implementation, we should never arrive + * here with a zero breakFlag because we always refresh rIBASE on + * return. + */ + .extern MterpCheckBefore + movl rSELF, %ecx + movl %ecx, OUT_ARG0(%esp) + leal OFF_FP_SHADOWFRAME(rFP), %eax + movl %eax, OUT_ARG1(%esp) + movl rPC, OUT_ARG2(%esp) + call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) + REFRESH_IBASE + jmp .L_op_nop+(${opnum}*${handler_size_bytes}) + +%def fallback(): +/* Transfer stub to alternate interpreter */ + jmp MterpFallback + + +%def helpers(): +% pass + +%def footer(): +/* + * =========================================================================== + * Common subroutines and data + * =========================================================================== + */ + + .text + .align 2 + +/* + * We've detected a condition that will result in an exception, but the exception + * has not yet been thrown. Just bail out to the reference interpreter to deal with it. + * TUNING: for consistency, we may want to just go ahead and handle these here. + */ +common_errDivideByZero: + EXPORT_PC +#if MTERP_LOGGING + movl rSELF, %eax + movl %eax, OUT_ARG0(%esp) + lea OFF_FP_SHADOWFRAME(rFP), %ecx + movl %ecx, OUT_ARG1(%esp) + call SYMBOL(MterpLogDivideByZeroException) +#endif + jmp MterpCommonFallback + +common_errArrayIndex: + EXPORT_PC +#if MTERP_LOGGING + movl rSELF, %eax + movl %eax, OUT_ARG0(%esp) + lea OFF_FP_SHADOWFRAME(rFP), %ecx + movl %ecx, OUT_ARG1(%esp) + call SYMBOL(MterpLogArrayIndexException) +#endif + jmp MterpCommonFallback + +common_errNegativeArraySize: + EXPORT_PC +#if MTERP_LOGGING + movl rSELF, %eax + movl %eax, OUT_ARG0(%esp) + lea OFF_FP_SHADOWFRAME(rFP), %ecx + movl %ecx, OUT_ARG1(%esp) + call SYMBOL(MterpLogNegativeArraySizeException) +#endif + jmp MterpCommonFallback + +common_errNoSuchMethod: + EXPORT_PC +#if MTERP_LOGGING + movl rSELF, %eax + movl %eax, OUT_ARG0(%esp) + lea OFF_FP_SHADOWFRAME(rFP), %ecx + movl %ecx, OUT_ARG1(%esp) + call SYMBOL(MterpLogNoSuchMethodException) +#endif + jmp MterpCommonFallback + +common_errNullObject: + EXPORT_PC +#if MTERP_LOGGING + movl rSELF, %eax + movl %eax, OUT_ARG0(%esp) + lea OFF_FP_SHADOWFRAME(rFP), %ecx + movl %ecx, OUT_ARG1(%esp) + call SYMBOL(MterpLogNullObjectException) +#endif + jmp MterpCommonFallback + +common_exceptionThrown: + EXPORT_PC +#if MTERP_LOGGING + movl rSELF, %eax + movl %eax, OUT_ARG0(%esp) + lea OFF_FP_SHADOWFRAME(rFP), %ecx + movl %ecx, OUT_ARG0(%esp) + call SYMBOL(MterpLogExceptionThrownException) +#endif + jmp MterpCommonFallback + +MterpSuspendFallback: + EXPORT_PC +#if MTERP_LOGGING + movl rSELF, %eax + movl %eax, OUT_ARG0(%esp) + lea OFF_FP_SHADOWFRAME(rFP), %ecx + movl %ecx, OUT_ARG0(%esp) + movl THREAD_FLAGS_OFFSET(%eax), %eax + movl %eax, OUT_ARG2(%esp) + call SYMBOL(MterpLogSuspendFallback) +#endif + jmp MterpCommonFallback + +/* + * If we're here, something is out of the ordinary. If there is a pending + * exception, handle it. Otherwise, roll back and retry with the reference + * interpreter. + */ +MterpPossibleException: + movl rSELF, %eax + testl $$-1, THREAD_EXCEPTION_OFFSET(%eax) + jz MterpFallback + /* intentional fallthrough - handle pending exception. */ + +/* + * On return from a runtime helper routine, we've found a pending exception. + * Can we handle it here - or need to bail out to caller? + * + */ +MterpException: + movl rSELF, %eax + movl %eax, OUT_ARG0(%esp) + lea OFF_FP_SHADOWFRAME(rFP), %ecx + movl %ecx, OUT_ARG1(%esp) + call SYMBOL(MterpHandleException) + testb %al, %al + jz MterpExceptionReturn + movl OFF_FP_DEX_INSTRUCTIONS(rFP), %eax + movl OFF_FP_DEX_PC(rFP), %ecx + lea (%eax, %ecx, 2), rPC + movl rPC, OFF_FP_DEX_PC_PTR(rFP) + /* Do we need to switch interpreters? */ + call SYMBOL(MterpShouldSwitchInterpreters) + testb %al, %al + jnz MterpFallback + /* resume execution at catch block */ + REFRESH_IBASE + FETCH_INST + GOTO_NEXT + /* NOTE: no fallthrough */ + +/* + * Common handling for branches with support for Jit profiling. + * On entry: + * rINST <= signed offset + * condition bits <= set to establish sign of offset (use "NoFlags" entry if not) + * + * We have quite a few different cases for branch profiling, OSR detection and + * suspend check support here. + * + * Taken backward branches: + * If profiling active, do hotness countdown and report if we hit zero. + * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. + * Is there a pending suspend request? If so, suspend. + * + * Taken forward branches and not-taken backward branches: + * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. + * + * Our most common case is expected to be a taken backward branch with active jit profiling, + * but no full OSR check and no pending suspend request. + * Next most common case is not-taken branch with no full OSR check. + * + */ +MterpCommonTakenBranch: + jg .L_forward_branch # don't add forward branches to hotness +/* + * We need to subtract 1 from positive values and we should not see 0 here, + * so we may use the result of the comparison with -1. + */ +#if JIT_CHECK_OSR != -1 +# error "JIT_CHECK_OSR must be -1." +#endif + cmpw $$JIT_CHECK_OSR, rPROFILE + je .L_osr_check + decw rPROFILE + je .L_add_batch # counted down to zero - report +.L_resume_backward_branch: + movl rSELF, %eax + testl $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(%eax) + leal (rPC, rINST, 2), rPC + FETCH_INST + jnz .L_suspend_request_pending + REFRESH_IBASE + GOTO_NEXT + +.L_suspend_request_pending: + EXPORT_PC + movl %eax, OUT_ARG0(%esp) # rSELF in eax + call SYMBOL(MterpSuspendCheck) # (self) + testb %al, %al + jnz MterpFallback + REFRESH_IBASE # might have changed during suspend + GOTO_NEXT + +.L_no_count_backwards: + cmpw $$JIT_CHECK_OSR, rPROFILE # possible OSR re-entry? + jne .L_resume_backward_branch +.L_osr_check: + EXPORT_PC + movl rSELF, %eax + movl %eax, OUT_ARG0(%esp) + leal OFF_FP_SHADOWFRAME(rFP), %ecx + movl %ecx, OUT_ARG1(%esp) + movl rINST, OUT_ARG2(%esp) + call SYMBOL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) + testb %al, %al + jz .L_resume_backward_branch + jmp MterpOnStackReplacement + +.L_forward_branch: + cmpw $$JIT_CHECK_OSR, rPROFILE # possible OSR re-entry? + je .L_check_osr_forward +.L_resume_forward_branch: + leal (rPC, rINST, 2), rPC + FETCH_INST + GOTO_NEXT + +.L_check_osr_forward: + EXPORT_PC + movl rSELF, %eax + movl %eax, OUT_ARG0(%esp) + leal OFF_FP_SHADOWFRAME(rFP), %ecx + movl %ecx, OUT_ARG1(%esp) + movl rINST, OUT_ARG2(%esp) + call SYMBOL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) + testb %al, %al + REFRESH_IBASE + jz .L_resume_forward_branch + jmp MterpOnStackReplacement + +.L_add_batch: + movl OFF_FP_METHOD(rFP), %eax + movl %eax, OUT_ARG0(%esp) + leal OFF_FP_SHADOWFRAME(rFP), %ecx + movl %ecx, OUT_ARG1(%esp) + movl rSELF, %eax + movl %eax, OUT_ARG2(%esp) + call SYMBOL(MterpAddHotnessBatch) # (method, shadow_frame, self) + jmp .L_no_count_backwards + +/* + * Entered from the conditional branch handlers when OSR check request active on + * not-taken path. All Dalvik not-taken conditional branch offsets are 2. + */ +.L_check_not_taken_osr: + EXPORT_PC + movl rSELF, %eax + movl %eax, OUT_ARG0(%esp) + leal OFF_FP_SHADOWFRAME(rFP), %ecx + movl %ecx, OUT_ARG1(%esp) + movl $$2, OUT_ARG2(%esp) + call SYMBOL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) + testb %al, %al + REFRESH_IBASE + jnz MterpOnStackReplacement + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +/* + * On-stack replacement has happened, and now we've returned from the compiled method. + */ +MterpOnStackReplacement: +#if MTERP_LOGGING + movl rSELF, %eax + movl %eax, OUT_ARG0(%esp) + lea OFF_FP_SHADOWFRAME(rFP), %ecx + movl %ecx, OUT_ARG1(%esp) + movl rINST, OUT_ARG2(%esp) + call SYMBOL(MterpLogOSR) +#endif + movl $$1, %eax + jmp MterpDone + +/* + * Bail out to reference interpreter. + */ +MterpFallback: + EXPORT_PC +#if MTERP_LOGGING + movl rSELF, %eax + movl %eax, OUT_ARG0(%esp) + lea OFF_FP_SHADOWFRAME(rFP), %ecx + movl %ecx, OUT_ARG1(%esp) + call SYMBOL(MterpLogFallback) +#endif +MterpCommonFallback: + xor %eax, %eax + jmp MterpDone + +/* + * On entry: + * uint32_t* rFP (should still be live, pointer to base of vregs) + */ +MterpExceptionReturn: + movl $$1, %eax + jmp MterpDone +MterpReturn: + movl OFF_FP_RESULT_REGISTER(rFP), %edx + movl %eax, (%edx) + movl %ecx, 4(%edx) + mov $$1, %eax +MterpDone: +/* + * At this point, we expect rPROFILE to be non-zero. If negative, hotness is disabled or we're + * checking for OSR. If greater than zero, we might have unreported hotness to register + * (the difference between the ending rPROFILE and the cached hotness counter). rPROFILE + * should only reach zero immediately after a hotness decrement, and is then reset to either + * a negative special state or the new non-zero countdown value. + */ + cmpw $$0, rPROFILE + jle MRestoreFrame # if > 0, we may have some counts to report. + + movl %eax, rINST # stash return value + /* Report cached hotness counts */ + movl OFF_FP_METHOD(rFP), %eax + movl %eax, OUT_ARG0(%esp) + leal OFF_FP_SHADOWFRAME(rFP), %ecx + movl %ecx, OUT_ARG1(%esp) + movl rSELF, %eax + movl %eax, OUT_ARG2(%esp) + call SYMBOL(MterpAddHotnessBatch) # (method, shadow_frame, self) + movl rINST, %eax # restore return value + + /* pop up frame */ +MRestoreFrame: + addl $$FRAME_SIZE, %esp + .cfi_adjust_cfa_offset -FRAME_SIZE + + /* Restore callee save register */ + POP %ebx + POP %esi + POP %edi + POP %ebp + ret + .cfi_endproc + SIZE(ExecuteMterpImpl,ExecuteMterpImpl) + +%def instruction_end(): + + OBJECT_TYPE(artMterpAsmInstructionEnd) + ASM_HIDDEN SYMBOL(artMterpAsmInstructionEnd) + .global SYMBOL(artMterpAsmInstructionEnd) +SYMBOL(artMterpAsmInstructionEnd): + +%def instruction_end_alt(): + + OBJECT_TYPE(artMterpAsmAltInstructionEnd) + ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionEnd) + .global SYMBOL(artMterpAsmAltInstructionEnd) +SYMBOL(artMterpAsmAltInstructionEnd): + +%def instruction_start(): + + OBJECT_TYPE(artMterpAsmInstructionStart) + ASM_HIDDEN SYMBOL(artMterpAsmInstructionStart) + .global SYMBOL(artMterpAsmInstructionStart) +SYMBOL(artMterpAsmInstructionStart) = .L_op_nop + .text + +%def instruction_start_alt(): + + OBJECT_TYPE(artMterpAsmAltInstructionStart) + ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionStart) + .global SYMBOL(artMterpAsmAltInstructionStart) + .text +SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop + diff --git a/runtime/interpreter/mterp/x86/object.S b/runtime/interpreter/mterp/x86/object.S new file mode 100644 index 0000000000000000000000000000000000000000..a47fa3a9303a54d439e605b47dae21fc9b2e6a1e --- /dev/null +++ b/runtime/interpreter/mterp/x86/object.S @@ -0,0 +1,278 @@ +%def field(helper=""): + /* + * General field read / write (iget-* iput-* sget-* sput-*). + */ + .extern $helper + REFRESH_INST ${opnum} # fix rINST to include opcode + movl rPC, OUT_ARG0(%esp) # arg0: Instruction* inst + movl rINST, OUT_ARG1(%esp) # arg1: uint16_t inst_data + leal OFF_FP_SHADOWFRAME(rFP), %eax + movl %eax, OUT_ARG2(%esp) # arg2: ShadowFrame* sf + movl rSELF, %eax + movl %eax, OUT_ARG3(%esp) # arg3: Thread* self + call SYMBOL($helper) + testb %al, %al + jz MterpPossibleException + RESTORE_IBASE + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_check_cast(): +/* + * Check to see if a cast from one class to another is allowed. + */ + /* check-cast vAA, class@BBBB */ + EXPORT_PC + movzwl 2(rPC), %eax # eax <- BBBB + movl %eax, OUT_ARG0(%esp) + leal VREG_ADDRESS(rINST), %ecx + movl %ecx, OUT_ARG1(%esp) + movl OFF_FP_METHOD(rFP),%eax + movl %eax, OUT_ARG2(%esp) + movl rSELF, %ecx + movl %ecx, OUT_ARG3(%esp) + call SYMBOL(MterpCheckCast) # (index, &obj, method, self) + RESTORE_IBASE + testb %al, %al + jnz MterpPossibleException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_iget(is_object="0", helper="MterpIGetU32"): +% field(helper=helper) + +%def op_iget_boolean(): +% op_iget(helper="MterpIGetU8") + +%def op_iget_boolean_quick(): +% op_iget_quick(load="movsbl") + +%def op_iget_byte(): +% op_iget(helper="MterpIGetI8") + +%def op_iget_byte_quick(): +% op_iget_quick(load="movsbl") + +%def op_iget_char(): +% op_iget(helper="MterpIGetU16") + +%def op_iget_char_quick(): +% op_iget_quick(load="movzwl") + +%def op_iget_object(): +% op_iget(is_object="1", helper="MterpIGetObj") + +%def op_iget_object_quick(): + /* For: iget-object-quick */ + /* op vA, vB, offset@CCCC */ + movzbl rINSTbl, %ecx # ecx <- BA + sarl $$4, %ecx # ecx <- B + GET_VREG %ecx, %ecx # vB (object we're operating on) + movzwl 2(rPC), %eax # eax <- field byte offset + movl %ecx, OUT_ARG0(%esp) + movl %eax, OUT_ARG1(%esp) + EXPORT_PC + call SYMBOL(artIGetObjectFromMterp) # (obj, offset) + movl rSELF, %ecx + RESTORE_IBASE_FROM_SELF %ecx + cmpl $$0, THREAD_EXCEPTION_OFFSET(%ecx) + jnz MterpException # bail out + andb $$0xf,rINSTbl # rINST <- A + SET_VREG_OBJECT %eax, rINST # fp[A] <- value + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_iget_quick(load="movl"): + /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ + /* op vA, vB, offset@CCCC */ + movzbl rINSTbl, %ecx # ecx <- BA + sarl $$4, %ecx # ecx <- B + GET_VREG %ecx, %ecx # vB (object we're operating on) + movzwl 2(rPC), %eax # eax <- field byte offset + testl %ecx, %ecx # is object null? + je common_errNullObject + ${load} (%ecx,%eax,1), %eax + andb $$0xf,rINSTbl # rINST <- A + SET_VREG %eax, rINST # fp[A] <- value + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_iget_short(): +% op_iget(helper="MterpIGetI16") + +%def op_iget_short_quick(): +% op_iget_quick(load="movswl") + +%def op_iget_wide(): +% op_iget(helper="MterpIGetU64") + +%def op_iget_wide_quick(): + /* iget-wide-quick vA, vB, offset@CCCC */ + movzbl rINSTbl, %ecx # ecx <- BA + sarl $$4, %ecx # ecx <- B + GET_VREG %ecx, %ecx # vB (object we're operating on) + movzwl 2(rPC), %eax # eax <- field byte offset + testl %ecx, %ecx # is object null? + je common_errNullObject + movq (%ecx,%eax,1), %xmm0 + andb $$0xf, rINSTbl # rINST <- A + SET_WIDE_FP_VREG %xmm0, rINST + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_instance_of(): +/* + * Check to see if an object reference is an instance of a class. + * + * Most common situation is a non-null object, being compared against + * an already-resolved class. + */ + /* instance-of vA, vB, class@CCCC */ + EXPORT_PC + movzwl 2(rPC), %eax # eax <- BBBB + movl %eax, OUT_ARG0(%esp) + movl rINST, %eax # eax <- BA + sarl $$4, %eax # eax <- B + leal VREG_ADDRESS(%eax), %ecx # Get object address + movl %ecx, OUT_ARG1(%esp) + movl OFF_FP_METHOD(rFP),%eax + movl %eax, OUT_ARG2(%esp) + movl rSELF, %ecx + movl %ecx, OUT_ARG3(%esp) + call SYMBOL(MterpInstanceOf) # (index, &obj, method, self) + movl rSELF, %ecx + RESTORE_IBASE_FROM_SELF %ecx + cmpl $$0, THREAD_EXCEPTION_OFFSET(%ecx) + jnz MterpException + andb $$0xf, rINSTbl # rINSTbl <- A + SET_VREG %eax, rINST + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_iput(is_object="0", helper="MterpIPutU32"): +% field(helper=helper) + +%def op_iput_boolean(): +% op_iput(helper="MterpIPutU8") + +%def op_iput_boolean_quick(): +% op_iput_quick(reg="rINSTbl", store="movb") + +%def op_iput_byte(): +% op_iput(helper="MterpIPutI8") + +%def op_iput_byte_quick(): +% op_iput_quick(reg="rINSTbl", store="movb") + +%def op_iput_char(): +% op_iput(helper="MterpIPutU16") + +%def op_iput_char_quick(): +% op_iput_quick(reg="rINSTw", store="movw") + +%def op_iput_object(): +% op_iput(is_object="1", helper="MterpIPutObj") + +%def op_iput_object_quick(): + EXPORT_PC + leal OFF_FP_SHADOWFRAME(rFP), %eax + movl %eax, OUT_ARG0(%esp) + movl rPC, OUT_ARG1(%esp) + REFRESH_INST ${opnum} + movl rINST, OUT_ARG2(%esp) + call SYMBOL(MterpIputObjectQuick) + testb %al, %al + jz MterpException + RESTORE_IBASE + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_iput_quick(reg="rINST", store="movl"): + /* For: iput-quick, iput-object-quick */ + /* op vA, vB, offset@CCCC */ + movzbl rINSTbl, %ecx # ecx <- BA + sarl $$4, %ecx # ecx <- B + GET_VREG %ecx, %ecx # vB (object we're operating on) + testl %ecx, %ecx # is object null? + je common_errNullObject + andb $$0xf, rINSTbl # rINST <- A + GET_VREG rINST, rINST # rINST <- v[A] + movzwl 2(rPC), %eax # eax <- field byte offset + ${store} ${reg}, (%ecx,%eax,1) + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_iput_short(): +% op_iput(helper="MterpIPutI16") + +%def op_iput_short_quick(): +% op_iput_quick(reg="rINSTw", store="movw") + +%def op_iput_wide(): +% op_iput(helper="MterpIPutU64") + +%def op_iput_wide_quick(): + /* iput-wide-quick vA, vB, offset@CCCC */ + movzbl rINSTbl, %ecx # ecx<- BA + sarl $$4, %ecx # ecx<- B + GET_VREG %ecx, %ecx # vB (object we're operating on) + testl %ecx, %ecx # is object null? + je common_errNullObject + movzwl 2(rPC), %eax # eax<- field byte offset + leal (%ecx,%eax,1), %ecx # ecx<- Address of 64-bit target + andb $$0xf, rINSTbl # rINST<- A + GET_WIDE_FP_VREG %xmm0, rINST # xmm0<- fp[A]/fp[A+1] + movq %xmm0, (%ecx) # obj.field<- r0/r1 + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_new_instance(): +/* + * Create a new instance of a class. + */ + /* new-instance vAA, class@BBBB */ + EXPORT_PC + leal OFF_FP_SHADOWFRAME(rFP), %eax + movl %eax, OUT_ARG0(%esp) + movl rSELF, %ecx + movl %ecx, OUT_ARG1(%esp) + REFRESH_INST ${opnum} + movl rINST, OUT_ARG2(%esp) + call SYMBOL(MterpNewInstance) + RESTORE_IBASE + testb %al, %al # 0 means an exception is thrown + jz MterpPossibleException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_sget(is_object="0", helper="MterpSGetU32"): +% field(helper=helper) + +%def op_sget_boolean(): +% op_sget(helper="MterpSGetU8") + +%def op_sget_byte(): +% op_sget(helper="MterpSGetI8") + +%def op_sget_char(): +% op_sget(helper="MterpSGetU16") + +%def op_sget_object(): +% op_sget(is_object="1", helper="MterpSGetObj") + +%def op_sget_short(): +% op_sget(helper="MterpSGetI16") + +%def op_sget_wide(): +% op_sget(helper="MterpSGetU64") + +%def op_sput(is_object="0", helper="MterpSPutU32"): +% field(helper=helper) + +%def op_sput_boolean(): +% op_sput(helper="MterpSPutU8") + +%def op_sput_byte(): +% op_sput(helper="MterpSPutI8") + +%def op_sput_char(): +% op_sput(helper="MterpSPutU16") + +%def op_sput_object(): +% op_sput(is_object="1", helper="MterpSPutObj") + +%def op_sput_short(): +% op_sput(helper="MterpSPutI16") + +%def op_sput_wide(): +% op_sput(helper="MterpSPutU64") diff --git a/runtime/interpreter/mterp/x86/op_add_double.S b/runtime/interpreter/mterp/x86/op_add_double.S deleted file mode 100644 index de2708f442ee79c6b88719fd2b617e9513d910bc..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_add_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/sseBinop.S" {"instr":"adds","suff":"d"} diff --git a/runtime/interpreter/mterp/x86/op_add_double_2addr.S b/runtime/interpreter/mterp/x86/op_add_double_2addr.S deleted file mode 100644 index 538c9ab76ef90c977d7ef4e3efd1c3e80b7f0c65..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_add_double_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/sseBinop2Addr.S" {"instr":"adds","suff":"d"} diff --git a/runtime/interpreter/mterp/x86/op_add_float.S b/runtime/interpreter/mterp/x86/op_add_float.S deleted file mode 100644 index 80b173658b695f27e05d6d37370b4aed20d0b500..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_add_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/sseBinop.S" {"instr":"adds","suff":"s"} diff --git a/runtime/interpreter/mterp/x86/op_add_float_2addr.S b/runtime/interpreter/mterp/x86/op_add_float_2addr.S deleted file mode 100644 index 66492539762423ca945461b0698fc5f975d39ee3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_add_float_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/sseBinop2Addr.S" {"instr":"adds","suff":"s"} diff --git a/runtime/interpreter/mterp/x86/op_add_int.S b/runtime/interpreter/mterp/x86/op_add_int.S deleted file mode 100644 index f71a56b65eca404a392b8c7baa4b66ccad893726..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_add_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/binop.S" {"instr":"addl (rFP,%ecx,4), %eax"} diff --git a/runtime/interpreter/mterp/x86/op_add_int_2addr.S b/runtime/interpreter/mterp/x86/op_add_int_2addr.S deleted file mode 100644 index 5d43b6517d639d644afc6e2c56acd9db1cb74058..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_add_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/binop2addr.S" {"instr":"addl %eax, (rFP,%ecx,4)"} diff --git a/runtime/interpreter/mterp/x86/op_add_int_lit16.S b/runtime/interpreter/mterp/x86/op_add_int_lit16.S deleted file mode 100644 index 4f34d173f260a8d52c638dc547518bc8deea4be2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_add_int_lit16.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/binopLit16.S" {"instr":"addl %ecx, %eax"} diff --git a/runtime/interpreter/mterp/x86/op_add_int_lit8.S b/runtime/interpreter/mterp/x86/op_add_int_lit8.S deleted file mode 100644 index 3f14744dcd6998f95c86d20221b0739889745c66..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_add_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/binopLit8.S" {"instr":"addl %ecx, %eax"} diff --git a/runtime/interpreter/mterp/x86/op_add_long.S b/runtime/interpreter/mterp/x86/op_add_long.S deleted file mode 100644 index dce0c265276ef4c307d873f445a8a2752053bc5b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_add_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/binopWide.S" {"instr1":"addl (rFP,%ecx,4), rIBASE", "instr2":"adcl 4(rFP,%ecx,4), %eax"} diff --git a/runtime/interpreter/mterp/x86/op_add_long_2addr.S b/runtime/interpreter/mterp/x86/op_add_long_2addr.S deleted file mode 100644 index 7847640e38c1e207fcccf8e5f3d8e91aa9b52807..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_add_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/binopWide2addr.S" {"instr1":"addl %eax, (rFP,rINST,4)","instr2":"adcl %ecx, 4(rFP,rINST,4)"} diff --git a/runtime/interpreter/mterp/x86/op_aget.S b/runtime/interpreter/mterp/x86/op_aget.S deleted file mode 100644 index 338386ff409ea32a9fb5e6b4783bfc140396e828..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_aget.S +++ /dev/null @@ -1,19 +0,0 @@ -%default { "load":"movl", "shift":"4", "data_offset":"MIRROR_INT_ARRAY_DATA_OFFSET" } -/* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short - * - */ - /* op vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB (array object) - GET_VREG %ecx, %ecx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - $load $data_offset(%eax,%ecx,$shift), %eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_aget_boolean.S b/runtime/interpreter/mterp/x86/op_aget_boolean.S deleted file mode 100644 index d910c94e458a5b73a4856513ce18918ff07ce2df..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_aget_boolean.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_aget.S" { "load":"movzbl", "shift":"1", "data_offset":"MIRROR_BOOLEAN_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/x86/op_aget_byte.S b/runtime/interpreter/mterp/x86/op_aget_byte.S deleted file mode 100644 index aba9ffc25a699e7f7aa31f06c2920b6464a9d1e6..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_aget_byte.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_aget.S" { "load":"movsbl", "shift":"1", "data_offset":"MIRROR_BYTE_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/x86/op_aget_char.S b/runtime/interpreter/mterp/x86/op_aget_char.S deleted file mode 100644 index 748e4108b33633eed27e56b68714b023f2f6375c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_aget_char.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_aget.S" { "load":"movzwl", "shift":"2", "data_offset":"MIRROR_CHAR_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/x86/op_aget_object.S b/runtime/interpreter/mterp/x86/op_aget_object.S deleted file mode 100644 index 35ec053854a8c8b049c93b3691f63418e19a232a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_aget_object.S +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Array object get. vAA <- vBB[vCC]. - * - * for: aget-object - */ - /* op vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB (array object) - GET_VREG %ecx, %ecx # ecs <- vCC (requested index) - EXPORT_PC - movl %eax, OUT_ARG0(%esp) - movl %ecx, OUT_ARG1(%esp) - call SYMBOL(artAGetObjectFromMterp) # (array, index) - movl rSELF, %ecx - RESTORE_IBASE_FROM_SELF %ecx - cmpl $$0, THREAD_EXCEPTION_OFFSET(%ecx) - jnz MterpException - SET_VREG_OBJECT %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_aget_short.S b/runtime/interpreter/mterp/x86/op_aget_short.S deleted file mode 100644 index 6eaf5d922d93dfb64ffa555abcef0136aaddbdbd..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_aget_short.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_aget.S" { "load":"movswl", "shift":"2", "data_offset":"MIRROR_SHORT_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/x86/op_aget_wide.S b/runtime/interpreter/mterp/x86/op_aget_wide.S deleted file mode 100644 index 92c612a25ca4c2c8f52d18456f7f6dba0e2151c3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_aget_wide.S +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Array get, 64 bits. vAA <- vBB[vCC]. - */ - /* aget-wide vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB (array object) - GET_VREG %ecx, %ecx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - leal MIRROR_WIDE_ARRAY_DATA_OFFSET(%eax,%ecx,8), %eax - movq (%eax), %xmm0 # xmm0 <- vBB[vCC] - SET_WIDE_FP_VREG %xmm0, rINST # vAA <- xmm0 - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_and_int.S b/runtime/interpreter/mterp/x86/op_and_int.S deleted file mode 100644 index 6272c4e30d032d4f1db75c36fccc14d38822a37b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_and_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/binop.S" {"instr":"andl (rFP,%ecx,4), %eax"} diff --git a/runtime/interpreter/mterp/x86/op_and_int_2addr.S b/runtime/interpreter/mterp/x86/op_and_int_2addr.S deleted file mode 100644 index 95df8731719e65583719e43ac0bf0efaef1f6047..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_and_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/binop2addr.S" {"instr":"andl %eax, (rFP,%ecx,4)"} diff --git a/runtime/interpreter/mterp/x86/op_and_int_lit16.S b/runtime/interpreter/mterp/x86/op_and_int_lit16.S deleted file mode 100644 index b06206410660b8c569d871e652eb5b2c6ebbccbe..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_and_int_lit16.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/binopLit16.S" {"instr":"andl %ecx, %eax"} diff --git a/runtime/interpreter/mterp/x86/op_and_int_lit8.S b/runtime/interpreter/mterp/x86/op_and_int_lit8.S deleted file mode 100644 index 99915dfa304eb9f08a590daefe2a88e075920e5e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_and_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/binopLit8.S" {"instr":"andl %ecx, %eax"} diff --git a/runtime/interpreter/mterp/x86/op_and_long.S b/runtime/interpreter/mterp/x86/op_and_long.S deleted file mode 100644 index f8514ea802f4fdd25b9ba0e401bde9f333b04ff4..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_and_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/binopWide.S" {"instr1":"andl (rFP,%ecx,4), rIBASE", "instr2":"andl 4(rFP,%ecx,4), %eax"} diff --git a/runtime/interpreter/mterp/x86/op_and_long_2addr.S b/runtime/interpreter/mterp/x86/op_and_long_2addr.S deleted file mode 100644 index 37249b8153f2dbf8729b7482d700610535851888..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_and_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/binopWide2addr.S" {"instr1":"andl %eax, (rFP,rINST,4)","instr2":"andl %ecx, 4(rFP,rINST,4)"} diff --git a/runtime/interpreter/mterp/x86/op_aput.S b/runtime/interpreter/mterp/x86/op_aput.S deleted file mode 100644 index 9d8c52d1273907b24eff570cf614b2337799951f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_aput.S +++ /dev/null @@ -1,20 +0,0 @@ -%default { "reg":"rINST", "store":"movl", "shift":"4", "data_offset":"MIRROR_INT_ARRAY_DATA_OFFSET" } -/* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short - * - */ - /* op vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB (array object) - GET_VREG %ecx, %ecx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - leal $data_offset(%eax,%ecx,$shift), %eax - GET_VREG rINST, rINST - $store $reg, (%eax) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_aput_boolean.S b/runtime/interpreter/mterp/x86/op_aput_boolean.S deleted file mode 100644 index e7fdd53924d2a637ec7f2493ec745c2a64ccae10..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_aput_boolean.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_aput.S" { "reg":"rINSTbl", "store":"movb", "shift":"1", "data_offset":"MIRROR_BOOLEAN_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/x86/op_aput_byte.S b/runtime/interpreter/mterp/x86/op_aput_byte.S deleted file mode 100644 index 491d03cd72ca0f6f42ce1f03b30d461dd5f03153..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_aput_byte.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_aput.S" { "reg":"rINSTbl", "store":"movb", "shift":"1", "data_offset":"MIRROR_BYTE_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/x86/op_aput_char.S b/runtime/interpreter/mterp/x86/op_aput_char.S deleted file mode 100644 index ca42cf0c74cca1cb3065f6386141391b6dbfef75..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_aput_char.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_aput.S" { "reg":"rINSTw", "store":"movw", "shift":"2", "data_offset":"MIRROR_CHAR_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/x86/op_aput_object.S b/runtime/interpreter/mterp/x86/op_aput_object.S deleted file mode 100644 index 980b26a40144906627472e1e6995c0773f528096..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_aput_object.S +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Store an object into an array. vBB[vCC] <- vAA. - */ - /* op vAA, vBB, vCC */ - EXPORT_PC - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG0(%esp) - movl rPC, OUT_ARG1(%esp) - REFRESH_INST ${opnum} - movl rINST, OUT_ARG2(%esp) - call SYMBOL(MterpAputObject) # (array, index) - RESTORE_IBASE - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_aput_short.S b/runtime/interpreter/mterp/x86/op_aput_short.S deleted file mode 100644 index 5e634821cc512ead0c3c649d5586a5578ef3fa8f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_aput_short.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_aput.S" { "reg":"rINSTw", "store":"movw", "shift":"2", "data_offset":"MIRROR_SHORT_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/x86/op_aput_wide.S b/runtime/interpreter/mterp/x86/op_aput_wide.S deleted file mode 100644 index 43ef64a54aac03f08b1d987ca1d951beef10e860..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_aput_wide.S +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Array put, 64 bits. vBB[vCC] <- vAA. - * - */ - /* aput-wide vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB (array object) - GET_VREG %ecx, %ecx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - leal MIRROR_WIDE_ARRAY_DATA_OFFSET(%eax,%ecx,8), %eax - GET_WIDE_FP_VREG %xmm0, rINST # xmm0 <- vAA - movq %xmm0, (%eax) # vBB[vCC] <- xmm0 - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_array_length.S b/runtime/interpreter/mterp/x86/op_array_length.S deleted file mode 100644 index 60ed80b5413c39ef9a71923277a93b0ba620e955..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_array_length.S +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Return the length of an array. - */ - mov rINST, %eax # eax <- BA - sarl $$4, rINST # rINST <- B - GET_VREG %ecx, rINST # ecx <- vB (object ref) - testl %ecx, %ecx # is null? - je common_errNullObject - andb $$0xf, %al # eax <- A - movl MIRROR_ARRAY_LENGTH_OFFSET(%ecx), rINST - SET_VREG rINST, %eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/op_check_cast.S b/runtime/interpreter/mterp/x86/op_check_cast.S deleted file mode 100644 index d090aa3785135d1630139d27da9962842ad3ed67..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_check_cast.S +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Check to see if a cast from one class to another is allowed. - */ - /* check-cast vAA, class@BBBB */ - EXPORT_PC - movzwl 2(rPC), %eax # eax <- BBBB - movl %eax, OUT_ARG0(%esp) - leal VREG_ADDRESS(rINST), %ecx - movl %ecx, OUT_ARG1(%esp) - movl OFF_FP_METHOD(rFP),%eax - movl %eax, OUT_ARG2(%esp) - movl rSELF, %ecx - movl %ecx, OUT_ARG3(%esp) - call SYMBOL(MterpCheckCast) # (index, &obj, method, self) - RESTORE_IBASE - testb %al, %al - jnz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_cmp_long.S b/runtime/interpreter/mterp/x86/op_cmp_long.S deleted file mode 100644 index 1f729b078e33625f625d39dfef8039aa7b6a58eb..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_cmp_long.S +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Compare two 64-bit values. Puts 0, 1, or -1 into the destination - * register based on the results of the comparison. - */ - /* cmp-long vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG_HIGH %eax, %eax # eax <- v[BB+1], BB is clobbered - cmpl VREG_HIGH_ADDRESS(%ecx), %eax - jl .L${opcode}_smaller - jg .L${opcode}_bigger - movzbl 2(rPC), %eax # eax <- BB, restore BB - GET_VREG %eax, %eax # eax <- v[BB] - sub VREG_ADDRESS(%ecx), %eax - ja .L${opcode}_bigger - jb .L${opcode}_smaller -.L${opcode}_finish: - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -.L${opcode}_bigger: - movl $$1, %eax - jmp .L${opcode}_finish - -.L${opcode}_smaller: - movl $$-1, %eax - jmp .L${opcode}_finish diff --git a/runtime/interpreter/mterp/x86/op_cmpg_double.S b/runtime/interpreter/mterp/x86/op_cmpg_double.S deleted file mode 100644 index a73ba550d23a5e1a721264068bff5cebb6f840ee..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_cmpg_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/fpcmp.S" {"suff":"d","nanval":"pos"} diff --git a/runtime/interpreter/mterp/x86/op_cmpg_float.S b/runtime/interpreter/mterp/x86/op_cmpg_float.S deleted file mode 100644 index 648051b583a7d756f5abc120a1bea6c6ef964d09..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_cmpg_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/fpcmp.S" {"suff":"s","nanval":"pos"} diff --git a/runtime/interpreter/mterp/x86/op_cmpl_double.S b/runtime/interpreter/mterp/x86/op_cmpl_double.S deleted file mode 100644 index 058163e8990d2bea41e0d8b97acdbb6af0da2d5f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_cmpl_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/fpcmp.S" {"suff":"d","nanval":"neg"} diff --git a/runtime/interpreter/mterp/x86/op_cmpl_float.S b/runtime/interpreter/mterp/x86/op_cmpl_float.S deleted file mode 100644 index 302f0784755ac155500b4cb707e1b64801034acf..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_cmpl_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/fpcmp.S" {"suff":"s","nanval":"neg"} diff --git a/runtime/interpreter/mterp/x86/op_const.S b/runtime/interpreter/mterp/x86/op_const.S deleted file mode 100644 index 544d63b22acc540e69f49add0e8984959125124c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_const.S +++ /dev/null @@ -1,4 +0,0 @@ - /* const vAA, #+BBBBbbbb */ - movl 2(rPC), %eax # grab all 32 bits at once - SET_VREG %eax, rINST # vAA<- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 diff --git a/runtime/interpreter/mterp/x86/op_const_16.S b/runtime/interpreter/mterp/x86/op_const_16.S deleted file mode 100644 index 97cd5faf2fb263cdd61485d21389f82d6a5f8f74..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_const_16.S +++ /dev/null @@ -1,4 +0,0 @@ - /* const/16 vAA, #+BBBB */ - movswl 2(rPC), %ecx # ecx <- ssssBBBB - SET_VREG %ecx, rINST # vAA <- ssssBBBB - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_const_4.S b/runtime/interpreter/mterp/x86/op_const_4.S deleted file mode 100644 index a60ba96c5a55d0e923186c36befec618afa350c8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_const_4.S +++ /dev/null @@ -1,7 +0,0 @@ - /* const/4 vA, #+B */ - movsx rINSTbl, %eax # eax <-ssssssBx - movl $$0xf, rINST - andl %eax, rINST # rINST <- A - sarl $$4, %eax - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/op_const_class.S b/runtime/interpreter/mterp/x86/op_const_class.S deleted file mode 100644 index 71648b5df7014919551922d4a3fc6de7f99a59a2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_const_class.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/const.S" { "helper":"MterpConstClass" } diff --git a/runtime/interpreter/mterp/x86/op_const_high16.S b/runtime/interpreter/mterp/x86/op_const_high16.S deleted file mode 100644 index 576967af99f54bd9579fca91c6cf33800eb6367d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_const_high16.S +++ /dev/null @@ -1,5 +0,0 @@ - /* const/high16 vAA, #+BBBB0000 */ - movzwl 2(rPC), %eax # eax <- 0000BBBB - sall $$16, %eax # eax <- BBBB0000 - SET_VREG %eax, rINST # vAA <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_const_method_handle.S b/runtime/interpreter/mterp/x86/op_const_method_handle.S deleted file mode 100644 index 77948fd8f9f72bbc6ba7602b0553f9e4bb42451e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_const_method_handle.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/const.S" { "helper":"MterpConstMethodHandle" } diff --git a/runtime/interpreter/mterp/x86/op_const_method_type.S b/runtime/interpreter/mterp/x86/op_const_method_type.S deleted file mode 100644 index 03c6ce535063fd7841be9ca582dafa1dd5be6bda..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_const_method_type.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/const.S" { "helper":"MterpConstMethodType" } diff --git a/runtime/interpreter/mterp/x86/op_const_string.S b/runtime/interpreter/mterp/x86/op_const_string.S deleted file mode 100644 index 5553aab55700c42aec96610903a62b7cb39b0f5f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_const_string.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/const.S" { "helper":"MterpConstString" } diff --git a/runtime/interpreter/mterp/x86/op_const_string_jumbo.S b/runtime/interpreter/mterp/x86/op_const_string_jumbo.S deleted file mode 100644 index e7f952a3060e3dca3295e5128a777dca62c62515..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_const_string_jumbo.S +++ /dev/null @@ -1,14 +0,0 @@ - /* const/string vAA, String@BBBBBBBB */ - EXPORT_PC - movl 2(rPC), %eax # eax <- BBBB - movl %eax, OUT_ARG0(%esp) - movl rINST, OUT_ARG1(%esp) - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG2(%esp) - movl rSELF, %eax - movl %eax, OUT_ARG3(%esp) - call SYMBOL(MterpConstString) # (index, tgt_reg, shadow_frame, self) - RESTORE_IBASE - testb %al, %al - jnz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 diff --git a/runtime/interpreter/mterp/x86/op_const_wide.S b/runtime/interpreter/mterp/x86/op_const_wide.S deleted file mode 100644 index 375072812810b193d3e56dcd7d80f0ae2b9973b2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_const_wide.S +++ /dev/null @@ -1,7 +0,0 @@ - /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ - movl 2(rPC), %eax # eax <- lsw - movzbl rINSTbl, %ecx # ecx <- AA - movl 6(rPC), rINST # rINST <- msw - SET_VREG %eax, %ecx - SET_VREG_HIGH rINST, %ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 5 diff --git a/runtime/interpreter/mterp/x86/op_const_wide_16.S b/runtime/interpreter/mterp/x86/op_const_wide_16.S deleted file mode 100644 index 1331c329dc929584d7d44fa009f2494eab283a70..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_const_wide_16.S +++ /dev/null @@ -1,8 +0,0 @@ - /* const-wide/16 vAA, #+BBBB */ - movswl 2(rPC), %eax # eax <- ssssBBBB - movl rIBASE, %ecx # preserve rIBASE (cltd trashes it) - cltd # rIBASE:eax <- ssssssssssssBBBB - SET_VREG_HIGH rIBASE, rINST # store msw - SET_VREG %eax, rINST # store lsw - movl %ecx, rIBASE # restore rIBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_const_wide_32.S b/runtime/interpreter/mterp/x86/op_const_wide_32.S deleted file mode 100644 index ed7d62b39677142de524dfd7320aaef393d28fd6..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_const_wide_32.S +++ /dev/null @@ -1,8 +0,0 @@ - /* const-wide/32 vAA, #+BBBBbbbb */ - movl 2(rPC), %eax # eax <- BBBBbbbb - movl rIBASE, %ecx # preserve rIBASE (cltd trashes it) - cltd # rIBASE:eax <- ssssssssssssBBBB - SET_VREG_HIGH rIBASE, rINST # store msw - SET_VREG %eax, rINST # store lsw - movl %ecx, rIBASE # restore rIBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 diff --git a/runtime/interpreter/mterp/x86/op_const_wide_high16.S b/runtime/interpreter/mterp/x86/op_const_wide_high16.S deleted file mode 100644 index 11b9310be54224c4392ce2550d3732925cd8d307..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_const_wide_high16.S +++ /dev/null @@ -1,7 +0,0 @@ - /* const-wide/high16 vAA, #+BBBB000000000000 */ - movzwl 2(rPC), %eax # eax <- 0000BBBB - sall $$16, %eax # eax <- BBBB0000 - SET_VREG_HIGH %eax, rINST # v[AA+1] <- eax - xorl %eax, %eax - SET_VREG %eax, rINST # v[AA+0] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_div_double.S b/runtime/interpreter/mterp/x86/op_div_double.S deleted file mode 100644 index 575716dc9d7ace76ed1ae6b500579e417ab68796..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_div_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/sseBinop.S" {"instr":"divs","suff":"d"} diff --git a/runtime/interpreter/mterp/x86/op_div_double_2addr.S b/runtime/interpreter/mterp/x86/op_div_double_2addr.S deleted file mode 100644 index 8229a31d6740793473ceeff0a36633fdb2c97310..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_div_double_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/sseBinop2Addr.S" {"instr":"divs","suff":"d"} diff --git a/runtime/interpreter/mterp/x86/op_div_float.S b/runtime/interpreter/mterp/x86/op_div_float.S deleted file mode 100644 index 250f1dccc6ac7329b8ca3c796af17db5d1c019df..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_div_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/sseBinop.S" {"instr":"divs","suff":"s"} diff --git a/runtime/interpreter/mterp/x86/op_div_float_2addr.S b/runtime/interpreter/mterp/x86/op_div_float_2addr.S deleted file mode 100644 index c30d148356e21e9ddc0bfc812dcbbc71c339c983..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_div_float_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/sseBinop2Addr.S" {"instr":"divs","suff":"s"} diff --git a/runtime/interpreter/mterp/x86/op_div_int.S b/runtime/interpreter/mterp/x86/op_div_int.S deleted file mode 100644 index 5fc8fa519e5b020982a757833bcbbbb92e28ddc6..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_div_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/bindiv.S" {"result":"%eax","special":"$0x80000000","rem":"0"} diff --git a/runtime/interpreter/mterp/x86/op_div_int_2addr.S b/runtime/interpreter/mterp/x86/op_div_int_2addr.S deleted file mode 100644 index 04cf1bae6a4c12d44c6ee05130429192e4de52f4..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_div_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/bindiv2addr.S" {"result":"%eax","special":"$0x80000000"} diff --git a/runtime/interpreter/mterp/x86/op_div_int_lit16.S b/runtime/interpreter/mterp/x86/op_div_int_lit16.S deleted file mode 100644 index dd396bb68a7b74548cc78f22f8f282d02a0da2aa..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_div_int_lit16.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/bindivLit16.S" {"result":"%eax","special":"$0x80000000"} diff --git a/runtime/interpreter/mterp/x86/op_div_int_lit8.S b/runtime/interpreter/mterp/x86/op_div_int_lit8.S deleted file mode 100644 index 3cbd9d0cf517f0f595363d1b05959e453153bd43..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_div_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/bindivLit8.S" {"result":"%eax","special":"$0x80000000"} diff --git a/runtime/interpreter/mterp/x86/op_div_long.S b/runtime/interpreter/mterp/x86/op_div_long.S deleted file mode 100644 index e56a035f1dc15803244da0b04917e3d015c9dfd0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_div_long.S +++ /dev/null @@ -1,23 +0,0 @@ -%default {"routine":"art_quick_ldiv"} -/* art_quick_* methods has quick abi, - * so use eax, ecx, edx, ebx for args - */ - /* div vAA, vBB, vCC */ - .extern $routine - mov rIBASE, LOCAL0(%esp) # save rIBASE/%edx - mov rINST, LOCAL1(%esp) # save rINST/%ebx - movzbl 3(rPC), %eax # eax <- CC - GET_VREG %ecx, %eax - GET_VREG_HIGH %ebx, %eax - movl %ecx, %edx - orl %ebx, %ecx - jz common_errDivideByZero - movzbl 2(rPC), %eax # eax <- BB - GET_VREG_HIGH %ecx, %eax - GET_VREG %eax, %eax - call SYMBOL($routine) - mov LOCAL1(%esp), rINST # restore rINST/%ebx - SET_VREG_HIGH rIBASE, rINST - SET_VREG %eax, rINST - mov LOCAL0(%esp), rIBASE # restore rIBASE/%edx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_div_long_2addr.S b/runtime/interpreter/mterp/x86/op_div_long_2addr.S deleted file mode 100644 index 159cc44444b910c72d85ff52c0e2c02e88b6ac69..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_div_long_2addr.S +++ /dev/null @@ -1,25 +0,0 @@ -%default {"routine":"art_quick_ldiv"} -/* art_quick_* methods has quick abi, - * so use eax, ecx, edx, ebx for args - */ - /* div/2addr vA, vB */ - .extern $routine - mov rIBASE, LOCAL0(%esp) # save rIBASE/%edx - movzbl rINSTbl, %eax - shrl $$4, %eax # eax <- B - andb $$0xf, rINSTbl # rINST <- A - mov rINST, LOCAL1(%esp) # save rINST/%ebx - movl %ebx, %ecx - GET_VREG %edx, %eax - GET_VREG_HIGH %ebx, %eax - movl %edx, %eax - orl %ebx, %eax - jz common_errDivideByZero - GET_VREG %eax, %ecx - GET_VREG_HIGH %ecx, %ecx - call SYMBOL($routine) - mov LOCAL1(%esp), rINST # restore rINST/%ebx - SET_VREG_HIGH rIBASE, rINST - SET_VREG %eax, rINST - mov LOCAL0(%esp), rIBASE # restore rIBASE/%edx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/op_double_to_float.S b/runtime/interpreter/mterp/x86/op_double_to_float.S deleted file mode 100644 index 5135d60ed7244d4a99b7abd5e0c59e1deb9caeab..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_double_to_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/fpcvt.S" {"load":"fldl","store":"fstps"} diff --git a/runtime/interpreter/mterp/x86/op_double_to_int.S b/runtime/interpreter/mterp/x86/op_double_to_int.S deleted file mode 100644 index 9c4e11cf9e122a559212f101b67d3a8fef161ef6..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_double_to_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/cvtfp_int.S" {"srcdouble":"1","tgtlong":"0"} diff --git a/runtime/interpreter/mterp/x86/op_double_to_long.S b/runtime/interpreter/mterp/x86/op_double_to_long.S deleted file mode 100644 index fe0eee24d0a294a65abfa9cb4986befcc80cba31..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_double_to_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/cvtfp_int.S" {"srcdouble":"1","tgtlong":"1"} diff --git a/runtime/interpreter/mterp/x86/op_fill_array_data.S b/runtime/interpreter/mterp/x86/op_fill_array_data.S deleted file mode 100644 index 585528490122d6a71fb74f02ac4fb10c4840c07d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_fill_array_data.S +++ /dev/null @@ -1,12 +0,0 @@ - /* fill-array-data vAA, +BBBBBBBB */ - EXPORT_PC - movl 2(rPC), %ecx # ecx <- BBBBbbbb - leal (rPC,%ecx,2), %ecx # ecx <- PC + BBBBbbbb*2 - GET_VREG %eax, rINST # eax <- vAA (array object) - movl %eax, OUT_ARG0(%esp) - movl %ecx, OUT_ARG1(%esp) - call SYMBOL(MterpFillArrayData) # (obj, payload) - REFRESH_IBASE - testb %al, %al # 0 means an exception is thrown - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 diff --git a/runtime/interpreter/mterp/x86/op_filled_new_array.S b/runtime/interpreter/mterp/x86/op_filled_new_array.S deleted file mode 100644 index 35b2fe8dfc9f765bb4cf9bfa39ed77b427ca829e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_filled_new_array.S +++ /dev/null @@ -1,20 +0,0 @@ -%default { "helper":"MterpFilledNewArray" } -/* - * Create a new array with elements filled from registers. - * - * for: filled-new-array, filled-new-array/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ - .extern $helper - EXPORT_PC - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG0(%esp) - movl rPC, OUT_ARG1(%esp) - movl rSELF, %ecx - movl %ecx, OUT_ARG2(%esp) - call SYMBOL($helper) - REFRESH_IBASE - testb %al, %al # 0 means an exception is thrown - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 diff --git a/runtime/interpreter/mterp/x86/op_filled_new_array_range.S b/runtime/interpreter/mterp/x86/op_filled_new_array_range.S deleted file mode 100644 index 841059e4e210314320cf62f6b7acce60f3de9059..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_filled_new_array_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_filled_new_array.S" { "helper":"MterpFilledNewArrayRange" } diff --git a/runtime/interpreter/mterp/x86/op_float_to_double.S b/runtime/interpreter/mterp/x86/op_float_to_double.S deleted file mode 100644 index 12a3e14caa86f68da9516a09ba12a3d64790a61e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_float_to_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/fpcvt.S" {"load":"flds","store":"fstpl","wide":"1"} diff --git a/runtime/interpreter/mterp/x86/op_float_to_int.S b/runtime/interpreter/mterp/x86/op_float_to_int.S deleted file mode 100644 index ac57388744ccdaca71a344d8fa67736f34a500c9..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_float_to_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/cvtfp_int.S" {"srcdouble":"0","tgtlong":"0"} diff --git a/runtime/interpreter/mterp/x86/op_float_to_long.S b/runtime/interpreter/mterp/x86/op_float_to_long.S deleted file mode 100644 index be1d9821b3271f07ce28df266271ccca0a543a2a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_float_to_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/cvtfp_int.S" {"srcdouble":"0","tgtlong":"1"} diff --git a/runtime/interpreter/mterp/x86/op_goto.S b/runtime/interpreter/mterp/x86/op_goto.S deleted file mode 100644 index 1827d68eed11f5a0436955a7d021460446bf2efb..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_goto.S +++ /dev/null @@ -1,10 +0,0 @@ -/* - * Unconditional branch, 8-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto +AA */ - movsbl rINSTbl, rINST # rINST <- ssssssAA - testl rINST, rINST - jmp MterpCommonTakenBranch diff --git a/runtime/interpreter/mterp/x86/op_goto_16.S b/runtime/interpreter/mterp/x86/op_goto_16.S deleted file mode 100644 index ea5ea9001fc848e89cf3d538e2aa316d9b9d4f51..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_goto_16.S +++ /dev/null @@ -1,10 +0,0 @@ -/* - * Unconditional branch, 16-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto/16 +AAAA */ - movswl 2(rPC), rINST # rINST <- ssssAAAA - testl rINST, rINST - jmp MterpCommonTakenBranch diff --git a/runtime/interpreter/mterp/x86/op_goto_32.S b/runtime/interpreter/mterp/x86/op_goto_32.S deleted file mode 100644 index 4becaf34b1d64b6ba2d66b15e0ed54c14e663138..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_goto_32.S +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Unconditional branch, 32-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - * - * Unlike most opcodes, this one is allowed to branch to itself, so - * our "backward branch" test must be "<=0" instead of "<0". Because - * we need the V bit set, we'll use an adds to convert from Dalvik - * offset to byte offset. - */ - /* goto/32 +AAAAAAAA */ - movl 2(rPC), rINST # rINST <- AAAAAAAA - testl rINST, rINST - jmp MterpCommonTakenBranch diff --git a/runtime/interpreter/mterp/x86/op_if_eq.S b/runtime/interpreter/mterp/x86/op_if_eq.S deleted file mode 100644 index 5413d98580820739ae23c4f9cf1690ed8391f53d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_if_eq.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/bincmp.S" { "revcmp":"ne" } diff --git a/runtime/interpreter/mterp/x86/op_if_eqz.S b/runtime/interpreter/mterp/x86/op_if_eqz.S deleted file mode 100644 index 53dc99ef9051351cd1a0e6b2b08f020181f4a695..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_if_eqz.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/zcmp.S" { "revcmp":"ne" } diff --git a/runtime/interpreter/mterp/x86/op_if_ge.S b/runtime/interpreter/mterp/x86/op_if_ge.S deleted file mode 100644 index c2ba3c6d5187b4c07156c713e8bf52f9bce29f09..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_if_ge.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/bincmp.S" { "revcmp":"l" } diff --git a/runtime/interpreter/mterp/x86/op_if_gez.S b/runtime/interpreter/mterp/x86/op_if_gez.S deleted file mode 100644 index cd2c77237d8fb0689ddcfb269c4b3e89c0334fe1..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_if_gez.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/zcmp.S" { "revcmp":"l" } diff --git a/runtime/interpreter/mterp/x86/op_if_gt.S b/runtime/interpreter/mterp/x86/op_if_gt.S deleted file mode 100644 index 9fe84bb786ecc6f7eca50498954e8911ed563816..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_if_gt.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/bincmp.S" { "revcmp":"le" } diff --git a/runtime/interpreter/mterp/x86/op_if_gtz.S b/runtime/interpreter/mterp/x86/op_if_gtz.S deleted file mode 100644 index b454ffdb34b1c7317b2438f03e4c89fd96a0db0a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_if_gtz.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/zcmp.S" { "revcmp":"le" } diff --git a/runtime/interpreter/mterp/x86/op_if_le.S b/runtime/interpreter/mterp/x86/op_if_le.S deleted file mode 100644 index 93571a7083a71578b04e971d65277140246ae658..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_if_le.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/bincmp.S" { "revcmp":"g" } diff --git a/runtime/interpreter/mterp/x86/op_if_lez.S b/runtime/interpreter/mterp/x86/op_if_lez.S deleted file mode 100644 index 779c77f2be792a5340d70b30b89049008a58394a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_if_lez.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/zcmp.S" { "revcmp":"g" } diff --git a/runtime/interpreter/mterp/x86/op_if_lt.S b/runtime/interpreter/mterp/x86/op_if_lt.S deleted file mode 100644 index 1fb15210548490780072f1a27b4bc1c0f6497800..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_if_lt.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/bincmp.S" { "revcmp":"ge" } diff --git a/runtime/interpreter/mterp/x86/op_if_ltz.S b/runtime/interpreter/mterp/x86/op_if_ltz.S deleted file mode 100644 index 155c356e4c98f72ac4daa7f74c0957becba45736..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_if_ltz.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/zcmp.S" { "revcmp":"ge" } diff --git a/runtime/interpreter/mterp/x86/op_if_ne.S b/runtime/interpreter/mterp/x86/op_if_ne.S deleted file mode 100644 index 7e1b065fc09ae9face8b01be86e1c1c03c2dfe65..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_if_ne.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/bincmp.S" { "revcmp":"e" } diff --git a/runtime/interpreter/mterp/x86/op_if_nez.S b/runtime/interpreter/mterp/x86/op_if_nez.S deleted file mode 100644 index 8951f5b19fe444c9710c1488c9c5595746800a4d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_if_nez.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/zcmp.S" { "revcmp":"e" } diff --git a/runtime/interpreter/mterp/x86/op_iget.S b/runtime/interpreter/mterp/x86/op_iget.S deleted file mode 100644 index d85d54c51522b1ecd9a1c2bb66e741f9b0d2cb43..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_iget.S +++ /dev/null @@ -1,2 +0,0 @@ -%default { "is_object":"0", "helper":"MterpIGetU32"} -%include "x86/field.S" { } diff --git a/runtime/interpreter/mterp/x86/op_iget_boolean.S b/runtime/interpreter/mterp/x86/op_iget_boolean.S deleted file mode 100644 index ddccc41cda9ff92bc2e98153ad8037adb8bcd4b1..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_iget_boolean.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_iget.S" { "helper":"MterpIGetU8" } diff --git a/runtime/interpreter/mterp/x86/op_iget_boolean_quick.S b/runtime/interpreter/mterp/x86/op_iget_boolean_quick.S deleted file mode 100644 index 02b0c16cf2c2d727c2e469c17c1ceb6cc9f8299c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_iget_boolean_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_iget_quick.S" { "load":"movsbl" } diff --git a/runtime/interpreter/mterp/x86/op_iget_byte.S b/runtime/interpreter/mterp/x86/op_iget_byte.S deleted file mode 100644 index cd46d3de082877f28ff5f1dda6b430f8bea68274..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_iget_byte.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_iget.S" { "helper":"MterpIGetI8" } diff --git a/runtime/interpreter/mterp/x86/op_iget_byte_quick.S b/runtime/interpreter/mterp/x86/op_iget_byte_quick.S deleted file mode 100644 index 02b0c16cf2c2d727c2e469c17c1ceb6cc9f8299c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_iget_byte_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_iget_quick.S" { "load":"movsbl" } diff --git a/runtime/interpreter/mterp/x86/op_iget_char.S b/runtime/interpreter/mterp/x86/op_iget_char.S deleted file mode 100644 index 99697349aebad51fa0df6ac17a43107a292956be..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_iget_char.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_iget.S" { "helper":"MterpIGetU16" } diff --git a/runtime/interpreter/mterp/x86/op_iget_char_quick.S b/runtime/interpreter/mterp/x86/op_iget_char_quick.S deleted file mode 100644 index a5d971278d6a4d4c7b66d341fd7f7927c3ce9bae..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_iget_char_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_iget_quick.S" { "load":"movzwl" } diff --git a/runtime/interpreter/mterp/x86/op_iget_object.S b/runtime/interpreter/mterp/x86/op_iget_object.S deleted file mode 100644 index 3d421fcf7fb2919d55074f325593bededa67db0b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_iget_object.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_iget.S" { "is_object":"1", "helper":"MterpIGetObj" } diff --git a/runtime/interpreter/mterp/x86/op_iget_object_quick.S b/runtime/interpreter/mterp/x86/op_iget_object_quick.S deleted file mode 100644 index b1551a01795021de057e28000cb8e8079e1761f5..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_iget_object_quick.S +++ /dev/null @@ -1,17 +0,0 @@ - /* For: iget-object-quick */ - /* op vA, vB, offset@CCCC */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $$4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # vB (object we're operating on) - movzwl 2(rPC), %eax # eax <- field byte offset - movl %ecx, OUT_ARG0(%esp) - movl %eax, OUT_ARG1(%esp) - EXPORT_PC - call SYMBOL(artIGetObjectFromMterp) # (obj, offset) - movl rSELF, %ecx - RESTORE_IBASE_FROM_SELF %ecx - cmpl $$0, THREAD_EXCEPTION_OFFSET(%ecx) - jnz MterpException # bail out - andb $$0xf,rINSTbl # rINST <- A - SET_VREG_OBJECT %eax, rINST # fp[A] <- value - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_iget_quick.S b/runtime/interpreter/mterp/x86/op_iget_quick.S deleted file mode 100644 index 1b7440fc9ad6a585224df206e50b0d6a9ed39bc2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_iget_quick.S +++ /dev/null @@ -1,13 +0,0 @@ -%default { "load":"movl"} - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ - /* op vA, vB, offset@CCCC */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $$4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # vB (object we're operating on) - movzwl 2(rPC), %eax # eax <- field byte offset - testl %ecx, %ecx # is object null? - je common_errNullObject - ${load} (%ecx,%eax,1), %eax - andb $$0xf,rINSTbl # rINST <- A - SET_VREG %eax, rINST # fp[A] <- value - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_iget_short.S b/runtime/interpreter/mterp/x86/op_iget_short.S deleted file mode 100644 index c7477f5db34f894ac6ad0f888217a2d8a023d561..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_iget_short.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_iget.S" { "helper":"MterpIGetI16" } diff --git a/runtime/interpreter/mterp/x86/op_iget_short_quick.S b/runtime/interpreter/mterp/x86/op_iget_short_quick.S deleted file mode 100644 index 2c3aeb67eb45e79a438edcb9bc93ae9aedaebb8e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_iget_short_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_iget_quick.S" { "load":"movswl" } diff --git a/runtime/interpreter/mterp/x86/op_iget_wide.S b/runtime/interpreter/mterp/x86/op_iget_wide.S deleted file mode 100644 index 741a64e4cb7e3ac897919b16b2f142e0ec97c163..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_iget_wide.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_iget.S" { "helper":"MterpIGetU64" } diff --git a/runtime/interpreter/mterp/x86/op_iget_wide_quick.S b/runtime/interpreter/mterp/x86/op_iget_wide_quick.S deleted file mode 100644 index 7ce74cc71bf332b1d89cbde41d3e816290a325a8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_iget_wide_quick.S +++ /dev/null @@ -1,11 +0,0 @@ - /* iget-wide-quick vA, vB, offset@CCCC */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $$4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # vB (object we're operating on) - movzwl 2(rPC), %eax # eax <- field byte offset - testl %ecx, %ecx # is object null? - je common_errNullObject - movq (%ecx,%eax,1), %xmm0 - andb $$0xf, rINSTbl # rINST <- A - SET_WIDE_FP_VREG %xmm0, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_instance_of.S b/runtime/interpreter/mterp/x86/op_instance_of.S deleted file mode 100644 index e6fe5b2cecf694d90e73b7500ff1da65126df94f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_instance_of.S +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Check to see if an object reference is an instance of a class. - * - * Most common situation is a non-null object, being compared against - * an already-resolved class. - */ - /* instance-of vA, vB, class@CCCC */ - EXPORT_PC - movzwl 2(rPC), %eax # eax <- BBBB - movl %eax, OUT_ARG0(%esp) - movl rINST, %eax # eax <- BA - sarl $$4, %eax # eax <- B - leal VREG_ADDRESS(%eax), %ecx # Get object address - movl %ecx, OUT_ARG1(%esp) - movl OFF_FP_METHOD(rFP),%eax - movl %eax, OUT_ARG2(%esp) - movl rSELF, %ecx - movl %ecx, OUT_ARG3(%esp) - call SYMBOL(MterpInstanceOf) # (index, &obj, method, self) - movl rSELF, %ecx - RESTORE_IBASE_FROM_SELF %ecx - cmpl $$0, THREAD_EXCEPTION_OFFSET(%ecx) - jnz MterpException - andb $$0xf, rINSTbl # rINSTbl <- A - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_int_to_byte.S b/runtime/interpreter/mterp/x86/op_int_to_byte.S deleted file mode 100644 index b4e8d22c98d1289e8ff93e2011c6abefa2b6814b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_int_to_byte.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/unop.S" {"instr":"movsbl %al, %eax"} diff --git a/runtime/interpreter/mterp/x86/op_int_to_char.S b/runtime/interpreter/mterp/x86/op_int_to_char.S deleted file mode 100644 index 4608971469f9c8e17edb03ad8ec9bde89312269a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_int_to_char.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/unop.S" {"instr":"movzwl %ax,%eax"} diff --git a/runtime/interpreter/mterp/x86/op_int_to_double.S b/runtime/interpreter/mterp/x86/op_int_to_double.S deleted file mode 100644 index 3e9921eb8f83d4f05e3e6111ddb6bdcabdca9856..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_int_to_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/fpcvt.S" {"load":"fildl","store":"fstpl","wide":"1"} diff --git a/runtime/interpreter/mterp/x86/op_int_to_float.S b/runtime/interpreter/mterp/x86/op_int_to_float.S deleted file mode 100644 index 849540da09cbcaabbe8960c07726c3c5d0a2883a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_int_to_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/fpcvt.S" {"load":"fildl","store":"fstps"} diff --git a/runtime/interpreter/mterp/x86/op_int_to_long.S b/runtime/interpreter/mterp/x86/op_int_to_long.S deleted file mode 100644 index 6f9ea269f4ddccbe30b0b942b957f730fe0e970a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_int_to_long.S +++ /dev/null @@ -1,12 +0,0 @@ - /* int to long vA, vB */ - movzbl rINSTbl, %eax # eax <- +A - sarl $$4, %eax # eax <- B - GET_VREG %eax, %eax # eax <- vB - andb $$0xf, rINSTbl # rINST <- A - movl rIBASE, %ecx # cltd trashes rIBASE/edx - cltd # rINST:eax<- sssssssBBBBBBBB - SET_VREG_HIGH rIBASE, rINST # v[A+1] <- rIBASE - SET_VREG %eax, rINST # v[A+0] <- %eax - movl %ecx, rIBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - diff --git a/runtime/interpreter/mterp/x86/op_int_to_short.S b/runtime/interpreter/mterp/x86/op_int_to_short.S deleted file mode 100644 index 90d0ae65b1da895dcc36e56fcdb2649038427776..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_int_to_short.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/unop.S" {"instr":"movswl %ax, %eax"} diff --git a/runtime/interpreter/mterp/x86/op_invoke_custom.S b/runtime/interpreter/mterp/x86/op_invoke_custom.S deleted file mode 100644 index eddd5b33a329cb5b095b4eb0e232a03000f23686..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_invoke_custom.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/invoke.S" { "helper":"MterpInvokeCustom" } diff --git a/runtime/interpreter/mterp/x86/op_invoke_custom_range.S b/runtime/interpreter/mterp/x86/op_invoke_custom_range.S deleted file mode 100644 index 1a4e884166b9eaa8e2404d3ae0cd52ca8fac1e12..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_invoke_custom_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/invoke.S" { "helper":"MterpInvokeCustomRange" } diff --git a/runtime/interpreter/mterp/x86/op_invoke_direct.S b/runtime/interpreter/mterp/x86/op_invoke_direct.S deleted file mode 100644 index 76fb9a6786db01ef130616773ae418e28f242f75..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_invoke_direct.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/invoke.S" { "helper":"MterpInvokeDirect" } diff --git a/runtime/interpreter/mterp/x86/op_invoke_direct_range.S b/runtime/interpreter/mterp/x86/op_invoke_direct_range.S deleted file mode 100644 index a6ab6049f537d65db8d9d141fe3f2a7ee72f5357..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_invoke_direct_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/invoke.S" { "helper":"MterpInvokeDirectRange" } diff --git a/runtime/interpreter/mterp/x86/op_invoke_interface.S b/runtime/interpreter/mterp/x86/op_invoke_interface.S deleted file mode 100644 index 91c24f5db63887039333ee3ce4ca82d95a6bfdc8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_invoke_interface.S +++ /dev/null @@ -1,8 +0,0 @@ -%include "x86/invoke.S" { "helper":"MterpInvokeInterface" } -/* - * Handle an interface method call. - * - * for: invoke-interface, invoke-interface/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ diff --git a/runtime/interpreter/mterp/x86/op_invoke_interface_range.S b/runtime/interpreter/mterp/x86/op_invoke_interface_range.S deleted file mode 100644 index e478beb596dedcacb85458e3b8f36efd76f5118f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_invoke_interface_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/invoke.S" { "helper":"MterpInvokeInterfaceRange" } diff --git a/runtime/interpreter/mterp/x86/op_invoke_polymorphic.S b/runtime/interpreter/mterp/x86/op_invoke_polymorphic.S deleted file mode 100644 index 3907689476c28a01166a0d90ddd00c197c19cffa..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_invoke_polymorphic.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/invoke_polymorphic.S" { "helper":"MterpInvokePolymorphic" } diff --git a/runtime/interpreter/mterp/x86/op_invoke_polymorphic_range.S b/runtime/interpreter/mterp/x86/op_invoke_polymorphic_range.S deleted file mode 100644 index 59a823076dec67ef102f056568bec30fb83f14ff..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_invoke_polymorphic_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/invoke_polymorphic.S" { "helper":"MterpInvokePolymorphicRange" } diff --git a/runtime/interpreter/mterp/x86/op_invoke_static.S b/runtime/interpreter/mterp/x86/op_invoke_static.S deleted file mode 100644 index b4c1236f7a3b77a1b6c512c0759aa19a3aa752a3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_invoke_static.S +++ /dev/null @@ -1,2 +0,0 @@ -%include "x86/invoke.S" { "helper":"MterpInvokeStatic" } - diff --git a/runtime/interpreter/mterp/x86/op_invoke_static_range.S b/runtime/interpreter/mterp/x86/op_invoke_static_range.S deleted file mode 100644 index 3dc8a26856b794d15898932108cb67d51d4e4647..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_invoke_static_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/invoke.S" { "helper":"MterpInvokeStaticRange" } diff --git a/runtime/interpreter/mterp/x86/op_invoke_super.S b/runtime/interpreter/mterp/x86/op_invoke_super.S deleted file mode 100644 index be20edd07c0c468c2b252cfce86622770db4f76e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_invoke_super.S +++ /dev/null @@ -1,8 +0,0 @@ -%include "x86/invoke.S" { "helper":"MterpInvokeSuper" } -/* - * Handle a "super" method call. - * - * for: invoke-super, invoke-super/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ diff --git a/runtime/interpreter/mterp/x86/op_invoke_super_range.S b/runtime/interpreter/mterp/x86/op_invoke_super_range.S deleted file mode 100644 index f36bf72bcfa8af7538f1a0d91d31491a1608ecf0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_invoke_super_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/invoke.S" { "helper":"MterpInvokeSuperRange" } diff --git a/runtime/interpreter/mterp/x86/op_invoke_virtual.S b/runtime/interpreter/mterp/x86/op_invoke_virtual.S deleted file mode 100644 index 7e9c456a95f83bd840ef4c8b5dfa2e8997666604..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_invoke_virtual.S +++ /dev/null @@ -1,8 +0,0 @@ -%include "x86/invoke.S" { "helper":"MterpInvokeVirtual" } -/* - * Handle a virtual method call. - * - * for: invoke-virtual, invoke-virtual/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ diff --git a/runtime/interpreter/mterp/x86/op_invoke_virtual_quick.S b/runtime/interpreter/mterp/x86/op_invoke_virtual_quick.S deleted file mode 100644 index 2dc9ab6298df635ebb95ef816a53bebf8b644437..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_invoke_virtual_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/invoke.S" { "helper":"MterpInvokeVirtualQuick" } diff --git a/runtime/interpreter/mterp/x86/op_invoke_virtual_range.S b/runtime/interpreter/mterp/x86/op_invoke_virtual_range.S deleted file mode 100644 index d1d20d29ac7f9bb745c7b78b0bf51125f768fdc5..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_invoke_virtual_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/invoke.S" { "helper":"MterpInvokeVirtualRange" } diff --git a/runtime/interpreter/mterp/x86/op_invoke_virtual_range_quick.S b/runtime/interpreter/mterp/x86/op_invoke_virtual_range_quick.S deleted file mode 100644 index 21bfc55b731e57f17fb9e38f2bd1fac5cb5bee11..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_invoke_virtual_range_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/invoke.S" { "helper":"MterpInvokeVirtualQuickRange" } diff --git a/runtime/interpreter/mterp/x86/op_iput.S b/runtime/interpreter/mterp/x86/op_iput.S deleted file mode 100644 index 3628ffdb56ef0bbdc184e8cce24fc26aae0ed1df..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_iput.S +++ /dev/null @@ -1,2 +0,0 @@ -%default { "is_object":"0", "helper":"MterpIPutU32" } -%include "x86/field.S" { } diff --git a/runtime/interpreter/mterp/x86/op_iput_boolean.S b/runtime/interpreter/mterp/x86/op_iput_boolean.S deleted file mode 100644 index fdd530374e2053255eda4fa724fb0042d2d3ad79..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_iput_boolean.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_iput.S" { "helper":"MterpIPutU8" } diff --git a/runtime/interpreter/mterp/x86/op_iput_boolean_quick.S b/runtime/interpreter/mterp/x86/op_iput_boolean_quick.S deleted file mode 100644 index 93865de169c965d8104563a215267ca2f8b6ae05..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_iput_boolean_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_iput_quick.S" { "reg":"rINSTbl", "store":"movb" } diff --git a/runtime/interpreter/mterp/x86/op_iput_byte.S b/runtime/interpreter/mterp/x86/op_iput_byte.S deleted file mode 100644 index b81850c5384ce798f0b1a7af4cea5dc8a86a0366..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_iput_byte.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_iput.S" { "helper":"MterpIPutI8" } diff --git a/runtime/interpreter/mterp/x86/op_iput_byte_quick.S b/runtime/interpreter/mterp/x86/op_iput_byte_quick.S deleted file mode 100644 index 93865de169c965d8104563a215267ca2f8b6ae05..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_iput_byte_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_iput_quick.S" { "reg":"rINSTbl", "store":"movb" } diff --git a/runtime/interpreter/mterp/x86/op_iput_char.S b/runtime/interpreter/mterp/x86/op_iput_char.S deleted file mode 100644 index dde385371e59aae452ec69d15970d555c1225f60..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_iput_char.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_iput.S" { "helper":"MterpIPutU16" } diff --git a/runtime/interpreter/mterp/x86/op_iput_char_quick.S b/runtime/interpreter/mterp/x86/op_iput_char_quick.S deleted file mode 100644 index 4ec80290c6a3b492857aba7ab87d85a60db5ad1f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_iput_char_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_iput_quick.S" { "reg":"rINSTw", "store":"movw" } diff --git a/runtime/interpreter/mterp/x86/op_iput_object.S b/runtime/interpreter/mterp/x86/op_iput_object.S deleted file mode 100644 index a124b7ed410db421c846f19e7d6fe06e558f0664..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_iput_object.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_iput.S" { "is_object":"1", "helper":"MterpIPutObj" } diff --git a/runtime/interpreter/mterp/x86/op_iput_object_quick.S b/runtime/interpreter/mterp/x86/op_iput_object_quick.S deleted file mode 100644 index cb779295b7beb2dc7e6d732dda7c831efc139f77..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_iput_object_quick.S +++ /dev/null @@ -1,11 +0,0 @@ - EXPORT_PC - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG0(%esp) - movl rPC, OUT_ARG1(%esp) - REFRESH_INST ${opnum} - movl rINST, OUT_ARG2(%esp) - call SYMBOL(MterpIputObjectQuick) - testb %al, %al - jz MterpException - RESTORE_IBASE - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_iput_quick.S b/runtime/interpreter/mterp/x86/op_iput_quick.S deleted file mode 100644 index b67cee08594b47ff07f750b5cdd3dbe9264efae8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_iput_quick.S +++ /dev/null @@ -1,13 +0,0 @@ -%default { "reg":"rINST", "store":"movl" } - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $$4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # vB (object we're operating on) - testl %ecx, %ecx # is object null? - je common_errNullObject - andb $$0xf, rINSTbl # rINST <- A - GET_VREG rINST, rINST # rINST <- v[A] - movzwl 2(rPC), %eax # eax <- field byte offset - ${store} ${reg}, (%ecx,%eax,1) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_iput_short.S b/runtime/interpreter/mterp/x86/op_iput_short.S deleted file mode 100644 index 130e875bb22d7e9fb50285f68353bb462218f17c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_iput_short.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_iput.S" { "helper":"MterpIPutI16" } diff --git a/runtime/interpreter/mterp/x86/op_iput_short_quick.S b/runtime/interpreter/mterp/x86/op_iput_short_quick.S deleted file mode 100644 index 4ec80290c6a3b492857aba7ab87d85a60db5ad1f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_iput_short_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_iput_quick.S" { "reg":"rINSTw", "store":"movw" } diff --git a/runtime/interpreter/mterp/x86/op_iput_wide.S b/runtime/interpreter/mterp/x86/op_iput_wide.S deleted file mode 100644 index 2820ede182975e5d1c5ec9659cba34fea633ac09..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_iput_wide.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_iput.S" { "helper":"MterpIPutU64" } diff --git a/runtime/interpreter/mterp/x86/op_iput_wide_quick.S b/runtime/interpreter/mterp/x86/op_iput_wide_quick.S deleted file mode 100644 index 17de6f8502111712bedc4da2234da80d308ffad6..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_iput_wide_quick.S +++ /dev/null @@ -1,12 +0,0 @@ - /* iput-wide-quick vA, vB, offset@CCCC */ - movzbl rINSTbl, %ecx # ecx<- BA - sarl $$4, %ecx # ecx<- B - GET_VREG %ecx, %ecx # vB (object we're operating on) - testl %ecx, %ecx # is object null? - je common_errNullObject - movzwl 2(rPC), %eax # eax<- field byte offset - leal (%ecx,%eax,1), %ecx # ecx<- Address of 64-bit target - andb $$0xf, rINSTbl # rINST<- A - GET_WIDE_FP_VREG %xmm0, rINST # xmm0<- fp[A]/fp[A+1] - movq %xmm0, (%ecx) # obj.field<- r0/r1 - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_long_to_double.S b/runtime/interpreter/mterp/x86/op_long_to_double.S deleted file mode 100644 index 2c7f90525974226632c4f9caf8c3711bdb439db5..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_long_to_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/fpcvt.S" {"load":"fildll","store":"fstpl","wide":"1"} diff --git a/runtime/interpreter/mterp/x86/op_long_to_float.S b/runtime/interpreter/mterp/x86/op_long_to_float.S deleted file mode 100644 index e500e39d46b12682b8ad302a3127cfb18e87493e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_long_to_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/fpcvt.S" {"load":"fildll","store":"fstps"} diff --git a/runtime/interpreter/mterp/x86/op_long_to_int.S b/runtime/interpreter/mterp/x86/op_long_to_int.S deleted file mode 100644 index 1c39b96d5c9a8c76eb910aa38ccdda42455d4de8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_long_to_int.S +++ /dev/null @@ -1,2 +0,0 @@ -/* we ignore the high word, making this equivalent to a 32-bit reg move */ -%include "x86/op_move.S" diff --git a/runtime/interpreter/mterp/x86/op_monitor_enter.S b/runtime/interpreter/mterp/x86/op_monitor_enter.S deleted file mode 100644 index b35c68488aecc46d750216972f29713ba16aea1a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_monitor_enter.S +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Synchronize on an object. - */ - /* monitor-enter vAA */ - EXPORT_PC - GET_VREG %ecx, rINST - movl %ecx, OUT_ARG0(%esp) - movl rSELF, %eax - movl %eax, OUT_ARG1(%esp) - call SYMBOL(artLockObjectFromCode) # (object, self) - RESTORE_IBASE - testb %al, %al - jnz MterpException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/op_monitor_exit.S b/runtime/interpreter/mterp/x86/op_monitor_exit.S deleted file mode 100644 index 2d17d5e7c55e386579f236839e10c1aac91754fa..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_monitor_exit.S +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Unlock an object. - * - * Exceptions that occur when unlocking a monitor need to appear as - * if they happened at the following instruction. See the Dalvik - * instruction spec. - */ - /* monitor-exit vAA */ - EXPORT_PC - GET_VREG %ecx, rINST - movl %ecx, OUT_ARG0(%esp) - movl rSELF, %eax - movl %eax, OUT_ARG1(%esp) - call SYMBOL(artUnlockObjectFromCode) # (object, self) - RESTORE_IBASE - testb %al, %al - jnz MterpException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/op_move.S b/runtime/interpreter/mterp/x86/op_move.S deleted file mode 100644 index ea173b97d6e809ae5ce44b20e3b6ad9e3ffb8023..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_move.S +++ /dev/null @@ -1,13 +0,0 @@ -%default { "is_object":"0" } - /* for move, move-object, long-to-int */ - /* op vA, vB */ - movzbl rINSTbl, %eax # eax <- BA - andb $$0xf, %al # eax <- A - shrl $$4, rINST # rINST <- B - GET_VREG rINST, rINST - .if $is_object - SET_VREG_OBJECT rINST, %eax # fp[A] <- fp[B] - .else - SET_VREG rINST, %eax # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/op_move_16.S b/runtime/interpreter/mterp/x86/op_move_16.S deleted file mode 100644 index 454deb5d08971399f3a45d2b19442ed2b9d1c82c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_move_16.S +++ /dev/null @@ -1,12 +0,0 @@ -%default { "is_object":"0" } - /* for: move/16, move-object/16 */ - /* op vAAAA, vBBBB */ - movzwl 4(rPC), %ecx # ecx <- BBBB - movzwl 2(rPC), %eax # eax <- AAAA - GET_VREG rINST, %ecx - .if $is_object - SET_VREG_OBJECT rINST, %eax # fp[A] <- fp[B] - .else - SET_VREG rINST, %eax # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 diff --git a/runtime/interpreter/mterp/x86/op_move_exception.S b/runtime/interpreter/mterp/x86/op_move_exception.S deleted file mode 100644 index d8dc74fdac6c9cda666c35946491716891811ca7..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_move_exception.S +++ /dev/null @@ -1,6 +0,0 @@ - /* move-exception vAA */ - movl rSELF, %ecx - movl THREAD_EXCEPTION_OFFSET(%ecx), %eax - SET_VREG_OBJECT %eax, rINST # fp[AA] <- exception object - movl $$0, THREAD_EXCEPTION_OFFSET(%ecx) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/op_move_from16.S b/runtime/interpreter/mterp/x86/op_move_from16.S deleted file mode 100644 index e86985536e331647a1a8cfae59da719205e3f5ed..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_move_from16.S +++ /dev/null @@ -1,12 +0,0 @@ -%default { "is_object":"0" } - /* for: move/from16, move-object/from16 */ - /* op vAA, vBBBB */ - movzx rINSTbl, %eax # eax <- AA - movw 2(rPC), rINSTw # rINSTw <- BBBB - GET_VREG rINST, rINST # rINST <- fp[BBBB] - .if $is_object - SET_VREG_OBJECT rINST, %eax # fp[A] <- fp[B] - .else - SET_VREG rINST, %eax # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_move_object.S b/runtime/interpreter/mterp/x86/op_move_object.S deleted file mode 100644 index a6a7c90195e09e03847a0337a85e4e773a46dc68..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_move_object.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_move.S" {"is_object":"1"} diff --git a/runtime/interpreter/mterp/x86/op_move_object_16.S b/runtime/interpreter/mterp/x86/op_move_object_16.S deleted file mode 100644 index e0c8527a29180f1b20cdc76bf231191610c3b2b8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_move_object_16.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_move_16.S" {"is_object":"1"} diff --git a/runtime/interpreter/mterp/x86/op_move_object_from16.S b/runtime/interpreter/mterp/x86/op_move_object_from16.S deleted file mode 100644 index e623820470028fbe4c84bfc577dbdfb20e187c0b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_move_object_from16.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_move_from16.S" {"is_object":"1"} diff --git a/runtime/interpreter/mterp/x86/op_move_result.S b/runtime/interpreter/mterp/x86/op_move_result.S deleted file mode 100644 index f6f2129f66960abafaa5e43de580c4f467e350ae..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_move_result.S +++ /dev/null @@ -1,11 +0,0 @@ -%default { "is_object":"0" } - /* for: move-result, move-result-object */ - /* op vAA */ - movl OFF_FP_RESULT_REGISTER(rFP), %eax # get pointer to result JType. - movl (%eax), %eax # r0 <- result.i. - .if $is_object - SET_VREG_OBJECT %eax, rINST # fp[A] <- fp[B] - .else - SET_VREG %eax, rINST # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/op_move_result_object.S b/runtime/interpreter/mterp/x86/op_move_result_object.S deleted file mode 100644 index cbf5e1db60a4b9ec869d687d69e0cc78df31eca4..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_move_result_object.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_move_result.S" {"is_object":"1"} diff --git a/runtime/interpreter/mterp/x86/op_move_result_wide.S b/runtime/interpreter/mterp/x86/op_move_result_wide.S deleted file mode 100644 index 7818cceaf99583fa7fef6438c7e2f45e20cb2ecc..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_move_result_wide.S +++ /dev/null @@ -1,7 +0,0 @@ - /* move-result-wide vAA */ - movl OFF_FP_RESULT_REGISTER(rFP), %eax # get pointer to result JType. - movl 4(%eax), %ecx # Get high - movl (%eax), %eax # Get low - SET_VREG %eax, rINST # v[AA+0] <- eax - SET_VREG_HIGH %ecx, rINST # v[AA+1] <- ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/op_move_wide.S b/runtime/interpreter/mterp/x86/op_move_wide.S deleted file mode 100644 index 79ce7b77bcd16f8d89ce49c6cafebb2d690f0829..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_move_wide.S +++ /dev/null @@ -1,8 +0,0 @@ - /* move-wide vA, vB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $$4, rINST # rINST <- B - andb $$0xf, %cl # ecx <- A - GET_WIDE_FP_VREG %xmm0, rINST # xmm0 <- v[B] - SET_WIDE_FP_VREG %xmm0, %ecx # v[A] <- xmm0 - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/op_move_wide_16.S b/runtime/interpreter/mterp/x86/op_move_wide_16.S deleted file mode 100644 index a6b8596b98abf686697d84cc78939e0c159f611f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_move_wide_16.S +++ /dev/null @@ -1,7 +0,0 @@ - /* move-wide/16 vAAAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - movzwl 4(rPC), %ecx # ecx<- BBBB - movzwl 2(rPC), %eax # eax<- AAAA - GET_WIDE_FP_VREG %xmm0, %ecx # xmm0 <- v[B] - SET_WIDE_FP_VREG %xmm0, %eax # v[A] <- xmm0 - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 diff --git a/runtime/interpreter/mterp/x86/op_move_wide_from16.S b/runtime/interpreter/mterp/x86/op_move_wide_from16.S deleted file mode 100644 index ec344de95fe58a48f628cf459cc372dc919fcdfc..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_move_wide_from16.S +++ /dev/null @@ -1,7 +0,0 @@ - /* move-wide/from16 vAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - movzwl 2(rPC), %ecx # ecx <- BBBB - movzbl rINSTbl, %eax # eax <- AAAA - GET_WIDE_FP_VREG %xmm0, %ecx # xmm0 <- v[B] - SET_WIDE_FP_VREG %xmm0, %eax # v[A] <- xmm0 - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_mul_double.S b/runtime/interpreter/mterp/x86/op_mul_double.S deleted file mode 100644 index 7cef4c08702410f90fd2ed1d731c3c00b543112c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_mul_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/sseBinop.S" {"instr":"muls","suff":"d"} diff --git a/runtime/interpreter/mterp/x86/op_mul_double_2addr.S b/runtime/interpreter/mterp/x86/op_mul_double_2addr.S deleted file mode 100644 index bb722b6901657335e2cd3a6face18872c8ad7856..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_mul_double_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/sseBinop2Addr.S" {"instr":"muls","suff":"d"} diff --git a/runtime/interpreter/mterp/x86/op_mul_float.S b/runtime/interpreter/mterp/x86/op_mul_float.S deleted file mode 100644 index 115623047aa5de0af1d1d75ea308b2cc4771d195..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_mul_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/sseBinop.S" {"instr":"muls","suff":"s"} diff --git a/runtime/interpreter/mterp/x86/op_mul_float_2addr.S b/runtime/interpreter/mterp/x86/op_mul_float_2addr.S deleted file mode 100644 index e9316dff69109915553bfd27f9cd73f379d53797..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_mul_float_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/sseBinop2Addr.S" {"instr":"muls","suff":"s"} diff --git a/runtime/interpreter/mterp/x86/op_mul_int.S b/runtime/interpreter/mterp/x86/op_mul_int.S deleted file mode 100644 index 77f4659d6a4e953dd8219759ff54a38e663a1497..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_mul_int.S +++ /dev/null @@ -1,12 +0,0 @@ - /* - * 32-bit binary multiplication. - */ - /* mul vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - GET_VREG %eax, %eax # eax <- vBB - mov rIBASE, LOCAL0(%esp) - imull (rFP,%ecx,4), %eax # trashes rIBASE/edx - mov LOCAL0(%esp), rIBASE - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_mul_int_2addr.S b/runtime/interpreter/mterp/x86/op_mul_int_2addr.S deleted file mode 100644 index da699ae19bf88a74c46fc69dec1eb4a81be00b92..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_mul_int_2addr.S +++ /dev/null @@ -1,10 +0,0 @@ - /* mul vA, vB */ - movzx rINSTbl, %ecx # ecx <- A+ - sarl $$4, rINST # rINST <- B - GET_VREG %eax, rINST # eax <- vB - andb $$0xf, %cl # ecx <- A - movl rIBASE, rINST - imull (rFP,%ecx,4), %eax # trashes rIBASE/edx - movl rINST, rIBASE - SET_VREG %eax, %ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/op_mul_int_lit16.S b/runtime/interpreter/mterp/x86/op_mul_int_lit16.S deleted file mode 100644 index 056f491befb1d56f25d499e098c7e37b0e35903e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_mul_int_lit16.S +++ /dev/null @@ -1,12 +0,0 @@ - /* mul/lit16 vA, vB, #+CCCC */ - /* Need A in rINST, ssssCCCC in ecx, vB in eax */ - movzbl rINSTbl, %eax # eax <- 000000BA - sarl $$4, %eax # eax <- B - GET_VREG %eax, %eax # eax <- vB - movl rIBASE, %ecx - movswl 2(rPC), rIBASE # rIBASE <- ssssCCCC - andb $$0xf, rINSTbl # rINST <- A - imull rIBASE, %eax # trashes rIBASE/edx - movl %ecx, rIBASE - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_mul_int_lit8.S b/runtime/interpreter/mterp/x86/op_mul_int_lit8.S deleted file mode 100644 index 59b384426c4ebfd57d8c15582b04a23355750581..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_mul_int_lit8.S +++ /dev/null @@ -1,9 +0,0 @@ - /* mul/lit8 vAA, vBB, #+CC */ - movzbl 2(rPC), %eax # eax <- BB - movl rIBASE, %ecx - GET_VREG %eax, %eax # eax <- rBB - movsbl 3(rPC), rIBASE # rIBASE <- ssssssCC - imull rIBASE, %eax # trashes rIBASE/edx - movl %ecx, rIBASE - SET_VREG %eax, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_mul_long.S b/runtime/interpreter/mterp/x86/op_mul_long.S deleted file mode 100644 index f35ca1372b078fd0edf897ad3578dac46da886de..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_mul_long.S +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Signed 64-bit integer multiply. - * - * We could definately use more free registers for - * this code. We spill rINSTw (ebx), - * giving us eax, ebc, ecx and edx as computational - * temps. On top of that, we'll spill edi (rFP) - * for use as the vB pointer and esi (rPC) for use - * as the vC pointer. Yuck. - * - */ - /* mul-long vAA, vBB, vCC */ - movzbl 2(rPC), %eax # eax <- B - movzbl 3(rPC), %ecx # ecx <- C - mov rPC, LOCAL0(%esp) # save Interpreter PC - mov rFP, LOCAL1(%esp) # save FP - mov rIBASE, LOCAL2(%esp) # save rIBASE - leal (rFP,%eax,4), %esi # esi <- &v[B] - leal (rFP,%ecx,4), rFP # rFP <- &v[C] - movl 4(%esi), %ecx # ecx <- Bmsw - imull (rFP), %ecx # ecx <- (Bmsw*Clsw) - movl 4(rFP), %eax # eax <- Cmsw - imull (%esi), %eax # eax <- (Cmsw*Blsw) - addl %eax, %ecx # ecx <- (Bmsw*Clsw)+(Cmsw*Blsw) - movl (rFP), %eax # eax <- Clsw - mull (%esi) # eax <- (Clsw*Alsw) - mov LOCAL0(%esp), rPC # restore Interpreter PC - mov LOCAL1(%esp), rFP # restore FP - leal (%ecx,rIBASE), rIBASE # full result now in rIBASE:%eax - SET_VREG_HIGH rIBASE, rINST # v[B+1] <- rIBASE - mov LOCAL2(%esp), rIBASE # restore IBASE - SET_VREG %eax, rINST # v[B] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_mul_long_2addr.S b/runtime/interpreter/mterp/x86/op_mul_long_2addr.S deleted file mode 100644 index 565a57cd399a65f14eae088a5a4a67477f2f43c3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_mul_long_2addr.S +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Signed 64-bit integer multiply, 2-addr version - * - * We could definately use more free registers for - * this code. We must spill %edx (rIBASE) because it - * is used by imul. We'll also spill rINST (ebx), - * giving us eax, ebc, ecx and rIBASE as computational - * temps. On top of that, we'll spill %esi (edi) - * for use as the vA pointer and rFP (esi) for use - * as the vB pointer. Yuck. - */ - /* mul-long/2addr vA, vB */ - movzbl rINSTbl, %eax # eax <- BA - andb $$0xf, %al # eax <- A - CLEAR_WIDE_REF %eax # clear refs in advance - sarl $$4, rINST # rINST <- B - mov rPC, LOCAL0(%esp) # save Interpreter PC - mov rFP, LOCAL1(%esp) # save FP - mov rIBASE, LOCAL2(%esp) # save rIBASE - leal (rFP,%eax,4), %esi # esi <- &v[A] - leal (rFP,rINST,4), rFP # rFP <- &v[B] - movl 4(%esi), %ecx # ecx <- Amsw - imull (rFP), %ecx # ecx <- (Amsw*Blsw) - movl 4(rFP), %eax # eax <- Bmsw - imull (%esi), %eax # eax <- (Bmsw*Alsw) - addl %eax, %ecx # ecx <- (Amsw*Blsw)+(Bmsw*Alsw) - movl (rFP), %eax # eax <- Blsw - mull (%esi) # eax <- (Blsw*Alsw) - leal (%ecx,rIBASE), rIBASE # full result now in %edx:%eax - movl rIBASE, 4(%esi) # v[A+1] <- rIBASE - movl %eax, (%esi) # v[A] <- %eax - mov LOCAL0(%esp), rPC # restore Interpreter PC - mov LOCAL2(%esp), rIBASE # restore IBASE - mov LOCAL1(%esp), rFP # restore FP - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/op_neg_double.S b/runtime/interpreter/mterp/x86/op_neg_double.S deleted file mode 100644 index fac4322f8e0c41ad5e300a87f4560d5bfc47bf33..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_neg_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/fpcvt.S" {"instr":"fchs","load":"fldl","store":"fstpl","wide":"1"} diff --git a/runtime/interpreter/mterp/x86/op_neg_float.S b/runtime/interpreter/mterp/x86/op_neg_float.S deleted file mode 100644 index 30f071b991002c5e16c3eb0e48f86c891c8146ee..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_neg_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/fpcvt.S" {"instr":"fchs","load":"flds","store":"fstps"} diff --git a/runtime/interpreter/mterp/x86/op_neg_int.S b/runtime/interpreter/mterp/x86/op_neg_int.S deleted file mode 100644 index 67d4d182aafe82149a241b314dcaadf9935b90c6..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_neg_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/unop.S" {"instr":"negl %eax"} diff --git a/runtime/interpreter/mterp/x86/op_neg_long.S b/runtime/interpreter/mterp/x86/op_neg_long.S deleted file mode 100644 index 30da247208066d5ecf227efc32b460068aadb6a2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_neg_long.S +++ /dev/null @@ -1,13 +0,0 @@ - /* unop vA, vB */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $$4, %ecx # ecx <- B - andb $$0xf, rINSTbl # rINST <- A - GET_VREG %eax, %ecx # eax <- v[B+0] - GET_VREG_HIGH %ecx, %ecx # ecx <- v[B+1] - negl %eax - adcl $$0, %ecx - negl %ecx - SET_VREG %eax, rINST # v[A+0] <- eax - SET_VREG_HIGH %ecx, rINST # v[A+1] <- ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - diff --git a/runtime/interpreter/mterp/x86/op_new_array.S b/runtime/interpreter/mterp/x86/op_new_array.S deleted file mode 100644 index 16226e989c65ac92f48b9c8e748531b74be520f8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_new_array.S +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Allocate an array of objects, specified with the array class - * and a count. - * - * The verifier guarantees that this is an array class, so we don't - * check for it here. - */ - /* new-array vA, vB, class@CCCC */ - EXPORT_PC - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG0(%esp) - movl rPC, OUT_ARG1(%esp) - REFRESH_INST ${opnum} - movl rINST, OUT_ARG2(%esp) - movl rSELF, %ecx - movl %ecx, OUT_ARG3(%esp) - call SYMBOL(MterpNewArray) - RESTORE_IBASE - testb %al, %al # 0 means an exception is thrown - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_new_instance.S b/runtime/interpreter/mterp/x86/op_new_instance.S deleted file mode 100644 index f976accb1e3ea75f380cb87f1068006de14999f2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_new_instance.S +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Create a new instance of a class. - */ - /* new-instance vAA, class@BBBB */ - EXPORT_PC - leal OFF_FP_SHADOWFRAME(rFP), %eax - movl %eax, OUT_ARG0(%esp) - movl rSELF, %ecx - movl %ecx, OUT_ARG1(%esp) - REFRESH_INST ${opnum} - movl rINST, OUT_ARG2(%esp) - call SYMBOL(MterpNewInstance) - RESTORE_IBASE - testb %al, %al # 0 means an exception is thrown - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_nop.S b/runtime/interpreter/mterp/x86/op_nop.S deleted file mode 100644 index 4cb68e392e719513e5e85a72fa4aeb942105536b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_nop.S +++ /dev/null @@ -1 +0,0 @@ - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/op_not_int.S b/runtime/interpreter/mterp/x86/op_not_int.S deleted file mode 100644 index 335ab09a5a02885c29c40a8937d2882f0743375b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_not_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/unop.S" {"instr":"notl %eax"} diff --git a/runtime/interpreter/mterp/x86/op_not_long.S b/runtime/interpreter/mterp/x86/op_not_long.S deleted file mode 100644 index 8f706e13bed3414a23aa81069ed476d259cd8dad..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_not_long.S +++ /dev/null @@ -1,11 +0,0 @@ - /* unop vA, vB */ - movzbl rINSTbl, %ecx # ecx <- BA - sarl $$4, %ecx # ecx <- B - andb $$0xf, rINSTbl # rINST <- A - GET_VREG %eax, %ecx # eax <- v[B+0] - GET_VREG_HIGH %ecx, %ecx # ecx <- v[B+1] - notl %eax - notl %ecx - SET_VREG %eax, rINST # v[A+0] <- eax - SET_VREG_HIGH %ecx, rINST # v[A+1] <- ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/op_or_int.S b/runtime/interpreter/mterp/x86/op_or_int.S deleted file mode 100644 index ebe2ec2cd6d448dff6c61eaf5960d8999d5915c8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_or_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/binop.S" {"instr":"orl (rFP,%ecx,4), %eax"} diff --git a/runtime/interpreter/mterp/x86/op_or_int_2addr.S b/runtime/interpreter/mterp/x86/op_or_int_2addr.S deleted file mode 100644 index 36c17db5a78cbf0e61825cfb609a76cf5c7421ec..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_or_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/binop2addr.S" {"instr":"orl %eax, (rFP,%ecx,4)"} diff --git a/runtime/interpreter/mterp/x86/op_or_int_lit16.S b/runtime/interpreter/mterp/x86/op_or_int_lit16.S deleted file mode 100644 index 0a88ff590205eb12c8f3e12a9e1acf933ba9fddd..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_or_int_lit16.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/binopLit16.S" {"instr":"orl %ecx, %eax"} diff --git a/runtime/interpreter/mterp/x86/op_or_int_lit8.S b/runtime/interpreter/mterp/x86/op_or_int_lit8.S deleted file mode 100644 index 0670b6785e0b2af661c76f6913463f9f8d103d97..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_or_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/binopLit8.S" {"instr":"orl %ecx, %eax"} diff --git a/runtime/interpreter/mterp/x86/op_or_long.S b/runtime/interpreter/mterp/x86/op_or_long.S deleted file mode 100644 index 09ca539f2ae57e8e6ac5ec7af0b264daa1ce6557..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_or_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/binopWide.S" {"instr1":"orl (rFP,%ecx,4), rIBASE", "instr2":"orl 4(rFP,%ecx,4), %eax"} diff --git a/runtime/interpreter/mterp/x86/op_or_long_2addr.S b/runtime/interpreter/mterp/x86/op_or_long_2addr.S deleted file mode 100644 index 2062e81e35dc3f0d0a4f7c532c34318e5d604355..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_or_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/binopWide2addr.S" {"instr1":"orl %eax, (rFP,rINST,4)","instr2":"orl %ecx, 4(rFP,rINST,4)"} diff --git a/runtime/interpreter/mterp/x86/op_packed_switch.S b/runtime/interpreter/mterp/x86/op_packed_switch.S deleted file mode 100644 index fcb7509ebf9166002008fa591969e54363481380..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_packed_switch.S +++ /dev/null @@ -1,21 +0,0 @@ -%default { "func":"MterpDoPackedSwitch" } -/* - * Handle a packed-switch or sparse-switch instruction. In both cases - * we decode it and hand it off to a helper function. - * - * We don't really expect backward branches in a switch statement, but - * they're perfectly legal, so we check for them here. - * - * for: packed-switch, sparse-switch - */ - /* op vAA, +BBBB */ - movl 2(rPC), %ecx # ecx <- BBBBbbbb - GET_VREG %eax, rINST # eax <- vAA - leal (rPC,%ecx,2), %ecx # ecx <- PC + BBBBbbbb*2 - movl %eax, OUT_ARG1(%esp) # ARG1 <- vAA - movl %ecx, OUT_ARG0(%esp) # ARG0 <- switchData - call SYMBOL($func) - REFRESH_IBASE - testl %eax, %eax - movl %eax, rINST - jmp MterpCommonTakenBranch diff --git a/runtime/interpreter/mterp/x86/op_rem_double.S b/runtime/interpreter/mterp/x86/op_rem_double.S deleted file mode 100644 index 4b52a06042f7a799250ea5fe2395f16ab56dd551..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_rem_double.S +++ /dev/null @@ -1,14 +0,0 @@ - /* rem_double vAA, vBB, vCC */ - movzbl 3(rPC), %ecx # ecx <- BB - movzbl 2(rPC), %eax # eax <- CC - fldl VREG_ADDRESS(%ecx) # %st1 <- fp[vBB] - fldl VREG_ADDRESS(%eax) # %st0 <- fp[vCC] -1: - fprem - fstsw %ax - sahf - jp 1b - fstp %st(1) - fstpl VREG_ADDRESS(rINST) # fp[vAA] <- %st - CLEAR_WIDE_REF rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_rem_double_2addr.S b/runtime/interpreter/mterp/x86/op_rem_double_2addr.S deleted file mode 100644 index 5a0e669787bdb02b60dd4951c0a4a0c6fad81a60..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_rem_double_2addr.S +++ /dev/null @@ -1,15 +0,0 @@ - /* rem_double/2addr vA, vB */ - movzx rINSTbl, %ecx # ecx <- A+ - sarl $$4, rINST # rINST <- B - fldl VREG_ADDRESS(rINST) # vB to fp stack - andb $$0xf, %cl # ecx <- A - fldl VREG_ADDRESS(%ecx) # vA to fp stack -1: - fprem - fstsw %ax - sahf - jp 1b - fstp %st(1) - fstpl VREG_ADDRESS(%ecx) # %st to vA - CLEAR_WIDE_REF %ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/op_rem_float.S b/runtime/interpreter/mterp/x86/op_rem_float.S deleted file mode 100644 index 05e0bf1132ac2a51cd53327cf1570256c23d62b5..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_rem_float.S +++ /dev/null @@ -1,14 +0,0 @@ - /* rem_float vAA, vBB, vCC */ - movzbl 3(rPC), %ecx # ecx <- BB - movzbl 2(rPC), %eax # eax <- CC - flds VREG_ADDRESS(%ecx) # vBB to fp stack - flds VREG_ADDRESS(%eax) # vCC to fp stack -1: - fprem - fstsw %ax - sahf - jp 1b - fstp %st(1) - fstps VREG_ADDRESS(rINST) # %st to vAA - CLEAR_REF rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_rem_float_2addr.S b/runtime/interpreter/mterp/x86/op_rem_float_2addr.S deleted file mode 100644 index 29f84e635ab43a3c04c25e7db05037cdc39d35e1..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_rem_float_2addr.S +++ /dev/null @@ -1,15 +0,0 @@ - /* rem_float/2addr vA, vB */ - movzx rINSTbl, %ecx # ecx <- A+ - sarl $$4, rINST # rINST <- B - flds VREG_ADDRESS(rINST) # vB to fp stack - andb $$0xf, %cl # ecx <- A - flds VREG_ADDRESS(%ecx) # vA to fp stack -1: - fprem - fstsw %ax - sahf - jp 1b - fstp %st(1) - fstps VREG_ADDRESS(%ecx) # %st to vA - CLEAR_REF %ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/op_rem_int.S b/runtime/interpreter/mterp/x86/op_rem_int.S deleted file mode 100644 index d25b93ce3fbd2c542bce0bea89ce3bc3361afa0d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_rem_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/bindiv.S" {"result":"rIBASE","special":"$0","rem":"1"} diff --git a/runtime/interpreter/mterp/x86/op_rem_int_2addr.S b/runtime/interpreter/mterp/x86/op_rem_int_2addr.S deleted file mode 100644 index c788e0eed06dcc3da1b80c3c2ffde4a7e3943639..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_rem_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/bindiv2addr.S" {"result":"rIBASE","special":"$0"} diff --git a/runtime/interpreter/mterp/x86/op_rem_int_lit16.S b/runtime/interpreter/mterp/x86/op_rem_int_lit16.S deleted file mode 100644 index 3df9d3911ddb0f1b021a07b95aac0812d1da6edd..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_rem_int_lit16.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/bindivLit16.S" {"result":"rIBASE","special":"$0"} diff --git a/runtime/interpreter/mterp/x86/op_rem_int_lit8.S b/runtime/interpreter/mterp/x86/op_rem_int_lit8.S deleted file mode 100644 index 56e19c6b17afb73c341468851ec8a96a3b2c3f84..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_rem_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/bindivLit8.S" {"result":"rIBASE","special":"$0"} diff --git a/runtime/interpreter/mterp/x86/op_rem_long.S b/runtime/interpreter/mterp/x86/op_rem_long.S deleted file mode 100644 index 0ffe1f668cca24f02c45bd277f812e38122a87ff..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_rem_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_div_long.S" {"routine":"art_quick_lmod"} diff --git a/runtime/interpreter/mterp/x86/op_rem_long_2addr.S b/runtime/interpreter/mterp/x86/op_rem_long_2addr.S deleted file mode 100644 index 4b977352a111c9ee55db38c5c5ebb0151a4f5df7..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_rem_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_div_long_2addr.S" {"routine":"art_quick_lmod"} diff --git a/runtime/interpreter/mterp/x86/op_return.S b/runtime/interpreter/mterp/x86/op_return.S deleted file mode 100644 index a8ebbed64e2a764e12ddfcc39ad90868a5c27a07..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_return.S +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Return a 32-bit value. - * - * for: return, return-object - */ - /* op vAA */ - .extern MterpThreadFenceForConstructor - call SYMBOL(MterpThreadFenceForConstructor) - movl rSELF, %eax - testl $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(%eax) - jz 1f - movl %eax, OUT_ARG0(%esp) - call SYMBOL(MterpSuspendCheck) -1: - GET_VREG %eax, rINST # eax <- vAA - xorl %ecx, %ecx - jmp MterpReturn diff --git a/runtime/interpreter/mterp/x86/op_return_object.S b/runtime/interpreter/mterp/x86/op_return_object.S deleted file mode 100644 index 12c84b32a2d94ddc9ec11dfbf894edc1e491a129..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_return_object.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_return.S" diff --git a/runtime/interpreter/mterp/x86/op_return_void.S b/runtime/interpreter/mterp/x86/op_return_void.S deleted file mode 100644 index d9eddf39f2524a305a4e7afdd9a9c00977234e11..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_return_void.S +++ /dev/null @@ -1,11 +0,0 @@ - .extern MterpThreadFenceForConstructor - call SYMBOL(MterpThreadFenceForConstructor) - movl rSELF, %eax - testl $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(%eax) - jz 1f - movl %eax, OUT_ARG0(%esp) - call SYMBOL(MterpSuspendCheck) -1: - xorl %eax, %eax - xorl %ecx, %ecx - jmp MterpReturn diff --git a/runtime/interpreter/mterp/x86/op_return_void_no_barrier.S b/runtime/interpreter/mterp/x86/op_return_void_no_barrier.S deleted file mode 100644 index 2fbda6bfe995dcc8fd16fa460684c22b01703316..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_return_void_no_barrier.S +++ /dev/null @@ -1,9 +0,0 @@ - movl rSELF, %eax - testl $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(%eax) - jz 1f - movl %eax, OUT_ARG0(%esp) - call SYMBOL(MterpSuspendCheck) -1: - xorl %eax, %eax - xorl %ecx, %ecx - jmp MterpReturn diff --git a/runtime/interpreter/mterp/x86/op_return_wide.S b/runtime/interpreter/mterp/x86/op_return_wide.S deleted file mode 100644 index 5fff62620065e1995121eb359fb331be370d3393..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_return_wide.S +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Return a 64-bit value. - */ - /* return-wide vAA */ - .extern MterpThreadFenceForConstructor - call SYMBOL(MterpThreadFenceForConstructor) - movl rSELF, %eax - testl $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(%eax) - jz 1f - movl %eax, OUT_ARG0(%esp) - call SYMBOL(MterpSuspendCheck) -1: - GET_VREG %eax, rINST # eax <- v[AA+0] - GET_VREG_HIGH %ecx, rINST # ecx <- v[AA+1] - jmp MterpReturn diff --git a/runtime/interpreter/mterp/x86/op_rsub_int.S b/runtime/interpreter/mterp/x86/op_rsub_int.S deleted file mode 100644 index d6449c6c47665afe6d34ecff132703472dbc1d65..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_rsub_int.S +++ /dev/null @@ -1,2 +0,0 @@ -/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ -%include "x86/binopLit16.S" {"instr":"subl %eax, %ecx","result":"%ecx"} diff --git a/runtime/interpreter/mterp/x86/op_rsub_int_lit8.S b/runtime/interpreter/mterp/x86/op_rsub_int_lit8.S deleted file mode 100644 index 15d0e359bff791fa70e32fa24abd8bb395f81960..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_rsub_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/binopLit8.S" {"instr":"subl %eax, %ecx" , "result":"%ecx"} diff --git a/runtime/interpreter/mterp/x86/op_sget.S b/runtime/interpreter/mterp/x86/op_sget.S deleted file mode 100644 index ada4e0e26a116a282bc9ac2af6ddfe7009d97367..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_sget.S +++ /dev/null @@ -1,2 +0,0 @@ -%default { "is_object":"0", "helper":"MterpSGetU32" } -%include "x86/field.S" { } diff --git a/runtime/interpreter/mterp/x86/op_sget_boolean.S b/runtime/interpreter/mterp/x86/op_sget_boolean.S deleted file mode 100644 index 3936eeae4548865fc8cca3e59a7dee53ab967ce3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_sget_boolean.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_sget.S" {"helper":"MterpSGetU8"} diff --git a/runtime/interpreter/mterp/x86/op_sget_byte.S b/runtime/interpreter/mterp/x86/op_sget_byte.S deleted file mode 100644 index 967586d9440bd83674797b7b5fc42c0933f6406f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_sget_byte.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_sget.S" {"helper":"MterpSGetI8"} diff --git a/runtime/interpreter/mterp/x86/op_sget_char.S b/runtime/interpreter/mterp/x86/op_sget_char.S deleted file mode 100644 index b706f18638f4fae7539348b1a5898123e625987a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_sget_char.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_sget.S" {"helper":"MterpSGetU16"} diff --git a/runtime/interpreter/mterp/x86/op_sget_object.S b/runtime/interpreter/mterp/x86/op_sget_object.S deleted file mode 100644 index eac88365347156292ca909478b21a0c98cc04101..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_sget_object.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_sget.S" {"is_object":"1", "helper":"MterpSGetObj"} diff --git a/runtime/interpreter/mterp/x86/op_sget_short.S b/runtime/interpreter/mterp/x86/op_sget_short.S deleted file mode 100644 index ee058a60167a1c3ca6d865d3940366840be63f29..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_sget_short.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_sget.S" {"helper":"MterpSGetI16"} diff --git a/runtime/interpreter/mterp/x86/op_sget_wide.S b/runtime/interpreter/mterp/x86/op_sget_wide.S deleted file mode 100644 index 59232749a2633527302289d909ed1cae2f932c42..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_sget_wide.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_sget.S" {"helper":"MterpSGetU64"} diff --git a/runtime/interpreter/mterp/x86/op_shl_int.S b/runtime/interpreter/mterp/x86/op_shl_int.S deleted file mode 100644 index 6a41d1c70bff084242133fa163532eff3b671fad..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_shl_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/binop1.S" {"instr":"sall %cl, %eax"} diff --git a/runtime/interpreter/mterp/x86/op_shl_int_2addr.S b/runtime/interpreter/mterp/x86/op_shl_int_2addr.S deleted file mode 100644 index 72abb8ebe0abab53042ba2968ed29e4d270eccab..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_shl_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/shop2addr.S" {"instr":"sall %cl, %eax"} diff --git a/runtime/interpreter/mterp/x86/op_shl_int_lit8.S b/runtime/interpreter/mterp/x86/op_shl_int_lit8.S deleted file mode 100644 index b8d60691779692b183fa5c2c1bc1170217105307..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_shl_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/binopLit8.S" {"instr":"sall %cl, %eax"} diff --git a/runtime/interpreter/mterp/x86/op_shl_long.S b/runtime/interpreter/mterp/x86/op_shl_long.S deleted file mode 100644 index aa58a93f9c88383af827db5018e655feb89ab765..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_shl_long.S +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Long integer shift. This is different from the generic 32/64-bit - * binary operations because vAA/vBB are 64-bit but vCC (the shift - * distance) is 32-bit. Also, Dalvik requires us to mask off the low - * 6 bits of the shift distance. x86 shifts automatically mask off - * the low 5 bits of %cl, so have to handle the 64 > shiftcount > 31 - * case specially. - */ - /* shl-long vAA, vBB, vCC */ - /* ecx gets shift count */ - /* Need to spill rINST */ - /* rINSTw gets AA */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - movl rIBASE, LOCAL0(%esp) - GET_VREG_HIGH rIBASE, %eax # ecx <- v[BB+1] - GET_VREG %ecx, %ecx # ecx <- vCC - GET_VREG %eax, %eax # eax <- v[BB+0] - shldl %eax,rIBASE - sall %cl, %eax - testb $$32, %cl - je 2f - movl %eax, rIBASE - xorl %eax, %eax -2: - SET_VREG_HIGH rIBASE, rINST # v[AA+1] <- rIBASE - movl LOCAL0(%esp), rIBASE - SET_VREG %eax, rINST # v[AA+0] <- %eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_shl_long_2addr.S b/runtime/interpreter/mterp/x86/op_shl_long_2addr.S deleted file mode 100644 index 6bbf49ca69a467f1b4c2d81045c0d95591da145b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_shl_long_2addr.S +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Long integer shift, 2addr version. vA is 64-bit value/result, vB is - * 32-bit shift distance. - */ - /* shl-long/2addr vA, vB */ - /* ecx gets shift count */ - /* Need to spill rIBASE */ - /* rINSTw gets AA */ - movzbl rINSTbl, %ecx # ecx <- BA - andb $$0xf, rINSTbl # rINST <- A - GET_VREG %eax, rINST # eax <- v[AA+0] - sarl $$4, %ecx # ecx <- B - movl rIBASE, LOCAL0(%esp) - GET_VREG_HIGH rIBASE, rINST # rIBASE <- v[AA+1] - GET_VREG %ecx, %ecx # ecx <- vBB - shldl %eax, rIBASE - sall %cl, %eax - testb $$32, %cl - je 2f - movl %eax, rIBASE - xorl %eax, %eax -2: - SET_VREG_HIGH rIBASE, rINST # v[AA+1] <- rIBASE - movl LOCAL0(%esp), rIBASE - SET_VREG %eax, rINST # v[AA+0] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/op_shr_int.S b/runtime/interpreter/mterp/x86/op_shr_int.S deleted file mode 100644 index 687b2c3b7b6546ea3df53eabd89cac4c0c0b37d0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_shr_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/binop1.S" {"instr":"sarl %cl, %eax"} diff --git a/runtime/interpreter/mterp/x86/op_shr_int_2addr.S b/runtime/interpreter/mterp/x86/op_shr_int_2addr.S deleted file mode 100644 index 533b0e95b9f1e11be525560af719d8c15ced1f36..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_shr_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/shop2addr.S" {"instr":"sarl %cl, %eax"} diff --git a/runtime/interpreter/mterp/x86/op_shr_int_lit8.S b/runtime/interpreter/mterp/x86/op_shr_int_lit8.S deleted file mode 100644 index ebd1beafaceed5164f238d146fdc2d8bcfc32673..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_shr_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/binopLit8.S" {"instr":"sarl %cl, %eax"} diff --git a/runtime/interpreter/mterp/x86/op_shr_long.S b/runtime/interpreter/mterp/x86/op_shr_long.S deleted file mode 100644 index 68aa0ee83712371f39c8c1fe302f85b23b71ab38..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_shr_long.S +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Long integer shift. This is different from the generic 32/64-bit - * binary operations because vAA/vBB are 64-bit but vCC (the shift - * distance) is 32-bit. Also, Dalvik requires us to mask off the low - * 6 bits of the shift distance. x86 shifts automatically mask off - * the low 5 bits of %cl, so have to handle the 64 > shiftcount > 31 - * case specially. - */ - /* shr-long vAA, vBB, vCC */ - /* ecx gets shift count */ - /* Need to spill rIBASE */ - /* rINSTw gets AA */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - movl rIBASE, LOCAL0(%esp) - GET_VREG_HIGH rIBASE, %eax # rIBASE<- v[BB+1] - GET_VREG %ecx, %ecx # ecx <- vCC - GET_VREG %eax, %eax # eax <- v[BB+0] - shrdl rIBASE, %eax - sarl %cl, rIBASE - testb $$32, %cl - je 2f - movl rIBASE, %eax - sarl $$31, rIBASE -2: - SET_VREG_HIGH rIBASE, rINST # v[AA+1] <- rIBASE - movl LOCAL0(%esp), rIBASE - SET_VREG %eax, rINST # v[AA+0] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_shr_long_2addr.S b/runtime/interpreter/mterp/x86/op_shr_long_2addr.S deleted file mode 100644 index 148bd1b9ebf6ab570aa62b021de14b3d400886af..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_shr_long_2addr.S +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Long integer shift, 2addr version. vA is 64-bit value/result, vB is - * 32-bit shift distance. - */ - /* shl-long/2addr vA, vB */ - /* ecx gets shift count */ - /* Need to spill rIBASE */ - /* rINSTw gets AA */ - movzbl rINSTbl, %ecx # ecx <- BA - andb $$0xf, rINSTbl # rINST <- A - GET_VREG %eax, rINST # eax <- v[AA+0] - sarl $$4, %ecx # ecx <- B - movl rIBASE, LOCAL0(%esp) - GET_VREG_HIGH rIBASE, rINST # rIBASE <- v[AA+1] - GET_VREG %ecx, %ecx # ecx <- vBB - shrdl rIBASE, %eax - sarl %cl, rIBASE - testb $$32, %cl - je 2f - movl rIBASE, %eax - sarl $$31, rIBASE -2: - SET_VREG_HIGH rIBASE, rINST # v[AA+1] <- rIBASE - movl LOCAL0(%esp), rIBASE - SET_VREG %eax, rINST # v[AA+0] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/op_sparse_switch.S b/runtime/interpreter/mterp/x86/op_sparse_switch.S deleted file mode 100644 index fdaec4762ad76f9945b6dc031e54dc09444668c7..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_sparse_switch.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_packed_switch.S" { "func":"MterpDoSparseSwitch" } diff --git a/runtime/interpreter/mterp/x86/op_sput.S b/runtime/interpreter/mterp/x86/op_sput.S deleted file mode 100644 index 2ad68e7683895533b7dc10769881e85e9c39c4af..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_sput.S +++ /dev/null @@ -1,2 +0,0 @@ -%default { "is_object":"0", "helper":"MterpSPutU32"} -%include "x86/field.S" { } diff --git a/runtime/interpreter/mterp/x86/op_sput_boolean.S b/runtime/interpreter/mterp/x86/op_sput_boolean.S deleted file mode 100644 index c6aa7c4cd128aabd7d88111ef73f36c8a5013359..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_sput_boolean.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_sput.S" {"helper":"MterpSPutU8"} diff --git a/runtime/interpreter/mterp/x86/op_sput_byte.S b/runtime/interpreter/mterp/x86/op_sput_byte.S deleted file mode 100644 index fd504a8023d204942ddb0ded13d89590564b08a9..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_sput_byte.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_sput.S" {"helper":"MterpSPutI8"} diff --git a/runtime/interpreter/mterp/x86/op_sput_char.S b/runtime/interpreter/mterp/x86/op_sput_char.S deleted file mode 100644 index b4d0997737673ac9d9896ab0c28bca0091b2bafe..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_sput_char.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_sput.S" {"helper":"MterpSPutU16"} diff --git a/runtime/interpreter/mterp/x86/op_sput_object.S b/runtime/interpreter/mterp/x86/op_sput_object.S deleted file mode 100644 index 4452dba2723820a26214259b6c875e024bee1ff7..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_sput_object.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_sput.S" {"is_object":"1", "helper":"MterpSPutObj"} diff --git a/runtime/interpreter/mterp/x86/op_sput_short.S b/runtime/interpreter/mterp/x86/op_sput_short.S deleted file mode 100644 index eba01bdfd0b93bc08415e1d4ad06bd0f58a24d92..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_sput_short.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_sput.S" {"helper":"MterpSPutI16"} diff --git a/runtime/interpreter/mterp/x86/op_sput_wide.S b/runtime/interpreter/mterp/x86/op_sput_wide.S deleted file mode 100644 index d79b068f33d9017d142650563822b6155a6d137d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_sput_wide.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/op_sput.S" {"helper":"MterpSPutU64"} diff --git a/runtime/interpreter/mterp/x86/op_sub_double.S b/runtime/interpreter/mterp/x86/op_sub_double.S deleted file mode 100644 index e83afeb215f5496a8651e7e112d67bc5941a3a9e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_sub_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/sseBinop.S" {"instr":"subs","suff":"d"} diff --git a/runtime/interpreter/mterp/x86/op_sub_double_2addr.S b/runtime/interpreter/mterp/x86/op_sub_double_2addr.S deleted file mode 100644 index af9a2ab3f84a60c204c6d1df7550016da2f52a85..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_sub_double_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/sseBinop2Addr.S" {"instr":"subs","suff":"d"} diff --git a/runtime/interpreter/mterp/x86/op_sub_float.S b/runtime/interpreter/mterp/x86/op_sub_float.S deleted file mode 100644 index 423d8340690e9e87e5cddc258ef903537ca3f1d6..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_sub_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/sseBinop.S" {"instr":"subs","suff":"s"} diff --git a/runtime/interpreter/mterp/x86/op_sub_float_2addr.S b/runtime/interpreter/mterp/x86/op_sub_float_2addr.S deleted file mode 100644 index 18de000b492ef5fbabfba33e465017c9c28d43f3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_sub_float_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/sseBinop2Addr.S" {"instr":"subs","suff":"s"} diff --git a/runtime/interpreter/mterp/x86/op_sub_int.S b/runtime/interpreter/mterp/x86/op_sub_int.S deleted file mode 100644 index 7fe03fb1693e2abc74af26301e6351269f0ec149..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_sub_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/binop.S" {"instr":"subl (rFP,%ecx,4), %eax"} diff --git a/runtime/interpreter/mterp/x86/op_sub_int_2addr.S b/runtime/interpreter/mterp/x86/op_sub_int_2addr.S deleted file mode 100644 index cc9bf60f2e2623fd0e6af9488fbd5573776302a9..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_sub_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/binop2addr.S" {"instr":"subl %eax, (rFP,%ecx,4)"} diff --git a/runtime/interpreter/mterp/x86/op_sub_long.S b/runtime/interpreter/mterp/x86/op_sub_long.S deleted file mode 100644 index 014591e41e9bc46a8f7d4e0b845a01308ff26b8e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_sub_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/binopWide.S" {"instr1":"subl (rFP,%ecx,4), rIBASE", "instr2":"sbbl 4(rFP,%ecx,4), %eax"} diff --git a/runtime/interpreter/mterp/x86/op_sub_long_2addr.S b/runtime/interpreter/mterp/x86/op_sub_long_2addr.S deleted file mode 100644 index 7498029ebf7b7cb394b1bc448fac75bd580398e7..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_sub_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/binopWide2addr.S" {"instr1":"subl %eax, (rFP,rINST,4)","instr2":"sbbl %ecx, 4(rFP,rINST,4)"} diff --git a/runtime/interpreter/mterp/x86/op_throw.S b/runtime/interpreter/mterp/x86/op_throw.S deleted file mode 100644 index a6e6b1ed5626efdd976d718a90e21721ca0d1142..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_throw.S +++ /dev/null @@ -1,11 +0,0 @@ -/* - * Throw an exception object in the current thread. - */ - /* throw vAA */ - EXPORT_PC - GET_VREG %eax, rINST # eax<- vAA (exception object) - testl %eax, %eax - jz common_errNullObject - movl rSELF,%ecx - movl %eax, THREAD_EXCEPTION_OFFSET(%ecx) - jmp MterpException diff --git a/runtime/interpreter/mterp/x86/op_unused_3e.S b/runtime/interpreter/mterp/x86/op_unused_3e.S deleted file mode 100644 index 31d98c1f3976aba75092829d6a05e76dd485d56b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_unused_3e.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/unused.S" diff --git a/runtime/interpreter/mterp/x86/op_unused_3f.S b/runtime/interpreter/mterp/x86/op_unused_3f.S deleted file mode 100644 index 31d98c1f3976aba75092829d6a05e76dd485d56b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_unused_3f.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/unused.S" diff --git a/runtime/interpreter/mterp/x86/op_unused_40.S b/runtime/interpreter/mterp/x86/op_unused_40.S deleted file mode 100644 index 31d98c1f3976aba75092829d6a05e76dd485d56b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_unused_40.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/unused.S" diff --git a/runtime/interpreter/mterp/x86/op_unused_41.S b/runtime/interpreter/mterp/x86/op_unused_41.S deleted file mode 100644 index 31d98c1f3976aba75092829d6a05e76dd485d56b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_unused_41.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/unused.S" diff --git a/runtime/interpreter/mterp/x86/op_unused_42.S b/runtime/interpreter/mterp/x86/op_unused_42.S deleted file mode 100644 index 31d98c1f3976aba75092829d6a05e76dd485d56b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_unused_42.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/unused.S" diff --git a/runtime/interpreter/mterp/x86/op_unused_43.S b/runtime/interpreter/mterp/x86/op_unused_43.S deleted file mode 100644 index 31d98c1f3976aba75092829d6a05e76dd485d56b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_unused_43.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/unused.S" diff --git a/runtime/interpreter/mterp/x86/op_unused_79.S b/runtime/interpreter/mterp/x86/op_unused_79.S deleted file mode 100644 index 31d98c1f3976aba75092829d6a05e76dd485d56b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_unused_79.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/unused.S" diff --git a/runtime/interpreter/mterp/x86/op_unused_7a.S b/runtime/interpreter/mterp/x86/op_unused_7a.S deleted file mode 100644 index 31d98c1f3976aba75092829d6a05e76dd485d56b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_unused_7a.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/unused.S" diff --git a/runtime/interpreter/mterp/x86/op_unused_f3.S b/runtime/interpreter/mterp/x86/op_unused_f3.S deleted file mode 100644 index 31d98c1f3976aba75092829d6a05e76dd485d56b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_unused_f3.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/unused.S" diff --git a/runtime/interpreter/mterp/x86/op_unused_f4.S b/runtime/interpreter/mterp/x86/op_unused_f4.S deleted file mode 100644 index 31d98c1f3976aba75092829d6a05e76dd485d56b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_unused_f4.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/unused.S" diff --git a/runtime/interpreter/mterp/x86/op_unused_f5.S b/runtime/interpreter/mterp/x86/op_unused_f5.S deleted file mode 100644 index 31d98c1f3976aba75092829d6a05e76dd485d56b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_unused_f5.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/unused.S" diff --git a/runtime/interpreter/mterp/x86/op_unused_f6.S b/runtime/interpreter/mterp/x86/op_unused_f6.S deleted file mode 100644 index 31d98c1f3976aba75092829d6a05e76dd485d56b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_unused_f6.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/unused.S" diff --git a/runtime/interpreter/mterp/x86/op_unused_f7.S b/runtime/interpreter/mterp/x86/op_unused_f7.S deleted file mode 100644 index 31d98c1f3976aba75092829d6a05e76dd485d56b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_unused_f7.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/unused.S" diff --git a/runtime/interpreter/mterp/x86/op_unused_f8.S b/runtime/interpreter/mterp/x86/op_unused_f8.S deleted file mode 100644 index 31d98c1f3976aba75092829d6a05e76dd485d56b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_unused_f8.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/unused.S" diff --git a/runtime/interpreter/mterp/x86/op_unused_f9.S b/runtime/interpreter/mterp/x86/op_unused_f9.S deleted file mode 100644 index 31d98c1f3976aba75092829d6a05e76dd485d56b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_unused_f9.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/unused.S" diff --git a/runtime/interpreter/mterp/x86/op_unused_fc.S b/runtime/interpreter/mterp/x86/op_unused_fc.S deleted file mode 100644 index 31d98c1f3976aba75092829d6a05e76dd485d56b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_unused_fc.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/unused.S" diff --git a/runtime/interpreter/mterp/x86/op_unused_fd.S b/runtime/interpreter/mterp/x86/op_unused_fd.S deleted file mode 100644 index 31d98c1f3976aba75092829d6a05e76dd485d56b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_unused_fd.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/unused.S" diff --git a/runtime/interpreter/mterp/x86/op_ushr_int.S b/runtime/interpreter/mterp/x86/op_ushr_int.S deleted file mode 100644 index dfe25ff05df2b02874dc0a89885d29c439f4afc0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_ushr_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/binop1.S" {"instr":"shrl %cl, %eax"} diff --git a/runtime/interpreter/mterp/x86/op_ushr_int_2addr.S b/runtime/interpreter/mterp/x86/op_ushr_int_2addr.S deleted file mode 100644 index c14bc980ba142cb95fe4a843b08d39180b39cfdf..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_ushr_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/shop2addr.S" {"instr":"shrl %cl, %eax"} diff --git a/runtime/interpreter/mterp/x86/op_ushr_int_lit8.S b/runtime/interpreter/mterp/x86/op_ushr_int_lit8.S deleted file mode 100644 index e129f6bbe6574cd446966a1a9c46fea5dd642a20..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_ushr_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/binopLit8.S" {"instr":"shrl %cl, %eax"} diff --git a/runtime/interpreter/mterp/x86/op_ushr_long.S b/runtime/interpreter/mterp/x86/op_ushr_long.S deleted file mode 100644 index 9527c9c2e465d93badec3b6a4bdc3188b0fcb07c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_ushr_long.S +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Long integer shift. This is different from the generic 32/64-bit - * binary operations because vAA/vBB are 64-bit but vCC (the shift - * distance) is 32-bit. Also, Dalvik requires us to mask off the low - * 6 bits of the shift distance. x86 shifts automatically mask off - * the low 5 bits of %cl, so have to handle the 64 > shiftcount > 31 - * case specially. - */ - /* shr-long vAA, vBB, vCC */ - /* ecx gets shift count */ - /* Need to spill rIBASE */ - /* rINSTw gets AA */ - movzbl 2(rPC), %eax # eax <- BB - movzbl 3(rPC), %ecx # ecx <- CC - movl rIBASE, LOCAL0(%esp) - GET_VREG_HIGH rIBASE, %eax # rIBASE <- v[BB+1] - GET_VREG %ecx, %ecx # ecx <- vCC - GET_VREG %eax, %eax # eax <- v[BB+0] - shrdl rIBASE, %eax - shrl %cl, rIBASE - testb $$32, %cl - je 2f - movl rIBASE, %eax - xorl rIBASE, rIBASE -2: - SET_VREG_HIGH rIBASE, rINST # v[AA+1] <- rIBASE - movl LOCAL0(%esp), rIBASE - SET_VREG %eax, rINST # v[BB+0] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/op_ushr_long_2addr.S b/runtime/interpreter/mterp/x86/op_ushr_long_2addr.S deleted file mode 100644 index 72fcc36fffeefc40fbd4467edd7f44993c03b67f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_ushr_long_2addr.S +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Long integer shift, 2addr version. vA is 64-bit value/result, vB is - * 32-bit shift distance. - */ - /* shl-long/2addr vA, vB */ - /* ecx gets shift count */ - /* Need to spill rIBASE */ - /* rINSTw gets AA */ - movzbl rINSTbl, %ecx # ecx <- BA - andb $$0xf, rINSTbl # rINST <- A - GET_VREG %eax, rINST # eax <- v[AA+0] - sarl $$4, %ecx # ecx <- B - movl rIBASE, LOCAL0(%esp) - GET_VREG_HIGH rIBASE, rINST # rIBASE <- v[AA+1] - GET_VREG %ecx, %ecx # ecx <- vBB - shrdl rIBASE, %eax - shrl %cl, rIBASE - testb $$32, %cl - je 2f - movl rIBASE, %eax - xorl rIBASE, rIBASE -2: - SET_VREG_HIGH rIBASE, rINST # v[AA+1] <- rIBASE - movl LOCAL0(%esp), rIBASE - SET_VREG %eax, rINST # v[AA+0] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/op_xor_int.S b/runtime/interpreter/mterp/x86/op_xor_int.S deleted file mode 100644 index 35aca6a821ae907cfc1973a3cb0d7be68844f6c2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_xor_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/binop.S" {"instr":"xorl (rFP,%ecx,4), %eax"} diff --git a/runtime/interpreter/mterp/x86/op_xor_int_2addr.S b/runtime/interpreter/mterp/x86/op_xor_int_2addr.S deleted file mode 100644 index d7b70e2ea1cb23ba95143fb7e0a3f3ea03ce674d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_xor_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/binop2addr.S" {"instr":"xorl %eax, (rFP,%ecx,4)"} diff --git a/runtime/interpreter/mterp/x86/op_xor_int_lit16.S b/runtime/interpreter/mterp/x86/op_xor_int_lit16.S deleted file mode 100644 index 115f0a0410a9367dccb16d37e265eaddeff10d8c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_xor_int_lit16.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/binopLit16.S" {"instr":"xorl %ecx, %eax"} diff --git a/runtime/interpreter/mterp/x86/op_xor_int_lit8.S b/runtime/interpreter/mterp/x86/op_xor_int_lit8.S deleted file mode 100644 index 243971c5494b1cdfecdd6089967608a89748e0f8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_xor_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/binopLit8.S" {"instr":"xorl %ecx, %eax"} diff --git a/runtime/interpreter/mterp/x86/op_xor_long.S b/runtime/interpreter/mterp/x86/op_xor_long.S deleted file mode 100644 index 0d3c0f5cac50190406e8e1de47f152c7d438ce8a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_xor_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/binopWide.S" {"instr1":"xorl (rFP,%ecx,4), rIBASE", "instr2":"xorl 4(rFP,%ecx,4), %eax"} diff --git a/runtime/interpreter/mterp/x86/op_xor_long_2addr.S b/runtime/interpreter/mterp/x86/op_xor_long_2addr.S deleted file mode 100644 index b5000e44268b03e90b9f387f5ed45b7c822d16df..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/op_xor_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86/binopWide2addr.S" {"instr1":"xorl %eax, (rFP,rINST,4)","instr2":"xorl %ecx, 4(rFP,rINST,4)"} diff --git a/runtime/interpreter/mterp/x86/other.S b/runtime/interpreter/mterp/x86/other.S new file mode 100644 index 0000000000000000000000000000000000000000..5de33813b8de2f957f16d162203b5156a16d7a96 --- /dev/null +++ b/runtime/interpreter/mterp/x86/other.S @@ -0,0 +1,318 @@ +%def const(helper="UndefinedConstHandler"): + /* const/class vAA, type@BBBB */ + /* const/method-handle vAA, method_handle@BBBB */ + /* const/method-type vAA, proto@BBBB */ + /* const/string vAA, string@@BBBB */ + .extern $helper + EXPORT_PC + movzwl 2(rPC), %eax # eax <- BBBB + movl %eax, OUT_ARG0(%esp) + movl rINST, OUT_ARG1(%esp) + leal OFF_FP_SHADOWFRAME(rFP), %eax + movl %eax, OUT_ARG2(%esp) + movl rSELF, %eax + movl %eax, OUT_ARG3(%esp) + call SYMBOL($helper) # (index, tgt_reg, shadow_frame, self) + RESTORE_IBASE + testb %al, %al + jnz MterpPossibleException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def unused(): +/* + * Bail to reference interpreter to throw. + */ + jmp MterpFallback + +%def op_const(): + /* const vAA, #+BBBBbbbb */ + movl 2(rPC), %eax # grab all 32 bits at once + SET_VREG %eax, rINST # vAA<- eax + ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 + +%def op_const_16(): + /* const/16 vAA, #+BBBB */ + movswl 2(rPC), %ecx # ecx <- ssssBBBB + SET_VREG %ecx, rINST # vAA <- ssssBBBB + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_const_4(): + /* const/4 vA, #+B */ + movsx rINSTbl, %eax # eax <-ssssssBx + movl $$0xf, rINST + andl %eax, rINST # rINST <- A + sarl $$4, %eax + SET_VREG %eax, rINST + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_const_class(): +% const(helper="MterpConstClass") + +%def op_const_high16(): + /* const/high16 vAA, #+BBBB0000 */ + movzwl 2(rPC), %eax # eax <- 0000BBBB + sall $$16, %eax # eax <- BBBB0000 + SET_VREG %eax, rINST # vAA <- eax + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_const_method_handle(): +% const(helper="MterpConstMethodHandle") + +%def op_const_method_type(): +% const(helper="MterpConstMethodType") + +%def op_const_string(): +% const(helper="MterpConstString") + +%def op_const_string_jumbo(): + /* const/string vAA, String@BBBBBBBB */ + EXPORT_PC + movl 2(rPC), %eax # eax <- BBBB + movl %eax, OUT_ARG0(%esp) + movl rINST, OUT_ARG1(%esp) + leal OFF_FP_SHADOWFRAME(rFP), %eax + movl %eax, OUT_ARG2(%esp) + movl rSELF, %eax + movl %eax, OUT_ARG3(%esp) + call SYMBOL(MterpConstString) # (index, tgt_reg, shadow_frame, self) + RESTORE_IBASE + testb %al, %al + jnz MterpPossibleException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 + +%def op_const_wide(): + /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ + movl 2(rPC), %eax # eax <- lsw + movzbl rINSTbl, %ecx # ecx <- AA + movl 6(rPC), rINST # rINST <- msw + SET_VREG %eax, %ecx + SET_VREG_HIGH rINST, %ecx + ADVANCE_PC_FETCH_AND_GOTO_NEXT 5 + +%def op_const_wide_16(): + /* const-wide/16 vAA, #+BBBB */ + movswl 2(rPC), %eax # eax <- ssssBBBB + movl rIBASE, %ecx # preserve rIBASE (cltd trashes it) + cltd # rIBASE:eax <- ssssssssssssBBBB + SET_VREG_HIGH rIBASE, rINST # store msw + SET_VREG %eax, rINST # store lsw + movl %ecx, rIBASE # restore rIBASE + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_const_wide_32(): + /* const-wide/32 vAA, #+BBBBbbbb */ + movl 2(rPC), %eax # eax <- BBBBbbbb + movl rIBASE, %ecx # preserve rIBASE (cltd trashes it) + cltd # rIBASE:eax <- ssssssssssssBBBB + SET_VREG_HIGH rIBASE, rINST # store msw + SET_VREG %eax, rINST # store lsw + movl %ecx, rIBASE # restore rIBASE + ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 + +%def op_const_wide_high16(): + /* const-wide/high16 vAA, #+BBBB000000000000 */ + movzwl 2(rPC), %eax # eax <- 0000BBBB + sall $$16, %eax # eax <- BBBB0000 + SET_VREG_HIGH %eax, rINST # v[AA+1] <- eax + xorl %eax, %eax + SET_VREG %eax, rINST # v[AA+0] <- eax + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_monitor_enter(): +/* + * Synchronize on an object. + */ + /* monitor-enter vAA */ + EXPORT_PC + GET_VREG %ecx, rINST + movl %ecx, OUT_ARG0(%esp) + movl rSELF, %eax + movl %eax, OUT_ARG1(%esp) + call SYMBOL(artLockObjectFromCode) # (object, self) + RESTORE_IBASE + testb %al, %al + jnz MterpException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_monitor_exit(): +/* + * Unlock an object. + * + * Exceptions that occur when unlocking a monitor need to appear as + * if they happened at the following instruction. See the Dalvik + * instruction spec. + */ + /* monitor-exit vAA */ + EXPORT_PC + GET_VREG %ecx, rINST + movl %ecx, OUT_ARG0(%esp) + movl rSELF, %eax + movl %eax, OUT_ARG1(%esp) + call SYMBOL(artUnlockObjectFromCode) # (object, self) + RESTORE_IBASE + testb %al, %al + jnz MterpException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_move(is_object="0"): + /* for move, move-object, long-to-int */ + /* op vA, vB */ + movzbl rINSTbl, %eax # eax <- BA + andb $$0xf, %al # eax <- A + shrl $$4, rINST # rINST <- B + GET_VREG rINST, rINST + .if $is_object + SET_VREG_OBJECT rINST, %eax # fp[A] <- fp[B] + .else + SET_VREG rINST, %eax # fp[A] <- fp[B] + .endif + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_move_16(is_object="0"): + /* for: move/16, move-object/16 */ + /* op vAAAA, vBBBB */ + movzwl 4(rPC), %ecx # ecx <- BBBB + movzwl 2(rPC), %eax # eax <- AAAA + GET_VREG rINST, %ecx + .if $is_object + SET_VREG_OBJECT rINST, %eax # fp[A] <- fp[B] + .else + SET_VREG rINST, %eax # fp[A] <- fp[B] + .endif + ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 + +%def op_move_exception(): + /* move-exception vAA */ + movl rSELF, %ecx + movl THREAD_EXCEPTION_OFFSET(%ecx), %eax + SET_VREG_OBJECT %eax, rINST # fp[AA] <- exception object + movl $$0, THREAD_EXCEPTION_OFFSET(%ecx) + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_move_from16(is_object="0"): + /* for: move/from16, move-object/from16 */ + /* op vAA, vBBBB */ + movzx rINSTbl, %eax # eax <- AA + movw 2(rPC), rINSTw # rINSTw <- BBBB + GET_VREG rINST, rINST # rINST <- fp[BBBB] + .if $is_object + SET_VREG_OBJECT rINST, %eax # fp[A] <- fp[B] + .else + SET_VREG rINST, %eax # fp[A] <- fp[B] + .endif + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_move_object(): +% op_move(is_object="1") + +%def op_move_object_16(): +% op_move_16(is_object="1") + +%def op_move_object_from16(): +% op_move_from16(is_object="1") + +%def op_move_result(is_object="0"): + /* for: move-result, move-result-object */ + /* op vAA */ + movl OFF_FP_RESULT_REGISTER(rFP), %eax # get pointer to result JType. + movl (%eax), %eax # r0 <- result.i. + .if $is_object + SET_VREG_OBJECT %eax, rINST # fp[A] <- fp[B] + .else + SET_VREG %eax, rINST # fp[A] <- fp[B] + .endif + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_move_result_object(): +% op_move_result(is_object="1") + +%def op_move_result_wide(): + /* move-result-wide vAA */ + movl OFF_FP_RESULT_REGISTER(rFP), %eax # get pointer to result JType. + movl 4(%eax), %ecx # Get high + movl (%eax), %eax # Get low + SET_VREG %eax, rINST # v[AA+0] <- eax + SET_VREG_HIGH %ecx, rINST # v[AA+1] <- ecx + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_move_wide(): + /* move-wide vA, vB */ + /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ + movzbl rINSTbl, %ecx # ecx <- BA + sarl $$4, rINST # rINST <- B + andb $$0xf, %cl # ecx <- A + GET_WIDE_FP_VREG %xmm0, rINST # xmm0 <- v[B] + SET_WIDE_FP_VREG %xmm0, %ecx # v[A] <- xmm0 + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_move_wide_16(): + /* move-wide/16 vAAAA, vBBBB */ + /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ + movzwl 4(rPC), %ecx # ecx<- BBBB + movzwl 2(rPC), %eax # eax<- AAAA + GET_WIDE_FP_VREG %xmm0, %ecx # xmm0 <- v[B] + SET_WIDE_FP_VREG %xmm0, %eax # v[A] <- xmm0 + ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 + +%def op_move_wide_from16(): + /* move-wide/from16 vAA, vBBBB */ + /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ + movzwl 2(rPC), %ecx # ecx <- BBBB + movzbl rINSTbl, %eax # eax <- AAAA + GET_WIDE_FP_VREG %xmm0, %ecx # xmm0 <- v[B] + SET_WIDE_FP_VREG %xmm0, %eax # v[A] <- xmm0 + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_nop(): + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_unused_3e(): +% unused() + +%def op_unused_3f(): +% unused() + +%def op_unused_40(): +% unused() + +%def op_unused_41(): +% unused() + +%def op_unused_42(): +% unused() + +%def op_unused_43(): +% unused() + +%def op_unused_79(): +% unused() + +%def op_unused_7a(): +% unused() + +%def op_unused_f3(): +% unused() + +%def op_unused_f4(): +% unused() + +%def op_unused_f5(): +% unused() + +%def op_unused_f6(): +% unused() + +%def op_unused_f7(): +% unused() + +%def op_unused_f8(): +% unused() + +%def op_unused_f9(): +% unused() + +%def op_unused_fc(): +% unused() + +%def op_unused_fd(): +% unused() diff --git a/runtime/interpreter/mterp/x86/shop2addr.S b/runtime/interpreter/mterp/x86/shop2addr.S deleted file mode 100644 index 96c9954d2162b62b29401036c6eaf1680cdc7550..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/shop2addr.S +++ /dev/null @@ -1,13 +0,0 @@ -%default {"result":"%eax"} -/* - * Generic 32-bit "shift/2addr" operation. - */ - /* shift/2addr vA, vB */ - movzx rINSTbl, %ecx # eax <- BA - sarl $$4, %ecx # ecx <- B - GET_VREG %ecx, %ecx # eax <- vBB - andb $$0xf, rINSTbl # rINST <- A - GET_VREG %eax, rINST # eax <- vAA - $instr # ex: sarl %cl, %eax - SET_VREG $result, rINST - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/sseBinop.S b/runtime/interpreter/mterp/x86/sseBinop.S deleted file mode 100644 index 63a1e21a8f745582486223733472ab0f20270150..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/sseBinop.S +++ /dev/null @@ -1,9 +0,0 @@ -%default {"instr":"","suff":""} - movzbl 2(rPC), %ecx # ecx <- BB - movzbl 3(rPC), %eax # eax <- CC - movs${suff} VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src - ${instr}${suff} VREG_ADDRESS(%eax), %xmm0 - movs${suff} %xmm0, VREG_ADDRESS(rINST) # vAA <- %xmm0 - pxor %xmm0, %xmm0 - movs${suff} %xmm0, VREG_REF_ADDRESS(rINST) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86/sseBinop2Addr.S b/runtime/interpreter/mterp/x86/sseBinop2Addr.S deleted file mode 100644 index d157e67b91924699f40248f7b1dbc0ca3c082aef..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/sseBinop2Addr.S +++ /dev/null @@ -1,10 +0,0 @@ -%default {"instr":"","suff":""} - movzx rINSTbl, %ecx # ecx <- A+ - andl $$0xf, %ecx # ecx <- A - movs${suff} VREG_ADDRESS(%ecx), %xmm0 # %xmm0 <- 1st src - sarl $$4, rINST # rINST<- B - ${instr}${suff} VREG_ADDRESS(rINST), %xmm0 - movs${suff} %xmm0, VREG_ADDRESS(%ecx) # vAA<- %xmm0 - pxor %xmm0, %xmm0 - movs${suff} %xmm0, VREG_REF_ADDRESS(rINST) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/unop.S b/runtime/interpreter/mterp/x86/unop.S deleted file mode 100644 index db09fc04879ff7b670a943f1c2c004d28a728107..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/unop.S +++ /dev/null @@ -1,13 +0,0 @@ -%default {"instr":""} -/* - * Generic 32-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op eax". - */ - /* unop vA, vB */ - movzbl rINSTbl,%ecx # ecx <- A+ - sarl $$4,rINST # rINST <- B - GET_VREG %eax, rINST # eax <- vB - andb $$0xf,%cl # ecx <- A - $instr - SET_VREG %eax, %ecx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86/unused.S b/runtime/interpreter/mterp/x86/unused.S deleted file mode 100644 index c95ef947d3c4187addee86d70f601836922c05c4..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/unused.S +++ /dev/null @@ -1,4 +0,0 @@ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback diff --git a/runtime/interpreter/mterp/x86/zcmp.S b/runtime/interpreter/mterp/x86/zcmp.S deleted file mode 100644 index c1161591c6262d3e718e493784e4228b78a710b2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86/zcmp.S +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Generic one-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - cmpl $$0, VREG_ADDRESS(rINST) # compare (vA, 0) - j${revcmp} 1f - movswl 2(rPC), rINST # fetch signed displacement - testl rINST, rINST - jmp MterpCommonTakenBranch -1: - cmpw $$JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/alt_stub.S b/runtime/interpreter/mterp/x86_64/alt_stub.S deleted file mode 100644 index 24cd1a821d465bb0870c78907b2b8db94ad02b76..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/alt_stub.S +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle - * any interesting requests and then jump to the real instruction - * handler. Unlike the Arm handler, we can't do this as a tail call - * because rIBASE is caller save and we need to reload it. - * - * Note that unlike in the Arm implementation, we should never arrive - * here with a zero breakFlag because we always refresh rIBASE on - * return. - */ - .extern MterpCheckBefore - REFRESH_IBASE - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) - jmp .L_op_nop+(${opnum}*${handler_size_bytes}) diff --git a/runtime/interpreter/mterp/x86_64/arithmetic.S b/runtime/interpreter/mterp/x86_64/arithmetic.S new file mode 100644 index 0000000000000000000000000000000000000000..ffe2008993c8047ecdd78c95faa5dc80bc8dcc67 --- /dev/null +++ b/runtime/interpreter/mterp/x86_64/arithmetic.S @@ -0,0 +1,575 @@ +%def bindiv(result="", second="", wide="", suffix="", rem="0", ext="cdq"): +/* + * 32-bit binary div/rem operation. Handles special case of op1=-1. + */ + /* div/rem vAA, vBB, vCC */ + movzbq 2(rPC), %rax # rax <- BB + movzbq 3(rPC), %rcx # rcx <- CC + .if $wide + GET_WIDE_VREG %rax, %rax # eax <- vBB + GET_WIDE_VREG $second, %rcx # ecx <- vCC + .else + GET_VREG %eax, %rax # eax <- vBB + GET_VREG $second, %rcx # ecx <- vCC + .endif + test${suffix} $second, $second + jz common_errDivideByZero + cmp${suffix} $$-1, $second + je 2f + $ext # rdx:rax <- sign-extended of rax + idiv${suffix} $second +1: + .if $wide + SET_WIDE_VREG $result, rINSTq # eax <- vBB + .else + SET_VREG $result, rINSTq # eax <- vBB + .endif + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 +2: + .if $rem + xor${suffix} $result, $result + .else + neg${suffix} $result + .endif + jmp 1b + +%def bindiv2addr(result="", second="", wide="", suffix="", rem="0", ext="cdq"): +/* + * 32-bit binary div/rem operation. Handles special case of op1=-1. + */ + /* div/rem/2addr vA, vB */ + movl rINST, %ecx # rcx <- BA + sarl $$4, %ecx # rcx <- B + andb $$0xf, rINSTbl # rINST <- A + .if $wide + GET_WIDE_VREG %rax, rINSTq # eax <- vA + GET_WIDE_VREG $second, %rcx # ecx <- vB + .else + GET_VREG %eax, rINSTq # eax <- vA + GET_VREG $second, %rcx # ecx <- vB + .endif + test${suffix} $second, $second + jz common_errDivideByZero + cmp${suffix} $$-1, $second + je 2f + $ext # rdx:rax <- sign-extended of rax + idiv${suffix} $second +1: + .if $wide + SET_WIDE_VREG $result, rINSTq # vA <- result + .else + SET_VREG $result, rINSTq # vA <- result + .endif + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 +2: + .if $rem + xor${suffix} $result, $result + .else + neg${suffix} $result + .endif + jmp 1b + +%def bindivLit16(result="", rem="0"): +/* + * 32-bit binary div/rem operation. Handles special case of op1=-1. + */ + /* div/rem/lit16 vA, vB, #+CCCC */ + /* Need A in rINST, ssssCCCC in ecx, vB in eax */ + movl rINST, %eax # rax <- 000000BA + sarl $$4, %eax # eax <- B + GET_VREG %eax, %rax # eax <- vB + movswl 2(rPC), %ecx # ecx <- ssssCCCC + andb $$0xf, rINSTbl # rINST <- A + testl %ecx, %ecx + jz common_errDivideByZero + cmpl $$-1, %ecx + je 2f + cdq # rax <- sign-extended of eax + idivl %ecx +1: + SET_VREG $result, rINSTq # vA <- result + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 +2: + .if $rem + xorl $result, $result + .else + negl $result + .endif + jmp 1b + +%def bindivLit8(result="", rem="0"): +/* + * 32-bit div/rem "lit8" binary operation. Handles special case of + * op0=minint & op1=-1 + */ + /* div/rem/lit8 vAA, vBB, #+CC */ + movzbq 2(rPC), %rax # eax <- BB + movsbl 3(rPC), %ecx # ecx <- ssssssCC + GET_VREG %eax, %rax # eax <- rBB + testl %ecx, %ecx + je common_errDivideByZero + cmpl $$-1, %ecx + je 2f + cdq # rax <- sign-extended of eax + idivl %ecx +1: + SET_VREG $result, rINSTq # vA <- result + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 +2: + .if $rem + xorl $result, $result + .else + negl $result + .endif + jmp 1b + +%def binop(result="%eax", instr=""): +/* + * Generic 32-bit binary operation. Provide an "instr" line that + * specifies an instruction that performs "result = eax op (rFP,%ecx,4)". + * This could be an x86 instruction or a function call. (If the result + * comes back in a register other than eax, you can override "result".) + * + * For: add-int, sub-int, and-int, or-int, + * xor-int, shl-int, shr-int, ushr-int + */ + /* binop vAA, vBB, vCC */ + movzbq 2(rPC), %rax # rax <- BB + movzbq 3(rPC), %rcx # rcx <- CC + GET_VREG %eax, %rax # eax <- vBB + $instr # ex: addl (rFP,%rcx,4),%eax + SET_VREG $result, rINSTq + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def binop1(wide="0", instr=""): +/* + * Generic 32-bit binary operation in which both operands loaded to + * registers (op0 in eax, op1 in ecx). + */ + /* binop vAA, vBB, vCC */ + movzbq 2(rPC), %rax # eax <- BB + movzbq 3(rPC), %rcx # ecx <- CC + GET_VREG %ecx, %rcx # eax <- vCC + .if $wide + GET_WIDE_VREG %rax, %rax # rax <- vBB + $instr # ex: addl %ecx,%eax + SET_WIDE_VREG %rax, rINSTq + .else + GET_VREG %eax, %rax # eax <- vBB + $instr # ex: addl %ecx,%eax + SET_VREG %eax, rINSTq + .endif + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def binop2addr(result="%eax", instr=""): +/* + * Generic 32-bit "/2addr" binary operation. Provide an "instr" line + * that specifies an instruction that performs "result = r0 op r1". + * This could be an instruction or a function call. + * + * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, + * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, + * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, + * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr + */ + /* binop/2addr vA, vB */ + movl rINST, %ecx # rcx <- A+ + sarl $$4, rINST # rINST <- B + andb $$0xf, %cl # ecx <- A + GET_VREG %eax, rINSTq # eax <- vB + $instr # for ex: addl %eax,(rFP,%ecx,4) + CLEAR_REF %rcx + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def binopLit16(result="%eax", instr=""): +/* + * Generic 32-bit "lit16" binary operation. Provide an "instr" line + * that specifies an instruction that performs "result = eax op ecx". + * This could be an x86 instruction or a function call. (If the result + * comes back in a register other than eax, you can override "result".) + * + * For: add-int/lit16, rsub-int, + * and-int/lit16, or-int/lit16, xor-int/lit16 + */ + /* binop/lit16 vA, vB, #+CCCC */ + movl rINST, %eax # rax <- 000000BA + sarl $$4, %eax # eax <- B + GET_VREG %eax, %rax # eax <- vB + andb $$0xf, rINSTbl # rINST <- A + movswl 2(rPC), %ecx # ecx <- ssssCCCC + $instr # for example: addl %ecx, %eax + SET_VREG $result, rINSTq + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def binopLit8(result="%eax", instr=""): +/* + * Generic 32-bit "lit8" binary operation. Provide an "instr" line + * that specifies an instruction that performs "result = eax op ecx". + * This could be an x86 instruction or a function call. (If the result + * comes back in a register other than r0, you can override "result".) + * + * For: add-int/lit8, rsub-int/lit8 + * and-int/lit8, or-int/lit8, xor-int/lit8, + * shl-int/lit8, shr-int/lit8, ushr-int/lit8 + */ + /* binop/lit8 vAA, vBB, #+CC */ + movzbq 2(rPC), %rax # rax <- BB + movsbl 3(rPC), %ecx # rcx <- ssssssCC + GET_VREG %eax, %rax # eax <- rBB + $instr # ex: addl %ecx,%eax + SET_VREG $result, rINSTq + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def binopWide(instr=""): +/* + * Generic 64-bit binary operation. + */ + /* binop vAA, vBB, vCC */ + movzbq 2(rPC), %rax # eax <- BB + movzbq 3(rPC), %rcx # ecx <- CC + GET_WIDE_VREG %rax, %rax # rax <- v[BB] + $instr # ex: addq (rFP,%rcx,4),%rax + SET_WIDE_VREG %rax, rINSTq # v[AA] <- rax + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def binopWide2addr(instr=""): +/* + * Generic 64-bit binary operation. + */ + /* binop/2addr vA, vB */ + movl rINST, %ecx # rcx <- A+ + sarl $$4, rINST # rINST <- B + andb $$0xf, %cl # ecx <- A + GET_WIDE_VREG %rax, rINSTq # rax <- vB + $instr # for ex: addq %rax,(rFP,%rcx,4) + CLEAR_WIDE_REF %rcx + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def cvtfp_int(fp_suffix="", i_suffix="", max_const="", result_reg="", wide=""): +/* On fp to int conversions, Java requires that + * if the result > maxint, it should be clamped to maxint. If it is less + * than minint, it should be clamped to minint. If it is a nan, the result + * should be zero. Further, the rounding mode is to truncate. + */ + /* float/double to int/long vA, vB */ + movl rINST, %ecx # rcx <- A+ + sarl $$4, rINST # rINST <- B + andb $$0xf, %cl # ecx <- A + movs${fp_suffix} VREG_ADDRESS(rINSTq), %xmm0 + mov${i_suffix} ${max_const}, ${result_reg} + cvtsi2s${fp_suffix}${i_suffix} ${result_reg}, %xmm1 + comis${fp_suffix} %xmm1, %xmm0 + jae 1f + jp 2f + cvtts${fp_suffix}2si${i_suffix} %xmm0, ${result_reg} + jmp 1f +2: + xor${i_suffix} ${result_reg}, ${result_reg} +1: + .if $wide + SET_WIDE_VREG ${result_reg}, %rcx + .else + SET_VREG ${result_reg}, %rcx + .endif + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def shop2addr(wide="0", instr=""): +/* + * Generic 32-bit "shift/2addr" operation. + */ + /* shift/2addr vA, vB */ + movl rINST, %ecx # ecx <- BA + sarl $$4, %ecx # ecx <- B + GET_VREG %ecx, %rcx # ecx <- vBB + andb $$0xf, rINSTbl # rINST <- A + .if $wide + GET_WIDE_VREG %rax, rINSTq # rax <- vAA + $instr # ex: sarl %cl, %eax + SET_WIDE_VREG %rax, rINSTq + .else + GET_VREG %eax, rINSTq # eax <- vAA + $instr # ex: sarl %cl, %eax + SET_VREG %eax, rINSTq + .endif + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def unop(preinstr="", instr="", wide="0"): +/* + * Generic 32/64-bit unary operation. Provide an "instr" line that + * specifies an instruction that performs "result = op eax". + */ + /* unop vA, vB */ + movl rINST, %ecx # rcx <- A+ + sarl $$4,rINST # rINST <- B + .if ${wide} + GET_WIDE_VREG %rax, rINSTq # rax <- vB + .else + GET_VREG %eax, rINSTq # eax <- vB + .endif + andb $$0xf,%cl # ecx <- A +$preinstr +$instr + .if ${wide} + SET_WIDE_VREG %rax, %rcx + .else + SET_VREG %eax, %rcx + .endif + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_add_int(): +% binop(instr="addl (rFP,%rcx,4), %eax") + +%def op_add_int_2addr(): +% binop2addr(instr="addl %eax, (rFP,%rcx,4)") + +%def op_add_int_lit16(): +% binopLit16(instr="addl %ecx, %eax") + +%def op_add_int_lit8(): +% binopLit8(instr="addl %ecx, %eax") + +%def op_add_long(): +% binopWide(instr="addq (rFP,%rcx,4), %rax") + +%def op_add_long_2addr(): +% binopWide2addr(instr="addq %rax, (rFP,%rcx,4)") + +%def op_and_int(): +% binop(instr="andl (rFP,%rcx,4), %eax") + +%def op_and_int_2addr(): +% binop2addr(instr="andl %eax, (rFP,%rcx,4)") + +%def op_and_int_lit16(): +% binopLit16(instr="andl %ecx, %eax") + +%def op_and_int_lit8(): +% binopLit8(instr="andl %ecx, %eax") + +%def op_and_long(): +% binopWide(instr="andq (rFP,%rcx,4), %rax") + +%def op_and_long_2addr(): +% binopWide2addr(instr="andq %rax, (rFP,%rcx,4)") + +%def op_cmp_long(): +/* + * Compare two 64-bit values. Puts 0, 1, or -1 into the destination + * register based on the results of the comparison. + */ + /* cmp-long vAA, vBB, vCC */ + movzbq 2(rPC), %rdx # edx <- BB + movzbq 3(rPC), %rcx # ecx <- CC + GET_WIDE_VREG %rdx, %rdx # rdx <- v[BB] + xorl %eax, %eax + xorl %edi, %edi + addb $$1, %al + movl $$-1, %esi + cmpq VREG_ADDRESS(%rcx), %rdx + cmovl %esi, %edi + cmovg %eax, %edi + SET_VREG %edi, rINSTq + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_div_int(): +% bindiv(result="%eax", second="%ecx", wide="0", suffix="l") + +%def op_div_int_2addr(): +% bindiv2addr(result="%eax", second="%ecx", wide="0", suffix="l") + +%def op_div_int_lit16(): +% bindivLit16(result="%eax") + +%def op_div_int_lit8(): +% bindivLit8(result="%eax") + +%def op_div_long(): +% bindiv(result="%rax", second="%rcx", wide="1", suffix="q", ext="cqo") + +%def op_div_long_2addr(): +% bindiv2addr(result="%rax", second="%rcx", wide="1", suffix="q", ext="cqo") + +%def op_int_to_byte(): +% unop(instr="movsbl %al, %eax") + +%def op_int_to_char(): +% unop(instr="movzwl %ax,%eax") + +%def op_int_to_long(): + /* int to long vA, vB */ + movzbq rINSTbl, %rax # rax <- +A + sarl $$4, %eax # eax <- B + andb $$0xf, rINSTbl # rINST <- A + movslq VREG_ADDRESS(%rax), %rax + SET_WIDE_VREG %rax, rINSTq # v[A] <- %rax + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + + +%def op_int_to_short(): +% unop(instr="movswl %ax, %eax") + +%def op_long_to_int(): +/* we ignore the high word, making this equivalent to a 32-bit reg move */ +% op_move() + +%def op_mul_int(): +% binop(instr="imull (rFP,%rcx,4), %eax") + +%def op_mul_int_2addr(): + /* mul vA, vB */ + movl rINST, %ecx # rcx <- A+ + sarl $$4, rINST # rINST <- B + andb $$0xf, %cl # ecx <- A + GET_VREG %eax, %rcx # eax <- vA + imull (rFP,rINSTq,4), %eax + SET_VREG %eax, %rcx + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_mul_int_lit16(): +% binopLit16(instr="imull %ecx, %eax") + +%def op_mul_int_lit8(): +% binopLit8(instr="imull %ecx, %eax") + +%def op_mul_long(): +% binopWide(instr="imulq (rFP,%rcx,4), %rax") + +%def op_mul_long_2addr(): + /* mul vA, vB */ + movl rINST, %ecx # rcx <- A+ + sarl $$4, rINST # rINST <- B + andb $$0xf, %cl # ecx <- A + GET_WIDE_VREG %rax, %rcx # rax <- vA + imulq (rFP,rINSTq,4), %rax + SET_WIDE_VREG %rax, %rcx + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_neg_int(): +% unop(instr=" negl %eax") + +%def op_neg_long(): +% unop(instr=" negq %rax", wide="1") + +%def op_not_int(): +% unop(instr=" notl %eax") + +%def op_not_long(): +% unop(instr=" notq %rax", wide="1") + +%def op_or_int(): +% binop(instr="orl (rFP,%rcx,4), %eax") + +%def op_or_int_2addr(): +% binop2addr(instr="orl %eax, (rFP,%rcx,4)") + +%def op_or_int_lit16(): +% binopLit16(instr="orl %ecx, %eax") + +%def op_or_int_lit8(): +% binopLit8(instr="orl %ecx, %eax") + +%def op_or_long(): +% binopWide(instr="orq (rFP,%rcx,4), %rax") + +%def op_or_long_2addr(): +% binopWide2addr(instr="orq %rax, (rFP,%rcx,4)") + +%def op_rem_int(): +% bindiv(result="%edx", second="%ecx", wide="0", suffix="l", rem="1") + +%def op_rem_int_2addr(): +% bindiv2addr(result="%edx", second="%ecx", wide="0", suffix="l", rem="1") + +%def op_rem_int_lit16(): +% bindivLit16(result="%edx", rem="1") + +%def op_rem_int_lit8(): +% bindivLit8(result="%edx", rem="1") + +%def op_rem_long(): +% bindiv(result="%rdx", second="%rcx", wide="1", suffix="q", ext="cqo", rem="1") + +%def op_rem_long_2addr(): +% bindiv2addr(result="%rdx", second="%rcx", wide="1", suffix="q", rem="1", ext="cqo") + +%def op_rsub_int(): +/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ +% binopLit16(instr="subl %eax, %ecx", result="%ecx") + +%def op_rsub_int_lit8(): +% binopLit8(instr="subl %eax, %ecx", result="%ecx") + +%def op_shl_int(): +% binop1(instr="sall %cl, %eax") + +%def op_shl_int_2addr(): +% shop2addr(instr="sall %cl, %eax") + +%def op_shl_int_lit8(): +% binopLit8(instr="sall %cl, %eax") + +%def op_shl_long(): +% binop1(instr="salq %cl, %rax", wide="1") + +%def op_shl_long_2addr(): +% shop2addr(instr="salq %cl, %rax", wide="1") + +%def op_shr_int(): +% binop1(instr="sarl %cl, %eax") + +%def op_shr_int_2addr(): +% shop2addr(instr="sarl %cl, %eax") + +%def op_shr_int_lit8(): +% binopLit8(instr="sarl %cl, %eax") + +%def op_shr_long(): +% binop1(instr="sarq %cl, %rax", wide="1") + +%def op_shr_long_2addr(): +% shop2addr(instr="sarq %cl, %rax", wide="1") + +%def op_sub_int(): +% binop(instr="subl (rFP,%rcx,4), %eax") + +%def op_sub_int_2addr(): +% binop2addr(instr="subl %eax, (rFP,%rcx,4)") + +%def op_sub_long(): +% binopWide(instr="subq (rFP,%rcx,4), %rax") + +%def op_sub_long_2addr(): +% binopWide2addr(instr="subq %rax, (rFP,%rcx,4)") + +%def op_ushr_int(): +% binop1(instr="shrl %cl, %eax") + +%def op_ushr_int_2addr(): +% shop2addr(instr="shrl %cl, %eax") + +%def op_ushr_int_lit8(): +% binopLit8(instr="shrl %cl, %eax") + +%def op_ushr_long(): +% binop1(instr="shrq %cl, %rax", wide="1") + +%def op_ushr_long_2addr(): +% shop2addr(instr="shrq %cl, %rax", wide="1") + +%def op_xor_int(): +% binop(instr="xorl (rFP,%rcx,4), %eax") + +%def op_xor_int_2addr(): +% binop2addr(instr="xorl %eax, (rFP,%rcx,4)") + +%def op_xor_int_lit16(): +% binopLit16(instr="xorl %ecx, %eax") + +%def op_xor_int_lit8(): +% binopLit8(instr="xorl %ecx, %eax") + +%def op_xor_long(): +% binopWide(instr="xorq (rFP,%rcx,4), %rax") + +%def op_xor_long_2addr(): +% binopWide2addr(instr="xorq %rax, (rFP,%rcx,4)") diff --git a/runtime/interpreter/mterp/x86_64/array.S b/runtime/interpreter/mterp/x86_64/array.S new file mode 100644 index 0000000000000000000000000000000000000000..e49c09778cc32a79fb276627f3dc86a0e21d61e3 --- /dev/null +++ b/runtime/interpreter/mterp/x86_64/array.S @@ -0,0 +1,178 @@ +%def op_aget(load="movl", shift="4", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET", wide="0"): +/* + * Array get, 32 bits or less. vAA <- vBB[vCC]. + * + * for: aget, aget-boolean, aget-byte, aget-char, aget-short, aget-wide + * + */ + /* op vAA, vBB, vCC */ + movzbq 2(rPC), %rax # eax <- BB + movzbq 3(rPC), %rcx # ecx <- CC + GET_VREG %eax, %rax # eax <- vBB (array object) + GET_VREG %ecx, %rcx # ecx <- vCC (requested index) + testl %eax, %eax # null array object? + je common_errNullObject # bail if so + cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx + jae common_errArrayIndex # index >= length, bail. + .if $wide + movq $data_offset(%rax,%rcx,8), %rax + SET_WIDE_VREG %rax, rINSTq + .else + $load $data_offset(%rax,%rcx,$shift), %eax + SET_VREG %eax, rINSTq + .endif + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_aget_boolean(): +% op_aget(load="movzbl", shift="1", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") + +%def op_aget_byte(): +% op_aget(load="movsbl", shift="1", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") + +%def op_aget_char(): +% op_aget(load="movzwl", shift="2", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") + +%def op_aget_object(): +/* + * Array object get. vAA <- vBB[vCC]. + * + * for: aget-object + */ + /* op vAA, vBB, vCC */ + movzbq 2(rPC), %rax # rax <- BB + movzbq 3(rPC), %rcx # rcx <- CC + GET_VREG OUT_32_ARG0, %rax # eax <- vBB (array object) + GET_VREG OUT_32_ARG1, %rcx # ecx <- vCC (requested index) + EXPORT_PC + call SYMBOL(artAGetObjectFromMterp) # (array, index) + movq rSELF, %rcx + cmpq $$0, THREAD_EXCEPTION_OFFSET(%rcx) + jnz MterpException + SET_VREG_OBJECT %eax, rINSTq + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_aget_short(): +% op_aget(load="movswl", shift="2", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") + +%def op_aget_wide(): +% op_aget(load="movq", shift="8", data_offset="MIRROR_WIDE_ARRAY_DATA_OFFSET", wide="1") + +%def op_aput(reg="rINST", store="movl", shift="4", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET", wide="0"): +/* + * Array put, 32 bits or less. vBB[vCC] <- vAA. + * + * for: aput, aput-boolean, aput-byte, aput-char, aput-short, aput-wide + * + */ + /* op vAA, vBB, vCC */ + movzbq 2(rPC), %rax # rax <- BB + movzbq 3(rPC), %rcx # rcx <- CC + GET_VREG %eax, %rax # eax <- vBB (array object) + GET_VREG %ecx, %rcx # ecx <- vCC (requested index) + testl %eax, %eax # null array object? + je common_errNullObject # bail if so + cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx + jae common_errArrayIndex # index >= length, bail. + .if $wide + GET_WIDE_VREG rINSTq, rINSTq + .else + GET_VREG rINST, rINSTq + .endif + $store $reg, $data_offset(%rax,%rcx,$shift) + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_aput_boolean(): +% op_aput(reg="rINSTbl", store="movb", shift="1", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET") + +%def op_aput_byte(): +% op_aput(reg="rINSTbl", store="movb", shift="1", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET") + +%def op_aput_char(): +% op_aput(reg="rINSTw", store="movw", shift="2", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET") + +%def op_aput_object(): +/* + * Store an object into an array. vBB[vCC] <- vAA. + */ + /* op vAA, vBB, vCC */ + EXPORT_PC + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG0 + movq rPC, OUT_ARG1 + REFRESH_INST ${opnum} + movq rINSTq, OUT_ARG2 + call SYMBOL(MterpAputObject) # (array, index) + testb %al, %al + jz MterpPossibleException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_aput_short(): +% op_aput(reg="rINSTw", store="movw", shift="2", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET") + +%def op_aput_wide(): +% op_aput(reg="rINSTq", store="movq", shift="8", data_offset="MIRROR_WIDE_ARRAY_DATA_OFFSET", wide="1") + +%def op_array_length(): +/* + * Return the length of an array. + */ + movl rINST, %eax # eax <- BA + sarl $$4, rINST # rINST <- B + GET_VREG %ecx, rINSTq # ecx <- vB (object ref) + testl %ecx, %ecx # is null? + je common_errNullObject + andb $$0xf, %al # eax <- A + movl MIRROR_ARRAY_LENGTH_OFFSET(%rcx), rINST + SET_VREG rINST, %rax + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_fill_array_data(): + /* fill-array-data vAA, +BBBBBBBB */ + EXPORT_PC + movslq 2(rPC), %rcx # rcx <- ssssssssBBBBbbbb + leaq (rPC,%rcx,2), OUT_ARG1 # OUT_ARG1 <- PC + ssssssssBBBBbbbb*2 + GET_VREG OUT_32_ARG0, rINSTq # OUT_ARG0 <- vAA (array object) + call SYMBOL(MterpFillArrayData) # (obj, payload) + testb %al, %al # 0 means an exception is thrown + jz MterpPossibleException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 + +%def op_filled_new_array(helper="MterpFilledNewArray"): +/* + * Create a new array with elements filled from registers. + * + * for: filled-new-array, filled-new-array/range + */ + /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ + /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ + .extern $helper + EXPORT_PC + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG0 + movq rPC, OUT_ARG1 + movq rSELF, OUT_ARG2 + call SYMBOL($helper) + testb %al, %al # 0 means an exception is thrown + jz MterpPossibleException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 + +%def op_filled_new_array_range(): +% op_filled_new_array(helper="MterpFilledNewArrayRange") + +%def op_new_array(): +/* + * Allocate an array of objects, specified with the array class + * and a count. + * + * The verifier guarantees that this is an array class, so we don't + * check for it here. + */ + /* new-array vA, vB, class@CCCC */ + EXPORT_PC + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG0 + movq rPC, OUT_ARG1 + REFRESH_INST ${opnum} + movq rINSTq, OUT_ARG2 + movq rSELF, OUT_ARG3 + call SYMBOL(MterpNewArray) + testb %al, %al # 0 means an exception is thrown + jz MterpPossibleException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/bincmp.S b/runtime/interpreter/mterp/x86_64/bincmp.S deleted file mode 100644 index 6601483ebe177cd54800cc340edf45dc6cce0cb2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/bincmp.S +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Generic two-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le - */ - /* if-cmp vA, vB, +CCCC */ - movl rINST, %ecx # rcx <- A+ - sarl $$4, rINST # rINST <- B - andb $$0xf, %cl # rcx <- A - GET_VREG %eax, %rcx # eax <- vA - cmpl VREG_ADDRESS(rINSTq), %eax # compare (vA, vB) - j${revcmp} 1f - movswq 2(rPC), rINSTq # Get signed branch offset - testq rINSTq, rINSTq - jmp MterpCommonTakenBranch -1: - cmpl $$JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/bindiv.S b/runtime/interpreter/mterp/x86_64/bindiv.S deleted file mode 100644 index e10d1dc4b10094c4a99b6a31df435fc1091e6362..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/bindiv.S +++ /dev/null @@ -1,34 +0,0 @@ -%default {"result":"","second":"","wide":"","suffix":"","rem":"0","ext":"cdq"} -/* - * 32-bit binary div/rem operation. Handles special case of op1=-1. - */ - /* div/rem vAA, vBB, vCC */ - movzbq 2(rPC), %rax # rax <- BB - movzbq 3(rPC), %rcx # rcx <- CC - .if $wide - GET_WIDE_VREG %rax, %rax # eax <- vBB - GET_WIDE_VREG $second, %rcx # ecx <- vCC - .else - GET_VREG %eax, %rax # eax <- vBB - GET_VREG $second, %rcx # ecx <- vCC - .endif - test${suffix} $second, $second - jz common_errDivideByZero - cmp${suffix} $$-1, $second - je 2f - $ext # rdx:rax <- sign-extended of rax - idiv${suffix} $second -1: - .if $wide - SET_WIDE_VREG $result, rINSTq # eax <- vBB - .else - SET_VREG $result, rINSTq # eax <- vBB - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 -2: - .if $rem - xor${suffix} $result, $result - .else - neg${suffix} $result - .endif - jmp 1b diff --git a/runtime/interpreter/mterp/x86_64/bindiv2addr.S b/runtime/interpreter/mterp/x86_64/bindiv2addr.S deleted file mode 100644 index 8b9bc953d2e6591f1551b6a159b9bde61c2f4429..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/bindiv2addr.S +++ /dev/null @@ -1,35 +0,0 @@ -%default {"result":"","second":"","wide":"","suffix":"","rem":"0","ext":"cdq"} -/* - * 32-bit binary div/rem operation. Handles special case of op1=-1. - */ - /* div/rem/2addr vA, vB */ - movl rINST, %ecx # rcx <- BA - sarl $$4, %ecx # rcx <- B - andb $$0xf, rINSTbl # rINST <- A - .if $wide - GET_WIDE_VREG %rax, rINSTq # eax <- vA - GET_WIDE_VREG $second, %rcx # ecx <- vB - .else - GET_VREG %eax, rINSTq # eax <- vA - GET_VREG $second, %rcx # ecx <- vB - .endif - test${suffix} $second, $second - jz common_errDivideByZero - cmp${suffix} $$-1, $second - je 2f - $ext # rdx:rax <- sign-extended of rax - idiv${suffix} $second -1: - .if $wide - SET_WIDE_VREG $result, rINSTq # vA <- result - .else - SET_VREG $result, rINSTq # vA <- result - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 -2: - .if $rem - xor${suffix} $result, $result - .else - neg${suffix} $result - .endif - jmp 1b diff --git a/runtime/interpreter/mterp/x86_64/bindivLit16.S b/runtime/interpreter/mterp/x86_64/bindivLit16.S deleted file mode 100644 index 80dbce297549f5b192b03beffeae28237347e011..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/bindivLit16.S +++ /dev/null @@ -1,27 +0,0 @@ -%default {"result":"","rem":"0"} -/* - * 32-bit binary div/rem operation. Handles special case of op1=-1. - */ - /* div/rem/lit16 vA, vB, #+CCCC */ - /* Need A in rINST, ssssCCCC in ecx, vB in eax */ - movl rINST, %eax # rax <- 000000BA - sarl $$4, %eax # eax <- B - GET_VREG %eax, %rax # eax <- vB - movswl 2(rPC), %ecx # ecx <- ssssCCCC - andb $$0xf, rINSTbl # rINST <- A - testl %ecx, %ecx - jz common_errDivideByZero - cmpl $$-1, %ecx - je 2f - cdq # rax <- sign-extended of eax - idivl %ecx -1: - SET_VREG $result, rINSTq # vA <- result - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 -2: - .if $rem - xorl $result, $result - .else - negl $result - .endif - jmp 1b diff --git a/runtime/interpreter/mterp/x86_64/bindivLit8.S b/runtime/interpreter/mterp/x86_64/bindivLit8.S deleted file mode 100644 index ab535f3fb0a564e1f06e21ada90f7b87d5597971..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/bindivLit8.S +++ /dev/null @@ -1,25 +0,0 @@ -%default {"result":"","rem":"0"} -/* - * 32-bit div/rem "lit8" binary operation. Handles special case of - * op0=minint & op1=-1 - */ - /* div/rem/lit8 vAA, vBB, #+CC */ - movzbq 2(rPC), %rax # eax <- BB - movsbl 3(rPC), %ecx # ecx <- ssssssCC - GET_VREG %eax, %rax # eax <- rBB - testl %ecx, %ecx - je common_errDivideByZero - cmpl $$-1, %ecx - je 2f - cdq # rax <- sign-extended of eax - idivl %ecx -1: - SET_VREG $result, rINSTq # vA <- result - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 -2: - .if $rem - xorl $result, $result - .else - negl $result - .endif - jmp 1b diff --git a/runtime/interpreter/mterp/x86_64/binop.S b/runtime/interpreter/mterp/x86_64/binop.S deleted file mode 100644 index 962dd61eea875919314693b1121ab165b7705813..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/binop.S +++ /dev/null @@ -1,17 +0,0 @@ -%default {"result":"%eax"} -/* - * Generic 32-bit binary operation. Provide an "instr" line that - * specifies an instruction that performs "result = eax op (rFP,%ecx,4)". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int, sub-int, and-int, or-int, - * xor-int, shl-int, shr-int, ushr-int - */ - /* binop vAA, vBB, vCC */ - movzbq 2(rPC), %rax # rax <- BB - movzbq 3(rPC), %rcx # rcx <- CC - GET_VREG %eax, %rax # eax <- vBB - $instr # ex: addl (rFP,%rcx,4),%eax - SET_VREG $result, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/binop1.S b/runtime/interpreter/mterp/x86_64/binop1.S deleted file mode 100644 index bdd57325aadaf04611b72eb1dfa41dd224ad36d0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/binop1.S +++ /dev/null @@ -1,19 +0,0 @@ -%default {"wide":"0"} -/* - * Generic 32-bit binary operation in which both operands loaded to - * registers (op0 in eax, op1 in ecx). - */ - /* binop vAA, vBB, vCC */ - movzbq 2(rPC), %rax # eax <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_VREG %ecx, %rcx # eax <- vCC - .if $wide - GET_WIDE_VREG %rax, %rax # rax <- vBB - $instr # ex: addl %ecx,%eax - SET_WIDE_VREG %rax, rINSTq - .else - GET_VREG %eax, %rax # eax <- vBB - $instr # ex: addl %ecx,%eax - SET_VREG %eax, rINSTq - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/binop2addr.S b/runtime/interpreter/mterp/x86_64/binop2addr.S deleted file mode 100644 index 4448a815e99cee6ae86bbd36cafe350c973aa996..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/binop2addr.S +++ /dev/null @@ -1,19 +0,0 @@ -%default {"result":"%eax"} -/* - * Generic 32-bit "/2addr" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = r0 op r1". - * This could be an instruction or a function call. - * - * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, - * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, - * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, - * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr - */ - /* binop/2addr vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $$4, rINST # rINST <- B - andb $$0xf, %cl # ecx <- A - GET_VREG %eax, rINSTq # eax <- vB - $instr # for ex: addl %eax,(rFP,%ecx,4) - CLEAR_REF %rcx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86_64/binopLit16.S b/runtime/interpreter/mterp/x86_64/binopLit16.S deleted file mode 100644 index de43b53d5cb3615f6a29895dafec80d11e80e656..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/binopLit16.S +++ /dev/null @@ -1,19 +0,0 @@ -%default {"result":"%eax"} -/* - * Generic 32-bit "lit16" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than eax, you can override "result".) - * - * For: add-int/lit16, rsub-int, - * and-int/lit16, or-int/lit16, xor-int/lit16 - */ - /* binop/lit16 vA, vB, #+CCCC */ - movl rINST, %eax # rax <- 000000BA - sarl $$4, %eax # eax <- B - GET_VREG %eax, %rax # eax <- vB - andb $$0xf, rINSTbl # rINST <- A - movswl 2(rPC), %ecx # ecx <- ssssCCCC - $instr # for example: addl %ecx, %eax - SET_VREG $result, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/binopLit8.S b/runtime/interpreter/mterp/x86_64/binopLit8.S deleted file mode 100644 index 995002b7e45caa3161910f8c8d4bd590a91d618b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/binopLit8.S +++ /dev/null @@ -1,18 +0,0 @@ -%default {"result":"%eax"} -/* - * Generic 32-bit "lit8" binary operation. Provide an "instr" line - * that specifies an instruction that performs "result = eax op ecx". - * This could be an x86 instruction or a function call. (If the result - * comes back in a register other than r0, you can override "result".) - * - * For: add-int/lit8, rsub-int/lit8 - * and-int/lit8, or-int/lit8, xor-int/lit8, - * shl-int/lit8, shr-int/lit8, ushr-int/lit8 - */ - /* binop/lit8 vAA, vBB, #+CC */ - movzbq 2(rPC), %rax # rax <- BB - movsbl 3(rPC), %ecx # rcx <- ssssssCC - GET_VREG %eax, %rax # eax <- rBB - $instr # ex: addl %ecx,%eax - SET_VREG $result, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/binopWide.S b/runtime/interpreter/mterp/x86_64/binopWide.S deleted file mode 100644 index f92f18e013a6b46c99c8319a3f991538fd78e65e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/binopWide.S +++ /dev/null @@ -1,10 +0,0 @@ -/* - * Generic 64-bit binary operation. - */ - /* binop vAA, vBB, vCC */ - movzbq 2(rPC), %rax # eax <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_WIDE_VREG %rax, %rax # rax <- v[BB] - $instr # ex: addq (rFP,%rcx,4),%rax - SET_WIDE_VREG %rax, rINSTq # v[AA] <- rax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/binopWide2addr.S b/runtime/interpreter/mterp/x86_64/binopWide2addr.S deleted file mode 100644 index d9e6cfbc9dc05700f635886bf6dda83dd3ec50a2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/binopWide2addr.S +++ /dev/null @@ -1,11 +0,0 @@ -/* - * Generic 64-bit binary operation. - */ - /* binop/2addr vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $$4, rINST # rINST <- B - andb $$0xf, %cl # ecx <- A - GET_WIDE_VREG %rax, rINSTq # rax <- vB - $instr # for ex: addq %rax,(rFP,%rcx,4) - CLEAR_WIDE_REF %rcx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86_64/const.S b/runtime/interpreter/mterp/x86_64/const.S deleted file mode 100644 index 1ddf20fdca66ab4bdd02920b6d77adcacf01442a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/const.S +++ /dev/null @@ -1,15 +0,0 @@ -%default { "helper":"UndefinedConstHandler" } - /* const/class vAA, type@BBBB */ - /* const/method-handle vAA, method_handle@BBBB */ - /* const/method-type vAA, proto@BBBB */ - /* const/string vAA, string@@BBBB */ - .extern $helper - EXPORT_PC - movzwq 2(rPC), OUT_ARG0 # eax <- OUT_ARG0 - movq rINSTq, OUT_ARG1 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 - movq rSELF, OUT_ARG3 - call SYMBOL($helper) # (index, tgt_reg, shadow_frame, self) - testb %al, %al - jnz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/control_flow.S b/runtime/interpreter/mterp/x86_64/control_flow.S new file mode 100644 index 0000000000000000000000000000000000000000..2f3b5e560f9844c6503c476c82a1c47653e1b395 --- /dev/null +++ b/runtime/interpreter/mterp/x86_64/control_flow.S @@ -0,0 +1,206 @@ +%def bincmp(revcmp=""): +/* + * Generic two-operand compare-and-branch operation. Provide a "revcmp" + * fragment that specifies the *reverse* comparison to perform, e.g. + * for "if-le" you would use "gt". + * + * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le + */ + /* if-cmp vA, vB, +CCCC */ + movl rINST, %ecx # rcx <- A+ + sarl $$4, rINST # rINST <- B + andb $$0xf, %cl # rcx <- A + GET_VREG %eax, %rcx # eax <- vA + cmpl VREG_ADDRESS(rINSTq), %eax # compare (vA, vB) + j${revcmp} 1f + movswq 2(rPC), rINSTq # Get signed branch offset + testq rINSTq, rINSTq + jmp MterpCommonTakenBranch +1: + cmpl $$JIT_CHECK_OSR, rPROFILE + je .L_check_not_taken_osr + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def zcmp(revcmp=""): +/* + * Generic one-operand compare-and-branch operation. Provide a "revcmp" + * fragment that specifies the *reverse* comparison to perform, e.g. + * for "if-le" you would use "gt". + * + * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez + */ + /* if-cmp vAA, +BBBB */ + cmpl $$0, VREG_ADDRESS(rINSTq) # compare (vA, 0) + j${revcmp} 1f + movswq 2(rPC), rINSTq # fetch signed displacement + testq rINSTq, rINSTq + jmp MterpCommonTakenBranch +1: + cmpl $$JIT_CHECK_OSR, rPROFILE + je .L_check_not_taken_osr + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_goto(): +/* + * Unconditional branch, 8-bit offset. + * + * The branch distance is a signed code-unit offset, which we need to + * double to get a byte offset. + */ + /* goto +AA */ + movsbq rINSTbl, rINSTq # rINSTq <- ssssssAA + testq rINSTq, rINSTq + jmp MterpCommonTakenBranch + +%def op_goto_16(): +/* + * Unconditional branch, 16-bit offset. + * + * The branch distance is a signed code-unit offset, which we need to + * double to get a byte offset. + */ + /* goto/16 +AAAA */ + movswq 2(rPC), rINSTq # rINSTq <- ssssAAAA + testq rINSTq, rINSTq + jmp MterpCommonTakenBranch + +%def op_goto_32(): +/* + * Unconditional branch, 32-bit offset. + * + * The branch distance is a signed code-unit offset, which we need to + * double to get a byte offset. + * + * Because we need the SF bit set, we'll use an adds + * to convert from Dalvik offset to byte offset. + */ + /* goto/32 +AAAAAAAA */ + movslq 2(rPC), rINSTq # rINSTq <- AAAAAAAA + testq rINSTq, rINSTq + jmp MterpCommonTakenBranch + +%def op_if_eq(): +% bincmp(revcmp="ne") + +%def op_if_eqz(): +% zcmp(revcmp="ne") + +%def op_if_ge(): +% bincmp(revcmp="l") + +%def op_if_gez(): +% zcmp(revcmp="l") + +%def op_if_gt(): +% bincmp(revcmp="le") + +%def op_if_gtz(): +% zcmp(revcmp="le") + +%def op_if_le(): +% bincmp(revcmp="g") + +%def op_if_lez(): +% zcmp(revcmp="g") + +%def op_if_lt(): +% bincmp(revcmp="ge") + +%def op_if_ltz(): +% zcmp(revcmp="ge") + +%def op_if_ne(): +% bincmp(revcmp="e") + +%def op_if_nez(): +% zcmp(revcmp="e") + +%def op_packed_switch(func="MterpDoPackedSwitch"): +/* + * Handle a packed-switch or sparse-switch instruction. In both cases + * we decode it and hand it off to a helper function. + * + * We don't really expect backward branches in a switch statement, but + * they're perfectly legal, so we check for them here. + * + * for: packed-switch, sparse-switch + */ + /* op vAA, +BBBB */ + movslq 2(rPC), OUT_ARG0 # rcx <- ssssssssBBBBbbbb + leaq (rPC,OUT_ARG0,2), OUT_ARG0 # rcx <- PC + ssssssssBBBBbbbb*2 + GET_VREG OUT_32_ARG1, rINSTq # eax <- vAA + call SYMBOL($func) + testl %eax, %eax + movslq %eax, rINSTq + jmp MterpCommonTakenBranch + +%def op_return(): +/* + * Return a 32-bit value. + * + * for: return, return-object + */ + /* op vAA */ + .extern MterpThreadFenceForConstructor + call SYMBOL(MterpThreadFenceForConstructor) + movq rSELF, OUT_ARG0 + testl $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(OUT_ARG0) + jz 1f + call SYMBOL(MterpSuspendCheck) +1: + GET_VREG %eax, rINSTq # eax <- vAA + jmp MterpReturn + +%def op_return_object(): +% op_return() + +%def op_return_void(): + .extern MterpThreadFenceForConstructor + call SYMBOL(MterpThreadFenceForConstructor) + movq rSELF, OUT_ARG0 + testl $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(OUT_ARG0) + jz 1f + call SYMBOL(MterpSuspendCheck) +1: + xorq %rax, %rax + jmp MterpReturn + +%def op_return_void_no_barrier(): + movq rSELF, OUT_ARG0 + testl $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(OUT_ARG0) + jz 1f + call SYMBOL(MterpSuspendCheck) +1: + xorq %rax, %rax + jmp MterpReturn + +%def op_return_wide(): +/* + * Return a 64-bit value. + */ + /* return-wide vAA */ + .extern MterpThreadFenceForConstructor + call SYMBOL(MterpThreadFenceForConstructor) + movq rSELF, OUT_ARG0 + testl $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(OUT_ARG0) + jz 1f + call SYMBOL(MterpSuspendCheck) +1: + GET_WIDE_VREG %rax, rINSTq # eax <- v[AA] + jmp MterpReturn + +%def op_sparse_switch(): +% op_packed_switch(func="MterpDoSparseSwitch") + +%def op_throw(): +/* + * Throw an exception object in the current thread. + */ + /* throw vAA */ + EXPORT_PC + GET_VREG %eax, rINSTq # eax<- vAA (exception object) + testb %al, %al + jz common_errNullObject + movq rSELF, %rcx + movq %rax, THREAD_EXCEPTION_OFFSET(%rcx) + jmp MterpException diff --git a/runtime/interpreter/mterp/x86_64/cvtfp_int.S b/runtime/interpreter/mterp/x86_64/cvtfp_int.S deleted file mode 100644 index 1472bd26bd5f13ee9cab83fd374aaa87be6edf36..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/cvtfp_int.S +++ /dev/null @@ -1,27 +0,0 @@ -%default {"fp_suffix":"","i_suffix":"","max_const":"","result_reg":"","wide":""} -/* On fp to int conversions, Java requires that - * if the result > maxint, it should be clamped to maxint. If it is less - * than minint, it should be clamped to minint. If it is a nan, the result - * should be zero. Further, the rounding mode is to truncate. - */ - /* float/double to int/long vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $$4, rINST # rINST <- B - andb $$0xf, %cl # ecx <- A - movs${fp_suffix} VREG_ADDRESS(rINSTq), %xmm0 - mov${i_suffix} ${max_const}, ${result_reg} - cvtsi2s${fp_suffix}${i_suffix} ${result_reg}, %xmm1 - comis${fp_suffix} %xmm1, %xmm0 - jae 1f - jp 2f - cvtts${fp_suffix}2si${i_suffix} %xmm0, ${result_reg} - jmp 1f -2: - xor${i_suffix} ${result_reg}, ${result_reg} -1: - .if $wide - SET_WIDE_VREG ${result_reg}, %rcx - .else - SET_VREG ${result_reg}, %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86_64/entry.S b/runtime/interpreter/mterp/x86_64/entry.S deleted file mode 100644 index b08419b2199c410a24af64ea5ba2c63c3ba69bdb..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/entry.S +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -/* - * Interpreter entry point. - */ - - .text - ASM_HIDDEN SYMBOL(ExecuteMterpImpl) - .global SYMBOL(ExecuteMterpImpl) - FUNCTION_TYPE(ExecuteMterpImpl) - -/* - * On entry: - * 0 Thread* self - * 1 insns_ - * 2 ShadowFrame - * 3 JValue* result_register - * - */ - -SYMBOL(ExecuteMterpImpl): - .cfi_startproc - .cfi_def_cfa rsp, 8 - - /* Spill callee save regs */ - PUSH %rbx - PUSH %rbp - PUSH %r12 - PUSH %r13 - PUSH %r14 - PUSH %r15 - - /* Allocate frame */ - subq $$FRAME_SIZE, %rsp - .cfi_adjust_cfa_offset FRAME_SIZE - - /* Remember the return register */ - movq IN_ARG3, SHADOWFRAME_RESULT_REGISTER_OFFSET(IN_ARG2) - - /* Remember the code_item */ - movq IN_ARG1, SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET(IN_ARG2) - - /* set up "named" registers */ - movl SHADOWFRAME_NUMBER_OF_VREGS_OFFSET(IN_ARG2), %eax - leaq SHADOWFRAME_VREGS_OFFSET(IN_ARG2), rFP - leaq (rFP, %rax, 4), rREFS - movl SHADOWFRAME_DEX_PC_OFFSET(IN_ARG2), %eax - leaq (IN_ARG1, %rax, 2), rPC - CFI_DEFINE_DEX_PC_WITH_OFFSET(CFI_TMP, CFI_DEX, 0) - EXPORT_PC - - /* Starting ibase */ - movq IN_ARG0, rSELF - REFRESH_IBASE_REG IN_ARG0 - - /* Set up for backwards branches & osr profiling */ - movq IN_ARG0, OUT_ARG2 /* Set up OUT_ARG2 before clobbering IN_ARG0 */ - movq OFF_FP_METHOD(rFP), OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - call SYMBOL(MterpSetUpHotnessCountdown) - movswl %ax, rPROFILE - - /* start executing the instruction at rPC */ - FETCH_INST - GOTO_NEXT - /* NOTE: no fallthrough */ diff --git a/runtime/interpreter/mterp/x86_64/fallback.S b/runtime/interpreter/mterp/x86_64/fallback.S deleted file mode 100644 index 8d61166f63d57a950db9bb1e3bceef3edb6a8374..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/fallback.S +++ /dev/null @@ -1,3 +0,0 @@ -/* Transfer stub to alternate interpreter */ - jmp MterpFallback - diff --git a/runtime/interpreter/mterp/x86_64/field.S b/runtime/interpreter/mterp/x86_64/field.S deleted file mode 100644 index f8b0588e1be4ace13dfa41b43e8e29449cc175fc..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/field.S +++ /dev/null @@ -1,14 +0,0 @@ -%default { } - /* - * General field read / write (iget-* iput-* sget-* sput-*). - */ - .extern $helper - REFRESH_INST ${opnum} # fix rINST to include opcode - movq rPC, OUT_ARG0 # arg0: Instruction* inst - movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf - movq rSELF, OUT_ARG3 # arg3: Thread* self - call SYMBOL($helper) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/floating_point.S b/runtime/interpreter/mterp/x86_64/floating_point.S new file mode 100644 index 0000000000000000000000000000000000000000..b40c0e632ef17238caf3fd0a977cc06b7353a9db --- /dev/null +++ b/runtime/interpreter/mterp/x86_64/floating_point.S @@ -0,0 +1,236 @@ +%def fpcmp(suff="d", nanval="pos"): +/* + * Compare two floating-point values. Puts 0, 1, or -1 into the + * destination register based on the results of the comparison. + * + * int compare(x, y) { + * if (x == y) { + * return 0; + * } else if (x < y) { + * return -1; + * } else if (x > y) { + * return 1; + * } else { + * return nanval ? 1 : -1; + * } + * } + */ + /* op vAA, vBB, vCC */ + movzbq 3(rPC), %rcx # ecx<- CC + movzbq 2(rPC), %rax # eax<- BB + movs${suff} VREG_ADDRESS(%rax), %xmm0 + xor %eax, %eax + ucomis${suff} VREG_ADDRESS(%rcx), %xmm0 + jp .L${opcode}_nan_is_${nanval} + je .L${opcode}_finish + jb .L${opcode}_less +.L${opcode}_nan_is_pos: + addb $$1, %al + jmp .L${opcode}_finish +.L${opcode}_nan_is_neg: +.L${opcode}_less: + movl $$-1, %eax +.L${opcode}_finish: + SET_VREG %eax, rINSTq + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def fpcvt(source_suffix="", dest_suffix="", wide=""): +/* + * Generic 32-bit FP conversion operation. + */ + /* unop vA, vB */ + movl rINST, %ecx # rcx <- A+ + sarl $$4, rINST # rINST <- B + andb $$0xf, %cl # ecx <- A + cvts${source_suffix}2s${dest_suffix} VREG_ADDRESS(rINSTq), %xmm0 + .if $wide + movsd %xmm0, VREG_ADDRESS(%rcx) + CLEAR_WIDE_REF %rcx + .else + movss %xmm0, VREG_ADDRESS(%rcx) + CLEAR_REF %rcx + .endif + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def sseBinop(instr="", suff=""): + movzbq 2(rPC), %rcx # ecx <- BB + movzbq 3(rPC), %rax # eax <- CC + movs${suff} VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src + ${instr}${suff} VREG_ADDRESS(%rax), %xmm0 + movs${suff} %xmm0, VREG_ADDRESS(rINSTq) # vAA <- %xmm0 + pxor %xmm0, %xmm0 + movs${suff} %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def sseBinop2Addr(instr="", suff=""): + movl rINST, %ecx # ecx <- A+ + andl $$0xf, %ecx # ecx <- A + movs${suff} VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src + sarl $$4, rINST # rINST<- B + ${instr}${suff} VREG_ADDRESS(rINSTq), %xmm0 + movs${suff} %xmm0, VREG_ADDRESS(%rcx) # vAA<- %xmm0 + pxor %xmm0, %xmm0 + movs${suff} %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_add_double(): +% sseBinop(instr="adds", suff="d") + +%def op_add_double_2addr(): +% sseBinop2Addr(instr="adds", suff="d") + +%def op_add_float(): +% sseBinop(instr="adds", suff="s") + +%def op_add_float_2addr(): +% sseBinop2Addr(instr="adds", suff="s") + +%def op_cmpg_double(): +% fpcmp(suff="d", nanval="pos") + +%def op_cmpg_float(): +% fpcmp(suff="s", nanval="pos") + +%def op_cmpl_double(): +% fpcmp(suff="d", nanval="neg") + +%def op_cmpl_float(): +% fpcmp(suff="s", nanval="neg") + +%def op_div_double(): +% sseBinop(instr="divs", suff="d") + +%def op_div_double_2addr(): +% sseBinop2Addr(instr="divs", suff="d") + +%def op_div_float(): +% sseBinop(instr="divs", suff="s") + +%def op_div_float_2addr(): +% sseBinop2Addr(instr="divs", suff="s") + +%def op_double_to_float(): +% fpcvt(source_suffix="d", dest_suffix="s", wide="0") + +%def op_double_to_int(): +% cvtfp_int(fp_suffix="d", i_suffix="l", max_const="$0x7fffffff", result_reg="%eax", wide="0") + +%def op_double_to_long(): +% cvtfp_int(fp_suffix="d", i_suffix="q", max_const="$0x7fffffffffffffff", result_reg="%rax", wide="1") + +%def op_float_to_double(): +% fpcvt(source_suffix="s", dest_suffix="d", wide="1") + +%def op_float_to_int(): +% cvtfp_int(fp_suffix="s", i_suffix="l", max_const="$0x7fffffff", result_reg="%eax", wide="0") + +%def op_float_to_long(): +% cvtfp_int(fp_suffix="s", i_suffix="q", max_const="$0x7fffffffffffffff", result_reg="%rax", wide="1") + +%def op_int_to_double(): +% fpcvt(source_suffix="i", dest_suffix="dl", wide="1") + +%def op_int_to_float(): +% fpcvt(source_suffix="i", dest_suffix="sl", wide="0") + +%def op_long_to_double(): +% fpcvt(source_suffix="i", dest_suffix="dq", wide="1") + +%def op_long_to_float(): +% fpcvt(source_suffix="i", dest_suffix="sq", wide="0") + +%def op_mul_double(): +% sseBinop(instr="muls", suff="d") + +%def op_mul_double_2addr(): +% sseBinop2Addr(instr="muls", suff="d") + +%def op_mul_float(): +% sseBinop(instr="muls", suff="s") + +%def op_mul_float_2addr(): +% sseBinop2Addr(instr="muls", suff="s") + +%def op_neg_double(): +% unop(preinstr=" movq $0x8000000000000000, %rsi", instr=" xorq %rsi, %rax", wide="1") + +%def op_neg_float(): +% unop(instr=" xorl $0x80000000, %eax") + +%def op_rem_double(): + /* rem_double vAA, vBB, vCC */ + movzbq 3(rPC), %rcx # ecx <- BB + movzbq 2(rPC), %rax # eax <- CC + fldl VREG_ADDRESS(%rcx) # %st1 <- fp[vBB] + fldl VREG_ADDRESS(%rax) # %st0 <- fp[vCC] +1: + fprem + fstsw %ax + sahf + jp 1b + fstp %st(1) + fstpl VREG_ADDRESS(rINSTq) # fp[vAA] <- %st + CLEAR_WIDE_REF rINSTq + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_rem_double_2addr(): + /* rem_double/2addr vA, vB */ + movzbq rINSTbl, %rcx # ecx <- A+ + sarl $$4, rINST # rINST <- B + fldl VREG_ADDRESS(rINSTq) # vB to fp stack + andb $$0xf, %cl # ecx <- A + fldl VREG_ADDRESS(%rcx) # vA to fp stack +1: + fprem + fstsw %ax + sahf + jp 1b + fstp %st(1) + fstpl VREG_ADDRESS(%rcx) # %st to vA + CLEAR_WIDE_REF %rcx + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_rem_float(): + /* rem_float vAA, vBB, vCC */ + movzbq 3(rPC), %rcx # ecx <- BB + movzbq 2(rPC), %rax # eax <- CC + flds VREG_ADDRESS(%rcx) # vBB to fp stack + flds VREG_ADDRESS(%rax) # vCC to fp stack +1: + fprem + fstsw %ax + sahf + jp 1b + fstp %st(1) + fstps VREG_ADDRESS(rINSTq) # %st to vAA + CLEAR_REF rINSTq + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_rem_float_2addr(): + /* rem_float/2addr vA, vB */ + movzbq rINSTbl, %rcx # ecx <- A+ + sarl $$4, rINST # rINST <- B + flds VREG_ADDRESS(rINSTq) # vB to fp stack + andb $$0xf, %cl # ecx <- A + flds VREG_ADDRESS(%rcx) # vA to fp stack +1: + fprem + fstsw %ax + sahf + jp 1b + fstp %st(1) + fstps VREG_ADDRESS(%rcx) # %st to vA + CLEAR_REF %rcx + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_sub_double(): +% sseBinop(instr="subs", suff="d") + +%def op_sub_double_2addr(): +% sseBinop2Addr(instr="subs", suff="d") + +%def op_sub_float(): +% sseBinop(instr="subs", suff="s") + +%def op_sub_float_2addr(): +% sseBinop2Addr(instr="subs", suff="s") diff --git a/runtime/interpreter/mterp/x86_64/footer.S b/runtime/interpreter/mterp/x86_64/footer.S deleted file mode 100644 index 3cc75321cf4ff1d6f47d588085d6ee4f30c728b7..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/footer.S +++ /dev/null @@ -1,297 +0,0 @@ -/* - * =========================================================================== - * Common subroutines and data - * =========================================================================== - */ - - .text - .align 2 - -/* - * We've detected a condition that will result in an exception, but the exception - * has not yet been thrown. Just bail out to the reference interpreter to deal with it. - * TUNING: for consistency, we may want to just go ahead and handle these here. - */ -common_errDivideByZero: - EXPORT_PC -#if MTERP_LOGGING - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - call SYMBOL(MterpLogDivideByZeroException) -#endif - jmp MterpCommonFallback - -common_errArrayIndex: - EXPORT_PC -#if MTERP_LOGGING - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - call SYMBOL(MterpLogArrayIndexException) -#endif - jmp MterpCommonFallback - -common_errNegativeArraySize: - EXPORT_PC -#if MTERP_LOGGING - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - call SYMBOL(MterpLogNegativeArraySizeException) -#endif - jmp MterpCommonFallback - -common_errNoSuchMethod: - EXPORT_PC -#if MTERP_LOGGING - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - call SYMBOL(MterpLogNoSuchMethodException) -#endif - jmp MterpCommonFallback - -common_errNullObject: - EXPORT_PC -#if MTERP_LOGGING - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - call SYMBOL(MterpLogNullObjectException) -#endif - jmp MterpCommonFallback - -common_exceptionThrown: - EXPORT_PC -#if MTERP_LOGGING - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - call SYMBOL(MterpLogExceptionThrownException) -#endif - jmp MterpCommonFallback - -MterpSuspendFallback: - EXPORT_PC -#if MTERP_LOGGING - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movl THREAD_FLAGS_OFFSET(OUT_ARG0), OUT_32_ARG2 - call SYMBOL(MterpLogSuspendFallback) -#endif - jmp MterpCommonFallback - -/* - * If we're here, something is out of the ordinary. If there is a pending - * exception, handle it. Otherwise, roll back and retry with the reference - * interpreter. - */ -MterpPossibleException: - movq rSELF, %rcx - cmpq $$0, THREAD_EXCEPTION_OFFSET(%rcx) - jz MterpFallback - /* intentional fallthrough - handle pending exception. */ - -/* - * On return from a runtime helper routine, we've found a pending exception. - * Can we handle it here - or need to bail out to caller? - * - */ -MterpException: - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - call SYMBOL(MterpHandleException) - testb %al, %al - jz MterpExceptionReturn - movq OFF_FP_DEX_INSTRUCTIONS(rFP), %rax - mov OFF_FP_DEX_PC(rFP), %ecx - leaq (%rax, %rcx, 2), rPC - movq rPC, OFF_FP_DEX_PC_PTR(rFP) - /* Do we need to switch interpreters? */ - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - /* resume execution at catch block */ - REFRESH_IBASE - FETCH_INST - GOTO_NEXT - /* NOTE: no fallthrough */ - -/* - * Common handling for branches with support for Jit profiling. - * On entry: - * rINST <= signed offset - * rPROFILE <= signed hotness countdown (expanded to 32 bits) - * condition bits <= set to establish sign of offset (use "NoFlags" entry if not) - * - * We have quite a few different cases for branch profiling, OSR detection and - * suspend check support here. - * - * Taken backward branches: - * If profiling active, do hotness countdown and report if we hit zero. - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * Is there a pending suspend request? If so, suspend. - * - * Taken forward branches and not-taken backward branches: - * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. - * - * Our most common case is expected to be a taken backward branch with active jit profiling, - * but no full OSR check and no pending suspend request. - * Next most common case is not-taken branch with no full OSR check. - * - */ -MterpCommonTakenBranch: - jg .L_forward_branch # don't add forward branches to hotness -/* - * We need to subtract 1 from positive values and we should not see 0 here, - * so we may use the result of the comparison with -1. - */ -#if JIT_CHECK_OSR != -1 -# error "JIT_CHECK_OSR must be -1." -#endif - cmpl $$JIT_CHECK_OSR, rPROFILE - je .L_osr_check - decl rPROFILE - je .L_add_batch # counted down to zero - report -.L_resume_backward_branch: - movq rSELF, %rax - testl $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(%rax) - REFRESH_IBASE_REG %rax - leaq (rPC, rINSTq, 2), rPC - FETCH_INST - jnz .L_suspend_request_pending - GOTO_NEXT - -.L_suspend_request_pending: - EXPORT_PC - movq rSELF, OUT_ARG0 - call SYMBOL(MterpSuspendCheck) # (self) - testb %al, %al - jnz MterpFallback - REFRESH_IBASE # might have changed during suspend - GOTO_NEXT - -.L_no_count_backwards: - cmpl $$JIT_CHECK_OSR, rPROFILE # possible OSR re-entry? - jne .L_resume_backward_branch -.L_osr_check: - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rINSTq, OUT_ARG2 - call SYMBOL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) - testb %al, %al - jz .L_resume_backward_branch - jmp MterpOnStackReplacement - -.L_forward_branch: - cmpl $$JIT_CHECK_OSR, rPROFILE # possible OSR re-entry? - je .L_check_osr_forward -.L_resume_forward_branch: - leaq (rPC, rINSTq, 2), rPC - FETCH_INST - GOTO_NEXT - -.L_check_osr_forward: - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rINSTq, OUT_ARG2 - call SYMBOL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) - testb %al, %al - jz .L_resume_forward_branch - jmp MterpOnStackReplacement - -.L_add_batch: - movl rPROFILE, %eax - movq OFF_FP_METHOD(rFP), OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movw %ax, OFF_FP_COUNTDOWN_OFFSET(rFP) - movq rSELF, OUT_ARG2 - call SYMBOL(MterpAddHotnessBatch) # (method, shadow_frame, self) - movswl %ax, rPROFILE - jmp .L_no_count_backwards - -/* - * Entered from the conditional branch handlers when OSR check request active on - * not-taken path. All Dalvik not-taken conditional branch offsets are 2. - */ -.L_check_not_taken_osr: - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movl $$2, OUT_32_ARG2 - call SYMBOL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) - testb %al, %al - jnz MterpOnStackReplacement - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 - -/* - * On-stack replacement has happened, and now we've returned from the compiled method. - */ -MterpOnStackReplacement: -#if MTERP_LOGGING - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movl rINST, OUT_32_ARG2 - call SYMBOL(MterpLogOSR) -#endif - movl $$1, %eax - jmp MterpDone - -/* - * Bail out to reference interpreter. - */ -MterpFallback: - EXPORT_PC -#if MTERP_LOGGING - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - call SYMBOL(MterpLogFallback) -#endif -MterpCommonFallback: - xorl %eax, %eax - jmp MterpDone - -/* - * On entry: - * uint32_t* rFP (should still be live, pointer to base of vregs) - */ -MterpExceptionReturn: - movl $$1, %eax - jmp MterpDone -MterpReturn: - movq OFF_FP_RESULT_REGISTER(rFP), %rdx - movq %rax, (%rdx) - movl $$1, %eax -MterpDone: -/* - * At this point, we expect rPROFILE to be non-zero. If negative, hotness is disabled or we're - * checking for OSR. If greater than zero, we might have unreported hotness to register - * (the difference between the ending rPROFILE and the cached hotness counter). rPROFILE - * should only reach zero immediately after a hotness decrement, and is then reset to either - * a negative special state or the new non-zero countdown value. - */ - testl rPROFILE, rPROFILE - jle MRestoreFrame # if > 0, we may have some counts to report. - - movl %eax, rINST # stash return value - /* Report cached hotness counts */ - movl rPROFILE, %eax - movq OFF_FP_METHOD(rFP), OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movw %ax, OFF_FP_COUNTDOWN_OFFSET(rFP) - movq rSELF, OUT_ARG2 - call SYMBOL(MterpAddHotnessBatch) # (method, shadow_frame, self) - movl rINST, %eax # restore return value - - /* pop up frame */ -MRestoreFrame: - addq $$FRAME_SIZE, %rsp - .cfi_adjust_cfa_offset -FRAME_SIZE - - /* Restore callee save register */ - POP %r15 - POP %r14 - POP %r13 - POP %r12 - POP %rbp - POP %rbx - ret - .cfi_endproc - SIZE(ExecuteMterpImpl,ExecuteMterpImpl) diff --git a/runtime/interpreter/mterp/x86_64/fpcmp.S b/runtime/interpreter/mterp/x86_64/fpcmp.S deleted file mode 100644 index 806bc2b1ef392193748e8caf680b227f45f1dba9..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/fpcmp.S +++ /dev/null @@ -1,35 +0,0 @@ -%default {"suff":"d","nanval":"pos"} -/* - * Compare two floating-point values. Puts 0, 1, or -1 into the - * destination register based on the results of the comparison. - * - * int compare(x, y) { - * if (x == y) { - * return 0; - * } else if (x < y) { - * return -1; - * } else if (x > y) { - * return 1; - * } else { - * return nanval ? 1 : -1; - * } - * } - */ - /* op vAA, vBB, vCC */ - movzbq 3(rPC), %rcx # ecx<- CC - movzbq 2(rPC), %rax # eax<- BB - movs${suff} VREG_ADDRESS(%rax), %xmm0 - xor %eax, %eax - ucomis${suff} VREG_ADDRESS(%rcx), %xmm0 - jp .L${opcode}_nan_is_${nanval} - je .L${opcode}_finish - jb .L${opcode}_less -.L${opcode}_nan_is_pos: - addb $$1, %al - jmp .L${opcode}_finish -.L${opcode}_nan_is_neg: -.L${opcode}_less: - movl $$-1, %eax -.L${opcode}_finish: - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/fpcvt.S b/runtime/interpreter/mterp/x86_64/fpcvt.S deleted file mode 100644 index 657869e0bdd60e5df4ce942f57df29d03f26d308..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/fpcvt.S +++ /dev/null @@ -1,17 +0,0 @@ -%default {"source_suffix":"","dest_suffix":"","wide":""} -/* - * Generic 32-bit FP conversion operation. - */ - /* unop vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $$4, rINST # rINST <- B - andb $$0xf, %cl # ecx <- A - cvts${source_suffix}2s${dest_suffix} VREG_ADDRESS(rINSTq), %xmm0 - .if $wide - movsd %xmm0, VREG_ADDRESS(%rcx) - CLEAR_WIDE_REF %rcx - .else - movss %xmm0, VREG_ADDRESS(%rcx) - CLEAR_REF %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86_64/header.S b/runtime/interpreter/mterp/x86_64/header.S deleted file mode 100644 index 0332ce272c8fa6ed2803163fc673b37a776ca7ba..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/header.S +++ /dev/null @@ -1,302 +0,0 @@ -/* - * Copyright (C) 2016 The Android Open Source Project - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - Art assembly interpreter notes: - - First validate assembly code by implementing ExecuteXXXImpl() style body (doesn't - handle invoke, allows higher-level code to create frame & shadow frame. - - Once that's working, support direct entry code & eliminate shadow frame (and - excess locals allocation. - - Some (hopefully) temporary ugliness. We'll treat rFP as pointing to the - base of the vreg array within the shadow frame. Access the other fields, - dex_pc_, method_ and number_of_vregs_ via negative offsets. For now, we'll continue - the shadow frame mechanism of double-storing object references - via rFP & - number_of_vregs_. - - */ - -/* -x86_64 ABI general notes: - -Caller save set: - rax, rdx, rcx, rsi, rdi, r8-r11, st(0)-st(7) -Callee save set: - rbx, rbp, r12-r15 -Return regs: - 32-bit in eax - 64-bit in rax - fp on xmm0 - -First 8 fp parameters came in xmm0-xmm7. -First 6 non-fp parameters came in rdi, rsi, rdx, rcx, r8, r9. -Other parameters passed on stack, pushed right-to-left. On entry to target, first -param is at 8(%esp). Traditional entry code is: - -Stack must be 16-byte aligned to support SSE in native code. - -If we're not doing variable stack allocation (alloca), the frame pointer can be -eliminated and all arg references adjusted to be esp relative. -*/ - -/* -Mterp and x86_64 notes: - -Some key interpreter variables will be assigned to registers. - - nick reg purpose - rPROFILE rbp countdown register for jit profiling - rPC r12 interpreted program counter, used for fetching instructions - rFP r13 interpreted frame pointer, used for accessing locals and args - rINSTw bx first 16-bit code of current instruction - rINSTbl bl opcode portion of instruction word - rINSTbh bh high byte of inst word, usually contains src/tgt reg names - rIBASE r14 base of instruction handler table - rREFS r15 base of object references in shadow frame. - -Notes: - o High order 16 bits of ebx must be zero on entry to handler - o rPC, rFP, rINSTw/rINSTbl valid on handler entry and exit - o eax and ecx are scratch, rINSTw/ebx sometimes scratch - -Macros are provided for common operations. Each macro MUST emit only -one instruction to make instruction-counting easier. They MUST NOT alter -unspecified registers or condition codes. -*/ - -/* - * This is a #include, not a %include, because we want the C pre-processor - * to expand the macros into assembler assignment statements. - */ -#include "asm_support.h" -#include "interpreter/cfi_asm_support.h" - -/* - * Handle mac compiler specific - */ -#if defined(__APPLE__) - #define MACRO_LITERAL(value) $$(value) - #define FUNCTION_TYPE(name) - #define OBJECT_TYPE(name) - #define SIZE(start,end) - // Mac OS' symbols have an _ prefix. - #define SYMBOL(name) _ ## name - #define ASM_HIDDEN .private_extern -#else - #define MACRO_LITERAL(value) $$value - #define FUNCTION_TYPE(name) .type name, @function - #define OBJECT_TYPE(name) .type name, @object - #define SIZE(start,end) .size start, .-end - #define SYMBOL(name) name - #define ASM_HIDDEN .hidden -#endif - -.macro PUSH _reg - pushq \_reg - .cfi_adjust_cfa_offset 8 - .cfi_rel_offset \_reg, 0 -.endm - -.macro POP _reg - popq \_reg - .cfi_adjust_cfa_offset -8 - .cfi_restore \_reg -.endm - -/* - * Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs. So, - * to access other shadow frame fields, we need to use a backwards offset. Define those here. - */ -#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) -#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) -#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) -#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) -#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) -#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) -#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) -#define OFF_FP_DEX_INSTRUCTIONS OFF_FP(SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET) -#define OFF_FP_COUNTDOWN_OFFSET OFF_FP(SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET) -#define OFF_FP_SHADOWFRAME (-SHADOWFRAME_VREGS_OFFSET) - -/* Frame size must be 16-byte aligned. - * Remember about 8 bytes for return address + 6 * 8 for spills. - */ -#define FRAME_SIZE 8 - -/* Frame diagram while executing ExecuteMterpImpl, high to low addresses */ -#define IN_ARG3 %rcx -#define IN_ARG2 %rdx -#define IN_ARG1 %rsi -#define IN_ARG0 %rdi -/* Spill offsets relative to %esp */ -#define SELF_SPILL (FRAME_SIZE - 8) -/* Out Args */ -#define OUT_ARG3 %rcx -#define OUT_ARG2 %rdx -#define OUT_ARG1 %rsi -#define OUT_ARG0 %rdi -#define OUT_32_ARG3 %ecx -#define OUT_32_ARG2 %edx -#define OUT_32_ARG1 %esi -#define OUT_32_ARG0 %edi -#define OUT_FP_ARG1 %xmm1 -#define OUT_FP_ARG0 %xmm0 - -/* During bringup, we'll use the shadow frame model instead of rFP */ -/* single-purpose registers, given names for clarity */ -#define rSELF SELF_SPILL(%rsp) -#define rPC %r12 -#define CFI_DEX 12 // DWARF register number of the register holding dex-pc (rPC). -#define CFI_TMP 5 // DWARF register number of the first argument register (rdi). -#define rFP %r13 -#define rINST %ebx -#define rINSTq %rbx -#define rINSTw %bx -#define rINSTbh %bh -#define rINSTbl %bl -#define rIBASE %r14 -#define rREFS %r15 -#define rPROFILE %ebp - -#define MTERP_LOGGING 0 - -/* - * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must - * be done *before* something throws. - * - * It's okay to do this more than once. - * - * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped - * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction - * offset into the code_items_[] array. For effiency, we will "export" the - * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC - * to convert to a dex pc when needed. - */ -.macro EXPORT_PC - movq rPC, OFF_FP_DEX_PC_PTR(rFP) -.endm - -/* - * Refresh handler table. - * IBase handles uses the caller save register so we must restore it after each call. - * Also it is used as a result of some 64-bit operations (like imul) and we should - * restore it in such cases also. - * - */ -.macro REFRESH_IBASE_REG self_reg - movq THREAD_CURRENT_IBASE_OFFSET(\self_reg), rIBASE -.endm -.macro REFRESH_IBASE - movq rSELF, rIBASE - REFRESH_IBASE_REG rIBASE -.endm - -/* - * Refresh rINST. - * At enter to handler rINST does not contain the opcode number. - * However some utilities require the full value, so this macro - * restores the opcode number. - */ -.macro REFRESH_INST _opnum - movb rINSTbl, rINSTbh - movb $$\_opnum, rINSTbl -.endm - -/* - * Fetch the next instruction from rPC into rINSTw. Does not advance rPC. - */ -.macro FETCH_INST - movzwq (rPC), rINSTq -.endm - -/* - * Remove opcode from rINST, compute the address of handler and jump to it. - */ -.macro GOTO_NEXT - movzx rINSTbl,%eax - movzbl rINSTbh,rINST - shll MACRO_LITERAL(${handler_size_bits}), %eax - addq rIBASE, %rax - jmp *%rax -.endm - -/* - * Advance rPC by instruction count. - */ -.macro ADVANCE_PC _count - leaq 2*\_count(rPC), rPC -.endm - -/* - * Advance rPC by instruction count, fetch instruction and jump to handler. - */ -.macro ADVANCE_PC_FETCH_AND_GOTO_NEXT _count - ADVANCE_PC \_count - FETCH_INST - GOTO_NEXT -.endm - -/* - * Get/set the 32-bit value from a Dalvik register. - */ -#define VREG_ADDRESS(_vreg) (rFP,_vreg,4) -#define VREG_REF_ADDRESS(_vreg) (rREFS,_vreg,4) - -.macro GET_VREG _reg _vreg - movl (rFP,\_vreg,4), \_reg -.endm - -/* Read wide value. */ -.macro GET_WIDE_VREG _reg _vreg - movq (rFP,\_vreg,4), \_reg -.endm - -.macro SET_VREG _reg _vreg - movl \_reg, (rFP,\_vreg,4) - movl MACRO_LITERAL(0), (rREFS,\_vreg,4) -.endm - -/* Write wide value. reg is clobbered. */ -.macro SET_WIDE_VREG _reg _vreg - movq \_reg, (rFP,\_vreg,4) - xorq \_reg, \_reg - movq \_reg, (rREFS,\_vreg,4) -.endm - -.macro SET_VREG_OBJECT _reg _vreg - movl \_reg, (rFP,\_vreg,4) - movl \_reg, (rREFS,\_vreg,4) -.endm - -.macro GET_VREG_HIGH _reg _vreg - movl 4(rFP,\_vreg,4), \_reg -.endm - -.macro SET_VREG_HIGH _reg _vreg - movl \_reg, 4(rFP,\_vreg,4) - movl MACRO_LITERAL(0), 4(rREFS,\_vreg,4) -.endm - -.macro CLEAR_REF _vreg - movl MACRO_LITERAL(0), (rREFS,\_vreg,4) -.endm - -.macro CLEAR_WIDE_REF _vreg - movl MACRO_LITERAL(0), (rREFS,\_vreg,4) - movl MACRO_LITERAL(0), 4(rREFS,\_vreg,4) -.endm diff --git a/runtime/interpreter/mterp/x86_64/instruction_end.S b/runtime/interpreter/mterp/x86_64/instruction_end.S deleted file mode 100644 index 94587f83b7ece94acc81c162b24242ca73dbf6a8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/instruction_end.S +++ /dev/null @@ -1,5 +0,0 @@ - - OBJECT_TYPE(artMterpAsmInstructionEnd) - ASM_HIDDEN SYMBOL(artMterpAsmInstructionEnd) - .global SYMBOL(artMterpAsmInstructionEnd) -SYMBOL(artMterpAsmInstructionEnd): diff --git a/runtime/interpreter/mterp/x86_64/instruction_end_alt.S b/runtime/interpreter/mterp/x86_64/instruction_end_alt.S deleted file mode 100644 index 7757bce9a7eba09c81d13bb34be3356a1c0813d8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/instruction_end_alt.S +++ /dev/null @@ -1,5 +0,0 @@ - - OBJECT_TYPE(artMterpAsmAltInstructionEnd) - ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionEnd) - .global SYMBOL(artMterpAsmAltInstructionEnd) -SYMBOL(artMterpAsmAltInstructionEnd): diff --git a/runtime/interpreter/mterp/x86_64/instruction_end_sister.S b/runtime/interpreter/mterp/x86_64/instruction_end_sister.S deleted file mode 100644 index 8eb79accdf82bd257721ba37a04ed9319d23c36b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/instruction_end_sister.S +++ /dev/null @@ -1,5 +0,0 @@ - - OBJECT_TYPE(artMterpAsmSisterEnd) - ASM_HIDDEN SYMBOL(artMterpAsmSisterEnd) - .global SYMBOL(artMterpAsmSisterEnd) -SYMBOL(artMterpAsmSisterEnd): diff --git a/runtime/interpreter/mterp/x86_64/instruction_start.S b/runtime/interpreter/mterp/x86_64/instruction_start.S deleted file mode 100644 index 5d29a8199373e2abfc49b32baf183107a96b3c1d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/instruction_start.S +++ /dev/null @@ -1,6 +0,0 @@ - - OBJECT_TYPE(artMterpAsmInstructionStart) - ASM_HIDDEN SYMBOL(artMterpAsmInstructionStart) - .global SYMBOL(artMterpAsmInstructionStart) -SYMBOL(artMterpAsmInstructionStart) = .L_op_nop - .text diff --git a/runtime/interpreter/mterp/x86_64/instruction_start_alt.S b/runtime/interpreter/mterp/x86_64/instruction_start_alt.S deleted file mode 100644 index 8dcf5bfaf95be22f84f4e8670a19a56d7b9a2d46..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/instruction_start_alt.S +++ /dev/null @@ -1,6 +0,0 @@ - - OBJECT_TYPE(artMterpAsmAltInstructionStart) - ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionStart) - .global SYMBOL(artMterpAsmAltInstructionStart) - .text -SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop diff --git a/runtime/interpreter/mterp/x86_64/instruction_start_sister.S b/runtime/interpreter/mterp/x86_64/instruction_start_sister.S deleted file mode 100644 index 796e98b09a4ca70adac9aa64992c0928fce7229e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/instruction_start_sister.S +++ /dev/null @@ -1,7 +0,0 @@ - - OBJECT_TYPE(artMterpAsmSisterStart) - ASM_HIDDEN SYMBOL(artMterpAsmSisterStart) - .global SYMBOL(artMterpAsmSisterStart) - .text - .balign 4 -SYMBOL(artMterpAsmSisterStart): diff --git a/runtime/interpreter/mterp/x86_64/invoke.S b/runtime/interpreter/mterp/x86_64/invoke.S index f7e6155c161db943fe415f12ab937aa05a88a7ac..63c233c4eb975efc800b0323db5f5e819557e7c1 100644 --- a/runtime/interpreter/mterp/x86_64/invoke.S +++ b/runtime/interpreter/mterp/x86_64/invoke.S @@ -1,4 +1,4 @@ -%default { "helper":"UndefinedInvokeHandler" } +%def invoke(helper="UndefinedInvokeHandler"): /* * Generic invoke handler wrapper. */ @@ -20,3 +20,96 @@ jnz MterpFallback FETCH_INST GOTO_NEXT + +%def invoke_polymorphic(helper="UndefinedInvokeHandler"): + /* + * invoke-polymorphic handler wrapper. + */ + /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ + /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ + .extern $helper + EXPORT_PC + movq rSELF, OUT_ARG0 + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 + movq rPC, OUT_ARG2 + REFRESH_INST ${opnum} + movl rINST, OUT_32_ARG3 + call SYMBOL($helper) + testb %al, %al + jz MterpException + ADVANCE_PC 4 + call SYMBOL(MterpShouldSwitchInterpreters) + testb %al, %al + jnz MterpFallback + FETCH_INST + GOTO_NEXT + +%def op_invoke_custom(): +% invoke(helper="MterpInvokeCustom") + +%def op_invoke_custom_range(): +% invoke(helper="MterpInvokeCustomRange") + +%def op_invoke_direct(): +% invoke(helper="MterpInvokeDirect") + +%def op_invoke_direct_range(): +% invoke(helper="MterpInvokeDirectRange") + +%def op_invoke_interface(): +% invoke(helper="MterpInvokeInterface") +/* + * Handle an interface method call. + * + * for: invoke-interface, invoke-interface/range + */ + /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ + /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ + +%def op_invoke_interface_range(): +% invoke(helper="MterpInvokeInterfaceRange") + +%def op_invoke_polymorphic(): +% invoke_polymorphic(helper="MterpInvokePolymorphic") + +%def op_invoke_polymorphic_range(): +% invoke_polymorphic(helper="MterpInvokePolymorphicRange") + +%def op_invoke_static(): +% invoke(helper="MterpInvokeStatic") + + +%def op_invoke_static_range(): +% invoke(helper="MterpInvokeStaticRange") + +%def op_invoke_super(): +% invoke(helper="MterpInvokeSuper") +/* + * Handle a "super" method call. + * + * for: invoke-super, invoke-super/range + */ + /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ + /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ + +%def op_invoke_super_range(): +% invoke(helper="MterpInvokeSuperRange") + +%def op_invoke_virtual(): +% invoke(helper="MterpInvokeVirtual") +/* + * Handle a virtual method call. + * + * for: invoke-virtual, invoke-virtual/range + */ + /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ + /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ + +%def op_invoke_virtual_quick(): +% invoke(helper="MterpInvokeVirtualQuick") + +%def op_invoke_virtual_range(): +% invoke(helper="MterpInvokeVirtualRange") + +%def op_invoke_virtual_range_quick(): +% invoke(helper="MterpInvokeVirtualQuickRange") diff --git a/runtime/interpreter/mterp/x86_64/invoke_polymorphic.S b/runtime/interpreter/mterp/x86_64/invoke_polymorphic.S deleted file mode 100644 index 5157860b376b8890f314f336341c157efcb69bad..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/invoke_polymorphic.S +++ /dev/null @@ -1,22 +0,0 @@ -%default { "helper":"UndefinedInvokeHandler" } - /* - * invoke-polymorphic handler wrapper. - */ - /* op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB, proto@HHHH */ - .extern $helper - EXPORT_PC - movq rSELF, OUT_ARG0 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 - movq rPC, OUT_ARG2 - REFRESH_INST ${opnum} - movl rINST, OUT_32_ARG3 - call SYMBOL($helper) - testb %al, %al - jz MterpException - ADVANCE_PC 4 - call SYMBOL(MterpShouldSwitchInterpreters) - testb %al, %al - jnz MterpFallback - FETCH_INST - GOTO_NEXT diff --git a/runtime/interpreter/mterp/x86_64/main.S b/runtime/interpreter/mterp/x86_64/main.S new file mode 100644 index 0000000000000000000000000000000000000000..83dc27f319c7f457f1bf92ecbd8a6e2d383fb59b --- /dev/null +++ b/runtime/interpreter/mterp/x86_64/main.S @@ -0,0 +1,740 @@ +%def header(): +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + Art assembly interpreter notes: + + First validate assembly code by implementing ExecuteXXXImpl() style body (doesn't + handle invoke, allows higher-level code to create frame & shadow frame. + + Once that's working, support direct entry code & eliminate shadow frame (and + excess locals allocation. + + Some (hopefully) temporary ugliness. We'll treat rFP as pointing to the + base of the vreg array within the shadow frame. Access the other fields, + dex_pc_, method_ and number_of_vregs_ via negative offsets. For now, we'll continue + the shadow frame mechanism of double-storing object references - via rFP & + number_of_vregs_. + + */ + +/* +x86_64 ABI general notes: + +Caller save set: + rax, rdx, rcx, rsi, rdi, r8-r11, st(0)-st(7) +Callee save set: + rbx, rbp, r12-r15 +Return regs: + 32-bit in eax + 64-bit in rax + fp on xmm0 + +First 8 fp parameters came in xmm0-xmm7. +First 6 non-fp parameters came in rdi, rsi, rdx, rcx, r8, r9. +Other parameters passed on stack, pushed right-to-left. On entry to target, first +param is at 8(%esp). Traditional entry code is: + +Stack must be 16-byte aligned to support SSE in native code. + +If we're not doing variable stack allocation (alloca), the frame pointer can be +eliminated and all arg references adjusted to be esp relative. +*/ + +/* +Mterp and x86_64 notes: + +Some key interpreter variables will be assigned to registers. + + nick reg purpose + rPROFILE rbp countdown register for jit profiling + rPC r12 interpreted program counter, used for fetching instructions + rFP r13 interpreted frame pointer, used for accessing locals and args + rINSTw bx first 16-bit code of current instruction + rINSTbl bl opcode portion of instruction word + rINSTbh bh high byte of inst word, usually contains src/tgt reg names + rIBASE r14 base of instruction handler table + rREFS r15 base of object references in shadow frame. + +Notes: + o High order 16 bits of ebx must be zero on entry to handler + o rPC, rFP, rINSTw/rINSTbl valid on handler entry and exit + o eax and ecx are scratch, rINSTw/ebx sometimes scratch + +Macros are provided for common operations. Each macro MUST emit only +one instruction to make instruction-counting easier. They MUST NOT alter +unspecified registers or condition codes. +*/ + +/* + * This is a #include, not a %include, because we want the C pre-processor + * to expand the macros into assembler assignment statements. + */ +#include "asm_support.h" +#include "interpreter/cfi_asm_support.h" + +/* + * Handle mac compiler specific + */ +#if defined(__APPLE__) + #define MACRO_LITERAL(value) $$(value) + #define FUNCTION_TYPE(name) + #define OBJECT_TYPE(name) + #define SIZE(start,end) + // Mac OS' symbols have an _ prefix. + #define SYMBOL(name) _ ## name + #define ASM_HIDDEN .private_extern +#else + #define MACRO_LITERAL(value) $$value + #define FUNCTION_TYPE(name) .type name, @function + #define OBJECT_TYPE(name) .type name, @object + #define SIZE(start,end) .size start, .-end + #define SYMBOL(name) name + #define ASM_HIDDEN .hidden +#endif + +.macro PUSH _reg + pushq \_reg + .cfi_adjust_cfa_offset 8 + .cfi_rel_offset \_reg, 0 +.endm + +.macro POP _reg + popq \_reg + .cfi_adjust_cfa_offset -8 + .cfi_restore \_reg +.endm + +/* + * Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs. So, + * to access other shadow frame fields, we need to use a backwards offset. Define those here. + */ +#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) +#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) +#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) +#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) +#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) +#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) +#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) +#define OFF_FP_DEX_INSTRUCTIONS OFF_FP(SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET) +#define OFF_FP_COUNTDOWN_OFFSET OFF_FP(SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET) +#define OFF_FP_SHADOWFRAME (-SHADOWFRAME_VREGS_OFFSET) + +/* Frame size must be 16-byte aligned. + * Remember about 8 bytes for return address + 6 * 8 for spills. + */ +#define FRAME_SIZE 8 + +/* Frame diagram while executing ExecuteMterpImpl, high to low addresses */ +#define IN_ARG3 %rcx +#define IN_ARG2 %rdx +#define IN_ARG1 %rsi +#define IN_ARG0 %rdi +/* Spill offsets relative to %esp */ +#define SELF_SPILL (FRAME_SIZE - 8) +/* Out Args */ +#define OUT_ARG3 %rcx +#define OUT_ARG2 %rdx +#define OUT_ARG1 %rsi +#define OUT_ARG0 %rdi +#define OUT_32_ARG3 %ecx +#define OUT_32_ARG2 %edx +#define OUT_32_ARG1 %esi +#define OUT_32_ARG0 %edi +#define OUT_FP_ARG1 %xmm1 +#define OUT_FP_ARG0 %xmm0 + +/* During bringup, we'll use the shadow frame model instead of rFP */ +/* single-purpose registers, given names for clarity */ +#define rSELF SELF_SPILL(%rsp) +#define rPC %r12 +#define CFI_DEX 12 // DWARF register number of the register holding dex-pc (rPC). +#define CFI_TMP 5 // DWARF register number of the first argument register (rdi). +#define rFP %r13 +#define rINST %ebx +#define rINSTq %rbx +#define rINSTw %bx +#define rINSTbh %bh +#define rINSTbl %bl +#define rIBASE %r14 +#define rREFS %r15 +#define rPROFILE %ebp + +#define MTERP_LOGGING 0 + +/* + * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must + * be done *before* something throws. + * + * It's okay to do this more than once. + * + * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped + * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction + * offset into the code_items_[] array. For effiency, we will "export" the + * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC + * to convert to a dex pc when needed. + */ +.macro EXPORT_PC + movq rPC, OFF_FP_DEX_PC_PTR(rFP) +.endm + +/* + * Refresh handler table. + * IBase handles uses the caller save register so we must restore it after each call. + * Also it is used as a result of some 64-bit operations (like imul) and we should + * restore it in such cases also. + * + */ +.macro REFRESH_IBASE_REG self_reg + movq THREAD_CURRENT_IBASE_OFFSET(\self_reg), rIBASE +.endm +.macro REFRESH_IBASE + movq rSELF, rIBASE + REFRESH_IBASE_REG rIBASE +.endm + +/* + * Refresh rINST. + * At enter to handler rINST does not contain the opcode number. + * However some utilities require the full value, so this macro + * restores the opcode number. + */ +.macro REFRESH_INST _opnum + movb rINSTbl, rINSTbh + movb $$\_opnum, rINSTbl +.endm + +/* + * Fetch the next instruction from rPC into rINSTw. Does not advance rPC. + */ +.macro FETCH_INST + movzwq (rPC), rINSTq +.endm + +/* + * Remove opcode from rINST, compute the address of handler and jump to it. + */ +.macro GOTO_NEXT + movzx rINSTbl,%eax + movzbl rINSTbh,rINST + shll MACRO_LITERAL(${handler_size_bits}), %eax + addq rIBASE, %rax + jmp *%rax +.endm + +/* + * Advance rPC by instruction count. + */ +.macro ADVANCE_PC _count + leaq 2*\_count(rPC), rPC +.endm + +/* + * Advance rPC by instruction count, fetch instruction and jump to handler. + */ +.macro ADVANCE_PC_FETCH_AND_GOTO_NEXT _count + ADVANCE_PC \_count + FETCH_INST + GOTO_NEXT +.endm + +/* + * Get/set the 32-bit value from a Dalvik register. + */ +#define VREG_ADDRESS(_vreg) (rFP,_vreg,4) +#define VREG_REF_ADDRESS(_vreg) (rREFS,_vreg,4) + +.macro GET_VREG _reg _vreg + movl (rFP,\_vreg,4), \_reg +.endm + +/* Read wide value. */ +.macro GET_WIDE_VREG _reg _vreg + movq (rFP,\_vreg,4), \_reg +.endm + +.macro SET_VREG _reg _vreg + movl \_reg, (rFP,\_vreg,4) + movl MACRO_LITERAL(0), (rREFS,\_vreg,4) +.endm + +/* Write wide value. reg is clobbered. */ +.macro SET_WIDE_VREG _reg _vreg + movq \_reg, (rFP,\_vreg,4) + xorq \_reg, \_reg + movq \_reg, (rREFS,\_vreg,4) +.endm + +.macro SET_VREG_OBJECT _reg _vreg + movl \_reg, (rFP,\_vreg,4) + movl \_reg, (rREFS,\_vreg,4) +.endm + +.macro GET_VREG_HIGH _reg _vreg + movl 4(rFP,\_vreg,4), \_reg +.endm + +.macro SET_VREG_HIGH _reg _vreg + movl \_reg, 4(rFP,\_vreg,4) + movl MACRO_LITERAL(0), 4(rREFS,\_vreg,4) +.endm + +.macro CLEAR_REF _vreg + movl MACRO_LITERAL(0), (rREFS,\_vreg,4) +.endm + +.macro CLEAR_WIDE_REF _vreg + movl MACRO_LITERAL(0), (rREFS,\_vreg,4) + movl MACRO_LITERAL(0), 4(rREFS,\_vreg,4) +.endm + +%def entry(): +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* + * Interpreter entry point. + */ + + .text + ASM_HIDDEN SYMBOL(ExecuteMterpImpl) + .global SYMBOL(ExecuteMterpImpl) + FUNCTION_TYPE(ExecuteMterpImpl) + +/* + * On entry: + * 0 Thread* self + * 1 insns_ + * 2 ShadowFrame + * 3 JValue* result_register + * + */ + +SYMBOL(ExecuteMterpImpl): + .cfi_startproc + .cfi_def_cfa rsp, 8 + + /* Spill callee save regs */ + PUSH %rbx + PUSH %rbp + PUSH %r12 + PUSH %r13 + PUSH %r14 + PUSH %r15 + + /* Allocate frame */ + subq $$FRAME_SIZE, %rsp + .cfi_adjust_cfa_offset FRAME_SIZE + + /* Remember the return register */ + movq IN_ARG3, SHADOWFRAME_RESULT_REGISTER_OFFSET(IN_ARG2) + + /* Remember the code_item */ + movq IN_ARG1, SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET(IN_ARG2) + + /* set up "named" registers */ + movl SHADOWFRAME_NUMBER_OF_VREGS_OFFSET(IN_ARG2), %eax + leaq SHADOWFRAME_VREGS_OFFSET(IN_ARG2), rFP + leaq (rFP, %rax, 4), rREFS + movl SHADOWFRAME_DEX_PC_OFFSET(IN_ARG2), %eax + leaq (IN_ARG1, %rax, 2), rPC + CFI_DEFINE_DEX_PC_WITH_OFFSET(CFI_TMP, CFI_DEX, 0) + EXPORT_PC + + /* Starting ibase */ + movq IN_ARG0, rSELF + REFRESH_IBASE_REG IN_ARG0 + + /* Set up for backwards branches & osr profiling */ + movq IN_ARG0, OUT_ARG2 /* Set up OUT_ARG2 before clobbering IN_ARG0 */ + movq OFF_FP_METHOD(rFP), OUT_ARG0 + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 + call SYMBOL(MterpSetUpHotnessCountdown) + movswl %ax, rPROFILE + + /* start executing the instruction at rPC */ + FETCH_INST + GOTO_NEXT + /* NOTE: no fallthrough */ + +%def alt_stub(): +/* + * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle + * any interesting requests and then jump to the real instruction + * handler. Unlike the Arm handler, we can't do this as a tail call + * because rIBASE is caller save and we need to reload it. + * + * Note that unlike in the Arm implementation, we should never arrive + * here with a zero breakFlag because we always refresh rIBASE on + * return. + */ + .extern MterpCheckBefore + REFRESH_IBASE + movq rSELF, OUT_ARG0 + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 + movq rPC, OUT_ARG2 + call SYMBOL(MterpCheckBefore) # (self, shadow_frame, dex_pc_ptr) + jmp .L_op_nop+(${opnum}*${handler_size_bytes}) + +%def fallback(): +/* Transfer stub to alternate interpreter */ + jmp MterpFallback + + +%def helpers(): +% pass + +%def footer(): +/* + * =========================================================================== + * Common subroutines and data + * =========================================================================== + */ + + .text + .align 2 + +/* + * We've detected a condition that will result in an exception, but the exception + * has not yet been thrown. Just bail out to the reference interpreter to deal with it. + * TUNING: for consistency, we may want to just go ahead and handle these here. + */ +common_errDivideByZero: + EXPORT_PC +#if MTERP_LOGGING + movq rSELF, OUT_ARG0 + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 + call SYMBOL(MterpLogDivideByZeroException) +#endif + jmp MterpCommonFallback + +common_errArrayIndex: + EXPORT_PC +#if MTERP_LOGGING + movq rSELF, OUT_ARG0 + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 + call SYMBOL(MterpLogArrayIndexException) +#endif + jmp MterpCommonFallback + +common_errNegativeArraySize: + EXPORT_PC +#if MTERP_LOGGING + movq rSELF, OUT_ARG0 + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 + call SYMBOL(MterpLogNegativeArraySizeException) +#endif + jmp MterpCommonFallback + +common_errNoSuchMethod: + EXPORT_PC +#if MTERP_LOGGING + movq rSELF, OUT_ARG0 + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 + call SYMBOL(MterpLogNoSuchMethodException) +#endif + jmp MterpCommonFallback + +common_errNullObject: + EXPORT_PC +#if MTERP_LOGGING + movq rSELF, OUT_ARG0 + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 + call SYMBOL(MterpLogNullObjectException) +#endif + jmp MterpCommonFallback + +common_exceptionThrown: + EXPORT_PC +#if MTERP_LOGGING + movq rSELF, OUT_ARG0 + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 + call SYMBOL(MterpLogExceptionThrownException) +#endif + jmp MterpCommonFallback + +MterpSuspendFallback: + EXPORT_PC +#if MTERP_LOGGING + movq rSELF, OUT_ARG0 + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 + movl THREAD_FLAGS_OFFSET(OUT_ARG0), OUT_32_ARG2 + call SYMBOL(MterpLogSuspendFallback) +#endif + jmp MterpCommonFallback + +/* + * If we're here, something is out of the ordinary. If there is a pending + * exception, handle it. Otherwise, roll back and retry with the reference + * interpreter. + */ +MterpPossibleException: + movq rSELF, %rcx + cmpq $$0, THREAD_EXCEPTION_OFFSET(%rcx) + jz MterpFallback + /* intentional fallthrough - handle pending exception. */ + +/* + * On return from a runtime helper routine, we've found a pending exception. + * Can we handle it here - or need to bail out to caller? + * + */ +MterpException: + movq rSELF, OUT_ARG0 + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 + call SYMBOL(MterpHandleException) + testb %al, %al + jz MterpExceptionReturn + movq OFF_FP_DEX_INSTRUCTIONS(rFP), %rax + mov OFF_FP_DEX_PC(rFP), %ecx + leaq (%rax, %rcx, 2), rPC + movq rPC, OFF_FP_DEX_PC_PTR(rFP) + /* Do we need to switch interpreters? */ + call SYMBOL(MterpShouldSwitchInterpreters) + testb %al, %al + jnz MterpFallback + /* resume execution at catch block */ + REFRESH_IBASE + FETCH_INST + GOTO_NEXT + /* NOTE: no fallthrough */ + +/* + * Common handling for branches with support for Jit profiling. + * On entry: + * rINST <= signed offset + * rPROFILE <= signed hotness countdown (expanded to 32 bits) + * condition bits <= set to establish sign of offset (use "NoFlags" entry if not) + * + * We have quite a few different cases for branch profiling, OSR detection and + * suspend check support here. + * + * Taken backward branches: + * If profiling active, do hotness countdown and report if we hit zero. + * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. + * Is there a pending suspend request? If so, suspend. + * + * Taken forward branches and not-taken backward branches: + * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. + * + * Our most common case is expected to be a taken backward branch with active jit profiling, + * but no full OSR check and no pending suspend request. + * Next most common case is not-taken branch with no full OSR check. + * + */ +MterpCommonTakenBranch: + jg .L_forward_branch # don't add forward branches to hotness +/* + * We need to subtract 1 from positive values and we should not see 0 here, + * so we may use the result of the comparison with -1. + */ +#if JIT_CHECK_OSR != -1 +# error "JIT_CHECK_OSR must be -1." +#endif + cmpl $$JIT_CHECK_OSR, rPROFILE + je .L_osr_check + decl rPROFILE + je .L_add_batch # counted down to zero - report +.L_resume_backward_branch: + movq rSELF, %rax + testl $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(%rax) + REFRESH_IBASE_REG %rax + leaq (rPC, rINSTq, 2), rPC + FETCH_INST + jnz .L_suspend_request_pending + GOTO_NEXT + +.L_suspend_request_pending: + EXPORT_PC + movq rSELF, OUT_ARG0 + call SYMBOL(MterpSuspendCheck) # (self) + testb %al, %al + jnz MterpFallback + REFRESH_IBASE # might have changed during suspend + GOTO_NEXT + +.L_no_count_backwards: + cmpl $$JIT_CHECK_OSR, rPROFILE # possible OSR re-entry? + jne .L_resume_backward_branch +.L_osr_check: + EXPORT_PC + movq rSELF, OUT_ARG0 + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 + movq rINSTq, OUT_ARG2 + call SYMBOL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) + testb %al, %al + jz .L_resume_backward_branch + jmp MterpOnStackReplacement + +.L_forward_branch: + cmpl $$JIT_CHECK_OSR, rPROFILE # possible OSR re-entry? + je .L_check_osr_forward +.L_resume_forward_branch: + leaq (rPC, rINSTq, 2), rPC + FETCH_INST + GOTO_NEXT + +.L_check_osr_forward: + EXPORT_PC + movq rSELF, OUT_ARG0 + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 + movq rINSTq, OUT_ARG2 + call SYMBOL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) + testb %al, %al + jz .L_resume_forward_branch + jmp MterpOnStackReplacement + +.L_add_batch: + movl rPROFILE, %eax + movq OFF_FP_METHOD(rFP), OUT_ARG0 + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 + movw %ax, OFF_FP_COUNTDOWN_OFFSET(rFP) + movq rSELF, OUT_ARG2 + call SYMBOL(MterpAddHotnessBatch) # (method, shadow_frame, self) + movswl %ax, rPROFILE + jmp .L_no_count_backwards + +/* + * Entered from the conditional branch handlers when OSR check request active on + * not-taken path. All Dalvik not-taken conditional branch offsets are 2. + */ +.L_check_not_taken_osr: + EXPORT_PC + movq rSELF, OUT_ARG0 + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 + movl $$2, OUT_32_ARG2 + call SYMBOL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) + testb %al, %al + jnz MterpOnStackReplacement + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +/* + * On-stack replacement has happened, and now we've returned from the compiled method. + */ +MterpOnStackReplacement: +#if MTERP_LOGGING + movq rSELF, OUT_ARG0 + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 + movl rINST, OUT_32_ARG2 + call SYMBOL(MterpLogOSR) +#endif + movl $$1, %eax + jmp MterpDone + +/* + * Bail out to reference interpreter. + */ +MterpFallback: + EXPORT_PC +#if MTERP_LOGGING + movq rSELF, OUT_ARG0 + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 + call SYMBOL(MterpLogFallback) +#endif +MterpCommonFallback: + xorl %eax, %eax + jmp MterpDone + +/* + * On entry: + * uint32_t* rFP (should still be live, pointer to base of vregs) + */ +MterpExceptionReturn: + movl $$1, %eax + jmp MterpDone +MterpReturn: + movq OFF_FP_RESULT_REGISTER(rFP), %rdx + movq %rax, (%rdx) + movl $$1, %eax +MterpDone: +/* + * At this point, we expect rPROFILE to be non-zero. If negative, hotness is disabled or we're + * checking for OSR. If greater than zero, we might have unreported hotness to register + * (the difference between the ending rPROFILE and the cached hotness counter). rPROFILE + * should only reach zero immediately after a hotness decrement, and is then reset to either + * a negative special state or the new non-zero countdown value. + */ + testl rPROFILE, rPROFILE + jle MRestoreFrame # if > 0, we may have some counts to report. + + movl %eax, rINST # stash return value + /* Report cached hotness counts */ + movl rPROFILE, %eax + movq OFF_FP_METHOD(rFP), OUT_ARG0 + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG1 + movw %ax, OFF_FP_COUNTDOWN_OFFSET(rFP) + movq rSELF, OUT_ARG2 + call SYMBOL(MterpAddHotnessBatch) # (method, shadow_frame, self) + movl rINST, %eax # restore return value + + /* pop up frame */ +MRestoreFrame: + addq $$FRAME_SIZE, %rsp + .cfi_adjust_cfa_offset -FRAME_SIZE + + /* Restore callee save register */ + POP %r15 + POP %r14 + POP %r13 + POP %r12 + POP %rbp + POP %rbx + ret + .cfi_endproc + SIZE(ExecuteMterpImpl,ExecuteMterpImpl) + +%def instruction_end(): + + OBJECT_TYPE(artMterpAsmInstructionEnd) + ASM_HIDDEN SYMBOL(artMterpAsmInstructionEnd) + .global SYMBOL(artMterpAsmInstructionEnd) +SYMBOL(artMterpAsmInstructionEnd): + +%def instruction_end_alt(): + + OBJECT_TYPE(artMterpAsmAltInstructionEnd) + ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionEnd) + .global SYMBOL(artMterpAsmAltInstructionEnd) +SYMBOL(artMterpAsmAltInstructionEnd): + +%def instruction_start(): + + OBJECT_TYPE(artMterpAsmInstructionStart) + ASM_HIDDEN SYMBOL(artMterpAsmInstructionStart) + .global SYMBOL(artMterpAsmInstructionStart) +SYMBOL(artMterpAsmInstructionStart) = .L_op_nop + .text + +%def instruction_start_alt(): + + OBJECT_TYPE(artMterpAsmAltInstructionStart) + ASM_HIDDEN SYMBOL(artMterpAsmAltInstructionStart) + .global SYMBOL(artMterpAsmAltInstructionStart) + .text +SYMBOL(artMterpAsmAltInstructionStart) = .L_ALT_op_nop diff --git a/runtime/interpreter/mterp/x86_64/object.S b/runtime/interpreter/mterp/x86_64/object.S new file mode 100644 index 0000000000000000000000000000000000000000..fa85f694044749c1ec675f794bdbbf9339bfed52 --- /dev/null +++ b/runtime/interpreter/mterp/x86_64/object.S @@ -0,0 +1,254 @@ +%def field(helper=""): + /* + * General field read / write (iget-* iput-* sget-* sput-*). + */ + .extern $helper + REFRESH_INST ${opnum} # fix rINST to include opcode + movq rPC, OUT_ARG0 # arg0: Instruction* inst + movl rINST, OUT_32_ARG1 # arg1: uint16_t inst_data + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 # arg2: ShadowFrame* sf + movq rSELF, OUT_ARG3 # arg3: Thread* self + call SYMBOL($helper) + testb %al, %al + jz MterpPossibleException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_check_cast(): +/* + * Check to see if a cast from one class to another is allowed. + */ + /* check-cast vAA, class@BBBB */ + EXPORT_PC + movzwq 2(rPC), OUT_ARG0 # OUT_ARG0 <- BBBB + leaq VREG_ADDRESS(rINSTq), OUT_ARG1 + movq OFF_FP_METHOD(rFP), OUT_ARG2 + movq rSELF, OUT_ARG3 + call SYMBOL(MterpCheckCast) # (index, &obj, method, self) + testb %al, %al + jnz MterpPossibleException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_iget(is_object="0", helper="MterpIGetU32"): +% field(helper=helper) + +%def op_iget_boolean(): +% op_iget(helper="MterpIGetU8") + +%def op_iget_boolean_quick(): +% op_iget_quick(load="movsbl") + +%def op_iget_byte(): +% op_iget(helper="MterpIGetI8") + +%def op_iget_byte_quick(): +% op_iget_quick(load="movsbl") + +%def op_iget_char(): +% op_iget(helper="MterpIGetU16") + +%def op_iget_char_quick(): +% op_iget_quick(load="movzwl") + +%def op_iget_object(): +% op_iget(is_object="1", helper="MterpIGetObj") + +%def op_iget_object_quick(): + /* For: iget-object-quick */ + /* op vA, vB, offset@CCCC */ + .extern artIGetObjectFromMterp + movzbq rINSTbl, %rcx # rcx <- BA + sarl $$4, %ecx # ecx <- B + GET_VREG OUT_32_ARG0, %rcx # vB (object we're operating on) + movzwl 2(rPC), OUT_32_ARG1 # eax <- field byte offset + EXPORT_PC + callq SYMBOL(artIGetObjectFromMterp) # (obj, offset) + movq rSELF, %rcx + cmpq $$0, THREAD_EXCEPTION_OFFSET(%rcx) + jnz MterpException # bail out + andb $$0xf, rINSTbl # rINST <- A + SET_VREG_OBJECT %eax, rINSTq # fp[A] <- value + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_iget_quick(load="movl", wide="0"): + /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick, iget-wide-quick */ + /* op vA, vB, offset@CCCC */ + movl rINST, %ecx # rcx <- BA + sarl $$4, %ecx # ecx <- B + GET_VREG %ecx, %rcx # vB (object we're operating on) + movzwq 2(rPC), %rax # eax <- field byte offset + testl %ecx, %ecx # is object null? + je common_errNullObject + andb $$0xf,rINSTbl # rINST <- A + .if $wide + movq (%rcx,%rax,1), %rax + SET_WIDE_VREG %rax, rINSTq # fp[A] <- value + .else + ${load} (%rcx,%rax,1), %eax + SET_VREG %eax, rINSTq # fp[A] <- value + .endif + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_iget_short(): +% op_iget(helper="MterpIGetI16") + +%def op_iget_short_quick(): +% op_iget_quick(load="movswl") + +%def op_iget_wide(): +% op_iget(helper="MterpIGetU64") + +%def op_iget_wide_quick(): +% op_iget_quick(load="movswl", wide="1") + +%def op_instance_of(): +/* + * Check to see if an object reference is an instance of a class. + * + * Most common situation is a non-null object, being compared against + * an already-resolved class. + */ + /* instance-of vA, vB, class@CCCC */ + EXPORT_PC + movzwl 2(rPC), OUT_32_ARG0 # OUT_32_ARG0 <- CCCC + movl rINST, %eax # eax <- BA + sarl $$4, %eax # eax <- B + leaq VREG_ADDRESS(%rax), OUT_ARG1 # Get object address + movq OFF_FP_METHOD(rFP), OUT_ARG2 + movq rSELF, OUT_ARG3 + call SYMBOL(MterpInstanceOf) # (index, &obj, method, self) + movsbl %al, %eax + movq rSELF, %rcx + cmpq $$0, THREAD_EXCEPTION_OFFSET(%rcx) + jnz MterpException + andb $$0xf, rINSTbl # rINSTbl <- A + SET_VREG %eax, rINSTq + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_iput(is_object="0", helper="MterpIPutU32"): +% field(helper=helper) + +%def op_iput_boolean(): +% op_iput(helper="MterpIPutU8") + +%def op_iput_boolean_quick(): +% op_iput_quick(reg="rINSTbl", store="movb") + +%def op_iput_byte(): +% op_iput(helper="MterpIPutI8") + +%def op_iput_byte_quick(): +% op_iput_quick(reg="rINSTbl", store="movb") + +%def op_iput_char(): +% op_iput(helper="MterpIPutU16") + +%def op_iput_char_quick(): +% op_iput_quick(reg="rINSTw", store="movw") + +%def op_iput_object(): +% op_iput(is_object="1", helper="MterpIPutObj") + +%def op_iput_object_quick(): + EXPORT_PC + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG0 + movq rPC, OUT_ARG1 + REFRESH_INST ${opnum} + movl rINST, OUT_32_ARG2 + call SYMBOL(MterpIputObjectQuick) + testb %al, %al + jz MterpException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_iput_quick(reg="rINST", store="movl"): + /* For: iput-quick, iput-object-quick */ + /* op vA, vB, offset@CCCC */ + movzbq rINSTbl, %rcx # rcx <- BA + sarl $$4, %ecx # ecx <- B + GET_VREG %ecx, %rcx # vB (object we're operating on) + testl %ecx, %ecx # is object null? + je common_errNullObject + andb $$0xf, rINSTbl # rINST <- A + GET_VREG rINST, rINSTq # rINST <- v[A] + movzwq 2(rPC), %rax # rax <- field byte offset + ${store} ${reg}, (%rcx,%rax,1) + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_iput_short(): +% op_iput(helper="MterpIPutI16") + +%def op_iput_short_quick(): +% op_iput_quick(reg="rINSTw", store="movw") + +%def op_iput_wide(): +% op_iput(helper="MterpIPutU64") + +%def op_iput_wide_quick(): + /* iput-wide-quick vA, vB, offset@CCCC */ + movzbq rINSTbl, %rcx # rcx<- BA + sarl $$4, %ecx # ecx<- B + GET_VREG %ecx, %rcx # vB (object we're operating on) + testl %ecx, %ecx # is object null? + je common_errNullObject + movzwq 2(rPC), %rax # rax<- field byte offset + leaq (%rcx,%rax,1), %rcx # ecx<- Address of 64-bit target + andb $$0xf, rINSTbl # rINST<- A + GET_WIDE_VREG %rax, rINSTq # rax<- fp[A]/fp[A+1] + movq %rax, (%rcx) # obj.field<- r0/r1 + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_new_instance(): +/* + * Create a new instance of a class. + */ + /* new-instance vAA, class@BBBB */ + EXPORT_PC + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG0 + movq rSELF, OUT_ARG1 + REFRESH_INST ${opnum} + movq rINSTq, OUT_ARG2 + call SYMBOL(MterpNewInstance) + testb %al, %al # 0 means an exception is thrown + jz MterpPossibleException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_sget(is_object="0", helper="MterpSGetU32"): +% field(helper=helper) + +%def op_sget_boolean(): +% op_sget(helper="MterpSGetU8") + +%def op_sget_byte(): +% op_sget(helper="MterpSGetI8") + +%def op_sget_char(): +% op_sget(helper="MterpSGetU16") + +%def op_sget_object(): +% op_sget(is_object="1", helper="MterpSGetObj") + +%def op_sget_short(): +% op_sget(helper="MterpSGetI16") + +%def op_sget_wide(): +% op_sget(helper="MterpSGetU64") + +%def op_sput(is_object="0", helper="MterpSPutU32"): +% field(helper=helper) + +%def op_sput_boolean(): +% op_sput(helper="MterpSPutU8") + +%def op_sput_byte(): +% op_sput(helper="MterpSPutI8") + +%def op_sput_char(): +% op_sput(helper="MterpSPutU16") + +%def op_sput_object(): +% op_sput(is_object="1", helper="MterpSPutObj") + +%def op_sput_short(): +% op_sput(helper="MterpSPutI16") + +%def op_sput_wide(): +% op_sput(helper="MterpSPutU64") diff --git a/runtime/interpreter/mterp/x86_64/op_add_double.S b/runtime/interpreter/mterp/x86_64/op_add_double.S deleted file mode 100644 index cb462cb816224e5f19a6471fd222ab7a866f690e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_add_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/sseBinop.S" {"instr":"adds","suff":"d"} diff --git a/runtime/interpreter/mterp/x86_64/op_add_double_2addr.S b/runtime/interpreter/mterp/x86_64/op_add_double_2addr.S deleted file mode 100644 index 063bde3fb3b5f88f06e35e36745e6046e7cbdb15..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_add_double_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/sseBinop2Addr.S" {"instr":"adds","suff":"d"} diff --git a/runtime/interpreter/mterp/x86_64/op_add_float.S b/runtime/interpreter/mterp/x86_64/op_add_float.S deleted file mode 100644 index 7753bf88702c879997680f3be5f3abc60929ca06..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_add_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/sseBinop.S" {"instr":"adds","suff":"s"} diff --git a/runtime/interpreter/mterp/x86_64/op_add_float_2addr.S b/runtime/interpreter/mterp/x86_64/op_add_float_2addr.S deleted file mode 100644 index 6c8005b1822c8b406efc37202c38397d412ceae2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_add_float_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/sseBinop2Addr.S" {"instr":"adds","suff":"s"} diff --git a/runtime/interpreter/mterp/x86_64/op_add_int.S b/runtime/interpreter/mterp/x86_64/op_add_int.S deleted file mode 100644 index e316be7b9dcb32f7d7a26cfdeaad3b13fa5c8515..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_add_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/binop.S" {"instr":"addl (rFP,%rcx,4), %eax"} diff --git a/runtime/interpreter/mterp/x86_64/op_add_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_add_int_2addr.S deleted file mode 100644 index 2ff82935ae87efc82f476bbbd167f740ec6850fd..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_add_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/binop2addr.S" {"instr":"addl %eax, (rFP,%rcx,4)"} diff --git a/runtime/interpreter/mterp/x86_64/op_add_int_lit16.S b/runtime/interpreter/mterp/x86_64/op_add_int_lit16.S deleted file mode 100644 index bfeb7caabcb03a0f6387f93985f8512448046a6e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_add_int_lit16.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/binopLit16.S" {"instr":"addl %ecx, %eax"} diff --git a/runtime/interpreter/mterp/x86_64/op_add_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_add_int_lit8.S deleted file mode 100644 index 8954844eae0f0f2e449f07de13184447f59b0968..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_add_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/binopLit8.S" {"instr":"addl %ecx, %eax"} diff --git a/runtime/interpreter/mterp/x86_64/op_add_long.S b/runtime/interpreter/mterp/x86_64/op_add_long.S deleted file mode 100644 index 89131ffe0e8e3f73a9314d6ea9b3988515e7d49e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_add_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/binopWide.S" {"instr":"addq (rFP,%rcx,4), %rax"} diff --git a/runtime/interpreter/mterp/x86_64/op_add_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_add_long_2addr.S deleted file mode 100644 index fed98bc3e688f5bcc7048adf63a61e83b7b20fe3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_add_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/binopWide2addr.S" {"instr":"addq %rax, (rFP,%rcx,4)"} diff --git a/runtime/interpreter/mterp/x86_64/op_aget.S b/runtime/interpreter/mterp/x86_64/op_aget.S deleted file mode 100644 index 58d49481cfdeaa164d5dbd19268a7a66926f78f5..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_aget.S +++ /dev/null @@ -1,24 +0,0 @@ -%default { "load":"movl", "shift":"4", "data_offset":"MIRROR_INT_ARRAY_DATA_OFFSET", "wide":"0" } -/* - * Array get, 32 bits or less. vAA <- vBB[vCC]. - * - * for: aget, aget-boolean, aget-byte, aget-char, aget-short, aget-wide - * - */ - /* op vAA, vBB, vCC */ - movzbq 2(rPC), %rax # eax <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_VREG %eax, %rax # eax <- vBB (array object) - GET_VREG %ecx, %rcx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - .if $wide - movq $data_offset(%rax,%rcx,8), %rax - SET_WIDE_VREG %rax, rINSTq - .else - $load $data_offset(%rax,%rcx,$shift), %eax - SET_VREG %eax, rINSTq - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_aget_boolean.S b/runtime/interpreter/mterp/x86_64/op_aget_boolean.S deleted file mode 100644 index cf7bdb582b21c73612d343cbd06d6d3853904278..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_aget_boolean.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_aget.S" { "load":"movzbl", "shift":"1", "data_offset":"MIRROR_BOOLEAN_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/x86_64/op_aget_byte.S b/runtime/interpreter/mterp/x86_64/op_aget_byte.S deleted file mode 100644 index 1cbb56902498628c451de56f4312c593f37c34f4..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_aget_byte.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_aget.S" { "load":"movsbl", "shift":"1", "data_offset":"MIRROR_BYTE_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/x86_64/op_aget_char.S b/runtime/interpreter/mterp/x86_64/op_aget_char.S deleted file mode 100644 index 45c90851fd3308adcfe7a4cf6f48374df60ac31a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_aget_char.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_aget.S" { "load":"movzwl", "shift":"2", "data_offset":"MIRROR_CHAR_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/x86_64/op_aget_object.S b/runtime/interpreter/mterp/x86_64/op_aget_object.S deleted file mode 100644 index 5f77a9774835c4e0155f3f448f0811ca4f9704fc..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_aget_object.S +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Array object get. vAA <- vBB[vCC]. - * - * for: aget-object - */ - /* op vAA, vBB, vCC */ - movzbq 2(rPC), %rax # rax <- BB - movzbq 3(rPC), %rcx # rcx <- CC - GET_VREG OUT_32_ARG0, %rax # eax <- vBB (array object) - GET_VREG OUT_32_ARG1, %rcx # ecx <- vCC (requested index) - EXPORT_PC - call SYMBOL(artAGetObjectFromMterp) # (array, index) - movq rSELF, %rcx - cmpq $$0, THREAD_EXCEPTION_OFFSET(%rcx) - jnz MterpException - SET_VREG_OBJECT %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_aget_short.S b/runtime/interpreter/mterp/x86_64/op_aget_short.S deleted file mode 100644 index 82c4a1ddf34498fbb9b748831a2a7ad80e7483e0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_aget_short.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_aget.S" { "load":"movswl", "shift":"2", "data_offset":"MIRROR_SHORT_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/x86_64/op_aget_wide.S b/runtime/interpreter/mterp/x86_64/op_aget_wide.S deleted file mode 100644 index 4f2771b9c403c24d158712f6e8de4b640694c670..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_aget_wide.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_aget.S" { "load":"movq", "shift":"8", "data_offset":"MIRROR_WIDE_ARRAY_DATA_OFFSET", "wide":"1" } diff --git a/runtime/interpreter/mterp/x86_64/op_and_int.S b/runtime/interpreter/mterp/x86_64/op_and_int.S deleted file mode 100644 index 446988993df6db0f10eb63a130ebb08767e7d497..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_and_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/binop.S" {"instr":"andl (rFP,%rcx,4), %eax"} diff --git a/runtime/interpreter/mterp/x86_64/op_and_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_and_int_2addr.S deleted file mode 100644 index 16315bba0353820ae51fcd87e75303ddcd18e36a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_and_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/binop2addr.S" {"instr":"andl %eax, (rFP,%rcx,4)"} diff --git a/runtime/interpreter/mterp/x86_64/op_and_int_lit16.S b/runtime/interpreter/mterp/x86_64/op_and_int_lit16.S deleted file mode 100644 index 63e851b4497da49bad125313747773e4b52027fa..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_and_int_lit16.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/binopLit16.S" {"instr":"andl %ecx, %eax"} diff --git a/runtime/interpreter/mterp/x86_64/op_and_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_and_int_lit8.S deleted file mode 100644 index da7a20fdff904fb3f472455b660dbb324c6d63ba..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_and_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/binopLit8.S" {"instr":"andl %ecx, %eax"} diff --git a/runtime/interpreter/mterp/x86_64/op_and_long.S b/runtime/interpreter/mterp/x86_64/op_and_long.S deleted file mode 100644 index ce1dd264dd55d151b709a6132ac04590a10595c7..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_and_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/binopWide.S" {"instr":"andq (rFP,%rcx,4), %rax"} diff --git a/runtime/interpreter/mterp/x86_64/op_and_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_and_long_2addr.S deleted file mode 100644 index d17ab8d58bd19921acb98ac127cbd570abcb5bad..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_and_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/binopWide2addr.S" {"instr":"andq %rax, (rFP,%rcx,4)"} diff --git a/runtime/interpreter/mterp/x86_64/op_aput.S b/runtime/interpreter/mterp/x86_64/op_aput.S deleted file mode 100644 index 11500ad201dd5166046bd7165174901b73d66085..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_aput.S +++ /dev/null @@ -1,23 +0,0 @@ -%default { "reg":"rINST", "store":"movl", "shift":"4", "data_offset":"MIRROR_INT_ARRAY_DATA_OFFSET", "wide":"0" } -/* - * Array put, 32 bits or less. vBB[vCC] <- vAA. - * - * for: aput, aput-boolean, aput-byte, aput-char, aput-short, aput-wide - * - */ - /* op vAA, vBB, vCC */ - movzbq 2(rPC), %rax # rax <- BB - movzbq 3(rPC), %rcx # rcx <- CC - GET_VREG %eax, %rax # eax <- vBB (array object) - GET_VREG %ecx, %rcx # ecx <- vCC (requested index) - testl %eax, %eax # null array object? - je common_errNullObject # bail if so - cmpl MIRROR_ARRAY_LENGTH_OFFSET(%eax), %ecx - jae common_errArrayIndex # index >= length, bail. - .if $wide - GET_WIDE_VREG rINSTq, rINSTq - .else - GET_VREG rINST, rINSTq - .endif - $store $reg, $data_offset(%rax,%rcx,$shift) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_aput_boolean.S b/runtime/interpreter/mterp/x86_64/op_aput_boolean.S deleted file mode 100644 index 7d77a865288fe99f9788fb83d45f147a4ba81896..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_aput_boolean.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_aput.S" { "reg":"rINSTbl", "store":"movb", "shift":"1", "data_offset":"MIRROR_BOOLEAN_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/x86_64/op_aput_byte.S b/runtime/interpreter/mterp/x86_64/op_aput_byte.S deleted file mode 100644 index 7a1723e0fe24a6879ea6a71690eaef0c9ac0d91f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_aput_byte.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_aput.S" { "reg":"rINSTbl", "store":"movb", "shift":"1", "data_offset":"MIRROR_BYTE_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/x86_64/op_aput_char.S b/runtime/interpreter/mterp/x86_64/op_aput_char.S deleted file mode 100644 index f8f50a3b2e61837196298c2496d3d0305d1335f1..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_aput_char.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_aput.S" { "reg":"rINSTw", "store":"movw", "shift":"2", "data_offset":"MIRROR_CHAR_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/x86_64/op_aput_object.S b/runtime/interpreter/mterp/x86_64/op_aput_object.S deleted file mode 100644 index b1bae0f45758b5740a12035fe6b260707b73a478..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_aput_object.S +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Store an object into an array. vBB[vCC] <- vAA. - */ - /* op vAA, vBB, vCC */ - EXPORT_PC - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG0 - movq rPC, OUT_ARG1 - REFRESH_INST ${opnum} - movq rINSTq, OUT_ARG2 - call SYMBOL(MterpAputObject) # (array, index) - testb %al, %al - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_aput_short.S b/runtime/interpreter/mterp/x86_64/op_aput_short.S deleted file mode 100644 index 481fd6847b7dfe0027f075eb81d2bbb49a6fcc28..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_aput_short.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_aput.S" { "reg":"rINSTw", "store":"movw", "shift":"2", "data_offset":"MIRROR_SHORT_ARRAY_DATA_OFFSET" } diff --git a/runtime/interpreter/mterp/x86_64/op_aput_wide.S b/runtime/interpreter/mterp/x86_64/op_aput_wide.S deleted file mode 100644 index 5bbd39b0b6426c15466d1c18f40cd7baf85d9078..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_aput_wide.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_aput.S" { "reg":"rINSTq", "store":"movq", "shift":"8", "data_offset":"MIRROR_WIDE_ARRAY_DATA_OFFSET", "wide":"1" } diff --git a/runtime/interpreter/mterp/x86_64/op_array_length.S b/runtime/interpreter/mterp/x86_64/op_array_length.S deleted file mode 100644 index e80d665160ec20cc0b5c88da3f97eb308ecbb1d9..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_array_length.S +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Return the length of an array. - */ - movl rINST, %eax # eax <- BA - sarl $$4, rINST # rINST <- B - GET_VREG %ecx, rINSTq # ecx <- vB (object ref) - testl %ecx, %ecx # is null? - je common_errNullObject - andb $$0xf, %al # eax <- A - movl MIRROR_ARRAY_LENGTH_OFFSET(%rcx), rINST - SET_VREG rINST, %rax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86_64/op_check_cast.S b/runtime/interpreter/mterp/x86_64/op_check_cast.S deleted file mode 100644 index f8fa7b2036e3527b410ef2792b79d7834d4a9041..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_check_cast.S +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Check to see if a cast from one class to another is allowed. - */ - /* check-cast vAA, class@BBBB */ - EXPORT_PC - movzwq 2(rPC), OUT_ARG0 # OUT_ARG0 <- BBBB - leaq VREG_ADDRESS(rINSTq), OUT_ARG1 - movq OFF_FP_METHOD(rFP), OUT_ARG2 - movq rSELF, OUT_ARG3 - call SYMBOL(MterpCheckCast) # (index, &obj, method, self) - testb %al, %al - jnz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_cmp_long.S b/runtime/interpreter/mterp/x86_64/op_cmp_long.S deleted file mode 100644 index 23ca3e5e6d5f09d30ac6c635fc91b021fee10f00..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_cmp_long.S +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Compare two 64-bit values. Puts 0, 1, or -1 into the destination - * register based on the results of the comparison. - */ - /* cmp-long vAA, vBB, vCC */ - movzbq 2(rPC), %rdx # edx <- BB - movzbq 3(rPC), %rcx # ecx <- CC - GET_WIDE_VREG %rdx, %rdx # rdx <- v[BB] - xorl %eax, %eax - xorl %edi, %edi - addb $$1, %al - movl $$-1, %esi - cmpq VREG_ADDRESS(%rcx), %rdx - cmovl %esi, %edi - cmovg %eax, %edi - SET_VREG %edi, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_cmpg_double.S b/runtime/interpreter/mterp/x86_64/op_cmpg_double.S deleted file mode 100644 index 7c0aa1bdbab7f247e4cdce74788677d924514801..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_cmpg_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/fpcmp.S" {"suff":"d","nanval":"pos"} diff --git a/runtime/interpreter/mterp/x86_64/op_cmpg_float.S b/runtime/interpreter/mterp/x86_64/op_cmpg_float.S deleted file mode 100644 index 14e8472672a8f8f5f61ce70347b47f0d2642b6c6..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_cmpg_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/fpcmp.S" {"suff":"s","nanval":"pos"} diff --git a/runtime/interpreter/mterp/x86_64/op_cmpl_double.S b/runtime/interpreter/mterp/x86_64/op_cmpl_double.S deleted file mode 100644 index 1d4c4243ae16cc9489152a487f7b5349ba2a735c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_cmpl_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/fpcmp.S" {"suff":"d","nanval":"neg"} diff --git a/runtime/interpreter/mterp/x86_64/op_cmpl_float.S b/runtime/interpreter/mterp/x86_64/op_cmpl_float.S deleted file mode 100644 index 97a12a6a7dd5cc80772f5487c0f4e35ee3711a93..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_cmpl_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/fpcmp.S" {"suff":"s","nanval":"neg"} diff --git a/runtime/interpreter/mterp/x86_64/op_const.S b/runtime/interpreter/mterp/x86_64/op_const.S deleted file mode 100644 index 3cfafdb13bbd44445ffde9e31038aa99db292c47..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_const.S +++ /dev/null @@ -1,4 +0,0 @@ - /* const vAA, #+BBBBbbbb */ - movl 2(rPC), %eax # grab all 32 bits at once - SET_VREG %eax, rINSTq # vAA<- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 diff --git a/runtime/interpreter/mterp/x86_64/op_const_16.S b/runtime/interpreter/mterp/x86_64/op_const_16.S deleted file mode 100644 index 1a139c683e2ff2d03bb90dde630797e608fb31ed..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_const_16.S +++ /dev/null @@ -1,4 +0,0 @@ - /* const/16 vAA, #+BBBB */ - movswl 2(rPC), %ecx # ecx <- ssssBBBB - SET_VREG %ecx, rINSTq # vAA <- ssssBBBB - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_const_4.S b/runtime/interpreter/mterp/x86_64/op_const_4.S deleted file mode 100644 index 23c4816f8288071cbec7f3f55e60664d015a28c0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_const_4.S +++ /dev/null @@ -1,7 +0,0 @@ - /* const/4 vA, #+B */ - movsbl rINSTbl, %eax # eax <-ssssssBx - movl $$0xf, rINST - andl %eax, rINST # rINST <- A - sarl $$4, %eax - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86_64/op_const_class.S b/runtime/interpreter/mterp/x86_64/op_const_class.S deleted file mode 100644 index 0c402e1489e9e1eb985add188985c9350991bbdd..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_const_class.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/const.S" { "helper":"MterpConstClass" } diff --git a/runtime/interpreter/mterp/x86_64/op_const_high16.S b/runtime/interpreter/mterp/x86_64/op_const_high16.S deleted file mode 100644 index 64e633c7a0d3799206aaca32868f3038c9c8296c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_const_high16.S +++ /dev/null @@ -1,5 +0,0 @@ - /* const/high16 vAA, #+BBBB0000 */ - movzwl 2(rPC), %eax # eax <- 0000BBBB - sall $$16, %eax # eax <- BBBB0000 - SET_VREG %eax, rINSTq # vAA <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_const_method_handle.S b/runtime/interpreter/mterp/x86_64/op_const_method_handle.S deleted file mode 100644 index 2b8b0a258a1440d8613ba119a74c91b76bae0fe8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_const_method_handle.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/const.S" { "helper":"MterpConstMethodHandle" } diff --git a/runtime/interpreter/mterp/x86_64/op_const_method_type.S b/runtime/interpreter/mterp/x86_64/op_const_method_type.S deleted file mode 100644 index 33ce952031eb96e7dea978a21923e7cd353319e7..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_const_method_type.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/const.S" { "helper":"MterpConstMethodType" } diff --git a/runtime/interpreter/mterp/x86_64/op_const_string.S b/runtime/interpreter/mterp/x86_64/op_const_string.S deleted file mode 100644 index 5a29bd3dde28e5ec45de65c45425be5eec092b4c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_const_string.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/const.S" { "helper":"MterpConstString" } diff --git a/runtime/interpreter/mterp/x86_64/op_const_string_jumbo.S b/runtime/interpreter/mterp/x86_64/op_const_string_jumbo.S deleted file mode 100644 index ae03d20f4f17cba3de06bfeda0cee2f8935975de..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_const_string_jumbo.S +++ /dev/null @@ -1,10 +0,0 @@ - /* const/string vAA, String@BBBBBBBB */ - EXPORT_PC - movl 2(rPC), OUT_32_ARG0 # OUT_32_ARG0 <- BBBB - movq rINSTq, OUT_ARG1 - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 - movq rSELF, OUT_ARG3 - call SYMBOL(MterpConstString) # (index, tgt_reg, shadow_frame, self) - testb %al, %al - jnz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 diff --git a/runtime/interpreter/mterp/x86_64/op_const_wide.S b/runtime/interpreter/mterp/x86_64/op_const_wide.S deleted file mode 100644 index 56151771752cd13efdef2090825c3d6e8c9e7308..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_const_wide.S +++ /dev/null @@ -1,4 +0,0 @@ - /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ - movq 2(rPC), %rax # rax <- HHHHhhhhBBBBbbbb - SET_WIDE_VREG %rax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 5 diff --git a/runtime/interpreter/mterp/x86_64/op_const_wide_16.S b/runtime/interpreter/mterp/x86_64/op_const_wide_16.S deleted file mode 100644 index 593b62466f677a55f65a62138a103deb1019db6d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_const_wide_16.S +++ /dev/null @@ -1,4 +0,0 @@ - /* const-wide/16 vAA, #+BBBB */ - movswq 2(rPC), %rax # rax <- ssssBBBB - SET_WIDE_VREG %rax, rINSTq # store - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_const_wide_32.S b/runtime/interpreter/mterp/x86_64/op_const_wide_32.S deleted file mode 100644 index 5ef363612973230c8d5477968a2e643002bc1a77..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_const_wide_32.S +++ /dev/null @@ -1,4 +0,0 @@ - /* const-wide/32 vAA, #+BBBBbbbb */ - movslq 2(rPC), %rax # eax <- ssssssssBBBBbbbb - SET_WIDE_VREG %rax, rINSTq # store - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 diff --git a/runtime/interpreter/mterp/x86_64/op_const_wide_high16.S b/runtime/interpreter/mterp/x86_64/op_const_wide_high16.S deleted file mode 100644 index b86b4e582bb7733c659fd98368fdf946970adabd..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_const_wide_high16.S +++ /dev/null @@ -1,5 +0,0 @@ - /* const-wide/high16 vAA, #+BBBB000000000000 */ - movzwq 2(rPC), %rax # eax <- 0000BBBB - salq $$48, %rax # eax <- BBBB0000 - SET_WIDE_VREG %rax, rINSTq # v[AA+0] <- eax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_div_double.S b/runtime/interpreter/mterp/x86_64/op_div_double.S deleted file mode 100644 index 45c700c0667791a5736cec47546439b9d8a9ce6c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_div_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/sseBinop.S" {"instr":"divs","suff":"d"} diff --git a/runtime/interpreter/mterp/x86_64/op_div_double_2addr.S b/runtime/interpreter/mterp/x86_64/op_div_double_2addr.S deleted file mode 100644 index 83f270e245b2ddc3317db25d2247cdac080ed456..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_div_double_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/sseBinop2Addr.S" {"instr":"divs","suff":"d"} diff --git a/runtime/interpreter/mterp/x86_64/op_div_float.S b/runtime/interpreter/mterp/x86_64/op_div_float.S deleted file mode 100644 index aa90b24698859e915198657a39f506481a2d8e49..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_div_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/sseBinop.S" {"instr":"divs","suff":"s"} diff --git a/runtime/interpreter/mterp/x86_64/op_div_float_2addr.S b/runtime/interpreter/mterp/x86_64/op_div_float_2addr.S deleted file mode 100644 index f0f8f1a6c8636de59341f5293c2d1ba5bf279c88..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_div_float_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/sseBinop2Addr.S" {"instr":"divs","suff":"s"} diff --git a/runtime/interpreter/mterp/x86_64/op_div_int.S b/runtime/interpreter/mterp/x86_64/op_div_int.S deleted file mode 100644 index bba5a176a0f9cb039904ad5313747f38854f00eb..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_div_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/bindiv.S" {"result":"%eax","second":"%ecx","wide":"0","suffix":"l"} diff --git a/runtime/interpreter/mterp/x86_64/op_div_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_div_int_2addr.S deleted file mode 100644 index fa4255ddfa8c13a39bb81b95006ea431db20490b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_div_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/bindiv2addr.S" {"result":"%eax","second":"%ecx","wide":"0","suffix":"l"} diff --git a/runtime/interpreter/mterp/x86_64/op_div_int_lit16.S b/runtime/interpreter/mterp/x86_64/op_div_int_lit16.S deleted file mode 100644 index 3fa1e09fd696ee2bb7214edb012b1bc4534aca68..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_div_int_lit16.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/bindivLit16.S" {"result":"%eax"} diff --git a/runtime/interpreter/mterp/x86_64/op_div_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_div_int_lit8.S deleted file mode 100644 index 859883e5c74e7133cf58e68a87f73a6b0d09b4ae..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_div_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/bindivLit8.S" {"result":"%eax"} diff --git a/runtime/interpreter/mterp/x86_64/op_div_long.S b/runtime/interpreter/mterp/x86_64/op_div_long.S deleted file mode 100644 index a061a88b135a0b06654041eb64ea18d86c451f71..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_div_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/bindiv.S" {"result":"%rax","second":"%rcx","wide":"1","suffix":"q","ext":"cqo"} diff --git a/runtime/interpreter/mterp/x86_64/op_div_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_div_long_2addr.S deleted file mode 100644 index 8886e6824878f445251a054a72ac6735f8a96d5b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_div_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/bindiv2addr.S" {"result":"%rax","second":"%rcx","wide":"1","suffix":"q","ext":"cqo"} diff --git a/runtime/interpreter/mterp/x86_64/op_double_to_float.S b/runtime/interpreter/mterp/x86_64/op_double_to_float.S deleted file mode 100644 index cea1482038a021322d3b74ff281049b46aaab5b8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_double_to_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/fpcvt.S" {"source_suffix":"d","dest_suffix":"s","wide":"0"} diff --git a/runtime/interpreter/mterp/x86_64/op_double_to_int.S b/runtime/interpreter/mterp/x86_64/op_double_to_int.S deleted file mode 100644 index a9965edcc3fe49784f26675fdba6a3fa7676a005..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_double_to_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/cvtfp_int.S" {"fp_suffix":"d","i_suffix":"l","max_const":"$0x7fffffff","result_reg":"%eax","wide":"0"} diff --git a/runtime/interpreter/mterp/x86_64/op_double_to_long.S b/runtime/interpreter/mterp/x86_64/op_double_to_long.S deleted file mode 100644 index 179e6a16053779fcbaf69a7e93b53d5b3ed62a10..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_double_to_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/cvtfp_int.S" {"fp_suffix":"d","i_suffix":"q","max_const":"$0x7fffffffffffffff","result_reg":"%rax","wide":"1"} diff --git a/runtime/interpreter/mterp/x86_64/op_fill_array_data.S b/runtime/interpreter/mterp/x86_64/op_fill_array_data.S deleted file mode 100644 index 7ea36a6136df96bc260ab7c27c1ce5cc5870a93e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_fill_array_data.S +++ /dev/null @@ -1,9 +0,0 @@ - /* fill-array-data vAA, +BBBBBBBB */ - EXPORT_PC - movslq 2(rPC), %rcx # rcx <- ssssssssBBBBbbbb - leaq (rPC,%rcx,2), OUT_ARG1 # OUT_ARG1 <- PC + ssssssssBBBBbbbb*2 - GET_VREG OUT_32_ARG0, rINSTq # OUT_ARG0 <- vAA (array object) - call SYMBOL(MterpFillArrayData) # (obj, payload) - testb %al, %al # 0 means an exception is thrown - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 diff --git a/runtime/interpreter/mterp/x86_64/op_filled_new_array.S b/runtime/interpreter/mterp/x86_64/op_filled_new_array.S deleted file mode 100644 index a7f7ddc2a0da16d320acf1fd95d2d7626442fe63..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_filled_new_array.S +++ /dev/null @@ -1,17 +0,0 @@ -%default { "helper":"MterpFilledNewArray" } -/* - * Create a new array with elements filled from registers. - * - * for: filled-new-array, filled-new-array/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ - .extern $helper - EXPORT_PC - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG0 - movq rPC, OUT_ARG1 - movq rSELF, OUT_ARG2 - call SYMBOL($helper) - testb %al, %al # 0 means an exception is thrown - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 diff --git a/runtime/interpreter/mterp/x86_64/op_filled_new_array_range.S b/runtime/interpreter/mterp/x86_64/op_filled_new_array_range.S deleted file mode 100644 index 4ca79a3fe16c4b370f66553422f0665d30630def..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_filled_new_array_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_filled_new_array.S" { "helper":"MterpFilledNewArrayRange" } diff --git a/runtime/interpreter/mterp/x86_64/op_float_to_double.S b/runtime/interpreter/mterp/x86_64/op_float_to_double.S deleted file mode 100644 index 785520557503fdd89b7bdfc32cd776f00dbbafa1..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_float_to_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/fpcvt.S" {"source_suffix":"s","dest_suffix":"d","wide":"1"} diff --git a/runtime/interpreter/mterp/x86_64/op_float_to_int.S b/runtime/interpreter/mterp/x86_64/op_float_to_int.S deleted file mode 100644 index cb90555405c59354555deee41996573bbf738fa2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_float_to_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/cvtfp_int.S" {"fp_suffix":"s","i_suffix":"l","max_const":"$0x7fffffff","result_reg":"%eax","wide":"0"} diff --git a/runtime/interpreter/mterp/x86_64/op_float_to_long.S b/runtime/interpreter/mterp/x86_64/op_float_to_long.S deleted file mode 100644 index 96bb4eee6f55c257c707b39f75f165d11bb9c861..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_float_to_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/cvtfp_int.S" {"fp_suffix":"s","i_suffix":"q","max_const":"$0x7fffffffffffffff","result_reg":"%rax","wide":"1"} diff --git a/runtime/interpreter/mterp/x86_64/op_goto.S b/runtime/interpreter/mterp/x86_64/op_goto.S deleted file mode 100644 index 9749901f5a7a46d889de27ec1d43c29b151d1378..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_goto.S +++ /dev/null @@ -1,10 +0,0 @@ -/* - * Unconditional branch, 8-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto +AA */ - movsbq rINSTbl, rINSTq # rINSTq <- ssssssAA - testq rINSTq, rINSTq - jmp MterpCommonTakenBranch diff --git a/runtime/interpreter/mterp/x86_64/op_goto_16.S b/runtime/interpreter/mterp/x86_64/op_goto_16.S deleted file mode 100644 index 77688e05e4f66b76154400e870baed07e2d1ebd2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_goto_16.S +++ /dev/null @@ -1,10 +0,0 @@ -/* - * Unconditional branch, 16-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - */ - /* goto/16 +AAAA */ - movswq 2(rPC), rINSTq # rINSTq <- ssssAAAA - testq rINSTq, rINSTq - jmp MterpCommonTakenBranch diff --git a/runtime/interpreter/mterp/x86_64/op_goto_32.S b/runtime/interpreter/mterp/x86_64/op_goto_32.S deleted file mode 100644 index 29d777b5a61e46d6b771d3c0fd4d45f1647d02f9..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_goto_32.S +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Unconditional branch, 32-bit offset. - * - * The branch distance is a signed code-unit offset, which we need to - * double to get a byte offset. - * - * Because we need the SF bit set, we'll use an adds - * to convert from Dalvik offset to byte offset. - */ - /* goto/32 +AAAAAAAA */ - movslq 2(rPC), rINSTq # rINSTq <- AAAAAAAA - testq rINSTq, rINSTq - jmp MterpCommonTakenBranch diff --git a/runtime/interpreter/mterp/x86_64/op_if_eq.S b/runtime/interpreter/mterp/x86_64/op_if_eq.S deleted file mode 100644 index d56ce72461c76894a9d8e9eba5f8c4f3015ae569..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_if_eq.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/bincmp.S" { "revcmp":"ne" } diff --git a/runtime/interpreter/mterp/x86_64/op_if_eqz.S b/runtime/interpreter/mterp/x86_64/op_if_eqz.S deleted file mode 100644 index a0fc4448a3980ebf8497955ed9e7981f123ddebe..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_if_eqz.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/zcmp.S" { "revcmp":"ne" } diff --git a/runtime/interpreter/mterp/x86_64/op_if_ge.S b/runtime/interpreter/mterp/x86_64/op_if_ge.S deleted file mode 100644 index a7832efb68368126366149d82f27fc769158bbf3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_if_ge.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/bincmp.S" { "revcmp":"l" } diff --git a/runtime/interpreter/mterp/x86_64/op_if_gez.S b/runtime/interpreter/mterp/x86_64/op_if_gez.S deleted file mode 100644 index f9af5db933dbf65b4f6fc14971e09d080c6fcc19..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_if_gez.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/zcmp.S" { "revcmp":"l" } diff --git a/runtime/interpreter/mterp/x86_64/op_if_gt.S b/runtime/interpreter/mterp/x86_64/op_if_gt.S deleted file mode 100644 index 70f2b9e12f29ec8c64302ba5318da02333c66a90..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_if_gt.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/bincmp.S" { "revcmp":"le" } diff --git a/runtime/interpreter/mterp/x86_64/op_if_gtz.S b/runtime/interpreter/mterp/x86_64/op_if_gtz.S deleted file mode 100644 index 2fb0d509377a06d45d5b8a3522e98e073938de17..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_if_gtz.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/zcmp.S" { "revcmp":"le" } diff --git a/runtime/interpreter/mterp/x86_64/op_if_le.S b/runtime/interpreter/mterp/x86_64/op_if_le.S deleted file mode 100644 index 321962a040367738c278b2fbd6f0929b4feeaa67..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_if_le.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/bincmp.S" { "revcmp":"g" } diff --git a/runtime/interpreter/mterp/x86_64/op_if_lez.S b/runtime/interpreter/mterp/x86_64/op_if_lez.S deleted file mode 100644 index d3dc334f7bcad1be0a42b630f904dd0bed16b987..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_if_lez.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/zcmp.S" { "revcmp":"g" } diff --git a/runtime/interpreter/mterp/x86_64/op_if_lt.S b/runtime/interpreter/mterp/x86_64/op_if_lt.S deleted file mode 100644 index f028005844911e31c39d413a33736f17953f4895..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_if_lt.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/bincmp.S" { "revcmp":"ge" } diff --git a/runtime/interpreter/mterp/x86_64/op_if_ltz.S b/runtime/interpreter/mterp/x86_64/op_if_ltz.S deleted file mode 100644 index 383d73aa7a70ba35c9dac15644724fc3b92541a6..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_if_ltz.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/zcmp.S" { "revcmp":"ge" } diff --git a/runtime/interpreter/mterp/x86_64/op_if_ne.S b/runtime/interpreter/mterp/x86_64/op_if_ne.S deleted file mode 100644 index ac6e063cd100a41f5cb834f1ecb98fa97cabe5c7..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_if_ne.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/bincmp.S" { "revcmp":"e" } diff --git a/runtime/interpreter/mterp/x86_64/op_if_nez.S b/runtime/interpreter/mterp/x86_64/op_if_nez.S deleted file mode 100644 index c96e4f3d16b878ffb472b750fc8a2032a31dae78..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_if_nez.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/zcmp.S" { "revcmp":"e" } diff --git a/runtime/interpreter/mterp/x86_64/op_iget.S b/runtime/interpreter/mterp/x86_64/op_iget.S deleted file mode 100644 index 4ab7c27c5116ad58e1408ed7c69a7e43b626a8cd..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_iget.S +++ /dev/null @@ -1,2 +0,0 @@ -%default { "is_object":"0", "helper":"MterpIGetU32"} -%include "x86_64/field.S" { } diff --git a/runtime/interpreter/mterp/x86_64/op_iget_boolean.S b/runtime/interpreter/mterp/x86_64/op_iget_boolean.S deleted file mode 100644 index 18e926492623b596dedf9f6f388b2155001d5466..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_iget_boolean.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_iget.S" { "helper":"MterpIGetU8" } diff --git a/runtime/interpreter/mterp/x86_64/op_iget_boolean_quick.S b/runtime/interpreter/mterp/x86_64/op_iget_boolean_quick.S deleted file mode 100644 index 07139c75ee394338f4680c97860af46cb24af45c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_iget_boolean_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_iget_quick.S" { "load":"movsbl" } diff --git a/runtime/interpreter/mterp/x86_64/op_iget_byte.S b/runtime/interpreter/mterp/x86_64/op_iget_byte.S deleted file mode 100644 index bec0ad526c262d2984294ba15733599749e5623a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_iget_byte.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_iget.S" { "helper":"MterpIGetI8" } diff --git a/runtime/interpreter/mterp/x86_64/op_iget_byte_quick.S b/runtime/interpreter/mterp/x86_64/op_iget_byte_quick.S deleted file mode 100644 index 07139c75ee394338f4680c97860af46cb24af45c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_iget_byte_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_iget_quick.S" { "load":"movsbl" } diff --git a/runtime/interpreter/mterp/x86_64/op_iget_char.S b/runtime/interpreter/mterp/x86_64/op_iget_char.S deleted file mode 100644 index 5e22b88129b312c6d0b03a6640ba322a85533c51..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_iget_char.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_iget.S" { "helper":"MterpIGetU16" } diff --git a/runtime/interpreter/mterp/x86_64/op_iget_char_quick.S b/runtime/interpreter/mterp/x86_64/op_iget_char_quick.S deleted file mode 100644 index 8cb3be3b65288583d6b506c6a91c68bc94c4cbc7..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_iget_char_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_iget_quick.S" { "load":"movzwl" } diff --git a/runtime/interpreter/mterp/x86_64/op_iget_object.S b/runtime/interpreter/mterp/x86_64/op_iget_object.S deleted file mode 100644 index bcef1d2c25e94c259fb454cb736c86384425d808..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_iget_object.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_iget.S" { "is_object":"1", "helper":"MterpIGetObj" } diff --git a/runtime/interpreter/mterp/x86_64/op_iget_object_quick.S b/runtime/interpreter/mterp/x86_64/op_iget_object_quick.S deleted file mode 100644 index 176c9544ef7a01f86e5657a69a0f13513125e3c6..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_iget_object_quick.S +++ /dev/null @@ -1,15 +0,0 @@ - /* For: iget-object-quick */ - /* op vA, vB, offset@CCCC */ - .extern artIGetObjectFromMterp - movzbq rINSTbl, %rcx # rcx <- BA - sarl $$4, %ecx # ecx <- B - GET_VREG OUT_32_ARG0, %rcx # vB (object we're operating on) - movzwl 2(rPC), OUT_32_ARG1 # eax <- field byte offset - EXPORT_PC - callq SYMBOL(artIGetObjectFromMterp) # (obj, offset) - movq rSELF, %rcx - cmpq $$0, THREAD_EXCEPTION_OFFSET(%rcx) - jnz MterpException # bail out - andb $$0xf, rINSTbl # rINST <- A - SET_VREG_OBJECT %eax, rINSTq # fp[A] <- value - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_iget_quick.S b/runtime/interpreter/mterp/x86_64/op_iget_quick.S deleted file mode 100644 index bfb7530167678594cb2defbe551aa2d5cbf8a0d2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_iget_quick.S +++ /dev/null @@ -1,18 +0,0 @@ -%default { "load":"movl", "wide":"0"} - /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick, iget-wide-quick */ - /* op vA, vB, offset@CCCC */ - movl rINST, %ecx # rcx <- BA - sarl $$4, %ecx # ecx <- B - GET_VREG %ecx, %rcx # vB (object we're operating on) - movzwq 2(rPC), %rax # eax <- field byte offset - testl %ecx, %ecx # is object null? - je common_errNullObject - andb $$0xf,rINSTbl # rINST <- A - .if $wide - movq (%rcx,%rax,1), %rax - SET_WIDE_VREG %rax, rINSTq # fp[A] <- value - .else - ${load} (%rcx,%rax,1), %eax - SET_VREG %eax, rINSTq # fp[A] <- value - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_iget_short.S b/runtime/interpreter/mterp/x86_64/op_iget_short.S deleted file mode 100644 index 14c49f77114c31664b1384b14675c6060f49bb04..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_iget_short.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_iget.S" { "helper":"MterpIGetI16" } diff --git a/runtime/interpreter/mterp/x86_64/op_iget_short_quick.S b/runtime/interpreter/mterp/x86_64/op_iget_short_quick.S deleted file mode 100644 index 56ca858e74db9c028e724047f83db8469dba57a9..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_iget_short_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_iget_quick.S" { "load":"movswl" } diff --git a/runtime/interpreter/mterp/x86_64/op_iget_wide.S b/runtime/interpreter/mterp/x86_64/op_iget_wide.S deleted file mode 100644 index a85a4748453d60faaa6860f02bf221f338fe3ab8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_iget_wide.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_iget.S" { "helper":"MterpIGetU64" } diff --git a/runtime/interpreter/mterp/x86_64/op_iget_wide_quick.S b/runtime/interpreter/mterp/x86_64/op_iget_wide_quick.S deleted file mode 100644 index 169d625529c7437ea65ac3b927ce81b6c82949d5..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_iget_wide_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_iget_quick.S" { "load":"movswl", "wide":"1" } diff --git a/runtime/interpreter/mterp/x86_64/op_instance_of.S b/runtime/interpreter/mterp/x86_64/op_instance_of.S deleted file mode 100644 index 4819833658906b8f06e4c9e71c78cf85633a40cd..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_instance_of.S +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Check to see if an object reference is an instance of a class. - * - * Most common situation is a non-null object, being compared against - * an already-resolved class. - */ - /* instance-of vA, vB, class@CCCC */ - EXPORT_PC - movzwl 2(rPC), OUT_32_ARG0 # OUT_32_ARG0 <- CCCC - movl rINST, %eax # eax <- BA - sarl $$4, %eax # eax <- B - leaq VREG_ADDRESS(%rax), OUT_ARG1 # Get object address - movq OFF_FP_METHOD(rFP), OUT_ARG2 - movq rSELF, OUT_ARG3 - call SYMBOL(MterpInstanceOf) # (index, &obj, method, self) - movsbl %al, %eax - movq rSELF, %rcx - cmpq $$0, THREAD_EXCEPTION_OFFSET(%rcx) - jnz MterpException - andb $$0xf, rINSTbl # rINSTbl <- A - SET_VREG %eax, rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_int_to_byte.S b/runtime/interpreter/mterp/x86_64/op_int_to_byte.S deleted file mode 100644 index f4e578f868e1046ce40121d461206958e849b3cf..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_int_to_byte.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/unop.S" {"instr":"movsbl %al, %eax"} diff --git a/runtime/interpreter/mterp/x86_64/op_int_to_char.S b/runtime/interpreter/mterp/x86_64/op_int_to_char.S deleted file mode 100644 index c1bf17f271e4685b8075dbea04acc39fdba66770..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_int_to_char.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/unop.S" {"instr":"movzwl %ax,%eax"} diff --git a/runtime/interpreter/mterp/x86_64/op_int_to_double.S b/runtime/interpreter/mterp/x86_64/op_int_to_double.S deleted file mode 100644 index 27ebf42dbb5920ae7f444f830967342aa546a495..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_int_to_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/fpcvt.S" {"source_suffix":"i","dest_suffix":"dl","wide":"1"} diff --git a/runtime/interpreter/mterp/x86_64/op_int_to_float.S b/runtime/interpreter/mterp/x86_64/op_int_to_float.S deleted file mode 100644 index 5a98d44337e9498e31b25f67b09ff1669b2b1c80..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_int_to_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/fpcvt.S" {"source_suffix":"i","dest_suffix":"sl","wide":"0"} diff --git a/runtime/interpreter/mterp/x86_64/op_int_to_long.S b/runtime/interpreter/mterp/x86_64/op_int_to_long.S deleted file mode 100644 index 9281137a546acac0e62f57b0027b26e55c0d6ed7..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_int_to_long.S +++ /dev/null @@ -1,8 +0,0 @@ - /* int to long vA, vB */ - movzbq rINSTbl, %rax # rax <- +A - sarl $$4, %eax # eax <- B - andb $$0xf, rINSTbl # rINST <- A - movslq VREG_ADDRESS(%rax), %rax - SET_WIDE_VREG %rax, rINSTq # v[A] <- %rax - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 - diff --git a/runtime/interpreter/mterp/x86_64/op_int_to_short.S b/runtime/interpreter/mterp/x86_64/op_int_to_short.S deleted file mode 100644 index 6ae6b50f3460dbd7fc1f08d2325c1074686d4fd2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_int_to_short.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/unop.S" {"instr":"movswl %ax, %eax"} diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_custom.S b/runtime/interpreter/mterp/x86_64/op_invoke_custom.S deleted file mode 100644 index f4011f6d86cdd78e2be64b0346da854da3b96bc2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_invoke_custom.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/invoke.S" { "helper":"MterpInvokeCustom" } diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_custom_range.S b/runtime/interpreter/mterp/x86_64/op_invoke_custom_range.S deleted file mode 100644 index 94612c47d58d51773a154cb17db0a8de2b7b40b1..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_invoke_custom_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/invoke.S" { "helper":"MterpInvokeCustomRange" } diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_direct.S b/runtime/interpreter/mterp/x86_64/op_invoke_direct.S deleted file mode 100644 index 9628589b03b777fb321be09e41ac22480ae88522..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_invoke_direct.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/invoke.S" { "helper":"MterpInvokeDirect" } diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_direct_range.S b/runtime/interpreter/mterp/x86_64/op_invoke_direct_range.S deleted file mode 100644 index 09ac8812fcda8f13f3ea20c9e285f54760911418..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_invoke_direct_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/invoke.S" { "helper":"MterpInvokeDirectRange" } diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_interface.S b/runtime/interpreter/mterp/x86_64/op_invoke_interface.S deleted file mode 100644 index 76d9cd426f617b84fd3262ea7bad5c5bf35e061b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_invoke_interface.S +++ /dev/null @@ -1,8 +0,0 @@ -%include "x86_64/invoke.S" { "helper":"MterpInvokeInterface" } -/* - * Handle an interface method call. - * - * for: invoke-interface, invoke-interface/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_interface_range.S b/runtime/interpreter/mterp/x86_64/op_invoke_interface_range.S deleted file mode 100644 index 785b43c1a881c21eb7af1b9b8e550339f0de5c77..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_invoke_interface_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/invoke.S" { "helper":"MterpInvokeInterfaceRange" } diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_polymorphic.S b/runtime/interpreter/mterp/x86_64/op_invoke_polymorphic.S deleted file mode 100644 index 452944536d93fbca29b04de3ad0e674a7a733805..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_invoke_polymorphic.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/invoke_polymorphic.S" { "helper":"MterpInvokePolymorphic" } diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_polymorphic_range.S b/runtime/interpreter/mterp/x86_64/op_invoke_polymorphic_range.S deleted file mode 100644 index 01981c1b49f84c88df4f8ea9955894ff45cfb835..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_invoke_polymorphic_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/invoke_polymorphic.S" { "helper":"MterpInvokePolymorphicRange" } diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_static.S b/runtime/interpreter/mterp/x86_64/op_invoke_static.S deleted file mode 100644 index dd8027d58c5501a594a0c6f429660e0661717585..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_invoke_static.S +++ /dev/null @@ -1,2 +0,0 @@ -%include "x86_64/invoke.S" { "helper":"MterpInvokeStatic" } - diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_static_range.S b/runtime/interpreter/mterp/x86_64/op_invoke_static_range.S deleted file mode 100644 index ee26074f921801d705d60b59c3519f5f7bb6e1cd..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_invoke_static_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/invoke.S" { "helper":"MterpInvokeStaticRange" } diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_super.S b/runtime/interpreter/mterp/x86_64/op_invoke_super.S deleted file mode 100644 index d07f8d555b0fbd34445a219036b60c573e473300..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_invoke_super.S +++ /dev/null @@ -1,8 +0,0 @@ -%include "x86_64/invoke.S" { "helper":"MterpInvokeSuper" } -/* - * Handle a "super" method call. - * - * for: invoke-super, invoke-super/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_super_range.S b/runtime/interpreter/mterp/x86_64/op_invoke_super_range.S deleted file mode 100644 index 7245cfd405c833d74dfe71a3e4c4ac7fdbbcc861..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_invoke_super_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/invoke.S" { "helper":"MterpInvokeSuperRange" } diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_virtual.S b/runtime/interpreter/mterp/x86_64/op_invoke_virtual.S deleted file mode 100644 index 19c708bd2aa7f460c4f0ec9cafeff8f019bee36e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_invoke_virtual.S +++ /dev/null @@ -1,8 +0,0 @@ -%include "x86_64/invoke.S" { "helper":"MterpInvokeVirtual" } -/* - * Handle a virtual method call. - * - * for: invoke-virtual, invoke-virtual/range - */ - /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ - /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_virtual_quick.S b/runtime/interpreter/mterp/x86_64/op_invoke_virtual_quick.S deleted file mode 100644 index 313bd058b1ec69f8dfe818df786e83b105ad8e94..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_invoke_virtual_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/invoke.S" { "helper":"MterpInvokeVirtualQuick" } diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_virtual_range.S b/runtime/interpreter/mterp/x86_64/op_invoke_virtual_range.S deleted file mode 100644 index 424ad321a3524aaaf1259e6dddcad8f9600df8ce..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_invoke_virtual_range.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/invoke.S" { "helper":"MterpInvokeVirtualRange" } diff --git a/runtime/interpreter/mterp/x86_64/op_invoke_virtual_range_quick.S b/runtime/interpreter/mterp/x86_64/op_invoke_virtual_range_quick.S deleted file mode 100644 index 556f718ffbf682b84aa379fb0fe5103268ef84d1..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_invoke_virtual_range_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/invoke.S" { "helper":"MterpInvokeVirtualQuickRange" } diff --git a/runtime/interpreter/mterp/x86_64/op_iput.S b/runtime/interpreter/mterp/x86_64/op_iput.S deleted file mode 100644 index dad5af664b371984b3793ed3712fb2e20e477e4c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_iput.S +++ /dev/null @@ -1,2 +0,0 @@ -%default { "is_object":"0", "helper":"MterpIPutU32" } -%include "x86_64/field.S" { } diff --git a/runtime/interpreter/mterp/x86_64/op_iput_boolean.S b/runtime/interpreter/mterp/x86_64/op_iput_boolean.S deleted file mode 100644 index 06bbd704d7725ce9b99136ae84036230454570a7..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_iput_boolean.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_iput.S" { "helper":"MterpIPutU8" } diff --git a/runtime/interpreter/mterp/x86_64/op_iput_boolean_quick.S b/runtime/interpreter/mterp/x86_64/op_iput_boolean_quick.S deleted file mode 100644 index 6bd060e4f3808dd94515fdf114a66dbfdf6f15ed..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_iput_boolean_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_iput_quick.S" { "reg":"rINSTbl", "store":"movb" } diff --git a/runtime/interpreter/mterp/x86_64/op_iput_byte.S b/runtime/interpreter/mterp/x86_64/op_iput_byte.S deleted file mode 100644 index 53f9008eb55e62811bba0226f42d2ef491681988..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_iput_byte.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_iput.S" { "helper":"MterpIPutI8" } diff --git a/runtime/interpreter/mterp/x86_64/op_iput_byte_quick.S b/runtime/interpreter/mterp/x86_64/op_iput_byte_quick.S deleted file mode 100644 index 6bd060e4f3808dd94515fdf114a66dbfdf6f15ed..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_iput_byte_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_iput_quick.S" { "reg":"rINSTbl", "store":"movb" } diff --git a/runtime/interpreter/mterp/x86_64/op_iput_char.S b/runtime/interpreter/mterp/x86_64/op_iput_char.S deleted file mode 100644 index 4736f5e9d44726921bffd488c227591063fb391f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_iput_char.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_iput.S" { "helper":"MterpIPutU16" } diff --git a/runtime/interpreter/mterp/x86_64/op_iput_char_quick.S b/runtime/interpreter/mterp/x86_64/op_iput_char_quick.S deleted file mode 100644 index 3da96d53afcec7a3948365c9b016ee491912cff2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_iput_char_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_iput_quick.S" { "reg":"rINSTw", "store":"movw" } diff --git a/runtime/interpreter/mterp/x86_64/op_iput_object.S b/runtime/interpreter/mterp/x86_64/op_iput_object.S deleted file mode 100644 index 202e33fa7606ef2689ac55c50297dbfe6185c340..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_iput_object.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_iput.S" { "is_object":"1", "helper":"MterpIPutObj" } diff --git a/runtime/interpreter/mterp/x86_64/op_iput_object_quick.S b/runtime/interpreter/mterp/x86_64/op_iput_object_quick.S deleted file mode 100644 index b5b128ab7fdc83fee0df8ad34805dfeeee0ec1a1..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_iput_object_quick.S +++ /dev/null @@ -1,9 +0,0 @@ - EXPORT_PC - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG0 - movq rPC, OUT_ARG1 - REFRESH_INST ${opnum} - movl rINST, OUT_32_ARG2 - call SYMBOL(MterpIputObjectQuick) - testb %al, %al - jz MterpException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_iput_quick.S b/runtime/interpreter/mterp/x86_64/op_iput_quick.S deleted file mode 100644 index ecaf98e415c69d572b9275cea41a3583186b789f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_iput_quick.S +++ /dev/null @@ -1,13 +0,0 @@ -%default { "reg":"rINST", "store":"movl" } - /* For: iput-quick, iput-object-quick */ - /* op vA, vB, offset@CCCC */ - movzbq rINSTbl, %rcx # rcx <- BA - sarl $$4, %ecx # ecx <- B - GET_VREG %ecx, %rcx # vB (object we're operating on) - testl %ecx, %ecx # is object null? - je common_errNullObject - andb $$0xf, rINSTbl # rINST <- A - GET_VREG rINST, rINSTq # rINST <- v[A] - movzwq 2(rPC), %rax # rax <- field byte offset - ${store} ${reg}, (%rcx,%rax,1) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_iput_short.S b/runtime/interpreter/mterp/x86_64/op_iput_short.S deleted file mode 100644 index dca5735963694550f7f33b788c112457b0b87656..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_iput_short.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_iput.S" { "helper":"MterpIPutI16" } diff --git a/runtime/interpreter/mterp/x86_64/op_iput_short_quick.S b/runtime/interpreter/mterp/x86_64/op_iput_short_quick.S deleted file mode 100644 index 3da96d53afcec7a3948365c9b016ee491912cff2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_iput_short_quick.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_iput_quick.S" { "reg":"rINSTw", "store":"movw" } diff --git a/runtime/interpreter/mterp/x86_64/op_iput_wide.S b/runtime/interpreter/mterp/x86_64/op_iput_wide.S deleted file mode 100644 index db520167d2844e48c4a56569ceda8d9d7c207fcc..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_iput_wide.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_iput.S" { "helper":"MterpIPutU64" } diff --git a/runtime/interpreter/mterp/x86_64/op_iput_wide_quick.S b/runtime/interpreter/mterp/x86_64/op_iput_wide_quick.S deleted file mode 100644 index 473189d007122db21736588cc45c1f0d16e05ac1..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_iput_wide_quick.S +++ /dev/null @@ -1,12 +0,0 @@ - /* iput-wide-quick vA, vB, offset@CCCC */ - movzbq rINSTbl, %rcx # rcx<- BA - sarl $$4, %ecx # ecx<- B - GET_VREG %ecx, %rcx # vB (object we're operating on) - testl %ecx, %ecx # is object null? - je common_errNullObject - movzwq 2(rPC), %rax # rax<- field byte offset - leaq (%rcx,%rax,1), %rcx # ecx<- Address of 64-bit target - andb $$0xf, rINSTbl # rINST<- A - GET_WIDE_VREG %rax, rINSTq # rax<- fp[A]/fp[A+1] - movq %rax, (%rcx) # obj.field<- r0/r1 - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_long_to_double.S b/runtime/interpreter/mterp/x86_64/op_long_to_double.S deleted file mode 100644 index 7cdae32373109d76c50933ecfdbe44c3f215cfb6..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_long_to_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/fpcvt.S" {"source_suffix":"i","dest_suffix":"dq","wide":"1"} diff --git a/runtime/interpreter/mterp/x86_64/op_long_to_float.S b/runtime/interpreter/mterp/x86_64/op_long_to_float.S deleted file mode 100644 index 7553348633db34683e0d4d418155d69c44cd98e4..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_long_to_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/fpcvt.S" {"source_suffix":"i","dest_suffix":"sq","wide":"0"} diff --git a/runtime/interpreter/mterp/x86_64/op_long_to_int.S b/runtime/interpreter/mterp/x86_64/op_long_to_int.S deleted file mode 100644 index 7b50c8e0b357dafee5aab52f1c13a1c8255fb7e9..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_long_to_int.S +++ /dev/null @@ -1,2 +0,0 @@ -/* we ignore the high word, making this equivalent to a 32-bit reg move */ -%include "x86_64/op_move.S" diff --git a/runtime/interpreter/mterp/x86_64/op_monitor_enter.S b/runtime/interpreter/mterp/x86_64/op_monitor_enter.S deleted file mode 100644 index 411091f23e044e12c98bd4ed01a312abed95f40e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_monitor_enter.S +++ /dev/null @@ -1,11 +0,0 @@ -/* - * Synchronize on an object. - */ - /* monitor-enter vAA */ - EXPORT_PC - GET_VREG OUT_32_ARG0, rINSTq - movq rSELF, OUT_ARG1 - call SYMBOL(artLockObjectFromCode) # (object, self) - testq %rax, %rax - jnz MterpException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86_64/op_monitor_exit.S b/runtime/interpreter/mterp/x86_64/op_monitor_exit.S deleted file mode 100644 index 72d9a23a87978fd18153f6420718cdf7a591c4a5..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_monitor_exit.S +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Unlock an object. - * - * Exceptions that occur when unlocking a monitor need to appear as - * if they happened at the following instruction. See the Dalvik - * instruction spec. - */ - /* monitor-exit vAA */ - EXPORT_PC - GET_VREG OUT_32_ARG0, rINSTq - movq rSELF, OUT_ARG1 - call SYMBOL(artUnlockObjectFromCode) # (object, self) - testq %rax, %rax - jnz MterpException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86_64/op_move.S b/runtime/interpreter/mterp/x86_64/op_move.S deleted file mode 100644 index ccaac2caa89db061daf6a30272c393745e0da058..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_move.S +++ /dev/null @@ -1,13 +0,0 @@ -%default { "is_object":"0" } - /* for move, move-object, long-to-int */ - /* op vA, vB */ - movl rINST, %eax # eax <- BA - andb $$0xf, %al # eax <- A - shrl $$4, rINST # rINST <- B - GET_VREG %edx, rINSTq - .if $is_object - SET_VREG_OBJECT %edx, %rax # fp[A] <- fp[B] - .else - SET_VREG %edx, %rax # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86_64/op_move_16.S b/runtime/interpreter/mterp/x86_64/op_move_16.S deleted file mode 100644 index 6a813eb5ce2d8592b7283785537aaa5d365adbfb..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_move_16.S +++ /dev/null @@ -1,12 +0,0 @@ -%default { "is_object":"0" } - /* for: move/16, move-object/16 */ - /* op vAAAA, vBBBB */ - movzwq 4(rPC), %rcx # ecx <- BBBB - movzwq 2(rPC), %rax # eax <- AAAA - GET_VREG %edx, %rcx - .if $is_object - SET_VREG_OBJECT %edx, %rax # fp[A] <- fp[B] - .else - SET_VREG %edx, %rax # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 diff --git a/runtime/interpreter/mterp/x86_64/op_move_exception.S b/runtime/interpreter/mterp/x86_64/op_move_exception.S deleted file mode 100644 index 33db8782362717e9543c66c1b161f2705aba3db2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_move_exception.S +++ /dev/null @@ -1,6 +0,0 @@ - /* move-exception vAA */ - movq rSELF, %rcx - movl THREAD_EXCEPTION_OFFSET(%rcx), %eax - SET_VREG_OBJECT %eax, rINSTq # fp[AA] <- exception object - movl $$0, THREAD_EXCEPTION_OFFSET(%rcx) - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86_64/op_move_from16.S b/runtime/interpreter/mterp/x86_64/op_move_from16.S deleted file mode 100644 index 150e9c2f2c8ef0218f2aaab67ce2249eac9bc9a8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_move_from16.S +++ /dev/null @@ -1,11 +0,0 @@ -%default { "is_object":"0" } - /* for: move/from16, move-object/from16 */ - /* op vAA, vBBBB */ - movzwq 2(rPC), %rax # eax <- BBBB - GET_VREG %edx, %rax # edx <- fp[BBBB] - .if $is_object - SET_VREG_OBJECT %edx, rINSTq # fp[A] <- fp[B] - .else - SET_VREG %edx, rINSTq # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_move_object.S b/runtime/interpreter/mterp/x86_64/op_move_object.S deleted file mode 100644 index 0d866496e8a17f20927019de15a9c2340368ecf8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_move_object.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_move.S" {"is_object":"1"} diff --git a/runtime/interpreter/mterp/x86_64/op_move_object_16.S b/runtime/interpreter/mterp/x86_64/op_move_object_16.S deleted file mode 100644 index 32541ff2bfdfee06ddee388d13bdea5f5a86bbcb..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_move_object_16.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_move_16.S" {"is_object":"1"} diff --git a/runtime/interpreter/mterp/x86_64/op_move_object_from16.S b/runtime/interpreter/mterp/x86_64/op_move_object_from16.S deleted file mode 100644 index 983e4abae5174c2794e494360a983ed27547f928..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_move_object_from16.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_move_from16.S" {"is_object":"1"} diff --git a/runtime/interpreter/mterp/x86_64/op_move_result.S b/runtime/interpreter/mterp/x86_64/op_move_result.S deleted file mode 100644 index 8268344bcedc0ae4996282c86eabc9550f9e6434..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_move_result.S +++ /dev/null @@ -1,11 +0,0 @@ -%default { "is_object":"0" } - /* for: move-result, move-result-object */ - /* op vAA */ - movq OFF_FP_RESULT_REGISTER(rFP), %rax # get pointer to result JType. - movl (%rax), %eax # r0 <- result.i. - .if $is_object - SET_VREG_OBJECT %eax, rINSTq # fp[A] <- fp[B] - .else - SET_VREG %eax, rINSTq # fp[A] <- fp[B] - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86_64/op_move_result_object.S b/runtime/interpreter/mterp/x86_64/op_move_result_object.S deleted file mode 100644 index c5aac17f41594016ab9651d035f1527752319770..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_move_result_object.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_move_result.S" {"is_object":"1"} diff --git a/runtime/interpreter/mterp/x86_64/op_move_result_wide.S b/runtime/interpreter/mterp/x86_64/op_move_result_wide.S deleted file mode 100644 index 03de7836273ef9726837e198647a68300cd19ab8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_move_result_wide.S +++ /dev/null @@ -1,5 +0,0 @@ - /* move-result-wide vAA */ - movq OFF_FP_RESULT_REGISTER(rFP), %rax # get pointer to result JType. - movq (%rax), %rdx # Get wide - SET_WIDE_VREG %rdx, rINSTq # v[AA] <- rdx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86_64/op_move_wide.S b/runtime/interpreter/mterp/x86_64/op_move_wide.S deleted file mode 100644 index 508f8cc1521fcbf2cbd741d3251fa19630f84b86..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_move_wide.S +++ /dev/null @@ -1,8 +0,0 @@ - /* move-wide vA, vB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - movl rINST, %ecx # ecx <- BA - sarl $$4, rINST # rINST <- B - andb $$0xf, %cl # ecx <- A - GET_WIDE_VREG %rdx, rINSTq # rdx <- v[B] - SET_WIDE_VREG %rdx, %rcx # v[A] <- rdx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86_64/op_move_wide_16.S b/runtime/interpreter/mterp/x86_64/op_move_wide_16.S deleted file mode 100644 index ce371a920eccb60fc402492389628f04292f4007..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_move_wide_16.S +++ /dev/null @@ -1,7 +0,0 @@ - /* move-wide/16 vAAAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - movzwq 4(rPC), %rcx # ecx<- BBBB - movzwq 2(rPC), %rax # eax<- AAAA - GET_WIDE_VREG %rdx, %rcx # rdx <- v[B] - SET_WIDE_VREG %rdx, %rax # v[A] <- rdx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 diff --git a/runtime/interpreter/mterp/x86_64/op_move_wide_from16.S b/runtime/interpreter/mterp/x86_64/op_move_wide_from16.S deleted file mode 100644 index 0d6971a674da52e598ec1d507c5cb2b16777fa6c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_move_wide_from16.S +++ /dev/null @@ -1,6 +0,0 @@ - /* move-wide/from16 vAA, vBBBB */ - /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ - movzwl 2(rPC), %ecx # ecx <- BBBB - GET_WIDE_VREG %rdx, %rcx # rdx <- v[B] - SET_WIDE_VREG %rdx, rINSTq # v[A] <- rdx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_mul_double.S b/runtime/interpreter/mterp/x86_64/op_mul_double.S deleted file mode 100644 index 1f4bcb3d00b49c217baff3bc1cf099676a930f19..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_mul_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/sseBinop.S" {"instr":"muls","suff":"d"} diff --git a/runtime/interpreter/mterp/x86_64/op_mul_double_2addr.S b/runtime/interpreter/mterp/x86_64/op_mul_double_2addr.S deleted file mode 100644 index 9850a28995cdbc543e0adac9e418ac61f0be150d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_mul_double_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/sseBinop2Addr.S" {"instr":"muls","suff":"d"} diff --git a/runtime/interpreter/mterp/x86_64/op_mul_float.S b/runtime/interpreter/mterp/x86_64/op_mul_float.S deleted file mode 100644 index 85960e9decbf6a35aeaf0e701447912bc071d455..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_mul_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/sseBinop.S" {"instr":"muls","suff":"s"} diff --git a/runtime/interpreter/mterp/x86_64/op_mul_float_2addr.S b/runtime/interpreter/mterp/x86_64/op_mul_float_2addr.S deleted file mode 100644 index 6d36b6a178554028806dec63876541e5b57dd655..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_mul_float_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/sseBinop2Addr.S" {"instr":"muls","suff":"s"} diff --git a/runtime/interpreter/mterp/x86_64/op_mul_int.S b/runtime/interpreter/mterp/x86_64/op_mul_int.S deleted file mode 100644 index 5f3923a20e7d446322f814a82bfe815823e1fc2f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_mul_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/binop.S" {"instr":"imull (rFP,%rcx,4), %eax"} diff --git a/runtime/interpreter/mterp/x86_64/op_mul_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_mul_int_2addr.S deleted file mode 100644 index 0b5af8a927fd83417ea0e43ae8db6bde28edf80d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_mul_int_2addr.S +++ /dev/null @@ -1,8 +0,0 @@ - /* mul vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $$4, rINST # rINST <- B - andb $$0xf, %cl # ecx <- A - GET_VREG %eax, %rcx # eax <- vA - imull (rFP,rINSTq,4), %eax - SET_VREG %eax, %rcx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86_64/op_mul_int_lit16.S b/runtime/interpreter/mterp/x86_64/op_mul_int_lit16.S deleted file mode 100644 index a4cfdbce3eac0bd6f07f5b12c0893b883cc27f1e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_mul_int_lit16.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/binopLit16.S" {"instr":"imull %ecx, %eax"} diff --git a/runtime/interpreter/mterp/x86_64/op_mul_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_mul_int_lit8.S deleted file mode 100644 index 89e9acb77df807c8f15443d61f1fac4cf34f27ab..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_mul_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/binopLit8.S" {"instr":"imull %ecx, %eax"} diff --git a/runtime/interpreter/mterp/x86_64/op_mul_long.S b/runtime/interpreter/mterp/x86_64/op_mul_long.S deleted file mode 100644 index 2b853705cf42bab73a42c6f4731f9084e399a891..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_mul_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/binopWide.S" {"instr":"imulq (rFP,%rcx,4), %rax"} diff --git a/runtime/interpreter/mterp/x86_64/op_mul_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_mul_long_2addr.S deleted file mode 100644 index 167128b4d180887d6ca457c3063d8ecf592ae5ce..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_mul_long_2addr.S +++ /dev/null @@ -1,8 +0,0 @@ - /* mul vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $$4, rINST # rINST <- B - andb $$0xf, %cl # ecx <- A - GET_WIDE_VREG %rax, %rcx # rax <- vA - imulq (rFP,rINSTq,4), %rax - SET_WIDE_VREG %rax, %rcx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86_64/op_neg_double.S b/runtime/interpreter/mterp/x86_64/op_neg_double.S deleted file mode 100644 index 2c14b091cb38e148fac4431638fc4ea6a6af2627..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_neg_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/unop.S" {"preinstr":" movq $0x8000000000000000, %rsi", "instr":" xorq %rsi, %rax", "wide":"1"} diff --git a/runtime/interpreter/mterp/x86_64/op_neg_float.S b/runtime/interpreter/mterp/x86_64/op_neg_float.S deleted file mode 100644 index 148b21ec9a325a63bf79f8be590ac58fd5c2f9cf..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_neg_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/unop.S" {"instr":" xorl $0x80000000, %eax"} diff --git a/runtime/interpreter/mterp/x86_64/op_neg_int.S b/runtime/interpreter/mterp/x86_64/op_neg_int.S deleted file mode 100644 index f90a937a8b7d784777fcbd859fca4a6514288739..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_neg_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/unop.S" {"instr":" negl %eax"} diff --git a/runtime/interpreter/mterp/x86_64/op_neg_long.S b/runtime/interpreter/mterp/x86_64/op_neg_long.S deleted file mode 100644 index 18fc3ccecef02c6895ddfd81467818dd997f81b2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_neg_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/unop.S" {"instr":" negq %rax", "wide":"1"} diff --git a/runtime/interpreter/mterp/x86_64/op_new_array.S b/runtime/interpreter/mterp/x86_64/op_new_array.S deleted file mode 100644 index 9831a0b8884c87205f2aa341e70b1bb6b5197eae..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_new_array.S +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Allocate an array of objects, specified with the array class - * and a count. - * - * The verifier guarantees that this is an array class, so we don't - * check for it here. - */ - /* new-array vA, vB, class@CCCC */ - EXPORT_PC - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG0 - movq rPC, OUT_ARG1 - REFRESH_INST ${opnum} - movq rINSTq, OUT_ARG2 - movq rSELF, OUT_ARG3 - call SYMBOL(MterpNewArray) - testb %al, %al # 0 means an exception is thrown - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_new_instance.S b/runtime/interpreter/mterp/x86_64/op_new_instance.S deleted file mode 100644 index fc8c8cd98c4cd5c17731f333f00ff1fe71ccb225..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_new_instance.S +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Create a new instance of a class. - */ - /* new-instance vAA, class@BBBB */ - EXPORT_PC - leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG0 - movq rSELF, OUT_ARG1 - REFRESH_INST ${opnum} - movq rINSTq, OUT_ARG2 - call SYMBOL(MterpNewInstance) - testb %al, %al # 0 means an exception is thrown - jz MterpPossibleException - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_nop.S b/runtime/interpreter/mterp/x86_64/op_nop.S deleted file mode 100644 index 4cb68e392e719513e5e85a72fa4aeb942105536b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_nop.S +++ /dev/null @@ -1 +0,0 @@ - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86_64/op_not_int.S b/runtime/interpreter/mterp/x86_64/op_not_int.S deleted file mode 100644 index 463d080de96da8e08188110e5b1e1fac4fa3a453..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_not_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/unop.S" {"instr":" notl %eax"} diff --git a/runtime/interpreter/mterp/x86_64/op_not_long.S b/runtime/interpreter/mterp/x86_64/op_not_long.S deleted file mode 100644 index c97bb9ea1aebab74f3c33ef176818919b77f5c04..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_not_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/unop.S" {"instr":" notq %rax", "wide":"1"} diff --git a/runtime/interpreter/mterp/x86_64/op_or_int.S b/runtime/interpreter/mterp/x86_64/op_or_int.S deleted file mode 100644 index 730310f6afa7e0f6074db8648170aafd09b628f6..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_or_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/binop.S" {"instr":"orl (rFP,%rcx,4), %eax"} diff --git a/runtime/interpreter/mterp/x86_64/op_or_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_or_int_2addr.S deleted file mode 100644 index f722e4dd9c6b095ba2e3d422404e67d25c904df0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_or_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/binop2addr.S" {"instr":"orl %eax, (rFP,%rcx,4)"} diff --git a/runtime/interpreter/mterp/x86_64/op_or_int_lit16.S b/runtime/interpreter/mterp/x86_64/op_or_int_lit16.S deleted file mode 100644 index fee86c7c62d5810c22a60545765e9603c7188c98..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_or_int_lit16.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/binopLit16.S" {"instr":"orl %ecx, %eax"} diff --git a/runtime/interpreter/mterp/x86_64/op_or_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_or_int_lit8.S deleted file mode 100644 index 81104c7e56a65eedc8668c38c9682b0c575fc3bf..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_or_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/binopLit8.S" {"instr":"orl %ecx, %eax"} diff --git a/runtime/interpreter/mterp/x86_64/op_or_long.S b/runtime/interpreter/mterp/x86_64/op_or_long.S deleted file mode 100644 index 6c70a2001ee10dd6f2e4ac4fa57f30a9fed0e3b2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_or_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/binopWide.S" {"instr":"orq (rFP,%rcx,4), %rax"} diff --git a/runtime/interpreter/mterp/x86_64/op_or_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_or_long_2addr.S deleted file mode 100644 index 546da1de2d02b5b8a99f3059e6323bc029df52f0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_or_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/binopWide2addr.S" {"instr":"orq %rax, (rFP,%rcx,4)"} diff --git a/runtime/interpreter/mterp/x86_64/op_packed_switch.S b/runtime/interpreter/mterp/x86_64/op_packed_switch.S deleted file mode 100644 index 148552f77eb661da25e977a55e88522d25176635..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_packed_switch.S +++ /dev/null @@ -1,18 +0,0 @@ -%default { "func":"MterpDoPackedSwitch" } -/* - * Handle a packed-switch or sparse-switch instruction. In both cases - * we decode it and hand it off to a helper function. - * - * We don't really expect backward branches in a switch statement, but - * they're perfectly legal, so we check for them here. - * - * for: packed-switch, sparse-switch - */ - /* op vAA, +BBBB */ - movslq 2(rPC), OUT_ARG0 # rcx <- ssssssssBBBBbbbb - leaq (rPC,OUT_ARG0,2), OUT_ARG0 # rcx <- PC + ssssssssBBBBbbbb*2 - GET_VREG OUT_32_ARG1, rINSTq # eax <- vAA - call SYMBOL($func) - testl %eax, %eax - movslq %eax, rINSTq - jmp MterpCommonTakenBranch diff --git a/runtime/interpreter/mterp/x86_64/op_rem_double.S b/runtime/interpreter/mterp/x86_64/op_rem_double.S deleted file mode 100644 index 00aed787cb33d9ea21e9c5536a9860b4ec9a547c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_rem_double.S +++ /dev/null @@ -1,14 +0,0 @@ - /* rem_double vAA, vBB, vCC */ - movzbq 3(rPC), %rcx # ecx <- BB - movzbq 2(rPC), %rax # eax <- CC - fldl VREG_ADDRESS(%rcx) # %st1 <- fp[vBB] - fldl VREG_ADDRESS(%rax) # %st0 <- fp[vCC] -1: - fprem - fstsw %ax - sahf - jp 1b - fstp %st(1) - fstpl VREG_ADDRESS(rINSTq) # fp[vAA] <- %st - CLEAR_WIDE_REF rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_rem_double_2addr.S b/runtime/interpreter/mterp/x86_64/op_rem_double_2addr.S deleted file mode 100644 index 9768266e211c6b6546dcb0f633c2dd7fe4b134e0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_rem_double_2addr.S +++ /dev/null @@ -1,15 +0,0 @@ - /* rem_double/2addr vA, vB */ - movzbq rINSTbl, %rcx # ecx <- A+ - sarl $$4, rINST # rINST <- B - fldl VREG_ADDRESS(rINSTq) # vB to fp stack - andb $$0xf, %cl # ecx <- A - fldl VREG_ADDRESS(%rcx) # vA to fp stack -1: - fprem - fstsw %ax - sahf - jp 1b - fstp %st(1) - fstpl VREG_ADDRESS(%rcx) # %st to vA - CLEAR_WIDE_REF %rcx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86_64/op_rem_float.S b/runtime/interpreter/mterp/x86_64/op_rem_float.S deleted file mode 100644 index 5af28accec3261409af74d1affe2fc398953a7c1..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_rem_float.S +++ /dev/null @@ -1,14 +0,0 @@ - /* rem_float vAA, vBB, vCC */ - movzbq 3(rPC), %rcx # ecx <- BB - movzbq 2(rPC), %rax # eax <- CC - flds VREG_ADDRESS(%rcx) # vBB to fp stack - flds VREG_ADDRESS(%rax) # vCC to fp stack -1: - fprem - fstsw %ax - sahf - jp 1b - fstp %st(1) - fstps VREG_ADDRESS(rINSTq) # %st to vAA - CLEAR_REF rINSTq - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/op_rem_float_2addr.S b/runtime/interpreter/mterp/x86_64/op_rem_float_2addr.S deleted file mode 100644 index e9282a8de95d9d587fa2777dbaae1460a23630d4..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_rem_float_2addr.S +++ /dev/null @@ -1,15 +0,0 @@ - /* rem_float/2addr vA, vB */ - movzbq rINSTbl, %rcx # ecx <- A+ - sarl $$4, rINST # rINST <- B - flds VREG_ADDRESS(rINSTq) # vB to fp stack - andb $$0xf, %cl # ecx <- A - flds VREG_ADDRESS(%rcx) # vA to fp stack -1: - fprem - fstsw %ax - sahf - jp 1b - fstp %st(1) - fstps VREG_ADDRESS(%rcx) # %st to vA - CLEAR_REF %rcx - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86_64/op_rem_int.S b/runtime/interpreter/mterp/x86_64/op_rem_int.S deleted file mode 100644 index fd77d7cdfe229554c1ea9b10758363ca27283b78..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_rem_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/bindiv.S" {"result":"%edx","second":"%ecx","wide":"0","suffix":"l","rem":"1"} diff --git a/runtime/interpreter/mterp/x86_64/op_rem_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_rem_int_2addr.S deleted file mode 100644 index 25ffbf713bdd750367a95832d5a145f004c66d05..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_rem_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/bindiv2addr.S" {"result":"%edx","second":"%ecx","wide":"0","suffix":"l","rem":"1"} diff --git a/runtime/interpreter/mterp/x86_64/op_rem_int_lit16.S b/runtime/interpreter/mterp/x86_64/op_rem_int_lit16.S deleted file mode 100644 index 21cc37087d64e7cb91b3213351edf36d80719f12..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_rem_int_lit16.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/bindivLit16.S" {"result":"%edx","rem":"1"} diff --git a/runtime/interpreter/mterp/x86_64/op_rem_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_rem_int_lit8.S deleted file mode 100644 index 2eb0150f63091614c9b386bea2bd241026bfb13b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_rem_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/bindivLit8.S" {"result":"%edx","rem":"1"} diff --git a/runtime/interpreter/mterp/x86_64/op_rem_long.S b/runtime/interpreter/mterp/x86_64/op_rem_long.S deleted file mode 100644 index efa721520dd415a14cc89f0ddc867db18aae4716..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_rem_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/bindiv.S" {"result":"%rdx","second":"%rcx","wide":"1","suffix":"q","ext":"cqo","rem":"1"} diff --git a/runtime/interpreter/mterp/x86_64/op_rem_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_rem_long_2addr.S deleted file mode 100644 index ce0dd86539c98efdf07c06d569172c59371833a6..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_rem_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/bindiv2addr.S" {"result":"%rdx","second":"%rcx","wide":"1","suffix":"q","rem":"1","ext":"cqo"} diff --git a/runtime/interpreter/mterp/x86_64/op_return.S b/runtime/interpreter/mterp/x86_64/op_return.S deleted file mode 100644 index 8cb6cbaee1e6aea53f04335f99c9510372431818..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_return.S +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Return a 32-bit value. - * - * for: return, return-object - */ - /* op vAA */ - .extern MterpThreadFenceForConstructor - call SYMBOL(MterpThreadFenceForConstructor) - movq rSELF, OUT_ARG0 - testl $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(OUT_ARG0) - jz 1f - call SYMBOL(MterpSuspendCheck) -1: - GET_VREG %eax, rINSTq # eax <- vAA - jmp MterpReturn diff --git a/runtime/interpreter/mterp/x86_64/op_return_object.S b/runtime/interpreter/mterp/x86_64/op_return_object.S deleted file mode 100644 index 1ae69a501c4e6db5621262f68d690bba0379882b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_return_object.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_return.S" diff --git a/runtime/interpreter/mterp/x86_64/op_return_void.S b/runtime/interpreter/mterp/x86_64/op_return_void.S deleted file mode 100644 index ba68e7e444a7dacde768db846b21c6f3fc3ae834..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_return_void.S +++ /dev/null @@ -1,9 +0,0 @@ - .extern MterpThreadFenceForConstructor - call SYMBOL(MterpThreadFenceForConstructor) - movq rSELF, OUT_ARG0 - testl $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(OUT_ARG0) - jz 1f - call SYMBOL(MterpSuspendCheck) -1: - xorq %rax, %rax - jmp MterpReturn diff --git a/runtime/interpreter/mterp/x86_64/op_return_void_no_barrier.S b/runtime/interpreter/mterp/x86_64/op_return_void_no_barrier.S deleted file mode 100644 index 6799da1dbd3701c6ca4fc740332ea8fc253fa693..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_return_void_no_barrier.S +++ /dev/null @@ -1,7 +0,0 @@ - movq rSELF, OUT_ARG0 - testl $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(OUT_ARG0) - jz 1f - call SYMBOL(MterpSuspendCheck) -1: - xorq %rax, %rax - jmp MterpReturn diff --git a/runtime/interpreter/mterp/x86_64/op_return_wide.S b/runtime/interpreter/mterp/x86_64/op_return_wide.S deleted file mode 100644 index d6d6d1bf5e835e5496cc863f206b5af3c2785e90..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_return_wide.S +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Return a 64-bit value. - */ - /* return-wide vAA */ - .extern MterpThreadFenceForConstructor - call SYMBOL(MterpThreadFenceForConstructor) - movq rSELF, OUT_ARG0 - testl $$(THREAD_SUSPEND_OR_CHECKPOINT_REQUEST), THREAD_FLAGS_OFFSET(OUT_ARG0) - jz 1f - call SYMBOL(MterpSuspendCheck) -1: - GET_WIDE_VREG %rax, rINSTq # eax <- v[AA] - jmp MterpReturn diff --git a/runtime/interpreter/mterp/x86_64/op_rsub_int.S b/runtime/interpreter/mterp/x86_64/op_rsub_int.S deleted file mode 100644 index 2dd20026df95c6c4486b610495fea0f146365625..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_rsub_int.S +++ /dev/null @@ -1,2 +0,0 @@ -/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ -%include "x86_64/binopLit16.S" {"instr":"subl %eax, %ecx","result":"%ecx"} diff --git a/runtime/interpreter/mterp/x86_64/op_rsub_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_rsub_int_lit8.S deleted file mode 100644 index 64d0d8a704fedd32bd4ce99bb9c2589d01fed04d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_rsub_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/binopLit8.S" {"instr":"subl %eax, %ecx" , "result":"%ecx"} diff --git a/runtime/interpreter/mterp/x86_64/op_sget.S b/runtime/interpreter/mterp/x86_64/op_sget.S deleted file mode 100644 index 21e8e64b8bfa514aef7cb19bcfbc24504b64296b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_sget.S +++ /dev/null @@ -1,2 +0,0 @@ -%default { "is_object":"0", "helper":"MterpSGetU32" } -%include "x86_64/field.S" { } diff --git a/runtime/interpreter/mterp/x86_64/op_sget_boolean.S b/runtime/interpreter/mterp/x86_64/op_sget_boolean.S deleted file mode 100644 index e5a4e41995cab58bfcd2c154f3c37160cebda6ea..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_sget_boolean.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_sget.S" {"helper":"MterpSGetU8"} diff --git a/runtime/interpreter/mterp/x86_64/op_sget_byte.S b/runtime/interpreter/mterp/x86_64/op_sget_byte.S deleted file mode 100644 index 4602f7da5357415660d35b3cd2009d844dba160c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_sget_byte.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_sget.S" {"helper":"MterpSGetI8"} diff --git a/runtime/interpreter/mterp/x86_64/op_sget_char.S b/runtime/interpreter/mterp/x86_64/op_sget_char.S deleted file mode 100644 index a094a542de6beb354f6c20833fae6632541049b9..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_sget_char.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_sget.S" {"helper":"MterpSGetU16"} diff --git a/runtime/interpreter/mterp/x86_64/op_sget_object.S b/runtime/interpreter/mterp/x86_64/op_sget_object.S deleted file mode 100644 index 94597b187cc8c70138d764e4c4218cbcb0786e47..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_sget_object.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_sget.S" {"is_object":"1", "helper":"MterpSGetObj"} diff --git a/runtime/interpreter/mterp/x86_64/op_sget_short.S b/runtime/interpreter/mterp/x86_64/op_sget_short.S deleted file mode 100644 index dee5c247b9818a78c2cff82584c07023b841badc..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_sget_short.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_sget.S" {"helper":"MterpSGetI16"} diff --git a/runtime/interpreter/mterp/x86_64/op_sget_wide.S b/runtime/interpreter/mterp/x86_64/op_sget_wide.S deleted file mode 100644 index c53c0773a5f718580c9cf6e4059d503e02ee85df..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_sget_wide.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_sget.S" {"helper":"MterpSGetU64"} diff --git a/runtime/interpreter/mterp/x86_64/op_shl_int.S b/runtime/interpreter/mterp/x86_64/op_shl_int.S deleted file mode 100644 index fa1edb7555f01219fbb8b1523f2b7ebe1d261f68..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_shl_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/binop1.S" {"instr":"sall %cl, %eax"} diff --git a/runtime/interpreter/mterp/x86_64/op_shl_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_shl_int_2addr.S deleted file mode 100644 index dd962792c9f0b71c785905bbd1ece29a054a09c8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_shl_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/shop2addr.S" {"instr":"sall %cl, %eax"} diff --git a/runtime/interpreter/mterp/x86_64/op_shl_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_shl_int_lit8.S deleted file mode 100644 index 39b23ae1fb4e531c7cd377e973271831e962aa4b..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_shl_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/binopLit8.S" {"instr":"sall %cl, %eax"} diff --git a/runtime/interpreter/mterp/x86_64/op_shl_long.S b/runtime/interpreter/mterp/x86_64/op_shl_long.S deleted file mode 100644 index fdc7cb64de5c6a5d16176ac2d261ffef2c5ec1cc..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_shl_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/binop1.S" {"instr":"salq %cl, %rax","wide":"1"} diff --git a/runtime/interpreter/mterp/x86_64/op_shl_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_shl_long_2addr.S deleted file mode 100644 index 546633f7d591219d9c3b63e22ff6811b8e45f121..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_shl_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/shop2addr.S" {"instr":"salq %cl, %rax","wide":"1"} diff --git a/runtime/interpreter/mterp/x86_64/op_shr_int.S b/runtime/interpreter/mterp/x86_64/op_shr_int.S deleted file mode 100644 index fc289f4638c9c352eed0180ed4d7386ad0b6726e..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_shr_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/binop1.S" {"instr":"sarl %cl, %eax"} diff --git a/runtime/interpreter/mterp/x86_64/op_shr_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_shr_int_2addr.S deleted file mode 100644 index 0e5bca7057e800f24a6c55c02d35dd41a3234623..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_shr_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/shop2addr.S" {"instr":"sarl %cl, %eax"} diff --git a/runtime/interpreter/mterp/x86_64/op_shr_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_shr_int_lit8.S deleted file mode 100644 index 3cc930756979cb562683e0c10a14374ad3151b79..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_shr_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/binopLit8.S" {"instr":"sarl %cl, %eax"} diff --git a/runtime/interpreter/mterp/x86_64/op_shr_long.S b/runtime/interpreter/mterp/x86_64/op_shr_long.S deleted file mode 100644 index 25028d3560f4c617eb047a138b12e9a3959a7e39..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_shr_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/binop1.S" {"instr":"sarq %cl, %rax","wide":"1"} diff --git a/runtime/interpreter/mterp/x86_64/op_shr_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_shr_long_2addr.S deleted file mode 100644 index 373841322dfdeca26abb79ef81bd667e8ea30653..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_shr_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/shop2addr.S" {"instr":"sarq %cl, %rax","wide":"1"} diff --git a/runtime/interpreter/mterp/x86_64/op_sparse_switch.S b/runtime/interpreter/mterp/x86_64/op_sparse_switch.S deleted file mode 100644 index 0eaa5148135db6d92cddda70bf7c87380795c262..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_sparse_switch.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_packed_switch.S" { "func":"MterpDoSparseSwitch" } diff --git a/runtime/interpreter/mterp/x86_64/op_sput.S b/runtime/interpreter/mterp/x86_64/op_sput.S deleted file mode 100644 index 7dd24985ffd529e425991ea4caf095fcedbec280..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_sput.S +++ /dev/null @@ -1,2 +0,0 @@ -%default { "is_object":"0", "helper":"MterpSPutU32"} -%include "x86_64/field.S" { } diff --git a/runtime/interpreter/mterp/x86_64/op_sput_boolean.S b/runtime/interpreter/mterp/x86_64/op_sput_boolean.S deleted file mode 100644 index ea9acbfdc72fce142960cad7cce1b4c596465a55..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_sput_boolean.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_sput.S" {"helper":"MterpSPutU8"} diff --git a/runtime/interpreter/mterp/x86_64/op_sput_byte.S b/runtime/interpreter/mterp/x86_64/op_sput_byte.S deleted file mode 100644 index 62c9e205a1437a7fd4928bd5eb1b9e49e047b7d8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_sput_byte.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_sput.S" {"helper":"MterpSPutI8"} diff --git a/runtime/interpreter/mterp/x86_64/op_sput_char.S b/runtime/interpreter/mterp/x86_64/op_sput_char.S deleted file mode 100644 index ab0196e027169a5a4bb347843557e002ca614b33..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_sput_char.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_sput.S" {"helper":"MterpSPutU16"} diff --git a/runtime/interpreter/mterp/x86_64/op_sput_object.S b/runtime/interpreter/mterp/x86_64/op_sput_object.S deleted file mode 100644 index c2bd07bcc89c2ba012e693e6ea366757f45699da..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_sput_object.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_sput.S" {"is_object":"1", "helper":"MterpSPutObj"} diff --git a/runtime/interpreter/mterp/x86_64/op_sput_short.S b/runtime/interpreter/mterp/x86_64/op_sput_short.S deleted file mode 100644 index f73a3fc69ee39d50091171921b7dee579990c6c4..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_sput_short.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_sput.S" {"helper":"MterpSPutI16"} diff --git a/runtime/interpreter/mterp/x86_64/op_sput_wide.S b/runtime/interpreter/mterp/x86_64/op_sput_wide.S deleted file mode 100644 index 7e77072dce8362ef207e89a3d0ac808c170c0f35..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_sput_wide.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/op_sput.S" {"helper":"MterpSPutU64"} diff --git a/runtime/interpreter/mterp/x86_64/op_sub_double.S b/runtime/interpreter/mterp/x86_64/op_sub_double.S deleted file mode 100644 index 952667e831e0235f73ef71afcb943be3546d8276..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_sub_double.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/sseBinop.S" {"instr":"subs","suff":"d"} diff --git a/runtime/interpreter/mterp/x86_64/op_sub_double_2addr.S b/runtime/interpreter/mterp/x86_64/op_sub_double_2addr.S deleted file mode 100644 index 0bd5dbb8ff0543d2ad8b469ca70bcfa561afea45..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_sub_double_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/sseBinop2Addr.S" {"instr":"subs","suff":"d"} diff --git a/runtime/interpreter/mterp/x86_64/op_sub_float.S b/runtime/interpreter/mterp/x86_64/op_sub_float.S deleted file mode 100644 index ea0ae14f5b1fb3b2b44d76351d12f9f424717980..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_sub_float.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/sseBinop.S" {"instr":"subs","suff":"s"} diff --git a/runtime/interpreter/mterp/x86_64/op_sub_float_2addr.S b/runtime/interpreter/mterp/x86_64/op_sub_float_2addr.S deleted file mode 100644 index 9dd17805c809b11f33f555534191939e3a3413c3..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_sub_float_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/sseBinop2Addr.S" {"instr":"subs","suff":"s"} diff --git a/runtime/interpreter/mterp/x86_64/op_sub_int.S b/runtime/interpreter/mterp/x86_64/op_sub_int.S deleted file mode 100644 index 560394f43f0d9b020c5238510db4e74d87e67cf6..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_sub_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/binop.S" {"instr":"subl (rFP,%rcx,4), %eax"} diff --git a/runtime/interpreter/mterp/x86_64/op_sub_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_sub_int_2addr.S deleted file mode 100644 index 6f50f78f41465da7a0ff4da814db8c1f6bf6c198..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_sub_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/binop2addr.S" {"instr":"subl %eax, (rFP,%rcx,4)"} diff --git a/runtime/interpreter/mterp/x86_64/op_sub_long.S b/runtime/interpreter/mterp/x86_64/op_sub_long.S deleted file mode 100644 index 7fa54e7a11662b549eff85839385e2e3f7e88ef9..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_sub_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/binopWide.S" {"instr":"subq (rFP,%rcx,4), %rax"} diff --git a/runtime/interpreter/mterp/x86_64/op_sub_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_sub_long_2addr.S deleted file mode 100644 index c18be10919af0f7349a5251b609ed329aeefdb0d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_sub_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/binopWide2addr.S" {"instr":"subq %rax, (rFP,%rcx,4)"} diff --git a/runtime/interpreter/mterp/x86_64/op_throw.S b/runtime/interpreter/mterp/x86_64/op_throw.S deleted file mode 100644 index 8095c25b0825b7140005d81d97a0510a7fabb42c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_throw.S +++ /dev/null @@ -1,11 +0,0 @@ -/* - * Throw an exception object in the current thread. - */ - /* throw vAA */ - EXPORT_PC - GET_VREG %eax, rINSTq # eax<- vAA (exception object) - testb %al, %al - jz common_errNullObject - movq rSELF, %rcx - movq %rax, THREAD_EXCEPTION_OFFSET(%rcx) - jmp MterpException diff --git a/runtime/interpreter/mterp/x86_64/op_unused_3e.S b/runtime/interpreter/mterp/x86_64/op_unused_3e.S deleted file mode 100644 index 280615f08b124bd9c513704501c49895504edcd0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_unused_3e.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/unused.S" diff --git a/runtime/interpreter/mterp/x86_64/op_unused_3f.S b/runtime/interpreter/mterp/x86_64/op_unused_3f.S deleted file mode 100644 index 280615f08b124bd9c513704501c49895504edcd0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_unused_3f.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/unused.S" diff --git a/runtime/interpreter/mterp/x86_64/op_unused_40.S b/runtime/interpreter/mterp/x86_64/op_unused_40.S deleted file mode 100644 index 280615f08b124bd9c513704501c49895504edcd0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_unused_40.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/unused.S" diff --git a/runtime/interpreter/mterp/x86_64/op_unused_41.S b/runtime/interpreter/mterp/x86_64/op_unused_41.S deleted file mode 100644 index 280615f08b124bd9c513704501c49895504edcd0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_unused_41.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/unused.S" diff --git a/runtime/interpreter/mterp/x86_64/op_unused_42.S b/runtime/interpreter/mterp/x86_64/op_unused_42.S deleted file mode 100644 index 280615f08b124bd9c513704501c49895504edcd0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_unused_42.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/unused.S" diff --git a/runtime/interpreter/mterp/x86_64/op_unused_43.S b/runtime/interpreter/mterp/x86_64/op_unused_43.S deleted file mode 100644 index 280615f08b124bd9c513704501c49895504edcd0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_unused_43.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/unused.S" diff --git a/runtime/interpreter/mterp/x86_64/op_unused_79.S b/runtime/interpreter/mterp/x86_64/op_unused_79.S deleted file mode 100644 index 280615f08b124bd9c513704501c49895504edcd0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_unused_79.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/unused.S" diff --git a/runtime/interpreter/mterp/x86_64/op_unused_7a.S b/runtime/interpreter/mterp/x86_64/op_unused_7a.S deleted file mode 100644 index 280615f08b124bd9c513704501c49895504edcd0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_unused_7a.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/unused.S" diff --git a/runtime/interpreter/mterp/x86_64/op_unused_f3.S b/runtime/interpreter/mterp/x86_64/op_unused_f3.S deleted file mode 100644 index 280615f08b124bd9c513704501c49895504edcd0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_unused_f3.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/unused.S" diff --git a/runtime/interpreter/mterp/x86_64/op_unused_f4.S b/runtime/interpreter/mterp/x86_64/op_unused_f4.S deleted file mode 100644 index 280615f08b124bd9c513704501c49895504edcd0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_unused_f4.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/unused.S" diff --git a/runtime/interpreter/mterp/x86_64/op_unused_f5.S b/runtime/interpreter/mterp/x86_64/op_unused_f5.S deleted file mode 100644 index 280615f08b124bd9c513704501c49895504edcd0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_unused_f5.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/unused.S" diff --git a/runtime/interpreter/mterp/x86_64/op_unused_f6.S b/runtime/interpreter/mterp/x86_64/op_unused_f6.S deleted file mode 100644 index 280615f08b124bd9c513704501c49895504edcd0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_unused_f6.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/unused.S" diff --git a/runtime/interpreter/mterp/x86_64/op_unused_f7.S b/runtime/interpreter/mterp/x86_64/op_unused_f7.S deleted file mode 100644 index 280615f08b124bd9c513704501c49895504edcd0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_unused_f7.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/unused.S" diff --git a/runtime/interpreter/mterp/x86_64/op_unused_f8.S b/runtime/interpreter/mterp/x86_64/op_unused_f8.S deleted file mode 100644 index 280615f08b124bd9c513704501c49895504edcd0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_unused_f8.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/unused.S" diff --git a/runtime/interpreter/mterp/x86_64/op_unused_f9.S b/runtime/interpreter/mterp/x86_64/op_unused_f9.S deleted file mode 100644 index 280615f08b124bd9c513704501c49895504edcd0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_unused_f9.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/unused.S" diff --git a/runtime/interpreter/mterp/x86_64/op_unused_fc.S b/runtime/interpreter/mterp/x86_64/op_unused_fc.S deleted file mode 100644 index 280615f08b124bd9c513704501c49895504edcd0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_unused_fc.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/unused.S" diff --git a/runtime/interpreter/mterp/x86_64/op_unused_fd.S b/runtime/interpreter/mterp/x86_64/op_unused_fd.S deleted file mode 100644 index 280615f08b124bd9c513704501c49895504edcd0..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_unused_fd.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/unused.S" diff --git a/runtime/interpreter/mterp/x86_64/op_ushr_int.S b/runtime/interpreter/mterp/x86_64/op_ushr_int.S deleted file mode 100644 index dd91086371e241d76d6a7957af630ee348211b84..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_ushr_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/binop1.S" {"instr":"shrl %cl, %eax"} diff --git a/runtime/interpreter/mterp/x86_64/op_ushr_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_ushr_int_2addr.S deleted file mode 100644 index d38aedd234bb0da0300b60c4f183fc39cb373bad..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_ushr_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/shop2addr.S" {"instr":"shrl %cl, %eax"} diff --git a/runtime/interpreter/mterp/x86_64/op_ushr_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_ushr_int_lit8.S deleted file mode 100644 index f7ff8abc869bc0a6721da5ef0e87b15ca92c582c..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_ushr_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/binopLit8.S" {"instr":"shrl %cl, %eax"} diff --git a/runtime/interpreter/mterp/x86_64/op_ushr_long.S b/runtime/interpreter/mterp/x86_64/op_ushr_long.S deleted file mode 100644 index 7c6daca05d4f92a2b1a49b6b31b1b002f6ff65e2..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_ushr_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/binop1.S" {"instr":"shrq %cl, %rax","wide":"1"} diff --git a/runtime/interpreter/mterp/x86_64/op_ushr_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_ushr_long_2addr.S deleted file mode 100644 index cd6a22c6fa398d2f8f7e11a8a0509e73dd2df111..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_ushr_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/shop2addr.S" {"instr":"shrq %cl, %rax","wide":"1"} diff --git a/runtime/interpreter/mterp/x86_64/op_xor_int.S b/runtime/interpreter/mterp/x86_64/op_xor_int.S deleted file mode 100644 index b295d74de0cc53821f02f187f3c9b832b6b20d63..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_xor_int.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/binop.S" {"instr":"xorl (rFP,%rcx,4), %eax"} diff --git a/runtime/interpreter/mterp/x86_64/op_xor_int_2addr.S b/runtime/interpreter/mterp/x86_64/op_xor_int_2addr.S deleted file mode 100644 index 879bfc05dc87b24ee77d81865c867ec3272a45ad..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_xor_int_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/binop2addr.S" {"instr":"xorl %eax, (rFP,%rcx,4)"} diff --git a/runtime/interpreter/mterp/x86_64/op_xor_int_lit16.S b/runtime/interpreter/mterp/x86_64/op_xor_int_lit16.S deleted file mode 100644 index 5d375a1cf69ce01aed1f823e27bd37d0a3b75b04..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_xor_int_lit16.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/binopLit16.S" {"instr":"xorl %ecx, %eax"} diff --git a/runtime/interpreter/mterp/x86_64/op_xor_int_lit8.S b/runtime/interpreter/mterp/x86_64/op_xor_int_lit8.S deleted file mode 100644 index 54cce9c18e36677f1dadd87d6538269c775274c8..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_xor_int_lit8.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/binopLit8.S" {"instr":"xorl %ecx, %eax"} diff --git a/runtime/interpreter/mterp/x86_64/op_xor_long.S b/runtime/interpreter/mterp/x86_64/op_xor_long.S deleted file mode 100644 index 52b44e29c113337b0522f92f536ce5d35c7ce5d4..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_xor_long.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/binopWide.S" {"instr":"xorq (rFP,%rcx,4), %rax"} diff --git a/runtime/interpreter/mterp/x86_64/op_xor_long_2addr.S b/runtime/interpreter/mterp/x86_64/op_xor_long_2addr.S deleted file mode 100644 index d75c4ba6ce95e9024edfcbe8e82f8acc9719131f..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/op_xor_long_2addr.S +++ /dev/null @@ -1 +0,0 @@ -%include "x86_64/binopWide2addr.S" {"instr":"xorq %rax, (rFP,%rcx,4)"} diff --git a/runtime/interpreter/mterp/x86_64/other.S b/runtime/interpreter/mterp/x86_64/other.S new file mode 100644 index 0000000000000000000000000000000000000000..849155ca8f5cb05cc410c0808484a32d5f989c79 --- /dev/null +++ b/runtime/interpreter/mterp/x86_64/other.S @@ -0,0 +1,287 @@ +%def const(helper="UndefinedConstHandler"): + /* const/class vAA, type@BBBB */ + /* const/method-handle vAA, method_handle@BBBB */ + /* const/method-type vAA, proto@BBBB */ + /* const/string vAA, string@@BBBB */ + .extern $helper + EXPORT_PC + movzwq 2(rPC), OUT_ARG0 # eax <- OUT_ARG0 + movq rINSTq, OUT_ARG1 + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 + movq rSELF, OUT_ARG3 + call SYMBOL($helper) # (index, tgt_reg, shadow_frame, self) + testb %al, %al + jnz MterpPossibleException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def unused(): +/* + * Bail to reference interpreter to throw. + */ + jmp MterpFallback + +%def op_const(): + /* const vAA, #+BBBBbbbb */ + movl 2(rPC), %eax # grab all 32 bits at once + SET_VREG %eax, rINSTq # vAA<- eax + ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 + +%def op_const_16(): + /* const/16 vAA, #+BBBB */ + movswl 2(rPC), %ecx # ecx <- ssssBBBB + SET_VREG %ecx, rINSTq # vAA <- ssssBBBB + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_const_4(): + /* const/4 vA, #+B */ + movsbl rINSTbl, %eax # eax <-ssssssBx + movl $$0xf, rINST + andl %eax, rINST # rINST <- A + sarl $$4, %eax + SET_VREG %eax, rINSTq + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_const_class(): +% const(helper="MterpConstClass") + +%def op_const_high16(): + /* const/high16 vAA, #+BBBB0000 */ + movzwl 2(rPC), %eax # eax <- 0000BBBB + sall $$16, %eax # eax <- BBBB0000 + SET_VREG %eax, rINSTq # vAA <- eax + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_const_method_handle(): +% const(helper="MterpConstMethodHandle") + +%def op_const_method_type(): +% const(helper="MterpConstMethodType") + +%def op_const_string(): +% const(helper="MterpConstString") + +%def op_const_string_jumbo(): + /* const/string vAA, String@BBBBBBBB */ + EXPORT_PC + movl 2(rPC), OUT_32_ARG0 # OUT_32_ARG0 <- BBBB + movq rINSTq, OUT_ARG1 + leaq OFF_FP_SHADOWFRAME(rFP), OUT_ARG2 + movq rSELF, OUT_ARG3 + call SYMBOL(MterpConstString) # (index, tgt_reg, shadow_frame, self) + testb %al, %al + jnz MterpPossibleException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 + +%def op_const_wide(): + /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ + movq 2(rPC), %rax # rax <- HHHHhhhhBBBBbbbb + SET_WIDE_VREG %rax, rINSTq + ADVANCE_PC_FETCH_AND_GOTO_NEXT 5 + +%def op_const_wide_16(): + /* const-wide/16 vAA, #+BBBB */ + movswq 2(rPC), %rax # rax <- ssssBBBB + SET_WIDE_VREG %rax, rINSTq # store + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_const_wide_32(): + /* const-wide/32 vAA, #+BBBBbbbb */ + movslq 2(rPC), %rax # eax <- ssssssssBBBBbbbb + SET_WIDE_VREG %rax, rINSTq # store + ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 + +%def op_const_wide_high16(): + /* const-wide/high16 vAA, #+BBBB000000000000 */ + movzwq 2(rPC), %rax # eax <- 0000BBBB + salq $$48, %rax # eax <- BBBB0000 + SET_WIDE_VREG %rax, rINSTq # v[AA+0] <- eax + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_monitor_enter(): +/* + * Synchronize on an object. + */ + /* monitor-enter vAA */ + EXPORT_PC + GET_VREG OUT_32_ARG0, rINSTq + movq rSELF, OUT_ARG1 + call SYMBOL(artLockObjectFromCode) # (object, self) + testq %rax, %rax + jnz MterpException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_monitor_exit(): +/* + * Unlock an object. + * + * Exceptions that occur when unlocking a monitor need to appear as + * if they happened at the following instruction. See the Dalvik + * instruction spec. + */ + /* monitor-exit vAA */ + EXPORT_PC + GET_VREG OUT_32_ARG0, rINSTq + movq rSELF, OUT_ARG1 + call SYMBOL(artUnlockObjectFromCode) # (object, self) + testq %rax, %rax + jnz MterpException + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_move(is_object="0"): + /* for move, move-object, long-to-int */ + /* op vA, vB */ + movl rINST, %eax # eax <- BA + andb $$0xf, %al # eax <- A + shrl $$4, rINST # rINST <- B + GET_VREG %edx, rINSTq + .if $is_object + SET_VREG_OBJECT %edx, %rax # fp[A] <- fp[B] + .else + SET_VREG %edx, %rax # fp[A] <- fp[B] + .endif + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_move_16(is_object="0"): + /* for: move/16, move-object/16 */ + /* op vAAAA, vBBBB */ + movzwq 4(rPC), %rcx # ecx <- BBBB + movzwq 2(rPC), %rax # eax <- AAAA + GET_VREG %edx, %rcx + .if $is_object + SET_VREG_OBJECT %edx, %rax # fp[A] <- fp[B] + .else + SET_VREG %edx, %rax # fp[A] <- fp[B] + .endif + ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 + +%def op_move_exception(): + /* move-exception vAA */ + movq rSELF, %rcx + movl THREAD_EXCEPTION_OFFSET(%rcx), %eax + SET_VREG_OBJECT %eax, rINSTq # fp[AA] <- exception object + movl $$0, THREAD_EXCEPTION_OFFSET(%rcx) + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_move_from16(is_object="0"): + /* for: move/from16, move-object/from16 */ + /* op vAA, vBBBB */ + movzwq 2(rPC), %rax # eax <- BBBB + GET_VREG %edx, %rax # edx <- fp[BBBB] + .if $is_object + SET_VREG_OBJECT %edx, rINSTq # fp[A] <- fp[B] + .else + SET_VREG %edx, rINSTq # fp[A] <- fp[B] + .endif + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_move_object(): +% op_move(is_object="1") + +%def op_move_object_16(): +% op_move_16(is_object="1") + +%def op_move_object_from16(): +% op_move_from16(is_object="1") + +%def op_move_result(is_object="0"): + /* for: move-result, move-result-object */ + /* op vAA */ + movq OFF_FP_RESULT_REGISTER(rFP), %rax # get pointer to result JType. + movl (%rax), %eax # r0 <- result.i. + .if $is_object + SET_VREG_OBJECT %eax, rINSTq # fp[A] <- fp[B] + .else + SET_VREG %eax, rINSTq # fp[A] <- fp[B] + .endif + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_move_result_object(): +% op_move_result(is_object="1") + +%def op_move_result_wide(): + /* move-result-wide vAA */ + movq OFF_FP_RESULT_REGISTER(rFP), %rax # get pointer to result JType. + movq (%rax), %rdx # Get wide + SET_WIDE_VREG %rdx, rINSTq # v[AA] <- rdx + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_move_wide(): + /* move-wide vA, vB */ + /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ + movl rINST, %ecx # ecx <- BA + sarl $$4, rINST # rINST <- B + andb $$0xf, %cl # ecx <- A + GET_WIDE_VREG %rdx, rINSTq # rdx <- v[B] + SET_WIDE_VREG %rdx, %rcx # v[A] <- rdx + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_move_wide_16(): + /* move-wide/16 vAAAA, vBBBB */ + /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ + movzwq 4(rPC), %rcx # ecx<- BBBB + movzwq 2(rPC), %rax # eax<- AAAA + GET_WIDE_VREG %rdx, %rcx # rdx <- v[B] + SET_WIDE_VREG %rdx, %rax # v[A] <- rdx + ADVANCE_PC_FETCH_AND_GOTO_NEXT 3 + +%def op_move_wide_from16(): + /* move-wide/from16 vAA, vBBBB */ + /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ + movzwl 2(rPC), %ecx # ecx <- BBBB + GET_WIDE_VREG %rdx, %rcx # rdx <- v[B] + SET_WIDE_VREG %rdx, rINSTq # v[A] <- rdx + ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 + +%def op_nop(): + ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 + +%def op_unused_3e(): +% unused() + +%def op_unused_3f(): +% unused() + +%def op_unused_40(): +% unused() + +%def op_unused_41(): +% unused() + +%def op_unused_42(): +% unused() + +%def op_unused_43(): +% unused() + +%def op_unused_79(): +% unused() + +%def op_unused_7a(): +% unused() + +%def op_unused_f3(): +% unused() + +%def op_unused_f4(): +% unused() + +%def op_unused_f5(): +% unused() + +%def op_unused_f6(): +% unused() + +%def op_unused_f7(): +% unused() + +%def op_unused_f8(): +% unused() + +%def op_unused_f9(): +% unused() + +%def op_unused_fc(): +% unused() + +%def op_unused_fd(): +% unused() diff --git a/runtime/interpreter/mterp/x86_64/shop2addr.S b/runtime/interpreter/mterp/x86_64/shop2addr.S deleted file mode 100644 index 6b06d002fc99c3e1cc441507185ad5934b0f9aaa..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/shop2addr.S +++ /dev/null @@ -1,19 +0,0 @@ -%default {"wide":"0"} -/* - * Generic 32-bit "shift/2addr" operation. - */ - /* shift/2addr vA, vB */ - movl rINST, %ecx # ecx <- BA - sarl $$4, %ecx # ecx <- B - GET_VREG %ecx, %rcx # ecx <- vBB - andb $$0xf, rINSTbl # rINST <- A - .if $wide - GET_WIDE_VREG %rax, rINSTq # rax <- vAA - $instr # ex: sarl %cl, %eax - SET_WIDE_VREG %rax, rINSTq - .else - GET_VREG %eax, rINSTq # eax <- vAA - $instr # ex: sarl %cl, %eax - SET_VREG %eax, rINSTq - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86_64/sseBinop.S b/runtime/interpreter/mterp/x86_64/sseBinop.S deleted file mode 100644 index 09d3364de76631a7c8920436e4a1c69580cc794a..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/sseBinop.S +++ /dev/null @@ -1,9 +0,0 @@ -%default {"instr":"","suff":""} - movzbq 2(rPC), %rcx # ecx <- BB - movzbq 3(rPC), %rax # eax <- CC - movs${suff} VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src - ${instr}${suff} VREG_ADDRESS(%rax), %xmm0 - movs${suff} %xmm0, VREG_ADDRESS(rINSTq) # vAA <- %xmm0 - pxor %xmm0, %xmm0 - movs${suff} %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2 diff --git a/runtime/interpreter/mterp/x86_64/sseBinop2Addr.S b/runtime/interpreter/mterp/x86_64/sseBinop2Addr.S deleted file mode 100644 index 084166b95d1dde1ed4e31eb0005bda49aa6b465d..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/sseBinop2Addr.S +++ /dev/null @@ -1,10 +0,0 @@ -%default {"instr":"","suff":""} - movl rINST, %ecx # ecx <- A+ - andl $$0xf, %ecx # ecx <- A - movs${suff} VREG_ADDRESS(%rcx), %xmm0 # %xmm0 <- 1st src - sarl $$4, rINST # rINST<- B - ${instr}${suff} VREG_ADDRESS(rINSTq), %xmm0 - movs${suff} %xmm0, VREG_ADDRESS(%rcx) # vAA<- %xmm0 - pxor %xmm0, %xmm0 - movs${suff} %xmm0, VREG_REF_ADDRESS(rINSTq) # clear ref - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86_64/unop.S b/runtime/interpreter/mterp/x86_64/unop.S deleted file mode 100644 index 1777123f3603a51dea8635c43b3e435618ae4672..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/unop.S +++ /dev/null @@ -1,22 +0,0 @@ -%default {"preinstr":"", "instr":"", "wide":"0"} -/* - * Generic 32/64-bit unary operation. Provide an "instr" line that - * specifies an instruction that performs "result = op eax". - */ - /* unop vA, vB */ - movl rINST, %ecx # rcx <- A+ - sarl $$4,rINST # rINST <- B - .if ${wide} - GET_WIDE_VREG %rax, rINSTq # rax <- vB - .else - GET_VREG %eax, rINSTq # eax <- vB - .endif - andb $$0xf,%cl # ecx <- A -$preinstr -$instr - .if ${wide} - SET_WIDE_VREG %rax, %rcx - .else - SET_VREG %eax, %rcx - .endif - ADVANCE_PC_FETCH_AND_GOTO_NEXT 1 diff --git a/runtime/interpreter/mterp/x86_64/unused.S b/runtime/interpreter/mterp/x86_64/unused.S deleted file mode 100644 index c95ef947d3c4187addee86d70f601836922c05c4..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/unused.S +++ /dev/null @@ -1,4 +0,0 @@ -/* - * Bail to reference interpreter to throw. - */ - jmp MterpFallback diff --git a/runtime/interpreter/mterp/x86_64/zcmp.S b/runtime/interpreter/mterp/x86_64/zcmp.S deleted file mode 100644 index fb8ae6af6ef554835f09aa3a29398490a320c2d9..0000000000000000000000000000000000000000 --- a/runtime/interpreter/mterp/x86_64/zcmp.S +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Generic one-operand compare-and-branch operation. Provide a "revcmp" - * fragment that specifies the *reverse* comparison to perform, e.g. - * for "if-le" you would use "gt". - * - * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez - */ - /* if-cmp vAA, +BBBB */ - cmpl $$0, VREG_ADDRESS(rINSTq) # compare (vA, 0) - j${revcmp} 1f - movswq 2(rPC), rINSTq # fetch signed displacement - testq rINSTq, rINSTq - jmp MterpCommonTakenBranch -1: - cmpl $$JIT_CHECK_OSR, rPROFILE - je .L_check_not_taken_osr - ADVANCE_PC_FETCH_AND_GOTO_NEXT 2