From d520a9486c628940b7530bc32973ba0c76934898 Mon Sep 17 00:00:00 2001
From: Patrick Daly <pdaly@codeaurora.org>
Date: Mon, 27 Feb 2017 16:55:09 -0800
Subject: [PATCH] lrdpv2: Correct caching of virt->physical translations
Cache translations for pages rather than by exact address. This shows
a large improvement in efficiency for some specific cases:
Before:
[9/33] --dmesg ... 18.810140s
[23/33] --print-rtb ... 78.879237s
[26/33] --print-tasks ... 29.115214s
After:
[9/33] --dmesg ... 0.952276s
[23/33] --print-rtb ... 7.542078s
[26/33] --print-tasks ... 4.092283s
Change-Id: I1268928e2f1f0493b9047497a0f91b86ad83a296
---
linux-ramdump-parser-v2/mmu.py | 17 +++++++++++------
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/linux-ramdump-parser-v2/mmu.py b/linux-ramdump-parser-v2/mmu.py
index 4444cd2..0d395a6 100644
--- a/linux-ramdump-parser-v2/mmu.py
+++ b/linux-ramdump-parser-v2/mmu.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
+# Copyright (c) 2013-2017, The Linux Foundation. All rights reserved.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License version 2 and
@@ -51,16 +51,21 @@ class MMU(object):
if addr is None:
return None
+ page_addr = (addr >> 12) << 12
+ page_offset = addr & 0xFFF
+
if not skip_tlb:
- if addr in self._tlb:
- return self._tlb[addr]
+ if page_addr in self._tlb:
+ return self._tlb[page_addr] + page_offset
- phys_addr = self.page_table_walk(addr)
+ phys_addr = self.page_table_walk(page_addr)
+ if phys_addr is None:
+ return None
if save_in_tlb:
- self._tlb[addr] = phys_addr
+ self._tlb[page_addr] = phys_addr
- return phys_addr
+ return phys_addr + page_offset
def load_page_tables(self):
raise NotImplementedError
--
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