diff --git a/linux-ramdump-parser-v2/iommulib.py b/linux-ramdump-parser-v2/iommulib.py index 612473466ecb2462e0e764400e44e66423a80793..edfbe3c1fba5b220de5f7c2013311916587e89a0 100644 --- a/linux-ramdump-parser-v2/iommulib.py +++ b/linux-ramdump-parser-v2/iommulib.py @@ -14,11 +14,12 @@ import linux_list as llist ARM_SMMU_DOMAIN = 0 MSM_SMMU_DOMAIN = 1 +MSM_SMMU_AARCH64_DOMAIN = 2 class Domain(object): def __init__(self, pg_table, redirect, ctx_list, client_name, - domain_type=MSM_SMMU_DOMAIN, level=4, domain_num=-1): + domain_type=MSM_SMMU_DOMAIN, level=3, domain_num=-1): self.domain_num = domain_num self.pg_table = pg_table self.redirect = redirect @@ -131,8 +132,13 @@ class IommuLib(object): redirect = self.ramdump.read_u64( priv_ptr + priv_pt_offset + redirect_offset) - domain_create = Domain(pg_table, redirect, [], - client_name) + if (self.ramdump.is_config_defined('CONFIG_IOMMU_AARCH64')): + domain_create = Domain(pg_table, redirect, [], client_name, + MSM_SMMU_AARCH64_DOMAIN) + else: + domain_create = Domain(pg_table, redirect, [], client_name, + MSM_SMMU_DOMAIN) + domain_list.append(domain_create) def _iommu_list_func(self, node, ctx_list): @@ -215,6 +221,11 @@ class IommuLib(object): 'attached_elm')) list_walker.walk(list_attached, self._iommu_list_func, ctx_list) - domain_list.append( - Domain(pg_table, redirect, ctx_list, client_name, - domain_num=domain_num)) + if (self.ramdump.is_config_defined('CONFIG_IOMMU_AARCH64')): + domain_create = Domain(pg_table, redirect, ctx_list, client_name, + MSM_SMMU_AARCH64_DOMAIN, domain_num=domain_num) + else: + domain_create = Domain(pg_table, redirect, ctx_list, client_name, + MSM_SMMU_DOMAIN, domain_num=domain_num) + + domain_list.append(domain_create) diff --git a/linux-ramdump-parser-v2/parsers/iommu.py b/linux-ramdump-parser-v2/parsers/iommu.py index 8a36681f1903c69b32674c4960305db0f2347036..5a8146c7ce9d086314ed3626624ab40680f0f6c1 100644 --- a/linux-ramdump-parser-v2/parsers/iommu.py +++ b/linux-ramdump-parser-v2/parsers/iommu.py @@ -14,7 +14,7 @@ import math from print_out import print_out_str from parser_util import register_parser, RamParser from sizes import SZ_4K, SZ_64K, SZ_1M, SZ_16M, get_order, order_size_strings -from iommulib import IommuLib, MSM_SMMU_DOMAIN +from iommulib import IommuLib, MSM_SMMU_DOMAIN, MSM_SMMU_AARCH64_DOMAIN, ARM_SMMU_DOMAIN from lpaeiommulib import parse_long_form_tables from aarch64iommulib import parse_aarch64_tables @@ -345,11 +345,8 @@ class IOMMU(RamParser): for (domain_num, d) in enumerate(self.domain_list): if self.ramdump.is_config_defined('CONFIG_IOMMU_LPAE'): parse_long_form_tables(self.ramdump, d, domain_num) - elif (self.ramdump.is_config_defined('CONFIG_IOMMU_AARCH64') or - self.ramdump.is_config_defined('CONFIG_ARM_SMMU')): - if (d.domain_type == MSM_SMMU_DOMAIN): - self.parse_short_form_tables(d, domain_num) - else: - parse_aarch64_tables(self.ramdump, d, domain_num) - else: + elif (d.domain_type == MSM_SMMU_DOMAIN): self.parse_short_form_tables(d, domain_num) + elif ((d.domain_type == ARM_SMMU_DOMAIN) or + (d.domain_type == MSM_SMMU_AARCH64_DOMAIN)): + parse_aarch64_tables(self.ramdump, d, domain_num)