diff --git a/linux-ramdump-parser-v2/cachedumplib.py b/linux-ramdump-parser-v2/cachedumplib.py
old mode 100755
new mode 100644
index 28714d8c4fac76066e8010fbe782d826f2564252..62b0fea050341880612677e5b8f2cfceb5c24708
--- a/linux-ramdump-parser-v2/cachedumplib.py
+++ b/linux-ramdump-parser-v2/cachedumplib.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+# Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License version 2 and
@@ -431,9 +431,165 @@ class L1_ICache_KRYO2XX_GOLD(CacheDumpType_v1):
output.append(n)
output.append(addr)
+class L1_DCache_KRYO3XX_SILVER(CacheDumpType_v1):
+ """Refer to documentation:ad003_atrm"""
+ def __init__(self):
+ super(L1_DCache_KRYO3XX_SILVER, self).__init__()
+ self.tableformat.addColumn('MESI')
+ self.tableformat.addColumn('Tag Address [39:12]')
+ self.tableformat.addColumn('NS')
+ self.tableformat.addColumn('Outer Allocation Hint')
+ self.unsupported_header_offset = 0
+ self.TagSize = 2
+ self.LineSize = 16
+ self.NumSets = 0x80
+ self.NumWays = 4
+
+ def MESI_to_string(MESI_d):
+ if MESI_d == 0:
+ return 'I'
+ elif MESI_d == 1:
+ return 'S'
+ elif MESI_d == 2:
+ return 'E'
+ else:
+ return 'M'
+
+ def parse_tag_fn(self, output, data, nset, nway):
+ if self.TagSize != 2:
+ raise Exception('cache tag size mismatch')
+
+ MESI_d = (data[1] >> 30) & 0x3
+ addr = (data[1] >> 1) & 0xfffffff
+ ns = (data[1] >> 29) & 0x1
+ alloc_hint = data[0] & 0x1
+
+ mesi = self.MESI_to_string(MESI_d)
+ output.append(mesi)
+ output.append(addr)
+ output.append(ns)
+ output.append(alloc_hint)
+
+class L1_ICache_KRYO3XX_SILVER(CacheDumpType_v1):
+ """Refer to documentation:ad003_atrm"""
+ def __init__(self):
+ super(L1_ICache_KRYO3XX_SILVER, self).__init__()
+ self.tableformat.addColumn('Valid and set mode')
+ self.tableformat.addColumn('NS')
+ self.tableformat.addColumn('Tag address')
+ self.unsupported_header_offset = 0
+ self.TagSize = 2
+ self.LineSize = 16
+ self.NumSets = 0x80
+ self.NumWays = 4
+
+ def valid_to_string(valid_d):
+ if valid_d == 0:
+ return 'A32'
+ elif valid_d == 1:
+ return 'T32'
+ elif valid_d == 2:
+ return 'A64'
+ else:
+ return 'Invalid'
+
+ def parse_tag_fn(self, output, data, nset, nway):
+ if self.TagSize != 2:
+ raise Exception('cache tag size mismatch')
+
+ valid_d = (data[0] >> 29) & 0x3
+ ns = (data[0] >> 28) & 0x1
+ addr = data[0] & 0xfffffff
+
+ set_mode = self.valid_to_string(valid_d)
+ output.append(set_mode)
+ output.append(ns)
+ output.append(addr)
+
+class L1_DCache_KRYO3XX_GOLD(CacheDumpType_v1):
+ """Refer to documentation:ad003_atrm"""
+ def __init__(self):
+ super(L1_DCache_KRYO3XX_GOLD, self).__init__()
+ self.tableformat.addColumn('PA [43:12]')
+ self.tableformat.addColumn('MESI')
+ self.unsupported_header_offset = 0
+ self.TagSize = 3
+ self.LineSize = 16
+ self.NumSets = 0x40
+ self.NumWays = 16
+
+ def MESI_to_string(MESI_d):
+ if MESI_d == 0:
+ return 'I'
+ elif MESI_d == 1:
+ return 'S'
+ elif MESI_d == 2:
+ return 'E'
+ else:
+ return 'M'
+
+ def parse_tag_fn(self, output, data, nset, nway):
+ if self.TagSize != 3:
+ raise Exception('cache tag size mismatch')
+
+ addr_lower = (data[0] >> 10) & 0x3fffff
+ addr_higher = data[1] & 0x3ff
+ mesi_d = (data[0] >> 2) & 0x3
+
+ addr = (addr_higher << 22) | addr_lower
+ mesi = MESI_to_string(mesi_d)
+ output.append(addr)
+ output.append(mesi)
+
+
+class L1_ICache_KRYO3XX_GOLD(CacheDumpType_v1):
+ """Refer to documentation:ad003_atrm"""
+ def __init__(self):
+ super(L1_ICache_KRYO3XX_GOLD, self).__init__()
+ self.tableformat.addColumn('Valid and set mode')
+ self.tableformat.addColumn('NS')
+ self.tableformat.addColumn('Tag address')
+ self.unsupported_header_offset = 0
+ self.TagSize = 2
+ self.LineSize = 16
+ self.NumSets = 0x100
+ self.NumWays = 4
+
+ def parse_tag_fn(self, output, data, nset, nway):
+ if self.TagSize != 2:
+ raise Exception('cache tag size mismatch')
+
+ valid = (data[0] >> 29) & 0x1
+ ns = (data[0] >> 28) & 0x1
+ addr = data[0] & 0xfffffff
+
+ output.append(valid)
+ output.append(ns)
+ output.append(addr)
+
L1_DCache_KRYO2XX_SILVER = L1_DCache_A53
L1_ICache_KYRO2XX_SILVER = L1_ICache_A53
+# "sdm845"
+lookuptable[("sdm845", 0x80, 0x14)] = L1_DCache_KRYO3XX_SILVER()
+lookuptable[("sdm845", 0x81, 0x14)] = L1_DCache_KRYO3XX_SILVER()
+lookuptable[("sdm845", 0x82, 0x14)] = L1_DCache_KRYO3XX_SILVER()
+lookuptable[("sdm845", 0x83, 0x14)] = L1_DCache_KRYO3XX_SILVER()
+lookuptable[("sdm845", 0x84, 0x14)] = L1_DCache_KRYO3XX_GOLD()
+lookuptable[("sdm845", 0x85, 0x14)] = L1_DCache_KRYO3XX_GOLD()
+lookuptable[("sdm845", 0x86, 0x14)] = L1_DCache_KRYO3XX_GOLD()
+lookuptable[("sdm845", 0x87, 0x14)] = L1_DCache_KRYO3XX_GOLD()
+
+
+lookuptable[("sdm845", 0x60, 0x14)] = L1_ICache_KRYO3XX_SILVER()
+lookuptable[("sdm845", 0x61, 0x14)] = L1_ICache_KRYO3XX_SILVER()
+lookuptable[("sdm845", 0x62, 0x14)] = L1_ICache_KRYO3XX_SILVER()
+lookuptable[("sdm845", 0x63, 0x14)] = L1_ICache_KRYO3XX_SILVER()
+lookuptable[("sdm845", 0x64, 0x14)] = L1_ICache_KRYO3XX_GOLD()
+lookuptable[("sdm845", 0x65, 0x14)] = L1_ICache_KRYO3XX_GOLD()
+lookuptable[("sdm845", 0x66, 0x14)] = L1_ICache_KRYO3XX_GOLD()
+lookuptable[("sdm845", 0x67, 0x14)] = L1_ICache_KRYO3XX_GOLD()
+
# "msmcobalt"
lookuptable[("cobalt", 0x80, 0x14)] = L1_DCache_KRYO2XX_SILVER()
lookuptable[("cobalt", 0x81, 0x14)] = L1_DCache_KRYO2XX_SILVER()